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port_map_tpu.hpp
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#pragma once
//=========================================================================//
/*! @file
@brief RX66N/RX72N/RX72M グループ・ポート・マッピング (TPU) @n
・TPU 型に従って、タイマー用ポートを設定 @n
TPU0, TPU1, TPU2, TPU3, TPU4, TPU5
@author 平松邦仁 ([email protected])
@copyright Copyright (C) 2021, 2024 Kunihito Hiramatsu @n
Released under the MIT license @n
https://github.com/hirakuni45/RX/blob/master/LICENSE
*/
//=========================================================================//
#if defined(SIG_RX66N)
#include "RX66N/peripheral.hpp"
#include "RX66N/port.hpp"
#include "RX66N/mpc.hpp"
#elif defined(SIG_RX72N)
#include "RX72N/peripheral.hpp"
#include "RX72N/port.hpp"
#include "RX72N/mpc.hpp"
#elif defined(SIG_RX72M)
#include "RX72M/peripheral.hpp"
#include "RX72N/port.hpp"
#include "RX72M/mpc.hpp"
#endif
#include "RX600/port_map_order.hpp"
namespace device {
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++//
/*!
@brief ポート・マッピング・ユーティリティー
*/
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++//
class port_map_tpu : public port_map_order {
static bool tpu0_(CHANNEL ch, bool ena, ORDER odr) noexcept
{
bool ret = true;
uint8_t sel = ena ? 0b00'0011 : 0;
switch(ch) {
case CHANNEL::A:
/// TIOCA0 (入出力)
/// 224 176 144 100
/// P86 o o o x
/// PA0 o o o o
switch(odr) {
case ORDER::FIRST:
PORT8::PMR.B6 = 0;
MPC::P86PFS.PSEL = sel;
PORT8::PMR.B6 = ena;
break;
case ORDER::SECOND:
PORTA::PMR.B0 = 0;
MPC::PA0PFS.PSEL = sel;
PORTA::PMR.B0 = ena;
break;
default:
ret = false;
break;
}
break;
case CHANNEL::B:
/// TIOCB0 (入出力)
/// 224 176 144 100
/// P17 o o o o
/// PA1 o o o o
switch(odr) {
case ORDER::FIRST:
PORT1::PMR.B7 = 0;
MPC::P17PFS.PSEL = sel;
PORT1::PMR.B7 = ena;
break;
case ORDER::SECOND:
PORTA::PMR.B1 = 0;
MPC::PA1PFS.PSEL = sel;
PORTA::PMR.B1 = ena;
break;
default:
ret = false;
break;
}
break;
case CHANNEL::C:
/// TIOCC0 (入出力)
/// 224 176 144 100
/// P32 o o o o
/// P85 o o x x
switch(odr) {
case ORDER::FIRST:
PORT3::PMR.B2 = 0;
MPC::P32PFS.PSEL = sel;
PORT3::PMR.B2 = ena;
break;
case ORDER::SECOND:
PORT8::PMR.B5 = 0;
MPC::P85PFS.PSEL = sel;
PORT8::PMR.B5 = ena;
break;
default:
ret = false;
break;
}
break;
case CHANNEL::D:
/// TIOCD0 (入出力)
/// 224 176 144 100
/// P33 o o o o
/// PA3 o o o o
switch(odr) {
case ORDER::FIRST:
PORT3::PMR.B3 = 0;
MPC::P33PFS.PSEL = sel;
PORT3::PMR.B3 = ena;
break;
case ORDER::SECOND:
PORTA::PMR.B3 = 0;
MPC::PA3PFS.PSEL = sel;
PORTA::PMR.B3 = ena;
break;
default:
ret = false;
break;
}
break;
default:
ret = false;
break;
}
return ret;
}
static bool tpu1_(CHANNEL ch, bool ena, ORDER odr) noexcept
{
bool ret = true;
uint8_t sel = ena ? 0b00'0011 : 0;
switch(ch) {
case CHANNEL::A:
/// TIOCA1 (入出力)
/// 224 176 144 100
/// P56 o o o x
/// PA4 o o o o
switch(odr) {
case ORDER::FIRST:
PORT5::PMR.B6 = 0;
MPC::P56PFS.PSEL = sel;
PORT5::PMR.B6 = ena;
break;
case ORDER::SECOND:
PORTA::PMR.B4 = 0;
MPC::PA4PFS.PSEL = sel;
PORTA::PMR.B4 = ena;
break;
default:
ret = false;
break;
}
break;
case CHANNEL::B:
/// TIOCB1 (入出力)
/// 224 176 144 100
/// P16 o o o o
/// PA5 o o o o
switch(odr) {
case ORDER::FIRST:
PORT1::PMR.B6 = 0;
MPC::P16PFS.PSEL = sel;
PORT1::PMR.B6 = ena;
break;
case ORDER::SECOND:
PORTA::PMR.B5 = 0;
MPC::PA5PFS.PSEL = sel;
PORTA::PMR.B5 = ena;
break;
default:
ret = false;
break;
}
break;
default:
ret = false;
break;
}
return ret;
}
static bool tpu2_(CHANNEL ch, bool ena, ORDER odr) noexcept
{
bool ret = true;
uint8_t sel = ena ? 0b00'0011 : 0;
switch(ch) {
case CHANNEL::A:
/// TIOCA2 (入出力)
/// 224 176 144 100
/// P87 o o o x
/// PA6 o o o o
switch(odr) {
case ORDER::FIRST:
PORT8::PMR.B7 = 0;
MPC::P87PFS.PSEL = sel;
PORT8::PMR.B7 = ena;
break;
case ORDER::SECOND:
PORTA::PMR.B6 = 0;
MPC::PA6PFS.PSEL = sel;
PORTA::PMR.B6 = ena;
break;
default:
ret = false;
break;
}
break;
case CHANNEL::B:
/// TIOCB2 (入出力)
/// 224 176 144 100
/// P15 o o o o
/// PA7 o o o o
switch(odr) {
case ORDER::FIRST:
PORT1::PMR.B5 = 0;
MPC::P15PFS.PSEL = sel;
PORT1::PMR.B5 = ena;
break;
case ORDER::SECOND:
PORTA::PMR.B7 = 0;
MPC::PA7PFS.PSEL = sel;
PORTA::PMR.B7 = ena;
break;
default:
ret = false;
break;
}
break;
default:
ret = false;
break;
}
return ret;
}
static bool tpu3_(CHANNEL ch, bool ena, ORDER odr) noexcept
{
bool ret = true;
uint8_t sel = ena ? 0b00'0011 : 0;
switch(ch) {
case CHANNEL::A:
/// TIOCA3 (入出力)
/// 224 176 144 100
/// P21 o o o o
/// PB0 o o o o
switch(odr) {
case ORDER::FIRST:
PORT2::PMR.B1 = 0;
MPC::P21PFS.PSEL = sel;
PORT2::PMR.B1 = ena;
break;
case ORDER::SECOND:
PORTB::PMR.B0 = 0;
MPC::PB0PFS.PSEL = sel;
PORTB::PMR.B0 = ena;
break;
default:
ret = false;
break;
}
break;
case CHANNEL::B:
/// TIOCB3 (入出力)
/// 224 176 144 100
/// P20 o o o o
/// PB1 o o o o
switch(odr) {
case ORDER::FIRST:
PORT2::PMR.B0 = 0;
MPC::P20PFS.PSEL = sel;
PORT2::PMR.B0 = ena;
break;
case ORDER::SECOND:
PORTB::PMR.B1 = 0;
MPC::PB1PFS.PSEL = sel;
PORTB::PMR.B1 = ena;
break;
default:
ret = false;
break;
}
break;
case CHANNEL::C:
/// TIOCC3 (入出力)
/// 224 176 144 100
/// P22 o o o o
/// PB2 o o o o
switch(odr) {
case ORDER::FIRST:
PORT2::PMR.B2 = 0;
MPC::P22PFS.PSEL = sel;
PORT2::PMR.B2 = ena;
break;
case ORDER::SECOND:
PORTB::PMR.B2 = 0;
MPC::PB2PFS.PSEL = sel;
PORTB::PMR.B2 = ena;
break;
default:
ret = false;
break;
}
break;
case CHANNEL::D:
/// TIOCD3 (入出力)
/// 224 176 144 100
/// P23 o o o o
/// PB3 o o o o
switch(odr) {
case ORDER::FIRST:
PORT2::PMR.B3 = 0;
MPC::P23PFS.PSEL = sel;
PORT2::PMR.B3 = ena;
break;
case ORDER::SECOND:
PORTB::PMR.B3 = 0;
MPC::PB3PFS.PSEL = sel;
PORTB::PMR.B3 = ena;
break;
default:
ret = false;
break;
}
break;
default:
ret = false;
break;
}
return ret;
}
static bool tpu4_(CHANNEL ch, bool ena, ORDER odr) noexcept
{
bool ret = true;
uint8_t sel = ena ? 0b00'0011 : 0;
switch(ch) {
case CHANNEL::A:
/// TIOCA4 (入出力)
/// 224 176 144 100
/// P25 o o o o
/// PB4 o o o o
switch(odr) {
case ORDER::FIRST:
PORT2::PMR.B5 = 0;
MPC::P25PFS.PSEL = sel;
PORT2::PMR.B5 = ena;
break;
case ORDER::SECOND:
PORTB::PMR.B4 = 0;
MPC::PB4PFS.PSEL = sel;
PORTB::PMR.B4 = ena;
break;
default:
ret = false;
break;
}
break;
case CHANNEL::B:
/// TIOCB4 (入出力)
/// 224 176 144 100
/// P24 o o o o
/// PB5 o o o o
switch(odr) {
case ORDER::FIRST:
PORT2::PMR.B4 = 0;
MPC::P24PFS.PSEL = sel;
PORT2::PMR.B4 = ena;
break;
case ORDER::SECOND:
PORTB::PMR.B5 = 0;
MPC::PB5PFS.PSEL = sel;
PORTB::PMR.B5 = ena;
break;
default:
ret = false;
break;
}
break;
default:
ret = false;
break;
}
return ret;
}
static bool tpu5_(CHANNEL ch, bool ena, ORDER odr) noexcept
{
bool ret = true;
uint8_t sel = ena ? 0b00'0011 : 0;
switch(ch) {
case CHANNEL::A:
/// TIOCA5 (入出力)
/// 224 176 144 100
/// P13 o o o o
/// PB6 o o o o
switch(odr) {
case ORDER::FIRST:
PORT1::PMR.B3 = 0;
MPC::P13PFS.PSEL = sel;
PORT1::PMR.B3 = ena;
break;
case ORDER::SECOND:
PORTB::PMR.B6 = 0;
MPC::PB6PFS.PSEL = sel;
PORTB::PMR.B6 = ena;
break;
default:
ret = false;
break;
}
break;
case CHANNEL::B:
/// TIOCB5 (入出力)
/// 224 176 144 100
/// P14 o o o o
/// PB7 o o o o
switch(odr) {
case ORDER::FIRST:
PORT1::PMR.B4 = 0;
MPC::P14PFS.PSEL = sel;
PORT1::PMR.B4 = ena;
break;
case ORDER::SECOND:
PORTB::PMR.B7 = 0;
MPC::PB7PFS.PSEL = sel;
PORTB::PMR.B7 = ena;
break;
default:
ret = false;
break;
}
break;
default:
ret = false;
break;
}
return ret;
}
public:
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++//
/*!
@brief タイマー系、チャネル別ポート切り替え
@param[in] per 周辺機器タイプ
@param[in] ch チャネル
@param[in] ena 無効にする場合場合「false」
@param[in] odr 候補を選択する場合
@return 無効な周辺機器の場合「false」
*/
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++//
static bool turn(peripheral per, CHANNEL ch, bool ena = true, ORDER odr = ORDER::FIRST) noexcept
{
if(odr == ORDER::BYPASS) return true;
MPC::PWPR.B0WI = 0; // PWPR 書き込み許可
MPC::PWPR.PFSWE = 1; // PxxPFS 書き込み許可
bool ret = true;
switch(per) {
case peripheral::TPU0:
ret = tpu0_(ch, ena, odr);
break;
case peripheral::TPU1:
ret = tpu1_(ch, ena, odr);
break;
case peripheral::TPU2:
ret = tpu2_(ch, ena, odr);
break;
case peripheral::TPU3:
ret = tpu3_(ch, ena, odr);
break;
case peripheral::TPU4:
ret = tpu4_(ch, ena, odr);
break;
case peripheral::TPU5:
ret = tpu5_(ch, ena, odr);
break;
default:
ret = false;
break;
}
MPC::PWPR = MPC::PWPR.B0WI.b();
return ret;
}
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++//
/*!
@brief TPU クロック入力切り替え
@param[in] clk クロック型
@param[in] ena 無効にする場合場合「false」
@param[in] odr 候補を選択する場合
@return 無効な周辺機器の場合「false」
*/
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++//
static bool turn_clock(CHANNEL clk, bool ena = true, ORDER odr = ORDER::FIRST) noexcept
{
MPC::PWPR.B0WI = 0; // PWPR 書き込み許可
MPC::PWPR.PFSWE = 1; // PxxPFS 書き込み許可
bool ret = true;
switch(clk) {
case CHANNEL::CLK_A:
/// TCLKA (入力)
/// 224 176 144 100
/// P14 o o o o
/// PC2 o o o o
switch(odr) {
case ORDER::FIRST:
PORT1::PMR.B4 = 0;
MPC::P14PFS.PSEL = ena ? 0b00'0100 : 0;
PORT1::PMR.B4 = ena;
break;
case ORDER::SECOND:
PORTC::PMR.B2 = 0;
MPC::PC2PFS.PSEL = ena ? 0b00'0011 : 0;
PORTC::PMR.B2 = ena;
break;
default:
ret = false;
break;
}
break;
case CHANNEL::CLK_B:
/// TCLKB (入力)
/// 224 176 144 100
/// P15 o o o o
/// PA3 o o o o
/// PC3 o o o o
switch(odr) {
case ORDER::FIRST:
PORT1::PMR.B5 = 0;
MPC::P15PFS.PSEL = ena ? 0b00'0100 : 0;
PORT1::PMR.B5 = ena;
break;
case ORDER::SECOND:
PORTA::PMR.B3 = 0;
MPC::PA3PFS.PSEL = ena ? 0b00'0100 : 0;
PORTA::PMR.B3 = ena;
break;
case ORDER::THIRD:
PORTC::PMR.B3 = 0;
MPC::PC3PFS.PSEL = ena ? 0b00'0011 : 0;
PORTC::PMR.B3 = ena;
break;
default:
ret = false;
break;
}
break;
case CHANNEL::CLK_C:
/// TCLKC (入力)
/// 224 176 144 100
/// P16 o o o o
/// PB2 o o o o
/// PC0 o o o o
switch(odr) {
case ORDER::FIRST:
PORT1::PMR.B6 = 0;
MPC::P16PFS.PSEL = ena ? 0b00'0100 : 0;
PORT1::PMR.B6 = ena;
break;
case ORDER::SECOND:
PORTB::PMR.B2 = 0;
MPC::PB2PFS.PSEL = ena ? 0b00'0100 : 0;
PORTB::PMR.B2 = ena;
break;
case ORDER::THIRD:
PORTC::PMR.B0 = 0;
MPC::PC0PFS.PSEL = ena ? 0b00'0011 : 0;
PORTC::PMR.B0 = ena;
break;
default:
ret = false;
break;
}
break;
case CHANNEL::CLK_D:
/// TCLKD (入力)
/// 224 176 144 100
/// P17 o o o o
/// PB3 o o o o
/// PC1 o o o o
switch(odr) {
case ORDER::FIRST:
PORT1::PMR.B7 = 0;
MPC::P17PFS.PSEL = ena ? 0b00'0100 : 0;
PORT1::PMR.B7 = ena;
break;
case ORDER::SECOND:
PORTB::PMR.B3 = 0;
MPC::PB3PFS.PSEL = ena ? 0b00'0100 : 0;
PORTB::PMR.B3 = ena;
break;
case ORDER::THIRD:
PORTC::PMR.B1 = 0;
MPC::PC1PFS.PSEL = ena ? 0b00'0011 : 0;
PORTC::PMR.B1 = ena;
break;
default:
ret = false;
break;
}
break;
default:
ret = false;
break;
}
MPC::PWPR = MPC::PWPR.B0WI.b();
return ret;
}
};
}