From 0a58130c6ab8ac82116942015f3e838672faf729 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Maciej=20Kope=C4=87?= <maciejpkopec@gmail.com>
Date: Tue, 13 Aug 2024 10:08:15 -0700
Subject: [PATCH 01/12] Organize snippets in alphabetical order according to
 their names

---
 snippets/verilog.snippets | 94 +++++++++++++++++++--------------------
 1 file changed, 47 insertions(+), 47 deletions(-)

diff --git a/snippets/verilog.snippets b/snippets/verilog.snippets
index 16bacc2a3..435f938d7 100644
--- a/snippets/verilog.snippets
+++ b/snippets/verilog.snippets
@@ -1,34 +1,6 @@
-# if statement
-snippet if
-	if (${1}) begin
-		${0}
-	end
-# If/else statements
-snippet ife
-	if (${1}) begin
-		${2}
-	end
-	else begin
-		${3}
-	end
-# Else if statement
-snippet eif
-	else if (${1}) begin
-		${0}
-	end
-#Else statement
-snippet el
-	else begin
-		${0}
-	end
-# While statement
-snippet wh
-	while (${1}) begin
-		${0}
-	end
-# Repeat Loop
-snippet rep
-	repeat (${1}) begin
+# Always block
+snippet al
+	always @(${1:/* sensitive list */}) begin
 		${0}
 	end
 # Case statement
@@ -51,16 +23,16 @@ snippet casez
 			${4}
 		end
 	endcase
-# Always block
-snippet al
-	always @(${1:/* sensitive list */}) begin
+# Else if statement
+snippet eif
+	else if (${1}) begin
 		${0}
 	end
-# Module block
-snippet mod
-	module ${1:`vim_snippets#Filename('$1', 'name')`} (${2});
+#Else statement
+snippet el
+	else begin
 		${0}
-	endmodule
+	end
 # For
 snippet for
 	for (int ${2:i} = 0; $2 < ${1:count}; $2${3:++}) begin
@@ -76,24 +48,52 @@ snippet fun
 	function ${1:void} ${2:name}(${3});
 		${0}
 	endfunction: $2
-# Task
-snippet task
-	task ${1:name}(${2});
+# if statement
+snippet if
+	if (${1}) begin
 		${0}
-	endtask: $1
+	end
+# If/else statements
+snippet ife
+	if (${1}) begin
+		${2}
+	end
+	else begin
+		${3}
+	end
 # Initial 
 snippet ini
 	initial begin
 		${0}
 	end
-# typedef struct packed
-snippet tdsp
-	typedef struct packed {
-		int ${2:data};
-	} ${1:`vim_snippets#Filename('$1_t', 'name')`};
+# Module block
+snippet mod
+	module ${1:`vim_snippets#Filename('$1', 'name')`} (${2});
+		${0}
+	endmodule
+# Repeat Loop
+snippet rep
+	repeat (${1}) begin
+		${0}
+	end
+# Task
+snippet task
+	task ${1:name}(${2});
+		${0}
+	endtask: $1
 # typedef eum
 snippet tde
 	typedef enum ${2:logic[15:0]}
 	{
 		${3:REG = 16'h0000}
 	} ${1:my_dest_t};
+# typedef struct packed
+snippet tdsp
+	typedef struct packed {
+		int ${2:data};
+	} ${1:`vim_snippets#Filename('$1_t', 'name')`};
+# While statement
+snippet wh
+	while (${1}) begin
+		${0}
+	end

From 566d36f8b66a1721d5420ba649f80249f4e97c29 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Maciej=20Kope=C4=87?= <maciejpkopec@gmail.com>
Date: Tue, 13 Aug 2024 13:32:36 -0700
Subject: [PATCH 02/12] Add mkopec's Verilog/SystemVerilog snippets

---
 UltiSnips/systemverilog.snippets         |  1 +
 UltiSnips/verilog.snippets               | 16 ++++++++++
 UltiSnips/verilog_systemverilog.snippets |  1 +
 snippets/verilog.snippets                | 38 +++++++++++++++++++++++-
 snippets/verilog_systemverilog.snippets  |  1 +
 5 files changed, 56 insertions(+), 1 deletion(-)
 create mode 100644 UltiSnips/systemverilog.snippets
 create mode 100644 UltiSnips/verilog.snippets
 create mode 100644 UltiSnips/verilog_systemverilog.snippets
 create mode 100644 snippets/verilog_systemverilog.snippets

diff --git a/UltiSnips/systemverilog.snippets b/UltiSnips/systemverilog.snippets
new file mode 100644
index 000000000..1e6c97c28
--- /dev/null
+++ b/UltiSnips/systemverilog.snippets
@@ -0,0 +1 @@
+extends verilog
diff --git a/UltiSnips/verilog.snippets b/UltiSnips/verilog.snippets
new file mode 100644
index 000000000..294187d40
--- /dev/null
+++ b/UltiSnips/verilog.snippets
@@ -0,0 +1,16 @@
+snippet in "Input"
+input${1: [${2:n}:${3:0}]} ${0:name}
+endsnippet
+
+snippet out "Output"
+output${1: reg}${2: [${3:n}:${4:0}]} ${0:name}
+endsnippet
+
+snippet reg "Register variable"
+reg${1: [${2:n}:${3:0}]} ${0:name};
+endsnippet
+
+snippet wire "Wire variable"
+wire${1: [${2:n}:${3:0}]} ${0:name};
+endsnippet
+
diff --git a/UltiSnips/verilog_systemverilog.snippets b/UltiSnips/verilog_systemverilog.snippets
new file mode 100644
index 000000000..07d26b409
--- /dev/null
+++ b/UltiSnips/verilog_systemverilog.snippets
@@ -0,0 +1 @@
+extends systemverilog
diff --git a/snippets/verilog.snippets b/snippets/verilog.snippets
index 435f938d7..b5a1f54cc 100644
--- a/snippets/verilog.snippets
+++ b/snippets/verilog.snippets
@@ -3,6 +3,13 @@ snippet al
 	always @(${1:/* sensitive list */}) begin
 		${0}
 	end
+snippet as "Assign"
+	assign ${1:name} = ${0:value};
+# Begin-end block
+snippet be
+	begin
+		${0:VISUAL}
+	end
 # Case statement
 snippet case
 	case (${1:/* variable */})
@@ -23,6 +30,8 @@ snippet casez
 			${4}
 		end
 	endcase
+snippet cond "Conditional operator"
+	(${1:if}) ? ${2:then} : ${3:else};
 # Else if statement
 snippet eif
 	else if (${1}) begin
@@ -48,6 +57,10 @@ snippet fun
 	function ${1:void} ${2:name}(${3});
 		${0}
 	endfunction: $2
+snippet gen
+	generate
+		${0:${VISUAL}}
+	endgenerate
 # if statement
 snippet if
 	if (${1}) begin
@@ -61,21 +74,44 @@ snippet ife
 	else begin
 		${3}
 	end
-# Initial 
+# Initial
 snippet ini
 	initial begin
 		${0}
 	end
+snippet lpar "Local parameter definition"
+	localparam ${1:name} = ${0:value}
 # Module block
 snippet mod
 	module ${1:`vim_snippets#Filename('$1', 'name')`} (${2});
 		${0}
 	endmodule
+# Module block with parameters
+snippet modp
+	module ${1:`vim_snippets#Filename('$1', 'name')`} #(${2}) (${3});
+		${0}
+	endmodule
+snippet ned "Negative edge"
+	negedge ${0:signal}
 # Repeat Loop
 snippet rep
 	repeat (${1}) begin
 		${0}
 	end
+snippet par "Parameter definition"
+	parameter ${1:name} = ${0:value}
+snippet ped "Positive edge"
+	posedge ${0:signal}
+# Sequential block
+snippet seq
+	always @(${1:posedge clk}${2:, posedge rst}) begin
+		if (${3:rst}) begin
+			${4}
+		end
+		else begin
+			${0}
+		end
+	end
 # Task
 snippet task
 	task ${1:name}(${2});
diff --git a/snippets/verilog_systemverilog.snippets b/snippets/verilog_systemverilog.snippets
new file mode 100644
index 000000000..07d26b409
--- /dev/null
+++ b/snippets/verilog_systemverilog.snippets
@@ -0,0 +1 @@
+extends systemverilog

From b78f298668b104dc5135eeb981d216de64563bab Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Maciej=20Kope=C4=87?= <maciejpkopec@gmail.com>
Date: Tue, 13 Aug 2024 13:41:46 -0700
Subject: [PATCH 03/12] Add descriptions to snippets, remove comments

---
 snippets/verilog.snippets | 102 ++++++++++++++++++--------------------
 1 file changed, 47 insertions(+), 55 deletions(-)

diff --git a/snippets/verilog.snippets b/snippets/verilog.snippets
index b5a1f54cc..6dde48c07 100644
--- a/snippets/verilog.snippets
+++ b/snippets/verilog.snippets
@@ -1,109 +1,101 @@
-# Always block
-snippet al
+snippet al "Always block"
 	always @(${1:/* sensitive list */}) begin
 		${0}
 	end
 snippet as "Assign"
 	assign ${1:name} = ${0:value};
-# Begin-end block
-snippet be
+
+snippet be "Begin-end"
 	begin
 		${0:VISUAL}
 	end
-# Case statement
-snippet case
-	case (${1:/* variable */})
-		${2:/* value */}: begin
-			${3}
-		end
-		default: begin
+
+snippet case "Case(xz) statement"
+	case${1:x} (${2:/* variable */})
+		${3:/* value */}: begin
 			${4}
 		end
-	endcase
-# CaseZ statement
-snippet casez
-	casez (${1:/* variable */})
-		${2:/* value */}: begin
-			${3}
-		end
 		default: begin
-			${4}
+			${5}
 		end
 	endcase
-snippet cond "Conditional operator"
-	(${1:if}) ? ${2:then} : ${3:else};
-# Else if statement
-snippet eif
+
+snippet eif "Else if"
 	else if (${1}) begin
 		${0}
 	end
-#Else statement
-snippet el
+
+snippet el "Else"
 	else begin
 		${0}
 	end
-# For
-snippet for
+
+snippet for "For loop"
 	for (int ${2:i} = 0; $2 < ${1:count}; $2${3:++}) begin
 		${4}
 	end
-# Forever
-snippet forev
+
+snippet forev "Forever loop"
 	forever begin
 		${0}
 	end
-# Function
-snippet fun
+
+snippet fun "Function"
 	function ${1:void} ${2:name}(${3});
 		${0}
 	endfunction: $2
-snippet gen
+
+snippet gen "Generate block"
 	generate
 		${0:${VISUAL}}
 	endgenerate
-# if statement
-snippet if
+
+snippet if "If statement"
 	if (${1}) begin
 		${0}
 	end
-# If/else statements
-snippet ife
+
+snippet ife "If-else statement"
 	if (${1}) begin
 		${2}
 	end
 	else begin
 		${3}
 	end
-# Initial
-snippet ini
+
+snippet ini "Initial block"
 	initial begin
 		${0}
 	end
-snippet lpar "Local parameter definition"
+
+snippet lpar "Local parameter"
 	localparam ${1:name} = ${0:value}
-# Module block
-snippet mod
+
+snippet mod "Module"
 	module ${1:`vim_snippets#Filename('$1', 'name')`} (${2});
 		${0}
 	endmodule
-# Module block with parameters
-snippet modp
+
+snippet modp "Module with parameters"
 	module ${1:`vim_snippets#Filename('$1', 'name')`} #(${2}) (${3});
 		${0}
 	endmodule
+
 snippet ned "Negative edge"
 	negedge ${0:signal}
-# Repeat Loop
-snippet rep
+
+snippet rep "Repeat loop"
 	repeat (${1}) begin
 		${0}
 	end
+
 snippet par "Parameter definition"
 	parameter ${1:name} = ${0:value}
+
 snippet ped "Positive edge"
 	posedge ${0:signal}
-# Sequential block
-snippet seq
+
+snippet seq "Sequential block"
 	always @(${1:posedge clk}${2:, posedge rst}) begin
 		if (${3:rst}) begin
 			${4}
@@ -112,24 +104,24 @@ snippet seq
 			${0}
 		end
 	end
-# Task
-snippet task
+
+snippet task "Task definition"
 	task ${1:name}(${2});
 		${0}
 	endtask: $1
-# typedef eum
-snippet tde
+
+snippet tde "Typedef enum"
 	typedef enum ${2:logic[15:0]}
 	{
 		${3:REG = 16'h0000}
 	} ${1:my_dest_t};
-# typedef struct packed
-snippet tdsp
+
+snippet tdsp "Typedef struct packed"
 	typedef struct packed {
 		int ${2:data};
 	} ${1:`vim_snippets#Filename('$1_t', 'name')`};
-# While statement
-snippet wh
+
+snippet wh "While loop"
 	while (${1}) begin
 		${0}
 	end

From 08c3d42c995ff7482153c33159e543a80ee040b0 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Maciej=20Kope=C4=87?= <maciejpkopec@gmail.com>
Date: Tue, 13 Aug 2024 16:11:43 -0700
Subject: [PATCH 04/12] Reorganize systemverilog snippets to alphabetical order

---
 snippets/systemverilog.snippets | 477 ++++++++++++++++----------------
 1 file changed, 231 insertions(+), 246 deletions(-)

diff --git a/snippets/systemverilog.snippets b/snippets/systemverilog.snippets
index 828a6de9c..437b9bed2 100644
--- a/snippets/systemverilog.snippets
+++ b/snippets/systemverilog.snippets
@@ -1,32 +1,22 @@
 extends verilog
 
-# Foreach Loop
-snippet forea
-	foreach (${1}) begin
-		${0}
-	end
-# Do-while statement
-snippet dowh
-	do begin
-		${0}
-	end while (${1});
-# Combinational always block
-snippet alc
+
+snippet alc "Always combinational"
 	always_comb begin ${1:: statement_label}
 		${0}
 	end $1
-# Sequential logic
-snippet alff
+
+snippet alff "Always flip-flop"
 	always_ff @(posedge ${1:clk}) begin ${2:: statement_label}
 		${0}
 	end $2
-# Latched logic
-snippet all
+
+snippet all "Always latch"
 	always_latch begin ${1:: statement_label}
 		${0}
 	end $1
-# Class
-snippet cl
+
+snippet cl "Class"
 	class ${1:class_name};
 		// data or class properties
 		${0}
@@ -36,17 +26,27 @@ snippet cl
 		endfunction : new
 
 	endclass : $1
-# Typedef structure
-snippet types
-	typedef struct {
+
+snippet clock "Clocking group"
+	clocking ${1:clocking_name} @(${2:posedge} ${3:clk});
 		${0}
-	} ${1:name_t};
-# Program block
-snippet prog
-	program ${1:program_name} ();
+	endclocking : $1
+
+snippet cg "Coverage group"
+	covergroup ${1:group_name} @(${2:posedge} ${3:clk});
 		${0}
-	endprogram : $1
-# Interface block
+	endgroup : $1
+
+snippet dowh "Do..while loop"
+	do begin
+		${0}
+	end while (${1});
+
+snippet forea "Foreach loop"
+	foreach (${1}) begin
+		${0}
+	end
+
 snippet intf
 	interface ${1:program_name} ();
 		// nets
@@ -56,66 +56,21 @@ snippet intf
 		// modports
 
 	endinterface : $1
-# Clocking Block
-snippet clock
-	clocking ${1:clocking_name} @(${2:posedge} ${3:clk});
-		${0}
-	endclocking : $1
-# Covergroup construct
-snippet cg
-	covergroup ${1:group_name} @(${2:posedge} ${3:clk});
-		${0}
-	endgroup : $1
-# Package declaration
+
 snippet pkg
 	package ${1:package_name};
 		${0}
 	endpackage : $1
 
-snippet uvm_object
-	//  Class: $1
-	//
-	class ${1:my_class} extends ${2:uvm_object};
-		\`uvm_object_utils($1);
-
-		//  Group: Variables
-
-
-		//  Group: Constraints
-
-
-		//  Group: Functions
-
-		//  Constructor: new
-		function new(string name = "$1");
-			super.new(name);
-		endfunction: new
-		$0
-	endclass: $1
-
-
-snippet uvm_object_with_parameters
-	//  Class: $1
-	//
-	class ${1:my_class} #(${2:parameters}) extends ${3:uvm_object};
-		typedef $1 #(${2/(\b(parameter|type)\s+([A-Za-z_][A-Za-z0-9_$]*)(\s*=\s*([A-Za-z0-9_$]+))?)*\b/$3/g}) this_type_t;
-		\`uvm_object_param_utils(this_type_t);
-
-		//  Group: Variables
-
-
-		//  Group: Constraints
-
-
-		//  Group: Functions
-
-		//  Constructor: new
-		function new(string name = "$1");
-			super.new(name);
-		endfunction: new
-		$0
-	endclass: $1
+snippet prog
+	program ${1:program_name} ();
+		${0}
+	endprogram : $1
 
+snippet types "Struct typedef"
+	typedef struct {
+		${0}
+	} ${1:name_t};
 
 snippet uvm_component
 	//  Class: $1
@@ -145,35 +100,6 @@ snippet uvm_component
 		$0
 	endclass: $1
 
-
-snippet uvm_component_with_parameters
-	//  Class: $1
-	//
-	class ${1:my_class} #(${2:parameters}) extends ${3:uvm_component};
-		typedef $1 #(${2/(\b(parameter|type)\s+([A-Za-z_][A-Za-z0-9_$]*)(\s*=\s*([A-Za-z0-9_$]+))?)*\b/$3/g}) this_type_t;
-		\`uvm_component_param_utils(this_type_t);
-
-		//  Group: Configuration Object(s)
-
-		//  Var: config_obj
-		${4:config_obj_t} config_obj;
-
-
-		//  Group: Components
-
-
-		//  Group: Variables
-
-
-		//  Constructor: new
-		function new(string name = "$1", uvm_component parent);
-			super.new(name, parent);
-		endfunction: new
-
-		$0
-	endclass: $1
-
-
 snippet uvm_component_extended
 	//  Class: $1
 	//
@@ -284,12 +210,37 @@ snippet uvm_component_extended
 		super.extract_phase(phase);
 	endfunction: extract_phase
 
+snippet uvm_component_with_parameters
+	//  Class: $1
+	//
+	class ${1:my_class} #(${2:parameters}) extends ${3:uvm_component};
+		typedef $1 #(${2/(\b(parameter|type)\s+([A-Za-z_][A-Za-z0-9_$]*)(\s*=\s*([A-Za-z0-9_$]+))?)*\b/$3/g}) this_type_t;
+		\`uvm_component_param_utils(this_type_t);
 
+		//  Group: Configuration Object(s)
 
-snippet uvm_sequence
+		//  Var: config_obj
+		${4:config_obj_t} config_obj;
+
+
+		//  Group: Components
+
+
+		//  Group: Variables
+
+
+		//  Constructor: new
+		function new(string name = "$1", uvm_component parent);
+			super.new(name, parent);
+		endfunction: new
+
+		$0
+	endclass: $1
+
+snippet uvm_object
 	//  Class: $1
 	//
-	class ${1:my_class} extends ${2:uvm_sequence};
+	class ${1:my_class} extends ${2:uvm_object};
 		\`uvm_object_utils($1);
 
 		//  Group: Variables
@@ -304,62 +255,36 @@ snippet uvm_sequence
 		function new(string name = "$1");
 			super.new(name);
 		endfunction: new
+		$0
+	endclass: $1
 
-		//  Task: pre_start
-		//  This task is a user-definable callback that is called before the optional 
-		//  execution of <pre_body>.
-		// extern virtual task pre_start();
-
-		//  Task: pre_body
-		//  This task is a user-definable callback that is called before the execution 
-		//  of <body> ~only~ when the sequence is started with <start>.
-		//  If <start> is called with ~call_pre_post~ set to 0, ~pre_body~ is not called.
-		// extern virtual task pre_body();
+snippet uvm_object_with_parameters
+	//  Class: $1
+	//
+	class ${1:my_class} #(${2:parameters}) extends ${3:uvm_object};
+		typedef $1 #(${2/(\b(parameter|type)\s+([A-Za-z_][A-Za-z0-9_$]*)(\s*=\s*([A-Za-z0-9_$]+))?)*\b/$3/g}) this_type_t;
+		\`uvm_object_param_utils(this_type_t);
 
-		//  Task: pre_do
-		//  This task is a user-definable callback task that is called ~on the parent 
-		//  sequence~, if any. The sequence has issued a wait_for_grant() call and after
-		//  the sequencer has selected this sequence, and before the item is randomized.
-		//
-		//  Although pre_do is a task, consuming simulation cycles may result in unexpected
-		//  behavior on the driver.
-		// extern virtual task pre_do(bit is_item);
+		//  Group: Variables
 
-		//  Function: mid_do
-		//  This function is a user-definable callback function that is called after the 
-		//  sequence item has been randomized, and just before the item is sent to the 
-		//  driver.
-		// extern virtual function void mid_do(uvm_sequence_item this_item);
 
-		//  Task: body
-		//  This is the user-defined task where the main sequence code resides.
-		extern virtual task body();
+		//  Group: Constraints
 
-		//  Function: post_do
-		//  This function is a user-definable callback function that is called after the 
-		//  driver has indicated that it has completed the item, using either this 
-		//  item_done or put methods. 
-		// extern virtual function void post_do(uvm_sequence_item this_item);
 
-		//  Task: post_body
-		//  This task is a user-definable callback task that is called after the execution 
-		//  of <body> ~only~ when the sequence is started with <start>.
-		//  If <start> is called with ~call_pre_post~ set to 0, ~post_body~ is not called.
-		// extern virtual task post_body();
+		//  Group: Functions
 
-		//  Task: post_start
-		//  This task is a user-definable callback that is called after the optional 
-		//  execution of <post_body>.
-		// extern virtual task post_start();
+		//  Constructor: new
+		function new(string name = "$1");
+			super.new(name);
+		endfunction: new
 		$0
 	endclass: $1
 
-snippet uvm_sequence_with_parameters
+snippet uvm_sequence
 	//  Class: $1
 	//
-	class ${1:my_class} #(${2:parameters}) extends ${3:uvm_sequence};
-		typedef $1 #(${2/(\b(parameter|type)\s+([A-Za-z_][A-Za-z0-9_$]*)(\s*=\s*([A-Za-z0-9_$]+))?)*\b/$3/g}) this_type_t;
-		\`uvm_object_param_utils(this_type_t);
+	class ${1:my_class} extends ${2:uvm_sequence};
+		\`uvm_object_utils($1);
 
 		//  Group: Variables
 
@@ -456,7 +381,6 @@ snippet uvm_sequence_functions
 	// task $1post_start();
 	// endtask: post_start
 
-
 snippet uvm_sequence_item
 	//  Class: $1
 	//
@@ -507,6 +431,102 @@ snippet uvm_sequence_item
 	/*----------------------------------------------------------------------------*/
 	
 
+snippet uvm_sequence_item_convert2string
+	function string ${1:my_class}${2:::}convert2string();
+		string s;
+
+		/*  chain the convert2string with parent classes  */
+		s = super.convert2string();
+
+		/*  list of local properties to be printed:  */
+		//  guide             0---4---8--12--16--20--24--28--32--36--40--44--48--
+		// s = {s, \$sformatf("property_label      : 0x%0h\n", property_name)};
+		// s = {s, \$sformatf("property_label      :   %0d\n", property_name)};
+
+		return s;
+	endfunction: convert2string$0
+
+snippet uvm_sequence_item_do_compare
+	function bit ${1:my_class}${2:::}do_compare(uvm_object rhs, uvm_comparer comparer);
+		this_type_t rhs_;
+
+		if (!\$cast(rhs_, rhs)) begin
+			\`uvm_error({this.get_name(), ".do_compare()"}, "Cast failed!");
+			return;
+		end
+		// \`uvm_info({this.get_name(), ".do_compare()"}, "Cast succeded.", UVM_HIGH);
+
+		/*  chain the compare with parent classes  */
+		do_compare = super.do_compare(rhs, comparer);
+
+		/*  list of local properties to be compared:  */
+		do_compare &= (
+			// <this.property_name == rhs_.property_name> &&
+			// <this.property_name == rhs_.property_name>
+		);
+	endfunction: do_compare$0
+
+snippet uvm_sequence_item_do_copy
+	function void ${1:my_class}${2:::}do_copy(uvm_object rhs);
+		this_type_t rhs_;
+
+		if (!\$cast(rhs_, rhs)) begin
+			\`uvm_error({this.get_name(), ".do_copy()"}, "Cast failed!");
+			return;
+		end
+		// \`uvm_info({this.get_name(), ".do_copy()"}, "Cast succeded.", UVM_HIGH);
+
+		/*  chain the copy with parent classes  */
+		super.do_copy(rhs);
+
+		/*  list of local properties to be copied  */
+		// <this.property_name = rhs_.property_name>;
+	endfunction: do_copy$0
+
+snippet uvm_sequence_item_do_pack
+	function void ${1:my_class}${2:::}do_pack(uvm_packer packer);
+		/*  chain the pack with parent classes  */
+		super.do_pack(packer);
+
+		/*  list of local properties to be packed:  */
+		//  note: look up the appropriate macro(s) for your properties!
+		// \`uvm_pack_int(property_name);
+		// \`uvm_pack_queue(property_name);
+		// \`uvm_pack_string(property_name);
+	endfunction: do_pack$0
+
+snippet uvm_sequence_item_do_print
+	function void ${1:my_class}${2:::}do_print(uvm_printer printer)
+		/*  chain the print with parent classes  */
+		super.do_print(printer);
+
+		/*  list of local properties to be printed:  */
+		// printer.print_string("property_label", property_name);
+		// printer.print_field_int("property_label", property_name, \$bits(property_name), UVM_HEX);
+	endfunction: do_print$0
+
+snippet uvm_sequence_item_do_record
+	function void ${1:my_class}${2:::}do_record(uvm_recorder recorder);
+		/*  chain the record with parent classes  */
+		super.do_record(recorder);
+
+		/*  list of local properties to be recorded:  */
+		/*  note: use uvm_record_int, uvm_record_string, uvm_record_time, uvm_record_real for known basic types.  */
+		// \`uvm_record_string("property_label", property_name);
+		// \`uvm_record_int("property_label", property_name, \$bits(property_name), UVM_HEX);
+	endfunction: do_record$0
+
+snippet uvm_sequence_item_do_unpack
+	function void ${1:my_class}${2:::}do_unpack(uvm_packer packer);
+		/*  chain the unpack with parent classes  */
+		super.do_unpack(packer);
+
+		/*  list of local properties to be unpacked:  */
+		//  note: look up the appropriate macro(s) for your properties!
+		// \`uvm_unpack_int(property_name);
+		// \`uvm_unpack_queue(property_name);
+		// \`uvm_unpack_string(property_name);
+	endfunction: do_unpack$0
 
 snippet uvm_sequence_item_with_parameters
 	//  Class: $1
@@ -558,107 +578,72 @@ snippet uvm_sequence_item_with_parameters
 	/*----------------------------------------------------------------------------*/
 	
 
+snippet uvm_sequence_with_parameters
+	//  Class: $1
+	//
+	class ${1:my_class} #(${2:parameters}) extends ${3:uvm_sequence};
+		typedef $1 #(${2/(\b(parameter|type)\s+([A-Za-z_][A-Za-z0-9_$]*)(\s*=\s*([A-Za-z0-9_$]+))?)*\b/$3/g}) this_type_t;
+		\`uvm_object_param_utils(this_type_t);
 
-snippet uvm_sequence_item_do_copy
-	function void ${1:my_class}${2:::}do_copy(uvm_object rhs);
-		this_type_t rhs_;
-
-		if (!\$cast(rhs_, rhs)) begin
-			\`uvm_error({this.get_name(), ".do_copy()"}, "Cast failed!");
-			return;
-		end
-		// \`uvm_info({this.get_name(), ".do_copy()"}, "Cast succeded.", UVM_HIGH);
-
-		/*  chain the copy with parent classes  */
-		super.do_copy(rhs);
-
-		/*  list of local properties to be copied  */
-		// <this.property_name = rhs_.property_name>;
-	endfunction: do_copy$0
-
-
-
-snippet uvm_sequence_item_do_compare
-	function bit ${1:my_class}${2:::}do_compare(uvm_object rhs, uvm_comparer comparer);
-		this_type_t rhs_;
-
-		if (!\$cast(rhs_, rhs)) begin
-			\`uvm_error({this.get_name(), ".do_compare()"}, "Cast failed!");
-			return;
-		end
-		// \`uvm_info({this.get_name(), ".do_compare()"}, "Cast succeded.", UVM_HIGH);
-
-		/*  chain the compare with parent classes  */
-		do_compare = super.do_compare(rhs, comparer);
-
-		/*  list of local properties to be compared:  */
-		do_compare &= (
-			// <this.property_name == rhs_.property_name> &&
-			// <this.property_name == rhs_.property_name>
-		);
-	endfunction: do_compare$0
-
-
-
-snippet uvm_sequence_item_convert2string
-	function string ${1:my_class}${2:::}convert2string();
-		string s;
+		//  Group: Variables
 
-		/*  chain the convert2string with parent classes  */
-		s = super.convert2string();
 
-		/*  list of local properties to be printed:  */
-		//  guide             0---4---8--12--16--20--24--28--32--36--40--44--48--
-		// s = {s, \$sformatf("property_label      : 0x%0h\n", property_name)};
-		// s = {s, \$sformatf("property_label      :   %0d\n", property_name)};
+		//  Group: Constraints
 
-		return s;
-	endfunction: convert2string$0
 
+		//  Group: Functions
 
+		//  Constructor: new
+		function new(string name = "$1");
+			super.new(name);
+		endfunction: new
 
-snippet uvm_sequence_item_do_print
-	function void ${1:my_class}${2:::}do_print(uvm_printer printer)
-		/*  chain the print with parent classes  */
-		super.do_print(printer);
+		//  Task: pre_start
+		//  This task is a user-definable callback that is called before the optional 
+		//  execution of <pre_body>.
+		// extern virtual task pre_start();
 
-		/*  list of local properties to be printed:  */
-		// printer.print_string("property_label", property_name);
-		// printer.print_field_int("property_label", property_name, \$bits(property_name), UVM_HEX);
-	endfunction: do_print$0
+		//  Task: pre_body
+		//  This task is a user-definable callback that is called before the execution 
+		//  of <body> ~only~ when the sequence is started with <start>.
+		//  If <start> is called with ~call_pre_post~ set to 0, ~pre_body~ is not called.
+		// extern virtual task pre_body();
 
-snippet uvm_sequence_item_do_record
-	function void ${1:my_class}${2:::}do_record(uvm_recorder recorder);
-		/*  chain the record with parent classes  */
-		super.do_record(recorder);
+		//  Task: pre_do
+		//  This task is a user-definable callback task that is called ~on the parent 
+		//  sequence~, if any. The sequence has issued a wait_for_grant() call and after
+		//  the sequencer has selected this sequence, and before the item is randomized.
+		//
+		//  Although pre_do is a task, consuming simulation cycles may result in unexpected
+		//  behavior on the driver.
+		// extern virtual task pre_do(bit is_item);
 
-		/*  list of local properties to be recorded:  */
-		/*  note: use uvm_record_int, uvm_record_string, uvm_record_time, uvm_record_real for known basic types.  */
-		// \`uvm_record_string("property_label", property_name);
-		// \`uvm_record_int("property_label", property_name, \$bits(property_name), UVM_HEX);
-	endfunction: do_record$0
+		//  Function: mid_do
+		//  This function is a user-definable callback function that is called after the 
+		//  sequence item has been randomized, and just before the item is sent to the 
+		//  driver.
+		// extern virtual function void mid_do(uvm_sequence_item this_item);
 
-snippet uvm_sequence_item_do_pack
-	function void ${1:my_class}${2:::}do_pack(uvm_packer packer);
-		/*  chain the pack with parent classes  */
-		super.do_pack(packer);
+		//  Task: body
+		//  This is the user-defined task where the main sequence code resides.
+		extern virtual task body();
 
-		/*  list of local properties to be packed:  */
-		//  note: look up the appropriate macro(s) for your properties!
-		// \`uvm_pack_int(property_name);
-		// \`uvm_pack_queue(property_name);
-		// \`uvm_pack_string(property_name);
-	endfunction: do_pack$0
+		//  Function: post_do
+		//  This function is a user-definable callback function that is called after the 
+		//  driver has indicated that it has completed the item, using either this 
+		//  item_done or put methods. 
+		// extern virtual function void post_do(uvm_sequence_item this_item);
 
-snippet uvm_sequence_item_do_unpack
-	function void ${1:my_class}${2:::}do_unpack(uvm_packer packer);
-		/*  chain the unpack with parent classes  */
-		super.do_unpack(packer);
+		//  Task: post_body
+		//  This task is a user-definable callback task that is called after the execution 
+		//  of <body> ~only~ when the sequence is started with <start>.
+		//  If <start> is called with ~call_pre_post~ set to 0, ~post_body~ is not called.
+		// extern virtual task post_body();
 
-		/*  list of local properties to be unpacked:  */
-		//  note: look up the appropriate macro(s) for your properties!
-		// \`uvm_unpack_int(property_name);
-		// \`uvm_unpack_queue(property_name);
-		// \`uvm_unpack_string(property_name);
-	endfunction: do_unpack$0
+		//  Task: post_start
+		//  This task is a user-definable callback that is called after the optional 
+		//  execution of <post_body>.
+		// extern virtual task post_start();
+		$0
+	endclass: $1
 

From 1621ec044d2432877633ab05d41328d62e2dfc3d Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Maciej=20Kope=C4=87?= <maciejpkopec@gmail.com>
Date: Tue, 13 Aug 2024 16:13:22 -0700
Subject: [PATCH 05/12] Change the ${0} to ${n}, to make it possible to leave
 the snippet after finishing the editing process

---
 UltiSnips/verilog.snippets |  4 ++--
 snippets/verilog.snippets  | 28 ++++++++++++++--------------
 2 files changed, 16 insertions(+), 16 deletions(-)

diff --git a/UltiSnips/verilog.snippets b/UltiSnips/verilog.snippets
index 294187d40..ef8d321b0 100644
--- a/UltiSnips/verilog.snippets
+++ b/UltiSnips/verilog.snippets
@@ -7,10 +7,10 @@ output${1: reg}${2: [${3:n}:${4:0}]} ${0:name}
 endsnippet
 
 snippet reg "Register variable"
-reg${1: [${2:n}:${3:0}]} ${0:name};
+reg${1: [${2:n}:${3:0}]} ${4:name};
 endsnippet
 
 snippet wire "Wire variable"
-wire${1: [${2:n}:${3:0}]} ${0:name};
+wire${1: [${2:n}:${3:0}]} ${4:name};
 endsnippet
 
diff --git a/snippets/verilog.snippets b/snippets/verilog.snippets
index 6dde48c07..546753479 100644
--- a/snippets/verilog.snippets
+++ b/snippets/verilog.snippets
@@ -1,13 +1,13 @@
 snippet al "Always block"
 	always @(${1:/* sensitive list */}) begin
-		${0}
+		${2}
 	end
 snippet as "Assign"
-	assign ${1:name} = ${0:value};
+	assign ${1:name} = ${2:value};
 
 snippet be "Begin-end"
 	begin
-		${0:VISUAL}
+		${1:VISUAL}
 	end
 
 snippet case "Case(xz) statement"
@@ -22,12 +22,12 @@ snippet case "Case(xz) statement"
 
 snippet eif "Else if"
 	else if (${1}) begin
-		${0}
+		${2}
 	end
 
 snippet el "Else"
 	else begin
-		${0}
+		${1}
 	end
 
 snippet for "For loop"
@@ -37,22 +37,22 @@ snippet for "For loop"
 
 snippet forev "Forever loop"
 	forever begin
-		${0}
+		${1}
 	end
 
 snippet fun "Function"
 	function ${1:void} ${2:name}(${3});
-		${0}
+		${4}
 	endfunction: $2
 
 snippet gen "Generate block"
 	generate
-		${0:${VISUAL}}
+		${1:${VISUAL}}
 	endgenerate
 
 snippet if "If statement"
 	if (${1}) begin
-		${0}
+		${2}
 	end
 
 snippet ife "If-else statement"
@@ -65,7 +65,7 @@ snippet ife "If-else statement"
 
 snippet ini "Initial block"
 	initial begin
-		${0}
+		${1}
 	end
 
 snippet lpar "Local parameter"
@@ -86,7 +86,7 @@ snippet ned "Negative edge"
 
 snippet rep "Repeat loop"
 	repeat (${1}) begin
-		${0}
+		${2}
 	end
 
 snippet par "Parameter definition"
@@ -101,13 +101,13 @@ snippet seq "Sequential block"
 			${4}
 		end
 		else begin
-			${0}
+			${5}
 		end
 	end
 
 snippet task "Task definition"
 	task ${1:name}(${2});
-		${0}
+		${3}
 	endtask: $1
 
 snippet tde "Typedef enum"
@@ -123,5 +123,5 @@ snippet tdsp "Typedef struct packed"
 
 snippet wh "While loop"
 	while (${1}) begin
-		${0}
+		${2}
 	end

From 24c6956c037154a8f23d3fe2d72aa3beaa0be1ba Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Maciej=20Kope=C4=87?= <maciejpkopec@gmail.com>
Date: Tue, 13 Aug 2024 16:16:53 -0700
Subject: [PATCH 06/12] Fix the posedge/negedge behaviour adding an empty line
 after

---
 snippets/verilog.snippets | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/snippets/verilog.snippets b/snippets/verilog.snippets
index 546753479..cef3668ec 100644
--- a/snippets/verilog.snippets
+++ b/snippets/verilog.snippets
@@ -2,6 +2,7 @@ snippet al "Always block"
 	always @(${1:/* sensitive list */}) begin
 		${2}
 	end
+
 snippet as "Assign"
 	assign ${1:name} = ${2:value};
 
@@ -81,9 +82,9 @@ snippet modp "Module with parameters"
 		${0}
 	endmodule
 
-snippet ned "Negative edge"
+snippet neg "Negative edge"
 	negedge ${0:signal}
-
+#
 snippet rep "Repeat loop"
 	repeat (${1}) begin
 		${2}
@@ -92,9 +93,9 @@ snippet rep "Repeat loop"
 snippet par "Parameter definition"
 	parameter ${1:name} = ${0:value}
 
-snippet ped "Positive edge"
+snippet pos "Positive edge"
 	posedge ${0:signal}
-
+#
 snippet seq "Sequential block"
 	always @(${1:posedge clk}${2:, posedge rst}) begin
 		if (${3:rst}) begin

From 101d37bae3731430de7c9f7a29a95071254685b3 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Maciej=20Kope=C4=87?= <maciejpkopec@gmail.com>
Date: Tue, 13 Aug 2024 16:34:41 -0700
Subject: [PATCH 07/12] Add VISUAL to verilog snippets wherever possible

---
 snippets/systemverilog.snippets | 24 ++++++++++++------------
 snippets/verilog.snippets       | 26 +++++++++++++-------------
 2 files changed, 25 insertions(+), 25 deletions(-)

diff --git a/snippets/systemverilog.snippets b/snippets/systemverilog.snippets
index 437b9bed2..94a315557 100644
--- a/snippets/systemverilog.snippets
+++ b/snippets/systemverilog.snippets
@@ -3,23 +3,23 @@ extends verilog
 
 snippet alc "Always combinational"
 	always_comb begin ${1:: statement_label}
-		${0}
+		${2:${VISUAL}}
 	end $1
 
 snippet alff "Always flip-flop"
 	always_ff @(posedge ${1:clk}) begin ${2:: statement_label}
-		${0}
+		${3:${VISUAL}}
 	end $2
 
 snippet all "Always latch"
 	always_latch begin ${1:: statement_label}
-		${0}
+		${2:${VISUAL}}
 	end $1
 
 snippet cl "Class"
 	class ${1:class_name};
 		// data or class properties
-		${0}
+		${2:${VISUAL}}
 
 		// initialization
 		function new();
@@ -29,28 +29,28 @@ snippet cl "Class"
 
 snippet clock "Clocking group"
 	clocking ${1:clocking_name} @(${2:posedge} ${3:clk});
-		${0}
+		${4:${VISUAL}}
 	endclocking : $1
 
 snippet cg "Coverage group"
 	covergroup ${1:group_name} @(${2:posedge} ${3:clk});
-		${0}
+		${4:${VISUAL}}
 	endgroup : $1
 
 snippet dowh "Do..while loop"
 	do begin
-		${0}
+		${2:${VISUAL}}
 	end while (${1});
 
 snippet forea "Foreach loop"
 	foreach (${1}) begin
-		${0}
+		${2:${VISUAL}}
 	end
 
 snippet intf
 	interface ${1:program_name} ();
 		// nets
-		${0}
+		${2:${VISUAL}}
 		// clocking
 
 		// modports
@@ -59,17 +59,17 @@ snippet intf
 
 snippet pkg
 	package ${1:package_name};
-		${0}
+		${2:${VISUAL}}
 	endpackage : $1
 
 snippet prog
 	program ${1:program_name} ();
-		${0}
+		${2:${VISUAL}}
 	endprogram : $1
 
 snippet types "Struct typedef"
 	typedef struct {
-		${0}
+		${2:${VISUAL}}
 	} ${1:name_t};
 
 snippet uvm_component
diff --git a/snippets/verilog.snippets b/snippets/verilog.snippets
index cef3668ec..5abed2c33 100644
--- a/snippets/verilog.snippets
+++ b/snippets/verilog.snippets
@@ -1,6 +1,6 @@
 snippet al "Always block"
 	always @(${1:/* sensitive list */}) begin
-		${2}
+		${2:${VISUAL}}
 	end
 
 snippet as "Assign"
@@ -23,27 +23,27 @@ snippet case "Case(xz) statement"
 
 snippet eif "Else if"
 	else if (${1}) begin
-		${2}
+		${2:${VISUAL}}
 	end
 
 snippet el "Else"
 	else begin
-		${1}
+		${1:${VISUAL}}
 	end
 
 snippet for "For loop"
 	for (int ${2:i} = 0; $2 < ${1:count}; $2${3:++}) begin
-		${4}
+		${4:${VISUAL}}
 	end
 
 snippet forev "Forever loop"
 	forever begin
-		${1}
+		${1:${VISUAL}}
 	end
 
 snippet fun "Function"
 	function ${1:void} ${2:name}(${3});
-		${4}
+		${4:${VISUAL}}
 	endfunction: $2
 
 snippet gen "Generate block"
@@ -53,7 +53,7 @@ snippet gen "Generate block"
 
 snippet if "If statement"
 	if (${1}) begin
-		${2}
+		${2:${VISUAL}}
 	end
 
 snippet ife "If-else statement"
@@ -66,7 +66,7 @@ snippet ife "If-else statement"
 
 snippet ini "Initial block"
 	initial begin
-		${1}
+		${1:${VISUAL}}
 	end
 
 snippet lpar "Local parameter"
@@ -74,12 +74,12 @@ snippet lpar "Local parameter"
 
 snippet mod "Module"
 	module ${1:`vim_snippets#Filename('$1', 'name')`} (${2});
-		${0}
+		${0:${VISUAL}}
 	endmodule
 
 snippet modp "Module with parameters"
 	module ${1:`vim_snippets#Filename('$1', 'name')`} #(${2}) (${3});
-		${0}
+		${0:${VISUAL}}
 	endmodule
 
 snippet neg "Negative edge"
@@ -87,7 +87,7 @@ snippet neg "Negative edge"
 #
 snippet rep "Repeat loop"
 	repeat (${1}) begin
-		${2}
+		${2:${VISUAL}}
 	end
 
 snippet par "Parameter definition"
@@ -108,7 +108,7 @@ snippet seq "Sequential block"
 
 snippet task "Task definition"
 	task ${1:name}(${2});
-		${3}
+		${3:${VISUAL}}
 	endtask: $1
 
 snippet tde "Typedef enum"
@@ -124,5 +124,5 @@ snippet tdsp "Typedef struct packed"
 
 snippet wh "While loop"
 	while (${1}) begin
-		${2}
+		${2:${VISUAL}}
 	end

From 4e918c9efa115d8cbf40e6828ac57ace50c5e511 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Maciej=20Kope=C4=87?= <maciejpkopec@gmail.com>
Date: Wed, 14 Aug 2024 08:23:55 -0700
Subject: [PATCH 08/12] Remove whitespace after the snipmate-style snippets to
 avoid inserting them during expansion.

---
 snippets/systemverilog.snippets | 58 ++++++++++++++++-----------------
 snippets/verilog.snippets       | 48 +++++++++++++--------------
 2 files changed, 53 insertions(+), 53 deletions(-)

diff --git a/snippets/systemverilog.snippets b/snippets/systemverilog.snippets
index 94a315557..f15a48a09 100644
--- a/snippets/systemverilog.snippets
+++ b/snippets/systemverilog.snippets
@@ -1,21 +1,21 @@
 extends verilog
 
-
+# --------------------------------------------------------------------------------
 snippet alc "Always combinational"
 	always_comb begin ${1:: statement_label}
 		${2:${VISUAL}}
 	end $1
-
+# --------------------------------------------------------------------------------
 snippet alff "Always flip-flop"
 	always_ff @(posedge ${1:clk}) begin ${2:: statement_label}
 		${3:${VISUAL}}
 	end $2
-
+# --------------------------------------------------------------------------------
 snippet all "Always latch"
 	always_latch begin ${1:: statement_label}
 		${2:${VISUAL}}
 	end $1
-
+# --------------------------------------------------------------------------------
 snippet cl "Class"
 	class ${1:class_name};
 		// data or class properties
@@ -26,27 +26,27 @@ snippet cl "Class"
 		endfunction : new
 
 	endclass : $1
-
+# --------------------------------------------------------------------------------
 snippet clock "Clocking group"
 	clocking ${1:clocking_name} @(${2:posedge} ${3:clk});
 		${4:${VISUAL}}
 	endclocking : $1
-
+# --------------------------------------------------------------------------------
 snippet cg "Coverage group"
 	covergroup ${1:group_name} @(${2:posedge} ${3:clk});
 		${4:${VISUAL}}
 	endgroup : $1
-
+# --------------------------------------------------------------------------------
 snippet dowh "Do..while loop"
 	do begin
 		${2:${VISUAL}}
 	end while (${1});
-
+# --------------------------------------------------------------------------------
 snippet forea "Foreach loop"
 	foreach (${1}) begin
 		${2:${VISUAL}}
 	end
-
+# --------------------------------------------------------------------------------
 snippet intf
 	interface ${1:program_name} ();
 		// nets
@@ -56,22 +56,22 @@ snippet intf
 		// modports
 
 	endinterface : $1
-
+# --------------------------------------------------------------------------------
 snippet pkg
 	package ${1:package_name};
 		${2:${VISUAL}}
 	endpackage : $1
-
+# --------------------------------------------------------------------------------
 snippet prog
 	program ${1:program_name} ();
 		${2:${VISUAL}}
 	endprogram : $1
-
+# --------------------------------------------------------------------------------
 snippet types "Struct typedef"
 	typedef struct {
 		${2:${VISUAL}}
 	} ${1:name_t};
-
+# --------------------------------------------------------------------------------
 snippet uvm_component
 	//  Class: $1
 	//
@@ -99,7 +99,7 @@ snippet uvm_component
 
 		$0
 	endclass: $1
-
+# --------------------------------------------------------------------------------
 snippet uvm_component_extended
 	//  Class: $1
 	//
@@ -209,7 +209,7 @@ snippet uvm_component_extended
 	function void $1::extract_phase(uvm_phase phase);
 		super.extract_phase(phase);
 	endfunction: extract_phase
-
+# --------------------------------------------------------------------------------
 snippet uvm_component_with_parameters
 	//  Class: $1
 	//
@@ -236,7 +236,7 @@ snippet uvm_component_with_parameters
 
 		$0
 	endclass: $1
-
+# --------------------------------------------------------------------------------
 snippet uvm_object
 	//  Class: $1
 	//
@@ -257,7 +257,7 @@ snippet uvm_object
 		endfunction: new
 		$0
 	endclass: $1
-
+# --------------------------------------------------------------------------------
 snippet uvm_object_with_parameters
 	//  Class: $1
 	//
@@ -279,7 +279,7 @@ snippet uvm_object_with_parameters
 		endfunction: new
 		$0
 	endclass: $1
-
+# --------------------------------------------------------------------------------
 snippet uvm_sequence
 	//  Class: $1
 	//
@@ -347,7 +347,7 @@ snippet uvm_sequence
 		// extern virtual task post_start();
 		$0
 	endclass: $1
-
+# --------------------------------------------------------------------------------
 snippet uvm_sequence_functions
 	// task ${1:my_class::}pre_start();
 	// endtask: pre_start
@@ -380,7 +380,7 @@ snippet uvm_sequence_functions
 
 	// task $1post_start();
 	// endtask: post_start
-
+# --------------------------------------------------------------------------------
 snippet uvm_sequence_item
 	//  Class: $1
 	//
@@ -430,7 +430,7 @@ snippet uvm_sequence_item
 	/*  Functions                                                                 */
 	/*----------------------------------------------------------------------------*/
 	
-
+# --------------------------------------------------------------------------------
 snippet uvm_sequence_item_convert2string
 	function string ${1:my_class}${2:::}convert2string();
 		string s;
@@ -445,7 +445,7 @@ snippet uvm_sequence_item_convert2string
 
 		return s;
 	endfunction: convert2string$0
-
+# --------------------------------------------------------------------------------
 snippet uvm_sequence_item_do_compare
 	function bit ${1:my_class}${2:::}do_compare(uvm_object rhs, uvm_comparer comparer);
 		this_type_t rhs_;
@@ -465,7 +465,7 @@ snippet uvm_sequence_item_do_compare
 			// <this.property_name == rhs_.property_name>
 		);
 	endfunction: do_compare$0
-
+# --------------------------------------------------------------------------------
 snippet uvm_sequence_item_do_copy
 	function void ${1:my_class}${2:::}do_copy(uvm_object rhs);
 		this_type_t rhs_;
@@ -482,7 +482,7 @@ snippet uvm_sequence_item_do_copy
 		/*  list of local properties to be copied  */
 		// <this.property_name = rhs_.property_name>;
 	endfunction: do_copy$0
-
+# --------------------------------------------------------------------------------
 snippet uvm_sequence_item_do_pack
 	function void ${1:my_class}${2:::}do_pack(uvm_packer packer);
 		/*  chain the pack with parent classes  */
@@ -494,7 +494,7 @@ snippet uvm_sequence_item_do_pack
 		// \`uvm_pack_queue(property_name);
 		// \`uvm_pack_string(property_name);
 	endfunction: do_pack$0
-
+# --------------------------------------------------------------------------------
 snippet uvm_sequence_item_do_print
 	function void ${1:my_class}${2:::}do_print(uvm_printer printer)
 		/*  chain the print with parent classes  */
@@ -504,7 +504,7 @@ snippet uvm_sequence_item_do_print
 		// printer.print_string("property_label", property_name);
 		// printer.print_field_int("property_label", property_name, \$bits(property_name), UVM_HEX);
 	endfunction: do_print$0
-
+# --------------------------------------------------------------------------------
 snippet uvm_sequence_item_do_record
 	function void ${1:my_class}${2:::}do_record(uvm_recorder recorder);
 		/*  chain the record with parent classes  */
@@ -515,7 +515,7 @@ snippet uvm_sequence_item_do_record
 		// \`uvm_record_string("property_label", property_name);
 		// \`uvm_record_int("property_label", property_name, \$bits(property_name), UVM_HEX);
 	endfunction: do_record$0
-
+# --------------------------------------------------------------------------------
 snippet uvm_sequence_item_do_unpack
 	function void ${1:my_class}${2:::}do_unpack(uvm_packer packer);
 		/*  chain the unpack with parent classes  */
@@ -527,7 +527,7 @@ snippet uvm_sequence_item_do_unpack
 		// \`uvm_unpack_queue(property_name);
 		// \`uvm_unpack_string(property_name);
 	endfunction: do_unpack$0
-
+# --------------------------------------------------------------------------------
 snippet uvm_sequence_item_with_parameters
 	//  Class: $1
 	//
@@ -577,7 +577,7 @@ snippet uvm_sequence_item_with_parameters
 	/*  Functions                                                                 */
 	/*----------------------------------------------------------------------------*/
 	
-
+# --------------------------------------------------------------------------------
 snippet uvm_sequence_with_parameters
 	//  Class: $1
 	//
diff --git a/snippets/verilog.snippets b/snippets/verilog.snippets
index 5abed2c33..1514df9ca 100644
--- a/snippets/verilog.snippets
+++ b/snippets/verilog.snippets
@@ -2,15 +2,15 @@ snippet al "Always block"
 	always @(${1:/* sensitive list */}) begin
 		${2:${VISUAL}}
 	end
-
+# --------------------------------------------------------------------------------
 snippet as "Assign"
 	assign ${1:name} = ${2:value};
-
+# --------------------------------------------------------------------------------
 snippet be "Begin-end"
 	begin
 		${1:VISUAL}
 	end
-
+# --------------------------------------------------------------------------------
 snippet case "Case(xz) statement"
 	case${1:x} (${2:/* variable */})
 		${3:/* value */}: begin
@@ -20,42 +20,42 @@ snippet case "Case(xz) statement"
 			${5}
 		end
 	endcase
-
+# --------------------------------------------------------------------------------
 snippet eif "Else if"
 	else if (${1}) begin
 		${2:${VISUAL}}
 	end
-
+# --------------------------------------------------------------------------------
 snippet el "Else"
 	else begin
 		${1:${VISUAL}}
 	end
-
+# --------------------------------------------------------------------------------
 snippet for "For loop"
 	for (int ${2:i} = 0; $2 < ${1:count}; $2${3:++}) begin
 		${4:${VISUAL}}
 	end
-
+# --------------------------------------------------------------------------------
 snippet forev "Forever loop"
 	forever begin
 		${1:${VISUAL}}
 	end
-
+# --------------------------------------------------------------------------------
 snippet fun "Function"
 	function ${1:void} ${2:name}(${3});
 		${4:${VISUAL}}
 	endfunction: $2
-
+# --------------------------------------------------------------------------------
 snippet gen "Generate block"
 	generate
 		${1:${VISUAL}}
 	endgenerate
-
+# --------------------------------------------------------------------------------
 snippet if "If statement"
 	if (${1}) begin
 		${2:${VISUAL}}
 	end
-
+# --------------------------------------------------------------------------------
 snippet ife "If-else statement"
 	if (${1}) begin
 		${2}
@@ -63,39 +63,39 @@ snippet ife "If-else statement"
 	else begin
 		${3}
 	end
-
+# --------------------------------------------------------------------------------
 snippet ini "Initial block"
 	initial begin
 		${1:${VISUAL}}
 	end
-
+# --------------------------------------------------------------------------------
 snippet lpar "Local parameter"
 	localparam ${1:name} = ${0:value}
-
+# --------------------------------------------------------------------------------
 snippet mod "Module"
 	module ${1:`vim_snippets#Filename('$1', 'name')`} (${2});
 		${0:${VISUAL}}
 	endmodule
-
+# --------------------------------------------------------------------------------
 snippet modp "Module with parameters"
 	module ${1:`vim_snippets#Filename('$1', 'name')`} #(${2}) (${3});
 		${0:${VISUAL}}
 	endmodule
-
+# --------------------------------------------------------------------------------
 snippet neg "Negative edge"
 	negedge ${0:signal}
-#
+# --------------------------------------------------------------------------------
 snippet rep "Repeat loop"
 	repeat (${1}) begin
 		${2:${VISUAL}}
 	end
-
+# --------------------------------------------------------------------------------
 snippet par "Parameter definition"
 	parameter ${1:name} = ${0:value}
-
+# --------------------------------------------------------------------------------
 snippet pos "Positive edge"
 	posedge ${0:signal}
-#
+# --------------------------------------------------------------------------------
 snippet seq "Sequential block"
 	always @(${1:posedge clk}${2:, posedge rst}) begin
 		if (${3:rst}) begin
@@ -105,23 +105,23 @@ snippet seq "Sequential block"
 			${5}
 		end
 	end
-
+# --------------------------------------------------------------------------------
 snippet task "Task definition"
 	task ${1:name}(${2});
 		${3:${VISUAL}}
 	endtask: $1
-
+# --------------------------------------------------------------------------------
 snippet tde "Typedef enum"
 	typedef enum ${2:logic[15:0]}
 	{
 		${3:REG = 16'h0000}
 	} ${1:my_dest_t};
-
+# --------------------------------------------------------------------------------
 snippet tdsp "Typedef struct packed"
 	typedef struct packed {
 		int ${2:data};
 	} ${1:`vim_snippets#Filename('$1_t', 'name')`};
-
+# --------------------------------------------------------------------------------
 snippet wh "While loop"
 	while (${1}) begin
 		${2:${VISUAL}}

From 73b99ee91471582b10809c7731f2151589e747a7 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Maciej=20Kope=C4=87?= <maciejpkopec@gmail.com>
Date: Wed, 14 Aug 2024 15:42:29 -0700
Subject: [PATCH 09/12] Add instantiation snippets

---
 snippets/verilog.snippets | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/snippets/verilog.snippets b/snippets/verilog.snippets
index 1514df9ca..d2265bf2f 100644
--- a/snippets/verilog.snippets
+++ b/snippets/verilog.snippets
@@ -69,6 +69,12 @@ snippet ini "Initial block"
 		${1:${VISUAL}}
 	end
 # --------------------------------------------------------------------------------
+snippet inst "Instantiate module"
+	${1:module_name} ${2:$1}_inst (${3:IO});
+# --------------------------------------------------------------------------------
+snippet instp "Instantiate module with parameters"
+	${1:module_name} #(${2:parameters}) ${3:$1}_inst (${4:IO});
+# --------------------------------------------------------------------------------
 snippet lpar "Local parameter"
 	localparam ${1:name} = ${0:value}
 # --------------------------------------------------------------------------------

From 0066e6bf2508e8c3e689e15c31d8d2478f4c0762 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Maciej=20Kope=C4=87?= <maciejpkopec@gmail.com>
Date: Wed, 14 Aug 2024 18:08:48 -0700
Subject: [PATCH 10/12] Add conditional operator

---
 snippets/verilog.snippets | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/snippets/verilog.snippets b/snippets/verilog.snippets
index d2265bf2f..726e3e698 100644
--- a/snippets/verilog.snippets
+++ b/snippets/verilog.snippets
@@ -21,6 +21,9 @@ snippet case "Case(xz) statement"
 		end
 	endcase
 # --------------------------------------------------------------------------------
+snippet cond "Conditional operator"
+	(${1:if}) ? ${2:then} : ${3:else};
+# --------------------------------------------------------------------------------
 snippet eif "Else if"
 	else if (${1}) begin
 		${2:${VISUAL}}

From 9f7ebf913ac961391f42997782ef950734d8bab1 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Maciej=20Kope=C4=87?= <maciejpkopec@gmail.com>
Date: Wed, 14 Aug 2024 19:30:40 -0700
Subject: [PATCH 11/12] Fix VISUAL in begin-end snippet

---
 snippets/verilog.snippets | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/snippets/verilog.snippets b/snippets/verilog.snippets
index 726e3e698..9ea89f364 100644
--- a/snippets/verilog.snippets
+++ b/snippets/verilog.snippets
@@ -8,7 +8,7 @@ snippet as "Assign"
 # --------------------------------------------------------------------------------
 snippet be "Begin-end"
 	begin
-		${1:VISUAL}
+		${1:${VISUAL}}
 	end
 # --------------------------------------------------------------------------------
 snippet case "Case(xz) statement"

From e9db4f6646c718d3936b13feaaeb1e04249e4ee5 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Maciej=20Kope=C4=87?= <maciejpkopec@gmail.com>
Date: Tue, 27 Aug 2024 17:04:32 +0200
Subject: [PATCH 12/12] Add IO snippet for instantiation

---
 snippets/verilog.snippets | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/snippets/verilog.snippets b/snippets/verilog.snippets
index 9ea89f364..659fc8a72 100644
--- a/snippets/verilog.snippets
+++ b/snippets/verilog.snippets
@@ -1,3 +1,6 @@
+snippet . "IO when instantiating the module"
+	.${1:io_name}(${2:$1})
+# --------------------------------------------------------------------------------
 snippet al "Always block"
 	always @(${1:/* sensitive list */}) begin
 		${2:${VISUAL}}
@@ -73,10 +76,10 @@ snippet ini "Initial block"
 	end
 # --------------------------------------------------------------------------------
 snippet inst "Instantiate module"
-	${1:module_name} ${2:$1}_inst (${3:IO});
+	${1:module_name} ${2:$1}_inst (${3:.*});
 # --------------------------------------------------------------------------------
 snippet instp "Instantiate module with parameters"
-	${1:module_name} #(${2:parameters}) ${3:$1}_inst (${4:IO});
+	${1:module_name} #(${2:parameters}) ${3:$1}_inst (${4:.*});
 # --------------------------------------------------------------------------------
 snippet lpar "Local parameter"
 	localparam ${1:name} = ${0:value}