Merge pull request hdl#321 from abrisco/verilator

Cleanup legacy uses of `@bazel_tools`

Author: QuantamHD

README.md

@@ -68,7 +68,7 @@ to build. The rules use yosys and OpenROAD to place and route your design.
 ```python
 load("@rules_hdl//synthesis:build_defs.bzl", "synthesize_rtl")
 load("@rules_hdl//place_and_route:build_defs.bzl", "place_and_route")
-load("@rules_hdl//verilog:providers.bzl", "verilog_library")
+load("@rules_hdl//verilog:defs.bzl", "verilog_library")
 
 place_and_route(
     name = "counter_place_and_route",

cocotb/BUILD renamed to cocotb/BUILD.bazel

@@ -15,7 +15,7 @@
 """Rules for running tests using Cocotb framework"""
 
 load("@rules_python//python:defs.bzl", "PyInfo")
-load("//verilog:providers.bzl", "VerilogInfo")
+load("//verilog:defs.bzl", "VerilogInfo")
 
 ## Helpers for parsing arguments
 
@@ -83,7 +83,7 @@ def _collect_python_direct_imports(ctx):
     return depset(direct = [module.dirname for module in ctx.files.test_module])
 
 def _collect_transitive_files(ctx):
-    py_toolchain = ctx.toolchains["@bazel_tools//tools/python:toolchain_type"].py3_runtime
+    py_toolchain = ctx.toolchains["@rules_python//python:toolchain_type"].py3_runtime
     return depset(
         direct = [py_toolchain.interpreter],
         transitive = [dep[PyInfo].transitive_sources for dep in ctx.attr.deps] +
@@ -132,7 +132,7 @@ def _get_test_command(ctx, verilog_files, vhdl_files):
     seed_args = " --seed {}".format(ctx.attr.seed) if ctx.attr.seed != "" else ""
 
     test_module_args = _pymodules_to_argstring(ctx.files.test_module, "test_module")
-    python_interpreter = ctx.toolchains["@bazel_tools//tools/python:toolchain_type"].py3_runtime.interpreter.path
+    python_interpreter = ctx.toolchains["@rules_python//python:toolchain_type"].py3_runtime.interpreter.path
 
     command = (
         "PATH={}:$PATH ".format(_get_path_to_set(ctx)) +
@@ -297,6 +297,6 @@ _cocotb_test_attrs = {
 cocotb_test = rule(
     implementation = _cocotb_test_impl,
     attrs = _cocotb_test_attrs,
-    toolchains = ["@bazel_tools//tools/python:toolchain_type"],
+    toolchains = ["@rules_python//python:toolchain_type"],
     test = True,
 )

cocotb/cocotb.bzl

@@ -14,7 +14,7 @@
 
 load("@rules_hdl_pip_deps//:requirements.bzl", "requirement")
 load("//cocotb:cocotb.bzl", "cocotb_test")
-load("//verilog:providers.bzl", "verilog_library")
+load("//verilog:defs.bzl", "verilog_library")
 
 package(
     default_applicable_licenses = ["//:package_license"],

cocotb/tests/BUILD renamed to cocotb/tests/BUILD.bazel

@@ -14,15 +14,15 @@ exports_files(["COPYING"])
 cc_library(
     name = "config_h",
     hdrs = select({
-        "@bazel_tools//src/conditions:darwin": [
+        "@platforms//os:macos": [
             "config-darwin/config.h",
         ],
         "//conditions:default": [
             "config-linux/config.h",
         ],
     }),
     includes = select({
-        "@bazel_tools//src/conditions:darwin": [
+        "@platforms//os:macos": [
             "config-darwin",
         ],
         "//conditions:default": [
@@ -146,7 +146,7 @@ cc_library(
     # https://github.com/bazelbuild/bazel/issues/3828
     # https://github.com/bazelbuild/bazel/issues/6337
     srcs = _GNULIB_SRCS + _GNULIB_HDRS + select({
-        "@bazel_tools//src/conditions:darwin": _GNULIB_DARWIN_SRCS,
+        "@platforms//os:macos": _GNULIB_DARWIN_SRCS,
         "//conditions:default": _GNULIB_LINUX_SRCS,
     }),
     hdrs = _GNULIB_HDRS,

dependency_support/org_gnu_gnulib/bundled.BUILD.bazel

@@ -15,7 +15,7 @@
 """Rules for synthesizing (System)Verilog code."""
 
 load("@rules_hdl//pdk:build_defs.bzl", "StandardCellInfo")
-load("//verilog:providers.bzl", "VerilogInfo")
+load("//verilog:defs.bzl", "VerilogInfo")
 
 # There are no rules to generate this provider, but it does provide the mechansim to build
 # rules based on surelog in the open source world.

synthesis/build_defs.bzl

@@ -20,7 +20,7 @@ load("//gds_write:build_defs.bzl", "gds_write")
 load("//place_and_route:build_defs.bzl", "place_and_route")
 load("//static_timing:build_defs.bzl", "run_opensta")
 load("//synthesis:build_defs.bzl", "synthesize_rtl")
-load("//verilog:providers.bzl", "verilog_library")
+load("//verilog:defs.bzl", "verilog_library")
 
 package(
     default_applicable_licenses = ["//:package_license"],

tests/BUILD

@@ -17,7 +17,7 @@
 
 load("@bazel_tools//tools/cpp:toolchain_utils.bzl", "find_cpp_toolchain")
 load("@rules_cc//cc:defs.bzl", "CcInfo")
-load("//verilog:providers.bzl", "VerilogInfo")
+load("//verilog:defs.bzl", "VerilogInfo")
 
 def cc_compile_and_link_static_library(ctx, srcs, hdrs, deps, runfiles, includes = [], defines = []):
     """Compile and link C++ source into a static library

verilator/defs.bzl

@@ -14,7 +14,7 @@
 
 load("@rules_cc//cc:defs.bzl", "cc_test")
 load("//verilator:defs.bzl", "verilator_cc_library")
-load("//verilog:providers.bzl", "verilog_library")
+load("//verilog:defs.bzl", "verilog_library")
 
 package(
     default_applicable_licenses = ["//:package_license"],

verilator/tests/BUILD

@@ -0,0 +1,10 @@
+"""verilog rules"""
+
+load(
+    ":providers.bzl",
+    _VerilogInfo = "VerilogInfo",
+    _verilog_library = "verilog_library",
+)
+
+VerilogInfo = _VerilogInfo
+verilog_library = _verilog_library

verilog/BUILD renamed to verilog/BUILD.bazel

@@ -78,7 +78,7 @@ def make_verilog_info(
         ),
     )
 
-def _produce_dag_impl(ctx):
+def _verilog_library_impl(ctx):
     """Produces a DAG for the given verilog_X target.
 
     Args:
@@ -103,12 +103,22 @@ def _produce_dag_impl(ctx):
     ]
 
 verilog_library = rule(
+    doc = "Define a Verilog module.",
+    implementation = _verilog_library_impl,
     attrs = {
-        "deps": attr.label_list(providers = [
-            VerilogInfo,
-        ]),
-        "hdrs": attr.label_list(allow_files = True),
-        "srcs": attr.label_list(allow_files = True),
+        "deps": attr.label_list(
+            doc = "The list of other libraries to be linked.",
+            providers = [
+                VerilogInfo,
+            ],
+        ),
+        "hdrs": attr.label_list(
+            doc = "Verilog or SystemVerilog headers.",
+            allow_files = True,
+        ),
+        "srcs": attr.label_list(
+            doc = "Verilog or SystemVerilog sources.",
+            allow_files = True,
+        ),
     },
-    implementation = _produce_dag_impl,
 )

verilog/defs.bzl

@@ -1,6 +1,6 @@
 """Defines rules for the Xilinx tool, vivado."""
 
-load("//verilog:providers.bzl", "VerilogInfo")
+load("//verilog:defs.bzl", "VerilogInfo")
 load("//vivado:providers.bzl", "VivadoIPBlockInfo", "VivadoPlacementCheckpointInfo", "VivadoRoutingCheckpointInfo", "VivadoSynthCheckpointInfo")
 
 def run_tcl_template(ctx, template, substitutions, xilinx_env, input_files, output_files, post_processing_command = ""):

verilog/providers.bzl

@@ -15,7 +15,7 @@
 load("@rules_cc//cc:defs.bzl", "cc_test")
 load("@rules_python//python:defs.bzl", "py_binary")
 load("//verilator:defs.bzl", "verilator_cc_library")
-load("//verilog:providers.bzl", "verilog_library")
+load("//verilog:defs.bzl", "verilog_library")
 load(
     "//vivado:defs.bzl",
     "vivado_create_ip",