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"""Floorplaning openROAD commands"""
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load ("@rules_hdl//pdk:open_road_configuration.bzl" , "get_open_road_configuration" )
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- load ("//place_and_route:open_road.bzl" , "OpenRoadInfo" , "openroad_command" )
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+ load ("//place_and_route:open_road.bzl" , "OpenRoadInfo" , "openroad_command" , "timing_setup_commands" )
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load ("//place_and_route:private/report_area.bzl" , "generate_area_results" )
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load ("//place_and_route:private/report_power.bzl" , "generate_power_results" )
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load ("//synthesis:build_defs.bzl" , "SynthesisInfo" )
@@ -73,6 +73,10 @@ def init_floor_plan(ctx):
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tieoneport = open_road_configuration .tie_high_port
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tiezeroport = open_road_configuration .tie_low_port
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+ timing_setup_command_struct = timing_setup_commands (ctx )
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+
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+ input_open_road_files = timing_setup_command_struct .inputs
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+
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open_road_commands = [
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"read_lef {tech_lef}" .format (
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tech_lef = tech_lef .path ,
@@ -89,6 +93,9 @@ def init_floor_plan(ctx):
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"link_design {top_module}" .format (
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top_module = top_module ,
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),
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+ ])
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+ open_road_commands .extend (timing_setup_command_struct .commands )
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+ open_road_commands .extend ([
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_initialize_floorplan_command (ctx ),
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"source {tracks_file}" .format (
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tracks_file = open_road_configuration .tracks_file .path ,
@@ -104,12 +111,14 @@ def init_floor_plan(ctx):
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open_road_commands .extend (generate_power_results (ctx , verilog_based_power_results ))
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open_road_commands .extend (generate_area_results (verilog_based_area_results ))
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- input_open_road_files = [
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+ input_open_road_files . extend ( [
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netlist ,
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liberty ,
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tech_lef ,
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open_road_configuration .tracks_file ,
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- ] + std_cell_lef + additional_liberties
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+ ])
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+ input_open_road_files .extend (std_cell_lef )
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+ input_open_road_files .extend (additional_liberties )
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command_output = openroad_command (
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ctx ,
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