Merge branch '2022-07-05-more-Kconfig-migrations' into next

- Migrate more CONFIG symbols to Kconfig, remove some dead code and
  clean-up arch/Kconfig.nxp slightly more.

Author: trini

README

@@ -388,10 +388,6 @@ The following options need to be configured:
 		CONFIG_SYS_FSL_DDR_ADDR
 		Freescale DDR memory-mapped register base.
 
-		CONFIG_SYS_FSL_DDR_EMU
-		Specify emulator support for DDR. Some DDR features such as
-		deskew training are not available.
-
 		CONFIG_SYS_FSL_DDRC_GEN1
 		Freescale DDR1 controller.
 
@@ -1306,11 +1302,6 @@ The following options need to be configured:
 
 		will skip addresses 0x50 and 0x68 on bus 0 and address 0x54 on bus 1
 
-		CONFIG_SYS_SPD_BUS_NUM
-
-		If defined, then this indicates the I2C bus number for DDR SPD.
-		If not defined, then U-Boot assumes that SPD is on I2C bus 0.
-
 		CONFIG_SYS_RTC_BUS_NUM
 
 		If defined, then this indicates the I2C bus number for the RTC.
@@ -1518,20 +1509,6 @@ The following options need to be configured:
 		overwriting the architecture dependent default
 		settings.
 
-- Frame Buffer Address:
-		CONFIG_FB_ADDR
-
-		Define CONFIG_FB_ADDR if you want to use specific
-		address for frame buffer.  This is typically the case
-		when using a graphics controller has separate video
-		memory.  U-Boot will then place the frame buffer at
-		the given address instead of dynamically reserving it
-		in system RAM by calling lcd_setmem(), which grabs
-		the memory for the frame buffer depending on the
-		configured panel size.
-
-		Please see board_init_f function.
-
 - Automatic software updates via TFTP server
 		CONFIG_UPDATE_TFTP
 		CONFIG_UPDATE_TFTP_CNT_MAX
@@ -2088,12 +2065,6 @@ Low Level (hardware related) configuration options:
 		one, specify here. Note that the value must resolve
 		to something your driver can deal with.
 
-- CONFIG_SYS_DDR_RAW_TIMING
-		Get DDR timing information from other than SPD. Common with
-		soldered DDR chips onboard without SPD. DDR raw timing
-		parameters are extracted from datasheet and hard-coded into
-		header files or board specific files.
-
 - CONFIG_FSL_DDR_INTERACTIVE
 		Enable interactive DDR debugging. See doc/README.fsl-ddr.
 

arch/Kconfig

@@ -451,6 +451,12 @@ source "arch/x86/Kconfig"
 source "arch/xtensa/Kconfig"
 source "arch/riscv/Kconfig"
 
+if ARM || M68K || PPC
+
+source "arch/Kconfig.nxp"
+
+endif
+
 source "board/keymile/Kconfig"
 
 if MIPS || MICROBLAZE

arch/Kconfig.nxp

@@ -0,0 +1,240 @@
+config NXP_ESBC
+	bool "NXP ESBC (secure boot) functionality"
+	help
+	  Enable Freescale Secure Boot feature. Normally selected by defconfig.
+	  If unsure, do not change.
+
+menu "Chain of trust / secure boot options"
+	depends on !FIT_SIGNATURE && NXP_ESBC
+
+config CHAIN_OF_TRUST
+	select FSL_CAAM
+	select ARCH_MISC_INIT
+	select FSL_SEC_MON
+	select SPL_BOARD_INIT if (ARM && SPL)
+	select SPL_HASH if (ARM && SPL)
+	select SHA_HW_ACCEL
+	select SHA_PROG_HW_ACCEL
+	select ENV_IS_NOWHERE
+	select CMD_EXT4 if ARM
+	select CMD_EXT4_WRITE if ARM
+	imply CMD_BLOB
+	imply CMD_HASH if ARM
+	def_bool y
+
+config CMD_ESBC_VALIDATE
+	bool "Enable the 'esbc_validate' and 'esbc_halt' commands"
+	default y
+	help
+	  This option enables two commands used for secure booting:
+
+	    esbc_validate - validate signature using RSA verification
+	    esbc_halt - put the core in spin loop (Secure Boot Only)
+
+config ESBC_HDR_LS
+	bool
+
+config ESBC_ADDR_64BIT
+	def_bool y
+	depends on ESBC_HDR_LS && FSL_LAYERSCAPE
+	help
+	  For Layerscape based platforms, ESBC image Address in Header is 64bit.
+
+config SYS_FSL_SFP_BE
+	def_bool y
+	depends on PPC || FSL_LSCH2 || ARCH_LS1021A
+
+config SYS_FSL_SFP_LE
+	def_bool y
+	depends on !SYS_FSL_SFP_BE
+
+choice
+	prompt "SFP IP revision"
+	default SYS_FSL_SFP_VER_3_0 if PPC
+	default SYS_FSL_SFP_VER_3_4
+
+config SYS_FSL_SFP_VER_3_0
+	bool "SFP version 3.0"
+
+config SYS_FSL_SFP_VER_3_2
+	bool "SFP version 3.2"
+
+config SYS_FSL_SFP_VER_3_4
+	bool "SFP version 3.4"
+
+endchoice
+
+config SPL_UBOOT_KEY_HASH
+	string "Non-SRK key hash for U-Boot public/private key pair"
+	depends on SPL
+	default ""
+	help
+	  Set the key hash for U-Boot here if public/private key pair used to
+	  sign U-boot are different from the SRK hash put in the fuse.  Example
+	  of a key hash is
+	  41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b.
+	  Otherwise leave this empty.
+
+if PPC
+
+config BOOTSCRIPT_COPY_RAM
+	bool "Secure boot copies boot script to RAM"
+	help
+	  On systems that support chain of trust booting, a number of addresses
+	  are required to set variables that are used in the copying and then
+	  verification of different parts of the system.  If enabled, the subsequent
+	  options are for what location to use in each step.
+
+config BS_ADDR_DEVICE
+	hex "Address in RAM for bs_device"
+	depends on BOOTSCRIPT_COPY_RAM
+
+config BS_SIZE
+	hex "The size of bs_size which is the amount read from bs_device"
+	depends on BOOTSCRIPT_COPY_RAM
+
+config BS_ADDR_RAM
+	hex "Address in RAM for bs_ram"
+	depends on BOOTSCRIPT_COPY_RAM
+
+config BS_HDR_ADDR_DEVICE
+	hex "Address in RAM for bs_hdr_device"
+	depends on BOOTSCRIPT_COPY_RAM
+
+config BS_HDR_SIZE
+	hex "The size of bs_hdr_size which is the amount read from bs_hdr_device"
+	depends on BOOTSCRIPT_COPY_RAM
+
+config BS_HDR_ADDR_RAM
+	hex "Address in RAM for bs_hdr_ram"
+	depends on BOOTSCRIPT_COPY_RAM
+
+config BOOTSCRIPT_HDR_ADDR
+	hex "CONFIG_BOOTSCRIPT_HDR_ADDR"
+	default BS_ADDR_RAM if BOOTSCRIPT_COPY_RAM
+
+endif
+
+config SYS_FSL_SRK_LE
+	def_bool y
+	depends on ARM
+
+config KEY_REVOCATION
+	def_bool y
+
+endmenu
+
+comment "Other functionality shared between NXP SoCs"
+
+config DEEP_SLEEP
+	bool "Enable SoC deep sleep feature"
+	depends on ARCH_T1024 || ARCH_T1040 || ARCH_T1042 || ARCH_LS1021A
+	default y
+	help
+	  Indicates this SoC supports deep sleep feature. If deep sleep is
+	  supported, core will start to execute uboot when wakes up.
+
+config LAYERSCAPE_NS_ACCESS
+	bool "Layerscape non-secure access support"
+	depends on ARCH_LS1021A || FSL_LSCH2
+
+config PCIE1
+	bool "PCIe controller #1"
+	depends on LAYERSCAPE_NS_ACCESS || PPC
+
+config PCIE2
+	bool "PCIe controller #2"
+	depends on LAYERSCAPE_NS_ACCESS || PPC
+
+config PCIE3
+	bool "PCIe controller #3"
+	depends on LAYERSCAPE_NS_ACCESS || PPC
+
+config PCIE4
+	bool "PCIe controller #4"
+	depends on LAYERSCAPE_NS_ACCESS || PPC
+
+config FSL_USE_PCA9547_MUX
+	bool "Enable PCA9547 I2C Mux on Freescale boards"
+	depends on PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3
+	help
+	 This option enables the PCA9547 I2C mux on Freescale boards.
+
+config VID
+	bool "Enable Freescale VID"
+	depends on (PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3) && (I2C || DM_I2C)
+	help
+	 This option enables setting core voltage based on individual
+	 values saved in SoC fuses.
+
+config SPL_VID
+	bool "Enable Freescale VID in SPL"
+	depends on (PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3) && (SPL_I2C || DM_SPL_I2C)
+	help
+	 This option enables setting core voltage based on individual
+	 values saved in SoC fuses, in SPL.
+
+if VID || SPL_VID
+
+config VID_FLS_ENV
+	string "Environment variable for overriding VDD"
+	help
+	  This option allows for specifying the environment variable
+	  to check to override VDD information.
+
+config VOL_MONITOR_INA220
+	bool "Enable the INA220 voltage monitor read"
+	help
+	  This option enables INA220 voltage monitor read
+	  functionality. It is used by the common VID driver.
+
+config VOL_MONITOR_IR36021_READ
+	bool "Enable the IR36021 voltage monitor read"
+	help
+	 This option enables IR36021 voltage monitor read
+	 functionality. It is used by the common VID driver.
+
+config VOL_MONITOR_IR36021_SET
+	bool "Enable the IR36021 voltage monitor set"
+	help
+	 This option enables IR36021 voltage monitor set
+	 functionality. It is used by the common VID driver.
+
+config VOL_MONITOR_LTC3882_READ
+	bool "Enable the LTC3882 voltage monitor read"
+	help
+	 This option enables LTC3882 voltage monitor read
+	 functionality. It is used by the common VID driver.
+
+config VOL_MONITOR_LTC3882_SET
+	bool "Enable the LTC3882 voltage monitor set"
+	help
+	 This option enables LTC3882 voltage monitor set
+	 functionality. It is used by the common VID driver.
+
+config VOL_MONITOR_ISL68233_READ
+	bool "Enable the ISL68233 voltage monitor read"
+	help
+	 This option enables ISL68233 voltage monitor read
+	 functionality. It is used by the common VID driver.
+
+config VOL_MONITOR_ISL68233_SET
+	bool "Enable the ISL68233 voltage monitor set"
+	help
+	 This option enables ISL68233 voltage monitor set
+	 functionality. It is used by the common VID driver.
+
+endif
+
+config FSL_QIXIS
+	bool "Enable QIXIS support"
+	depends on PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3
+
+config QIXIS_I2C_ACCESS
+	bool "Access to QIXIS is over i2c"
+	depends on FSL_QIXIS
+	default y
+
+config HAS_FSL_DR_USB
+	def_bool y
+	depends on USB_EHCI_HCD && PPC

arch/arm/cpu/armv7/ls102xa/Kconfig

@@ -41,12 +41,6 @@ config MAX_CPUS
 	  cores, count the reserved ports. This will allocate enough memory
 	  in spin table to properly handle all cores.
 
-config NXP_ESBC
-	bool	"NXP_ESBC"
-	help
-		Enable Freescale Secure Boot feature. Normally selected
-		by defconfig. If unsure, do not change.
-
 config SYS_CCI400_OFFSET
 	hex "Offset for CCI400 base"
 	depends on SYS_FSL_HAS_CCI400

arch/arm/cpu/armv7/s5p-common/Makefile

@@ -3,14 +3,13 @@
 # Copyright (C) 2009 Samsung Electronics
 # Minkyu Kang <[email protected]>
 
+obj-$(CONFIG_PWM_S5P) += pwm.o
 ifdef CONFIG_ARCH_NEXELL
-obj-$(CONFIG_PWM_NX) += pwm.o
 obj-$(CONFIG_S5P4418_ONEWIRE) += pwm.o
 else
 obj-y += cpu_info.o
 ifndef CONFIG_SPL_BUILD
 obj-y += timer.o
 obj-y += sromc.o
-obj-$(CONFIG_PWM) += pwm.o
 endif
 endif