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trinitrini
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Merge branch 'master' into next
Merge in v2022.07-rc5.
2 parents 78533a1 + 568a226 commit 52af010

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‎.gitignore

+2
Original file line numberDiff line numberDiff line change
@@ -10,6 +10,7 @@
1010
*.asn1.[ch]
1111
*.bin
1212
*.cfgout
13+
*.cover
1314
*.dtb
1415
*.dtbo
1516
*.dtb.S
@@ -22,6 +23,7 @@
2223
*.lex.c
2324
*.lst
2425
*.mod.c
26+
*.mbx
2527
*.o
2628
*.o.*
2729
*.order

‎Makefile

+1-1
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@
33
VERSION = 2022
44
PATCHLEVEL = 07
55
SUBLEVEL =
6-
EXTRAVERSION = -rc4
6+
EXTRAVERSION = -rc5
77
NAME =
88

99
# *DOCUMENTATION*

‎arch/arm/cpu/armv8/cache_v8.c

+24-4
Original file line numberDiff line numberDiff line change
@@ -39,8 +39,28 @@ DECLARE_GLOBAL_DATA_PTR;
3939
* off: FFF
4040
*/
4141

42-
u64 get_tcr(int el, u64 *pips, u64 *pva_bits)
42+
static int get_effective_el(void)
4343
{
44+
int el = current_el();
45+
46+
if (el == 2) {
47+
u64 hcr_el2;
48+
49+
/*
50+
* If we are using the EL2&0 translation regime, the TCR_EL2
51+
* looks like the EL1 version, even though we are in EL2.
52+
*/
53+
__asm__ ("mrs %0, HCR_EL2\n" : "=r" (hcr_el2));
54+
if (hcr_el2 & BIT(HCR_EL2_E2H_BIT))
55+
return 1;
56+
}
57+
58+
return el;
59+
}
60+
61+
u64 get_tcr(u64 *pips, u64 *pva_bits)
62+
{
63+
int el = get_effective_el();
4464
u64 max_addr = 0;
4565
u64 ips, va_bits;
4666
u64 tcr;
@@ -115,7 +135,7 @@ static u64 *find_pte(u64 addr, int level)
115135

116136
debug("addr=%llx level=%d\n", addr, level);
117137

118-
get_tcr(0, NULL, &va_bits);
138+
get_tcr(NULL, &va_bits);
119139
if (va_bits < 39)
120140
start_level = 1;
121141

@@ -343,7 +363,7 @@ __weak u64 get_page_table_size(void)
343363
u64 va_bits;
344364
int start_level = 0;
345365

346-
get_tcr(0, NULL, &va_bits);
366+
get_tcr(NULL, &va_bits);
347367
if (va_bits < 39)
348368
start_level = 1;
349369

@@ -415,7 +435,7 @@ __weak void mmu_setup(void)
415435
setup_all_pgtables();
416436

417437
el = current_el();
418-
set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL),
438+
set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(NULL, NULL),
419439
MEMORY_ATTRIBUTES);
420440

421441
/* enable the mmu */

‎arch/arm/cpu/armv8/fsl-layerscape/cpu.c

+2-2
Original file line numberDiff line numberDiff line change
@@ -454,7 +454,7 @@ static inline void early_mmu_setup(void)
454454

455455
/* point TTBR to the new table */
456456
set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
457-
get_tcr(el, NULL, NULL) &
457+
get_tcr(NULL, NULL) &
458458
~(TCR_ORGN_MASK | TCR_IRGN_MASK),
459459
MEMORY_ATTRIBUTES);
460460

@@ -609,7 +609,7 @@ static inline void final_mmu_setup(void)
609609
invalidate_icache_all();
610610

611611
/* point TTBR to the new table */
612-
set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL),
612+
set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(NULL, NULL),
613613
MEMORY_ATTRIBUTES);
614614

615615
set_sctlr(get_sctlr() | CR_M);

‎arch/arm/cpu/armv8/start.S

+1-1
Original file line numberDiff line numberDiff line change
@@ -125,7 +125,7 @@ pie_fixup_done:
125125
msr cptr_el3, xzr /* Enable FP/SIMD */
126126
b 0f
127127
2: mrs x1, hcr_el2
128-
tbnz x1, #34, 1f /* HCR_EL2.E2H */
128+
tbnz x1, #HCR_EL2_E2H_BIT, 1f /* HCR_EL2.E2H */
129129
orr x1, x1, #HCR_EL2_AMO_EL2 /* Route SErrors to EL2 */
130130
msr hcr_el2, x1
131131
set_vbar vbar_el2, x0

‎arch/arm/dts/Makefile

+2-1
Original file line numberDiff line numberDiff line change
@@ -1178,7 +1178,8 @@ dtb-$(CONFIG_STM32MP15x) += \
11781178
stm32mp15xx-dhcom-drc02.dtb \
11791179
stm32mp15xx-dhcom-pdk2.dtb \
11801180
stm32mp15xx-dhcom-picoitx.dtb \
1181-
stm32mp15xx-dhcor-avenger96.dtb
1181+
stm32mp15xx-dhcor-avenger96.dtb \
1182+
stm32mp15xx-dhcor-drc-compact.dtb
11821183

11831184
dtb-$(CONFIG_SOC_K3_AM6) += \
11841185
k3-am654-base-board.dtb \

‎arch/arm/dts/imx6qdl-sr-som.dtsi

+15-2
Original file line numberDiff line numberDiff line change
@@ -55,7 +55,13 @@
5555
pinctrl-0 = <&pinctrl_microsom_enet_ar8035>;
5656
phy-handle = <&phy>;
5757
phy-mode = "rgmii-id";
58-
phy-reset-duration = <2>;
58+
59+
/*
60+
* The PHY seems to require a long-enough reset duration to avoid
61+
* some rare issues where the PHY gets stuck in an inconsistent and
62+
* non-functional state at boot-up. 10ms proved to be fine .
63+
*/
64+
phy-reset-duration = <10>;
5965
phy-reset-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
6066
status = "okay";
6167

@@ -64,8 +70,15 @@
6470
#size-cells = <0>;
6571

6672
phy: ethernet-phy@0 {
67-
reg = <0>;
73+
/*
74+
* The PHY can appear either:
75+
* - AR8035: at address 0 or 4
76+
* - ADIN1300: at address 1
77+
* Actual address being detected at runtime.
78+
*/
79+
reg = <0xffffffff>;
6880
qca,clk-out-frequency = <125000000>;
81+
adi,phy-output-clock = "125mhz-free-running";
6982
};
7083
};
7184
};

‎arch/arm/dts/imx8mn-evk-u-boot.dtsi

+3-1
Original file line numberDiff line numberDiff line change
@@ -58,7 +58,9 @@
5858
};
5959

6060

61-
flash {
61+
spl {
62+
filename = "spl.bin";
63+
6264
mkimage {
6365
args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x912000";
6466

‎arch/arm/dts/imx8mq-kontron-pitx-imx8m-u-boot.dtsi

+15
Original file line numberDiff line numberDiff line change
@@ -10,3 +10,18 @@
1010
sd-uhs-sdr104;
1111
sd-uhs-ddr50;
1212
};
13+
14+
&uart1 {
15+
/delete-property/ assigned-clocks;
16+
/delete-property/ assigned-clock-parents;
17+
};
18+
19+
&uart2 {
20+
/delete-property/ assigned-clocks;
21+
/delete-property/ assigned-clock-parents;
22+
};
23+
24+
&uart3 {
25+
/delete-property/ assigned-clocks;
26+
/delete-property/ assigned-clock-parents;
27+
};

‎arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi

+10-1
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22
/*
33
* U-Boot additions
44
*
5-
* Copyright (C) 2019 Intel Corporation <www.intel.com>
5+
* Copyright (C) 2019-2022 Intel Corporation <www.intel.com>
66
*/
77

88
#include "socfpga_agilex-u-boot.dtsi"
@@ -11,6 +11,15 @@
1111
aliases {
1212
spi0 = &qspi;
1313
i2c0 = &i2c1;
14+
freeze_br0 = &freeze_controller;
15+
};
16+
17+
soc {
18+
freeze_controller: freeze_controller@f9000450 {
19+
compatible = "altr,freeze-bridge-controller";
20+
reg = <0xf9000450 0x00000010>;
21+
status = "disabled";
22+
};
1423
};
1524

1625
memory {

‎arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi

+10-1
Original file line numberDiff line numberDiff line change
@@ -2,14 +2,23 @@
22
/*
33
* U-Boot additions
44
*
5-
* Copyright (C) 2019-2020 Intel Corporation <www.intel.com>
5+
* Copyright (C) 2019-2022 Intel Corporation <www.intel.com>
66
*/
77

88
#include "socfpga_stratix10-u-boot.dtsi"
99

1010
/{
1111
aliases {
1212
spi0 = &qspi;
13+
freeze_br0 = &freeze_controller;
14+
};
15+
16+
soc {
17+
freeze_controller: freeze_controller@f9000450 {
18+
compatible = "altr,freeze-bridge-controller";
19+
reg = <0xf9000450 0x00000010>;
20+
status = "disabled";
21+
};
1322
};
1423
};
1524

‎arch/arm/dts/socfpga_stratix10_socdk.dts

+1-1
Original file line numberDiff line numberDiff line change
@@ -92,7 +92,7 @@
9292
broken-cd;
9393
bus-width = <4>;
9494
drvsel = <3>;
95-
smplsel = <0>;
95+
smplsel = <2>;
9696
};
9797

9898
&qspi {

‎arch/arm/dts/stm32mp15-pinctrl.dtsi

+119
Original file line numberDiff line numberDiff line change
@@ -929,6 +929,26 @@
929929
};
930930
};
931931

932+
m_can1_pins_c: m-can1-2 {
933+
pins1 {
934+
pinmux = <STM32_PINMUX('H', 13, AF9)>; /* CAN1_TX */
935+
slew-rate = <1>;
936+
drive-push-pull;
937+
bias-disable;
938+
};
939+
pins2 {
940+
pinmux = <STM32_PINMUX('H', 14, AF9)>; /* CAN1_RX */
941+
bias-disable;
942+
};
943+
};
944+
945+
m_can1_sleep_pins_c: m_can1-sleep-2 {
946+
pins {
947+
pinmux = <STM32_PINMUX('H', 13, ANALOG)>, /* CAN1_TX */
948+
<STM32_PINMUX('H', 14, ANALOG)>; /* CAN1_RX */
949+
};
950+
};
951+
932952
m_can2_pins_a: m-can2-0 {
933953
pins1 {
934954
pinmux = <STM32_PINMUX('B', 13, AF9)>; /* CAN2_TX */
@@ -1758,6 +1778,21 @@
17581778
};
17591779
};
17601780

1781+
spi2_pins_b: spi2-1 {
1782+
pins1 {
1783+
pinmux = <STM32_PINMUX('I', 1, AF5)>, /* SPI1_SCK */
1784+
<STM32_PINMUX('I', 3, AF5)>; /* SPI1_MOSI */
1785+
bias-disable;
1786+
drive-push-pull;
1787+
slew-rate = <1>;
1788+
};
1789+
1790+
pins2 {
1791+
pinmux = <STM32_PINMUX('I', 2, AF5)>; /* SPI1_MISO */
1792+
bias-disable;
1793+
};
1794+
};
1795+
17611796
spi4_pins_a: spi4-0 {
17621797
pins {
17631798
pinmux = <STM32_PINMUX('E', 12, AF5)>, /* SPI4_SCK */
@@ -1835,6 +1870,49 @@
18351870
};
18361871
};
18371872

1873+
uart4_pins_d: uart4-3 {
1874+
pins1 {
1875+
pinmux = <STM32_PINMUX('A', 13, AF8)>; /* UART4_TX */
1876+
bias-disable;
1877+
drive-push-pull;
1878+
slew-rate = <0>;
1879+
};
1880+
pins2 {
1881+
pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
1882+
bias-disable;
1883+
};
1884+
};
1885+
1886+
uart4_idle_pins_d: uart4-idle-3 {
1887+
pins1 {
1888+
pinmux = <STM32_PINMUX('A', 13, ANALOG)>; /* UART4_TX */
1889+
};
1890+
pins2 {
1891+
pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
1892+
bias-disable;
1893+
};
1894+
};
1895+
1896+
uart4_sleep_pins_d: uart4-sleep-3 {
1897+
pins {
1898+
pinmux = <STM32_PINMUX('A', 13, ANALOG)>, /* UART4_TX */
1899+
<STM32_PINMUX('B', 2, ANALOG)>; /* UART4_RX */
1900+
};
1901+
};
1902+
1903+
uart5_pins_a: uart5-0 {
1904+
pins1 {
1905+
pinmux = <STM32_PINMUX('B', 13, AF14)>; /* UART5_TX */
1906+
bias-disable;
1907+
drive-push-pull;
1908+
slew-rate = <0>;
1909+
};
1910+
pins2 {
1911+
pinmux = <STM32_PINMUX('B', 5, AF12)>; /* UART5_RX */
1912+
bias-disable;
1913+
};
1914+
};
1915+
18381916
uart7_pins_a: uart7-0 {
18391917
pins1 {
18401918
pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART7_TX */
@@ -2134,6 +2212,47 @@
21342212
};
21352213
};
21362214

2215+
usart3_pins_e: usart3-4 {
2216+
pins1 {
2217+
pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
2218+
<STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */
2219+
bias-disable;
2220+
drive-push-pull;
2221+
slew-rate = <0>;
2222+
};
2223+
pins2 {
2224+
pinmux = <STM32_PINMUX('B', 11, AF7)>, /* USART3_RX */
2225+
<STM32_PINMUX('D', 11, AF7)>; /* USART3_CTS_NSS */
2226+
bias-pull-up;
2227+
};
2228+
};
2229+
2230+
usart3_idle_pins_e: usart3-idle-4 {
2231+
pins1 {
2232+
pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
2233+
<STM32_PINMUX('D', 11, ANALOG)>; /* USART3_CTS_NSS */
2234+
};
2235+
pins2 {
2236+
pinmux = <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */
2237+
bias-disable;
2238+
drive-push-pull;
2239+
slew-rate = <0>;
2240+
};
2241+
pins3 {
2242+
pinmux = <STM32_PINMUX('B', 11, AF7)>; /* USART3_RX */
2243+
bias-pull-up;
2244+
};
2245+
};
2246+
2247+
usart3_sleep_pins_e: usart3-sleep-4 {
2248+
pins {
2249+
pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
2250+
<STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */
2251+
<STM32_PINMUX('D', 11, ANALOG)>, /* USART3_CTS_NSS */
2252+
<STM32_PINMUX('B', 11, ANALOG)>; /* USART3_RX */
2253+
};
2254+
};
2255+
21372256
usbotg_hs_pins_a: usbotg-hs-0 {
21382257
pins {
21392258
pinmux = <STM32_PINMUX('A', 10, ANALOG)>; /* OTG_ID */

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