Merge branch 'master' into next

Merge in v2022.07-rc5.

Author: trini

.gitignore

@@ -10,6 +10,7 @@
 *.asn1.[ch]
 *.bin
 *.cfgout
+*.cover
 *.dtb
 *.dtbo
 *.dtb.S
@@ -22,6 +23,7 @@
 *.lex.c
 *.lst
 *.mod.c
+*.mbx
 *.o
 *.o.*
 *.order

Makefile

@@ -3,7 +3,7 @@
 VERSION = 2022
 PATCHLEVEL = 07
 SUBLEVEL =
-EXTRAVERSION = -rc4
+EXTRAVERSION = -rc5
 NAME =
 
 # *DOCUMENTATION*

arch/arm/cpu/armv8/cache_v8.c

@@ -39,8 +39,28 @@ DECLARE_GLOBAL_DATA_PTR;
  *    off:          FFF
  */
 
-u64 get_tcr(int el, u64 *pips, u64 *pva_bits)
+static int get_effective_el(void)
 {
+	int el = current_el();
+
+	if (el == 2) {
+		u64 hcr_el2;
+
+		/*
+		 * If we are using the EL2&0 translation regime, the TCR_EL2
+		 * looks like the EL1 version, even though we are in EL2.
+		 */
+		__asm__ ("mrs %0, HCR_EL2\n" : "=r" (hcr_el2));
+		if (hcr_el2 & BIT(HCR_EL2_E2H_BIT))
+			return 1;
+	}
+
+	return el;
+}
+
+u64 get_tcr(u64 *pips, u64 *pva_bits)
+{
+	int el = get_effective_el();
 	u64 max_addr = 0;
 	u64 ips, va_bits;
 	u64 tcr;
@@ -115,7 +135,7 @@ static u64 *find_pte(u64 addr, int level)
 
 	debug("addr=%llx level=%d\n", addr, level);
 
-	get_tcr(0, NULL, &va_bits);
+	get_tcr(NULL, &va_bits);
 	if (va_bits < 39)
 		start_level = 1;
 
@@ -343,7 +363,7 @@ __weak u64 get_page_table_size(void)
 	u64 va_bits;
 	int start_level = 0;
 
-	get_tcr(0, NULL, &va_bits);
+	get_tcr(NULL, &va_bits);
 	if (va_bits < 39)
 		start_level = 1;
 
@@ -415,7 +435,7 @@ __weak void mmu_setup(void)
 		setup_all_pgtables();
 
 	el = current_el();
-	set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL),
+	set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(NULL, NULL),
 			  MEMORY_ATTRIBUTES);
 
 	/* enable the mmu */

arch/arm/cpu/armv8/fsl-layerscape/cpu.c

@@ -454,7 +454,7 @@ static inline void early_mmu_setup(void)
 
 	/* point TTBR to the new table */
 	set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
-			  get_tcr(el, NULL, NULL) &
+			  get_tcr(NULL, NULL) &
 			  ~(TCR_ORGN_MASK | TCR_IRGN_MASK),
 			  MEMORY_ATTRIBUTES);
 
@@ -609,7 +609,7 @@ static inline void final_mmu_setup(void)
 	invalidate_icache_all();
 
 	/* point TTBR to the new table */
-	set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL),
+	set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(NULL, NULL),
 			  MEMORY_ATTRIBUTES);
 
 	set_sctlr(get_sctlr() | CR_M);

arch/arm/cpu/armv8/start.S

@@ -125,7 +125,7 @@ pie_fixup_done:
 	msr	cptr_el3, xzr			/* Enable FP/SIMD */
 	b	0f
 2:	mrs	x1, hcr_el2
-	tbnz	x1, #34, 1f			/* HCR_EL2.E2H */
+	tbnz	x1, #HCR_EL2_E2H_BIT, 1f	/* HCR_EL2.E2H */
 	orr	x1, x1, #HCR_EL2_AMO_EL2	/* Route SErrors to EL2 */
 	msr	hcr_el2, x1
 	set_vbar vbar_el2, x0

arch/arm/dts/Makefile

@@ -1178,7 +1178,8 @@ dtb-$(CONFIG_STM32MP15x) += \
 	stm32mp15xx-dhcom-drc02.dtb \
 	stm32mp15xx-dhcom-pdk2.dtb \
 	stm32mp15xx-dhcom-picoitx.dtb \
-	stm32mp15xx-dhcor-avenger96.dtb
+	stm32mp15xx-dhcor-avenger96.dtb \
+	stm32mp15xx-dhcor-drc-compact.dtb
 
 dtb-$(CONFIG_SOC_K3_AM6) += \
 	k3-am654-base-board.dtb \

arch/arm/dts/imx6qdl-sr-som.dtsi

@@ -55,7 +55,13 @@
 	pinctrl-0 = <&pinctrl_microsom_enet_ar8035>;
 	phy-handle = <&phy>;
 	phy-mode = "rgmii-id";
-	phy-reset-duration = <2>;
+
+	/*
+	 * The PHY seems to require a long-enough reset duration to avoid
+	 * some rare issues where the PHY gets stuck in an inconsistent and
+	 * non-functional state at boot-up. 10ms proved to be fine .
+	 */
+	phy-reset-duration = <10>;
 	phy-reset-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
 	status = "okay";
 
@@ -64,8 +70,15 @@
 		#size-cells = <0>;
 
 		phy: ethernet-phy@0 {
-			reg = <0>;
+			/*
+			 * The PHY can appear either:
+			 * - AR8035: at address 0 or 4
+			 * - ADIN1300: at address 1
+			 * Actual address being detected at runtime.
+			 */
+			reg = <0xffffffff>;
 			qca,clk-out-frequency = <125000000>;
+			adi,phy-output-clock = "125mhz-free-running";
 		};
 	};
 };

arch/arm/dts/imx8mn-evk-u-boot.dtsi

@@ -58,7 +58,9 @@
 	};
 
 
-	flash {
+	spl {
+		filename = "spl.bin";
+
 		mkimage {
 			args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x912000";
 

arch/arm/dts/imx8mq-kontron-pitx-imx8m-u-boot.dtsi

@@ -10,3 +10,18 @@
 	sd-uhs-sdr104;
 	sd-uhs-ddr50;
 };
+
+&uart1 {
+	/delete-property/ assigned-clocks;
+	/delete-property/ assigned-clock-parents;
+};
+
+&uart2 {
+	/delete-property/ assigned-clocks;
+	/delete-property/ assigned-clock-parents;
+};
+
+&uart3 {
+	/delete-property/ assigned-clocks;
+	/delete-property/ assigned-clock-parents;
+};

arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi

@@ -2,7 +2,7 @@
 /*
  * U-Boot additions
  *
- * Copyright (C) 2019 Intel Corporation <www.intel.com>
+ * Copyright (C) 2019-2022 Intel Corporation <www.intel.com>
  */
 
 #include "socfpga_agilex-u-boot.dtsi"
@@ -11,6 +11,15 @@
 	aliases {
 		spi0 = &qspi;
 		i2c0 = &i2c1;
+		freeze_br0 = &freeze_controller;
+	};
+
+	soc {
+		freeze_controller: freeze_controller@f9000450 {
+			compatible = "altr,freeze-bridge-controller";
+			reg = <0xf9000450 0x00000010>;
+			status = "disabled";
+		};
 	};
 
 	memory {