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This repository was archived by the owner on Oct 3, 2024. It is now read-only.

Commit 96ec825

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zhenywzhenyw
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Merge remote-tracking branch 'origin/gvt-next' into gvt-staging
2 parents 5d1bfc4 + f32c276 commit 96ec825

25 files changed

+546
-1426
lines changed

‎drivers/gpu/drm/i915/Kconfig

Lines changed: 8 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -98,39 +98,24 @@ config DRM_I915_USERPTR
9898

9999
If in doubt, say "Y".
100100

101-
config DRM_I915_GVT
102-
bool "Enable Intel GVT-g graphics virtualization host support"
101+
config DRM_I915_GVT_KVMGT
102+
tristate "Enable KVM host support Intel GVT-g graphics virtualization"
103103
depends on DRM_I915
104104
depends on 64BIT
105-
default n
105+
depends on KVM
106+
depends on VFIO_MDEV
106107
help
107108
Choose this option if you want to enable Intel GVT-g graphics
108109
virtualization technology host support with integrated graphics.
109110
With GVT-g, it's possible to have one integrated graphics
110-
device shared by multiple VMs under different hypervisors.
111+
device shared by multiple VMs under KVM.
111112

112-
Note that at least one hypervisor like Xen or KVM is required for
113-
this driver to work, and it only supports newer device from
114-
Broadwell+. For further information and setup guide, you can
115-
visit: http://01.org/igvt-g.
116-
117-
Now it's just a stub to support the modifications of i915 for
118-
GVT device model. It requires at least one MPT modules for Xen/KVM
119-
and other components of GVT device model to work. Use it under
120-
you own risk.
113+
Note that this driver only supports newer device from Broadwell on.
114+
For further information and setup guide, you can visit:
115+
http://01.org/igvt-g.
121116

122117
If in doubt, say "N".
123118

124-
config DRM_I915_GVT_KVMGT
125-
tristate "Enable KVM/VFIO support for Intel GVT-g"
126-
depends on DRM_I915_GVT
127-
depends on KVM
128-
depends on VFIO_MDEV
129-
default n
130-
help
131-
Choose this option if you want to enable KVMGT support for
132-
Intel GVT-g.
133-
134119
menu "drm/i915 Debugging"
135120
depends on DRM_I915
136121
depends on EXPERT

‎drivers/gpu/drm/i915/Makefile

Lines changed: 25 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -296,14 +296,34 @@ i915-$(CONFIG_DRM_I915_SELFTEST) += \
296296

297297
# virtual gpu code
298298
i915-y += i915_vgpu.o
299+
i915-$(CONFIG_DRM_I915_GVT_KVMGT) += intel_gvt.o
299300

300-
ifeq ($(CONFIG_DRM_I915_GVT),y)
301-
i915-y += intel_gvt.o
302-
include $(src)/gvt/Makefile
303-
endif
301+
kvmgt-y += gvt/kvmgt.o \
302+
gvt/gvt.o \
303+
gvt/aperture_gm.o \
304+
gvt/handlers.o \
305+
gvt/vgpu.o \
306+
gvt/trace_points.o \
307+
gvt/firmware.o \
308+
gvt/interrupt.o \
309+
gvt/gtt.o \
310+
gvt/cfg_space.o \
311+
gvt/opregion.o \
312+
gvt/mmio.o \
313+
gvt/display.o \
314+
gvt/edid.o \
315+
gvt/execlist.o \
316+
gvt/scheduler.o \
317+
gvt/sched_policy.o \
318+
gvt/mmio_context.o \
319+
gvt/cmd_parser.o \
320+
gvt/debugfs.o \
321+
gvt/fb_decoder.o \
322+
gvt/dmabuf.o \
323+
gvt/page_track.o
304324

305325
obj-$(CONFIG_DRM_I915) += i915.o
306-
obj-$(CONFIG_DRM_I915_GVT_KVMGT) += gvt/kvmgt.o
326+
obj-$(CONFIG_DRM_I915_GVT_KVMGT) += kvmgt.o
307327

308328
# header test
309329

‎drivers/gpu/drm/i915/gt/intel_execlists_submission.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -416,7 +416,7 @@ execlists_context_status_change(struct i915_request *rq, unsigned long status)
416416
* Only used when GVT-g is enabled now. When GVT-g is disabled,
417417
* The compiler should eliminate this function as dead-code.
418418
*/
419-
if (!IS_ENABLED(CONFIG_DRM_I915_GVT))
419+
if (!IS_ENABLED(CONFIG_DRM_I915_GVT_KVMGT))
420420
return;
421421

422422
atomic_notifier_call_chain(&rq->engine->context_status_notifier,
@@ -926,7 +926,7 @@ static void execlists_submit_ports(struct intel_engine_cs *engine)
926926

927927
static bool ctx_single_port_submission(const struct intel_context *ce)
928928
{
929-
return (IS_ENABLED(CONFIG_DRM_I915_GVT) &&
929+
return (IS_ENABLED(CONFIG_DRM_I915_GVT_KVMGT) &&
930930
intel_context_force_single_submission(ce));
931931
}
932932

‎drivers/gpu/drm/i915/gvt/Makefile

Lines changed: 0 additions & 9 deletions
This file was deleted.

‎drivers/gpu/drm/i915/gvt/cfg_space.c

Lines changed: 17 additions & 72 deletions
Original file line numberDiff line numberDiff line change
@@ -129,60 +129,16 @@ int intel_vgpu_emulate_cfg_read(struct intel_vgpu *vgpu, unsigned int offset,
129129
return 0;
130130
}
131131

132-
static int map_aperture(struct intel_vgpu *vgpu, bool map)
132+
static void map_aperture(struct intel_vgpu *vgpu, bool map)
133133
{
134-
phys_addr_t aperture_pa = vgpu_aperture_pa_base(vgpu);
135-
unsigned long aperture_sz = vgpu_aperture_sz(vgpu);
136-
u64 first_gfn;
137-
u64 val;
138-
int ret;
139-
140-
if (map == vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_APERTURE].tracked)
141-
return 0;
142-
143-
val = vgpu_cfg_space(vgpu)[PCI_BASE_ADDRESS_2];
144-
if (val & PCI_BASE_ADDRESS_MEM_TYPE_64)
145-
val = *(u64 *)(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_2);
146-
else
147-
val = *(u32 *)(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_2);
148-
149-
first_gfn = (val + vgpu_aperture_offset(vgpu)) >> PAGE_SHIFT;
150-
151-
ret = intel_gvt_hypervisor_map_gfn_to_mfn(vgpu, first_gfn,
152-
aperture_pa >> PAGE_SHIFT,
153-
aperture_sz >> PAGE_SHIFT,
154-
map);
155-
if (ret)
156-
return ret;
157-
158-
vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_APERTURE].tracked = map;
159-
return 0;
134+
if (map != vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_APERTURE].tracked)
135+
vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_APERTURE].tracked = map;
160136
}
161137

162-
static int trap_gttmmio(struct intel_vgpu *vgpu, bool trap)
138+
static void trap_gttmmio(struct intel_vgpu *vgpu, bool trap)
163139
{
164-
u64 start, end;
165-
u64 val;
166-
int ret;
167-
168-
if (trap == vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_GTTMMIO].tracked)
169-
return 0;
170-
171-
val = vgpu_cfg_space(vgpu)[PCI_BASE_ADDRESS_0];
172-
if (val & PCI_BASE_ADDRESS_MEM_TYPE_64)
173-
start = *(u64 *)(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_0);
174-
else
175-
start = *(u32 *)(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_0);
176-
177-
start &= ~GENMASK(3, 0);
178-
end = start + vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_GTTMMIO].size - 1;
179-
180-
ret = intel_gvt_hypervisor_set_trap_area(vgpu, start, end, trap);
181-
if (ret)
182-
return ret;
183-
184-
vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_GTTMMIO].tracked = trap;
185-
return 0;
140+
if (trap != vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_GTTMMIO].tracked)
141+
vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_GTTMMIO].tracked = trap;
186142
}
187143

188144
static int emulate_pci_command_write(struct intel_vgpu *vgpu,
@@ -191,26 +147,17 @@ static int emulate_pci_command_write(struct intel_vgpu *vgpu,
191147
u8 old = vgpu_cfg_space(vgpu)[offset];
192148
u8 new = *(u8 *)p_data;
193149
u8 changed = old ^ new;
194-
int ret;
195150

196151
vgpu_pci_cfg_mem_write(vgpu, offset, p_data, bytes);
197152
if (!(changed & PCI_COMMAND_MEMORY))
198153
return 0;
199154

200155
if (old & PCI_COMMAND_MEMORY) {
201-
ret = trap_gttmmio(vgpu, false);
202-
if (ret)
203-
return ret;
204-
ret = map_aperture(vgpu, false);
205-
if (ret)
206-
return ret;
156+
trap_gttmmio(vgpu, false);
157+
map_aperture(vgpu, false);
207158
} else {
208-
ret = trap_gttmmio(vgpu, true);
209-
if (ret)
210-
return ret;
211-
ret = map_aperture(vgpu, true);
212-
if (ret)
213-
return ret;
159+
trap_gttmmio(vgpu, true);
160+
map_aperture(vgpu, true);
214161
}
215162

216163
return 0;
@@ -230,13 +177,12 @@ static int emulate_pci_rom_bar_write(struct intel_vgpu *vgpu,
230177
return 0;
231178
}
232179

233-
static int emulate_pci_bar_write(struct intel_vgpu *vgpu, unsigned int offset,
180+
static void emulate_pci_bar_write(struct intel_vgpu *vgpu, unsigned int offset,
234181
void *p_data, unsigned int bytes)
235182
{
236183
u32 new = *(u32 *)(p_data);
237184
bool lo = IS_ALIGNED(offset, 8);
238185
u64 size;
239-
int ret = 0;
240186
bool mmio_enabled =
241187
vgpu_cfg_space(vgpu)[PCI_COMMAND] & PCI_COMMAND_MEMORY;
242188
struct intel_vgpu_pci_bar *bars = vgpu->cfg_space.bar;
@@ -259,14 +205,14 @@ static int emulate_pci_bar_write(struct intel_vgpu *vgpu, unsigned int offset,
259205
* Untrap the BAR, since guest hasn't configured a
260206
* valid GPA
261207
*/
262-
ret = trap_gttmmio(vgpu, false);
208+
trap_gttmmio(vgpu, false);
263209
break;
264210
case PCI_BASE_ADDRESS_2:
265211
case PCI_BASE_ADDRESS_3:
266212
size = ~(bars[INTEL_GVT_PCI_BAR_APERTURE].size -1);
267213
intel_vgpu_write_pci_bar(vgpu, offset,
268214
size >> (lo ? 0 : 32), lo);
269-
ret = map_aperture(vgpu, false);
215+
map_aperture(vgpu, false);
270216
break;
271217
default:
272218
/* Unimplemented BARs */
@@ -282,19 +228,18 @@ static int emulate_pci_bar_write(struct intel_vgpu *vgpu, unsigned int offset,
282228
*/
283229
trap_gttmmio(vgpu, false);
284230
intel_vgpu_write_pci_bar(vgpu, offset, new, lo);
285-
ret = trap_gttmmio(vgpu, mmio_enabled);
231+
trap_gttmmio(vgpu, mmio_enabled);
286232
break;
287233
case PCI_BASE_ADDRESS_2:
288234
case PCI_BASE_ADDRESS_3:
289235
map_aperture(vgpu, false);
290236
intel_vgpu_write_pci_bar(vgpu, offset, new, lo);
291-
ret = map_aperture(vgpu, mmio_enabled);
237+
map_aperture(vgpu, mmio_enabled);
292238
break;
293239
default:
294240
intel_vgpu_write_pci_bar(vgpu, offset, new, lo);
295241
}
296242
}
297-
return ret;
298243
}
299244

300245
/**
@@ -336,8 +281,8 @@ int intel_vgpu_emulate_cfg_write(struct intel_vgpu *vgpu, unsigned int offset,
336281
case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_5:
337282
if (drm_WARN_ON(&i915->drm, !IS_ALIGNED(offset, 4)))
338283
return -EINVAL;
339-
return emulate_pci_bar_write(vgpu, offset, p_data, bytes);
340-
284+
emulate_pci_bar_write(vgpu, offset, p_data, bytes);
285+
break;
341286
case INTEL_GVT_PCI_SWSCI:
342287
if (drm_WARN_ON(&i915->drm, !IS_ALIGNED(offset, 4)))
343288
return -EINVAL;

‎drivers/gpu/drm/i915/gvt/cmd_parser.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1009,7 +1009,7 @@ static int cmd_reg_handler(struct parser_exec_state *s,
10091009
if (GRAPHICS_VER(s->engine->i915) == 9 &&
10101010
intel_gvt_mmio_is_sr_in_ctx(gvt, offset) &&
10111011
!strncmp(cmd, "lri", 3)) {
1012-
intel_gvt_hypervisor_read_gpa(s->vgpu,
1012+
intel_gvt_read_gpa(s->vgpu,
10131013
s->workload->ring_context_gpa + 12, &ctx_sr_ctl, 4);
10141014
/* check inhibit context */
10151015
if (ctx_sr_ctl & 1) {
@@ -1773,7 +1773,7 @@ static int copy_gma_to_hva(struct intel_vgpu *vgpu, struct intel_vgpu_mm *mm,
17731773
copy_len = (end_gma - gma) >= (I915_GTT_PAGE_SIZE - offset) ?
17741774
I915_GTT_PAGE_SIZE - offset : end_gma - gma;
17751775

1776-
intel_gvt_hypervisor_read_gpa(vgpu, gpa, va + len, copy_len);
1776+
intel_gvt_read_gpa(vgpu, gpa, va + len, copy_len);
17771777

17781778
len += copy_len;
17791779
gma += copy_len;

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