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| 1 | +;=========================== begin_copyright_notice ============================ |
| 2 | +; |
| 3 | +; Copyright (C) 2025 Intel Corporation |
| 4 | +; |
| 5 | +; SPDX-License-Identifier: MIT |
| 6 | +; |
| 7 | +;============================ end_copyright_notice ============================= |
| 8 | + |
| 9 | +; RUN: igc_opt --typed-pointers %s -S -o - -ocl -inputocl -platformdg2 -igc-vectorpreprocess | FileCheck %s |
| 10 | + |
| 11 | +; Test finding vector elements in insertelement instructions used to construct the vector. |
| 12 | +; Test that the last inserted value is used. |
| 13 | + |
| 14 | +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-n8:16:32" |
| 15 | + |
| 16 | +define void @test_kernel(i8 addrspace(2490368)* %bso, i32 %bufferOffset, half %a, half %b, half %c, half %d, half %e) |
| 17 | +{ |
| 18 | +entry: |
| 19 | + %vec0 = insertelement <5 x half> undef, half %a, i64 0 |
| 20 | + %vec1 = insertelement <5 x half> %vec0, half %b, i64 1 |
| 21 | + %vec2 = insertelement <5 x half> %vec1, half %c, i64 2 |
| 22 | + %vec3 = insertelement <5 x half> %vec2, half %d, i64 3 |
| 23 | + %vec4.overwritten = insertelement <5 x half> %vec3, half %d, i64 4 |
| 24 | + %vec4 = insertelement <5 x half> %vec4.overwritten, half %e, i64 4 |
| 25 | + call void @llvm.genx.GenISA.storerawvector.indexed.p2490368i8.v5f16(i8 addrspace(2490368)* %bso, i32 %bufferOffset, <5 x half> %vec4, i32 16, i1 false) |
| 26 | + |
| 27 | + ret void |
| 28 | +} |
| 29 | + |
| 30 | +; CHECK-LABEL: void @test_kernel( |
| 31 | +; CHECK-SAME: i8 addrspace(2490368)* [[BSO:%.*]], i32 [[OFFSET:%.*]], half [[A:%.*]], half [[B:%.*]], half [[C:%.*]], half [[D:%.*]], half [[E:%.*]]) |
| 32 | + |
| 33 | +; CHECK: [[VEC0:%.*]] = insertelement <4 x half> undef, half [[A]], i32 0 |
| 34 | +; CHECK: [[VEC1:%.*]] = insertelement <4 x half> [[VEC0]], half [[B]], i32 1 |
| 35 | +; CHECK: [[VEC2:%.*]] = insertelement <4 x half> [[VEC1]], half [[C]], i32 2 |
| 36 | +; CHECK: [[VEC3:%.*]] = insertelement <4 x half> [[VEC2]], half [[D]], i32 3 |
| 37 | +; CHECK: [[OFF0:%.*]] = add i32 0, [[OFFSET]] |
| 38 | +; CHECK: call void @llvm.genx.GenISA.storerawvector.indexed.p2490368i8.v4f16(i8 addrspace(2490368)* [[BSO]], i32 [[OFF0]], <4 x half> [[VEC3]], i32 16, i1 false) |
| 39 | +; CHECK: [[OFF1:%.*]] = add i32 8, [[OFFSET]] |
| 40 | +; CHECK: call void @llvm.genx.GenISA.storerawvector.indexed.p2490368i8.f16(i8 addrspace(2490368)* [[BSO]], i32 [[OFF1]], half [[E]], i32 8, i1 false) |
| 41 | + |
| 42 | + |
| 43 | +; Function Desc: Write a vector to a buffer pointer at byte offset |
| 44 | +; Output: |
| 45 | +; Arg 0: buffer pointer, result of GetBufferPtr |
| 46 | +; Arg 1: offset from the base pointer, in bytes |
| 47 | +; Arg 2: value to store |
| 48 | +; Arg 3: aligment in bytes |
| 49 | +; Arg 4: volatile, must be an immediate |
| 50 | +; Function Attrs: argmemonly nounwind writeonly |
| 51 | +declare void @llvm.genx.GenISA.storerawvector.indexed.p2490368i8.v5f16(i8 addrspace(2490368)*, i32, <5 x half>, i32, i1) |
| 52 | + |
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