Written by Jacob Koziej (EE '25) & Ani Vardanyan (EE '25)
Instruction Set Architecture (ISA)
- Jacob (60%)
- Ani (40%)
CPU implementation in Verilog
- Jacob (50%)
- Ani (50%)
ALU
- Jacob (50%)
- Ani (50%)
Controller
- Jacob (60%)
- Ani (40%)
Datapath
- Jacob (50%)
- Ani (50%)
Verilog test bench for computer
- Jacob (60%)
- Ani (40%)
Compilation of assembly code into machine code
- Jacob (80%)
- Ani (20%)
Timing diagrams
- Jacob (80%)
- Ani (20%)
Schematic
- Jacob (10%)
- Ani (90%)
Assembler
- Jacob (98%)
- Ani (2%)