removing linear zise option, renaming module

Author: jeras

README.md

@@ -36,11 +36,11 @@ for the rest of the code.
 
 ### VIP (Verification IP)
 
-| module                                      | status | description |
-|---------------------------------------------|--------|-------------|
-| [`tcb_vip_pkg`](hdl/tbn/vip/tcb_vip_pkg.sv) | VIP    | Package containing manager/monitor/subordinate code. |
-| [`tcb_vip_mem`](hdl/tbn/vip/tcb_vip_mem.sv) | VIP    | Multi port memory model. |
-| [`tcb_vip_tb` ](hdl/tbn/vip/tcb_vip_tb.sv ) | VIP    | Testbench for core VIP functionality. |
+| module                                           | status | description |
+|--------------------------------------------------|--------|-------------|
+| [`tcb_vip_pkg`](hdl/tbn/vip/tcb_vip_pkg.sv)      | VIP    | Package containing manager/monitor/subordinate code. |
+| [`tcb_vip_memory`](hdl/tbn/vip/tcb_if_memory.sv) | VIP    | Multi port memory model. |
+| [`tcb_vip_tb` ](hdl/tbn/vip/tcb_vip_tb.sv )      | VIP    | Testbench for core VIP functionality. |
 
 ### Reference implementation library
 
@@ -76,4 +76,4 @@ for the rest of the code.
 1. OpenHW Group [OBI](https://github.com/openhwgroup/obi) (OpenBus Interface)
 1. TileLink [1.8.0](https://github.com/chipsalliance/omnixtend/blob/c192bb6862846a24535b3808dc2f8612d44f2ff8/OmniXtend-1.0.3/spec/TileLink-1.8.0.pdf),
 [1.8.1](https://starfivetech.com/uploads/tilelink_spec_1.8.1.pdf)
-1. OpenTitan [TileLink IP](https://docs.opentitan.org/hw/ip/tlul/doc/)
+1. OpenTitan [TileLink IP](https://docs.opentitan.org/hw/ip/tlul/doc/)

doc/TCB.md

@@ -464,7 +464,6 @@ The following parameters affect data packing.
 | parameter | default          | type (enumeration) | description |
 |-----------|------------------|--------------------|-------------|
 | `PHY.ALW` | `clog2(DBW/SLW)` | `int unsigned`     | Alignment width, number of least significant address bits which are zero. |
-| `PHY.SIZ` | `LOGARITHMIC`    | `tcb_par_size_t`   | Transfer size encoding, logarithmic or linear. |
 | `PHY.MOD` | `REFERENCE`      | `tcb_par_mode_t`   | Data position mode. |
 | `PHY.ORD` | `DESCENDING`     | `tcb_par_order_t`  | Byte order, ascending or descending. |
 
@@ -497,6 +496,8 @@ other values in between can be used for custom implementations.
 
 ##### Transfer size encoding
 
+TODO: remove references to LINEAR size.
+
 The `SIZ` parameter encoding defines the following options.
 - `LOGARITHMIC`,
 - `LINEAR`.
@@ -523,13 +524,6 @@ The width of the transfer size signal `siz` in the logarithmic case is
 NOTE: The linear option is an experimental proposal and
 is not yet compatible with any other standard or implementation.
 
-A more generic option `LINEAR` allows for any number of bytes
-up to the data bus width to be transferred.
-In this case the number of transferred bytes is `num=siz+1`.
-
-The width of the transfer size signal `siz` in the linear case is
-`clog2(DBW/SLW)==clog2(BEW)`.
-
 The byte enable signal `ben` is restricted in both the logarithmic and linear cases to
 only number long sequences of adjacent active bits (representing data bytes),
 with all other bits inactive.

hdl/rtl/lib/tcb_lib_decoder.sv

@@ -20,12 +20,12 @@ module tcb_lib_decoder
   import tcb_pkg::*;
 #(
   // TCB parameters (contains address width)
-  parameter  tcb_par_phy_t  PHY = TCB_PAR_PHY_DEF,
+  parameter  tcb_par_phy_t PHY = TCB_PAR_PHY_DEF,
   // interconnect parameters (manager port number and logarithm)
   parameter  int unsigned MPN = 2,
   localparam int unsigned MPL = $clog2(MPN),
   // decoder address and mask array
-  parameter  logic [PHY.ABW-1:0] DAM [MPN-1:0] = '{MPN{PHY.ABW'('x)}}
+  parameter  logic [PHY.ABW-1:0] DAM [MPN-1:0] = '{default: 'x}
 )(
   // TCB interfaces
   tcb_if.sub tcb,  // TCB subordinate port (manager device connects here)

hdl/rtl/tcb_if.sv

@@ -36,10 +36,7 @@ interface tcb_if
   localparam int unsigned PHY_BEW = PHY.DBW / PHY.SLW;
 
   // transfer size width calculation
-  localparam int unsigned PHY_SZW_LIN = $clog2(       PHY_BEW   );  // linear
-  localparam int unsigned PHY_SZW_LOG = $clog2($clog2(PHY_BEW)+1);  // logarithmic (default)
-  // transfer size width selection
-  localparam int unsigned PHY_SZW = (PHY.SIZ == TCB_LINEAR) ? PHY_SZW_LIN : PHY_SZW_LOG;
+  localparam int unsigned PHY_SZW = $clog2($clog2(PHY_BEW)+1);
 
 ////////////////////////////////////////////////////////////////////////////////
 // I/O ports
@@ -132,10 +129,7 @@ interface tcb_if
   generate
   if (PHY.MOD == TCB_REFERENCE) begin: byteenable
     for (genvar b=0; b<PHY_BEW; b++) begin
-      case (PHY.SIZ)
-        TCB_LOGARITHMIC:  assign req_ben[b] = b < (2**    req.siz );
-        TCB_LINEAR     :  assign req_ben[b] = b < (2**(2**req.siz));
-      endcase
+      assign req_ben[b] = b < (2**req.siz);
     end
   end: byteenable
   else begin

hdl/rtl/tcb_pkg.sv

@@ -35,12 +35,6 @@ package tcb_pkg;
 // size/mode/order/channel (used for compile time parameters)
 ////////////////////////////////////////////////////////////////////////////////
 
-  // transfer size encoding
-  typedef enum bit {
-    TCB_LOGARITHMIC = 1'b0,  // logarithmic (2^n)
-    TCB_LINEAR      = 1'b1   // linear (n)
-  } tcb_par_size_t;
-
   // data position mode
   typedef enum bit {
     TCB_REFERENCE = 1'b0,  // always LSB aligned
@@ -68,7 +62,7 @@ package tcb_pkg;
 
   // physical interface parameter structure
   // TODO: the structure is packed to workaround a Verilator bug
-  typedef struct {
+  typedef struct packed {
     // protocol
     int unsigned      DLY;  // response delay
     // signal widths
@@ -77,7 +71,6 @@ package tcb_pkg;
     int unsigned      DBW;  // data    bus width
     int unsigned      ALW;  // alignment width
     // data packing parameters
-    tcb_par_size_t    SIZ;  // transfer size encoding
     tcb_par_mode_t    MOD;  // data position mode
     tcb_par_order_t   ORD;  // byte order
     // channel configuration
@@ -94,7 +87,6 @@ package tcb_pkg;
     DBW: 32,
     ALW: 2,   // $clog2(DBW/SLW)
     // data packing parameters
-    SIZ: TCB_LOGARITHMIC,
     MOD: TCB_MEMORY,
     ORD: TCB_DESCENDING,
     // channel configuration
@@ -129,7 +121,6 @@ package tcb_pkg;
     status.ABW = phy_val.ABW ==? phy_ref.ABW;
     status.DBW = phy_val.DBW ==? phy_ref.DBW;
     status.ALW = phy_val.ALW ==? phy_ref.ALW;
-    status.SIZ = phy_val.SIZ ==? phy_ref.SIZ;
     status.MOD = phy_val.MOD ==? phy_ref.MOD;
     status.ORD = phy_val.ORD ==? phy_ref.ORD;
     status.CHN = phy_val.CHN ==? phy_ref.CHN;
@@ -140,7 +131,6 @@ package tcb_pkg;
     if (status.ABW)  $error("parameter mismatch PHY.ABW=%d != PHY.ABW=%d", phy_val.ABW, phy_ref.ABW);
     if (status.DBW)  $error("parameter mismatch PHY.DBW=%d != PHY.DBW=%d", phy_val.DBW, phy_ref.DBW);
     if (status.ALW)  $error("parameter mismatch PHY.ALW=%d != PHY.ALW=%d", phy_val.ALW, phy_ref.ALW);
-    if (status.SIZ)  $error("parameter mismatch PHY.SIZ=%d != PHY.SIZ=%d", phy_val.SIZ, phy_ref.SIZ);
     if (status.MOD)  $error("parameter mismatch PHY.MOD=%d != PHY.MOD=%d", phy_val.MOD, phy_ref.MOD);
     if (status.ORD)  $error("parameter mismatch PHY.ORD=%d != PHY.ORD=%d", phy_val.ORD, phy_ref.ORD);
     if (status.CHN)  $error("parameter mismatch PHY.CHN=%d != PHY.CHN=%d", phy_val.CHN, phy_ref.CHN);

hdl/tbn/lib/tcb_lib_converter_tb.sv

@@ -165,7 +165,7 @@ module tcb_lib_converter_tb
 ////////////////////////////////////////////////////////////////////////////////
 
   // memory model subordinate
-  tcb_vip_mem         mem       (.tcb (tcb_mem));
+  tcb_vip_memory      mem       (.tcb (tcb_mem));
 
   // connect interfaces to interface array
   tcb_lib_passthrough pas [0:0] (.sub (tcb_sub), .man (tcb_mem));

hdl/tbn/lib/tcb_lib_register_backpressure_tb.sv

@@ -75,10 +75,10 @@ module tcb_lib_register_backpressure_tb
 // VIP instances
 ////////////////////////////////////////////////////////////////////////////////
 
-  tcb_vip_dev #("MAN") man     (.tcb (tcb_man));  // manager
-  tcb_vip_dev #("MON") mon_man (.tcb (tcb_man));  // manager monitor
-  tcb_vip_dev #("MON") mon_sub (.tcb (tcb_sub));  // subordinate monitor
-  tcb_vip_mem #("SUB") mem     (.tcb (tcb_mem));  // subordinate
+  tcb_vip_dev    #("MAN") man     (.tcb (tcb_man));  // manager
+  tcb_vip_dev    #("MON") mon_man (.tcb (tcb_man));  // manager monitor
+  tcb_vip_dev    #("MON") mon_sub (.tcb (tcb_sub));  // subordinate monitor
+  tcb_vip_memory #("SUB") mem     (.tcb (tcb_mem));  // subordinate
 
   // connect interfaces to interface array
   tcb_lib_passthrough pas [0:0] (.sub (tcb_sub), .man (tcb_mem));
@@ -104,4 +104,4 @@ module tcb_lib_register_backpressure_tb
     $dumpvars;
   end
 
-endmodule: tcb_lib_register_backpressure_tb
+endmodule: tcb_lib_register_backpressure_tb

hdl/tbn/lib/tcb_lib_register_request_tb.sv

@@ -76,10 +76,10 @@ module tcb_lib_register_request_tb
 // VIP instances
 ////////////////////////////////////////////////////////////////////////////////
 
-  tcb_vip_dev #("MAN") man     (.tcb (tcb_man));  // manager
-  tcb_vip_dev #("MON") mon_man (.tcb (tcb_man));  // manager monitor
-  tcb_vip_dev #("MON") mon_sub (.tcb (tcb_sub));  // subordinate monitor
-  tcb_vip_mem          mem     (.tcb (tcb_mem));  // subordinate
+  tcb_vip_dev    #("MAN") man     (.tcb (tcb_man));  // manager
+  tcb_vip_dev    #("MON") mon_man (.tcb (tcb_man));  // manager monitor
+  tcb_vip_dev    #("MON") mon_sub (.tcb (tcb_sub));  // subordinate monitor
+  tcb_vip_memory          mem     (.tcb (tcb_mem));  // subordinate
 
   // connect interfaces to interface array
   tcb_lib_passthrough pas [0:0] (.sub (tcb_sub), .man (tcb_mem));
@@ -105,4 +105,4 @@ module tcb_lib_register_request_tb
     $dumpvars;
   end
 
-endmodule: tcb_lib_register_request_tb
+endmodule: tcb_lib_register_request_tb

hdl/tbn/lib/tcb_lib_register_response_tb.sv

@@ -76,10 +76,10 @@ module tcb_lib_register_response_tb
 // VIP instances
 ////////////////////////////////////////////////////////////////////////////////
 
-  tcb_vip_dev #("MAN") man     (.tcb (tcb_man));  // manager
-  tcb_vip_dev #("MON") mon_man (.tcb (tcb_man));  // manager monitor
-  tcb_vip_dev #("MON") mon_sub (.tcb (tcb_sub));  // subordinate monitor
-  tcb_vip_mem          mem     (.tcb (tcb_mem));  // subordinate
+  tcb_vip_dev    #("MAN") man     (.tcb (tcb_man));  // manager
+  tcb_vip_dev    #("MON") mon_man (.tcb (tcb_man));  // manager monitor
+  tcb_vip_dev    #("MON") mon_sub (.tcb (tcb_sub));  // subordinate monitor
+  tcb_vip_memory          mem     (.tcb (tcb_mem));  // subordinate
 
   // connect interfaces to interface array
   tcb_lib_passthrough pas [0:0] (.sub (tcb_sub), .man (tcb_mem));
@@ -105,4 +105,4 @@ module tcb_lib_register_response_tb
     $dumpvars;
   end
 
-endmodule: tcb_lib_register_response_tb
+endmodule: tcb_lib_register_response_tb

hdl/tbn/vip/tcb_vip_mem.sv hdl/tbn/vip/tcb_vip_memory.sv

@@ -16,7 +16,7 @@
 // limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////
 
-module tcb_vip_mem
+module tcb_vip_memory
   import tcb_pkg::*;
 //  import tcb_vip_pkg::*;
 #(
@@ -69,7 +69,6 @@ module tcb_vip_mem
     int unsigned start_addr = 0,
     int unsigned finish_addr = SIZ-1
   );
-    int code;  // status code
     int fd;    // file descriptor
     fd = $fopen(fn, "w");
     for (int unsigned addr=start_addr; addr<finish_addr; addr+=4) begin
@@ -80,7 +79,6 @@ module tcb_vip_mem
   //    end
     end
     $fclose(fd);
-    return code;
   endfunction: write_hex
 
 ////////////////////////////////////////////////////////////////////////////////
@@ -106,10 +104,10 @@ module tcb_vip_mem
     // map write data to a packed array
     assign tmp_req_wdt = tcb[i].req.wdt;
 
-    assign tmp_req_siz = (tcb[i].PHY.SIZ == TCB_LINEAR) ? tcb[i].req.siz : 2**tcb[i].req.siz;
+    assign tmp_req_siz = 2**tcb[i].req.siz;
 
     // write access
-    always @(posedge tcb[i].clk)
+    always_ff @(posedge tcb[i].clk)
     if (tcb[i].trn) begin
       if (tcb[i].req.wen) begin: write
         // temporary variables
@@ -139,13 +137,13 @@ module tcb_vip_mem
     end
 
     // combinational read data
-    always @(*)
+    always_comb
     if (tcb[i].trn) begin
       if (~tcb[i].req.wen) begin: read
         // temporary variables
         automatic int unsigned adr;
         if (tcb[i].PHY.MOD == TCB_REFERENCE) begin: reference
-          tmp_rsp_rdt = '{default: 'x};
+          tmp_rsp_rdt[0] = '{default: 'x};
           for (int unsigned b=0; b<tmp_req_siz; b++) begin: byteenable
             adr = b + int'(tcb[i].req.adr);
             tmp_rsp_rdt[0][b] = mem[adr%SIZ];
@@ -184,4 +182,4 @@ module tcb_vip_mem
   end: port
   endgenerate
 
-endmodule: tcb_vip_mem
+endmodule: tcb_vip_memory

hdl/tbn/vip/tcb_vip_pkg.sv

@@ -41,7 +41,7 @@ package tcb_vip_pkg;
     localparam int unsigned PHY_SZW_LIN = $clog2(       PHY_BEW   );  // linear
     localparam int unsigned PHY_SZW_LOG = $clog2($clog2(PHY_BEW)+1);  // logarithmic (default)
     // transfer size width selection
-    localparam int unsigned PHY_SZW = (PHY.SIZ == TCB_LINEAR) ? PHY_SZW_LIN : PHY_SZW_LOG;
+    localparam int unsigned PHY_SZW = PHY_SZW_LOG;
 
 ////////////////////////////////////////////////////////////////////////////////
 ////////////////////////////////////////////////////////////////////////////////
@@ -367,10 +367,10 @@ package tcb_vip_pkg;
           transfer_array[i].req.ndn = transaction_req.ndn;
           transfer_array[i].req.adr = transaction_req.adr;
           transfer_array[i].req.ben = '0;
-          transfer_array[i].req.siz = (PHY.SIZ == TCB_LINEAR) ? PHY_BEW : $clog2(PHY_BEW);
+          transfer_array[i].req.siz = $clog2(PHY_BEW);
         end
         if (siz <= PHY_BEW) begin
-          transfer_array[0].req.siz = (PHY.SIZ == TCB_LINEAR) ?     siz : $clog2(    siz);
+          transfer_array[0].req.siz = $clog2(    siz);
         end
         // data signals
         for (int unsigned i=0; i<siz; i++) begin

hdl/tbn/vip/tcb_vip_tb.sv

@@ -246,7 +246,7 @@ module tcb_vip_tb
 ////////////////////////////////////////////////////////////////////////////////
 
   // memory model subordinate
-  tcb_vip_mem         mem       (.tcb (tcb_mem));
+  tcb_vip_memory         mem       (.tcb (tcb_mem));
 
 ////////////////////////////////////////////////////////////////////////////////
 // DUT instance

sim/edaplayground/Makefile

@@ -30,7 +30,7 @@ RTL+=${PATH_HDL}/rtl/lib/tcb_lib_converter.sv
 # SystemVerilog VIP
 TBN+=${PATH_HDL}/tbn/vip/tcb_vip_pkg.sv
 TBN+=${PATH_HDL}/tbn/vip/tcb_vip_dev.sv
-TBN+=${PATH_HDL}/tbn/vip/tcb_vip_mem.sv
+TBN+=${PATH_HDL}/tbn/vip/tcb_vip_memory.sv
 #TBN+=${PATH_HDL}/tbn/vip/tcb_vip_tb.sv
 ## LIBrary
 #TBN+=${PATH_HDL}/tbn/lib/tcb_lib_passthrough_tb.sv

sim/filelist.mk

@@ -29,7 +29,7 @@ RTL+=${PATH_HDL}/rtl/lib/tcb_lib_converter.sv
 
 # SystemVerilog VIP
 TBN+=${PATH_HDL}/tbn/vip/tcb_vip_pkg.sv
-TBN+=${PATH_HDL}/tbn/vip/tcb_vip_mem.sv
+TBN+=${PATH_HDL}/tbn/vip/tcb_vip_memory.sv
 #TBN+=${PATH_HDL}/tbn/vip/tcb_vip_tb.sv
 # LIBrary
 #TBN+=${PATH_HDL}/tbn/lib/tcb_lib_passthrough_tb.sv