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TCC.lst
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; LST file generated by mikroListExporter - v.2.0
; Date/Time: 4/7/2020 2:28:17 PM
;----------------------------------------------
;Address Opcode ASM
0x0000 0xF008EF00 GOTO 4096
0x0004 0x0000 NOP
0x0006 0x0000 NOP
0x0008 0xF009EF79 GOTO 4850
0x000C 0x0000 NOP
0x000E 0x0000 NOP
0x0010 0x0000 NOP
0x0012 0x0000 NOP
0x0014 0x0000 NOP
0x0016 0x0000 NOP
0x0018 0xD7F3 BRA 0
_main:
0x1000 0xF00AEC00 CALL 5120, 0
;TCC.c,33 :: void main()org 0x1000 { //faz a função main ir para o enderço 0x1000 de memória.
;TCC.c,37 :: board_Init(); //Função de "inicialização" da placa e configuração dos bits.
0x1004 0xD935 RCALL _board_Init
;TCC.c,38 :: interruptConfig();
0x1006 0xD96F RCALL _interruptConfig
;TCC.c,39 :: UART1_Init(9600); // Inicializa a comunicação serial UART com baudrate de 9600bps
0x1008 0x86B8 BSF BAUDCON, 3, 0
0x100A 0x0E02 MOVLW 2
0x100C 0x6EB0 MOVWF SPBRGH
0x100E 0x0E08 MOVLW 8
0x1010 0x6EAF MOVWF SPBRG
0x1012 0x84AC BSF TXSTA, 2, 0
0x1014 0xD93C RCALL _UART1_Init
;TCC.c,40 :: delay_ms(100); // Tempo para o módulo UART estabilizar a conexão.
0x1016 0x0E03 MOVLW 3
0x1018 0x6E0B MOVWF R11, 0
0x101A 0x0E8A MOVLW 138
0x101C 0x6E0C MOVWF R12, 0
0x101E 0x0E55 MOVLW 85
0x1020 0x6E0D MOVWF R13, 0
L_main1:
0x1022 0x2E0D DECFSZ R13, 1, 0
0x1024 0xD7FE BRA L_main1
0x1026 0x2E0C DECFSZ R12, 1, 0
0x1028 0xD7FC BRA L_main1
0x102A 0x2E0B DECFSZ R11, 1, 0
0x102C 0xD7FA BRA L_main1
0x102E 0x0000 NOP
0x1030 0x0000 NOP
;TCC.c,41 :: UART1_Write_Text(INIT); //Envia uma mensagem de inicialização.
0x1032 0x0E2C MOVLW ?lstr1_TCC
0x1034 0x6F1E MOVWF FARG_UART1_Write_Text_uart_text, 1
0x1036 0x0E00 MOVLW hi_addr(?lstr1_TCC)
0x1038 0x6F1F MOVWF FARG_UART1_Write_Text_uart_text+1, 1
0x103A 0xD8EA RCALL _UART1_Write_Text
;TCC.c,42 :: delay_ms(500);
0x103C 0x0E0D MOVLW 13
0x103E 0x6E0B MOVWF R11, 0
0x1040 0x0EAF MOVLW 175
0x1042 0x6E0C MOVWF R12, 0
0x1044 0x0EB6 MOVLW 182
0x1046 0x6E0D MOVWF R13, 0
L_main2:
0x1048 0x2E0D DECFSZ R13, 1, 0
0x104A 0xD7FE BRA L_main2
0x104C 0x2E0C DECFSZ R12, 1, 0
0x104E 0xD7FC BRA L_main2
0x1050 0x2E0B DECFSZ R11, 1, 0
0x1052 0xD7FA BRA L_main2
0x1054 0x0000 NOP
;TCC.c,43 :: while(1){//Inicia o loop infinito.
L_main3:
;TCC.c,44 :: if (UART1_Data_Ready() == 1) {
0x1056 0xD8F6 RCALL _UART1_Data_Ready
0x1058 0x5000 MOVF R0, 0
0x105A 0x0A01 XORLW 1
0x105C 0xE131 BNZ L_main5
;TCC.c,45 :: option = UART1_Read();
0x105E 0xD8F7 RCALL _UART1_Read
0x1060 0xF107C000 MOVFF R0, _option
;TCC.c,46 :: if(!UART1_Data_Ready() && option != 'Z'){
0x1064 0xD8EF RCALL _UART1_Data_Ready
0x1066 0x5200 MOVF R0, 1
0x1068 0xE12B BNZ L_main8
0x106A 0x0101 MOVLB 1
0x106C 0x5107 MOVF _option, 0, 1
0x106E 0x0A5A XORLW 90
0x1070 0xE027 BZ L_main8
L__main46:
;TCC.c,47 :: UART1_Write_Text(ERROR);
0x1072 0x0E66 MOVLW ?lstr2_TCC
0x1074 0x6F1E MOVWF FARG_UART1_Write_Text_uart_text, 1
0x1076 0x0E00 MOVLW hi_addr(?lstr2_TCC)
0x1078 0x6F1F MOVWF FARG_UART1_Write_Text_uart_text+1, 1
0x107A 0xD8CA RCALL _UART1_Write_Text
;TCC.c,48 :: if (UART1_Data_Ready() == 1) {
0x107C 0xD8E3 RCALL _UART1_Data_Ready
0x107E 0x5000 MOVF R0, 0
0x1080 0x0A01 XORLW 1
0x1082 0xE103 BNZ L_main9
;TCC.c,49 :: option = UART1_Read();
0x1084 0xD8E4 RCALL _UART1_Read
0x1086 0xF107C000 MOVFF R0, _option
;TCC.c,50 :: }
L_main9:
;TCC.c,51 :: for(i = 0; i < 3; i++){
0x108A 0x0101 MOVLB 1
0x108C 0x6B1A CLRF main_i_L0, 1
0x108E 0x6B1B CLRF main_i_L0+1, 1
L_main10:
0x1090 0x0E00 MOVLW 0
0x1092 0x5D1B SUBWF main_i_L0+1, 0, 1
0x1094 0xE102 BNZ L__main50
0x1096 0x0E03 MOVLW 3
0x1098 0x5D1A SUBWF main_i_L0, 0, 1
L__main50:
0x109A 0xE212 BC L_main11
;TCC.c,52 :: PORTD.B3 = 1;
0x109C 0x8683 BSF PORTD, 3
;TCC.c,53 :: delay_ms(500);
0x109E 0x0E0D MOVLW 13
0x10A0 0x6E0B MOVWF R11, 0
0x10A2 0x0EAF MOVLW 175
0x10A4 0x6E0C MOVWF R12, 0
0x10A6 0x0EB6 MOVLW 182
0x10A8 0x6E0D MOVWF R13, 0
L_main13:
0x10AA 0x2E0D DECFSZ R13, 1, 0
0x10AC 0xD7FE BRA L_main13
0x10AE 0x2E0C DECFSZ R12, 1, 0
0x10B0 0xD7FC BRA L_main13
0x10B2 0x2E0B DECFSZ R11, 1, 0
0x10B4 0xD7FA BRA L_main13
0x10B6 0x0000 NOP
;TCC.c,54 :: PORTD.B3 = 0;
0x10B8 0x9683 BCF PORTD, 3
;TCC.c,51 :: for(i = 0; i < 3; i++){
0x10BA 0x4B1A INFSNZ main_i_L0, 1, 1
0x10BC 0x2B1B INCF main_i_L0+1, 1, 1
;TCC.c,55 :: }
0x10BE 0xD7E8 BRA L_main10
L_main11:
;TCC.c,56 :: }
L_main8:
;TCC.c,57 :: }
L_main5:
0x10C0 0x0101 MOVLB 1
;TCC.c,58 :: if(option == 'Z'){
0x10C2 0x5107 MOVF _option, 0, 1
0x10C4 0x0A5A XORLW 90
0x10C6 0xE13A BNZ L_main14
;TCC.c,59 :: UART1_Write_Text(ACEPTED);
0x10C8 0x0E41 MOVLW ?lstr3_TCC
0x10CA 0x6F1E MOVWF FARG_UART1_Write_Text_uart_text, 1
0x10CC 0x0E00 MOVLW hi_addr(?lstr3_TCC)
0x10CE 0x6F1F MOVWF FARG_UART1_Write_Text_uart_text+1, 1
0x10D0 0xD89F RCALL _UART1_Write_Text
;TCC.c,60 :: UART1_Write_Text(pointer);
0x10D2 0xF11EC105 MOVFF _pointer, FARG_UART1_Write_Text_uart_text
0x10D6 0xF11FC106 MOVFF _pointer+1, FARG_UART1_Write_Text_uart_text+1
0x10DA 0xD89A RCALL _UART1_Write_Text
;TCC.c,61 :: for(blink = 0; blink < 3; blink++){
0x10DC 0x6B1C CLRF main_blink_L0, 1
0x10DE 0x6B1D CLRF main_blink_L0+1, 1
L_main15:
0x10E0 0x0E00 MOVLW 0
0x10E2 0x5D1D SUBWF main_blink_L0+1, 0, 1
0x10E4 0xE102 BNZ L__main51
0x10E6 0x0E03 MOVLW 3
0x10E8 0x5D1C SUBWF main_blink_L0, 0, 1
L__main51:
0x10EA 0xE213 BC L_main16
;TCC.c,62 :: PORTD.B0 = 0;
0x10EC 0x9083 BCF PORTD, 0
;TCC.c,63 :: delay_ms(300);
0x10EE 0x0E08 MOVLW 8
0x10F0 0x6E0B MOVWF R11, 0
0x10F2 0x0E9D MOVLW 157
0x10F4 0x6E0C MOVWF R12, 0
0x10F6 0x0E05 MOVLW 5
0x10F8 0x6E0D MOVWF R13, 0
L_main18:
0x10FA 0x2E0D DECFSZ R13, 1, 0
0x10FC 0xD7FE BRA L_main18
0x10FE 0x2E0C DECFSZ R12, 1, 0
0x1100 0xD7FC BRA L_main18
0x1102 0x2E0B DECFSZ R11, 1, 0
0x1104 0xD7FA BRA L_main18
0x1106 0x0000 NOP
0x1108 0x0000 NOP
;TCC.c,64 :: PORTD.B0 = 1;
0x110A 0x8083 BSF PORTD, 0
;TCC.c,61 :: for(blink = 0; blink < 3; blink++){
0x110C 0x4B1C INFSNZ main_blink_L0, 1, 1
0x110E 0x2B1D INCF main_blink_L0+1, 1, 1
;TCC.c,65 :: }
0x1110 0xD7E7 BRA L_main15
L_main16:
;TCC.c,66 :: if(SPORTA || SCHAVE){
0x1112 0xB080 BTFSC PORTA, 0
0x1114 0xD003 BRA L__main45
0x1116 0xB280 BTFSC PORTA, 1
0x1118 0xD001 BRA L__main45
0x111A 0xD00F BRA L_main21
L__main45:
;TCC.c,67 :: if(!SPORTA){
0x111C 0xB080 BTFSC PORTA, 0
0x111E 0xD006 BRA L_main22
;TCC.c,68 :: UART1_Write_Text(PORTAX);
0x1120 0x0E15 MOVLW ?lstr4_TCC
0x1122 0x6F1E MOVWF FARG_UART1_Write_Text_uart_text, 1
0x1124 0x0E00 MOVLW hi_addr(?lstr4_TCC)
0x1126 0x6F1F MOVWF FARG_UART1_Write_Text_uart_text+1, 1
0x1128 0xD873 RCALL _UART1_Write_Text
;TCC.c,69 :: }
0x112A 0xD007 BRA L_main23
L_main22:
;TCC.c,70 :: else if(!SCHAVE){
0x112C 0xB280 BTFSC PORTA, 1
0x112E 0xD005 BRA L_main24
;TCC.c,71 :: UART1_Write_Text(CHAVEX);
0x1130 0x0E92 MOVLW ?lstr5_TCC
0x1132 0x6F1E MOVWF FARG_UART1_Write_Text_uart_text, 1
0x1134 0x0E00 MOVLW hi_addr(?lstr5_TCC)
0x1136 0x6F1F MOVWF FARG_UART1_Write_Text_uart_text+1, 1
0x1138 0xD86B RCALL _UART1_Write_Text
;TCC.c,72 :: }
L_main24:
L_main23:
;TCC.c,73 :: }
L_main21:
;TCC.c,74 :: }
0x113A 0xD021 BRA L_main25
L_main14:
;TCC.c,76 :: for(i = 0; i < 3; i++){
0x113C 0x6B1A CLRF main_i_L0, 1
0x113E 0x6B1B CLRF main_i_L0+1, 1
L_main26:
0x1140 0x0E00 MOVLW 0
0x1142 0x5D1B SUBWF main_i_L0+1, 0, 1
0x1144 0xE102 BNZ L__main52
0x1146 0x0E03 MOVLW 3
0x1148 0x5D1A SUBWF main_i_L0, 0, 1
L__main52:
0x114A 0xE217 BC L_main27
;TCC.c,77 :: PORTD.B0 = 1;
0x114C 0x8083 BSF PORTD, 0
;TCC.c,78 :: UART1_Write_Text(WAITING);
0x114E 0x0EDF MOVLW ?lstr6_TCC
0x1150 0x6F1E MOVWF FARG_UART1_Write_Text_uart_text, 1
0x1152 0x0E00 MOVLW hi_addr(?lstr6_TCC)
0x1154 0x6F1F MOVWF FARG_UART1_Write_Text_uart_text+1, 1
0x1156 0xD85C RCALL _UART1_Write_Text
;TCC.c,79 :: PORTD.B0 = 0;
0x1158 0x9083 BCF PORTD, 0
;TCC.c,80 :: delay_ms(500);
0x115A 0x0E0D MOVLW 13
0x115C 0x6E0B MOVWF R11, 0
0x115E 0x0EAF MOVLW 175
0x1160 0x6E0C MOVWF R12, 0
0x1162 0x0EB6 MOVLW 182
0x1164 0x6E0D MOVWF R13, 0
L_main29:
0x1166 0x2E0D DECFSZ R13, 1, 0
0x1168 0xD7FE BRA L_main29
0x116A 0x2E0C DECFSZ R12, 1, 0
0x116C 0xD7FC BRA L_main29
0x116E 0x2E0B DECFSZ R11, 1, 0
0x1170 0xD7FA BRA L_main29
0x1172 0x0000 NOP
;TCC.c,76 :: for(i = 0; i < 3; i++){
0x1174 0x4B1A INFSNZ main_i_L0, 1, 1
0x1176 0x2B1B INCF main_i_L0+1, 1, 1
;TCC.c,81 :: }
0x1178 0xD7E3 BRA L_main26
L_main27:
;TCC.c,82 :: i = 0;
0x117A 0x6B1A CLRF main_i_L0, 1
0x117C 0x6B1B CLRF main_i_L0+1, 1
;TCC.c,83 :: }
L_main25:
;TCC.c,84 :: if(SPORTA == 0 && SCHAVE == 0 && option == 'Z'){//Realizaa verificação dos sensores.
0x117E 0xB080 BTFSC PORTA, 0
0x1180 0xD03C BRA L_main32
0x1182 0xB280 BTFSC PORTA, 1
0x1184 0xD03A BRA L_main32
0x1186 0x5107 MOVF _option, 0, 1
0x1188 0x0A5A XORLW 90
0x118A 0xE137 BNZ L_main32
L__main44:
;TCC.c,85 :: UART1_Write_Text(PROTECTED);
0x118C 0x0EF0 MOVLW ?lstr7_TCC
0x118E 0x6F1E MOVWF FARG_UART1_Write_Text_uart_text, 1
0x1190 0x0E00 MOVLW hi_addr(?lstr7_TCC)
0x1192 0x6F1F MOVWF FARG_UART1_Write_Text_uart_text+1, 1
0x1194 0xD83D RCALL _UART1_Write_Text
;TCC.c,86 :: control = ON;
0x1196 0x0E01 MOVLW 1
0x1198 0x6F18 MOVWF main_control_L0, 1
0x119A 0x0E00 MOVLW 0
0x119C 0x6F19 MOVWF main_control_L0+1, 1
;TCC.c,88 :: PORTD.B1 = 1;
0x119E 0x8283 BSF PORTD, 1
;TCC.c,89 :: PORTD.B2 = 1;
0x11A0 0x8483 BSF PORTD, 2
;TCC.c,94 :: }
L_main34:
;TCC.c,95 :: while(control && option != 'X'){
L_main35:
0x11A2 0x5118 MOVF main_control_L0, 0, 1
0x11A4 0x1119 IORWF main_control_L0+1, 0, 1
0x11A6 0xE01E BZ L_main36
0x11A8 0x5107 MOVF _option, 0, 1
0x11AA 0x0A58 XORLW 88
0x11AC 0xE01B BZ L_main36
L__main43:
;TCC.c,96 :: if (UART1_Data_Ready() == 1) {
0x11AE 0xD84A RCALL _UART1_Data_Ready
0x11B0 0x5000 MOVF R0, 0
0x11B2 0x0A01 XORLW 1
0x11B4 0xE103 BNZ L_main39
;TCC.c,97 :: option = UART1_Read();
0x11B6 0xD84B RCALL _UART1_Read
0x11B8 0xF107C000 MOVFF R0, _option
;TCC.c,98 :: }
L_main39:
;TCC.c,99 :: UART1_Write_Text(STARTED);
0x11BC 0x0EC4 MOVLW ?lstr8_TCC
0x11BE 0x0101 MOVLB 1
0x11C0 0x6F1E MOVWF FARG_UART1_Write_Text_uart_text, 1
0x11C2 0x0E00 MOVLW hi_addr(?lstr8_TCC)
0x11C4 0x6F1F MOVWF FARG_UART1_Write_Text_uart_text+1, 1
0x11C6 0xD824 RCALL _UART1_Write_Text
;TCC.c,100 :: delay_ms(1000);
0x11C8 0x0E1A MOVLW 26
0x11CA 0x6E0B MOVWF R11, 0
0x11CC 0x0E5E MOVLW 94
0x11CE 0x6E0C MOVWF R12, 0
0x11D0 0x0E6E MOVLW 110
0x11D2 0x6E0D MOVWF R13, 0
L_main40:
0x11D4 0x2E0D DECFSZ R13, 1, 0
0x11D6 0xD7FE BRA L_main40
0x11D8 0x2E0C DECFSZ R12, 1, 0
0x11DA 0xD7FC BRA L_main40
0x11DC 0x2E0B DECFSZ R11, 1, 0
0x11DE 0xD7FA BRA L_main40
0x11E0 0x0000 NOP
;TCC.c,101 :: }
0x11E2 0xD7DF BRA L_main35
L_main36:
;TCC.c,102 :: if(option == 'X'){
0x11E4 0x5107 MOVF _option, 0, 1
0x11E6 0x0A58 XORLW 88
0x11E8 0xE107 BNZ L_main41
;TCC.c,103 :: control = OFF;
0x11EA 0x6B18 CLRF main_control_L0, 1
0x11EC 0x6B19 CLRF main_control_L0+1, 1
;TCC.c,104 :: UART1_Write_Text(BLOCKED);
0x11EE 0x0EAB MOVLW ?lstr9_TCC
0x11F0 0x6F1E MOVWF FARG_UART1_Write_Text_uart_text, 1
0x11F2 0x0E00 MOVLW hi_addr(?lstr9_TCC)
0x11F4 0x6F1F MOVWF FARG_UART1_Write_Text_uart_text+1, 1
0x11F6 0xD80C RCALL _UART1_Write_Text
;TCC.c,105 :: }
L_main41:
;TCC.c,106 :: }
0x11F8 0xD002 BRA L_main42
L_main32:
;TCC.c,108 :: PORTD.B1 = 0;
0x11FA 0x9283 BCF PORTD, 1
;TCC.c,109 :: PORTD.B2 = 0;
0x11FC 0x9483 BCF PORTD, 2
;TCC.c,110 :: }
L_main42:
;TCC.c,111 :: }
0x11FE 0xD72B BRA L_main3
;TCC.c,112 :: }
L_end_main:
0x1200 0xD7FF BRA $+0
; end of _main
_UART1_Write:
;__Lib_UART_c67.c,58 ::
;__Lib_UART_c67.c,59 ::
L_UART1_Write3:
0x1202 0xB2AC BTFSC TXSTA, 1
0x1204 0xD002 BRA L_UART1_Write4
;__Lib_UART_c67.c,60 ::
0x1206 0x0000 NOP
0x1208 0xD7FC BRA L_UART1_Write3
L_UART1_Write4:
;__Lib_UART_c67.c,61 ::
0x120A 0xFFADC122 MOVFF FARG_UART1_Write_data_, TXREG
;__Lib_UART_c67.c,62 ::
L_end_UART1_Write:
0x120E 0x0012 RETURN 0
; end of _UART1_Write
_UART1_Write_Text:
;__Lib_UART_c67.c,66 ::
;__Lib_UART_c67.c,67 ::
0x1210 0x0101 MOVLB 1
0x1212 0x6B21 CLRF UART1_Write_Text_counter_L0, 1
;__Lib_UART_c67.c,69 ::
0x1214 0xFFE9C11E MOVFF FARG_UART1_Write_Text_uart_text, FSR0L
0x1218 0xFFEAC11F MOVFF FARG_UART1_Write_Text_uart_text+1, FSR0H
0x121C 0xF120CFEE MOVFF POSTINC0, UART1_Write_Text_data__L0
;__Lib_UART_c67.c,70 ::
L_UART1_Write_Text5:
0x1220 0x5120 MOVF UART1_Write_Text_data__L0, 0, 1
0x1222 0x0A00 XORLW 0
0x1224 0xE00E BZ L_UART1_Write_Text6
;__Lib_UART_c67.c,71 ::
0x1226 0xF122C120 MOVFF UART1_Write_Text_data__L0, FARG_UART1_Write_data_
0x122A 0xDFEB RCALL _UART1_Write
;__Lib_UART_c67.c,72 ::
0x122C 0x0101 MOVLB 1
0x122E 0x2B21 INCF UART1_Write_Text_counter_L0, 1, 1
;__Lib_UART_c67.c,73 ::
0x1230 0x5121 MOVF UART1_Write_Text_counter_L0, 0, 1
0x1232 0x251E ADDWF FARG_UART1_Write_Text_uart_text, 0, 1
0x1234 0x6EE9 MOVWF FSR0L
0x1236 0x0E00 MOVLW 0
0x1238 0x211F ADDWFC FARG_UART1_Write_Text_uart_text+1, 0, 1
0x123A 0x6EEA MOVWF FSR0H
0x123C 0xF120CFEE MOVFF POSTINC0, UART1_Write_Text_data__L0
;__Lib_UART_c67.c,74 ::
0x1240 0xD7EF BRA L_UART1_Write_Text5
L_UART1_Write_Text6:
;__Lib_UART_c67.c,75 ::
L_end_UART1_Write_Text:
0x1242 0x0012 RETURN 0
; end of _UART1_Write_Text
_UART1_Data_Ready:
;__Lib_UART_c67.c,34 ::
;__Lib_UART_c67.c,35 ::
0x1244 0x0E00 MOVLW 0
0x1246 0xBA9E BTFSC PIR1, 5
0x1248 0x0E01 MOVLW 1
0x124A 0x6E00 MOVWF R0
;__Lib_UART_c67.c,36 ::
L_end_UART1_Data_Ready:
0x124C 0x0012 RETURN 0
; end of _UART1_Data_Ready
_UART1_Read:
;__Lib_UART_c67.c,39 ::
;__Lib_UART_c67.c,42 ::
0x124E 0xF001CFAE MOVFF RCREG, R1
;__Lib_UART_c67.c,43 ::
0x1252 0xA2AB BTFSS RCSTA, 1
0x1254 0xD002 BRA L_UART1_Read2
;__Lib_UART_c67.c,44 ::
0x1256 0x98AB BCF RCSTA, 4
;__Lib_UART_c67.c,45 ::
0x1258 0x88AB BSF RCSTA, 4
;__Lib_UART_c67.c,46 ::
L_UART1_Read2:
;__Lib_UART_c67.c,47 ::
0x125A 0xF000C001 MOVFF R1, R0
;__Lib_UART_c67.c,48 ::
L_end_UART1_Read:
0x125E 0x0012 RETURN 0
; end of _UART1_Read
___CC2DW:
;__Lib_System.c,21 ::
;__Lib_System.c,23 ::
_CC2DL_Loop1:
;__Lib_System.c,24 ::
0x1260 0x0009 TBLRD*+
;__Lib_System.c,25 ::
0x1262 0xFFE6CFF5 MOVFF TABLAT, POSTINC1
;__Lib_System.c,26 ::
0x1266 0x0600 DECF R0, 1, 0
;__Lib_System.c,27 ::
0x1268 0xE1FB BNZ _CC2DL_Loop1
;__Lib_System.c,28 ::
0x126A 0x0601 DECF R1, 1, 0
;__Lib_System.c,29 ::
0x126C 0xE1F9 BNZ _CC2DL_Loop1
;__Lib_System.c,31 ::
L_end___CC2DW:
0x126E 0x0012 RETURN 0
; end of ___CC2DW
_board_Init:
;TCC.c,120 :: void board_Init(){//Função de configuração dos bits.
;TCC.c,121 :: TRISC = 0x80;
0x1270 0x0E80 MOVLW 128
0x1272 0x6E94 MOVWF TRISC
;TCC.c,122 :: ADCON1 |= 0x0F;
0x1274 0x0E0F MOVLW 15
0x1276 0x12C1 IORWF ADCON1, 1
;TCC.c,123 :: CMCON |= 7;
0x1278 0x0E07 MOVLW 7
0x127A 0x12B4 IORWF CMCON, 1
;TCC.c,124 :: TRISA = 255;
0x127C 0x0EFF MOVLW 255
0x127E 0x6E92 MOVWF TRISA
;TCC.c,125 :: TRISB = 0b00000000;//define PORTB como saída em todas as portas.
0x1280 0x6A93 CLRF TRISB
;TCC.c,127 :: TRISD = 0b00000000;//define PORTD como saída em todas as portas.
0x1282 0x6A95 CLRF TRISD
;TCC.c,128 :: TRISE = 0b00000000;//define PORTE como saída em todas as portas.
0x1284 0x6A96 CLRF TRISE
;TCC.c,129 :: PORTB = 0;//define PORTB recebendo 0 na entrada.
0x1286 0x6A81 CLRF PORTB
;TCC.c,131 :: PORTD = 0;//define PORTB recebendo 0 na entrada.
0x1288 0x6A83 CLRF PORTD
;TCC.c,132 :: PORTE = 0;//define PORTB recebendo 0 na entrada.
0x128A 0x6A84 CLRF PORTE
;TCC.c,133 :: }
L_end_board_Init:
0x128C 0x0012 RETURN 0
; end of _board_Init
_UART1_Init:
;__Lib_UART_c67.c,15 ::
;__Lib_UART_c67.c,18 ::
0x128E 0x0E02 MOVLW _UART1_Write
0x1290 0x0101 MOVLB 1
0x1292 0x6F08 MOVWF _UART_Wr_Ptr, 1
0x1294 0x0E12 MOVLW hi_addr(_UART1_Write)
0x1296 0x6F09 MOVWF _UART_Wr_Ptr+1, 1
0x1298 0x0E22 MOVLW FARG_UART1_Write_data_
0x129A 0x6F0A MOVWF _UART_Wr_Ptr+2, 1
0x129C 0x0E01 MOVLW hi_addr(FARG_UART1_Write_data_)
0x129E 0x6F0B MOVWF _UART_Wr_Ptr+3, 1
;__Lib_UART_c67.c,19 ::
0x12A0 0x0E4E MOVLW _UART1_Read
0x12A2 0x6F14 MOVWF _UART_Rd_Ptr, 1
0x12A4 0x0E12 MOVLW hi_addr(_UART1_Read)
0x12A6 0x6F15 MOVWF _UART_Rd_Ptr+1, 1
0x12A8 0x0E00 MOVLW 0
0x12AA 0x6F16 MOVWF _UART_Rd_Ptr+2, 1
0x12AC 0x0E00 MOVLW 0
0x12AE 0x6F17 MOVWF _UART_Rd_Ptr+3, 1
;__Lib_UART_c67.c,20 ::
0x12B0 0x0E44 MOVLW _UART1_Data_Ready
0x12B2 0x6F10 MOVWF _UART_Rdy_Ptr, 1
0x12B4 0x0E12 MOVLW hi_addr(_UART1_Data_Ready)
0x12B6 0x6F11 MOVWF _UART_Rdy_Ptr+1, 1
0x12B8 0x0E00 MOVLW 0
0x12BA 0x6F12 MOVWF _UART_Rdy_Ptr+2, 1
0x12BC 0x0E00 MOVLW 0
0x12BE 0x6F13 MOVWF _UART_Rdy_Ptr+3, 1
;__Lib_UART_c67.c,21 ::
0x12C0 0x0EFF MOVLW _UART1_Tx_Idle
0x12C2 0x6F0C MOVWF _UART_Tx_Idle_Ptr, 1
0x12C4 0x0EFF MOVLW hi_addr(_UART1_Tx_Idle)
0x12C6 0x6F0D MOVWF _UART_Tx_Idle_Ptr+1, 1
0x12C8 0x0E00 MOVLW 0
0x12CA 0x6F0E MOVWF _UART_Tx_Idle_Ptr+2, 1
0x12CC 0x0E00 MOVLW 0
0x12CE 0x6F0F MOVWF _UART_Tx_Idle_Ptr+3, 1
;__Lib_UART_c67.c,23 ::
0x12D0 0x8AAC BSF TXSTA, 5
;__Lib_UART_c67.c,24 ::
0x12D2 0x0E90 MOVLW 144
0x12D4 0x6EAB MOVWF RCSTA
;__Lib_UART_c67.c,25 ::
0x12D6 0x8E94 BSF TRISC7_bit, BitPos(TRISC7_bit+0)
;__Lib_UART_c67.c,26 ::
0x12D8 0x9C94 BCF TRISC6_bit, BitPos(TRISC6_bit+0)
;__Lib_UART_c67.c,28 ::
L_UART1_Init0:
0x12DA 0xAA9E BTFSS PIR1, 5
0x12DC 0xD003 BRA L_UART1_Init1
;__Lib_UART_c67.c,29 ::
0x12DE 0xF000CFAE MOVFF RCREG, R0
0x12E2 0xD7FB BRA L_UART1_Init0
L_UART1_Init1:
;__Lib_UART_c67.c,30 ::
L_end_UART1_Init:
0x12E4 0x0012 RETURN 0
; end of _UART1_Init
_interruptConfig:
;TCC.c,113 :: void interruptConfig(){
;TCC.c,114 :: RCON.IPEN = 0;
0x12E6 0x9ED0 BCF RCON, 7
;TCC.c,115 :: INTCON.GIE = 1;
0x12E8 0x8EF2 BSF INTCON, 7
;TCC.c,116 :: INTCON.PEIE = 1;
0x12EA 0x8CF2 BSF INTCON, 6
;TCC.c,117 :: INTCON.INT0IE = 1;
0x12EC 0x88F2 BSF INTCON, 4
;TCC.c,118 :: INTCON.INT0IF = 0;
0x12EE 0x92F2 BCF INTCON, 1
;TCC.c,119 :: }
L_end_interruptConfig:
0x12F0 0x0012 RETURN 0
; end of _interruptConfig
_interrupt:
;TCC.c,25 :: void interrupt(){
;TCC.c,26 :: if(INTCON.INT0IF == 1){
0x12F2 0xA2F2 BTFSS INTCON, 1
0x12F4 0xD00C BRA L_interrupt0
;TCC.c,27 :: pointer = &option;
0x12F6 0x0E07 MOVLW _option
0x12F8 0x0101 MOVLB 1
0x12FA 0x6F05 MOVWF _pointer, 1
0x12FC 0x0E01 MOVLW hi_addr(_option)
0x12FE 0x6F06 MOVWF _pointer+1, 1
;TCC.c,28 :: *pointer = 'X';
0x1300 0xFFE1C105 MOVFF _pointer, FSR1L
0x1304 0xFFE2C106 MOVFF _pointer+1, FSR1H
0x1308 0x0E58 MOVLW 88
0x130A 0x6EE6 MOVWF POSTINC1
;TCC.c,29 :: INTCON.INT0IF = 0;
0x130C 0x92F2 BCF INTCON, 1
;TCC.c,30 :: }
L_interrupt0:
;TCC.c,31 :: }
L_end_interrupt:
L__interrupt48:
0x130E 0x0011 RETFIE 1
; end of _interrupt
0x1400 0xF015EE10 LFSR 1, 21
0x1404 0x0EF0 MOVLW 240
0x1406 0x6E00 MOVWF R0
0x1408 0x0E01 MOVLW 1
0x140A 0x6E01 MOVWF R1
0x140C 0x0E10 MOVLW 16
0x140E 0x6EF6 MOVWF 4086
0x1410 0x0E13 MOVLW 19
0x1412 0x6EF7 MOVWF TBLPTRH
0x1414 0x0E00 MOVLW 0
0x1416 0x6EF8 MOVWF TBLPTRU
0x1418 0xF009EC30 CALL 4704, 0
0x141C 0x0012 RETURN 0
;TCC.c,0 :: ?ICS?lstr4_TCC
0x1310 0x6741 ;?ICS?lstr4_TCC+0
0x1312 0x6175 ;?ICS?lstr4_TCC+2
0x1314 0x6472 ;?ICS?lstr4_TCC+4
0x1316 0x6E61 ;?ICS?lstr4_TCC+6
0x1318 0x6F64 ;?ICS?lstr4_TCC+8
0x131A 0x7020 ;?ICS?lstr4_TCC+10
0x131C 0x726F ;?ICS?lstr4_TCC+12
0x131E 0x6174 ;?ICS?lstr4_TCC+14
0x1320 0x2E2E ;?ICS?lstr4_TCC+16
0x1322 0x202E ;?ICS?lstr4_TCC+18
0x1324 0x0A0D ;?ICS?lstr4_TCC+20
0x1326 0x00 ;?ICS?lstr4_TCC+22
; end of ?ICS?lstr4_TCC
;TCC.c,0 :: ?ICS?lstr1_TCC
0x1327 0x6E49 ;?ICS?lstr1_TCC+0
0x1329 0x6369 ;?ICS?lstr1_TCC+2
0x132B 0x6169 ;?ICS?lstr1_TCC+4
0x132D 0x646E ;?ICS?lstr1_TCC+6
0x132F 0x206F ;?ICS?lstr1_TCC+8
0x1331 0x6973 ;?ICS?lstr1_TCC+10
0x1333 0x7473 ;?ICS?lstr1_TCC+12
0x1335 0x6D65 ;?ICS?lstr1_TCC+14
0x1337 0x0D61 ;?ICS?lstr1_TCC+16
0x1339 0x000A ;?ICS?lstr1_TCC+18
0x133B 0x00 ;?ICS?lstr1_TCC+20
; end of ?ICS?lstr1_TCC
;TCC.c,0 :: ?ICS?lstr3_TCC
0x133C 0x204F ;?ICS?lstr3_TCC+0
0x133E 0x6164 ;?ICS?lstr3_TCC+2
0x1340 0x6F64 ;?ICS?lstr3_TCC+4
0x1342 0x6420 ;?ICS?lstr3_TCC+6
0x1344 0x2065 ;?ICS?lstr3_TCC+8
0x1346 0x6361 ;?ICS?lstr3_TCC+10
0x1348 0x6F69 ;?ICS?lstr3_TCC+12
0x134A 0x616E ;?ICS?lstr3_TCC+14
0x134C 0x656D ;?ICS?lstr3_TCC+16
0x134E 0x746E ;?ICS?lstr3_TCC+18
0x1350 0x206F ;?ICS?lstr3_TCC+20
0x1352 0x6F66 ;?ICS?lstr3_TCC+22
0x1354 0x2069 ;?ICS?lstr3_TCC+24
0x1356 0x6572 ;?ICS?lstr3_TCC+26
0x1358 0x6563 ;?ICS?lstr3_TCC+28
0x135A 0x6962 ;?ICS?lstr3_TCC+30
0x135C 0x6F64 ;?ICS?lstr3_TCC+32
0x135E 0x0A0D ;?ICS?lstr3_TCC+34
0x1360 0x00 ;?ICS?lstr3_TCC+36
; end of ?ICS?lstr3_TCC
;TCC.c,0 :: ?ICS?lstr2_TCC
0x1361 0x6C41 ;?ICS?lstr2_TCC+0
0x1363 0x7567 ;?ICS?lstr2_TCC+2
0x1365 0x206D ;?ICS?lstr2_TCC+4
0x1367 0x7265 ;?ICS?lstr2_TCC+6
0x1369 0x6F72 ;?ICS?lstr2_TCC+8
0x136B 0x6F20 ;?ICS?lstr2_TCC+10
0x136D 0x6F63 ;?ICS?lstr2_TCC+12
0x136F 0x7272 ;?ICS?lstr2_TCC+14
0x1371 0x7565 ;?ICS?lstr2_TCC+16
0x1373 0x6E20 ;?ICS?lstr2_TCC+18
0x1375 0x206F ;?ICS?lstr2_TCC+20
0x1377 0x7270 ;?ICS?lstr2_TCC+22
0x1379 0x636F ;?ICS?lstr2_TCC+24
0x137B 0x7365 ;?ICS?lstr2_TCC+26
0x137D 0x6F73 ;?ICS?lstr2_TCC+28
0x137F 0x6420 ;?ICS?lstr2_TCC+30
0x1381 0x2065 ;?ICS?lstr2_TCC+32
0x1383 0x6F63 ;?ICS?lstr2_TCC+34
0x1385 0x656E ;?ICS?lstr2_TCC+36
0x1387 0xE378 ;?ICS?lstr2_TCC+38
0x1389 0x0D6F ;?ICS?lstr2_TCC+40
0x138B 0x000A ;?ICS?lstr2_TCC+42
; end of ?ICS?lstr2_TCC
;TCC.c,0 :: ?ICS?lstr5_TCC
0x138D 0x6741 ;?ICS?lstr5_TCC+0
0x138F 0x6175 ;?ICS?lstr5_TCC+2
0x1391 0x6472 ;?ICS?lstr5_TCC+4
0x1393 0x6E61 ;?ICS?lstr5_TCC+6
0x1395 0x6F64 ;?ICS?lstr5_TCC+8
0x1397 0x6920 ;?ICS?lstr5_TCC+10
0x1399 0x6E67 ;?ICS?lstr5_TCC+12
0x139B 0xE769 ;?ICS?lstr5_TCC+14
0x139D 0x6FE3 ;?ICS?lstr5_TCC+16
0x139F 0x2E2E ;?ICS?lstr5_TCC+18
0x13A1 0x202E ;?ICS?lstr5_TCC+20
0x13A3 0x0A0D ;?ICS?lstr5_TCC+22
0x13A5 0x00 ;?ICS?lstr5_TCC+24
; end of ?ICS?lstr5_TCC
;TCC.c,0 :: ?ICS?lstr9_TCC
0x13A6 0x6953 ;?ICS?lstr9_TCC+0
0x13A8 0x7473 ;?ICS?lstr9_TCC+2
0x13AA 0x6D65 ;?ICS?lstr9_TCC+4
0x13AC 0x2061 ;?ICS?lstr9_TCC+6
0x13AE 0x6D65 ;?ICS?lstr9_TCC+8
0x13B0 0x6220 ;?ICS?lstr9_TCC+10
0x13B2 0x6F6C ;?ICS?lstr9_TCC+12
0x13B4 0x7571 ;?ICS?lstr9_TCC+14
0x13B6 0x6165 ;?ICS?lstr9_TCC+16
0x13B8 0x6F64 ;?ICS?lstr9_TCC+18
0x13BA 0x202E ;?ICS?lstr9_TCC+20
0x13BC 0x0A0D ;?ICS?lstr9_TCC+22
0x13BE 0x00 ;?ICS?lstr9_TCC+24
; end of ?ICS?lstr9_TCC
;TCC.c,0 :: ?ICS?lstr8_TCC
0x13BF 0x6953 ;?ICS?lstr8_TCC+0
0x13C1 0x7473 ;?ICS?lstr8_TCC+2
0x13C3 0x6D65 ;?ICS?lstr8_TCC+4
0x13C5 0x2061 ;?ICS?lstr8_TCC+6
0x13C7 0x6D65 ;?ICS?lstr8_TCC+8
0x13C9 0x6620 ;?ICS?lstr8_TCC+10
0x13CB 0x6E75 ;?ICS?lstr8_TCC+12
0x13CD 0x6963 ;?ICS?lstr8_TCC+14
0x13CF 0x6E6F ;?ICS?lstr8_TCC+16
0x13D1 0x6E61 ;?ICS?lstr8_TCC+18
0x13D3 0x6F64 ;?ICS?lstr8_TCC+20
0x13D5 0x202E ;?ICS?lstr8_TCC+22
0x13D7 0x0A0D ;?ICS?lstr8_TCC+24
0x13D9 0x00 ;?ICS?lstr8_TCC+26
; end of ?ICS?lstr8_TCC
;TCC.c,0 :: ?ICS?lstr6_TCC
0x13DA 0x6157 ;?ICS?lstr6_TCC+0
0x13DC 0x7469 ;?ICS?lstr6_TCC+2
0x13DE 0x6E69 ;?ICS?lstr6_TCC+4
0x13E0 0x2067 ;?ICS?lstr6_TCC+6
0x13E2 0x7473 ;?ICS?lstr6_TCC+8
0x13E4 0x7261 ;?ICS?lstr6_TCC+10
0x13E6 0x2074 ;?ICS?lstr6_TCC+12
0x13E8 0x0A0D ;?ICS?lstr6_TCC+14
0x13EA 0x00 ;?ICS?lstr6_TCC+16
; end of ?ICS?lstr6_TCC
;TCC.c,0 :: ?ICS?lstr7_TCC
0x13EB 0x6953 ;?ICS?lstr7_TCC+0
0x13ED 0x7473 ;?ICS?lstr7_TCC+2
0x13EF 0x6D65 ;?ICS?lstr7_TCC+4
0x13F1 0x2061 ;?ICS?lstr7_TCC+6
0x13F3 0x7270 ;?ICS?lstr7_TCC+8
0x13F5 0x746F ;?ICS?lstr7_TCC+10
0x13F7 0x6765 ;?ICS?lstr7_TCC+12
0x13F9 0x6469 ;?ICS?lstr7_TCC+14
0x13FB 0x206F ;?ICS?lstr7_TCC+16
0x13FD 0x0A0D ;?ICS?lstr7_TCC+18
0x13FF 0x00 ;?ICS?lstr7_TCC+20
; end of ?ICS?lstr7_TCC
Symbol List:
//** Routines locations **
//ADDRESS SIZE PROCEDURE
//----------------------------------------------
0x1000 [514] _main
0x1202 [14] _UART1_Write
0x1210 [52] _UART1_Write_Text
0x1244 [10] _UART1_Data_Ready
0x124E [18] _UART1_Read
0x1260 [16] ___CC2DW
0x1270 [30] _board_Init
0x128E [88] _UART1_Init
0x12E6 [12] _interruptConfig
0x12F2 [30] _interrupt
//** Variables locations **
//ADDRESS SIZE VARIABLE
//----------------------------------------------
0x0000 [1] UART1_Init_tmp_L0
0x0000 [1] R0
0x0001 [1] UART1_Read___tmp_UART1_Read_L0
0x0001 [1] R1
0x0002 [1] R2
0x0003 [1] R3
0x0004 [1] R4
0x0005 [1] R5
0x0006 [1] R6
0x0007 [1] R7
0x0008 [1] R8
0x0009 [1] R9
0x000A [1] R10
0x000B [1] R11
0x000C [1] R12
0x000D [1] R13
0x000E [1] R14
0x000F [1] R15
0x0010 [1] R16
0x0011 [1] R17
0x0012 [1] R18
0x0013 [1] R19
0x0014 [1] R20
0x0015 [23] ?lstr4_TCC
0x002C [21] ?lstr1_TCC
0x0041 [37] ?lstr3_TCC
0x0066 [44] ?lstr2_TCC
0x0092 [25] ?lstr5_TCC
0x00AB [25] ?lstr9_TCC
0x00C4 [27] ?lstr8_TCC
0x00DF [17] ?lstr6_TCC
0x00F0 [21] ?lstr7_TCC
0x0105 [2] _pointer
0x0107 [1] _option
0x0108 [4] _UART_Wr_Ptr
0x010C [4] _UART_Tx_Idle_Ptr
0x0110 [4] _UART_Rdy_Ptr
0x0114 [4] _UART_Rd_Ptr
0x0118 [2] main_control_L0
0x011A [2] main_i_L0
0x011C [2] main_blink_L0
0x011E [2] FARG_UART1_Write_Text_uart_text
0x0120 [1] UART1_Write_Text_data__L0
0x0121 [1] UART1_Write_Text_counter_L0
0x0122 [1] FARG_UART1_Write_data_
0x0F80 [1] PORTA
0x0F80 [0] SCHAVE
0x0F80 [0] SPORTA
0x0F81 [1] PORTB
0x0F83 [1] PORTD
0x0F84 [1] PORTE
0x0F92 [1] TRISA
0x0F93 [1] TRISB
0x0F94 [0] TRISC7_bit
0x0F94 [1] TRISC
0x0F94 [0] TRISC6_bit
0x0F95 [1] TRISD
0x0F96 [1] TRISE
0x0F9E [1] PIR1
0x0FAB [1] RCSTA
0x0FAC [1] TXSTA
0x0FAD [1] TXREG
0x0FAE [1] RCREG
0x0FAF [1] SPBRG
0x0FB0 [1] SPBRGH
0x0FB4 [1] CMCON
0x0FB8 [1] BAUDCON
0x0FC1 [1] ADCON1
0x0FD0 [1] RCON
0x0FD8 [1] STATUS
0x0FD9 [1] FSR2L
0x0FDA [1] FSR2H
0x0FDE [1] POSTINC2
0x0FE0 [1] BSR
0x0FE1 [1] FSR1L
0x0FE2 [1] FSR1H
0x0FE4 [1] PREINC1
0x0FE6 [1] POSTINC1
0x0FE7 [1] INDF1
0x0FE8 [1] WREG
0x0FE9 [1] FSR0L
0x0FEA [1] FSR0H
0x0FEE [1] POSTINC0
0x0FF2 [1] INTCON
0x0FF3 [1] PRODL
0x0FF4 [1] PRODH
0x0FF5 [1] TABLAT
0x0FF6 [1] TBLPTRL
0x0FF7 [1] TBLPTRH
0x0FF8 [1] TBLPTRU
//** Constants locations **
//ADDRESS SIZE CONSTANT
//----------------------------------------------
0x1310 [23] ?ICS?lstr4_TCC
0x1327 [21] ?ICS?lstr1_TCC
0x133C [37] ?ICS?lstr3_TCC
0x1361 [44] ?ICS?lstr2_TCC
0x138D [25] ?ICS?lstr5_TCC
0x13A6 [25] ?ICS?lstr9_TCC
0x13BF [27] ?ICS?lstr8_TCC
0x13DA [17] ?ICS?lstr6_TCC
0x13EB [21] ?ICS?lstr7_TCC