@@ -7,6 +7,7 @@ use gdbstub::outputln;
7
7
8
8
use log:: debug;
9
9
10
+ use crate :: bus:: Bus ;
10
11
use crate :: MemoryMapConfig ;
11
12
use crate :: gdb:: simulation;
12
13
@@ -94,38 +95,56 @@ impl SingleThreadBase for ZmuTarget {
94
95
regs. r = self . simulation . processor . r0_12 ;
95
96
regs. sp = self . simulation . processor . get_r ( Reg :: SP ) ;
96
97
regs. lr = self . simulation . processor . lr ;
97
- regs. pc = self . simulation . processor . get_pc ( ) ;
98
+ regs. pc = self . simulation . processor . pc ;
98
99
regs. cpsr = self . simulation . processor . cfsr ;
99
100
Ok ( ( ) )
100
101
}
101
102
102
103
#[ inline( never) ]
103
104
fn write_registers (
104
105
& mut self ,
105
- _regs : & gdbstub_arch:: arm:: reg:: ArmCoreRegs
106
+ regs : & gdbstub_arch:: arm:: reg:: ArmCoreRegs
106
107
) -> TargetResult < ( ) , Self > {
107
108
debug ! ( "> write_registers" ) ;
109
+ self . simulation . processor . r0_12 = regs. r ;
110
+ self . simulation . processor . set_r ( Reg :: SP , regs. sp ) ;
111
+ self . simulation . processor . lr = regs. lr ;
112
+ self . simulation . processor . pc = regs. pc ;
113
+ self . simulation . processor . cfsr = regs. cpsr ;
108
114
Ok ( ( ) )
109
115
}
110
116
111
117
#[ inline( never) ]
112
118
fn read_addrs (
113
119
& mut self ,
114
- _start_addr : u32 ,
120
+ start_addr : u32 ,
115
121
data : & mut [ u8 ] ,
116
122
) -> TargetResult < usize , Self > {
117
- debug ! ( "> read_addrs" ) ;
118
- data. iter_mut ( ) . for_each ( |b| * b = 0x55 ) ;
123
+ for i in 0 ..data. len ( ) {
124
+ match self . simulation . processor . read8 ( start_addr + i as u32 ) {
125
+ Ok ( b) => data[ i] = b,
126
+ Err ( _) => {
127
+ return Ok ( i) ;
128
+ }
129
+ }
130
+ }
119
131
Ok ( data. len ( ) )
120
132
}
121
133
122
134
#[ inline( never) ]
123
135
fn write_addrs (
124
136
& mut self ,
125
- _start_addr : u32 ,
126
- _data : & [ u8 ] ,
137
+ start_addr : u32 ,
138
+ data : & [ u8 ] ,
127
139
) -> TargetResult < ( ) , Self > {
128
- debug ! ( "> write_addrs" ) ;
140
+ for i in 0 ..data. len ( ) {
141
+ match self . simulation . processor . write8 ( start_addr + i as u32 , data[ i] ) {
142
+ Ok ( _) => ( ) ,
143
+ Err ( _) => {
144
+ return Err ( target:: TargetError :: NonFatal ) ;
145
+ }
146
+ }
147
+ }
129
148
Ok ( ( ) )
130
149
}
131
150
0 commit comments