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Merge pull request #53 from asanza/add_support_for_write_read_addresses_with_gdb
add support for writing and reading addresses with gdb.
2 parents ff8b008 + de35644 commit 2a2c510

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+27
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zmu_cortex_m/src/gdb/target.rs

Lines changed: 27 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -7,6 +7,7 @@ use gdbstub::outputln;
77

88
use log::debug;
99

10+
use crate::bus::Bus;
1011
use crate::MemoryMapConfig;
1112
use crate::gdb::simulation;
1213

@@ -94,38 +95,56 @@ impl SingleThreadBase for ZmuTarget {
9495
regs.r = self.simulation.processor.r0_12;
9596
regs.sp = self.simulation.processor.get_r(Reg::SP);
9697
regs.lr = self.simulation.processor.lr;
97-
regs.pc = self.simulation.processor.get_pc();
98+
regs.pc = self.simulation.processor.pc;
9899
regs.cpsr = self.simulation.processor.cfsr;
99100
Ok(())
100101
}
101102

102103
#[inline(never)]
103104
fn write_registers(
104105
&mut self,
105-
_regs: &gdbstub_arch::arm::reg::ArmCoreRegs
106+
regs: &gdbstub_arch::arm::reg::ArmCoreRegs
106107
) -> TargetResult<(), Self> {
107108
debug!("> write_registers");
109+
self.simulation.processor.r0_12 = regs.r;
110+
self.simulation.processor.set_r(Reg::SP, regs.sp);
111+
self.simulation.processor.lr = regs.lr;
112+
self.simulation.processor.pc = regs.pc;
113+
self.simulation.processor.cfsr = regs.cpsr;
108114
Ok(())
109115
}
110116

111117
#[inline(never)]
112118
fn read_addrs(
113119
&mut self,
114-
_start_addr: u32,
120+
start_addr: u32,
115121
data: &mut [u8],
116122
) -> TargetResult<usize, Self> {
117-
debug!("> read_addrs");
118-
data.iter_mut().for_each(|b| *b = 0x55);
123+
for i in 0..data.len() {
124+
match self.simulation.processor.read8(start_addr + i as u32) {
125+
Ok(b) => data[i] = b,
126+
Err(_) => {
127+
return Ok(i);
128+
}
129+
}
130+
}
119131
Ok(data.len())
120132
}
121133

122134
#[inline(never)]
123135
fn write_addrs(
124136
&mut self,
125-
_start_addr: u32,
126-
_data: &[u8],
137+
start_addr: u32,
138+
data: &[u8],
127139
) -> TargetResult<(), Self> {
128-
debug!("> write_addrs");
140+
for i in 0..data.len() {
141+
match self.simulation.processor.write8(start_addr + i as u32, data[i]) {
142+
Ok(_) => (),
143+
Err(_) => {
144+
return Err(target::TargetError::NonFatal);
145+
}
146+
}
147+
}
129148
Ok(())
130149
}
131150

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