diff --git a/src/dotnes.tasks/Utilities/IL2NESWriter.cs b/src/dotnes.tasks/Utilities/IL2NESWriter.cs
index 8bf1e3b..6e9e02c 100644
--- a/src/dotnes.tasks/Utilities/IL2NESWriter.cs
+++ b/src/dotnes.tasks/Utilities/IL2NESWriter.cs
@@ -221,10 +221,9 @@ public void Write(ILInstruction instruction, int operand, ushort sizeOfMain)
                 Write(NESInstruction.BNE_rel, NumberOfInstructionsForBranch(instruction.Offset + operand + 2, sizeOfMain));
                 break;
             case ILOpCode.Brtrue_s:
-                //TODO: implement
-                break;
             case ILOpCode.Brfalse_s:
-                //TODO: implement
+                Write(NESInstruction.CMP, 0);
+                Write(instruction.OpCode == ILOpCode.Brtrue_s ? NESInstruction.BNE_rel : NESInstruction.BEQ_rel, NumberOfInstructionsForBranch(instruction.Offset + operand + 2, sizeOfMain));
                 break;
             default:
                 throw new NotImplementedException($"OpCode {instruction.OpCode} with Int32 operand is not implemented!");
diff --git a/src/dotnes.tests/RoslynTests.cs b/src/dotnes.tests/RoslynTests.cs
index fb134f6..2468734 100644
--- a/src/dotnes.tests/RoslynTests.cs
+++ b/src/dotnes.tests/RoslynTests.cs
@@ -446,34 +446,36 @@ public void PadInput()
                 """,
             expectedAssembly:
                 """
-                A9F6
+                A9FA
                 A285
-                201182  ; JSR _pal_all
-                208982  ; JSR _ppu_on_all
+                201182  ; JSR pal_all
+                208982  ; JSR ppu_on_all
                 A928
                 8D2403
                 A922
                 A286
                 A900
-                202286
+                202686  ; JSR pad_poll
+                C900
+                F015
                 AD2403
-                20A785  ; JSR popa
-                A929
+                20AB85  ; JSR popa
+                A92A
                 8D2403
                 A922
                 A286
                 AD2403
-                20A785  ; JSR popa
+                20AB85  ; JSR popa
                 AD2403
-                20A785  ; JSR popa
+                20AB85  ; JSR popa
                 A910
-                20A785  ; JSR popa
+                20AB85  ; JSR popa
                 A903
-                20A785  ; JSR popa
+                20AB85  ; JSR popa
                 A900
-                20F685  ; JSR _oam_spr
-                20DB82  ; JSR _ppu_wait_frame
-                4C4585  ; JMP $8512
+                20FA85  ; JSR oam_spr
+                20DB82  ; JSR ppu_wait_frame
+                4C4985  ; JMP $8512
                 """);
     }
 }