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1 | | -New in version 0.4.2 since 0.4.1-beta |
| 1 | +New in version 0.4.3 since 0.4.2 |
2 | 2 |
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3 | 3 | *********** |
4 | 4 | * Changes * |
5 | 5 | *********** |
6 | | -- Updated to .NET Core 3.1.102. Newer versions won't work with VHDL code |
7 | | - generation. |
8 | | -- Processes are now run concurrently. There is still some false dependency |
9 | | - between them, due to buses, which results in processes not always running in |
10 | | - parallel. |
11 | | -- Changed when an SME simulation stops. The new default is to stop when all of |
12 | | - the simulation processes have finished. Stopping a simulation can also be |
13 | | - triggered by invoking `Simulation.Current.RequestStop()`. |
14 | | -- Processes can now inherit from an abstract class. |
15 | | -- Updated RAM components to give a warning, instead of throwing an exception, |
16 | | - when doing both a read and a write on the same address. |
| 6 | +- Added the option to not render the buses, when generating the dot graph. This |
| 7 | + allows for a much cleaner graph. |
| 8 | +- Inferred true dual port memory are now more portable. The old definition |
| 9 | + produced inconsistent behaviour, depending on which VHDL simulator was being |
| 10 | + used. |
| 11 | +- Moved function definitions in VHDL into the process definition. This allows |
| 12 | + the functions to access variables and buses, which are local to the process. |
17 | 13 |
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18 | 14 | ********* |
19 | 15 | * Fixes * |
20 | 16 | ********* |
21 | | -- Fixed error with arrays containing default values being expanded into huge |
22 | | - initializations instead of using `others => `. |
23 | | -- Updated unit tests to correctly do testing. |
24 | | -- Updated examples to reflect proper SME. |
25 | | -- All examples are now also run as unit tests, as in they now verify their |
26 | | - output is correct. |
27 | | -- Removed GHDL warning about redundant `others` case. |
28 | | -- Updated Travis for continoues integration of the updated SME on the Debug |
29 | | - build. |
30 | | -- Fixed VHDL simulation, where a `RDY` flag wasn't properly set. |
31 | | -- Fixed overflow error when generating bit strings |
32 | | -- Flipped how arrays are initialized in the RAM templates. |
33 | | -- Added intermediate signals for buses in VHDL, which are both input for |
34 | | - processes and top-level output. |
35 | | -- Fixed handling of non-continoues enums. |
36 | | -- Removed unused flag in state machines. |
37 | | -- Reworked state machine transformations so they are more stable. |
38 | | -- Fixed premature bus loading performed by the .NET debugger. |
39 | | -- Fixed triggering of processes in VHDL. |
40 | | -- Fixed error with generating too many type definitions in VHDL. |
41 | | -- Fixed redundant variable definition for loop invariants. |
42 | | -- Fixed error with inner exceptions silently being "handled". |
43 | | -- Fixed export of arrays in VHDL. |
| 17 | +- Fixed error when initializing multidimensional arrays. |
| 18 | +- Fixed triggering of unclocked processes. Before, clocked processes wouldn't |
| 19 | + properly set the signal triggering unclocked processes. |
| 20 | +- Fixed Windows line endings not being stripped in csv_util.vhdl. |
| 21 | +- Fixed wrong name generation, when the first instance of a process came from |
| 22 | + a different namespace. E.g. when the first process was a |
| 23 | + SME.Components.TrueDualPortRAM, all names would start with SME_Components |
| 24 | + instead of the proper namespace of the process. |
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