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| 1 | +;****************************************************************************** |
| 2 | +;* File Name : startup_stm32l071xx.s |
| 3 | +;* Author : MCD Application Team |
| 4 | +;* Description : STM32l071xx Devices vector table for MDK-ARM toolchain. |
| 5 | +;* This module performs: |
| 6 | +;* - Set the initial SP |
| 7 | +;* - Set the initial PC == Reset_Handler |
| 8 | +;* - Set the vector table entries with the exceptions ISR address |
| 9 | +;* - Branches to __main in the C library (which eventually |
| 10 | +;* calls main()). |
| 11 | +;* After Reset the Cortex-M0+ processor is in Thread mode, |
| 12 | +;* priority is Privileged, and the Stack is set to Main. |
| 13 | +;****************************************************************************** |
| 14 | +;* @attention |
| 15 | +;* |
| 16 | +;* Copyright (c) 2016 STMicroelectronics. |
| 17 | +;* All rights reserved. |
| 18 | +;* |
| 19 | +;* This software component is licensed by ST under BSD 3-Clause license, |
| 20 | +;* the "License"; You may not use this file except in compliance with the |
| 21 | +;* License. You may obtain a copy of the License at: |
| 22 | +;* opensource.org/licenses/BSD-3-Clause |
| 23 | +;* |
| 24 | +;****************************************************************************** |
| 25 | + |
| 26 | + PRESERVE8 |
| 27 | + THUMB |
| 28 | + |
| 29 | + |
| 30 | +; Vector Table Mapped to Address 0 at Reset |
| 31 | + AREA RESET, DATA, READONLY |
| 32 | + EXPORT __Vectors |
| 33 | + EXPORT __Vectors_End |
| 34 | + EXPORT __Vectors_Size |
| 35 | + |
| 36 | + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| |
| 37 | +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack |
| 38 | + DCD Reset_Handler ; Reset Handler |
| 39 | + DCD NMI_Handler ; NMI Handler |
| 40 | + DCD HardFault_Handler ; Hard Fault Handler |
| 41 | + DCD 0 ; Reserved |
| 42 | + DCD 0 ; Reserved |
| 43 | + DCD 0 ; Reserved |
| 44 | + DCD 0 ; Reserved |
| 45 | + DCD 0 ; Reserved |
| 46 | + DCD 0 ; Reserved |
| 47 | + DCD 0 ; Reserved |
| 48 | + DCD SVC_Handler ; SVCall Handler |
| 49 | + DCD 0 ; Reserved |
| 50 | + DCD 0 ; Reserved |
| 51 | + DCD PendSV_Handler ; PendSV Handler |
| 52 | + DCD SysTick_Handler ; SysTick Handler |
| 53 | + |
| 54 | + ; External Interrupts |
| 55 | + DCD WWDG_IRQHandler ; Window Watchdog |
| 56 | + DCD PVD_IRQHandler ; PVD through EXTI Line detect |
| 57 | + DCD RTC_IRQHandler ; RTC through EXTI Line |
| 58 | + DCD FLASH_IRQHandler ; FLASH |
| 59 | + DCD RCC_IRQHandler ; RCC |
| 60 | + DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 |
| 61 | + DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 |
| 62 | + DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 |
| 63 | + DCD 0 ; Reserved |
| 64 | + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 |
| 65 | + DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 |
| 66 | + DCD DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 |
| 67 | + DCD ADC1_COMP_IRQHandler ; ADC1, COMP1 and COMP2 |
| 68 | + DCD LPTIM1_IRQHandler ; LPTIM1 |
| 69 | + DCD USART4_5_IRQHandler ; USART4 and USART5 |
| 70 | + DCD TIM2_IRQHandler ; TIM2 |
| 71 | + DCD TIM3_IRQHandler ; TIM3 |
| 72 | + DCD TIM6_IRQHandler ; TIM6 |
| 73 | + DCD TIM7_IRQHandler ; TIM7 |
| 74 | + DCD 0 ; Reserved |
| 75 | + DCD TIM21_IRQHandler ; TIM21 |
| 76 | + DCD I2C3_IRQHandler ; I2C3 |
| 77 | + DCD TIM22_IRQHandler ; TIM22 |
| 78 | + DCD I2C1_IRQHandler ; I2C1 |
| 79 | + DCD I2C2_IRQHandler ; I2C2 |
| 80 | + DCD SPI1_IRQHandler ; SPI1 |
| 81 | + DCD SPI2_IRQHandler ; SPI2 |
| 82 | + DCD USART1_IRQHandler ; USART1 |
| 83 | + DCD USART2_IRQHandler ; USART2 |
| 84 | + DCD LPUART1_IRQHandler ; LPUART1 |
| 85 | + DCD 0 ; Reserved |
| 86 | + DCD 0 ; Reserved |
| 87 | + |
| 88 | +__Vectors_End |
| 89 | + |
| 90 | +__Vectors_Size EQU __Vectors_End - __Vectors |
| 91 | + |
| 92 | + AREA |.text|, CODE, READONLY |
| 93 | + |
| 94 | +; Reset handler routine |
| 95 | +Reset_Handler PROC |
| 96 | + EXPORT Reset_Handler [WEAK] |
| 97 | + IMPORT __main |
| 98 | + IMPORT SystemInit |
| 99 | + LDR R0, =SystemInit |
| 100 | + BLX R0 |
| 101 | + LDR R0, =__main |
| 102 | + BX R0 |
| 103 | + ENDP |
| 104 | + |
| 105 | +; Dummy Exception Handlers (infinite loops which can be modified) |
| 106 | + |
| 107 | +NMI_Handler PROC |
| 108 | + EXPORT NMI_Handler [WEAK] |
| 109 | + B . |
| 110 | + ENDP |
| 111 | +HardFault_Handler\ |
| 112 | + PROC |
| 113 | + EXPORT HardFault_Handler [WEAK] |
| 114 | + B . |
| 115 | + ENDP |
| 116 | +SVC_Handler PROC |
| 117 | + EXPORT SVC_Handler [WEAK] |
| 118 | + B . |
| 119 | + ENDP |
| 120 | +PendSV_Handler PROC |
| 121 | + EXPORT PendSV_Handler [WEAK] |
| 122 | + B . |
| 123 | + ENDP |
| 124 | +SysTick_Handler PROC |
| 125 | + EXPORT SysTick_Handler [WEAK] |
| 126 | + B . |
| 127 | + ENDP |
| 128 | + |
| 129 | +Default_Handler PROC |
| 130 | + |
| 131 | + EXPORT WWDG_IRQHandler [WEAK] |
| 132 | + EXPORT PVD_IRQHandler [WEAK] |
| 133 | + EXPORT RTC_IRQHandler [WEAK] |
| 134 | + EXPORT FLASH_IRQHandler [WEAK] |
| 135 | + EXPORT RCC_IRQHandler [WEAK] |
| 136 | + EXPORT EXTI0_1_IRQHandler [WEAK] |
| 137 | + EXPORT EXTI2_3_IRQHandler [WEAK] |
| 138 | + EXPORT EXTI4_15_IRQHandler [WEAK] |
| 139 | + EXPORT DMA1_Channel1_IRQHandler [WEAK] |
| 140 | + EXPORT DMA1_Channel2_3_IRQHandler [WEAK] |
| 141 | + EXPORT DMA1_Channel4_5_6_7_IRQHandler [WEAK] |
| 142 | + EXPORT ADC1_COMP_IRQHandler [WEAK] |
| 143 | + EXPORT LPTIM1_IRQHandler [WEAK] |
| 144 | + EXPORT USART4_5_IRQHandler [WEAK] |
| 145 | + EXPORT TIM2_IRQHandler [WEAK] |
| 146 | + EXPORT TIM3_IRQHandler [WEAK] |
| 147 | + EXPORT TIM6_IRQHandler [WEAK] |
| 148 | + EXPORT TIM7_IRQHandler [WEAK] |
| 149 | + EXPORT TIM21_IRQHandler [WEAK] |
| 150 | + EXPORT TIM22_IRQHandler [WEAK] |
| 151 | + EXPORT I2C1_IRQHandler [WEAK] |
| 152 | + EXPORT I2C2_IRQHandler [WEAK] |
| 153 | + EXPORT I2C3_IRQHandler [WEAK] |
| 154 | + EXPORT SPI1_IRQHandler [WEAK] |
| 155 | + EXPORT SPI2_IRQHandler [WEAK] |
| 156 | + EXPORT USART1_IRQHandler [WEAK] |
| 157 | + EXPORT USART2_IRQHandler [WEAK] |
| 158 | + EXPORT LPUART1_IRQHandler [WEAK] |
| 159 | + |
| 160 | +WWDG_IRQHandler |
| 161 | +PVD_IRQHandler |
| 162 | +RTC_IRQHandler |
| 163 | +FLASH_IRQHandler |
| 164 | +RCC_IRQHandler |
| 165 | +EXTI0_1_IRQHandler |
| 166 | +EXTI2_3_IRQHandler |
| 167 | +EXTI4_15_IRQHandler |
| 168 | +DMA1_Channel1_IRQHandler |
| 169 | +DMA1_Channel2_3_IRQHandler |
| 170 | +DMA1_Channel4_5_6_7_IRQHandler |
| 171 | +ADC1_COMP_IRQHandler |
| 172 | +LPTIM1_IRQHandler |
| 173 | +USART4_5_IRQHandler |
| 174 | +TIM2_IRQHandler |
| 175 | +TIM3_IRQHandler |
| 176 | +TIM6_IRQHandler |
| 177 | +TIM7_IRQHandler |
| 178 | +TIM21_IRQHandler |
| 179 | +TIM22_IRQHandler |
| 180 | +I2C1_IRQHandler |
| 181 | +I2C2_IRQHandler |
| 182 | +I2C3_IRQHandler |
| 183 | +SPI1_IRQHandler |
| 184 | +SPI2_IRQHandler |
| 185 | +USART1_IRQHandler |
| 186 | +USART2_IRQHandler |
| 187 | +LPUART1_IRQHandler |
| 188 | + |
| 189 | + B . |
| 190 | + |
| 191 | + ENDP |
| 192 | + |
| 193 | + ALIGN |
| 194 | + |
| 195 | +;******************************************************************************* |
| 196 | +; User Stack and Heap initialization |
| 197 | +;******************************************************************************* |
| 198 | + |
| 199 | + END |
| 200 | + |
| 201 | +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** |
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