Skip to content

Commit 2026861

Browse files
authored
Merge pull request ARMmbed#15277 from jeromecoutant/PR_L071KB
STM32L0: add MCU_STM32L071xB support
2 parents 9f326aa + 6a8a52a commit 2026861

File tree

10 files changed

+1196
-0
lines changed

10 files changed

+1196
-0
lines changed

targets/TARGET_STM/TARGET_STM32L0/CMakeLists.txt

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2,6 +2,7 @@
22
# SPDX-License-Identifier: Apache-2.0
33

44
add_subdirectory(TARGET_STM32L053x8 EXCLUDE_FROM_ALL)
5+
add_subdirectory(TARGET_STM32L071xB EXCLUDE_FROM_ALL)
56
add_subdirectory(TARGET_STM32L071xZ EXCLUDE_FROM_ALL)
67
add_subdirectory(TARGET_STM32L072xZ EXCLUDE_FROM_ALL)
78
add_subdirectory(TARGET_STM32L073xZ EXCLUDE_FROM_ALL)
Lines changed: 26 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,26 @@
1+
# Copyright (c) 2020 ARM Limited. All rights reserved.
2+
# SPDX-License-Identifier: Apache-2.0
3+
4+
if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM")
5+
set(STARTUP_FILE TOOLCHAIN_GCC_ARM/startup_stm32l071xx.S)
6+
set(LINKER_FILE TOOLCHAIN_GCC_ARM/stm32l071xb.ld)
7+
elseif(${MBED_TOOLCHAIN} STREQUAL "ARM")
8+
set(STARTUP_FILE TOOLCHAIN_ARM/startup_stm32l071xx.S)
9+
set(LINKER_FILE TOOLCHAIN_ARM/stm32l071xb.sct)
10+
endif()
11+
12+
add_library(mbed-stm32l071xb INTERFACE)
13+
14+
target_include_directories(mbed-stm32l071xb
15+
INTERFACE
16+
.
17+
)
18+
19+
target_sources(mbed-stm32l071xb
20+
INTERFACE
21+
${STARTUP_FILE}
22+
)
23+
24+
mbed_set_linker_script(mbed-stm32l071xb ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE})
25+
26+
target_link_libraries(mbed-stm32l071xb INTERFACE mbed-stm32l0)
Lines changed: 201 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,201 @@
1+
;******************************************************************************
2+
;* File Name : startup_stm32l071xx.s
3+
;* Author : MCD Application Team
4+
;* Description : STM32l071xx Devices vector table for MDK-ARM toolchain.
5+
;* This module performs:
6+
;* - Set the initial SP
7+
;* - Set the initial PC == Reset_Handler
8+
;* - Set the vector table entries with the exceptions ISR address
9+
;* - Branches to __main in the C library (which eventually
10+
;* calls main()).
11+
;* After Reset the Cortex-M0+ processor is in Thread mode,
12+
;* priority is Privileged, and the Stack is set to Main.
13+
;******************************************************************************
14+
;* @attention
15+
;*
16+
;* Copyright (c) 2016 STMicroelectronics.
17+
;* All rights reserved.
18+
;*
19+
;* This software component is licensed by ST under BSD 3-Clause license,
20+
;* the "License"; You may not use this file except in compliance with the
21+
;* License. You may obtain a copy of the License at:
22+
;* opensource.org/licenses/BSD-3-Clause
23+
;*
24+
;******************************************************************************
25+
26+
PRESERVE8
27+
THUMB
28+
29+
30+
; Vector Table Mapped to Address 0 at Reset
31+
AREA RESET, DATA, READONLY
32+
EXPORT __Vectors
33+
EXPORT __Vectors_End
34+
EXPORT __Vectors_Size
35+
36+
IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
37+
__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
38+
DCD Reset_Handler ; Reset Handler
39+
DCD NMI_Handler ; NMI Handler
40+
DCD HardFault_Handler ; Hard Fault Handler
41+
DCD 0 ; Reserved
42+
DCD 0 ; Reserved
43+
DCD 0 ; Reserved
44+
DCD 0 ; Reserved
45+
DCD 0 ; Reserved
46+
DCD 0 ; Reserved
47+
DCD 0 ; Reserved
48+
DCD SVC_Handler ; SVCall Handler
49+
DCD 0 ; Reserved
50+
DCD 0 ; Reserved
51+
DCD PendSV_Handler ; PendSV Handler
52+
DCD SysTick_Handler ; SysTick Handler
53+
54+
; External Interrupts
55+
DCD WWDG_IRQHandler ; Window Watchdog
56+
DCD PVD_IRQHandler ; PVD through EXTI Line detect
57+
DCD RTC_IRQHandler ; RTC through EXTI Line
58+
DCD FLASH_IRQHandler ; FLASH
59+
DCD RCC_IRQHandler ; RCC
60+
DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1
61+
DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3
62+
DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15
63+
DCD 0 ; Reserved
64+
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
65+
DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3
66+
DCD DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7
67+
DCD ADC1_COMP_IRQHandler ; ADC1, COMP1 and COMP2
68+
DCD LPTIM1_IRQHandler ; LPTIM1
69+
DCD USART4_5_IRQHandler ; USART4 and USART5
70+
DCD TIM2_IRQHandler ; TIM2
71+
DCD TIM3_IRQHandler ; TIM3
72+
DCD TIM6_IRQHandler ; TIM6
73+
DCD TIM7_IRQHandler ; TIM7
74+
DCD 0 ; Reserved
75+
DCD TIM21_IRQHandler ; TIM21
76+
DCD I2C3_IRQHandler ; I2C3
77+
DCD TIM22_IRQHandler ; TIM22
78+
DCD I2C1_IRQHandler ; I2C1
79+
DCD I2C2_IRQHandler ; I2C2
80+
DCD SPI1_IRQHandler ; SPI1
81+
DCD SPI2_IRQHandler ; SPI2
82+
DCD USART1_IRQHandler ; USART1
83+
DCD USART2_IRQHandler ; USART2
84+
DCD LPUART1_IRQHandler ; LPUART1
85+
DCD 0 ; Reserved
86+
DCD 0 ; Reserved
87+
88+
__Vectors_End
89+
90+
__Vectors_Size EQU __Vectors_End - __Vectors
91+
92+
AREA |.text|, CODE, READONLY
93+
94+
; Reset handler routine
95+
Reset_Handler PROC
96+
EXPORT Reset_Handler [WEAK]
97+
IMPORT __main
98+
IMPORT SystemInit
99+
LDR R0, =SystemInit
100+
BLX R0
101+
LDR R0, =__main
102+
BX R0
103+
ENDP
104+
105+
; Dummy Exception Handlers (infinite loops which can be modified)
106+
107+
NMI_Handler PROC
108+
EXPORT NMI_Handler [WEAK]
109+
B .
110+
ENDP
111+
HardFault_Handler\
112+
PROC
113+
EXPORT HardFault_Handler [WEAK]
114+
B .
115+
ENDP
116+
SVC_Handler PROC
117+
EXPORT SVC_Handler [WEAK]
118+
B .
119+
ENDP
120+
PendSV_Handler PROC
121+
EXPORT PendSV_Handler [WEAK]
122+
B .
123+
ENDP
124+
SysTick_Handler PROC
125+
EXPORT SysTick_Handler [WEAK]
126+
B .
127+
ENDP
128+
129+
Default_Handler PROC
130+
131+
EXPORT WWDG_IRQHandler [WEAK]
132+
EXPORT PVD_IRQHandler [WEAK]
133+
EXPORT RTC_IRQHandler [WEAK]
134+
EXPORT FLASH_IRQHandler [WEAK]
135+
EXPORT RCC_IRQHandler [WEAK]
136+
EXPORT EXTI0_1_IRQHandler [WEAK]
137+
EXPORT EXTI2_3_IRQHandler [WEAK]
138+
EXPORT EXTI4_15_IRQHandler [WEAK]
139+
EXPORT DMA1_Channel1_IRQHandler [WEAK]
140+
EXPORT DMA1_Channel2_3_IRQHandler [WEAK]
141+
EXPORT DMA1_Channel4_5_6_7_IRQHandler [WEAK]
142+
EXPORT ADC1_COMP_IRQHandler [WEAK]
143+
EXPORT LPTIM1_IRQHandler [WEAK]
144+
EXPORT USART4_5_IRQHandler [WEAK]
145+
EXPORT TIM2_IRQHandler [WEAK]
146+
EXPORT TIM3_IRQHandler [WEAK]
147+
EXPORT TIM6_IRQHandler [WEAK]
148+
EXPORT TIM7_IRQHandler [WEAK]
149+
EXPORT TIM21_IRQHandler [WEAK]
150+
EXPORT TIM22_IRQHandler [WEAK]
151+
EXPORT I2C1_IRQHandler [WEAK]
152+
EXPORT I2C2_IRQHandler [WEAK]
153+
EXPORT I2C3_IRQHandler [WEAK]
154+
EXPORT SPI1_IRQHandler [WEAK]
155+
EXPORT SPI2_IRQHandler [WEAK]
156+
EXPORT USART1_IRQHandler [WEAK]
157+
EXPORT USART2_IRQHandler [WEAK]
158+
EXPORT LPUART1_IRQHandler [WEAK]
159+
160+
WWDG_IRQHandler
161+
PVD_IRQHandler
162+
RTC_IRQHandler
163+
FLASH_IRQHandler
164+
RCC_IRQHandler
165+
EXTI0_1_IRQHandler
166+
EXTI2_3_IRQHandler
167+
EXTI4_15_IRQHandler
168+
DMA1_Channel1_IRQHandler
169+
DMA1_Channel2_3_IRQHandler
170+
DMA1_Channel4_5_6_7_IRQHandler
171+
ADC1_COMP_IRQHandler
172+
LPTIM1_IRQHandler
173+
USART4_5_IRQHandler
174+
TIM2_IRQHandler
175+
TIM3_IRQHandler
176+
TIM6_IRQHandler
177+
TIM7_IRQHandler
178+
TIM21_IRQHandler
179+
TIM22_IRQHandler
180+
I2C1_IRQHandler
181+
I2C2_IRQHandler
182+
I2C3_IRQHandler
183+
SPI1_IRQHandler
184+
SPI2_IRQHandler
185+
USART1_IRQHandler
186+
USART2_IRQHandler
187+
LPUART1_IRQHandler
188+
189+
B .
190+
191+
ENDP
192+
193+
ALIGN
194+
195+
;*******************************************************************************
196+
; User Stack and Heap initialization
197+
;*******************************************************************************
198+
199+
END
200+
201+
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
Lines changed: 57 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,57 @@
1+
#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
2+
; Scatter-Loading Description File
3+
;
4+
; SPDX-License-Identifier: BSD-3-Clause
5+
;******************************************************************************
6+
;* @attention
7+
;*
8+
;* Copyright (c) 2016-2020 STMicroelectronics.
9+
;* All rights reserved.
10+
;*
11+
;* This software component is licensed by ST under BSD 3-Clause license,
12+
;* the "License"; You may not use this file except in compliance with the
13+
;* License. You may obtain a copy of the License at:
14+
;* opensource.org/licenses/BSD-3-Clause
15+
;*
16+
;******************************************************************************
17+
18+
#include "../cmsis_nvic.h"
19+
20+
#if !defined(MBED_APP_START)
21+
#define MBED_APP_START MBED_ROM_START
22+
#endif
23+
24+
#if !defined(MBED_APP_SIZE)
25+
#define MBED_APP_SIZE MBED_ROM_SIZE
26+
#endif
27+
28+
#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE)
29+
/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */
30+
#if defined(MBED_BOOT_STACK_SIZE)
31+
#define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE
32+
#else
33+
#define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400
34+
#endif
35+
#endif
36+
37+
/* Round up VECTORS_SIZE to 8 bytes */
38+
#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) AND ~7)
39+
40+
LR_IROM1 MBED_APP_START MBED_APP_SIZE {
41+
42+
ER_IROM1 MBED_APP_START MBED_APP_SIZE {
43+
*.o (RESET, +First)
44+
*(InRoot$$Sections)
45+
.ANY (+RO)
46+
}
47+
48+
RW_IRAM1 (MBED_RAM_START + VECTORS_SIZE) { ; RW data
49+
.ANY (+RW +ZI)
50+
}
51+
52+
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_START + MBED_RAM_SIZE - MBED_CONF_TARGET_BOOT_STACK_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16)) { ; Heap growing up
53+
}
54+
55+
ARM_LIB_STACK (MBED_RAM_START + MBED_RAM_SIZE) EMPTY -MBED_CONF_TARGET_BOOT_STACK_SIZE { ; Stack region growing down
56+
}
57+
}

0 commit comments

Comments
 (0)