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RolandF77RolandF77
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[PowerPC] dmr extract update assembly operand order (#132083)
The operand order of the assembly for dmr extract instructions has changed since they were added. The results now come before the uses.
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9 files changed

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‎llvm/lib/Target/PowerPC/PPCInstrFutureMMA.td

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -163,14 +163,14 @@ let Predicates = [IsISAFuture] in {
163163
def DMXXEXTFDMR512 : XX3Form_AT3_XABp5_P1<60, 226,
164164
(outs vsrprc:$XAp, vsrprc:$XBp),
165165
(ins wacc:$AT),
166-
"dmxxextfdmr512 $AT, $XAp, $XBp, 0", []> {
166+
"dmxxextfdmr512 $XAp, $XBp, $AT, 0", []> {
167167
let P = 0;
168168
}
169169

170170
def DMXXEXTFDMR512_HI : XX3Form_AT3_XABp5_P1<60, 226,
171171
(outs vsrprc:$XAp, vsrprc:$XBp),
172172
(ins wacc_hi:$AT),
173-
"dmxxextfdmr512 $AT, $XAp, $XBp, 1", []> {
173+
"dmxxextfdmr512 $XAp, $XBp, $AT, 1", []> {
174174
let P = 1;
175175
}
176176

@@ -188,7 +188,7 @@ let Predicates = [IsISAFuture] in {
188188

189189
def DMXXEXTFDMR256 : XX2Form_AT3_XBp5_P2<60, 484, (outs vsrprc:$XBp),
190190
(ins dmrrowp:$AT, u2imm:$P),
191-
"dmxxextfdmr256 $AT, $XBp, $P", []>;
191+
"dmxxextfdmr256 $XBp, $AT, $P", []>;
192192

193193
def DMXXINSTFDMR256 : XX2Form_AT3_XBp5_P2<60, 485, (outs dmrrowp:$AT),
194194
(ins vsrprc:$XBp, u2imm:$P),

‎llvm/test/CodeGen/PowerPC/dmf-outer-product.ll

Lines changed: 24 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -15,10 +15,10 @@ define void @test_dmxvi8gerx4(ptr %vpp, ptr %vcp, ptr %resp) {
1515
; CHECK-NEXT: lxv vs0, 0(r4)
1616
; CHECK-NEXT: lxv v3, 0(r3)
1717
; CHECK-NEXT: dmxvi8gerx4 dmr0, vsp34, vs0
18-
; CHECK-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
18+
; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
1919
; CHECK-NEXT: stxvp vsp34, 96(r5)
2020
; CHECK-NEXT: stxvp vsp36, 64(r5)
21-
; CHECK-NEXT: dmxxextfdmr512 wacc_hi0, vsp34, vsp36, 1
21+
; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
2222
; CHECK-NEXT: stxvp vsp34, 32(r5)
2323
; CHECK-NEXT: stxvp vsp36, 0(r5)
2424
; CHECK-NEXT: blr
@@ -29,10 +29,10 @@ define void @test_dmxvi8gerx4(ptr %vpp, ptr %vcp, ptr %resp) {
2929
; CHECK-BE-NEXT: lxv vs0, 0(r4)
3030
; CHECK-BE-NEXT: lxv v3, 16(r3)
3131
; CHECK-BE-NEXT: dmxvi8gerx4 dmr0, vsp34, vs0
32-
; CHECK-BE-NEXT: dmxxextfdmr512 wacc_hi0, vsp34, vsp36, 1
32+
; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
3333
; CHECK-BE-NEXT: stxvp vsp36, 96(r5)
3434
; CHECK-BE-NEXT: stxvp vsp34, 64(r5)
35-
; CHECK-BE-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
35+
; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
3636
; CHECK-BE-NEXT: stxvp vsp36, 32(r5)
3737
; CHECK-BE-NEXT: stxvp vsp34, 0(r5)
3838
; CHECK-BE-NEXT: blr
@@ -59,10 +59,10 @@ define void @test_dmxvi8gerx4pp(ptr %vop, ptr %vpp, ptr %vcp, ptr %resp) {
5959
; CHECK-NEXT: lxv vs0, 0(r5)
6060
; CHECK-NEXT: lxv v3, 0(r4)
6161
; CHECK-NEXT: dmxvi8gerx4pp dmr0, vsp34, vs0
62-
; CHECK-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
62+
; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
6363
; CHECK-NEXT: stxvp vsp34, 96(r6)
6464
; CHECK-NEXT: stxvp vsp36, 64(r6)
65-
; CHECK-NEXT: dmxxextfdmr512 wacc_hi0, vsp34, vsp36, 1
65+
; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
6666
; CHECK-NEXT: stxvp vsp34, 32(r6)
6767
; CHECK-NEXT: stxvp vsp36, 0(r6)
6868
; CHECK-NEXT: blr
@@ -79,10 +79,10 @@ define void @test_dmxvi8gerx4pp(ptr %vop, ptr %vpp, ptr %vcp, ptr %resp) {
7979
; CHECK-BE-NEXT: lxv vs0, 0(r5)
8080
; CHECK-BE-NEXT: lxv v3, 16(r4)
8181
; CHECK-BE-NEXT: dmxvi8gerx4pp dmr0, vsp34, vs0
82-
; CHECK-BE-NEXT: dmxxextfdmr512 wacc_hi0, vsp34, vsp36, 1
82+
; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
8383
; CHECK-BE-NEXT: stxvp vsp36, 96(r6)
8484
; CHECK-BE-NEXT: stxvp vsp34, 64(r6)
85-
; CHECK-BE-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
85+
; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
8686
; CHECK-BE-NEXT: stxvp vsp36, 32(r6)
8787
; CHECK-BE-NEXT: stxvp vsp34, 0(r6)
8888
; CHECK-BE-NEXT: blr
@@ -110,10 +110,10 @@ define void @test_dmxvi8gerx4spp(ptr %vop, ptr %vpp, ptr %vcp, ptr %resp) {
110110
; CHECK-NEXT: lxv vs0, 0(r5)
111111
; CHECK-NEXT: lxv v3, 0(r4)
112112
; CHECK-NEXT: dmxvi8gerx4spp dmr0, vsp34, vs0
113-
; CHECK-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
113+
; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
114114
; CHECK-NEXT: stxvp vsp34, 96(r6)
115115
; CHECK-NEXT: stxvp vsp36, 64(r6)
116-
; CHECK-NEXT: dmxxextfdmr512 wacc_hi0, vsp34, vsp36, 1
116+
; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
117117
; CHECK-NEXT: stxvp vsp34, 32(r6)
118118
; CHECK-NEXT: stxvp vsp36, 0(r6)
119119
; CHECK-NEXT: blr
@@ -130,10 +130,10 @@ define void @test_dmxvi8gerx4spp(ptr %vop, ptr %vpp, ptr %vcp, ptr %resp) {
130130
; CHECK-BE-NEXT: lxv vs0, 0(r5)
131131
; CHECK-BE-NEXT: lxv v3, 16(r4)
132132
; CHECK-BE-NEXT: dmxvi8gerx4spp dmr0, vsp34, vs0
133-
; CHECK-BE-NEXT: dmxxextfdmr512 wacc_hi0, vsp34, vsp36, 1
133+
; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
134134
; CHECK-BE-NEXT: stxvp vsp36, 96(r6)
135135
; CHECK-BE-NEXT: stxvp vsp34, 64(r6)
136-
; CHECK-BE-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
136+
; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
137137
; CHECK-BE-NEXT: stxvp vsp36, 32(r6)
138138
; CHECK-BE-NEXT: stxvp vsp34, 0(r6)
139139
; CHECK-BE-NEXT: blr
@@ -161,10 +161,10 @@ define void @test_pmdmxvi8gerx4pp(ptr %vop, ptr %vpp, ptr %vcp, ptr %resp) {
161161
; CHECK-NEXT: lxv vs0, 0(r5)
162162
; CHECK-NEXT: lxv v3, 0(r4)
163163
; CHECK-NEXT: pmdmxvi8gerx4pp dmr0, vsp34, vs0, 42, 7, 9
164-
; CHECK-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
164+
; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
165165
; CHECK-NEXT: stxvp vsp34, 96(r6)
166166
; CHECK-NEXT: stxvp vsp36, 64(r6)
167-
; CHECK-NEXT: dmxxextfdmr512 wacc_hi0, vsp34, vsp36, 1
167+
; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
168168
; CHECK-NEXT: stxvp vsp34, 32(r6)
169169
; CHECK-NEXT: stxvp vsp36, 0(r6)
170170
; CHECK-NEXT: blr
@@ -181,10 +181,10 @@ define void @test_pmdmxvi8gerx4pp(ptr %vop, ptr %vpp, ptr %vcp, ptr %resp) {
181181
; CHECK-BE-NEXT: lxv vs0, 0(r5)
182182
; CHECK-BE-NEXT: lxv v3, 16(r4)
183183
; CHECK-BE-NEXT: pmdmxvi8gerx4pp dmr0, vsp34, vs0, 42, 7, 9
184-
; CHECK-BE-NEXT: dmxxextfdmr512 wacc_hi0, vsp34, vsp36, 1
184+
; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
185185
; CHECK-BE-NEXT: stxvp vsp36, 96(r6)
186186
; CHECK-BE-NEXT: stxvp vsp34, 64(r6)
187-
; CHECK-BE-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
187+
; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
188188
; CHECK-BE-NEXT: stxvp vsp36, 32(r6)
189189
; CHECK-BE-NEXT: stxvp vsp34, 0(r6)
190190
; CHECK-BE-NEXT: blr
@@ -206,10 +206,10 @@ define void @test_pmdmxvi8gerx4(ptr %vpp, ptr %vcp, ptr %resp) {
206206
; CHECK-NEXT: lxv vs0, 0(r4)
207207
; CHECK-NEXT: lxv v3, 0(r3)
208208
; CHECK-NEXT: pmdmxvi8gerx4 dmr0, vsp34, vs0, 55, 5, 10
209-
; CHECK-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
209+
; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
210210
; CHECK-NEXT: stxvp vsp34, 96(r5)
211211
; CHECK-NEXT: stxvp vsp36, 64(r5)
212-
; CHECK-NEXT: dmxxextfdmr512 wacc_hi0, vsp34, vsp36, 1
212+
; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
213213
; CHECK-NEXT: stxvp vsp34, 32(r5)
214214
; CHECK-NEXT: stxvp vsp36, 0(r5)
215215
; CHECK-NEXT: blr
@@ -220,10 +220,10 @@ define void @test_pmdmxvi8gerx4(ptr %vpp, ptr %vcp, ptr %resp) {
220220
; CHECK-BE-NEXT: lxv vs0, 0(r4)
221221
; CHECK-BE-NEXT: lxv v3, 16(r3)
222222
; CHECK-BE-NEXT: pmdmxvi8gerx4 dmr0, vsp34, vs0, 55, 5, 10
223-
; CHECK-BE-NEXT: dmxxextfdmr512 wacc_hi0, vsp34, vsp36, 1
223+
; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
224224
; CHECK-BE-NEXT: stxvp vsp36, 96(r5)
225225
; CHECK-BE-NEXT: stxvp vsp34, 64(r5)
226-
; CHECK-BE-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
226+
; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
227227
; CHECK-BE-NEXT: stxvp vsp36, 32(r5)
228228
; CHECK-BE-NEXT: stxvp vsp34, 0(r5)
229229
; CHECK-BE-NEXT: blr
@@ -250,10 +250,10 @@ define dso_local void @test_pmdmxvi8gerx4spp(ptr %vop, ptr %vpp, ptr %vcp, ptr %
250250
; CHECK-NEXT: lxv vs0, 0(r5)
251251
; CHECK-NEXT: lxv v3, 0(r4)
252252
; CHECK-NEXT: pmdmxvi8gerx4spp dmr0, vsp34, vs0, 100, 6, 12
253-
; CHECK-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
253+
; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
254254
; CHECK-NEXT: stxvp vsp34, 96(r6)
255255
; CHECK-NEXT: stxvp vsp36, 64(r6)
256-
; CHECK-NEXT: dmxxextfdmr512 wacc_hi0, vsp34, vsp36, 1
256+
; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
257257
; CHECK-NEXT: stxvp vsp34, 32(r6)
258258
; CHECK-NEXT: stxvp vsp36, 0(r6)
259259
; CHECK-NEXT: blr
@@ -270,10 +270,10 @@ define dso_local void @test_pmdmxvi8gerx4spp(ptr %vop, ptr %vpp, ptr %vcp, ptr %
270270
; CHECK-BE-NEXT: lxv vs0, 0(r5)
271271
; CHECK-BE-NEXT: lxv v3, 16(r4)
272272
; CHECK-BE-NEXT: pmdmxvi8gerx4spp dmr0, vsp34, vs0, 100, 6, 12
273-
; CHECK-BE-NEXT: dmxxextfdmr512 wacc_hi0, vsp34, vsp36, 1
273+
; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
274274
; CHECK-BE-NEXT: stxvp vsp36, 96(r6)
275275
; CHECK-BE-NEXT: stxvp vsp34, 64(r6)
276-
; CHECK-BE-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
276+
; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
277277
; CHECK-BE-NEXT: stxvp vsp36, 32(r6)
278278
; CHECK-BE-NEXT: stxvp vsp34, 0(r6)
279279
; CHECK-BE-NEXT: blr

‎llvm/test/CodeGen/PowerPC/dmr-enable.ll

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -10,21 +10,21 @@ define void @tdmrz(ptr nocapture readonly %vp1, ptr nocapture %resp) {
1010
; CHECK-LABEL: tdmrz:
1111
; CHECK: # %bb.0: # %entry
1212
; CHECK-NEXT: dmsetdmrz dmr0
13-
; CHECK-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
13+
; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
1414
; CHECK-NEXT: stxvp vsp34, 96(r4)
1515
; CHECK-NEXT: stxvp vsp36, 64(r4)
16-
; CHECK-NEXT: dmxxextfdmr512 wacc_hi0, vsp34, vsp36, 1
16+
; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
1717
; CHECK-NEXT: stxvp vsp34, 32(r4)
1818
; CHECK-NEXT: stxvp vsp36, 0(r4)
1919
; CHECK-NEXT: blr
2020
;
2121
; CHECK-BE-LABEL: tdmrz:
2222
; CHECK-BE: # %bb.0: # %entry
2323
; CHECK-BE-NEXT: dmsetdmrz dmr0
24-
; CHECK-BE-NEXT: dmxxextfdmr512 wacc_hi0, vsp34, vsp36, 1
24+
; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
2525
; CHECK-BE-NEXT: stxvp vsp36, 96(r4)
2626
; CHECK-BE-NEXT: stxvp vsp34, 64(r4)
27-
; CHECK-BE-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
27+
; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
2828
; CHECK-BE-NEXT: stxvp vsp36, 32(r4)
2929
; CHECK-BE-NEXT: stxvp vsp34, 0(r4)
3030
; CHECK-BE-NEXT: blr
@@ -44,10 +44,10 @@ define void @tdmmr(ptr nocapture readonly %vp1, ptr nocapture %resp) {
4444
; CHECK-NEXT: lxvp vsp36, 96(r3)
4545
; CHECK-NEXT: dmxxinstfdmr512 wacc0, vsp36, vsp34, 0
4646
; CHECK-NEXT: dmmr dmr0, dmr0
47-
; CHECK-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
47+
; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
4848
; CHECK-NEXT: stxvp vsp34, 96(r4)
4949
; CHECK-NEXT: stxvp vsp36, 64(r4)
50-
; CHECK-NEXT: dmxxextfdmr512 wacc_hi0, vsp34, vsp36, 1
50+
; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
5151
; CHECK-NEXT: stxvp vsp34, 32(r4)
5252
; CHECK-NEXT: stxvp vsp36, 0(r4)
5353
; CHECK-NEXT: blr
@@ -61,10 +61,10 @@ define void @tdmmr(ptr nocapture readonly %vp1, ptr nocapture %resp) {
6161
; CHECK-BE-NEXT: lxvp vsp36, 0(r3)
6262
; CHECK-BE-NEXT: dmxxinstfdmr512 wacc0, vsp36, vsp34, 0
6363
; CHECK-BE-NEXT: dmmr dmr0, dmr0
64-
; CHECK-BE-NEXT: dmxxextfdmr512 wacc_hi0, vsp34, vsp36, 1
64+
; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
6565
; CHECK-BE-NEXT: stxvp vsp36, 96(r4)
6666
; CHECK-BE-NEXT: stxvp vsp34, 64(r4)
67-
; CHECK-BE-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
67+
; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
6868
; CHECK-BE-NEXT: stxvp vsp36, 32(r4)
6969
; CHECK-BE-NEXT: stxvp vsp34, 0(r4)
7070
; CHECK-BE-NEXT: blr
@@ -91,10 +91,10 @@ define void @tdmxor(ptr nocapture readonly %vp1, ptr %vp2, ptr nocapture %resp)
9191
; CHECK-NEXT: lxvp vsp36, 96(r4)
9292
; CHECK-NEXT: dmxxinstfdmr512 wacc1, vsp36, vsp34, 0
9393
; CHECK-NEXT: dmxor dmr0, dmr1
94-
; CHECK-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
94+
; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
9595
; CHECK-NEXT: stxvp vsp34, 96(r5)
9696
; CHECK-NEXT: stxvp vsp36, 64(r5)
97-
; CHECK-NEXT: dmxxextfdmr512 wacc_hi0, vsp34, vsp36, 1
97+
; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
9898
; CHECK-NEXT: stxvp vsp34, 32(r5)
9999
; CHECK-NEXT: stxvp vsp36, 0(r5)
100100
; CHECK-NEXT: blr
@@ -114,10 +114,10 @@ define void @tdmxor(ptr nocapture readonly %vp1, ptr %vp2, ptr nocapture %resp)
114114
; CHECK-BE-NEXT: lxvp vsp36, 0(r4)
115115
; CHECK-BE-NEXT: dmxxinstfdmr512 wacc1, vsp36, vsp34, 0
116116
; CHECK-BE-NEXT: dmxor dmr0, dmr1
117-
; CHECK-BE-NEXT: dmxxextfdmr512 wacc_hi0, vsp34, vsp36, 1
117+
; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1
118118
; CHECK-BE-NEXT: stxvp vsp36, 96(r5)
119119
; CHECK-BE-NEXT: stxvp vsp34, 64(r5)
120-
; CHECK-BE-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
120+
; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
121121
; CHECK-BE-NEXT: stxvp vsp36, 32(r5)
122122
; CHECK-BE-NEXT: stxvp vsp34, 0(r5)
123123
; CHECK-BE-NEXT: blr

‎llvm/test/CodeGen/PowerPC/mmaplus-acc-spill.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -37,15 +37,15 @@ define void @intrinsics1(<16 x i8> %vc1, <16 x i8> %vc2, <16 x i8> %vc3, <16 x i
3737
; CHECK-NEXT: ld r30, 272(r1)
3838
; CHECK-NEXT: dmxxinstfdmr512 wacc0, vsp60, vsp62, 0
3939
; CHECK-NEXT: xvf16ger2pp wacc0, v2, v4
40-
; CHECK-NEXT: dmxxextfdmr512 wacc0, vsp36, vsp34, 0
40+
; CHECK-NEXT: dmxxextfdmr512 vsp36, vsp34, wacc0, 0
4141
; CHECK-NEXT: stxvp vsp36, 64(r1)
4242
; CHECK-NEXT: stxvp vsp34, 32(r1)
4343
; CHECK-NEXT: bl foo@notoc
4444
; CHECK-NEXT: lxvp vsp34, 64(r1)
4545
; CHECK-NEXT: lxvp vsp36, 32(r1)
4646
; CHECK-NEXT: dmxxinstfdmr512 wacc0, vsp34, vsp36, 0
4747
; CHECK-NEXT: xvf16ger2pp wacc0, v28, v30
48-
; CHECK-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
48+
; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
4949
; CHECK-NEXT: stxv v4, 48(r30)
5050
; CHECK-NEXT: stxv v5, 32(r30)
5151
; CHECK-NEXT: stxv v2, 16(r30)
@@ -84,7 +84,7 @@ define void @intrinsics1(<16 x i8> %vc1, <16 x i8> %vc2, <16 x i8> %vc3, <16 x i
8484
; CHECK-BE-NEXT: ld r30, 368(r1)
8585
; CHECK-BE-NEXT: dmxxinstfdmr512 wacc0, vsp60, vsp62, 0
8686
; CHECK-BE-NEXT: xvf16ger2pp wacc0, v2, v4
87-
; CHECK-BE-NEXT: dmxxextfdmr512 wacc0, vsp36, vsp34, 0
87+
; CHECK-BE-NEXT: dmxxextfdmr512 vsp36, vsp34, wacc0, 0
8888
; CHECK-BE-NEXT: stxvp vsp36, 112(r1)
8989
; CHECK-BE-NEXT: stxvp vsp34, 144(r1)
9090
; CHECK-BE-NEXT: bl foo
@@ -93,7 +93,7 @@ define void @intrinsics1(<16 x i8> %vc1, <16 x i8> %vc2, <16 x i8> %vc3, <16 x i
9393
; CHECK-BE-NEXT: lxvp vsp36, 144(r1)
9494
; CHECK-BE-NEXT: dmxxinstfdmr512 wacc0, vsp34, vsp36, 0
9595
; CHECK-BE-NEXT: xvf16ger2pp wacc0, v28, v30
96-
; CHECK-BE-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
96+
; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0
9797
; CHECK-BE-NEXT: stxv v5, 48(r30)
9898
; CHECK-BE-NEXT: stxv v4, 32(r30)
9999
; CHECK-BE-NEXT: stxv v3, 16(r30)

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