@@ -83,8 +83,8 @@ void VirtRegMap::grow() {
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Virt2SplitMap.resize (NumRegs);
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}
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- void VirtRegMap::assignVirt2Phys (Register virtReg, MCPhysReg physReg) {
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- assert (virtReg.isVirtual () && Register::isPhysicalRegister ( physReg));
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+ void VirtRegMap::assignVirt2Phys (Register virtReg, MCRegister physReg) {
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+ assert (virtReg.isVirtual () && physReg. isPhysical ( ));
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assert (!Virt2PhysMap[virtReg] &&
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" attempt to assign physical register to already mapped "
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" virtual register" );
@@ -221,7 +221,7 @@ class VirtRegRewriter : public MachineFunctionPass {
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bool subRegLiveThrough (const MachineInstr &MI, MCRegister SuperPhysReg) const ;
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LaneBitmask liveOutUndefPhiLanesForUndefSubregDef (
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const LiveInterval &LI, const MachineBasicBlock &MBB, unsigned SubReg,
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- MCPhysReg PhysReg, const MachineInstr &MI) const ;
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+ MCRegister PhysReg, const MachineInstr &MI) const ;
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public:
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static char ID;
@@ -563,7 +563,7 @@ bool VirtRegRewriter::subRegLiveThrough(const MachineInstr &MI,
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// / is assigned to \p LI, which is the main range.
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LaneBitmask VirtRegRewriter::liveOutUndefPhiLanesForUndefSubregDef (
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const LiveInterval &LI, const MachineBasicBlock &MBB, unsigned SubReg,
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- MCPhysReg PhysReg, const MachineInstr &MI) const {
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+ MCRegister PhysReg, const MachineInstr &MI) const {
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LaneBitmask UndefMask = ~TRI->getSubRegIndexLaneMask (SubReg);
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LaneBitmask LiveOutUndefLanes;
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