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[RISCV] Add CSRs and an instruction for Smctr and Ssctr extensions. (#105148)
https://github.com/riscv/riscv-control-transfer-records/releases/tag/v1.0_rc3
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‎clang/test/Driver/print-supported-extensions-riscv.c

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// CHECK-NEXT: zalasr 0.1 'Zalasr' (Load-Acquire and Store-Release Instructions)
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// CHECK-NEXT: zvbc32e 0.7 'Zvbc32e' (Vector Carryless Multiplication with 32-bits elements)
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// CHECK-NEXT: zvkgs 0.7 'Zvkgs' (Vector-Scalar GCM instructions for Cryptography)
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// CHECK-NEXT: smctr 1.0 'Smctr' (Control Transfer Records Machine Level)
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// CHECK-NEXT: smmpm 1.0 'Smmpm' (Machine-level Pointer Masking for M-mode)
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// CHECK-NEXT: smnpm 1.0 'Smnpm' (Machine-level Pointer Masking for next lower privilege mode)
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// CHECK-NEXT: ssctr 1.0 'Ssctr' (Control Transfer Records Supervisor Level)
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// CHECK-NEXT: ssnpm 1.0 'Ssnpm' (Supervisor-level Pointer Masking for next lower privilege mode)
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// CHECK-NEXT: sspm 1.0 'Sspm' (Indicates Supervisor-mode Pointer Masking)
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// CHECK-NEXT: supm 1.0 'Supm' (Indicates User-mode Pointer Masking)

‎clang/test/Preprocessor/riscv-target-features.c

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// Experimental extensions
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// CHECK-NOT: __riscv_smctr{{.*$}}
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// CHECK-NOT: __riscv_smmpm{{.*$}}
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// CHECK-NOT: __riscv_smnpm{{.*$}}
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// CHECK-NOT: __riscv_ssctr{{.*$}}
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// CHECK-NOT: __riscv_ssnpm{{.*$}}
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// CHECK-NOT: __riscv_sspm{{.*$}}
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// CHECK-NOT: __riscv_supm{{.*$}}
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// RUN: -o - | FileCheck --check-prefix=CHECK-SUPM-EXT %s
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// CHECK-SUPM-EXT: __riscv_supm 1000000{{$}}
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// RUN: %clang --target=riscv32 -menable-experimental-extensions \
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// RUN: -march=rv32i_smctr1p0 -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-SMCTR-EXT %s
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// RUN: %clang --target=riscv64 -menable-experimental-extensions \
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// RUN: -march=rv64i_smctr1p0 -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-SMCTR-EXT %s
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// CHECK-SMCTR-EXT: __riscv_smctr 1000000{{$}}
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// RUN: %clang --target=riscv32 -menable-experimental-extensions \
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// RUN: -march=rv32i_ssctr1p0 -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-SSCTR-EXT %s
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// RUN: %clang --target=riscv64 -menable-experimental-extensions \
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// RUN: -march=rv64i_ssctr1p0 -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-SSCTR-EXT %s
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// CHECK-SSCTR-EXT: __riscv_ssctr 1000000{{$}}
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// Misaligned
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// RUN: %clang --target=riscv32-unknown-linux-gnu -march=rv32i -E -dM %s \

‎llvm/docs/RISCVUsage.rst

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@@ -303,6 +303,9 @@ The primary goal of experimental support is to assist in the process of ratifica
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``experimental-zvbc32e``, ``experimental-zvkgs``
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LLVM implements the `0.7 release specification <https://github.com/user-attachments/files/16450464/riscv-crypto-spec-vector-extra_v0.0.7.pdf>`__.
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``experimental-smctr``, ``experimental-ssctr``
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LLVM implements the `1.0-rc3 specification <https://github.com/riscv/riscv-control-transfer-records/releases/tag/v1.0_rc3>`__.
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To use an experimental extension from `clang`, you must add `-menable-experimental-extensions` to the command line, and specify the exact version of the experimental extension you are using. To use an experimental extension with LLVM's internal developer tools (e.g. `llc`, `llvm-objdump`, `llvm-mc`), you must prefix the extension name with `experimental-`. Note that you don't need to specify the version with internal tools, and shouldn't include the `experimental-` prefix with `clang`.
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Vendor Extensions

‎llvm/docs/ReleaseNotes.rst

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@@ -114,6 +114,7 @@ Changes to the RISC-V Backend
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means Zve32x and Zve32f will also require Zvl64b. The prior support was
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largely untested.
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* The ``Zvbc32e`` and ``Zvkgs`` extensions are now supported experimentally.
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* Added ``Smctr`` and ``Ssctr`` extensions.
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Changes to the WebAssembly Backend
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----------------------------------

‎llvm/lib/Target/RISCV/RISCVFeatures.td

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@@ -1054,6 +1054,19 @@ def FeatureStdExtSupm
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: RISCVExperimentalExtension<"supm", 1, 0,
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"'Supm' (Indicates User-mode Pointer Masking)">;
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def FeatureStdExtSmctr
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: RISCVExperimentalExtension<"smctr", 1, 0,
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"'Smctr' (Control Transfer Records Machine Level)",
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[FeatureStdExtSscsrind]>;
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def FeatureStdExtSsctr
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: RISCVExperimentalExtension<"ssctr" ,1, 0,
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"'Ssctr' (Control Transfer Records Supervisor Level)",
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[FeatureStdExtSscsrind]>;
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def HasStdExtSmctrOrSsctr : Predicate<"Subtarget->hasStdExtSmctrOrSsctr()">,
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AssemblerPredicate<(any_of FeatureStdExtSmctr, FeatureStdExtSsctr),
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"'Smctr' (Control Transfer Records Machine Level) or "
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"'Ssctr' (Control Transfer Records Supervisor Level)">;
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//===----------------------------------------------------------------------===//
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// Vendor extensions
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//===----------------------------------------------------------------------===//

‎llvm/lib/Target/RISCV/RISCVInstrInfo.td

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@@ -839,6 +839,14 @@ def HLV_D : HLoad_r<0b0110110, 0b00000, "hlv.d">, Sched<[]>;
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def HSV_D : HStore_rr<0b0110111, "hsv.d">, Sched<[]>;
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}
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let Predicates = [HasStdExtSmctrOrSsctr] in {
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def SCTRCLR : Priv<"sctrclr", 0b0001000>, Sched<[]> {
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let rd = 0;
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let rs1 = 0;
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let rs2 = 0b00100;
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}
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}
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//===----------------------------------------------------------------------===//
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// Debug instructions
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//===----------------------------------------------------------------------===//

‎llvm/lib/Target/RISCV/RISCVSystemOperands.td

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@@ -455,3 +455,12 @@ def : SysReg<"mnscratch", 0x740>;
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def : SysReg<"mnepc", 0x741>;
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def : SysReg<"mncause", 0x742>;
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def : SysReg<"mnstatus", 0x744>;
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//===-----------------------------------------------
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// Control Transfer Records CSRs
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//===-----------------------------------------------
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def : SysReg<"sctrctl", 0x14e>;
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def : SysReg<"sctrstatus", 0x14f>;
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def : SysReg<"sctrdepth", 0x15f>;
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def : SysReg<"vsctrctl", 0x24e>;
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def : SysReg<"mctrctl", 0x34e>;

‎llvm/test/CodeGen/RISCV/attributes.ll

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; RUN: llc -mtriple=riscv32 -mattr=+experimental-smmpm %s -o - | FileCheck --check-prefix=RV32SMMPM %s
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-sspm %s -o - | FileCheck --check-prefix=RV32SSPM %s
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-supm %s -o - | FileCheck --check-prefix=RV32SUPM %s
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-smctr %s -o - | FileCheck --check-prefix=RV32SMCTR %s
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-ssctr %s -o - | FileCheck --check-prefix=RV32SSCTR %s
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; RUN: llc -mtriple=riscv64 %s -o - | FileCheck %s
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; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefixes=CHECK,RV64M %s
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; RUN: llc -mtriple=riscv64 -mattr=+experimental-smmpm %s -o - | FileCheck --check-prefix=RV64SMMPM %s
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; RUN: llc -mtriple=riscv64 -mattr=+experimental-sspm %s -o - | FileCheck --check-prefix=RV64SSPM %s
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; RUN: llc -mtriple=riscv64 -mattr=+experimental-supm %s -o - | FileCheck --check-prefix=RV64SUPM %s
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; RUN: llc -mtriple=riscv64 -mattr=+experimental-smctr %s -o - | FileCheck --check-prefix=RV64SMCTR %s
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; RUN: llc -mtriple=riscv64 -mattr=+experimental-ssctr %s -o - | FileCheck --check-prefix=RV64SSCTR %s
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; Tests for profile features.
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; RUN: llc -mtriple=riscv32 -mattr=+rvi20u32 %s -o - | FileCheck --check-prefix=RVI20U32 %s
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; RV32SMMPM: .attribute 5, "rv32i2p1_smmpm1p0"
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; RV32SSPM: .attribute 5, "rv32i2p1_sspm1p0"
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; RV32SUPM: .attribute 5, "rv32i2p1_supm1p0"
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; RV32SMCTR: .attribute 5, "rv32i2p1_smctr1p0_sscsrind1p0"
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; RV32SSCTR: .attribute 5, "rv32i2p1_sscsrind1p0_ssctr1p0"
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; RV64M: .attribute 5, "rv64i2p1_m2p0_zmmul1p0"
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; RV64ZMMUL: .attribute 5, "rv64i2p1_zmmul1p0"
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; RV64SMMPM: .attribute 5, "rv64i2p1_smmpm1p0"
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; RV64SSPM: .attribute 5, "rv64i2p1_sspm1p0"
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; RV64SUPM: .attribute 5, "rv64i2p1_supm1p0"
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; RV64SMCTR: .attribute 5, "rv64i2p1_smctr1p0_sscsrind1p0"
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; RV64SSCTR: .attribute 5, "rv64i2p1_sscsrind1p0_ssctr1p0"
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; RVI20U32: .attribute 5, "rv32i2p1"
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; RVI20U64: .attribute 5, "rv64i2p1"

‎llvm/test/MC/RISCV/attribute-arch.s

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.attribute arch, "rv64i_supm1p0"
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# CHECK: attribute 5, "rv64i2p1_supm1p0"
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.attribute arch, "rv32i_smctr1p0"
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# CHECK: attribute 5, "rv32i2p1_smctr1p0_sscsrind1p0"
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.attribute arch, "rv32i_ssctr1p0"
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# CHECK: attribute 5, "rv32i2p1_sscsrind1p0_ssctr1p0"

‎llvm/test/MC/RISCV/hypervisor-csr-names.s

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csrrs t1, vstopi, zero
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# uimm12
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csrrs t2, 0xEB0, zero
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##################################
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# Control Transfer Records
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##################################
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# vsctrctl
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# name
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# CHECK-INST: csrrs t1, vsctrctl, zero
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# CHECK-ENC: encoding: [0x73,0x23,0xe0,0x24]
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# CHECK-INST-ALIAS: csrr t1, vsctrctl
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# uimm12
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# CHECK-INST: csrrs t2, vsctrctl, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0xe0,0x24]
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# CHECK-INST-ALIAS: csrr t2, vsctrctl
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csrrs t1, vsctrctl, zero
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# uimm12
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csrrs t2, 0x24E, zero

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