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[RISCV][SLP] Add test coverage for 2^N-1 vector sizes
Mostly copied from the AArch64 coverage for same, but also added a couple tests for reductions which aren't currently supported.
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‎llvm/test/Transforms/SLPVectorizer/RISCV/vec15-base.ll

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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
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; RUN: opt -passes=slp-vectorizer -slp-vectorize-non-power-of-2 -mtriple=riscv64 -mattr=+v -S %s | FileCheck --check-prefixes=NON-POW2 %s
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; RUN: opt -passes=slp-vectorizer -slp-vectorize-non-power-of-2=false -mtriple=riscv64 -mattr=+v -S %s | FileCheck --check-prefixes=POW2-ONLY %s
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define void @v15_load_i8_mul_by_constant_store(ptr %src, ptr noalias %dst) {
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; NON-POW2-LABEL: define void @v15_load_i8_mul_by_constant_store(
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; NON-POW2-SAME: ptr [[SRC:%.*]], ptr noalias [[DST:%.*]]) #[[ATTR0:[0-9]+]] {
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; NON-POW2-NEXT: entry:
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; NON-POW2-NEXT: [[GEP_SRC_0:%.*]] = getelementptr inbounds i8, ptr [[SRC]], i8 0
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; NON-POW2-NEXT: [[TMP0:%.*]] = load <15 x i8>, ptr [[GEP_SRC_0]], align 4
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; NON-POW2-NEXT: [[TMP1:%.*]] = mul nsw <15 x i8> [[TMP0]], <i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10>
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; NON-POW2-NEXT: store <15 x i8> [[TMP1]], ptr [[DST]], align 1
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; NON-POW2-NEXT: ret void
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;
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; POW2-ONLY-LABEL: define void @v15_load_i8_mul_by_constant_store(
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; POW2-ONLY-SAME: ptr [[SRC:%.*]], ptr noalias [[DST:%.*]]) #[[ATTR0:[0-9]+]] {
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; POW2-ONLY-NEXT: entry:
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; POW2-ONLY-NEXT: [[GEP_SRC_0:%.*]] = getelementptr inbounds i8, ptr [[SRC]], i8 0
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; POW2-ONLY-NEXT: [[TMP0:%.*]] = load <8 x i8>, ptr [[GEP_SRC_0]], align 4
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; POW2-ONLY-NEXT: [[TMP1:%.*]] = mul nsw <8 x i8> [[TMP0]], <i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10>
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; POW2-ONLY-NEXT: store <8 x i8> [[TMP1]], ptr [[DST]], align 1
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; POW2-ONLY-NEXT: [[GEP_SRC_8:%.*]] = getelementptr inbounds i8, ptr [[SRC]], i8 8
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; POW2-ONLY-NEXT: [[DST_8:%.*]] = getelementptr i8, ptr [[DST]], i8 8
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; POW2-ONLY-NEXT: [[TMP2:%.*]] = load <4 x i8>, ptr [[GEP_SRC_8]], align 4
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; POW2-ONLY-NEXT: [[TMP3:%.*]] = mul nsw <4 x i8> [[TMP2]], <i8 10, i8 10, i8 10, i8 10>
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; POW2-ONLY-NEXT: store <4 x i8> [[TMP3]], ptr [[DST_8]], align 1
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; POW2-ONLY-NEXT: [[GEP_SRC_12:%.*]] = getelementptr inbounds i8, ptr [[SRC]], i8 12
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; POW2-ONLY-NEXT: [[DST_12:%.*]] = getelementptr i8, ptr [[DST]], i8 12
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; POW2-ONLY-NEXT: [[TMP4:%.*]] = load <2 x i8>, ptr [[GEP_SRC_12]], align 4
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; POW2-ONLY-NEXT: [[TMP5:%.*]] = mul nsw <2 x i8> [[TMP4]], <i8 10, i8 10>
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; POW2-ONLY-NEXT: store <2 x i8> [[TMP5]], ptr [[DST_12]], align 1
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; POW2-ONLY-NEXT: [[GEP_SRC_14:%.*]] = getelementptr inbounds i8, ptr [[SRC]], i8 14
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; POW2-ONLY-NEXT: [[L_SRC_14:%.*]] = load i8, ptr [[GEP_SRC_14]], align 4
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; POW2-ONLY-NEXT: [[MUL_14:%.*]] = mul nsw i8 [[L_SRC_14]], 10
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; POW2-ONLY-NEXT: [[DST_14:%.*]] = getelementptr i8, ptr [[DST]], i8 14
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; POW2-ONLY-NEXT: store i8 [[MUL_14]], ptr [[DST_14]], align 1
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; POW2-ONLY-NEXT: ret void
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;
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entry:
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%gep.src.0 = getelementptr inbounds i8, ptr %src, i8 0
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%l.src.0 = load i8, ptr %gep.src.0, align 4
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%mul.0 = mul nsw i8 %l.src.0, 10
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store i8 %mul.0, ptr %dst
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%gep.src.1 = getelementptr inbounds i8, ptr %src, i8 1
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%l.src.1 = load i8, ptr %gep.src.1, align 4
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%mul.1 = mul nsw i8 %l.src.1, 10
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%dst.1 = getelementptr i8, ptr %dst, i8 1
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store i8 %mul.1, ptr %dst.1
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%gep.src.2 = getelementptr inbounds i8, ptr %src, i8 2
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%l.src.2 = load i8, ptr %gep.src.2, align 4
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%mul.2 = mul nsw i8 %l.src.2, 10
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%dst.2 = getelementptr i8, ptr %dst, i8 2
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store i8 %mul.2, ptr %dst.2
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%gep.src.3 = getelementptr inbounds i8, ptr %src, i8 3
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%l.src.3 = load i8, ptr %gep.src.3, align 4
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%mul.3 = mul nsw i8 %l.src.3, 10
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%dst.3 = getelementptr i8, ptr %dst, i8 3
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store i8 %mul.3, ptr %dst.3
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%gep.src.4 = getelementptr inbounds i8, ptr %src, i8 4
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%l.src.4 = load i8, ptr %gep.src.4, align 4
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%mul.4 = mul nsw i8 %l.src.4, 10
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%dst.4 = getelementptr i8, ptr %dst, i8 4
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store i8 %mul.4, ptr %dst.4
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%gep.src.5 = getelementptr inbounds i8, ptr %src, i8 5
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%l.src.5 = load i8, ptr %gep.src.5, align 4
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%mul.5 = mul nsw i8 %l.src.5, 10
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%dst.5 = getelementptr i8, ptr %dst, i8 5
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store i8 %mul.5, ptr %dst.5
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%gep.src.6 = getelementptr inbounds i8, ptr %src, i8 6
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%l.src.6 = load i8, ptr %gep.src.6, align 4
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%mul.6 = mul nsw i8 %l.src.6, 10
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%dst.6 = getelementptr i8, ptr %dst, i8 6
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store i8 %mul.6, ptr %dst.6
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%gep.src.7 = getelementptr inbounds i8, ptr %src, i8 7
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%l.src.7 = load i8, ptr %gep.src.7, align 4
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%mul.7 = mul nsw i8 %l.src.7, 10
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%dst.7 = getelementptr i8, ptr %dst, i8 7
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store i8 %mul.7, ptr %dst.7
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%gep.src.8 = getelementptr inbounds i8, ptr %src, i8 8
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%l.src.8 = load i8, ptr %gep.src.8, align 4
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%mul.8 = mul nsw i8 %l.src.8, 10
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%dst.8 = getelementptr i8, ptr %dst, i8 8
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store i8 %mul.8, ptr %dst.8
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%gep.src.9 = getelementptr inbounds i8, ptr %src, i8 9
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%l.src.9 = load i8, ptr %gep.src.9, align 4
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%mul.9 = mul nsw i8 %l.src.9, 10
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%dst.9 = getelementptr i8, ptr %dst, i8 9
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store i8 %mul.9, ptr %dst.9
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%gep.src.10 = getelementptr inbounds i8, ptr %src, i8 10
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%l.src.10 = load i8, ptr %gep.src.10, align 4
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%mul.10 = mul nsw i8 %l.src.10, 10
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%dst.10 = getelementptr i8, ptr %dst, i8 10
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store i8 %mul.10, ptr %dst.10
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%gep.src.11 = getelementptr inbounds i8, ptr %src, i8 11
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%l.src.11 = load i8, ptr %gep.src.11, align 4
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%mul.11 = mul nsw i8 %l.src.11, 10
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%dst.11 = getelementptr i8, ptr %dst, i8 11
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store i8 %mul.11, ptr %dst.11
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%gep.src.12 = getelementptr inbounds i8, ptr %src, i8 12
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%l.src.12 = load i8, ptr %gep.src.12, align 4
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%mul.12 = mul nsw i8 %l.src.12, 10
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%dst.12 = getelementptr i8, ptr %dst, i8 12
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store i8 %mul.12, ptr %dst.12
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%gep.src.13 = getelementptr inbounds i8, ptr %src, i8 13
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%l.src.13 = load i8, ptr %gep.src.13, align 4
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%mul.13 = mul nsw i8 %l.src.13, 10
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%dst.13 = getelementptr i8, ptr %dst, i8 13
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store i8 %mul.13, ptr %dst.13
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%gep.src.14 = getelementptr inbounds i8, ptr %src, i8 14
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%l.src.14 = load i8, ptr %gep.src.14, align 4
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%mul.14 = mul nsw i8 %l.src.14, 10
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%dst.14 = getelementptr i8, ptr %dst, i8 14
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store i8 %mul.14, ptr %dst.14
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ret void
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}

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