llvm
diff --git a/‎llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+3-5 b/‎llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+3-5
diff --git a/‎llvm/test/MC/AMDGPU/gfx11_asm_vop3.s
+546-336 b/‎llvm/test/MC/AMDGPU/gfx11_asm_vop3.s
+546-336
diff --git a/‎llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16.s
+742-418 b/‎llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16.s
+742-418
diff --git a/‎llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8.s
+625-358 b/‎llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8.s
+625-358
diff --git a/‎llvm/test/MC/AMDGPU/gfx12_asm_vop3.s
+442-334 b/‎llvm/test/MC/AMDGPU/gfx12_asm_vop3.s
+442-334
diff --git a/‎llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp16.s
+569-434 b/‎llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp16.s
+569-434
diff --git a/‎llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp8.s
+477-342 b/‎llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp8.s
+477-342
diff --git a/‎llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3.txt
+1,073-305 b/‎llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3.txt
+1,073-305
diff --git a/‎llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16.txt
+1,077-285 b/‎llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16.txt
+1,077-285
diff --git a/‎llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp8.txt
+1,042-274 b/‎llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp8.txt
+1,042-274
diff --git a/‎llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3.txt
+914-167 b/‎llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3.txt
+914-167
diff --git a/‎llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_dpp16.txt
+1,162-163 b/‎llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_dpp16.txt
+1,162-163
diff --git a/‎llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_dpp8.txt
+1,050-135 b/‎llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_dpp8.txt
+1,050-135
@@ -7472,11 +7472,9 @@ void SIInstrInfo::moveToVALUImpl(SIInstrWorklist &Worklist,
   case AMDGPU::S_MINIMUM_F16:
   case AMDGPU::S_MAXIMUM_F16: {
     const DebugLoc &DL = Inst.getDebugLoc();
-    Register NewDst;
-    if (ST.useRealTrue16Insts())
-      NewDst = MRI.createVirtualRegister(&AMDGPU::VGPR_16RegClass);
-    else
-      NewDst = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
+    Register NewDst = MRI.createVirtualRegister(ST.useRealTrue16Insts()
+                                                    ? &AMDGPU::VGPR_16RegClass
+                                                    : &AMDGPU::VGPR_32RegClass);
     MachineInstr *NewInstr = BuildMI(*MBB, Inst, DL, get(NewOpcode), NewDst)
                                  .addImm(0) // src0_modifiers
                                  .add(Inst.getOperand(1))