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JonPsson1JonPsson1
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Initial experiments
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Diff for: ‎clang/lib/Basic/Targets/SystemZ.h

+9
Original file line numberDiff line numberDiff line change
@@ -91,11 +91,20 @@ class LLVM_LIBRARY_VISIBILITY SystemZTargetInfo : public TargetInfo {
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"-v128:64-a:8:16-n32:64");
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}
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MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 128;
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HasLegalHalfType = false; // Default=false
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HalfArgsAndReturns = false; // Default=false
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HasFloat16 = true; // Default=false
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HasStrictFP = true;
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}
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unsigned getMinGlobalAlign(uint64_t Size, bool HasNonWeakDef) const override;
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bool useFP16ConversionIntrinsics() const override {
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return false;
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}
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void getTargetDefines(const LangOptions &Opts,
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MacroBuilder &Builder) const override;
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Diff for: ‎llvm/lib/Target/SystemZ/SystemZISelLowering.cpp

+7
Original file line numberDiff line numberDiff line change
@@ -704,6 +704,13 @@ SystemZTargetLowering::SystemZTargetLowering(const TargetMachine &TM,
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setOperationAction(ISD::BITCAST, MVT::f32, Custom);
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}
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// Expand FP16 <=> FP32 conversions to libcalls and handle FP16 loads and
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// stores in GPRs.
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setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
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setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
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setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
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setTruncStoreAction(MVT::f32, MVT::f16, Expand);
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// VASTART and VACOPY need to deal with the SystemZ-specific varargs
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// structure, but VAEND is a no-op.
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setOperationAction(ISD::VASTART, MVT::Other, Custom);

Diff for: ‎llvm/lib/Target/SystemZ/SystemZISelLowering.h

+1
Original file line numberDiff line numberDiff line change
@@ -476,6 +476,7 @@ class SystemZTargetLowering : public TargetLowering {
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// LD, and having the full constant in memory enables reg/mem opcodes.
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return VT != MVT::f64;
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}
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bool softPromoteHalfType() const override { return true; }
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bool hasInlineStackProbe(const MachineFunction &MF) const override;
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AtomicExpansionKind shouldCastAtomicLoadInIR(LoadInst *LI) const override;
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AtomicExpansionKind shouldCastAtomicStoreInIR(StoreInst *SI) const override;

Diff for: ‎llvm/test/CodeGen/SystemZ/fp-half.ll

+158
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@@ -0,0 +1,158 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
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;
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; Tests for FP16 (Half).
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; A function where everything is done in Half.
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define void @fun0(ptr %Op0, ptr %Op1, ptr %Dst) {
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; CHECK-LABEL: fun0:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: stmg %r12, %r15, 96(%r15)
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; CHECK-NEXT: .cfi_offset %r12, -64
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; CHECK-NEXT: .cfi_offset %r13, -56
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; CHECK-NEXT: .cfi_offset %r14, -48
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; CHECK-NEXT: .cfi_offset %r15, -40
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; CHECK-NEXT: aghi %r15, -168
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; CHECK-NEXT: .cfi_def_cfa_offset 328
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; CHECK-NEXT: std %f8, 160(%r15) # 8-byte Folded Spill
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; CHECK-NEXT: .cfi_offset %f8, -168
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; CHECK-NEXT: llgh %r0, 0(%r3)
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; CHECK-NEXT: llgh %r13, 0(%r2)
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; CHECK-NEXT: lgr %r12, %r4
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; CHECK-NEXT: lgr %r2, %r0
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; CHECK-NEXT: brasl %r14, __gnu_h2f_ieee@PLT
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; CHECK-NEXT: ler %f8, %f0
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; CHECK-NEXT: lgr %r2, %r13
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; CHECK-NEXT: brasl %r14, __gnu_h2f_ieee@PLT
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; CHECK-NEXT: aebr %f0, %f8
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; CHECK-NEXT: brasl %r14, __gnu_f2h_ieee@PLT
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; CHECK-NEXT: sth %r2, 0(%r12)
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; CHECK-NEXT: ld %f8, 160(%r15) # 8-byte Folded Reload
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; CHECK-NEXT: lmg %r12, %r15, 264(%r15)
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; CHECK-NEXT: br %r14
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entry:
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%0 = load half, ptr %Op0, align 2
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%1 = load half, ptr %Op1, align 2
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%add = fadd half %0, %1
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store half %add, ptr %Dst, align 2
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ret void
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}
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; A function where Half values are loaded and extended to float and then
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; operated on.
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define void @fun1(ptr %Op0, ptr %Op1, ptr %Dst) {
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; CHECK-LABEL: fun1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: stmg %r12, %r15, 96(%r15)
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; CHECK-NEXT: .cfi_offset %r12, -64
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; CHECK-NEXT: .cfi_offset %r13, -56
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; CHECK-NEXT: .cfi_offset %r14, -48
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; CHECK-NEXT: .cfi_offset %r15, -40
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; CHECK-NEXT: aghi %r15, -168
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; CHECK-NEXT: .cfi_def_cfa_offset 328
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; CHECK-NEXT: std %f8, 160(%r15) # 8-byte Folded Spill
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; CHECK-NEXT: .cfi_offset %f8, -168
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; CHECK-NEXT: llgh %r2, 0(%r2)
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; CHECK-NEXT: lgr %r13, %r4
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; CHECK-NEXT: lgr %r12, %r3
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; CHECK-NEXT: brasl %r14, __gnu_h2f_ieee@PLT
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; CHECK-NEXT: llgh %r2, 0(%r12)
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; CHECK-NEXT: ler %f8, %f0
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; CHECK-NEXT: brasl %r14, __gnu_h2f_ieee@PLT
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; CHECK-NEXT: aebr %f0, %f8
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; CHECK-NEXT: brasl %r14, __gnu_f2h_ieee@PLT
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; CHECK-NEXT: sth %r2, 0(%r13)
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; CHECK-NEXT: ld %f8, 160(%r15) # 8-byte Folded Reload
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; CHECK-NEXT: lmg %r12, %r15, 264(%r15)
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; CHECK-NEXT: br %r14
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entry:
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%0 = load half, ptr %Op0, align 2
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%ext = fpext half %0 to float
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%1 = load half, ptr %Op1, align 2
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%ext1 = fpext half %1 to float
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%add = fadd float %ext, %ext1
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%res = fptrunc float %add to half
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store half %res, ptr %Dst, align 2
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ret void
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}
78+
79+
; Test case with a Half incoming argument.
80+
define zeroext i1 @fun2(half noundef %f) {
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; CHECK-LABEL: fun2:
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; CHECK: # %bb.0: # %start
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; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
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; CHECK-NEXT: .cfi_offset %r14, -48
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; CHECK-NEXT: .cfi_offset %r15, -40
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; CHECK-NEXT: aghi %r15, -160
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; CHECK-NEXT: .cfi_def_cfa_offset 320
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; CHECK-NEXT: llgfr %r2, %r2
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; CHECK-NEXT: brasl %r14, __gnu_h2f_ieee@PLT
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; CHECK-NEXT: larl %r1, .LCPI2_0
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; CHECK-NEXT: deb %f0, 0(%r1)
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; CHECK-NEXT: brasl %r14, __gnu_f2h_ieee@PLT
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; CHECK-NEXT: risbg %r2, %r2, 63, 191, 49
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; CHECK-NEXT: lmg %r14, %r15, 272(%r15)
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; CHECK-NEXT: br %r14
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start:
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%self = fdiv half %f, 0xHC700
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%_4 = bitcast half %self to i16
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%_0 = icmp slt i16 %_4, 0
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ret i1 %_0
101+
}
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103+
; Test a chain of Half operations which should have each operation surrounded
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; by conversions to/from fp32 to properly emulate Half operations.
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define void @fun3(ptr %Op0, ptr %Op1, ptr %Op2, ptr %Op3, ptr %Dst) {
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; CHECK-LABEL: fun3:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: stmg %r11, %r15, 88(%r15)
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; CHECK-NEXT: .cfi_offset %r11, -72
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; CHECK-NEXT: .cfi_offset %r12, -64
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; CHECK-NEXT: .cfi_offset %r13, -56
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; CHECK-NEXT: .cfi_offset %r14, -48
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; CHECK-NEXT: .cfi_offset %r15, -40
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; CHECK-NEXT: aghi %r15, -168
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; CHECK-NEXT: .cfi_def_cfa_offset 328
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; CHECK-NEXT: std %f8, 160(%r15) # 8-byte Folded Spill
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; CHECK-NEXT: .cfi_offset %f8, -168
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; CHECK-NEXT: llgh %r0, 0(%r3)
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; CHECK-NEXT: llgh %r13, 0(%r2)
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; CHECK-NEXT: lgr %r12, %r5
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; CHECK-NEXT: lgr %r11, %r4
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; CHECK-NEXT: lgr %r2, %r0
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; CHECK-NEXT: brasl %r14, __gnu_h2f_ieee@PLT
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; CHECK-NEXT: ler %f8, %f0
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; CHECK-NEXT: lgr %r2, %r13
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; CHECK-NEXT: brasl %r14, __gnu_h2f_ieee@PLT
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; CHECK-NEXT: aebr %f0, %f8
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; CHECK-NEXT: brasl %r14, __gnu_f2h_ieee@PLT
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; CHECK-NEXT: llgh %r13, 0(%r11)
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; CHECK-NEXT: brasl %r14, __gnu_h2f_ieee@PLT
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; CHECK-NEXT: ler %f8, %f0
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; CHECK-NEXT: lgr %r2, %r13
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; CHECK-NEXT: brasl %r14, __gnu_h2f_ieee@PLT
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; CHECK-NEXT: aebr %f0, %f8
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; CHECK-NEXT: brasl %r14, __gnu_f2h_ieee@PLT
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; CHECK-NEXT: llgh %r13, 0(%r12)
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; CHECK-NEXT: brasl %r14, __gnu_h2f_ieee@PLT
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; CHECK-NEXT: ler %f8, %f0
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; CHECK-NEXT: lgr %r2, %r13
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; CHECK-NEXT: brasl %r14, __gnu_h2f_ieee@PLT
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; CHECK-NEXT: sebr %f8, %f0
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; CHECK-NEXT: ler %f0, %f8
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; CHECK-NEXT: brasl %r14, __gnu_f2h_ieee@PLT
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; CHECK-NEXT: sth %r2, 0(%r6)
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; CHECK-NEXT: ld %f8, 160(%r15) # 8-byte Folded Reload
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; CHECK-NEXT: lmg %r11, %r15, 256(%r15)
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; CHECK-NEXT: br %r14
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entry:
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%0 = load half, ptr %Op0, align 2
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%1 = load half, ptr %Op1, align 2
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%add = fadd half %0, %1
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%2 = load half, ptr %Op2, align 2
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%add1 = fadd half %add, %2
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%3 = load half, ptr %Op3, align 2
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%sub = fsub half %add1, %3
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store half %sub, ptr %Dst, align 2
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ret void
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}

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