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[CodeGen] Remove static member function Register::isVirtualRegister. NFC (#127968)
Use nonstatic member instead. This requires explicit conversions, but many will go away as we continue converting unsigned to Register. In a few places where it was simple, I changed unsigned to Register.
1 parent 609732c commit ff99af7

27 files changed

+50
-59
lines changed

‎llvm/include/llvm/CodeGen/RDFRegisters.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -114,7 +114,7 @@ struct RegisterRef {
114114
return Register::isPhysicalRegister(Id);
115115
}
116116
static constexpr bool isUnitId(unsigned Id) {
117-
return Register::isVirtualRegister(Id);
117+
return Register(Id).isVirtual();
118118
}
119119
static constexpr bool isMaskId(unsigned Id) { return Register(Id).isStack(); }
120120

‎llvm/include/llvm/CodeGen/Register.h

+3-9
Original file line numberDiff line numberDiff line change
@@ -54,12 +54,6 @@ class Register {
5454
return MCRegister::isPhysicalRegister(Reg);
5555
}
5656

57-
/// Return true if the specified register number is in
58-
/// the virtual register namespace.
59-
static constexpr bool isVirtualRegister(unsigned Reg) {
60-
return Reg & MCRegister::VirtualRegFlag;
61-
}
62-
6357
/// Convert a 0-based index to a virtual register number.
6458
/// This is the inverse operation of VirtReg2IndexFunctor below.
6559
static Register index2VirtReg(unsigned Index) {
@@ -69,7 +63,7 @@ class Register {
6963

7064
/// Return true if the specified register number is in the virtual register
7165
/// namespace.
72-
constexpr bool isVirtual() const { return isVirtualRegister(Reg); }
66+
constexpr bool isVirtual() const { return Reg & MCRegister::VirtualRegFlag; }
7367

7468
/// Return true if the specified register number is in the physical register
7569
/// namespace.
@@ -156,14 +150,14 @@ class VirtRegOrUnit {
156150

157151
public:
158152
constexpr explicit VirtRegOrUnit(MCRegUnit Unit) : VRegOrUnit(Unit) {
159-
assert(!Register::isVirtualRegister(VRegOrUnit));
153+
assert(!Register(VRegOrUnit).isVirtual());
160154
}
161155
constexpr explicit VirtRegOrUnit(Register Reg) : VRegOrUnit(Reg.id()) {
162156
assert(Reg.isVirtual());
163157
}
164158

165159
constexpr bool isVirtualReg() const {
166-
return Register::isVirtualRegister(VRegOrUnit);
160+
return Register(VRegOrUnit).isVirtual();
167161
}
168162

169163
constexpr MCRegUnit asMCRegUnit() const {

‎llvm/lib/CodeGen/EarlyIfConversion.cpp

+2-2
Original file line numberDiff line numberDiff line change
@@ -522,8 +522,8 @@ bool SSAIfConv::canConvertIf(MachineBasicBlock *MBB, bool Predicate) {
522522
if (PI.PHI->getOperand(i+1).getMBB() == FPred)
523523
PI.FReg = PI.PHI->getOperand(i).getReg();
524524
}
525-
assert(Register::isVirtualRegister(PI.TReg) && "Bad PHI");
526-
assert(Register::isVirtualRegister(PI.FReg) && "Bad PHI");
525+
assert(Register(PI.TReg).isVirtual() && "Bad PHI");
526+
assert(Register(PI.FReg).isVirtual() && "Bad PHI");
527527

528528
// Get target information.
529529
if (!TII->canInsertSelect(*Head, Cond, PI.PHI->getOperand(0).getReg(),

‎llvm/lib/CodeGen/LiveInterval.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -876,7 +876,7 @@ static void stripValuesNotDefiningMask(unsigned Reg, LiveInterval::SubRange &SR,
876876
unsigned ComposeSubRegIdx) {
877877
// Phys reg should not be tracked at subreg level.
878878
// Same for noreg (Reg == 0).
879-
if (!Register::isVirtualRegister(Reg) || !Reg)
879+
if (!Register(Reg).isVirtual() || !Reg)
880880
return;
881881
// Remove the values that don't define those lanes.
882882
SmallVector<VNInfo *, 8> ToBeRemoved;

‎llvm/lib/CodeGen/MIRVRegNamerUtils.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -137,7 +137,7 @@ std::string VRegRenamer::getInstructionOpcodeHash(MachineInstr &MI) {
137137
}
138138

139139
unsigned VRegRenamer::createVirtualRegister(unsigned VReg) {
140-
assert(Register::isVirtualRegister(VReg) && "Expected Virtual Registers");
140+
assert(Register(VReg).isVirtual() && "Expected Virtual Registers");
141141
std::string Name = getInstructionOpcodeHash(*MRI.getVRegDef(VReg));
142142
return createVirtualRegisterWithLowerName(VReg, Name);
143143
}

‎llvm/lib/CodeGen/MachineTraceMetrics.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -682,7 +682,7 @@ struct DataDep {
682682
/// Create a DataDep from an SSA form virtual register.
683683
DataDep(const MachineRegisterInfo *MRI, unsigned VirtReg, unsigned UseOp)
684684
: UseOp(UseOp) {
685-
assert(Register::isVirtualRegister(VirtReg));
685+
assert(Register(VirtReg).isVirtual());
686686
MachineOperand *DefMO = MRI->getOneDef(VirtReg);
687687
assert(DefMO && "Register does not have unique def");
688688
DefMI = DefMO->getParent();

‎llvm/lib/CodeGen/RegisterPressure.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -231,7 +231,7 @@ void LiveRegSet::clear() {
231231
}
232232

233233
static const LiveRange *getLiveRange(const LiveIntervals &LIS, unsigned Reg) {
234-
if (Register::isVirtualRegister(Reg))
234+
if (Register(Reg).isVirtual())
235235
return &LIS.getInterval(Reg);
236236
return LIS.getCachedRegUnit(Reg);
237237
}

‎llvm/lib/CodeGen/SelectionDAG/FastISel.cpp

+1-2
Original file line numberDiff line numberDiff line change
@@ -2229,8 +2229,7 @@ Register FastISel::fastEmitInst_i(unsigned MachineInstOpcode,
22292229
Register FastISel::fastEmitInst_extractsubreg(MVT RetVT, unsigned Op0,
22302230
uint32_t Idx) {
22312231
Register ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
2232-
assert(Register::isVirtualRegister(Op0) &&
2233-
"Cannot yet extract from physregs");
2232+
assert(Register(Op0).isVirtual() && "Cannot yet extract from physregs");
22342233
const TargetRegisterClass *RC = MRI.getRegClass(Op0);
22352234
MRI.constrainRegClass(Op0, TRI.getSubClassWithSubReg(RC, Idx));
22362235
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(TargetOpcode::COPY),

‎llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp

+4-4
Original file line numberDiff line numberDiff line change
@@ -116,11 +116,11 @@ static void CheckForPhysRegDependency(SDNode *Def, SDNode *User, unsigned Op,
116116
if (Op != 2 || User->getOpcode() != ISD::CopyToReg)
117117
return;
118118

119-
unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
119+
Register Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
120120
if (TLI.checkForPhysRegDependency(Def, User, Op, TRI, TII, PhysReg, Cost))
121121
return;
122122

123-
if (Register::isVirtualRegister(Reg))
123+
if (Reg.isVirtual())
124124
return;
125125

126126
unsigned ResNo = User->getOperand(2).getResNo();
@@ -664,8 +664,8 @@ void ScheduleDAGSDNodes::computeOperandLatency(SDNode *Def, SDNode *Use,
664664
TII->getOperandLatency(InstrItins, Def, DefIdx, Use, OpIdx);
665665
if (Latency > 1U && Use->getOpcode() == ISD::CopyToReg &&
666666
!BB->succ_empty()) {
667-
unsigned Reg = cast<RegisterSDNode>(Use->getOperand(1))->getReg();
668-
if (Register::isVirtualRegister(Reg))
667+
Register Reg = cast<RegisterSDNode>(Use->getOperand(1))->getReg();
668+
if (Reg.isVirtual())
669669
// This copy is a liveout value. It is likely coalesced, so reduce the
670670
// latency so not to penalize the def.
671671
// FIXME: need target specific adjustment here?

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

+2-3
Original file line numberDiff line numberDiff line change
@@ -908,8 +908,7 @@ SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
908908

909909
// If the source register was virtual and if we know something about it,
910910
// add an assert node.
911-
if (!Register::isVirtualRegister(Regs[Part + i]) ||
912-
!RegisterVT.isInteger())
911+
if (!Regs[Part + i].isVirtual() || !RegisterVT.isInteger())
913912
continue;
914913

915914
const FunctionLoweringInfo::LiveOutInfo *LOI =
@@ -1023,7 +1022,7 @@ void RegsForValue::AddInlineAsmOperands(InlineAsm::Kind Code, bool HasMatching,
10231022
InlineAsm::Flag Flag(Code, Regs.size());
10241023
if (HasMatching)
10251024
Flag.setMatchingOp(MatchingIdx);
1026-
else if (!Regs.empty() && Register::isVirtualRegister(Regs.front())) {
1025+
else if (!Regs.empty() && Regs.front().isVirtual()) {
10271026
// Put the register class of the virtual registers in the flag word. That
10281027
// way, later passes can recompute register class constraints for inline
10291028
// assembly as well as normal instructions.

‎llvm/lib/CodeGen/TargetRegisterInfo.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -160,7 +160,7 @@ Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI) {
160160

161161
Printable printVRegOrUnit(unsigned Unit, const TargetRegisterInfo *TRI) {
162162
return Printable([Unit, TRI](raw_ostream &OS) {
163-
if (Register::isVirtualRegister(Unit)) {
163+
if (Register(Unit).isVirtual()) {
164164
OS << '%' << Register(Unit).virtRegIndex();
165165
} else {
166166
OS << printRegUnit(Unit, TRI);

‎llvm/lib/Target/AArch64/AArch64AdvSIMDScalarPass.cpp

+2-2
Original file line numberDiff line numberDiff line change
@@ -105,14 +105,14 @@ static bool isGPR64(unsigned Reg, unsigned SubReg,
105105
const MachineRegisterInfo *MRI) {
106106
if (SubReg)
107107
return false;
108-
if (Register::isVirtualRegister(Reg))
108+
if (Register(Reg).isVirtual())
109109
return MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::GPR64RegClass);
110110
return AArch64::GPR64RegClass.contains(Reg);
111111
}
112112

113113
static bool isFPR64(unsigned Reg, unsigned SubReg,
114114
const MachineRegisterInfo *MRI) {
115-
if (Register::isVirtualRegister(Reg))
115+
if (Register(Reg).isVirtual())
116116
return (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR64RegClass) &&
117117
SubReg == 0) ||
118118
(MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR128RegClass) &&

‎llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -258,7 +258,7 @@ bool SSACCmpConv::isDeadDef(unsigned DstReg) {
258258
// Writes to the zero register are dead.
259259
if (DstReg == AArch64::WZR || DstReg == AArch64::XZR)
260260
return true;
261-
if (!Register::isVirtualRegister(DstReg))
261+
if (!Register(DstReg).isVirtual())
262262
return false;
263263
// A virtual register def without any uses will be marked dead later, and
264264
// eventually replaced by the zero register.

‎llvm/lib/Target/AArch64/AArch64InstrInfo.cpp

+6-6
Original file line numberDiff line numberDiff line change
@@ -677,7 +677,7 @@ unsigned AArch64InstrInfo::insertBranch(
677677

678678
// Find the original register that VReg is copied from.
679679
static unsigned removeCopies(const MachineRegisterInfo &MRI, unsigned VReg) {
680-
while (Register::isVirtualRegister(VReg)) {
680+
while (Register(VReg).isVirtual()) {
681681
const MachineInstr *DefMI = MRI.getVRegDef(VReg);
682682
if (!DefMI->isFullCopy())
683683
return VReg;
@@ -692,7 +692,7 @@ static unsigned removeCopies(const MachineRegisterInfo &MRI, unsigned VReg) {
692692
static unsigned canFoldIntoCSel(const MachineRegisterInfo &MRI, unsigned VReg,
693693
unsigned *NewVReg = nullptr) {
694694
VReg = removeCopies(MRI, VReg);
695-
if (!Register::isVirtualRegister(VReg))
695+
if (!Register(VReg).isVirtual())
696696
return 0;
697697

698698
bool Is64Bit = AArch64::GPR64allRegClass.hasSubClassEq(MRI.getRegClass(VReg));
@@ -6121,9 +6121,9 @@ MachineInstr *AArch64InstrInfo::foldMemoryOperandImpl(
61216121
Register SrcReg = SrcMO.getReg();
61226122
// This is slightly expensive to compute for physical regs since
61236123
// getMinimalPhysRegClass is slow.
6124-
auto getRegClass = [&](unsigned Reg) {
6125-
return Register::isVirtualRegister(Reg) ? MRI.getRegClass(Reg)
6126-
: TRI.getMinimalPhysRegClass(Reg);
6124+
auto getRegClass = [&](Register Reg) {
6125+
return Reg.isVirtual() ? MRI.getRegClass(Reg)
6126+
: TRI.getMinimalPhysRegClass(Reg);
61276127
};
61286128

61296129
if (DstMO.getSubReg() == 0 && SrcMO.getSubReg() == 0) {
@@ -7456,7 +7456,7 @@ static MachineInstr *genMaddR(MachineFunction &MF, MachineRegisterInfo &MRI,
74567456
MRI.constrainRegClass(SrcReg0, RC);
74577457
if (SrcReg1.isVirtual())
74587458
MRI.constrainRegClass(SrcReg1, RC);
7459-
if (Register::isVirtualRegister(VR))
7459+
if (Register(VR).isVirtual())
74607460
MRI.constrainRegClass(VR, RC);
74617461

74627462
MachineInstrBuilder MIB =

‎llvm/lib/Target/ARC/ARCOptAddrMode.cpp

+2-2
Original file line numberDiff line numberDiff line change
@@ -151,7 +151,7 @@ static bool dominatesAllUsesOf(const MachineInstr *MI, unsigned VReg,
151151
MachineDominatorTree *MDT,
152152
MachineRegisterInfo *MRI) {
153153

154-
assert(Register::isVirtualRegister(VReg) && "Expected virtual register!");
154+
assert(Register(VReg).isVirtual() && "Expected virtual register!");
155155

156156
for (const MachineOperand &Use : MRI->use_nodbg_operands(VReg)) {
157157
const MachineInstr *User = Use.getParent();
@@ -216,7 +216,7 @@ MachineInstr *ARCOptAddrMode::tryToCombine(MachineInstr &Ldst) {
216216
}
217217

218218
Register B = Base.getReg();
219-
if (!Register::isVirtualRegister(B)) {
219+
if (!B.isVirtual())
220220
LLVM_DEBUG(dbgs() << "[ABAW] Base is not VReg\n");
221221
return nullptr;
222222
}

‎llvm/lib/Target/ARM/A15SDOptimizer.cpp

+3-3
Original file line numberDiff line numberDiff line change
@@ -152,7 +152,7 @@ unsigned A15SDOptimizer::getDPRLaneFromSPR(unsigned SReg) {
152152
// Get the subreg type that is most likely to be coalesced
153153
// for an SPR register that will be used in VDUP32d pseudo.
154154
unsigned A15SDOptimizer::getPrefSPRLane(unsigned SReg) {
155-
if (!Register::isVirtualRegister(SReg))
155+
if (!Register(SReg).isVirtual())
156156
return getDPRLaneFromSPR(SReg);
157157

158158
MachineInstr *MI = MRI->getVRegDef(SReg);
@@ -166,7 +166,7 @@ unsigned A15SDOptimizer::getPrefSPRLane(unsigned SReg) {
166166
SReg = MI->getOperand(1).getReg();
167167
}
168168

169-
if (Register::isVirtualRegister(SReg)) {
169+
if (Register(SReg).isVirtual()) {
170170
if (MO->getSubReg() == ARM::ssub_1) return ARM::ssub_1;
171171
return ARM::ssub_0;
172172
}
@@ -598,7 +598,7 @@ bool A15SDOptimizer::runOnInstruction(MachineInstr *MI) {
598598
// we can end up with multiple defs of this DPR.
599599

600600
SmallVector<MachineInstr *, 8> DefSrcs;
601-
if (!Register::isVirtualRegister(I))
601+
if (!Register(I).isVirtual())
602602
continue;
603603
MachineInstr *Def = MRI->getVRegDef(I);
604604
if (!Def)

‎llvm/lib/Target/ARM/ARMLatencyMutations.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -756,7 +756,7 @@ signed M85Overrides::modifyMixedWidthFP(const MachineInstr *SrcMI,
756756
!II->producesQP(SrcMI->getOpcode()))
757757
return 0;
758758

759-
if (Register::isVirtualRegister(RegID)) {
759+
if (Register(RegID).isVirtual()) {
760760
if (II->producesSP(SrcMI->getOpcode()) &&
761761
II->consumesDP(DstMI->getOpcode())) {
762762
for (auto &OP : SrcMI->operands())

‎llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp

+3-3
Original file line numberDiff line numberDiff line change
@@ -253,15 +253,15 @@ bool AVRDAGToDAGISel::SelectInlineAsmMemoryOperand(
253253
SDValue ImmOp = Op->getOperand(1);
254254
ConstantSDNode *ImmNode = dyn_cast<ConstantSDNode>(ImmOp);
255255

256-
unsigned Reg;
256+
Register Reg;
257257
bool CanHandleRegImmOpt = ImmNode && ImmNode->getAPIntValue().ult(64);
258258

259259
if (CopyFromRegOp->getOpcode() == ISD::CopyFromReg) {
260260
RegisterSDNode *RegNode =
261261
cast<RegisterSDNode>(CopyFromRegOp->getOperand(1));
262262
Reg = RegNode->getReg();
263-
CanHandleRegImmOpt &= (Register::isVirtualRegister(Reg) ||
264-
AVR::PTRDISPREGSRegClass.contains(Reg));
263+
CanHandleRegImmOpt &=
264+
(Reg.isVirtual() || AVR::PTRDISPREGSRegClass.contains(Reg));
265265
} else {
266266
CanHandleRegImmOpt = false;
267267
}

‎llvm/lib/Target/Hexagon/HexagonCopyHoisting.cpp

+1-2
Original file line numberDiff line numberDiff line change
@@ -139,8 +139,7 @@ void HexagonCopyHoisting::addMItoCopyList(MachineInstr *MI) {
139139
Register DstReg = MI->getOperand(0).getReg();
140140
Register SrcReg = MI->getOperand(1).getReg();
141141

142-
if (!Register::isVirtualRegister(DstReg) ||
143-
!Register::isVirtualRegister(SrcReg) ||
142+
if (!DstReg.isVirtual() || !SrcReg.isVirtual() ||
144143
MRI->getRegClass(DstReg) != &Hexagon::IntRegsRegClass ||
145144
MRI->getRegClass(SrcReg) != &Hexagon::IntRegsRegClass)
146145
return;

‎llvm/lib/Target/M68k/M68kISelLowering.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -322,7 +322,7 @@ static bool MatchingStackOffset(SDValue Arg, unsigned Offset,
322322
int FI = INT_MAX;
323323
if (Arg.getOpcode() == ISD::CopyFromReg) {
324324
Register VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
325-
if (!Register::isVirtualRegister(VR))
325+
if (!VR.isVirtual())
326326
return false;
327327
MachineInstr *Def = MRI->getVRegDef(VR);
328328
if (!Def)

‎llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -205,7 +205,7 @@ MCOperand NVPTXAsmPrinter::lowerOperand(const MachineOperand &MO) {
205205
}
206206

207207
unsigned NVPTXAsmPrinter::encodeVirtualRegister(unsigned Reg) {
208-
if (Register::isVirtualRegister(Reg)) {
208+
if (Register(Reg).isVirtual()) {
209209
const TargetRegisterClass *RC = MRI->getRegClass(Reg);
210210

211211
DenseMap<unsigned, unsigned> &RegMap = VRegMapping[RC];

‎llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

+3-3
Original file line numberDiff line numberDiff line change
@@ -5131,7 +5131,7 @@ static bool isOpZeroOfSubwordPreincLoad(int Opcode) {
51315131
// This function checks for sign extension from 32 bits to 64 bits.
51325132
static bool definedBySignExtendingOp(const unsigned Reg,
51335133
const MachineRegisterInfo *MRI) {
5134-
if (!Register::isVirtualRegister(Reg))
5134+
if (!Register(Reg).isVirtual())
51355135
return false;
51365136

51375137
MachineInstr *MI = MRI->getVRegDef(Reg);
@@ -5178,7 +5178,7 @@ static bool definedBySignExtendingOp(const unsigned Reg,
51785178
// in the higher 32 bits then this function will return true.
51795179
static bool definedByZeroExtendingOp(const unsigned Reg,
51805180
const MachineRegisterInfo *MRI) {
5181-
if (!Register::isVirtualRegister(Reg))
5181+
if (!Register(Reg).isVirtual())
51825182
return false;
51835183

51845184
MachineInstr *MI = MRI->getVRegDef(Reg);
@@ -5463,7 +5463,7 @@ std::pair<bool, bool>
54635463
PPCInstrInfo::isSignOrZeroExtended(const unsigned Reg,
54645464
const unsigned BinOpDepth,
54655465
const MachineRegisterInfo *MRI) const {
5466-
if (!Register::isVirtualRegister(Reg))
5466+
if (!Register(Reg).isVirtual())
54675467
return std::pair<bool, bool>(false, false);
54685468

54695469
MachineInstr *MI = MRI->getVRegDef(Reg);

‎llvm/lib/Target/PowerPC/PPCMIPeephole.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -1482,7 +1482,7 @@ static unsigned getSrcVReg(unsigned Reg, MachineBasicBlock *BB1,
14821482
}
14831483
else if (Inst->isFullCopy())
14841484
NextReg = Inst->getOperand(1).getReg();
1485-
if (NextReg == SrcReg || !Register::isVirtualRegister(NextReg))
1485+
if (NextReg == SrcReg || !Register(NextReg).isVirtual())
14861486
break;
14871487
SrcReg = NextReg;
14881488
}

‎llvm/lib/Target/PowerPC/PPCReduceCRLogicals.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -537,7 +537,7 @@ MachineInstr *PPCReduceCRLogicals::lookThroughCRCopy(unsigned Reg,
537537
unsigned &Subreg,
538538
MachineInstr *&CpDef) {
539539
Subreg = -1;
540-
if (!Register::isVirtualRegister(Reg))
540+
if (!Register(Reg).isVirtual())
541541
return nullptr;
542542
MachineInstr *Copy = MRI->getVRegDef(Reg);
543543
CpDef = Copy;

‎llvm/lib/Target/PowerPC/PPCVSXCopy.cpp

+2-2
Original file line numberDiff line numberDiff line change
@@ -40,9 +40,9 @@ namespace {
4040

4141
const TargetInstrInfo *TII;
4242

43-
bool IsRegInClass(unsigned Reg, const TargetRegisterClass *RC,
43+
bool IsRegInClass(Register Reg, const TargetRegisterClass *RC,
4444
MachineRegisterInfo &MRI) {
45-
if (Register::isVirtualRegister(Reg)) {
45+
if (Reg.isVirtual()) {
4646
return RC->hasSubClassEq(MRI.getRegClass(Reg));
4747
} else if (RC->contains(Reg)) {
4848
return true;

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