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[hw,tlul_adapter_sram_racl,rtl] Add RACL protected SRAM adapter
Signed-off-by: Robert Schilling <[email protected]>
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‎hw/ip/tlul/adapter_sram_racl.core

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CAPI=2:
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# Copyright lowRISC contributors (OpenTitan project).
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# Licensed under the Apache License, Version 2.0, see LICENSE for details.
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# SPDX-License-Identifier: Apache-2.0
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name: "lowrisc:tlul:adapter_sram_racl:0.1"
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description: "TL-UL to SRAM adapter (device) with RACL support"
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filesets:
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files_rtl:
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depend:
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- lowrisc:prim:util
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- lowrisc:prim:assert
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- lowrisc:tlul:common
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- lowrisc:tlul:adapter_sram
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- lowrisc:tlul:request_loopback
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- lowrisc:systems:top_racl_pkg
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files:
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- rtl/tlul_adapter_sram_racl.sv
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file_type: systemVerilogSource
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files_verilator_waiver:
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depend:
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# common waivers
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- lowrisc:lint:common
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file_type: vlt
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files_ascentlint_waiver:
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depend:
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# common waivers
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- lowrisc:lint:common
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file_type: waiver
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files_veriblelint_waiver:
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depend:
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# common waivers
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- lowrisc:lint:common
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parameters:
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SYNTHESIS:
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datatype: bool
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paramtype: vlogdefine
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targets:
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default: &default_target
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filesets:
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- tool_verilator ? (files_verilator_waiver)
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- tool_ascentlint ? (files_ascentlint_waiver)
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- tool_veriblelint ? (files_veriblelint_waiver)
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- files_rtl
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toplevel: tlul_adapter_sram_racl
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lint:
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<<: *default_target
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default_tool: verilator
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parameters:
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- SYNTHESIS=true
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tools:
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verilator:
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mode: lint-only
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verilator_options:
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- "-Wall"

‎hw/ip/tlul/rtl/tlul_adapter_sram_racl.sv

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// Copyright lowRISC contributors (OpenTitan project).
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// Licensed under the Apache License, Version 2.0, see LICENSE for details.
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// SPDX-License-Identifier: Apache-2.0
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`include "prim_assert.sv"
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/**
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* Tile-Link UL adapter for SRAM-like devices with RACL support
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*
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* - Intentionally omitted BaseAddr in case of multiple memory maps are used in a SoC,
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* it means that aliasing can happen if target device size in TL-UL crossbar is bigger
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* than SRAM size
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* - At most one of EnableDataIntgGen / EnableDataIntgPt can be enabled. However it
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* possible for both to be disabled.
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* A module can neither generate an integrity response nor pass through any pre-existing
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* integrity. This might be the case for non-security critical memories where there is
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* no stored integrity AND another entity upstream is already generating returning integrity.
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* There is however no case where EnableDataIntgGen and EnableDataIntgPt are both true.
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*/
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module tlul_adapter_sram_racl
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import tlul_pkg::*;
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import prim_mubi_pkg::mubi4_t;
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#(
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parameter int SramAw = 12,
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parameter int SramDw = 32, // Must be multiple of the TL width
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parameter int Outstanding = 1, // Only one request is accepted
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parameter int SramBusBankAW = 12, // SRAM bus address width of the SRAM bank. Only used
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// when DataXorAddr=1.
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parameter bit ByteAccess = 1, // 1: Enables sub-word write transactions. Note that this
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// results in read-modify-write operations for integrity
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// re-generation if EnableDataIntgPt is set to 1.
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parameter bit ErrOnWrite = 0, // 1: Writes not allowed, automatically error
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parameter bit ErrOnRead = 0, // 1: Reads not allowed, automatically error
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parameter bit CmdIntgCheck = 0, // 1: Enable command integrity check
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parameter bit EnableRspIntgGen = 0, // 1: Generate response integrity
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parameter bit EnableDataIntgGen = 0, // 1: Generate response data integrity
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parameter bit EnableDataIntgPt = 0, // 1: Passthrough command/response data integrity
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parameter bit SecFifoPtr = 0, // 1: Duplicated fifo pointers
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parameter bit EnableReadback = 0, // 1: Readback and check written/read data.
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parameter bit DataXorAddr = 0, // 1: XOR data and address for address protection
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parameter bit EnableRacl = 0, // 1: Enable RACL checks on access
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parameter bit RaclErrorRsp = 1, // 1: Return TLUL error on RACL errors
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parameter int RaclPolicySelVec = 0, // RACL policy for this SRAM adapter
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localparam int WidthMult = SramDw / top_pkg::TL_DW,
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localparam int IntgWidth = tlul_pkg::DataIntgWidth * WidthMult,
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localparam int DataOutW = EnableDataIntgPt ? SramDw + IntgWidth : SramDw
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) (
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input clk_i,
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input rst_ni,
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// TL-UL interface
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input tl_h2d_t tl_i,
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output tl_d2h_t tl_o,
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// control interface
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input mubi4_t en_ifetch_i,
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// SRAM interface
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output logic req_o,
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output mubi4_t req_type_o,
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input gnt_i,
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output logic we_o,
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output logic [SramAw-1:0] addr_o,
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output logic [DataOutW-1:0] wdata_o,
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output logic [DataOutW-1:0] wmask_o,
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output logic intg_error_o,
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output logic [RsvdWidth-1:0] user_rsvd_o,
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input [DataOutW-1:0] rdata_i,
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input rvalid_i,
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input [1:0] rerror_i, // 2 bit error [1]: Uncorrectable, [0]: Correctable
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output logic compound_txn_in_progress_o,
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input mubi4_t readback_en_i,
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output logic readback_error_o,
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input logic wr_collision_i,
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input logic write_pending_i,
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// RACL interface
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input top_racl_pkg::racl_policy_vec_t racl_policies_i,
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output logic racl_error_o,
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output top_racl_pkg::racl_error_log_t racl_error_log_o
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);
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tl_h2d_t tl_h2d_filtered;
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tl_d2h_t tl_d2h_filtered;
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if (EnableRacl) begin : gen_racl_role_logic
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// Retrieve RACL role from user bits and one-hot encode that for the comparison bitmap
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top_racl_pkg::racl_role_t racl_role;
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assign racl_role = top_racl_pkg::tlul_extract_racl_role_bits(tl_i.a_user.rsvd);
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top_racl_pkg::racl_role_vec_t racl_role_vec;
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prim_onehot_enc #(
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.OneHotWidth( $bits(top_racl_pkg::racl_role_vec_t) )
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) u_racl_role_encode (
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.in_i ( racl_role ),
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.en_i ( 1'b1 ),
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.out_o( racl_role_vec )
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);
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logic rd_req, racl_read_allowed, racl_write_allowed;
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assign rd_req = tl_i.a_opcode == tlul_pkg::Get;
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assign racl_read_allowed = (|(racl_policies_i[RaclPolicySelVec].read_perm & racl_role_vec));
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assign racl_write_allowed = (|(racl_policies_i[RaclPolicySelVec].write_perm & racl_role_vec));
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assign racl_error_o = (rd_req & ~racl_read_allowed) | (~rd_req & ~racl_write_allowed);
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tlul_request_loopback #(
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.ErrorRsp(RaclErrorRsp)
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) u_loopback (
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.clk_i,
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.rst_ni,
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.squash_req_i ( racl_error_o ),
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.tl_h2d_i ( tl_i ),
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.tl_d2h_o ( tl_o ),
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.tl_h2d_o ( tl_h2d_filtered ),
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.tl_d2h_i ( tl_d2h_filtered )
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);
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// Collect RACL error information
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assign racl_error_log_o.read_access = tl_i.a_opcode == tlul_pkg::Get;
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assign racl_error_log_o.racl_role = racl_role;
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assign racl_error_log_o.ctn_uid = top_racl_pkg::tlul_extract_ctn_uid_bits(tl_i.a_user.rsvd);
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end else begin : gen_no_racl_role_logic
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// Pass through and default assignments
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assign tl_h2d_filtered = tl_i;
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assign tl_o = tl_d2h_filtered;
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assign racl_error_o = 1'b0;
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assign racl_error_log_o = '0;
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end
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tlul_adapter_sram #(
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.SramAw ( SramAw ),
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.SramDw ( SramDw ),
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.Outstanding ( Outstanding ),
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.SramBusBankAW ( SramBusBankAW ),
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.ByteAccess ( ByteAccess ),
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.ErrOnWrite ( ErrOnWrite ),
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.ErrOnRead ( ErrOnRead ),
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.CmdIntgCheck ( CmdIntgCheck ),
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.EnableRspIntgGen ( EnableRspIntgGen ),
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.EnableDataIntgPt ( EnableDataIntgPt ),
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.SecFifoPtr ( SecFifoPtr ),
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.EnableReadback ( EnableReadback ),
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.DataXorAddr ( DataXorAddr )
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) tlul_adapter_sram (
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.clk_i,
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.rst_ni,
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.tl_i(tl_h2d_filtered),
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.tl_i(tl_d2h_filtered),
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.en_ifetch_i,
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.req_o,
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.req_type_o,
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.gnt_i,
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.we_o,
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.addr_o,
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.wdata_o,
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.intg_error_o,
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.user_rsvd_o,
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.rdata_i,
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.rvalid_i,
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.rerror_i,
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.compound_txn_in_progress_o,
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.readback_en_i,
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.readback_error_o,
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.wr_collision_i,
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.write_pending_i
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);
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// Not all RACL policies are used, even if RACL is enabled
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logic unused_policy_sel;
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assign unused_policy_sel = ^racl_policies_i;
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// Ensure that RACL signals are not undefined
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`ASSERT_KNOWN(RaclAdapterSramErrorKnown_A, racl_error_o)
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`ASSERT_KNOWN(RaclAdapterSramErrorLogKnown_A, racl_error_log_o)
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endmodule

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