From 7de72a0fc58bc12b6e786dacdc7d314121b607a4 Mon Sep 17 00:00:00 2001 From: Robert Schilling Date: Tue, 4 Feb 2025 16:58:34 +0100 Subject: [PATCH] [topgen] All RACL configs are relative to the top HJSON Signed-off-by: Robert Schilling --- .../data/autogen/top_darjeeling.gen.hjson | 2 +- hw/top_darjeeling/data/top_darjeeling.hjson | 20 +++++++++---------- util/topgen.py | 10 +++++++++- util/topgen/merge.py | 12 ++++++++--- util/topgen/validate.py | 1 + 5 files changed, 30 insertions(+), 15 deletions(-) diff --git a/hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson b/hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson index d9f2c57e218a8..34b28ddd0c934 100644 --- a/hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson +++ b/hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson @@ -13,7 +13,7 @@ type: top rnd_cnst_seed: 1017106219537032642877583828875051302543807092889754935647094601236425074047 datawidth: "32" - racl_config: top_darjeeling/data/racl/racl.hjson + racl_config: racl/racl.hjson power: { domains: diff --git a/hw/top_darjeeling/data/top_darjeeling.hjson b/hw/top_darjeeling/data/top_darjeeling.hjson index 5b5fb5407c47a..90c549a7063e7 100644 --- a/hw/top_darjeeling/data/top_darjeeling.hjson +++ b/hw/top_darjeeling/data/top_darjeeling.hjson @@ -16,7 +16,7 @@ datawidth: "32", // Enable RACL on Darjeeling based on the following configuration - racl_config: 'top_darjeeling/data/racl/racl.hjson' + racl_config: 'racl/racl.hjson' // Power information for the design power: { @@ -901,7 +901,7 @@ soc: {soc_mbx: "0x01465000"}, }, racl_mappings: { - soc: 'top_darjeeling/data/racl/all_rd_wr_mapping.hjson' + soc: 'racl/all_rd_wr_mapping.hjson' } }, { name: "mbx1", @@ -914,7 +914,7 @@ soc: {soc_mbx: "0x01465100"}, }, racl_mappings: { - soc: 'top_darjeeling/data/racl/all_rd_wr_mapping.hjson' + soc: 'racl/all_rd_wr_mapping.hjson' } }, { name: "mbx2", @@ -927,7 +927,7 @@ soc: {soc_mbx: "0x01465200"}, }, racl_mappings: { - soc: 'top_darjeeling/data/racl/all_rd_wr_mapping.hjson' + soc: 'racl/all_rd_wr_mapping.hjson' } }, { name: "mbx3", @@ -950,7 +950,7 @@ soc: {soc_mbx: "0x01465400"}, }, racl_mappings: { - soc: 'top_darjeeling/data/racl/all_rd_wr_mapping.hjson' + soc: 'racl/all_rd_wr_mapping.hjson' } }, { name: "mbx5", @@ -963,7 +963,7 @@ soc: {soc_mbx: "0x01465500"}, }, racl_mappings: { - soc: 'top_darjeeling/data/racl/all_rd_wr_mapping.hjson' + soc: 'racl/all_rd_wr_mapping.hjson' } }, { name: "mbx6", @@ -986,7 +986,7 @@ soc: {soc_dbg: "0x1000"}, }, racl_mappings: { - soc: 'top_darjeeling/data/racl/all_rd_wr_mapping.hjson' + soc: 'racl/all_rd_wr_mapping.hjson' } }, { name: "mbx_pcie0", @@ -999,7 +999,7 @@ soc: {soc_mbx: "0x01460100"}, }, racl_mappings: { - soc: 'top_darjeeling/data/racl/soc_rot_mapping.hjson' + soc: 'racl/soc_rot_mapping.hjson' } }, { name: "mbx_pcie1", @@ -1012,7 +1012,7 @@ soc: {soc_mbx: "0x01460200"}, }, racl_mappings: { - soc: 'top_darjeeling/data/racl/soc_rot_mapping.hjson' + soc: 'racl/soc_rot_mapping.hjson' } }, { name: "soc_dbg_ctrl", @@ -1049,7 +1049,7 @@ num_ranges: 32 } attr: "ipgen", - racl_mapping: 'top_darjeeling/data/racl/soc_rot_mapping.hjson' + racl_mapping: 'racl/soc_rot_mapping.hjson' }, { name: "rv_core_ibex", type: "rv_core_ibex", diff --git a/util/topgen.py b/util/topgen.py index 5d92c3e12035a..560142c670068 100755 --- a/util/topgen.py +++ b/util/topgen.py @@ -1125,6 +1125,7 @@ def _process_top( them to further populate the top config. It can raise exceptions for errors found in the process. """ + assert "cfg_path" in topcfg # Prepare the topcfg. extract_clocks(topcfg) ip_attrs = create_generic_ip_blocks(topcfg, alias_cfgs, cfg_path, out_path) @@ -1155,6 +1156,7 @@ def _process_top( if error != 0: raise SystemExit("Error occured while validating top.hjson") + completecfg = merge_top(topcfg, name_to_block, xbar_objs) name_to_hjson: Dict[str, Path] = {k: v.hjson_path @@ -1168,6 +1170,7 @@ def _process_top( params = _get_alert_handler_params(topcfg) name_to_block[name] = create_ipgen_ip_block(topcfg["name"], name, params, alias_cfgs) + # Delete return completecfg, name_to_block, name_to_hjson @@ -1530,8 +1533,13 @@ def main(): log.info("Generation pass {}".format(pass_idx + 1)) # Use the same seed for each pass to have stable random constants. secure_prng.reseed(topcfg["rnd_cnst_seed"]) + # Insert the config file path of the HJSON to allow parsing files relative + # the config directory + cfg_copy["cfg_path"] = Path(args.topcfg).parent completecfg, name_to_block, name_to_hjson = _process_top( cfg_copy, args, cfg_path, out_path_gen, alias_cfgs) + # Delete config path before dumping, not needed + del completecfg["cfg_path"] dump_path = Path(f"/tmp/top{topname}cfg_{pass_idx}.hjson") _dump_cfg(dump_path, completecfg) if pass_idx > 0 and filecmp.cmp( @@ -1824,4 +1832,4 @@ def render_template(template_path: str, rendered_path: Path, if __name__ == "__main__": - main() + main() \ No newline at end of file diff --git a/util/topgen/merge.py b/util/topgen/merge.py index 21aac42f8179b..28f980603dffa 100644 --- a/util/topgen/merge.py +++ b/util/topgen/merge.py @@ -1449,8 +1449,9 @@ def amend_racl(top_cfg: OrderedDict, if 'racl_config' not in top_cfg: return + assert "cfg_path" in top_cfg # Read the top-level RACL information - top_cfg['racl'] = parse_racl_config(top_cfg['racl_config']) + top_cfg["racl"] = parse_racl_config(top_cfg["cfg_path"] / top_cfg["racl_config"]) # Generate the RACL mappings for all subscribing IPs for m in top_cfg['module']: @@ -1467,8 +1468,8 @@ def amend_racl(top_cfg: OrderedDict, # once and need no further updates. continue parsed_register_mapping, parsed_window_mapping, racl_group, _ = ( - parse_racl_mapping(top_cfg['racl'], mapping_path, if_name, - block)) + parse_racl_mapping(top_cfg["racl"], top_cfg["cfg_path"] / mapping_path, + if_name, block)) m['racl_mappings'][if_name] = { 'racl_group': racl_group, 'register_mapping': parsed_register_mapping, @@ -1479,6 +1480,8 @@ def amend_racl(top_cfg: OrderedDict, def merge_top(topcfg: OrderedDict, name_to_block: Dict[str, IpBlock], xbarobjs: OrderedDict) -> OrderedDict: + + assert "cfg_path" in topcfg # Combine ip cfg into topcfg elaborate_instances(topcfg, name_to_block) @@ -1489,6 +1492,8 @@ def merge_top(topcfg: OrderedDict, # as part of alerts. # amend_clocks(topcfg) + assert "cfg_path" in topcfg + # Combine the wakeups amend_wkup(topcfg, name_to_block) amend_reset_request(topcfg, name_to_block) @@ -1517,6 +1522,7 @@ def merge_top(topcfg: OrderedDict, amend_resets(topcfg, name_to_block) # Parse racl configuration and annotate individual modules affected. + assert "cfg_path" in topcfg amend_racl(topcfg, name_to_block) # remove unwanted fields 'debug_mem_base_addr' diff --git a/util/topgen/validate.py b/util/topgen/validate.py index e16af6f2d7f09..a6955cab41745 100644 --- a/util/topgen/validate.py +++ b/util/topgen/validate.py @@ -85,6 +85,7 @@ 'l', 'list of wakeup requests each holding name, width, and module' ], + 'cfg_path': ['s', 'Path to the folder of the toplevel HJSON file'] } pinmux_required = {