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davidschrammeldavidschrammel
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[racl,rtl,sram_ctrl,spi_host,spi_device] Enable RACL ranges for sram_ctrl
And implement ranges for tlul_adapter_sram_racl and rewire parameters where it is already being used. Signed-off-by: David Schrammel <[email protected]>
1 parent f4a1d19 commit a53c3ff

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6 files changed

+78
-18
lines changed

6 files changed

+78
-18
lines changed

‎hw/ip/spi_device/rtl/spi_device.sv

Lines changed: 9 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -16,7 +16,11 @@ module spi_device
1616
parameter bit RaclErrorRsp = EnableRacl,
1717
parameter top_racl_pkg::racl_policy_sel_t RaclPolicySelVec[73] = '{73{0}},
1818
parameter top_racl_pkg::racl_policy_sel_t RaclPolicySelWinEgressbuffer = 0,
19-
parameter top_racl_pkg::racl_policy_sel_t RaclPolicySelWinIngressbuffer = 0
19+
parameter top_racl_pkg::racl_policy_sel_t RaclPolicySelWinIngressbuffer = 0,
20+
localparam top_racl_pkg::racl_range_t RaclPolicySelRangesEgressbuffer =
21+
'{base:'0,mask:{top_pkg::TL_AW{1'b1}},policy_sel:RaclPolicySelWinEgressbuffer},
22+
localparam top_racl_pkg::racl_range_t RaclPolicySelRangesIngressbuffer =
23+
'{base:'0,mask:{top_pkg::TL_AW{1'b1}},policy_sel:RaclPolicySelWinIngressbuffer}
2024
) (
2125
input clk_i,
2226
input rst_ni,
@@ -1687,7 +1691,8 @@ module spi_device
16871691
.ByteAccess (0),
16881692
.EnableRacl (EnableRacl),
16891693
.RaclErrorRsp (RaclErrorRsp),
1690-
.RaclPolicySelVec (RaclPolicySelWinEgressbuffer)
1694+
.RaclPolicySelNumRanges(1),
1695+
.RaclPolicySelRanges('{RaclPolicySelRangesEgressbuffer})
16911696
) u_tlul2sram_egress (
16921697
.clk_i,
16931698
.rst_ni,
@@ -1725,7 +1730,8 @@ module spi_device
17251730
.ByteAccess (0),
17261731
.EnableRacl (EnableRacl),
17271732
.RaclErrorRsp (RaclErrorRsp),
1728-
.RaclPolicySelVec (RaclPolicySelWinIngressbuffer)
1733+
.RaclPolicySelNumRanges(1),
1734+
.RaclPolicySelRanges('{RaclPolicySelRangesIngressbuffer})
17291735
) u_tlul2sram_ingress (
17301736
.clk_i,
17311737
.rst_ni,

‎hw/ip/spi_host/rtl/spi_host_window.sv

Lines changed: 5 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,9 @@ module spi_host_window
1010
parameter bit EnableRacl = 1'b0,
1111
parameter bit RaclErrorRsp = 1'b1,
1212
parameter top_racl_pkg::racl_policy_sel_t RaclPolicySelWinRXDATA = 0,
13-
parameter top_racl_pkg::racl_policy_sel_t RaclPolicySelWinTXDATA = 0
13+
parameter top_racl_pkg::racl_policy_sel_t RaclPolicySelWinTXDATA = 0,
14+
localparam top_racl_pkg::racl_range_t RaclPolicySelRangesTXDATA =
15+
'{base:'0,mask:{top_pkg::TL_AW{1'b1}},policy_sel:RaclPolicySelWinTXDATA}
1416
) (
1517
input clk_i,
1618
input rst_ni,
@@ -97,7 +99,8 @@ module spi_host_window
9799
.ErrOnRead(1),
98100
.EnableRacl(EnableRacl),
99101
.RaclErrorRsp(RaclErrorRsp),
100-
.RaclPolicySelVec(RaclPolicySelWinTXDATA)
102+
.RaclPolicySelNumRanges(1),
103+
.RaclPolicySelRanges('{RaclPolicySelRangesTXDATA})
101104
) u_adapter_tx (
102105
.clk_i,
103106
.rst_ni,

‎hw/ip/sram_ctrl/data/sram_ctrl.hjson

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -29,7 +29,7 @@
2929

3030
bus_interfaces: [
3131
{ protocol: "tlul", direction: "device", name: "regs", racl_support: true }
32-
{ protocol: "tlul", direction: "device", name: "ram" },
32+
{ protocol: "tlul", direction: "device", name: "ram" , racl_support: true }
3333
],
3434

3535
///////////////////////////

‎hw/ip/sram_ctrl/rtl/sram_ctrl.sv

Lines changed: 24 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -31,7 +31,9 @@ module sram_ctrl
3131
parameter lfsr_perm_t RndCnstLfsrPerm = RndCnstLfsrPermDefault,
3232
parameter bit EnableRacl = 1'b0,
3333
parameter bit RaclErrorRsp = EnableRacl,
34-
parameter top_racl_pkg::racl_policy_sel_t RaclPolicySelVecRegs[NumRegsRegs] = '{NumRegsRegs{0}}
34+
parameter top_racl_pkg::racl_policy_sel_t RaclPolicySelVecRegs[NumRegsRegs] = '{NumRegsRegs{0}},
35+
parameter int unsigned RaclPolicySelRangesRamNum = 1,
36+
parameter top_racl_pkg::racl_range_t RaclPolicySelRangesRam[RaclPolicySelRangesRamNum] = '{'0}
3537
) (
3638
// SRAM Clock
3739
input logic clk_i,
@@ -90,6 +92,13 @@ module sram_ctrl
9092

9193
`ASSERT_INIT(NonceWidthsLessThanSource_A, NonceWidth + LfsrWidth <= otp_ctrl_pkg::SramNonceWidth)
9294

95+
logic racl_error_regs;
96+
logic racl_error_ram;
97+
top_racl_pkg::racl_error_log_t racl_error_regs_log;
98+
top_racl_pkg::racl_error_log_t racl_error_ram_log;
99+
// We are combining all racl errors here because only one of them can be set at any time.
100+
assign racl_error_o = racl_error_regs | racl_error_ram;
101+
assign racl_error_log_o = racl_error_regs_log | racl_error_ram_log;
93102

94103
/////////////////////////////////////
95104
// Anchor incoming seeds and constants
@@ -137,8 +146,8 @@ module sram_ctrl
137146
.hw2reg,
138147
// RACL interface
139148
.racl_policies_i ( racl_policies_i ),
140-
.racl_error_o ( racl_error_o ),
141-
.racl_error_log_o ( racl_error_log_o ),
149+
.racl_error_o ( racl_error_regs ),
150+
.racl_error_log_o ( racl_error_regs_log),
142151
// SEC_CM: BUS.INTEGRITY
143152
.intg_err_o ( bus_integ_error[0] )
144153
);
@@ -492,7 +501,7 @@ module sram_ctrl
492501
mubi4_t reg_readback_en;
493502
assign reg_readback_en = mubi4_t'(reg2hw.readback.q);
494503

495-
tlul_adapter_sram #(
504+
tlul_adapter_sram_racl #(
496505
.SramAw(AddrWidth),
497506
.SramDw(DataWidth - tlul_pkg::DataIntgWidth),
498507
.Outstanding(2),
@@ -502,8 +511,12 @@ module sram_ctrl
502511
.EnableDataIntgGen(0),
503512
.EnableDataIntgPt(1), // SEC_CM: MEM.INTEGRITY
504513
.SecFifoPtr (1), // SEC_CM: TLUL_FIFO.CTR.REDUN
505-
.EnableReadback (1) // SEC_CM: MEM.READBACK
506-
) u_tlul_adapter_sram (
514+
.EnableReadback (1), // SEC_CM: MEM.READBACK
515+
.EnableRacl(EnableRacl),
516+
.RaclErrorRsp(RaclErrorRsp),
517+
.RaclPolicySelNumRanges(RaclPolicySelRangesRamNum),
518+
.RaclPolicySelRanges(RaclPolicySelRangesRam)
519+
) u_tlul_adapter_sram_racl (
507520
.clk_i,
508521
.rst_ni,
509522
.tl_i (ram_tl_in_gated),
@@ -526,7 +539,11 @@ module sram_ctrl
526539
.readback_en_i (reg_readback_en),
527540
.readback_error_o (readback_error),
528541
.wr_collision_i (sram_wr_collision),
529-
.write_pending_i (sram_wpending)
542+
.write_pending_i (sram_wpending),
543+
// RACL interface
544+
.racl_policies_i (racl_policies_i),
545+
.racl_error_o (racl_error_ram),
546+
.racl_error_log_o (racl_error_ram_log)
530547
);
531548

532549
logic key_valid;

‎hw/ip/sram_ctrl/rtl/sram_ctrl_ram_reg_top.sv

Lines changed: 14 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -6,13 +6,24 @@
66

77
`include "prim_assert.sv"
88

9-
module sram_ctrl_ram_reg_top (
9+
module sram_ctrl_ram_reg_top
10+
# (
11+
parameter bit EnableRacl = 1'b0,
12+
parameter bit RaclErrorRsp = 1'b1,
13+
parameter top_racl_pkg::racl_policy_sel_t RaclPolicySelVec[sram_ctrl_reg_pkg::NumRegsRam] =
14+
'{sram_ctrl_reg_pkg::NumRegsRam{0}}
15+
) (
1016
input clk_i,
1117
input rst_ni,
1218
input tlul_pkg::tl_h2d_t tl_i,
1319
output tlul_pkg::tl_d2h_t tl_o,
1420
// To HW
1521

22+
// RACL interface
23+
input top_racl_pkg::racl_policy_vec_t racl_policies_i,
24+
output logic racl_error_o,
25+
output top_racl_pkg::racl_error_log_t racl_error_log_o,
26+
1627
// Integrity check errors
1728
output logic intg_err_o
1829
);
@@ -39,4 +50,6 @@ module sram_ctrl_ram_reg_top (
3950
assign tl_o_pre = tl_reg_d2h;
4051

4152
// Unused signal tieoff
53+
logic unused_policy_sel;
54+
assign unused_policy_sel = ^racl_policies_i;
4255
endmodule

‎hw/ip/tlul/rtl/tlul_adapter_sram_racl.sv

Lines changed: 25 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -41,8 +41,8 @@ module tlul_adapter_sram_racl
4141
parameter bit DataXorAddr = 0, // 1: XOR data and address for address protection
4242
parameter bit EnableRacl = 0, // 1: Enable RACL checks on access
4343
parameter bit RaclErrorRsp = EnableRacl, // 1: Return TLUL error on RACL errors
44-
parameter top_racl_pkg::racl_policy_sel_t RaclPolicySelVec = 0, // RACL policy for this SRAM
45-
// adapter
44+
parameter int RaclPolicySelNumRanges = 1, // Number of ranges with a RACL policy
45+
parameter top_racl_pkg::racl_range_t RaclPolicySelRanges [RaclPolicySelNumRanges] = '{'0},
4646
localparam int WidthMult = SramDw / top_pkg::TL_DW,
4747
localparam int IntgWidth = tlul_pkg::DataIntgWidth * WidthMult,
4848
localparam int DataOutW = EnableDataIntgPt ? SramDw + IntgWidth : SramDw
@@ -98,12 +98,31 @@ module tlul_adapter_sram_racl
9898
);
9999

100100
logic req, rd_req, wr_req, racl_read_allowed, racl_write_allowed;
101+
logic [RaclPolicySelNumRanges-1:0] range_read_allowed;
102+
logic [RaclPolicySelNumRanges-1:0] range_write_allowed;
103+
104+
for (genvar r = 0; r < RaclPolicySelNumRanges; r++) begin : gen_racl_range_check
105+
top_racl_pkg::racl_range_t range;
106+
top_racl_pkg::racl_policy_t policy;
107+
logic range_match;
108+
assign range = RaclPolicySelRanges[r];
109+
assign policy = racl_policies_i[range.policy_sel];
110+
// Asserts that a valid range is defined
111+
`ASSERT(RaclAdapterSramNumRanges, range.mask > 0)
112+
// Check if the address is within range
113+
assign range_match = (tl_i.a_address & ~range.mask) == range.base;
114+
// If address mataches, lookup permissions for policy defined for this range
115+
assign range_read_allowed[r] = range_match & |(policy.read_perm & racl_role_vec);
116+
assign range_write_allowed[r] = range_match & |(policy.write_perm & racl_role_vec);
117+
end
118+
119+
assign racl_read_allowed = |range_read_allowed;
120+
assign racl_write_allowed = |range_write_allowed;
121+
101122
assign req = tl_i.a_valid & tl_o.a_ready;
102123
assign rd_req = req & (tl_i.a_opcode == tlul_pkg::Get);
103124
assign wr_req = req & (tl_i.a_opcode == tlul_pkg::PutFullData |
104125
tl_i.a_opcode == tlul_pkg::PutPartialData);
105-
assign racl_read_allowed = (|(racl_policies_i[RaclPolicySelVec].read_perm & racl_role_vec));
106-
assign racl_write_allowed = (|(racl_policies_i[RaclPolicySelVec].write_perm & racl_role_vec));
107126
assign racl_error_o = (rd_req & ~racl_read_allowed) | (wr_req & ~racl_write_allowed);
108127

109128
tlul_request_loopback #(
@@ -174,6 +193,8 @@ module tlul_adapter_sram_racl
174193
logic unused_policy_sel;
175194
assign unused_policy_sel = ^racl_policies_i;
176195

196+
`ASSERT(RaclAdapterSramNumRanges, EnableRacl |-> RaclPolicySelNumRanges > 0)
197+
177198
// Ensure that RACL signals are not undefined
178199
`ASSERT_KNOWN(RaclAdapterSramErrorKnown_A, racl_error_o)
179200
`ASSERT_KNOWN(RaclAdapterSramErrorLogKnown_A, racl_error_log_o)

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