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AlexJones0jwnrt
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[sw] Port rstmgr_cpu_info_test to devicetables
Signed-off-by: Alex Jones <[email protected]>
1 parent 8e90f01 commit a7f6327

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2 files changed

+13
-12
lines changed

2 files changed

+13
-12
lines changed

sw/device/tests/BUILD

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3619,14 +3619,15 @@ opentitan_test(
36193619
EARLGREY_SILICON_OWNER_ROM_EXT_ENVS,
36203620
{
36213621
"//hw/top_earlgrey:silicon_creator": None,
3622+
"//hw/top_darjeeling:sim_dv": None,
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},
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),
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verilator = verilator_params(
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timeout = "long",
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tags = ["broken"],
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),
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deps = [
3629-
"//hw/top_earlgrey/sw/autogen:top_earlgrey",
3630+
"//hw/top:dt",
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"//sw/device/lib/base:abs_mmio",
36313632
"//sw/device/lib/base:macros",
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"//sw/device/lib/base:mmio",

sw/device/tests/rstmgr_cpu_info_test.c

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -2,6 +2,9 @@
22
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
33
// SPDX-License-Identifier: Apache-2.0
44

5+
#include "dt/dt_pwrmgr.h" // Generated
6+
#include "dt/dt_rstmgr.h" // Generated
7+
#include "dt/dt_rv_core_ibex.h" // Generated
58
#include "sw/device/lib/base/abs_mmio.h"
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#include "sw/device/lib/base/macros.h"
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#include "sw/device/lib/base/mmio.h"
@@ -16,8 +19,6 @@
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#include "sw/device/lib/testing/test_framework/ottf_isrs.h"
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#include "sw/device/lib/testing/test_framework/ottf_main.h"
1821

19-
#include "hw/top_earlgrey/sw/autogen/top_earlgrey.h"
20-
2122
OTTF_DEFINE_TEST_CONFIG();
2223

2324
/**
@@ -32,7 +33,7 @@ OTTF_DEFINE_TEST_CONFIG();
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* the expected values for this single fault. The watch dog is then set up
3334
* and another illegal memory access is performed. Only this time
3435
* the exception handler performs another illegal read.
35-
* Causing the ibex to be haulted by the alert handler.
36+
* Causing the ibex to be halted by the alert handler.
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* The watch dog will eventually trigger a reset.
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*
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* 3. After the watchdog reset, the CPU info dump is checked against
@@ -182,16 +183,15 @@ bool test_main(void) {
182183
dif_aon_timer_t aon_timer;
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dif_pwrmgr_t pwrmgr;
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dif_rv_core_ibex_t ibex;
186+
dt_rv_core_ibex_t ibex_dt = (dt_rv_core_ibex_t)0;
187+
static_assert(kDtRvCoreIbexCount >= 1,
188+
"This test requires at least 1 Ibex core.");
185189

186190
// Initialize Handles.
187-
CHECK_DIF_OK(dif_rstmgr_init(
188-
mmio_region_from_addr(TOP_EARLGREY_RSTMGR_AON_BASE_ADDR), &rstmgr));
189-
CHECK_DIF_OK(dif_aon_timer_init(
190-
mmio_region_from_addr(TOP_EARLGREY_AON_TIMER_AON_BASE_ADDR), &aon_timer));
191-
CHECK_DIF_OK(dif_pwrmgr_init(
192-
mmio_region_from_addr(TOP_EARLGREY_PWRMGR_AON_BASE_ADDR), &pwrmgr));
193-
CHECK_DIF_OK(dif_rv_core_ibex_init(
194-
mmio_region_from_addr(TOP_EARLGREY_RV_CORE_IBEX_CFG_BASE_ADDR), &ibex));
191+
CHECK_DIF_OK(dif_rstmgr_init_from_dt(kDtRstmgrAon, &rstmgr));
192+
CHECK_DIF_OK(dif_aon_timer_init_from_dt(kDtAonTimerAon, &aon_timer));
193+
CHECK_DIF_OK(dif_pwrmgr_init_from_dt(kDtPwrmgrAon, &pwrmgr));
194+
CHECK_DIF_OK(dif_rv_core_ibex_init_from_dt(ibex_dt, &ibex));
195195

196196
switch (rstmgr_testutils_reason_get()) {
197197
case kDifRstmgrResetInfoPor: // The first power-up.

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