[sw] Port rstmgr_cpu_info_test to devicetables

Signed-off-by: Alex Jones <[email protected]>

Author: AlexJones0

sw/device/tests/BUILD

@@ -3594,14 +3594,15 @@ opentitan_test(
         EARLGREY_SILICON_OWNER_ROM_EXT_ENVS,
         {
             "//hw/top_earlgrey:silicon_creator": None,
+            "//hw/top_darjeeling:sim_dv": None,
         },
     ),
     verilator = verilator_params(
         timeout = "long",
         tags = ["broken"],
     ),
     deps = [
-        "//hw/top_earlgrey/sw/autogen:top_earlgrey",
+        "//hw/top:dt",
         "//sw/device/lib/base:abs_mmio",
         "//sw/device/lib/base:macros",
         "//sw/device/lib/base:mmio",

sw/device/tests/rstmgr_cpu_info_test.c

@@ -2,6 +2,9 @@
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
+#include "dt/dt_pwrmgr.h"        // Generated
+#include "dt/dt_rstmgr.h"        // Generated
+#include "dt/dt_rv_core_ibex.h"  // Generated
 #include "sw/device/lib/base/abs_mmio.h"
 #include "sw/device/lib/base/macros.h"
 #include "sw/device/lib/base/mmio.h"
@@ -16,8 +19,6 @@
 #include "sw/device/lib/testing/test_framework/ottf_isrs.h"
 #include "sw/device/lib/testing/test_framework/ottf_main.h"
 
-#include "hw/top_earlgrey/sw/autogen/top_earlgrey.h"
-
 OTTF_DEFINE_TEST_CONFIG();
 
 /**
@@ -32,7 +33,7 @@ OTTF_DEFINE_TEST_CONFIG();
  *    the expected values for this single fault. The watch dog is then set up
  *    and another illegal memory access is performed. Only this time
  *    the exception handler performs another illegal read.
- *    Causing the ibex to be haulted by the alert handler.
+ *    Causing the ibex to be halted by the alert handler.
  *    The watch dog will eventually trigger a reset.
  *
  * 3. After the watchdog reset, the CPU info dump is checked against
@@ -60,6 +61,7 @@ extern const char kDoubleFaultSecondAddr[];
 
 // A handle to the reset manager.
 static dif_rstmgr_t rstmgr;
+static dt_rstmgr_t kRstmgrDt = kDtRstmgrAon;
 
 // This variable is used to ensure loads from an address aren't optimised out.
 volatile static uint32_t addr_val;
@@ -180,18 +182,19 @@ bool test_main(void) {
   dif_rv_core_ibex_crash_dump_info_t dump;
 
   dif_aon_timer_t aon_timer;
+  dt_aon_timer_t aon_timer_dt = kDtAonTimerAon;
   dif_pwrmgr_t pwrmgr;
+  dt_pwrmgr_t pwrmgr_dt = kDtPwrmgrAon;
   dif_rv_core_ibex_t ibex;
+  dt_rv_core_ibex_t ibex_dt = (dt_rv_core_ibex_t)0;
+  static_assert(kDtRvCoreIbexCount >= 1,
+                "This test requires at least 1 Ibex core.");
 
   // Initialize Handles.
-  CHECK_DIF_OK(dif_rstmgr_init(
-      mmio_region_from_addr(TOP_EARLGREY_RSTMGR_AON_BASE_ADDR), &rstmgr));
-  CHECK_DIF_OK(dif_aon_timer_init(
-      mmio_region_from_addr(TOP_EARLGREY_AON_TIMER_AON_BASE_ADDR), &aon_timer));
-  CHECK_DIF_OK(dif_pwrmgr_init(
-      mmio_region_from_addr(TOP_EARLGREY_PWRMGR_AON_BASE_ADDR), &pwrmgr));
-  CHECK_DIF_OK(dif_rv_core_ibex_init(
-      mmio_region_from_addr(TOP_EARLGREY_RV_CORE_IBEX_CFG_BASE_ADDR), &ibex));
+  CHECK_DIF_OK(dif_rstmgr_init_from_dt(kRstmgrDt, &rstmgr));
+  CHECK_DIF_OK(dif_aon_timer_init_from_dt(aon_timer_dt, &aon_timer));
+  CHECK_DIF_OK(dif_pwrmgr_init_from_dt(pwrmgr_dt, &pwrmgr));
+  CHECK_DIF_OK(dif_rv_core_ibex_init_from_dt(ibex_dt, &ibex));
 
   switch (rstmgr_testutils_reason_get()) {
     case kDifRstmgrResetInfoPor:  // The first power-up.