diff --git a/hw/ip_templates/ac_range_check/ac_range_check.core.tpl b/hw/ip_templates/ac_range_check/ac_range_check.core.tpl index 739540a509fcc..2dd6631f6ee07 100644 --- a/hw/ip_templates/ac_range_check/ac_range_check.core.tpl +++ b/hw/ip_templates/ac_range_check/ac_range_check.core.tpl @@ -12,6 +12,8 @@ filesets: - lowrisc:prim:mubi - lowrisc:prim:all - lowrisc:systems:top_racl_pkg + - lowrisc:prim:edge_detector + - lowrisc:prim:onehot files: - rtl/${module_instance_name}_reg_pkg.sv - rtl/${module_instance_name}_reg_top.sv diff --git a/hw/ip_templates/ac_range_check/doc/checklist.md b/hw/ip_templates/ac_range_check/doc/checklist.md new file mode 100644 index 0000000000000..f663bc000f973 --- /dev/null +++ b/hw/ip_templates/ac_range_check/doc/checklist.md @@ -0,0 +1,275 @@ +--- +title: "AC_RANGE_CHECK Checklist" +--- + + +This checklist is for [Hardware Stage](/doc/project_governance/development_stages.md) transitions for the [AC_RANGE_CHECK peripheral.](../README.md) +All checklist items refer to the content in the [Checklist.](/doc/project_governance/checklist/README.md) + +## Design Checklist + +### D1 + +Type | Item | Resolution | Note/Collaterals +--------------|--------------------------------|-------------|------------------ +Documentation | [SPEC_COMPLETE][] | Not Started | [AC_RANGE_CHECK Design Spec](../README.md) +Documentation | [CSR_DEFINED][] | Not Started | +RTL | [CLKRST_CONNECTED][] | Not Started | +RTL | [IP_TOP][] | Not Started | +RTL | [IP_INSTANTIABLE][] | Not Started | +RTL | [PHYSICAL_MACROS_DEFINED_80][] | Not Started | +RTL | [FUNC_IMPLEMENTED][] | Not Started | +RTL | [ASSERT_KNOWN_ADDED][] | Not Started | +Code Quality | [LINT_SETUP][] | Not Started | +Security | [SEC_CM_SCOPED][] | Not Started | + +[SPEC_COMPLETE]: /doc/project_governance/checklist/README.md#spec_complete +[CSR_DEFINED]: /doc/project_governance/checklist/README.md#csr_defined +[CLKRST_CONNECTED]: /doc/project_governance/checklist/README.md#clkrst_connected +[IP_TOP]: /doc/project_governance/checklist/README.md#ip_top +[IP_INSTANTIABLE]: /doc/project_governance/checklist/README.md#ip_instantiable +[PHYSICAL_MACROS_DEFINED_80]: /doc/project_governance/checklist/README.md#physical_macros_defined_80 +[FUNC_IMPLEMENTED]: /doc/project_governance/checklist/README.md#func_implemented +[ASSERT_KNOWN_ADDED]: /doc/project_governance/checklist/README.md#assert_known_added +[LINT_SETUP]: /doc/project_governance/checklist/README.md#lint_setup +[SEC_CM_SCOPED]: /doc/project_governance/checklist/README.md#sec_cm_scoped + +### D2 + +Type | Item | Resolution | Note/Collaterals +--------------|---------------------------|-------------|------------------ +Documentation | [NEW_FEATURES][] | Not Started | +Documentation | [BLOCK_DIAGRAM][] | Not Started | +Documentation | [DOC_INTERFACE][] | Not Started | +Documentation | [DOC_INTEGRATION_GUIDE][] | Not Started | +Documentation | [MISSING_FUNC][] | Not Started | +Documentation | [FEATURE_FROZEN][] | Not Started | +RTL | [FEATURE_COMPLETE][] | Not Started | +RTL | [PORT_FROZEN][] | Not Started | +RTL | [ARCHITECTURE_FROZEN][] | Not Started | +RTL | [REVIEW_TODO][] | Not Started | +RTL | [STYLE_X][] | Not Started | +RTL | [CDC_SYNCMACRO][] | Not Started | +Code Quality | [LINT_PASS][] | Not Started | +Code Quality | [CDC_SETUP][] | Not Started | +Code Quality | [RDC_SETUP][] | Not Started | +Code Quality | [AREA_CHECK][] | Not Started | +Code Quality | [TIMING_CHECK][] | Not Started | +Security | [SEC_CM_DOCUMENTED][] | Not Started | + +[NEW_FEATURES]: /doc/project_governance/checklist/README.md#new_features +[BLOCK_DIAGRAM]: /doc/project_governance/checklist/README.md#block_diagram +[DOC_INTERFACE]: /doc/project_governance/checklist/README.md#doc_interface +[DOC_INTEGRATION_GUIDE]: /doc/project_governance/checklist/README.md#doc_integration_guide +[MISSING_FUNC]: /doc/project_governance/checklist/README.md#missing_func +[FEATURE_FROZEN]: /doc/project_governance/checklist/README.md#feature_frozen +[FEATURE_COMPLETE]: /doc/project_governance/checklist/README.md#feature_complete +[PORT_FROZEN]: /doc/project_governance/checklist/README.md#port_frozen +[ARCHITECTURE_FROZEN]: /doc/project_governance/checklist/README.md#architecture_frozen +[REVIEW_TODO]: /doc/project_governance/checklist/README.md#review_todo +[STYLE_X]: /doc/project_governance/checklist/README.md#style_x +[CDC_SYNCMACRO]: /doc/project_governance/checklist/README.md#cdc_syncmacro +[LINT_PASS]: /doc/project_governance/checklist/README.md#lint_pass +[CDC_SETUP]: /doc/project_governance/checklist/README.md#cdc_setup +[RDC_SETUP]: /doc/project_governance/checklist/README.md#rdc_setup +[AREA_CHECK]: /doc/project_governance/checklist/README.md#area_check +[TIMING_CHECK]: /doc/project_governance/checklist/README.md#timing_check +[SEC_CM_DOCUMENTED]: /doc/project_governance/checklist/README.md#sec_cm_documented + +### D2S + + Type | Item | Resolution | Note/Collaterals +--------------|------------------------------|-------------|------------------ +Security | [SEC_CM_ASSETS_LISTED][] | Not Started | +Security | [SEC_CM_IMPLEMENTED][] | Not Started | +Security | [SEC_CM_RND_CNST][] | Not Started | +Security | [SEC_CM_NON_RESET_FLOPS][] | Not Started | +Security | [SEC_CM_SHADOW_REGS][] | Not Started | +Security | [SEC_CM_RTL_REVIEWED][] | Not Started | +Security | [SEC_CM_COUNCIL_REVIEWED][] | Not Started | + +[SEC_CM_ASSETS_LISTED]: /doc/project_governance/checklist/README.md#sec_cm_assets_listed +[SEC_CM_IMPLEMENTED]: /doc/project_governance/checklist/README.md#sec_cm_implemented +[SEC_CM_RND_CNST]: /doc/project_governance/checklist/README.md#sec_cm_rnd_cnst +[SEC_CM_NON_RESET_FLOPS]: /doc/project_governance/checklist/README.md#sec_cm_non_reset_flops +[SEC_CM_SHADOW_REGS]: /doc/project_governance/checklist/README.md#sec_cm_shadow_regs +[SEC_CM_RTL_REVIEWED]: /doc/project_governance/checklist/README.md#sec_cm_rtl_reviewed +[SEC_CM_COUNCIL_REVIEWED]: /doc/project_governance/checklist/README.md#sec_cm_council_reviewed + +### D3 + + Type | Item | Resolution | Note/Collaterals +--------------|-------------------------|-------------|------------------ +Documentation | [NEW_FEATURES_D3][] | Not Started | +RTL | [TODO_COMPLETE][] | Not Started | +Code Quality | [LINT_COMPLETE][] | Not Started | +Code Quality | [CDC_COMPLETE][] | Not Started | +Code Quality | [RDC_COMPLETE][] | Not Started | +Review | [REVIEW_RTL][] | Not Started | +Review | [REVIEW_DELETED_FF][] | Not Started | +Review | [REVIEW_SW_CHANGE][] | Not Started | +Review | [REVIEW_SW_ERRATA][] | Not Started | +Review | Reviewer(s) | Not Started | +Review | Signoff date | Not Started | + +[NEW_FEATURES_D3]: /doc/project_governance/checklist/README.md#new_features_d3 +[TODO_COMPLETE]: /doc/project_governance/checklist/README.md#todo_complete +[LINT_COMPLETE]: /doc/project_governance/checklist/README.md#lint_complete +[CDC_COMPLETE]: /doc/project_governance/checklist/README.md#cdc_complete +[RDC_COMPLETE]: /doc/project_governance/checklist/README.md#rdc_complete +[REVIEW_RTL]: /doc/project_governance/checklist/README.md#review_rtl +[REVIEW_DELETED_FF]: /doc/project_governance/checklist/README.md#review_deleted_ff +[REVIEW_SW_CHANGE]: /doc/project_governance/checklist/README.md#review_sw_change +[REVIEW_SW_ERRATA]: /doc/project_governance/checklist/README.md#review_sw_errata + +## Verification Checklist + +### V1 + + Type | Item | Resolution | Note/Collaterals +--------------|---------------------------------------|-------------|------------------ +Documentation | [DV_DOC_DRAFT_COMPLETED][] | Not Started | [AC_RANGE_CHECK DV document](../dv/README.md) +Documentation | [TESTPLAN_COMPLETED][] | Not Started | [AC_RANGE_CHECK Testplan](../dv/README.md#testplan) +Testbench | [TB_TOP_CREATED][] | Not Started | +Testbench | [PRELIMINARY_ASSERTION_CHECKS_ADDED][]| Not Started | +Testbench | [SIM_TB_ENV_CREATED][] | Not Started | +Testbench | [SIM_RAL_MODEL_GEN_AUTOMATED][] | Not Started | +Testbench | [CSR_CHECK_GEN_AUTOMATED][] | Not Started | +Testbench | [TB_GEN_AUTOMATED][] | Not Started | +Tests | [SIM_SMOKE_TEST_PASSING][] | Not Started | +Tests | [SIM_CSR_MEM_TEST_SUITE_PASSING][] | Not Started | +Tests | [FPV_MAIN_ASSERTIONS_PROVEN][] | Not Started | +Tool Setup | [SIM_ALT_TOOL_SETUP][] | Not Started | +Regression | [SIM_SMOKE_REGRESSION_SETUP][] | Not Started | +Regression | [SIM_NIGHTLY_REGRESSION_SETUP][] | Not Started | +Regression | [FPV_REGRESSION_SETUP][] | Not Started | +Coverage | [SIM_COVERAGE_MODEL_ADDED][] | Not Started | +Code Quality | [TB_LINT_SETUP][] | Not Started | +Integration | [PRE_VERIFIED_SUB_MODULES_V1][] | Not Started | +Review | [DESIGN_SPEC_REVIEWED][] | Not Started | +Review | [TESTPLAN_REVIEWED][] | Not Started | +Review | [STD_TEST_CATEGORIES_PLANNED][] | Not Started | Exception (?) +Review | [V2_CHECKLIST_SCOPED][] | Not Started | + +[DV_DOC_DRAFT_COMPLETED]: /doc/project_governance/checklist/README.md#dv_doc_draft_completed +[TESTPLAN_COMPLETED]: /doc/project_governance/checklist/README.md#testplan_completed +[TB_TOP_CREATED]: /doc/project_governance/checklist/README.md#tb_top_created +[PRELIMINARY_ASSERTION_CHECKS_ADDED]: /doc/project_governance/checklist/README.md#preliminary_assertion_checks_added +[SIM_TB_ENV_CREATED]: /doc/project_governance/checklist/README.md#sim_tb_env_created +[SIM_RAL_MODEL_GEN_AUTOMATED]: /doc/project_governance/checklist/README.md#sim_ral_model_gen_automated +[CSR_CHECK_GEN_AUTOMATED]: /doc/project_governance/checklist/README.md#csr_check_gen_automated +[TB_GEN_AUTOMATED]: /doc/project_governance/checklist/README.md#tb_gen_automated +[SIM_SMOKE_TEST_PASSING]: /doc/project_governance/checklist/README.md#sim_smoke_test_passing +[SIM_CSR_MEM_TEST_SUITE_PASSING]: /doc/project_governance/checklist/README.md#sim_csr_mem_test_suite_passing +[FPV_MAIN_ASSERTIONS_PROVEN]: /doc/project_governance/checklist/README.md#fpv_main_assertions_proven +[SIM_ALT_TOOL_SETUP]: /doc/project_governance/checklist/README.md#sim_alt_tool_setup +[SIM_SMOKE_REGRESSION_SETUP]: /doc/project_governance/checklist/README.md#sim_smoke_regression_setup +[SIM_NIGHTLY_REGRESSION_SETUP]: /doc/project_governance/checklist/README.md#sim_nightly_regression_setup +[FPV_REGRESSION_SETUP]: /doc/project_governance/checklist/README.md#fpv_regression_setup +[SIM_COVERAGE_MODEL_ADDED]: /doc/project_governance/checklist/README.md#sim_coverage_model_added +[TB_LINT_SETUP]: /doc/project_governance/checklist/README.md#tb_lint_setup +[PRE_VERIFIED_SUB_MODULES_V1]: /doc/project_governance/checklist/README.md#pre_verified_sub_modules_v1 +[DESIGN_SPEC_REVIEWED]: /doc/project_governance/checklist/README.md#design_spec_reviewed +[TESTPLAN_REVIEWED]: /doc/project_governance/checklist/README.md#testplan_reviewed +[STD_TEST_CATEGORIES_PLANNED]: /doc/project_governance/checklist/README.md#std_test_categories_planned +[V2_CHECKLIST_SCOPED]: /doc/project_governance/checklist/README.md#v2_checklist_scoped + +### V2 + + Type | Item | Resolution | Note/Collaterals +--------------|-----------------------------------------|-------------|------------------ +Documentation | [DESIGN_DELTAS_CAPTURED_V2][] | Not Started | +Documentation | [DV_DOC_COMPLETED][] | Not Started | +Testbench | [FUNCTIONAL_COVERAGE_IMPLEMENTED][] | Not Started | +Testbench | [ALL_INTERFACES_EXERCISED][] | Not Started | +Testbench | [ALL_ASSERTION_CHECKS_ADDED][] | Not Started | +Testbench | [SIM_TB_ENV_COMPLETED][] | Not Started | +Tests | [SIM_ALL_TESTS_PASSING][] | Not Started | +Tests | [FPV_ALL_ASSERTIONS_WRITTEN][] | Not Started | +Tests | [FPV_ALL_ASSUMPTIONS_REVIEWED][] | Not Started | +Tests | [SIM_FW_SIMULATED][] | Not Started | +Regression | [SIM_NIGHTLY_REGRESSION_V2][] | Not Started | +Coverage | [SIM_CODE_COVERAGE_V2][] | Not Started | +Coverage | [SIM_FUNCTIONAL_COVERAGE_V2][] | Not Started | +Coverage | [FPV_CODE_COVERAGE_V2][] | Not Started | +Coverage | [FPV_COI_COVERAGE_V2][] | Not Started | +Integration | [PRE_VERIFIED_SUB_MODULES_V2][] | Not Started | +Issues | [NO_HIGH_PRIORITY_ISSUES_PENDING][] | Not Started | +Issues | [ALL_LOW_PRIORITY_ISSUES_ROOT_CAUSED][] | Not Started | +Review | [DV_DOC_TESTPLAN_REVIEWED][] | Not Started | +Review | [V3_CHECKLIST_SCOPED][] | Not Started | + +[DESIGN_DELTAS_CAPTURED_V2]: /doc/project_governance/checklist/README.md#design_deltas_captured_v2 +[DV_DOC_COMPLETED]: /doc/project_governance/checklist/README.md#dv_doc_completed +[FUNCTIONAL_COVERAGE_IMPLEMENTED]: /doc/project_governance/checklist/README.md#functional_coverage_implemented +[ALL_INTERFACES_EXERCISED]: /doc/project_governance/checklist/README.md#all_interfaces_exercised +[ALL_ASSERTION_CHECKS_ADDED]: /doc/project_governance/checklist/README.md#all_assertion_checks_added +[SIM_TB_ENV_COMPLETED]: /doc/project_governance/checklist/README.md#sim_tb_env_completed +[SIM_ALL_TESTS_PASSING]: /doc/project_governance/checklist/README.md#sim_all_tests_passing +[FPV_ALL_ASSERTIONS_WRITTEN]: /doc/project_governance/checklist/README.md#fpv_all_assertions_written +[FPV_ALL_ASSUMPTIONS_REVIEWED]: /doc/project_governance/checklist/README.md#fpv_all_assumptions_reviewed +[SIM_FW_SIMULATED]: /doc/project_governance/checklist/README.md#sim_fw_simulated +[SIM_NIGHTLY_REGRESSION_V2]: /doc/project_governance/checklist/README.md#sim_nightly_regression_v2 +[SIM_CODE_COVERAGE_V2]: /doc/project_governance/checklist/README.md#sim_code_coverage_v2 +[SIM_FUNCTIONAL_COVERAGE_V2]: /doc/project_governance/checklist/README.md#sim_functional_coverage_v2 +[FPV_CODE_COVERAGE_V2]: /doc/project_governance/checklist/README.md#fpv_code_coverage_v2 +[FPV_COI_COVERAGE_V2]: /doc/project_governance/checklist/README.md#fpv_coi_coverage_v2 +[PRE_VERIFIED_SUB_MODULES_V2]: /doc/project_governance/checklist/README.md#pre_verified_sub_modules_v2 +[NO_HIGH_PRIORITY_ISSUES_PENDING]: /doc/project_governance/checklist/README.md#no_high_priority_issues_pending +[ALL_LOW_PRIORITY_ISSUES_ROOT_CAUSED]:/doc/project_governance/checklist/README.md#all_low_priority_issues_root_caused +[DV_DOC_TESTPLAN_REVIEWED]: /doc/project_governance/checklist/README.md#dv_doc_testplan_reviewed +[V3_CHECKLIST_SCOPED]: /doc/project_governance/checklist/README.md#v3_checklist_scoped + +### V2S + + Type | Item | Resolution | Note/Collaterals +--------------|-----------------------------------------|-------------|------------------ +Documentation | [SEC_CM_TESTPLAN_COMPLETED][] | Not Started | +Tests | [FPV_SEC_CM_VERIFIED][] | Not Started | +Tests | [SIM_SEC_CM_VERIFIED][] | Not Started | +Coverage | [SIM_COVERAGE_REVIEWED][] | Not Started | +Review | [SEC_CM_DV_REVIEWED][] | Not Started | + +[SEC_CM_TESTPLAN_COMPLETED]: /doc/project_governance/checklist/README.md#sec_cm_testplan_completed +[FPV_SEC_CM_VERIFIED]: /doc/project_governance/checklist/README.md#fpv_sec_cm_verified +[SIM_SEC_CM_VERIFIED]: /doc/project_governance/checklist/README.md#sim_sec_cm_verified +[SIM_COVERAGE_REVIEWED]: /doc/project_governance/checklist/README.md#sim_coverage_reviewed +[SEC_CM_DV_REVIEWED]: /doc/project_governance/checklist/README.md#sec_cm_dv_reviewed + +### V3 + + Type | Item | Resolution | Note/Collaterals +--------------|-----------------------------------|-------------|------------------ +Documentation | [DESIGN_DELTAS_CAPTURED_V3][] | Not Started | +Tests | [X_PROP_ANALYSIS_COMPLETED][] | Not Started | +Tests | [FPV_ASSERTIONS_PROVEN_AT_V3][] | Not Started | +Regression | [SIM_NIGHTLY_REGRESSION_AT_V3][] | Not Started | +Coverage | [SIM_CODE_COVERAGE_AT_100][] | Not Started | +Coverage | [SIM_FUNCTIONAL_COVERAGE_AT_100][]| Not Started | +Coverage | [FPV_CODE_COVERAGE_AT_100][] | Not Started | +Coverage | [FPV_COI_COVERAGE_AT_100][] | Not Started | +Code Quality | [ALL_TODOS_RESOLVED][] | Not Started | +Code Quality | [NO_TOOL_WARNINGS_THROWN][] | Not Started | +Code Quality | [TB_LINT_COMPLETE][] | Not Started | +Integration | [PRE_VERIFIED_SUB_MODULES_V3][] | Not Started | +Issues | [NO_ISSUES_PENDING][] | Not Started | +Review | Reviewer(s) | Not Started | +Review | Signoff date | Not Started | + +[DESIGN_DELTAS_CAPTURED_V3]: /doc/project_governance/checklist/README.md#design_deltas_captured_v3 +[X_PROP_ANALYSIS_COMPLETED]: /doc/project_governance/checklist/README.md#x_prop_analysis_completed +[FPV_ASSERTIONS_PROVEN_AT_V3]: /doc/project_governance/checklist/README.md#fpv_assertions_proven_at_v3 +[SIM_NIGHTLY_REGRESSION_AT_V3]: /doc/project_governance/checklist/README.md#sim_nightly_regression_at_v3 +[SIM_CODE_COVERAGE_AT_100]: /doc/project_governance/checklist/README.md#sim_code_coverage_at_100 +[SIM_FUNCTIONAL_COVERAGE_AT_100]:/doc/project_governance/checklist/README.md#sim_functional_coverage_at_100 +[FPV_CODE_COVERAGE_AT_100]: /doc/project_governance/checklist/README.md#fpv_code_coverage_at_100 +[FPV_COI_COVERAGE_AT_100]: /doc/project_governance/checklist/README.md#fpv_coi_coverage_at_100 +[ALL_TODOS_RESOLVED]: /doc/project_governance/checklist/README.md#all_todos_resolved +[NO_TOOL_WARNINGS_THROWN]: /doc/project_governance/checklist/README.md#no_tool_warnings_thrown +[TB_LINT_COMPLETE]: /doc/project_governance/checklist/README.md#tb_lint_complete +[PRE_VERIFIED_SUB_MODULES_V3]: /doc/project_governance/checklist/README.md#pre_verified_sub_modules_v3 +[NO_ISSUES_PENDING]: /doc/project_governance/checklist/README.md#no_issues_pending diff --git a/hw/ip_templates/ac_range_check/dv/README.md.tpl b/hw/ip_templates/ac_range_check/dv/README.md.tpl new file mode 100644 index 0000000000000..207b8387c29b4 --- /dev/null +++ b/hw/ip_templates/ac_range_check/dv/README.md.tpl @@ -0,0 +1,129 @@ +# AC_RANGE_CHECK DV document + +${"##"} Goals +* **DV** + * Verify all AC_RANGE_CHECK IP features by running dynamic simulations with a SV/UVM based testbench + * Develop and run all tests based on the [testplan](#testplan) below towards closing code and functional coverage on the IP and all of its sub-modules +* **FPV** + * Verify TileLink device protocol compliance with an SVA based testbench + +${"##"} Current status +* [Design & verification stage](../../../../README.md) + * [HW development stages](../../../../../doc/project_governance/development_stages.md) +* [Simulation results](https://reports.opentitan.org/hw/top_${topname}/ip_autogen/ac_range_check/dv/latest/report.html) + +${"##"} Design features +For detailed information on `ac_range_check` design features, please see the [`ac_range_check` HWIP technical specification](../README.md). + +${"##"} Testbench architecture +The `ac_range_check` UVM DV testbench has been constructed based on the [CIP testbench architecture](../../../../dv/sv/cip_lib/README.md). + +${"###"} Block diagram +![Block diagram](./doc/tb.svg) + +${"###"} Top level testbench +Top level testbench is located at `hw/top_${topname}/ip_autogen/ac_range_check/dv/tb/tb.sv`. +It instantiates the `ac_range_check` DUT module `hw/ip/ac_range_check/rtl/ac_range_check.sv`. +In addition, the testbench instantiates the following interfaces, connects them to the DUT and sets their handle into `uvm_config_db`: +* [Clock and reset interface](../../../../dv/sv/common_ifs/README.md) +* [Reset shadowed interface](../../../../dv/sv/common_ifs/README.md) // TODO add something in this doc about this interface. +* [TileLink host interface for the CSRs](../../../../dv/sv/tl_agent/README.md) +* [TileLink host interface for the Unfiltered CTN accesses](../../../../dv/sv/tl_agent/README.md) +* [TileLink device interface for the Filtered CTN accesses](../../../../dv/sv/tl_agent/README.md) +* Interrupts ([`pins_if`](../../../../dv/sv/common_ifs/README.md)) +* Alerts ([`alert_esc_if`](../../../../dv/sv/alert_esc_agent/README.md)) + + +${"###"} Common DV utility components +The following utilities provide generic helper tasks and functions to perform activities that are common across the project: +* [dv_utils_pkg](../../../../dv/sv/dv_utils/README.md) +* [csr_utils_pkg](../../../../dv/sv/csr_utils/README.md) + +${"###"} Compile-time configurations +[list compile time configurations, if any and what are they used for] + +${"###"} Global types & methods +All common types and methods defined at the package level can be found in `ac_range_check_env_pkg`. +Some of them in use are: +```systemverilog +[list a few parameters, types & methods; no need to mention all] +``` + +${"###"} TL_agent +* `ac_range_check` UVM environment instantiates a (already handled in CIP base env) [tl_agent](../../../../dv/sv/tl_agent/README.md) which provides the ability to drive and independently monitor random traffic via TL host interface into `ac_range_check` device, to access to the CSRs (Control/Status Registers). +* Host interface to the Unfiltered CTN accesses. +* Device interface to the Filtered CTN accesses. + +The `tl_agent` monitor supplies partial TileLink request packets as well as completed TileLink response packets over the TLM analysis port for further processing within the `ac_range_check` scoreboard. + +${"###"} Alert_agent +`ac_range_check` testbench instantiates (already handled in CIP base env) [alert_agents](../../../../dv/sv/alert_esc_agent/README.md): +[list alert names]. +The alert_agents provide the ability to drive and independently monitor alert handshakes via alert interfaces in AC_RANGE_CHECK device. + +${"###"} UVM RAL Model +The `ac_range_check` RAL model is created with the [`ralgen`](../../../../dv/tools/ralgen/README.md) FuseSoC generator script automatically when the simulation is at the build stage. + +It can be created manually by invoking [`regtool`](../../../../../util/reggen/doc/setup_and_use.md): + +${"####"} Sequence cfg +An efficient way to develop test sequences is by providing some random variables that are used to configure the DUT / drive stimulus. +The random variables are constrained using weights and knobs that can be controlled. +These weights and knobs take on a "default" value that will result in the widest exploration of the design state space, when the test sequence is randomized and run as-is. +To steer the randomization towards a particular distribution or to achieve interesting combinations of the random variables, the test sequence can be extended to create a specialized variant. +In this extended sequence, nothing would need to be done, other than setting those weights and knobs appropriately. +This helps increase the likelihood of hitting the design corners that would otherwise be difficult to achieve, while maximizing reuse. + +This object aims to provide such run-time controls. + +${"####"} Env cfg +The `ac_range_check_env_cfg`, environment configuration object provides access to the following elements: +* Build-time controls to configure the UVM environment composition during the `build_phase` +* Downstream agent configuration objects for ease of lookup from any environment component + * This includes the `tl_agent_cfg` objects for both TL interfaces +* All virtual interfaces that connect to the DUT listed above (retrieved from the `uvm_config_db`) +* Sequence configuration object described above + +All environment components contain a handle to an instance of this class (that was created in the test class via the parent `dv_base_test`). +By housing all of the above, all pertinent information is more easily shared with all environment components. + +${"###"} Stimulus strategy +${"####"} Test sequences +All test sequences reside in `hw/top_${topname}/ip_autogen/ac_range_check/dv/env/seq_lib`. +The `ac_range_check_base_vseq` virtual sequence is extended from `cip_base_vseq` and serves as a starting point. +All test sequences are extended from `ac_range_check_base_vseq`. +It provides commonly used handles, variables, functions and tasks that the test sequences can simple use / call. +Some of the most commonly used tasks / functions are as follows: From `hw/top_${topname}/ip_autogen/ac_range_check/dv/env/seq/ac_range_check_base_vseq.sv`, +* task 1: +* task 2: + +${"####"} Functional coverage +To ensure high quality constrained random stimulus, it is necessary to develop a functional coverage model. +The following covergroups have been developed to prove that the test intent has been adequately met: +* cg1: +* cg2: + +${"###"} Self-checking strategy +${"####"} Scoreboard +It creates the following analysis ports to retrieve the data monitored by corresponding interface agents: +* analysis port1: +* analysis port2: + + +${"####"} Assertions +* TLUL assertions: The `hw/top_${topname}/ip_autogen/ac_range_check/dv/sva/ac_range_check_bind.sv` binds the `tlul_assert` [assertions](../../../../ip/tlul/doc/TlulProtocolChecker.md) to the IP to ensure TileLink interface protocol compliance. +* Unknown checks on DUT outputs: The RTL has assertions to ensure all outputs are initialized to known values after coming out of reset. +* assert prop 1: +* assert prop 2: + +${"##"} Building and running tests +We are using our in-house developed [regression tool](../../../../../util/dvsim/README.md) for building and running our tests and regressions. +Please take a look at the link for detailed information on the usage, capabilities, features and known issues. +Here's how to run a smoke test: +```console +$ cd $REPO_TOP +$ ./util/dvsim/dvsim.py hw/top_${topname}/ip_autogen/ac_range_check/dv/ac_range_check_sim_cfg.hjson -i ac_range_check_smoke +``` + +${"##"} Testplan +[Testplan](../data/ac_range_check_testplan.hjson) diff --git a/hw/ip_templates/ac_range_check/dv/ac_range_check_sim.core.tpl b/hw/ip_templates/ac_range_check/dv/ac_range_check_sim.core.tpl new file mode 100644 index 0000000000000..f8ffb019d8ad9 --- /dev/null +++ b/hw/ip_templates/ac_range_check/dv/ac_range_check_sim.core.tpl @@ -0,0 +1,31 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: ${instance_vlnv("lowrisc:dv:ac_range_check_sim:0.1")} +description: "AC_RANGE_CHECK DV sim target" +filesets: + files_rtl: + depend: + - lowrisc:ip:tlul + - ${instance_vlnv("lowrisc:ip:ac_range_check:0.1")} + file_type: systemVerilogSource + + files_dv: + depend: + - ${instance_vlnv("lowrisc:dv:ac_range_check_test")} + - ${instance_vlnv("lowrisc:dv:ac_range_check_sva")} + files: + - tb/tb.sv + file_type: systemVerilogSource + +targets: + sim: &sim_target + toplevel: tb + filesets: + - files_rtl + - files_dv + default_tool: vcs + + lint: + <<: *sim_target diff --git a/hw/ip_templates/ac_range_check/dv/ac_range_check_sim_cfg.hjson.tpl b/hw/ip_templates/ac_range_check/dv/ac_range_check_sim_cfg.hjson.tpl new file mode 100644 index 0000000000000..95af4f0d75677 --- /dev/null +++ b/hw/ip_templates/ac_range_check/dv/ac_range_check_sim_cfg.hjson.tpl @@ -0,0 +1,63 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ + // Name of the sim cfg - typically same as the name of the DUT. + name: ac_range_check + + // Top level dut name (sv module). + dut: ac_range_check + + // Top level testbench name (sv module). + tb: tb + + // Simulator used to sign off this block + tool: xcelium + + // Fusesoc core file used for building the file list. + fusesoc_core: ${instance_vlnv("lowrisc:dv:ac_range_check_sim:0.1")} + + // Testplan hjson file. + testplan: "{self_dir}/../data/ac_range_check_testplan.hjson" + + // Import additional common sim cfg files. + import_cfgs: [// Project wide common sim cfg file + "{proj_root}/hw/dv/tools/dvsim/common_sim_cfg.hjson", + // Common CIP test lists + "{proj_root}/hw/dv/tools/dvsim/tests/csr_tests.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/mem_tests.hjson", // TODO MVy needed? + "{proj_root}/hw/dv/tools/dvsim/tests/intr_test.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/alert_test.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/shadow_reg_errors_tests.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/tl_access_tests.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/sec_cm_tests.hjson", // TODO MVy needed? + "{proj_root}/hw/dv/tools/dvsim/tests/stress_tests.hjson"] + + // Add additional tops for simulation. + sim_tops: ["ac_range_check_bind"] + + // Default iterations for all tests - each test entry can override this. + reseed: 50 + + // Default UVM test and seq class name. + uvm_test: ac_range_check_base_test + uvm_test_seq: ac_range_check_base_vseq + + // List of test specifications. + tests: [ + { + name: ac_range_check_smoke + uvm_test_seq: ac_range_check_smoke_vseq + } + + // TODO: add more tests here + ] + + // List of regressions. + regressions: [ + { + name: smoke + tests: ["ac_range_check_smoke"] + } + ] +} diff --git a/hw/ip_templates/ac_range_check/dv/env/ac_range_check_env.core.tpl b/hw/ip_templates/ac_range_check/dv/env/ac_range_check_env.core.tpl new file mode 100644 index 0000000000000..8b7e0cf24f712 --- /dev/null +++ b/hw/ip_templates/ac_range_check/dv/env/ac_range_check_env.core.tpl @@ -0,0 +1,40 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: ${instance_vlnv("lowrisc:dv:ac_range_check_env:0.1")} +description: "AC_RANGE_CHECK DV UVM environment" +filesets: + files_dv: + depend: + - lowrisc:dv:ralgen + - lowrisc:dv:cip_lib + - lowrisc:dv:dv_base_reg + - lowrisc:dv:dv_lib + files: + - ac_range_check_env_pkg.sv + - ac_range_check_ral_pkg.sv + - ac_range_check_env_cfg.sv: {is_include_file: true} + - ac_range_check_env_cov.sv: {is_include_file: true} + - ac_range_check_virtual_sequencer.sv: {is_include_file: true} + - ac_range_check_scoreboard.sv: {is_include_file: true} + - ac_range_check_env.sv: {is_include_file: true} + - seq_lib/ac_range_check_vseq_list.sv: {is_include_file: true} + - seq_lib/ac_range_check_base_vseq.sv: {is_include_file: true} + - seq_lib/ac_range_check_common_vseq.sv: {is_include_file: true} + - seq_lib/ac_range_check_smoke_vseq.sv: {is_include_file: true} + file_type: systemVerilogSource + +generate: + ral: + generator: ralgen + parameters: + name: ac_range_check + ip_hjson: ../../data/ac_range_check.hjson + +targets: + default: + filesets: + - files_dv + generate: + - ral diff --git a/hw/ip_templates/ac_range_check/dv/env/ac_range_check_env.sv b/hw/ip_templates/ac_range_check/dv/env/ac_range_check_env.sv new file mode 100644 index 0000000000000..ab3fc70d125d2 --- /dev/null +++ b/hw/ip_templates/ac_range_check/dv/env/ac_range_check_env.sv @@ -0,0 +1,63 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class ac_range_check_env extends cip_base_env #( + .CFG_T (ac_range_check_env_cfg), + .COV_T (ac_range_check_env_cov), + .VIRTUAL_SEQUENCER_T(ac_range_check_virtual_sequencer), + .SCOREBOARD_T (ac_range_check_scoreboard) + ); + `uvm_component_utils(ac_range_check_env) + + tl_agent tl_csr_agt; + tl_agent tl_unfilt_agt; + tl_agent tl_filt_agt; + + // Standard SV/UVM methods + extern function new(string name="", uvm_component parent=null); + extern function void build_phase(uvm_phase phase); + extern function void connect_phase(uvm_phase phase); +endclass : ac_range_check_env + + +function ac_range_check_env::new(string name="", uvm_component parent=null); + super.new(name, parent); +endfunction : new + +function void ac_range_check_env::build_phase(uvm_phase phase); + super.build_phase(phase); + + // Create CSR TL agent + tl_csr_agt = tl_agent::type_id::create("tl_csr_agt", this); + uvm_config_db#(tl_agent_cfg)::set(this, "tl_csr_agt*", "cfg", cfg.tl_csr_agt_cfg); + cfg.tl_csr_agt_cfg.en_cov = cfg.en_cov; + + // Create Unfiltered TL agent + tl_unfilt_agt = tl_agent::type_id::create("tl_unfilt_agt", this); + uvm_config_db#(tl_agent_cfg)::set(this, "tl_unfilt_agt*", "cfg", cfg.tl_unfilt_agt_cfg); + cfg.tl_unfilt_agt_cfg.en_cov = cfg.en_cov; + + // Create Fltered TL agent + tl_filt_agt = tl_agent::type_id::create("tl_filt_agt", this); + uvm_config_db#(tl_agent_cfg)::set(this, "tl_filt_agt*", "cfg", cfg.tl_filt_agt_cfg); + cfg.tl_filt_agt_cfg.en_cov = cfg.en_cov; +endfunction : build_phase + +function void ac_range_check_env::connect_phase(uvm_phase phase); + super.connect_phase(phase); + if (cfg.en_scb) begin + tl_csr_agt.monitor.analysis_port.connect(scoreboard.tl_csr_fifo.analysis_export); + tl_unfilt_agt.monitor.analysis_port.connect(scoreboard.tl_unfilt_fifo.analysis_export); + tl_filt_agt.monitor.analysis_port.connect(scoreboard.tl_filt_fifo.analysis_export); + end + if (cfg.is_active && cfg.tl_csr_agt_cfg.is_active) begin + virtual_sequencer.tl_csr_sqr = tl_csr_agt.sequencer; + end + if (cfg.is_active && cfg.tl_unfilt_agt_cfg.is_active) begin + virtual_sequencer.tl_unfilt_sqr = tl_unfilt_agt.sequencer; + end + if (cfg.is_active && cfg.tl_filt_agt_cfg.is_active) begin + virtual_sequencer.tl_filt_sqr = tl_filt_agt.sequencer; + end +endfunction : connect_phase diff --git a/hw/ip_templates/ac_range_check/dv/env/ac_range_check_env_cfg.sv b/hw/ip_templates/ac_range_check/dv/env/ac_range_check_env_cfg.sv new file mode 100644 index 0000000000000..b4e1f6a6872bb --- /dev/null +++ b/hw/ip_templates/ac_range_check/dv/env/ac_range_check_env_cfg.sv @@ -0,0 +1,47 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class ac_range_check_env_cfg extends cip_base_env_cfg #(.RAL_T(ac_range_check_reg_block)); + + // External component config objects + rand tl_agent_cfg tl_csr_agt_cfg; + rand tl_agent_cfg tl_unfilt_agt_cfg; + rand tl_agent_cfg tl_filt_agt_cfg; + + `uvm_object_utils_begin(ac_range_check_env_cfg) + `uvm_field_object(tl_csr_agt_cfg, UVM_DEFAULT) + `uvm_field_object(tl_unfilt_agt_cfg, UVM_DEFAULT) + `uvm_field_object(tl_filt_agt_cfg, UVM_DEFAULT) + `uvm_object_utils_end + + // Standard SV/UVM methods + extern function new(string name=""); + + // Class specific methods + extern function void initialize(bit [31:0] csr_base_addr = '1); +endclass : ac_range_check_env_cfg + + +function ac_range_check_env_cfg::new(string name=""); + super.new(name); +endfunction : new + +function void ac_range_check_env_cfg::initialize(bit [31:0] csr_base_addr = '1); + list_of_alerts = ac_range_check_env_pkg::LIST_OF_ALERTS; + super.initialize(csr_base_addr); + // Create tl_csr agent config obj + tl_csr_agt_cfg = tl_agent_cfg::type_id::create("tl_csr_agt_cfg"); + // Create tl_unfilt agent config obj + tl_unfilt_agt_cfg = tl_agent_cfg::type_id::create("tl_unfilt_agt_cfg"); + // Create tl_filt agent config obj + tl_filt_agt_cfg = tl_agent_cfg::type_id::create("tl_filt_agt_cfg"); + + // Set num_interrupts + begin + uvm_reg rg = ral.get_reg_by_name("intr_state"); + if (rg != null) begin + num_interrupts = ral.intr_state.get_n_used_bits(); + end + end +endfunction : initialize diff --git a/hw/ip_templates/ac_range_check/dv/env/ac_range_check_env_cov.sv b/hw/ip_templates/ac_range_check/dv/env/ac_range_check_env_cov.sv new file mode 100644 index 0000000000000..c5068f7a7da75 --- /dev/null +++ b/hw/ip_templates/ac_range_check/dv/env/ac_range_check_env_cov.sv @@ -0,0 +1,36 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +/** + * Covergoups that are dependent on run-time parameters that may be available + * only in build_phase can be defined here + * Covergroups may also be wrapped inside helper classes if needed. + */ + +class ac_range_check_env_cov extends cip_base_env_cov #(.CFG_T(ac_range_check_env_cfg)); + `uvm_component_utils(ac_range_check_env_cov) + + // The base class provides the following handles for use: + // ac_range_check_env_cfg: cfg + + // Covergroups + // TODO MVy [add covergroups here] + + // Standard SV/UVM methods + extern function new(string name, uvm_component parent); + extern function void build_phase(uvm_phase phase); +endclass : ac_range_check_env_cov + + +function ac_range_check_env_cov::new(string name, uvm_component parent); + super.new(name, parent); + // TODO MVy [instantiate covergroups here] +endfunction : new + +function void ac_range_check_env_cov::build_phase(uvm_phase phase); + super.build_phase(phase); + // TODO MVy [or instantiate covergroups here] + // Please instantiate sticky_intr_cov array of objects for all interrupts that are sticky + // See cip_base_env_cov for details +endfunction : build_phase diff --git a/hw/ip_templates/ac_range_check/dv/env/ac_range_check_env_pkg.sv b/hw/ip_templates/ac_range_check/dv/env/ac_range_check_env_pkg.sv new file mode 100644 index 0000000000000..ce22c57c0ff38 --- /dev/null +++ b/hw/ip_templates/ac_range_check/dv/env/ac_range_check_env_pkg.sv @@ -0,0 +1,40 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +package ac_range_check_env_pkg; + // Dep packages + import uvm_pkg::*; + import top_pkg::*; + import dv_utils_pkg::*; + import tl_agent_pkg::*; + import dv_lib_pkg::*; + import cip_base_pkg::*; + import dv_base_reg_pkg::*; + import csr_utils_pkg::*; + import ac_range_check_ral_pkg::*; + + // Macro includes + `include "uvm_macros.svh" + `include "dv_macros.svh" + + // Parameters + // TODO MVy check order is correct + parameter uint NUM_ALERTS = 2; + parameter string LIST_OF_ALERTS[] = {"recov_ctrl_update_err", "fatal_fault"}; + + // Types + typedef enum int { + DenyCntReached = 0 + } ac_range_check_intr_e; + + // Functions + + // Package sources + `include "ac_range_check_env_cfg.sv" + `include "ac_range_check_env_cov.sv" + `include "ac_range_check_virtual_sequencer.sv" + `include "ac_range_check_scoreboard.sv" + `include "ac_range_check_env.sv" + `include "ac_range_check_vseq_list.sv" +endpackage : ac_range_check_env_pkg diff --git a/hw/ip_templates/ac_range_check/dv/env/ac_range_check_ral_pkg.sv b/hw/ip_templates/ac_range_check/dv/env/ac_range_check_ral_pkg.sv new file mode 100644 index 0000000000000..96836c25e8e43 --- /dev/null +++ b/hw/ip_templates/ac_range_check/dv/env/ac_range_check_ral_pkg.sv @@ -0,0 +1,3595 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// UVM Registers auto-generated by `reggen` containing data structure +package ac_range_check_ral_pkg; + // dep packages + import uvm_pkg::*; + import dv_base_reg_pkg::*; + + // macro includes + `include "uvm_macros.svh" + + // Forward declare all register/memory/block classes + typedef class ac_range_check_reg_intr_state; + typedef class ac_range_check_reg_intr_enable; + typedef class ac_range_check_reg_intr_test; + typedef class ac_range_check_reg_alert_test; + typedef class ac_range_check_reg_log_config; + typedef class ac_range_check_reg_log_status; + typedef class ac_range_check_reg_log_address; + typedef class ac_range_check_reg_range_regwen; + typedef class ac_range_check_reg_range_base; + typedef class ac_range_check_reg_range_limit; + typedef class ac_range_check_reg_range_perm; + typedef class ac_range_check_reg_range_racl_policy_shadowed; + typedef class ac_range_check_reg_block; + + class ac_range_check_reg_intr_state extends dv_base_reg; + // fields + rand dv_base_reg_field deny_cnt_reached; + + `uvm_object_utils(ac_range_check_reg_intr_state) + + function new(string name = "ac_range_check_reg_intr_state", + int unsigned n_bits = 32, + int has_coverage = UVM_NO_COVERAGE); + super.new(name, n_bits, has_coverage); + endfunction : new + + virtual function void build(csr_excl_item csr_excl = null); + deny_cnt_reached = + (dv_base_reg_field:: + type_id::create("deny_cnt_reached")); + deny_cnt_reached.configure( + .parent(this), + .size(1), + .lsb_pos(0), + .access("W1C"), + .mubi_access("NONE"), + .volatile(1), + .reset(32'h0), + .has_reset(1), + .is_rand(1), + .individually_accessible(1)); + + deny_cnt_reached.set_original_access("W1C"); + endfunction : build + endclass : ac_range_check_reg_intr_state + + class ac_range_check_reg_intr_enable extends dv_base_reg; + // fields + rand dv_base_reg_field deny_cnt_reached; + + `uvm_object_utils(ac_range_check_reg_intr_enable) + + function new(string name = "ac_range_check_reg_intr_enable", + int unsigned n_bits = 32, + int has_coverage = UVM_NO_COVERAGE); + super.new(name, n_bits, has_coverage); + endfunction : new + + virtual function void build(csr_excl_item csr_excl = null); + deny_cnt_reached = + (dv_base_reg_field:: + type_id::create("deny_cnt_reached")); + deny_cnt_reached.configure( + .parent(this), + .size(1), + .lsb_pos(0), + .access("RW"), + .mubi_access("NONE"), + .volatile(0), + .reset(32'h0), + .has_reset(1), + .is_rand(1), + .individually_accessible(1)); + + deny_cnt_reached.set_original_access("RW"); + endfunction : build + endclass : ac_range_check_reg_intr_enable + + class ac_range_check_reg_intr_test extends dv_base_reg; + // fields + rand dv_base_reg_field deny_cnt_reached; + + `uvm_object_utils(ac_range_check_reg_intr_test) + + function new(string name = "ac_range_check_reg_intr_test", + int unsigned n_bits = 32, + int has_coverage = UVM_NO_COVERAGE); + super.new(name, n_bits, has_coverage); + endfunction : new + + virtual function void build(csr_excl_item csr_excl = null); + deny_cnt_reached = + (dv_base_reg_field:: + type_id::create("deny_cnt_reached")); + deny_cnt_reached.configure( + .parent(this), + .size(1), + .lsb_pos(0), + .access("WO"), + .mubi_access("NONE"), + .volatile(0), + .reset(32'h0), + .has_reset(1), + .is_rand(1), + .individually_accessible(1)); + + deny_cnt_reached.set_original_access("WO"); + set_is_ext_reg(1); + endfunction : build + endclass : ac_range_check_reg_intr_test + + class ac_range_check_reg_alert_test extends dv_base_reg; + // fields + rand dv_base_reg_field recov_ctrl_update_err; + rand dv_base_reg_field fatal_fault; + + `uvm_object_utils(ac_range_check_reg_alert_test) + + function new(string name = "ac_range_check_reg_alert_test", + int unsigned n_bits = 32, + int has_coverage = UVM_NO_COVERAGE); + super.new(name, n_bits, has_coverage); + endfunction : new + + virtual function void build(csr_excl_item csr_excl = null); + recov_ctrl_update_err = + (dv_base_reg_field:: + type_id::create("recov_ctrl_update_err")); + recov_ctrl_update_err.configure( + .parent(this), + .size(1), + .lsb_pos(0), + .access("WO"), + .mubi_access("NONE"), + .volatile(0), + .reset(32'h0), + .has_reset(1), + .is_rand(1), + .individually_accessible(1)); + + recov_ctrl_update_err.set_original_access("WO"); + fatal_fault = + (dv_base_reg_field:: + type_id::create("fatal_fault")); + fatal_fault.configure( + .parent(this), + .size(1), + .lsb_pos(1), + .access("WO"), + .mubi_access("NONE"), + .volatile(0), + .reset(32'h0), + .has_reset(1), + .is_rand(1), + .individually_accessible(1)); + + fatal_fault.set_original_access("WO"); + set_is_ext_reg(1); + endfunction : build + endclass : ac_range_check_reg_alert_test + + class ac_range_check_reg_log_config extends dv_base_reg; + // fields + rand dv_base_reg_field log_enable; + rand dv_base_reg_field log_clear; + rand dv_base_reg_field deny_cnt_threshold; + + `uvm_object_utils(ac_range_check_reg_log_config) + + function new(string name = "ac_range_check_reg_log_config", + int unsigned n_bits = 32, + int has_coverage = UVM_NO_COVERAGE); + super.new(name, n_bits, has_coverage); + endfunction : new + + virtual function void build(csr_excl_item csr_excl = null); + log_enable = + (dv_base_reg_field:: + type_id::create("log_enable")); + log_enable.configure( + .parent(this), + .size(1), + .lsb_pos(0), + .access("RW"), + .mubi_access("NONE"), + .volatile(0), + .reset(32'h0), + .has_reset(1), + .is_rand(1), + .individually_accessible(1)); + + log_enable.set_original_access("RW"); + log_clear = + (dv_base_reg_field:: + type_id::create("log_clear")); + log_clear.configure( + .parent(this), + .size(1), + .lsb_pos(1), + .access("RW"), + .mubi_access("NONE"), + .volatile(0), + .reset(32'h0), + .has_reset(1), + .is_rand(1), + .individually_accessible(1)); + + log_clear.set_original_access("RW"); + deny_cnt_threshold = + (dv_base_reg_field:: + type_id::create("deny_cnt_threshold")); + deny_cnt_threshold.configure( + .parent(this), + .size(8), + .lsb_pos(2), + .access("RW"), + .mubi_access("NONE"), + .volatile(0), + .reset(32'h0), + .has_reset(1), + .is_rand(1), + .individually_accessible(1)); + + deny_cnt_threshold.set_original_access("RW"); + endfunction : build + endclass : ac_range_check_reg_log_config + + class ac_range_check_reg_log_status extends dv_base_reg; + // fields + rand dv_base_reg_field deny_cnt; + rand dv_base_reg_field denied_read_access; + rand dv_base_reg_field denied_write_access; + rand dv_base_reg_field denied_execute_access; + rand dv_base_reg_field denied_no_match; + rand dv_base_reg_field denied_racl_read; + rand dv_base_reg_field denied_racl_write; + rand dv_base_reg_field denied_source_role; + rand dv_base_reg_field denied_ctn_uid; + rand dv_base_reg_field deny_range_index; + + `uvm_object_utils(ac_range_check_reg_log_status) + + function new(string name = "ac_range_check_reg_log_status", + int unsigned n_bits = 32, + int has_coverage = UVM_NO_COVERAGE); + super.new(name, n_bits, has_coverage); + endfunction : new + + virtual function void build(csr_excl_item csr_excl = null); + deny_cnt = + (dv_base_reg_field:: + type_id::create("deny_cnt")); + deny_cnt.configure( + .parent(this), + .size(8), + .lsb_pos(0), + .access("RO"), + .mubi_access("NONE"), + .volatile(1), + .reset(32'h0), + .has_reset(1), + .is_rand(1), + .individually_accessible(1)); + + deny_cnt.set_original_access("RO"); + denied_read_access = + (dv_base_reg_field:: + type_id::create("denied_read_access")); + denied_read_access.configure( + .parent(this), + .size(1), + .lsb_pos(8), + .access("RO"), + .mubi_access("NONE"), + .volatile(1), + .reset(32'h0), + .has_reset(1), + .is_rand(1), + .individually_accessible(1)); + + denied_read_access.set_original_access("RO"); + denied_write_access = + (dv_base_reg_field:: + type_id::create("denied_write_access")); + denied_write_access.configure( + .parent(this), + .size(1), + .lsb_pos(9), + .access("RO"), + .mubi_access("NONE"), + .volatile(1), + .reset(32'h0), + .has_reset(1), + .is_rand(1), + .individually_accessible(1)); + + denied_write_access.set_original_access("RO"); + denied_execute_access = + (dv_base_reg_field:: + type_id::create("denied_execute_access")); + denied_execute_access.configure( + .parent(this), + .size(1), + .lsb_pos(10), + .access("RO"), + .mubi_access("NONE"), + .volatile(1), + .reset(32'h0), + .has_reset(1), + .is_rand(1), + .individually_accessible(1)); + + denied_execute_access.set_original_access("RO"); + denied_no_match = + (dv_base_reg_field:: + type_id::create("denied_no_match")); + denied_no_match.configure( + .parent(this), + .size(1), + .lsb_pos(11), + .access("RO"), + .mubi_access("NONE"), + .volatile(1), + .reset(32'h0), + .has_reset(1), + .is_rand(1), + .individually_accessible(1)); + + denied_no_match.set_original_access("RO"); + denied_racl_read = + (dv_base_reg_field:: + type_id::create("denied_racl_read")); + denied_racl_read.configure( + .parent(this), + .size(1), + .lsb_pos(12), + .access("RO"), + .mubi_access("NONE"), + .volatile(1), + .reset(32'h0), + .has_reset(1), + .is_rand(1), + .individually_accessible(1)); + + denied_racl_read.set_original_access("RO"); + denied_racl_write = + (dv_base_reg_field:: + type_id::create("denied_racl_write")); + denied_racl_write.configure( + .parent(this), + .size(1), + .lsb_pos(13), + .access("RO"), + .mubi_access("NONE"), + .volatile(1), + .reset(32'h0), + .has_reset(1), + .is_rand(1), + .individually_accessible(1)); + + denied_racl_write.set_original_access("RO"); + denied_source_role = + (dv_base_reg_field:: + type_id::create("denied_source_role")); + denied_source_role.configure( + .parent(this), + .size(4), + .lsb_pos(14), + .access("RO"), + .mubi_access("NONE"), + .volatile(1), + .reset(32'h0), + .has_reset(1), + .is_rand(1), + .individually_accessible(1)); + + denied_source_role.set_original_access("RO"); + denied_ctn_uid = + (dv_base_reg_field:: + type_id::create("denied_ctn_uid")); + denied_ctn_uid.configure( + .parent(this), + .size(5), + .lsb_pos(18), + .access("RO"), + .mubi_access("NONE"), + .volatile(1), + .reset(32'h0), + .has_reset(1), + .is_rand(1), + .individually_accessible(1)); + + denied_ctn_uid.set_original_access("RO"); + deny_range_index = + (dv_base_reg_field:: + type_id::create("deny_range_index")); + deny_range_index.configure( + .parent(this), + .size(5), + .lsb_pos(23), + .access("RO"), + .mubi_access("NONE"), + .volatile(1), + .reset(32'h0), + .has_reset(1), + .is_rand(1), + .individually_accessible(1)); + + deny_range_index.set_original_access("RO"); + endfunction : build + endclass : ac_range_check_reg_log_status + + class ac_range_check_reg_log_address extends dv_base_reg; + // fields + rand dv_base_reg_field log_address; + + `uvm_object_utils(ac_range_check_reg_log_address) + + function new(string name = "ac_range_check_reg_log_address", + int unsigned n_bits = 32, + int has_coverage = UVM_NO_COVERAGE); + super.new(name, n_bits, has_coverage); + endfunction : new + + virtual function void build(csr_excl_item csr_excl = null); + log_address = + (dv_base_reg_field:: + type_id::create("log_address")); + log_address.configure( + .parent(this), + .size(32), + .lsb_pos(0), + .access("RO"), + .mubi_access("NONE"), + .volatile(1), + .reset(32'h0), + .has_reset(1), + .is_rand(1), + .individually_accessible(1)); + + log_address.set_original_access("RO"); + endfunction : build + endclass : ac_range_check_reg_log_address + + class ac_range_check_reg_range_regwen extends dv_base_reg; + // fields + rand dv_base_reg_field regwen; + + `uvm_object_utils(ac_range_check_reg_range_regwen) + + function new(string name = "ac_range_check_reg_range_regwen", + int unsigned n_bits = 32, + int has_coverage = UVM_NO_COVERAGE); + super.new(name, n_bits, has_coverage); + endfunction : new + + virtual function void build(csr_excl_item csr_excl = null); + regwen = + (dv_base_reg_field:: + type_id::create("regwen")); + regwen.configure( + .parent(this), + .size(4), + .lsb_pos(0), + .access("RW"), + .mubi_access("W0C"), + .volatile(0), + .reset(32'h6), + .has_reset(1), + .is_rand(1), + .individually_accessible(1)); + + regwen.set_original_access("RW"); + regwen.set_mubi_width(4); + endfunction : build + endclass : ac_range_check_reg_range_regwen + + class ac_range_check_reg_range_base extends dv_base_reg; + // fields + rand dv_base_reg_field base; + + `uvm_object_utils(ac_range_check_reg_range_base) + + function new(string name = "ac_range_check_reg_range_base", + int unsigned n_bits = 32, + int has_coverage = UVM_NO_COVERAGE); + super.new(name, n_bits, has_coverage); + endfunction : new + + virtual function void build(csr_excl_item csr_excl = null); + base = + (dv_base_reg_field:: + type_id::create("base")); + base.configure( + .parent(this), + .size(30), + .lsb_pos(2), + .access("RW"), + .mubi_access("NONE"), + .volatile(0), + .reset(32'h0), + .has_reset(1), + .is_rand(1), + .individually_accessible(1)); + + base.set_original_access("RW"); + endfunction : build + endclass : ac_range_check_reg_range_base + + class ac_range_check_reg_range_limit extends dv_base_reg; + // fields + rand dv_base_reg_field limit; + + `uvm_object_utils(ac_range_check_reg_range_limit) + + function new(string name = "ac_range_check_reg_range_limit", + int unsigned n_bits = 32, + int has_coverage = UVM_NO_COVERAGE); + super.new(name, n_bits, has_coverage); + endfunction : new + + virtual function void build(csr_excl_item csr_excl = null); + limit = + (dv_base_reg_field:: + type_id::create("limit")); + limit.configure( + .parent(this), + .size(30), + .lsb_pos(2), + .access("RW"), + .mubi_access("NONE"), + .volatile(0), + .reset(32'h0), + .has_reset(1), + .is_rand(1), + .individually_accessible(1)); + + limit.set_original_access("RW"); + endfunction : build + endclass : ac_range_check_reg_range_limit + + class ac_range_check_reg_range_perm extends dv_base_reg; + // fields + rand dv_base_reg_field enable; + rand dv_base_reg_field read_access; + rand dv_base_reg_field write_access; + rand dv_base_reg_field execute_access; + rand dv_base_reg_field log_denied_access; + + `uvm_object_utils(ac_range_check_reg_range_perm) + + function new(string name = "ac_range_check_reg_range_perm", + int unsigned n_bits = 32, + int has_coverage = UVM_NO_COVERAGE); + super.new(name, n_bits, has_coverage); + endfunction : new + + virtual function void build(csr_excl_item csr_excl = null); + enable = + (dv_base_reg_field:: + type_id::create("enable")); + enable.configure( + .parent(this), + .size(4), + .lsb_pos(0), + .access("RW"), + .mubi_access("RW"), + .volatile(0), + .reset(32'h9), + .has_reset(1), + .is_rand(1), + .individually_accessible(1)); + + enable.set_original_access("RW"); + enable.set_mubi_width(4); + read_access = + (dv_base_reg_field:: + type_id::create("read_access")); + read_access.configure( + .parent(this), + .size(4), + .lsb_pos(4), + .access("RW"), + .mubi_access("RW"), + .volatile(0), + .reset(32'h9), + .has_reset(1), + .is_rand(1), + .individually_accessible(1)); + + read_access.set_original_access("RW"); + read_access.set_mubi_width(4); + write_access = + (dv_base_reg_field:: + type_id::create("write_access")); + write_access.configure( + .parent(this), + .size(4), + .lsb_pos(8), + .access("RW"), + .mubi_access("RW"), + .volatile(0), + .reset(32'h9), + .has_reset(1), + .is_rand(1), + .individually_accessible(1)); + + write_access.set_original_access("RW"); + write_access.set_mubi_width(4); + execute_access = + (dv_base_reg_field:: + type_id::create("execute_access")); + execute_access.configure( + .parent(this), + .size(4), + .lsb_pos(12), + .access("RW"), + .mubi_access("RW"), + .volatile(0), + .reset(32'h9), + .has_reset(1), + .is_rand(1), + .individually_accessible(1)); + + execute_access.set_original_access("RW"); + execute_access.set_mubi_width(4); + log_denied_access = + (dv_base_reg_field:: + type_id::create("log_denied_access")); + log_denied_access.configure( + .parent(this), + .size(4), + .lsb_pos(16), + .access("RW"), + .mubi_access("RW"), + .volatile(0), + .reset(32'h6), + .has_reset(1), + .is_rand(1), + .individually_accessible(1)); + + log_denied_access.set_original_access("RW"); + log_denied_access.set_mubi_width(4); + endfunction : build + endclass : ac_range_check_reg_range_perm + + class ac_range_check_reg_range_racl_policy_shadowed extends dv_base_reg; + // fields + rand dv_base_reg_field read_perm; + rand dv_base_reg_field write_perm; + + `uvm_object_utils(ac_range_check_reg_range_racl_policy_shadowed) + + function new(string name = "ac_range_check_reg_range_racl_policy_shadowed", + int unsigned n_bits = 32, + int has_coverage = UVM_NO_COVERAGE); + super.new(name, n_bits, has_coverage); + endfunction : new + + virtual function void build(csr_excl_item csr_excl = null); + read_perm = + (dv_base_reg_field:: + type_id::create("read_perm")); + read_perm.configure( + .parent(this), + .size(16), + .lsb_pos(0), + .access("RW"), + .mubi_access("NONE"), + .volatile(0), + .reset(32'h0), + .has_reset(1), + .is_rand(1), + .individually_accessible(1)); + + read_perm.set_original_access("RW"); + write_perm = + (dv_base_reg_field:: + type_id::create("write_perm")); + write_perm.configure( + .parent(this), + .size(16), + .lsb_pos(16), + .access("RW"), + .mubi_access("NONE"), + .volatile(0), + .reset(32'h0), + .has_reset(1), + .is_rand(1), + .individually_accessible(1)); + + write_perm.set_original_access("RW"); + endfunction : build + endclass : ac_range_check_reg_range_racl_policy_shadowed + + class ac_range_check_reg_block extends dv_base_reg_block; + // registers + rand ac_range_check_reg_intr_state intr_state; + rand ac_range_check_reg_intr_enable intr_enable; + rand ac_range_check_reg_intr_test intr_test; + rand ac_range_check_reg_alert_test alert_test; + rand ac_range_check_reg_log_config log_config; + rand ac_range_check_reg_log_status log_status; + rand ac_range_check_reg_log_address log_address; + rand ac_range_check_reg_range_regwen range_regwen[32]; + rand ac_range_check_reg_range_base range_base[32]; + rand ac_range_check_reg_range_limit range_limit[32]; + rand ac_range_check_reg_range_perm range_perm[32]; + rand ac_range_check_reg_range_racl_policy_shadowed range_racl_policy_shadowed[32]; + + `uvm_object_utils(ac_range_check_reg_block) + + function new(string name = "ac_range_check_reg_block", + int has_coverage = UVM_NO_COVERAGE); + super.new(name, has_coverage); + endfunction : new + + virtual function void build(uvm_reg_addr_t base_addr, + csr_excl_item csr_excl = null); + // create default map + this.default_map = create_map(.name("default_map"), + .base_addr(base_addr), + .n_bytes(4), + .endian(UVM_LITTLE_ENDIAN)); + if (csr_excl == null) begin + csr_excl = csr_excl_item::type_id::create("csr_excl"); + this.csr_excl = csr_excl; + end + set_hdl_path_root("tb.dut", "BkdrRegPathRtl"); + set_hdl_path_root("tb.dut", "BkdrRegPathRtlShadow"); + // create registers + intr_state = + (ac_range_check_reg_intr_state:: + type_id::create("intr_state")); + intr_state.configure(.blk_parent(this)); + intr_state.build(csr_excl); + default_map.add_reg(.rg(intr_state), + .offset(32'h0)); + intr_state.add_hdl_path_slice( + "u_ac_range_check_reg.u_intr_state.q", + 0, 1, 0, "BkdrRegPathRtl"); + + // create register tags + csr_excl.add_excl(intr_state.get_full_name(), + CsrExclAll, CsrAllTests); + intr_enable = + (ac_range_check_reg_intr_enable:: + type_id::create("intr_enable")); + intr_enable.configure(.blk_parent(this)); + intr_enable.build(csr_excl); + default_map.add_reg(.rg(intr_enable), + .offset(32'h4)); + intr_enable.add_hdl_path_slice( + "u_ac_range_check_reg.u_intr_enable.q", + 0, 1, 0, "BkdrRegPathRtl"); + + intr_test = + (ac_range_check_reg_intr_test:: + type_id::create("intr_test")); + intr_test.configure(.blk_parent(this)); + intr_test.build(csr_excl); + default_map.add_reg(.rg(intr_test), + .offset(32'h8)); + intr_test.add_hdl_path_slice( + "u_ac_range_check_reg.u_intr_test.qs", + 0, 1, 0, "BkdrRegPathRtl"); + + // create register tags + csr_excl.add_excl(intr_test.get_full_name(), + CsrExclWrite, CsrNonInitTests); + alert_test = + (ac_range_check_reg_alert_test:: + type_id::create("alert_test")); + alert_test.configure(.blk_parent(this)); + alert_test.build(csr_excl); + default_map.add_reg(.rg(alert_test), + .offset(32'hc)); + alert_test.add_hdl_path_slice( + "u_ac_range_check_reg.u_alert_test_recov_ctrl_update_err.qs", + 0, 1, 0, "BkdrRegPathRtl"); + alert_test.add_hdl_path_slice( + "u_ac_range_check_reg.u_alert_test_fatal_fault.qs", + 1, 1, 0, "BkdrRegPathRtl"); + + log_config = + (ac_range_check_reg_log_config:: + type_id::create("log_config")); + log_config.configure(.blk_parent(this)); + log_config.build(csr_excl); + default_map.add_reg(.rg(log_config), + .offset(32'h10)); + log_config.add_hdl_path_slice( + "u_ac_range_check_reg.u_log_config_log_enable.q", + 0, 1, 0, "BkdrRegPathRtl"); + log_config.add_hdl_path_slice( + "u_ac_range_check_reg.u_log_config_log_clear.q", + 1, 1, 0, "BkdrRegPathRtl"); + log_config.add_hdl_path_slice( + "u_ac_range_check_reg.u_log_config_deny_cnt_threshold.q", + 2, 8, 0, "BkdrRegPathRtl"); + + log_status = + (ac_range_check_reg_log_status:: + type_id::create("log_status")); + log_status.configure(.blk_parent(this)); + log_status.build(csr_excl); + default_map.add_reg(.rg(log_status), + .offset(32'h14)); + log_status.add_hdl_path_slice( + "u_ac_range_check_reg.u_log_status_deny_cnt.q", + 0, 8, 0, "BkdrRegPathRtl"); + log_status.add_hdl_path_slice( + "u_ac_range_check_reg.u_log_status_denied_read_access.q", + 8, 1, 0, "BkdrRegPathRtl"); + log_status.add_hdl_path_slice( + "u_ac_range_check_reg.u_log_status_denied_write_access.q", + 9, 1, 0, "BkdrRegPathRtl"); + log_status.add_hdl_path_slice( + "u_ac_range_check_reg.u_log_status_denied_execute_access.q", + 10, 1, 0, "BkdrRegPathRtl"); + log_status.add_hdl_path_slice( + "u_ac_range_check_reg.u_log_status_denied_no_match.q", + 11, 1, 0, "BkdrRegPathRtl"); + log_status.add_hdl_path_slice( + "u_ac_range_check_reg.u_log_status_denied_racl_read.q", + 12, 1, 0, "BkdrRegPathRtl"); + log_status.add_hdl_path_slice( + "u_ac_range_check_reg.u_log_status_denied_racl_write.q", + 13, 1, 0, "BkdrRegPathRtl"); + log_status.add_hdl_path_slice( + "u_ac_range_check_reg.u_log_status_denied_source_role.q", + 14, 4, 0, "BkdrRegPathRtl"); + log_status.add_hdl_path_slice( + "u_ac_range_check_reg.u_log_status_denied_ctn_uid.q", + 18, 5, 0, "BkdrRegPathRtl"); + log_status.add_hdl_path_slice( + "u_ac_range_check_reg.u_log_status_deny_range_index.q", + 23, 5, 0, "BkdrRegPathRtl"); + + log_address = + (ac_range_check_reg_log_address:: + type_id::create("log_address")); + log_address.configure(.blk_parent(this)); + log_address.build(csr_excl); + default_map.add_reg(.rg(log_address), + .offset(32'h18)); + log_address.add_hdl_path_slice( + "u_ac_range_check_reg.u_log_address.q", + 0, 32, 0, "BkdrRegPathRtl"); + + range_regwen[0] = + (ac_range_check_reg_range_regwen:: + type_id::create("range_regwen_0")); + range_regwen[0].configure(.blk_parent(this)); + range_regwen[0].build(csr_excl); + default_map.add_reg(.rg(range_regwen[0]), + .offset(32'h1c)); + range_regwen[0].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_regwen_0.q", + 0, 4, 0, "BkdrRegPathRtl"); + + range_regwen[1] = + (ac_range_check_reg_range_regwen:: + type_id::create("range_regwen_1")); + range_regwen[1].configure(.blk_parent(this)); + range_regwen[1].build(csr_excl); + default_map.add_reg(.rg(range_regwen[1]), + .offset(32'h20)); + range_regwen[1].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_regwen_1.q", + 0, 4, 0, "BkdrRegPathRtl"); + + range_regwen[2] = + (ac_range_check_reg_range_regwen:: + type_id::create("range_regwen_2")); + range_regwen[2].configure(.blk_parent(this)); + range_regwen[2].build(csr_excl); + default_map.add_reg(.rg(range_regwen[2]), + .offset(32'h24)); + range_regwen[2].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_regwen_2.q", + 0, 4, 0, "BkdrRegPathRtl"); + + range_regwen[3] = + (ac_range_check_reg_range_regwen:: + type_id::create("range_regwen_3")); + range_regwen[3].configure(.blk_parent(this)); + range_regwen[3].build(csr_excl); + default_map.add_reg(.rg(range_regwen[3]), + .offset(32'h28)); + range_regwen[3].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_regwen_3.q", + 0, 4, 0, "BkdrRegPathRtl"); + + range_regwen[4] = + (ac_range_check_reg_range_regwen:: + type_id::create("range_regwen_4")); + range_regwen[4].configure(.blk_parent(this)); + range_regwen[4].build(csr_excl); + default_map.add_reg(.rg(range_regwen[4]), + .offset(32'h2c)); + range_regwen[4].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_regwen_4.q", + 0, 4, 0, "BkdrRegPathRtl"); + + range_regwen[5] = + (ac_range_check_reg_range_regwen:: + type_id::create("range_regwen_5")); + range_regwen[5].configure(.blk_parent(this)); + range_regwen[5].build(csr_excl); + default_map.add_reg(.rg(range_regwen[5]), + .offset(32'h30)); + range_regwen[5].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_regwen_5.q", + 0, 4, 0, "BkdrRegPathRtl"); + + range_regwen[6] = + (ac_range_check_reg_range_regwen:: + type_id::create("range_regwen_6")); + range_regwen[6].configure(.blk_parent(this)); + range_regwen[6].build(csr_excl); + default_map.add_reg(.rg(range_regwen[6]), + .offset(32'h34)); + range_regwen[6].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_regwen_6.q", + 0, 4, 0, "BkdrRegPathRtl"); + + range_regwen[7] = + (ac_range_check_reg_range_regwen:: + type_id::create("range_regwen_7")); + range_regwen[7].configure(.blk_parent(this)); + range_regwen[7].build(csr_excl); + default_map.add_reg(.rg(range_regwen[7]), + .offset(32'h38)); + range_regwen[7].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_regwen_7.q", + 0, 4, 0, "BkdrRegPathRtl"); + + range_regwen[8] = + (ac_range_check_reg_range_regwen:: + type_id::create("range_regwen_8")); + range_regwen[8].configure(.blk_parent(this)); + range_regwen[8].build(csr_excl); + default_map.add_reg(.rg(range_regwen[8]), + .offset(32'h3c)); + range_regwen[8].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_regwen_8.q", + 0, 4, 0, "BkdrRegPathRtl"); + + range_regwen[9] = + (ac_range_check_reg_range_regwen:: + type_id::create("range_regwen_9")); + range_regwen[9].configure(.blk_parent(this)); + range_regwen[9].build(csr_excl); + default_map.add_reg(.rg(range_regwen[9]), + .offset(32'h40)); + range_regwen[9].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_regwen_9.q", + 0, 4, 0, "BkdrRegPathRtl"); + + range_regwen[10] = + (ac_range_check_reg_range_regwen:: + type_id::create("range_regwen_10")); + range_regwen[10].configure(.blk_parent(this)); + range_regwen[10].build(csr_excl); + default_map.add_reg(.rg(range_regwen[10]), + .offset(32'h44)); + range_regwen[10].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_regwen_10.q", + 0, 4, 0, "BkdrRegPathRtl"); + + range_regwen[11] = + (ac_range_check_reg_range_regwen:: + type_id::create("range_regwen_11")); + range_regwen[11].configure(.blk_parent(this)); + range_regwen[11].build(csr_excl); + default_map.add_reg(.rg(range_regwen[11]), + .offset(32'h48)); + range_regwen[11].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_regwen_11.q", + 0, 4, 0, "BkdrRegPathRtl"); + + range_regwen[12] = + (ac_range_check_reg_range_regwen:: + type_id::create("range_regwen_12")); + range_regwen[12].configure(.blk_parent(this)); + range_regwen[12].build(csr_excl); + default_map.add_reg(.rg(range_regwen[12]), + .offset(32'h4c)); + range_regwen[12].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_regwen_12.q", + 0, 4, 0, "BkdrRegPathRtl"); + + range_regwen[13] = + (ac_range_check_reg_range_regwen:: + type_id::create("range_regwen_13")); + range_regwen[13].configure(.blk_parent(this)); + range_regwen[13].build(csr_excl); + default_map.add_reg(.rg(range_regwen[13]), + .offset(32'h50)); + range_regwen[13].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_regwen_13.q", + 0, 4, 0, "BkdrRegPathRtl"); + + range_regwen[14] = + (ac_range_check_reg_range_regwen:: + type_id::create("range_regwen_14")); + range_regwen[14].configure(.blk_parent(this)); + range_regwen[14].build(csr_excl); + default_map.add_reg(.rg(range_regwen[14]), + .offset(32'h54)); + range_regwen[14].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_regwen_14.q", + 0, 4, 0, "BkdrRegPathRtl"); + + range_regwen[15] = + (ac_range_check_reg_range_regwen:: + type_id::create("range_regwen_15")); + range_regwen[15].configure(.blk_parent(this)); + range_regwen[15].build(csr_excl); + default_map.add_reg(.rg(range_regwen[15]), + .offset(32'h58)); + range_regwen[15].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_regwen_15.q", + 0, 4, 0, "BkdrRegPathRtl"); + + range_regwen[16] = + (ac_range_check_reg_range_regwen:: + type_id::create("range_regwen_16")); + range_regwen[16].configure(.blk_parent(this)); + range_regwen[16].build(csr_excl); + default_map.add_reg(.rg(range_regwen[16]), + .offset(32'h5c)); + range_regwen[16].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_regwen_16.q", + 0, 4, 0, "BkdrRegPathRtl"); + + range_regwen[17] = + (ac_range_check_reg_range_regwen:: + type_id::create("range_regwen_17")); + range_regwen[17].configure(.blk_parent(this)); + range_regwen[17].build(csr_excl); + default_map.add_reg(.rg(range_regwen[17]), + .offset(32'h60)); + range_regwen[17].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_regwen_17.q", + 0, 4, 0, "BkdrRegPathRtl"); + + range_regwen[18] = + (ac_range_check_reg_range_regwen:: + type_id::create("range_regwen_18")); + range_regwen[18].configure(.blk_parent(this)); + range_regwen[18].build(csr_excl); + default_map.add_reg(.rg(range_regwen[18]), + .offset(32'h64)); + range_regwen[18].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_regwen_18.q", + 0, 4, 0, "BkdrRegPathRtl"); + + range_regwen[19] = + (ac_range_check_reg_range_regwen:: + type_id::create("range_regwen_19")); + range_regwen[19].configure(.blk_parent(this)); + range_regwen[19].build(csr_excl); + default_map.add_reg(.rg(range_regwen[19]), + .offset(32'h68)); + range_regwen[19].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_regwen_19.q", + 0, 4, 0, "BkdrRegPathRtl"); + + range_regwen[20] = + (ac_range_check_reg_range_regwen:: + type_id::create("range_regwen_20")); + range_regwen[20].configure(.blk_parent(this)); + range_regwen[20].build(csr_excl); + default_map.add_reg(.rg(range_regwen[20]), + .offset(32'h6c)); + range_regwen[20].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_regwen_20.q", + 0, 4, 0, "BkdrRegPathRtl"); + + range_regwen[21] = + (ac_range_check_reg_range_regwen:: + type_id::create("range_regwen_21")); + range_regwen[21].configure(.blk_parent(this)); + range_regwen[21].build(csr_excl); + default_map.add_reg(.rg(range_regwen[21]), + .offset(32'h70)); + range_regwen[21].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_regwen_21.q", + 0, 4, 0, "BkdrRegPathRtl"); + + range_regwen[22] = + (ac_range_check_reg_range_regwen:: + type_id::create("range_regwen_22")); + range_regwen[22].configure(.blk_parent(this)); + range_regwen[22].build(csr_excl); + default_map.add_reg(.rg(range_regwen[22]), + .offset(32'h74)); + range_regwen[22].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_regwen_22.q", + 0, 4, 0, "BkdrRegPathRtl"); + + range_regwen[23] = + (ac_range_check_reg_range_regwen:: + type_id::create("range_regwen_23")); + range_regwen[23].configure(.blk_parent(this)); + range_regwen[23].build(csr_excl); + default_map.add_reg(.rg(range_regwen[23]), + .offset(32'h78)); + range_regwen[23].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_regwen_23.q", + 0, 4, 0, "BkdrRegPathRtl"); + + range_regwen[24] = + (ac_range_check_reg_range_regwen:: + type_id::create("range_regwen_24")); + range_regwen[24].configure(.blk_parent(this)); + range_regwen[24].build(csr_excl); + default_map.add_reg(.rg(range_regwen[24]), + .offset(32'h7c)); + range_regwen[24].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_regwen_24.q", + 0, 4, 0, "BkdrRegPathRtl"); + + range_regwen[25] = + (ac_range_check_reg_range_regwen:: + type_id::create("range_regwen_25")); + range_regwen[25].configure(.blk_parent(this)); + range_regwen[25].build(csr_excl); + default_map.add_reg(.rg(range_regwen[25]), + .offset(32'h80)); + range_regwen[25].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_regwen_25.q", + 0, 4, 0, "BkdrRegPathRtl"); + + range_regwen[26] = + (ac_range_check_reg_range_regwen:: + type_id::create("range_regwen_26")); + range_regwen[26].configure(.blk_parent(this)); + range_regwen[26].build(csr_excl); + default_map.add_reg(.rg(range_regwen[26]), + .offset(32'h84)); + range_regwen[26].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_regwen_26.q", + 0, 4, 0, "BkdrRegPathRtl"); + + range_regwen[27] = + (ac_range_check_reg_range_regwen:: + type_id::create("range_regwen_27")); + range_regwen[27].configure(.blk_parent(this)); + range_regwen[27].build(csr_excl); + default_map.add_reg(.rg(range_regwen[27]), + .offset(32'h88)); + range_regwen[27].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_regwen_27.q", + 0, 4, 0, "BkdrRegPathRtl"); + + range_regwen[28] = + (ac_range_check_reg_range_regwen:: + type_id::create("range_regwen_28")); + range_regwen[28].configure(.blk_parent(this)); + range_regwen[28].build(csr_excl); + default_map.add_reg(.rg(range_regwen[28]), + .offset(32'h8c)); + range_regwen[28].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_regwen_28.q", + 0, 4, 0, "BkdrRegPathRtl"); + + range_regwen[29] = + (ac_range_check_reg_range_regwen:: + type_id::create("range_regwen_29")); + range_regwen[29].configure(.blk_parent(this)); + range_regwen[29].build(csr_excl); + default_map.add_reg(.rg(range_regwen[29]), + .offset(32'h90)); + range_regwen[29].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_regwen_29.q", + 0, 4, 0, "BkdrRegPathRtl"); + + range_regwen[30] = + (ac_range_check_reg_range_regwen:: + type_id::create("range_regwen_30")); + range_regwen[30].configure(.blk_parent(this)); + range_regwen[30].build(csr_excl); + default_map.add_reg(.rg(range_regwen[30]), + .offset(32'h94)); + range_regwen[30].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_regwen_30.q", + 0, 4, 0, "BkdrRegPathRtl"); + + range_regwen[31] = + (ac_range_check_reg_range_regwen:: + type_id::create("range_regwen_31")); + range_regwen[31].configure(.blk_parent(this)); + range_regwen[31].build(csr_excl); + default_map.add_reg(.rg(range_regwen[31]), + .offset(32'h98)); + range_regwen[31].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_regwen_31.q", + 0, 4, 0, "BkdrRegPathRtl"); + + range_base[0] = + (ac_range_check_reg_range_base:: + type_id::create("range_base_0")); + range_base[0].configure(.blk_parent(this)); + range_base[0].build(csr_excl); + default_map.add_reg(.rg(range_base[0]), + .offset(32'h9c)); + range_base[0].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_base_0.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_base[1] = + (ac_range_check_reg_range_base:: + type_id::create("range_base_1")); + range_base[1].configure(.blk_parent(this)); + range_base[1].build(csr_excl); + default_map.add_reg(.rg(range_base[1]), + .offset(32'ha0)); + range_base[1].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_base_1.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_base[2] = + (ac_range_check_reg_range_base:: + type_id::create("range_base_2")); + range_base[2].configure(.blk_parent(this)); + range_base[2].build(csr_excl); + default_map.add_reg(.rg(range_base[2]), + .offset(32'ha4)); + range_base[2].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_base_2.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_base[3] = + (ac_range_check_reg_range_base:: + type_id::create("range_base_3")); + range_base[3].configure(.blk_parent(this)); + range_base[3].build(csr_excl); + default_map.add_reg(.rg(range_base[3]), + .offset(32'ha8)); + range_base[3].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_base_3.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_base[4] = + (ac_range_check_reg_range_base:: + type_id::create("range_base_4")); + range_base[4].configure(.blk_parent(this)); + range_base[4].build(csr_excl); + default_map.add_reg(.rg(range_base[4]), + .offset(32'hac)); + range_base[4].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_base_4.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_base[5] = + (ac_range_check_reg_range_base:: + type_id::create("range_base_5")); + range_base[5].configure(.blk_parent(this)); + range_base[5].build(csr_excl); + default_map.add_reg(.rg(range_base[5]), + .offset(32'hb0)); + range_base[5].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_base_5.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_base[6] = + (ac_range_check_reg_range_base:: + type_id::create("range_base_6")); + range_base[6].configure(.blk_parent(this)); + range_base[6].build(csr_excl); + default_map.add_reg(.rg(range_base[6]), + .offset(32'hb4)); + range_base[6].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_base_6.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_base[7] = + (ac_range_check_reg_range_base:: + type_id::create("range_base_7")); + range_base[7].configure(.blk_parent(this)); + range_base[7].build(csr_excl); + default_map.add_reg(.rg(range_base[7]), + .offset(32'hb8)); + range_base[7].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_base_7.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_base[8] = + (ac_range_check_reg_range_base:: + type_id::create("range_base_8")); + range_base[8].configure(.blk_parent(this)); + range_base[8].build(csr_excl); + default_map.add_reg(.rg(range_base[8]), + .offset(32'hbc)); + range_base[8].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_base_8.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_base[9] = + (ac_range_check_reg_range_base:: + type_id::create("range_base_9")); + range_base[9].configure(.blk_parent(this)); + range_base[9].build(csr_excl); + default_map.add_reg(.rg(range_base[9]), + .offset(32'hc0)); + range_base[9].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_base_9.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_base[10] = + (ac_range_check_reg_range_base:: + type_id::create("range_base_10")); + range_base[10].configure(.blk_parent(this)); + range_base[10].build(csr_excl); + default_map.add_reg(.rg(range_base[10]), + .offset(32'hc4)); + range_base[10].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_base_10.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_base[11] = + (ac_range_check_reg_range_base:: + type_id::create("range_base_11")); + range_base[11].configure(.blk_parent(this)); + range_base[11].build(csr_excl); + default_map.add_reg(.rg(range_base[11]), + .offset(32'hc8)); + range_base[11].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_base_11.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_base[12] = + (ac_range_check_reg_range_base:: + type_id::create("range_base_12")); + range_base[12].configure(.blk_parent(this)); + range_base[12].build(csr_excl); + default_map.add_reg(.rg(range_base[12]), + .offset(32'hcc)); + range_base[12].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_base_12.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_base[13] = + (ac_range_check_reg_range_base:: + type_id::create("range_base_13")); + range_base[13].configure(.blk_parent(this)); + range_base[13].build(csr_excl); + default_map.add_reg(.rg(range_base[13]), + .offset(32'hd0)); + range_base[13].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_base_13.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_base[14] = + (ac_range_check_reg_range_base:: + type_id::create("range_base_14")); + range_base[14].configure(.blk_parent(this)); + range_base[14].build(csr_excl); + default_map.add_reg(.rg(range_base[14]), + .offset(32'hd4)); + range_base[14].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_base_14.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_base[15] = + (ac_range_check_reg_range_base:: + type_id::create("range_base_15")); + range_base[15].configure(.blk_parent(this)); + range_base[15].build(csr_excl); + default_map.add_reg(.rg(range_base[15]), + .offset(32'hd8)); + range_base[15].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_base_15.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_base[16] = + (ac_range_check_reg_range_base:: + type_id::create("range_base_16")); + range_base[16].configure(.blk_parent(this)); + range_base[16].build(csr_excl); + default_map.add_reg(.rg(range_base[16]), + .offset(32'hdc)); + range_base[16].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_base_16.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_base[17] = + (ac_range_check_reg_range_base:: + type_id::create("range_base_17")); + range_base[17].configure(.blk_parent(this)); + range_base[17].build(csr_excl); + default_map.add_reg(.rg(range_base[17]), + .offset(32'he0)); + range_base[17].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_base_17.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_base[18] = + (ac_range_check_reg_range_base:: + type_id::create("range_base_18")); + range_base[18].configure(.blk_parent(this)); + range_base[18].build(csr_excl); + default_map.add_reg(.rg(range_base[18]), + .offset(32'he4)); + range_base[18].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_base_18.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_base[19] = + (ac_range_check_reg_range_base:: + type_id::create("range_base_19")); + range_base[19].configure(.blk_parent(this)); + range_base[19].build(csr_excl); + default_map.add_reg(.rg(range_base[19]), + .offset(32'he8)); + range_base[19].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_base_19.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_base[20] = + (ac_range_check_reg_range_base:: + type_id::create("range_base_20")); + range_base[20].configure(.blk_parent(this)); + range_base[20].build(csr_excl); + default_map.add_reg(.rg(range_base[20]), + .offset(32'hec)); + range_base[20].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_base_20.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_base[21] = + (ac_range_check_reg_range_base:: + type_id::create("range_base_21")); + range_base[21].configure(.blk_parent(this)); + range_base[21].build(csr_excl); + default_map.add_reg(.rg(range_base[21]), + .offset(32'hf0)); + range_base[21].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_base_21.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_base[22] = + (ac_range_check_reg_range_base:: + type_id::create("range_base_22")); + range_base[22].configure(.blk_parent(this)); + range_base[22].build(csr_excl); + default_map.add_reg(.rg(range_base[22]), + .offset(32'hf4)); + range_base[22].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_base_22.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_base[23] = + (ac_range_check_reg_range_base:: + type_id::create("range_base_23")); + range_base[23].configure(.blk_parent(this)); + range_base[23].build(csr_excl); + default_map.add_reg(.rg(range_base[23]), + .offset(32'hf8)); + range_base[23].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_base_23.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_base[24] = + (ac_range_check_reg_range_base:: + type_id::create("range_base_24")); + range_base[24].configure(.blk_parent(this)); + range_base[24].build(csr_excl); + default_map.add_reg(.rg(range_base[24]), + .offset(32'hfc)); + range_base[24].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_base_24.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_base[25] = + (ac_range_check_reg_range_base:: + type_id::create("range_base_25")); + range_base[25].configure(.blk_parent(this)); + range_base[25].build(csr_excl); + default_map.add_reg(.rg(range_base[25]), + .offset(32'h100)); + range_base[25].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_base_25.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_base[26] = + (ac_range_check_reg_range_base:: + type_id::create("range_base_26")); + range_base[26].configure(.blk_parent(this)); + range_base[26].build(csr_excl); + default_map.add_reg(.rg(range_base[26]), + .offset(32'h104)); + range_base[26].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_base_26.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_base[27] = + (ac_range_check_reg_range_base:: + type_id::create("range_base_27")); + range_base[27].configure(.blk_parent(this)); + range_base[27].build(csr_excl); + default_map.add_reg(.rg(range_base[27]), + .offset(32'h108)); + range_base[27].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_base_27.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_base[28] = + (ac_range_check_reg_range_base:: + type_id::create("range_base_28")); + range_base[28].configure(.blk_parent(this)); + range_base[28].build(csr_excl); + default_map.add_reg(.rg(range_base[28]), + .offset(32'h10c)); + range_base[28].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_base_28.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_base[29] = + (ac_range_check_reg_range_base:: + type_id::create("range_base_29")); + range_base[29].configure(.blk_parent(this)); + range_base[29].build(csr_excl); + default_map.add_reg(.rg(range_base[29]), + .offset(32'h110)); + range_base[29].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_base_29.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_base[30] = + (ac_range_check_reg_range_base:: + type_id::create("range_base_30")); + range_base[30].configure(.blk_parent(this)); + range_base[30].build(csr_excl); + default_map.add_reg(.rg(range_base[30]), + .offset(32'h114)); + range_base[30].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_base_30.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_base[31] = + (ac_range_check_reg_range_base:: + type_id::create("range_base_31")); + range_base[31].configure(.blk_parent(this)); + range_base[31].build(csr_excl); + default_map.add_reg(.rg(range_base[31]), + .offset(32'h118)); + range_base[31].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_base_31.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_limit[0] = + (ac_range_check_reg_range_limit:: + type_id::create("range_limit_0")); + range_limit[0].configure(.blk_parent(this)); + range_limit[0].build(csr_excl); + default_map.add_reg(.rg(range_limit[0]), + .offset(32'h11c)); + range_limit[0].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_limit_0.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_limit[1] = + (ac_range_check_reg_range_limit:: + type_id::create("range_limit_1")); + range_limit[1].configure(.blk_parent(this)); + range_limit[1].build(csr_excl); + default_map.add_reg(.rg(range_limit[1]), + .offset(32'h120)); + range_limit[1].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_limit_1.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_limit[2] = + (ac_range_check_reg_range_limit:: + type_id::create("range_limit_2")); + range_limit[2].configure(.blk_parent(this)); + range_limit[2].build(csr_excl); + default_map.add_reg(.rg(range_limit[2]), + .offset(32'h124)); + range_limit[2].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_limit_2.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_limit[3] = + (ac_range_check_reg_range_limit:: + type_id::create("range_limit_3")); + range_limit[3].configure(.blk_parent(this)); + range_limit[3].build(csr_excl); + default_map.add_reg(.rg(range_limit[3]), + .offset(32'h128)); + range_limit[3].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_limit_3.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_limit[4] = + (ac_range_check_reg_range_limit:: + type_id::create("range_limit_4")); + range_limit[4].configure(.blk_parent(this)); + range_limit[4].build(csr_excl); + default_map.add_reg(.rg(range_limit[4]), + .offset(32'h12c)); + range_limit[4].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_limit_4.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_limit[5] = + (ac_range_check_reg_range_limit:: + type_id::create("range_limit_5")); + range_limit[5].configure(.blk_parent(this)); + range_limit[5].build(csr_excl); + default_map.add_reg(.rg(range_limit[5]), + .offset(32'h130)); + range_limit[5].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_limit_5.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_limit[6] = + (ac_range_check_reg_range_limit:: + type_id::create("range_limit_6")); + range_limit[6].configure(.blk_parent(this)); + range_limit[6].build(csr_excl); + default_map.add_reg(.rg(range_limit[6]), + .offset(32'h134)); + range_limit[6].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_limit_6.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_limit[7] = + (ac_range_check_reg_range_limit:: + type_id::create("range_limit_7")); + range_limit[7].configure(.blk_parent(this)); + range_limit[7].build(csr_excl); + default_map.add_reg(.rg(range_limit[7]), + .offset(32'h138)); + range_limit[7].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_limit_7.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_limit[8] = + (ac_range_check_reg_range_limit:: + type_id::create("range_limit_8")); + range_limit[8].configure(.blk_parent(this)); + range_limit[8].build(csr_excl); + default_map.add_reg(.rg(range_limit[8]), + .offset(32'h13c)); + range_limit[8].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_limit_8.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_limit[9] = + (ac_range_check_reg_range_limit:: + type_id::create("range_limit_9")); + range_limit[9].configure(.blk_parent(this)); + range_limit[9].build(csr_excl); + default_map.add_reg(.rg(range_limit[9]), + .offset(32'h140)); + range_limit[9].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_limit_9.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_limit[10] = + (ac_range_check_reg_range_limit:: + type_id::create("range_limit_10")); + range_limit[10].configure(.blk_parent(this)); + range_limit[10].build(csr_excl); + default_map.add_reg(.rg(range_limit[10]), + .offset(32'h144)); + range_limit[10].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_limit_10.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_limit[11] = + (ac_range_check_reg_range_limit:: + type_id::create("range_limit_11")); + range_limit[11].configure(.blk_parent(this)); + range_limit[11].build(csr_excl); + default_map.add_reg(.rg(range_limit[11]), + .offset(32'h148)); + range_limit[11].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_limit_11.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_limit[12] = + (ac_range_check_reg_range_limit:: + type_id::create("range_limit_12")); + range_limit[12].configure(.blk_parent(this)); + range_limit[12].build(csr_excl); + default_map.add_reg(.rg(range_limit[12]), + .offset(32'h14c)); + range_limit[12].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_limit_12.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_limit[13] = + (ac_range_check_reg_range_limit:: + type_id::create("range_limit_13")); + range_limit[13].configure(.blk_parent(this)); + range_limit[13].build(csr_excl); + default_map.add_reg(.rg(range_limit[13]), + .offset(32'h150)); + range_limit[13].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_limit_13.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_limit[14] = + (ac_range_check_reg_range_limit:: + type_id::create("range_limit_14")); + range_limit[14].configure(.blk_parent(this)); + range_limit[14].build(csr_excl); + default_map.add_reg(.rg(range_limit[14]), + .offset(32'h154)); + range_limit[14].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_limit_14.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_limit[15] = + (ac_range_check_reg_range_limit:: + type_id::create("range_limit_15")); + range_limit[15].configure(.blk_parent(this)); + range_limit[15].build(csr_excl); + default_map.add_reg(.rg(range_limit[15]), + .offset(32'h158)); + range_limit[15].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_limit_15.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_limit[16] = + (ac_range_check_reg_range_limit:: + type_id::create("range_limit_16")); + range_limit[16].configure(.blk_parent(this)); + range_limit[16].build(csr_excl); + default_map.add_reg(.rg(range_limit[16]), + .offset(32'h15c)); + range_limit[16].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_limit_16.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_limit[17] = + (ac_range_check_reg_range_limit:: + type_id::create("range_limit_17")); + range_limit[17].configure(.blk_parent(this)); + range_limit[17].build(csr_excl); + default_map.add_reg(.rg(range_limit[17]), + .offset(32'h160)); + range_limit[17].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_limit_17.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_limit[18] = + (ac_range_check_reg_range_limit:: + type_id::create("range_limit_18")); + range_limit[18].configure(.blk_parent(this)); + range_limit[18].build(csr_excl); + default_map.add_reg(.rg(range_limit[18]), + .offset(32'h164)); + range_limit[18].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_limit_18.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_limit[19] = + (ac_range_check_reg_range_limit:: + type_id::create("range_limit_19")); + range_limit[19].configure(.blk_parent(this)); + range_limit[19].build(csr_excl); + default_map.add_reg(.rg(range_limit[19]), + .offset(32'h168)); + range_limit[19].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_limit_19.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_limit[20] = + (ac_range_check_reg_range_limit:: + type_id::create("range_limit_20")); + range_limit[20].configure(.blk_parent(this)); + range_limit[20].build(csr_excl); + default_map.add_reg(.rg(range_limit[20]), + .offset(32'h16c)); + range_limit[20].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_limit_20.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_limit[21] = + (ac_range_check_reg_range_limit:: + type_id::create("range_limit_21")); + range_limit[21].configure(.blk_parent(this)); + range_limit[21].build(csr_excl); + default_map.add_reg(.rg(range_limit[21]), + .offset(32'h170)); + range_limit[21].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_limit_21.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_limit[22] = + (ac_range_check_reg_range_limit:: + type_id::create("range_limit_22")); + range_limit[22].configure(.blk_parent(this)); + range_limit[22].build(csr_excl); + default_map.add_reg(.rg(range_limit[22]), + .offset(32'h174)); + range_limit[22].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_limit_22.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_limit[23] = + (ac_range_check_reg_range_limit:: + type_id::create("range_limit_23")); + range_limit[23].configure(.blk_parent(this)); + range_limit[23].build(csr_excl); + default_map.add_reg(.rg(range_limit[23]), + .offset(32'h178)); + range_limit[23].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_limit_23.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_limit[24] = + (ac_range_check_reg_range_limit:: + type_id::create("range_limit_24")); + range_limit[24].configure(.blk_parent(this)); + range_limit[24].build(csr_excl); + default_map.add_reg(.rg(range_limit[24]), + .offset(32'h17c)); + range_limit[24].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_limit_24.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_limit[25] = + (ac_range_check_reg_range_limit:: + type_id::create("range_limit_25")); + range_limit[25].configure(.blk_parent(this)); + range_limit[25].build(csr_excl); + default_map.add_reg(.rg(range_limit[25]), + .offset(32'h180)); + range_limit[25].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_limit_25.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_limit[26] = + (ac_range_check_reg_range_limit:: + type_id::create("range_limit_26")); + range_limit[26].configure(.blk_parent(this)); + range_limit[26].build(csr_excl); + default_map.add_reg(.rg(range_limit[26]), + .offset(32'h184)); + range_limit[26].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_limit_26.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_limit[27] = + (ac_range_check_reg_range_limit:: + type_id::create("range_limit_27")); + range_limit[27].configure(.blk_parent(this)); + range_limit[27].build(csr_excl); + default_map.add_reg(.rg(range_limit[27]), + .offset(32'h188)); + range_limit[27].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_limit_27.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_limit[28] = + (ac_range_check_reg_range_limit:: + type_id::create("range_limit_28")); + range_limit[28].configure(.blk_parent(this)); + range_limit[28].build(csr_excl); + default_map.add_reg(.rg(range_limit[28]), + .offset(32'h18c)); + range_limit[28].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_limit_28.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_limit[29] = + (ac_range_check_reg_range_limit:: + type_id::create("range_limit_29")); + range_limit[29].configure(.blk_parent(this)); + range_limit[29].build(csr_excl); + default_map.add_reg(.rg(range_limit[29]), + .offset(32'h190)); + range_limit[29].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_limit_29.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_limit[30] = + (ac_range_check_reg_range_limit:: + type_id::create("range_limit_30")); + range_limit[30].configure(.blk_parent(this)); + range_limit[30].build(csr_excl); + default_map.add_reg(.rg(range_limit[30]), + .offset(32'h194)); + range_limit[30].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_limit_30.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_limit[31] = + (ac_range_check_reg_range_limit:: + type_id::create("range_limit_31")); + range_limit[31].configure(.blk_parent(this)); + range_limit[31].build(csr_excl); + default_map.add_reg(.rg(range_limit[31]), + .offset(32'h198)); + range_limit[31].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_limit_31.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_perm[0] = + (ac_range_check_reg_range_perm:: + type_id::create("range_perm_0")); + range_perm[0].configure(.blk_parent(this)); + range_perm[0].build(csr_excl); + default_map.add_reg(.rg(range_perm[0]), + .offset(32'h19c)); + range_perm[0].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_0_enable_0.q", + 0, 4, 0, "BkdrRegPathRtl"); + range_perm[0].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_0_read_access_0.q", + 4, 4, 0, "BkdrRegPathRtl"); + range_perm[0].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_0_write_access_0.q", + 8, 4, 0, "BkdrRegPathRtl"); + range_perm[0].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_0_execute_access_0.q", + 12, 4, 0, "BkdrRegPathRtl"); + range_perm[0].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_0_log_denied_access_0.q", + 16, 4, 0, "BkdrRegPathRtl"); + + range_perm[1] = + (ac_range_check_reg_range_perm:: + type_id::create("range_perm_1")); + range_perm[1].configure(.blk_parent(this)); + range_perm[1].build(csr_excl); + default_map.add_reg(.rg(range_perm[1]), + .offset(32'h1a0)); + range_perm[1].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_1_enable_1.q", + 0, 4, 0, "BkdrRegPathRtl"); + range_perm[1].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_1_read_access_1.q", + 4, 4, 0, "BkdrRegPathRtl"); + range_perm[1].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_1_write_access_1.q", + 8, 4, 0, "BkdrRegPathRtl"); + range_perm[1].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_1_execute_access_1.q", + 12, 4, 0, "BkdrRegPathRtl"); + range_perm[1].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_1_log_denied_access_1.q", + 16, 4, 0, "BkdrRegPathRtl"); + + range_perm[2] = + (ac_range_check_reg_range_perm:: + type_id::create("range_perm_2")); + range_perm[2].configure(.blk_parent(this)); + range_perm[2].build(csr_excl); + default_map.add_reg(.rg(range_perm[2]), + .offset(32'h1a4)); + range_perm[2].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_2_enable_2.q", + 0, 4, 0, "BkdrRegPathRtl"); + range_perm[2].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_2_read_access_2.q", + 4, 4, 0, "BkdrRegPathRtl"); + range_perm[2].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_2_write_access_2.q", + 8, 4, 0, "BkdrRegPathRtl"); + range_perm[2].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_2_execute_access_2.q", + 12, 4, 0, "BkdrRegPathRtl"); + range_perm[2].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_2_log_denied_access_2.q", + 16, 4, 0, "BkdrRegPathRtl"); + + range_perm[3] = + (ac_range_check_reg_range_perm:: + type_id::create("range_perm_3")); + range_perm[3].configure(.blk_parent(this)); + range_perm[3].build(csr_excl); + default_map.add_reg(.rg(range_perm[3]), + .offset(32'h1a8)); + range_perm[3].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_3_enable_3.q", + 0, 4, 0, "BkdrRegPathRtl"); + range_perm[3].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_3_read_access_3.q", + 4, 4, 0, "BkdrRegPathRtl"); + range_perm[3].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_3_write_access_3.q", + 8, 4, 0, "BkdrRegPathRtl"); + range_perm[3].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_3_execute_access_3.q", + 12, 4, 0, "BkdrRegPathRtl"); + range_perm[3].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_3_log_denied_access_3.q", + 16, 4, 0, "BkdrRegPathRtl"); + + range_perm[4] = + (ac_range_check_reg_range_perm:: + type_id::create("range_perm_4")); + range_perm[4].configure(.blk_parent(this)); + range_perm[4].build(csr_excl); + default_map.add_reg(.rg(range_perm[4]), + .offset(32'h1ac)); + range_perm[4].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_4_enable_4.q", + 0, 4, 0, "BkdrRegPathRtl"); + range_perm[4].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_4_read_access_4.q", + 4, 4, 0, "BkdrRegPathRtl"); + range_perm[4].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_4_write_access_4.q", + 8, 4, 0, "BkdrRegPathRtl"); + range_perm[4].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_4_execute_access_4.q", + 12, 4, 0, "BkdrRegPathRtl"); + range_perm[4].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_4_log_denied_access_4.q", + 16, 4, 0, "BkdrRegPathRtl"); + + range_perm[5] = + (ac_range_check_reg_range_perm:: + type_id::create("range_perm_5")); + range_perm[5].configure(.blk_parent(this)); + range_perm[5].build(csr_excl); + default_map.add_reg(.rg(range_perm[5]), + .offset(32'h1b0)); + range_perm[5].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_5_enable_5.q", + 0, 4, 0, "BkdrRegPathRtl"); + range_perm[5].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_5_read_access_5.q", + 4, 4, 0, "BkdrRegPathRtl"); + range_perm[5].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_5_write_access_5.q", + 8, 4, 0, "BkdrRegPathRtl"); + range_perm[5].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_5_execute_access_5.q", + 12, 4, 0, "BkdrRegPathRtl"); + range_perm[5].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_5_log_denied_access_5.q", + 16, 4, 0, "BkdrRegPathRtl"); + + range_perm[6] = + (ac_range_check_reg_range_perm:: + type_id::create("range_perm_6")); + range_perm[6].configure(.blk_parent(this)); + range_perm[6].build(csr_excl); + default_map.add_reg(.rg(range_perm[6]), + .offset(32'h1b4)); + range_perm[6].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_6_enable_6.q", + 0, 4, 0, "BkdrRegPathRtl"); + range_perm[6].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_6_read_access_6.q", + 4, 4, 0, "BkdrRegPathRtl"); + range_perm[6].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_6_write_access_6.q", + 8, 4, 0, "BkdrRegPathRtl"); + range_perm[6].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_6_execute_access_6.q", + 12, 4, 0, "BkdrRegPathRtl"); + range_perm[6].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_6_log_denied_access_6.q", + 16, 4, 0, "BkdrRegPathRtl"); + + range_perm[7] = + (ac_range_check_reg_range_perm:: + type_id::create("range_perm_7")); + range_perm[7].configure(.blk_parent(this)); + range_perm[7].build(csr_excl); + default_map.add_reg(.rg(range_perm[7]), + .offset(32'h1b8)); + range_perm[7].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_7_enable_7.q", + 0, 4, 0, "BkdrRegPathRtl"); + range_perm[7].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_7_read_access_7.q", + 4, 4, 0, "BkdrRegPathRtl"); + range_perm[7].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_7_write_access_7.q", + 8, 4, 0, "BkdrRegPathRtl"); + range_perm[7].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_7_execute_access_7.q", + 12, 4, 0, "BkdrRegPathRtl"); + range_perm[7].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_7_log_denied_access_7.q", + 16, 4, 0, "BkdrRegPathRtl"); + + range_perm[8] = + (ac_range_check_reg_range_perm:: + type_id::create("range_perm_8")); + range_perm[8].configure(.blk_parent(this)); + range_perm[8].build(csr_excl); + default_map.add_reg(.rg(range_perm[8]), + .offset(32'h1bc)); + range_perm[8].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_8_enable_8.q", + 0, 4, 0, "BkdrRegPathRtl"); + range_perm[8].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_8_read_access_8.q", + 4, 4, 0, "BkdrRegPathRtl"); + range_perm[8].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_8_write_access_8.q", + 8, 4, 0, "BkdrRegPathRtl"); + range_perm[8].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_8_execute_access_8.q", + 12, 4, 0, "BkdrRegPathRtl"); + range_perm[8].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_8_log_denied_access_8.q", + 16, 4, 0, "BkdrRegPathRtl"); + + range_perm[9] = + (ac_range_check_reg_range_perm:: + type_id::create("range_perm_9")); + range_perm[9].configure(.blk_parent(this)); + range_perm[9].build(csr_excl); + default_map.add_reg(.rg(range_perm[9]), + .offset(32'h1c0)); + range_perm[9].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_9_enable_9.q", + 0, 4, 0, "BkdrRegPathRtl"); + range_perm[9].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_9_read_access_9.q", + 4, 4, 0, "BkdrRegPathRtl"); + range_perm[9].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_9_write_access_9.q", + 8, 4, 0, "BkdrRegPathRtl"); + range_perm[9].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_9_execute_access_9.q", + 12, 4, 0, "BkdrRegPathRtl"); + range_perm[9].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_9_log_denied_access_9.q", + 16, 4, 0, "BkdrRegPathRtl"); + + range_perm[10] = + (ac_range_check_reg_range_perm:: + type_id::create("range_perm_10")); + range_perm[10].configure(.blk_parent(this)); + range_perm[10].build(csr_excl); + default_map.add_reg(.rg(range_perm[10]), + .offset(32'h1c4)); + range_perm[10].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_10_enable_10.q", + 0, 4, 0, "BkdrRegPathRtl"); + range_perm[10].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_10_read_access_10.q", + 4, 4, 0, "BkdrRegPathRtl"); + range_perm[10].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_10_write_access_10.q", + 8, 4, 0, "BkdrRegPathRtl"); + range_perm[10].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_10_execute_access_10.q", + 12, 4, 0, "BkdrRegPathRtl"); + range_perm[10].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_10_log_denied_access_10.q", + 16, 4, 0, "BkdrRegPathRtl"); + + range_perm[11] = + (ac_range_check_reg_range_perm:: + type_id::create("range_perm_11")); + range_perm[11].configure(.blk_parent(this)); + range_perm[11].build(csr_excl); + default_map.add_reg(.rg(range_perm[11]), + .offset(32'h1c8)); + range_perm[11].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_11_enable_11.q", + 0, 4, 0, "BkdrRegPathRtl"); + range_perm[11].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_11_read_access_11.q", + 4, 4, 0, "BkdrRegPathRtl"); + range_perm[11].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_11_write_access_11.q", + 8, 4, 0, "BkdrRegPathRtl"); + range_perm[11].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_11_execute_access_11.q", + 12, 4, 0, "BkdrRegPathRtl"); + range_perm[11].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_11_log_denied_access_11.q", + 16, 4, 0, "BkdrRegPathRtl"); + + range_perm[12] = + (ac_range_check_reg_range_perm:: + type_id::create("range_perm_12")); + range_perm[12].configure(.blk_parent(this)); + range_perm[12].build(csr_excl); + default_map.add_reg(.rg(range_perm[12]), + .offset(32'h1cc)); + range_perm[12].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_12_enable_12.q", + 0, 4, 0, "BkdrRegPathRtl"); + range_perm[12].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_12_read_access_12.q", + 4, 4, 0, "BkdrRegPathRtl"); + range_perm[12].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_12_write_access_12.q", + 8, 4, 0, "BkdrRegPathRtl"); + range_perm[12].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_12_execute_access_12.q", + 12, 4, 0, "BkdrRegPathRtl"); + range_perm[12].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_12_log_denied_access_12.q", + 16, 4, 0, "BkdrRegPathRtl"); + + range_perm[13] = + (ac_range_check_reg_range_perm:: + type_id::create("range_perm_13")); + range_perm[13].configure(.blk_parent(this)); + range_perm[13].build(csr_excl); + default_map.add_reg(.rg(range_perm[13]), + .offset(32'h1d0)); + range_perm[13].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_13_enable_13.q", + 0, 4, 0, "BkdrRegPathRtl"); + range_perm[13].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_13_read_access_13.q", + 4, 4, 0, "BkdrRegPathRtl"); + range_perm[13].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_13_write_access_13.q", + 8, 4, 0, "BkdrRegPathRtl"); + range_perm[13].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_13_execute_access_13.q", + 12, 4, 0, "BkdrRegPathRtl"); + range_perm[13].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_13_log_denied_access_13.q", + 16, 4, 0, "BkdrRegPathRtl"); + + range_perm[14] = + (ac_range_check_reg_range_perm:: + type_id::create("range_perm_14")); + range_perm[14].configure(.blk_parent(this)); + range_perm[14].build(csr_excl); + default_map.add_reg(.rg(range_perm[14]), + .offset(32'h1d4)); + range_perm[14].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_14_enable_14.q", + 0, 4, 0, "BkdrRegPathRtl"); + range_perm[14].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_14_read_access_14.q", + 4, 4, 0, "BkdrRegPathRtl"); + range_perm[14].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_14_write_access_14.q", + 8, 4, 0, "BkdrRegPathRtl"); + range_perm[14].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_14_execute_access_14.q", + 12, 4, 0, "BkdrRegPathRtl"); + range_perm[14].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_14_log_denied_access_14.q", + 16, 4, 0, "BkdrRegPathRtl"); + + range_perm[15] = + (ac_range_check_reg_range_perm:: + type_id::create("range_perm_15")); + range_perm[15].configure(.blk_parent(this)); + range_perm[15].build(csr_excl); + default_map.add_reg(.rg(range_perm[15]), + .offset(32'h1d8)); + range_perm[15].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_15_enable_15.q", + 0, 4, 0, "BkdrRegPathRtl"); + range_perm[15].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_15_read_access_15.q", + 4, 4, 0, "BkdrRegPathRtl"); + range_perm[15].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_15_write_access_15.q", + 8, 4, 0, "BkdrRegPathRtl"); + range_perm[15].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_15_execute_access_15.q", + 12, 4, 0, "BkdrRegPathRtl"); + range_perm[15].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_15_log_denied_access_15.q", + 16, 4, 0, "BkdrRegPathRtl"); + + range_perm[16] = + (ac_range_check_reg_range_perm:: + type_id::create("range_perm_16")); + range_perm[16].configure(.blk_parent(this)); + range_perm[16].build(csr_excl); + default_map.add_reg(.rg(range_perm[16]), + .offset(32'h1dc)); + range_perm[16].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_16_enable_16.q", + 0, 4, 0, "BkdrRegPathRtl"); + range_perm[16].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_16_read_access_16.q", + 4, 4, 0, "BkdrRegPathRtl"); + range_perm[16].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_16_write_access_16.q", + 8, 4, 0, "BkdrRegPathRtl"); + range_perm[16].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_16_execute_access_16.q", + 12, 4, 0, "BkdrRegPathRtl"); + range_perm[16].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_16_log_denied_access_16.q", + 16, 4, 0, "BkdrRegPathRtl"); + + range_perm[17] = + (ac_range_check_reg_range_perm:: + type_id::create("range_perm_17")); + range_perm[17].configure(.blk_parent(this)); + range_perm[17].build(csr_excl); + default_map.add_reg(.rg(range_perm[17]), + .offset(32'h1e0)); + range_perm[17].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_17_enable_17.q", + 0, 4, 0, "BkdrRegPathRtl"); + range_perm[17].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_17_read_access_17.q", + 4, 4, 0, "BkdrRegPathRtl"); + range_perm[17].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_17_write_access_17.q", + 8, 4, 0, "BkdrRegPathRtl"); + range_perm[17].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_17_execute_access_17.q", + 12, 4, 0, "BkdrRegPathRtl"); + range_perm[17].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_17_log_denied_access_17.q", + 16, 4, 0, "BkdrRegPathRtl"); + + range_perm[18] = + (ac_range_check_reg_range_perm:: + type_id::create("range_perm_18")); + range_perm[18].configure(.blk_parent(this)); + range_perm[18].build(csr_excl); + default_map.add_reg(.rg(range_perm[18]), + .offset(32'h1e4)); + range_perm[18].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_18_enable_18.q", + 0, 4, 0, "BkdrRegPathRtl"); + range_perm[18].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_18_read_access_18.q", + 4, 4, 0, "BkdrRegPathRtl"); + range_perm[18].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_18_write_access_18.q", + 8, 4, 0, "BkdrRegPathRtl"); + range_perm[18].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_18_execute_access_18.q", + 12, 4, 0, "BkdrRegPathRtl"); + range_perm[18].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_18_log_denied_access_18.q", + 16, 4, 0, "BkdrRegPathRtl"); + + range_perm[19] = + (ac_range_check_reg_range_perm:: + type_id::create("range_perm_19")); + range_perm[19].configure(.blk_parent(this)); + range_perm[19].build(csr_excl); + default_map.add_reg(.rg(range_perm[19]), + .offset(32'h1e8)); + range_perm[19].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_19_enable_19.q", + 0, 4, 0, "BkdrRegPathRtl"); + range_perm[19].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_19_read_access_19.q", + 4, 4, 0, "BkdrRegPathRtl"); + range_perm[19].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_19_write_access_19.q", + 8, 4, 0, "BkdrRegPathRtl"); + range_perm[19].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_19_execute_access_19.q", + 12, 4, 0, "BkdrRegPathRtl"); + range_perm[19].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_19_log_denied_access_19.q", + 16, 4, 0, "BkdrRegPathRtl"); + + range_perm[20] = + (ac_range_check_reg_range_perm:: + type_id::create("range_perm_20")); + range_perm[20].configure(.blk_parent(this)); + range_perm[20].build(csr_excl); + default_map.add_reg(.rg(range_perm[20]), + .offset(32'h1ec)); + range_perm[20].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_20_enable_20.q", + 0, 4, 0, "BkdrRegPathRtl"); + range_perm[20].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_20_read_access_20.q", + 4, 4, 0, "BkdrRegPathRtl"); + range_perm[20].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_20_write_access_20.q", + 8, 4, 0, "BkdrRegPathRtl"); + range_perm[20].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_20_execute_access_20.q", + 12, 4, 0, "BkdrRegPathRtl"); + range_perm[20].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_20_log_denied_access_20.q", + 16, 4, 0, "BkdrRegPathRtl"); + + range_perm[21] = + (ac_range_check_reg_range_perm:: + type_id::create("range_perm_21")); + range_perm[21].configure(.blk_parent(this)); + range_perm[21].build(csr_excl); + default_map.add_reg(.rg(range_perm[21]), + .offset(32'h1f0)); + range_perm[21].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_21_enable_21.q", + 0, 4, 0, "BkdrRegPathRtl"); + range_perm[21].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_21_read_access_21.q", + 4, 4, 0, "BkdrRegPathRtl"); + range_perm[21].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_21_write_access_21.q", + 8, 4, 0, "BkdrRegPathRtl"); + range_perm[21].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_21_execute_access_21.q", + 12, 4, 0, "BkdrRegPathRtl"); + range_perm[21].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_21_log_denied_access_21.q", + 16, 4, 0, "BkdrRegPathRtl"); + + range_perm[22] = + (ac_range_check_reg_range_perm:: + type_id::create("range_perm_22")); + range_perm[22].configure(.blk_parent(this)); + range_perm[22].build(csr_excl); + default_map.add_reg(.rg(range_perm[22]), + .offset(32'h1f4)); + range_perm[22].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_22_enable_22.q", + 0, 4, 0, "BkdrRegPathRtl"); + range_perm[22].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_22_read_access_22.q", + 4, 4, 0, "BkdrRegPathRtl"); + range_perm[22].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_22_write_access_22.q", + 8, 4, 0, "BkdrRegPathRtl"); + range_perm[22].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_22_execute_access_22.q", + 12, 4, 0, "BkdrRegPathRtl"); + range_perm[22].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_22_log_denied_access_22.q", + 16, 4, 0, "BkdrRegPathRtl"); + + range_perm[23] = + (ac_range_check_reg_range_perm:: + type_id::create("range_perm_23")); + range_perm[23].configure(.blk_parent(this)); + range_perm[23].build(csr_excl); + default_map.add_reg(.rg(range_perm[23]), + .offset(32'h1f8)); + range_perm[23].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_23_enable_23.q", + 0, 4, 0, "BkdrRegPathRtl"); + range_perm[23].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_23_read_access_23.q", + 4, 4, 0, "BkdrRegPathRtl"); + range_perm[23].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_23_write_access_23.q", + 8, 4, 0, "BkdrRegPathRtl"); + range_perm[23].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_23_execute_access_23.q", + 12, 4, 0, "BkdrRegPathRtl"); + range_perm[23].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_23_log_denied_access_23.q", + 16, 4, 0, "BkdrRegPathRtl"); + + range_perm[24] = + (ac_range_check_reg_range_perm:: + type_id::create("range_perm_24")); + range_perm[24].configure(.blk_parent(this)); + range_perm[24].build(csr_excl); + default_map.add_reg(.rg(range_perm[24]), + .offset(32'h1fc)); + range_perm[24].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_24_enable_24.q", + 0, 4, 0, "BkdrRegPathRtl"); + range_perm[24].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_24_read_access_24.q", + 4, 4, 0, "BkdrRegPathRtl"); + range_perm[24].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_24_write_access_24.q", + 8, 4, 0, "BkdrRegPathRtl"); + range_perm[24].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_24_execute_access_24.q", + 12, 4, 0, "BkdrRegPathRtl"); + range_perm[24].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_24_log_denied_access_24.q", + 16, 4, 0, "BkdrRegPathRtl"); + + range_perm[25] = + (ac_range_check_reg_range_perm:: + type_id::create("range_perm_25")); + range_perm[25].configure(.blk_parent(this)); + range_perm[25].build(csr_excl); + default_map.add_reg(.rg(range_perm[25]), + .offset(32'h200)); + range_perm[25].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_25_enable_25.q", + 0, 4, 0, "BkdrRegPathRtl"); + range_perm[25].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_25_read_access_25.q", + 4, 4, 0, "BkdrRegPathRtl"); + range_perm[25].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_25_write_access_25.q", + 8, 4, 0, "BkdrRegPathRtl"); + range_perm[25].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_25_execute_access_25.q", + 12, 4, 0, "BkdrRegPathRtl"); + range_perm[25].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_25_log_denied_access_25.q", + 16, 4, 0, "BkdrRegPathRtl"); + + range_perm[26] = + (ac_range_check_reg_range_perm:: + type_id::create("range_perm_26")); + range_perm[26].configure(.blk_parent(this)); + range_perm[26].build(csr_excl); + default_map.add_reg(.rg(range_perm[26]), + .offset(32'h204)); + range_perm[26].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_26_enable_26.q", + 0, 4, 0, "BkdrRegPathRtl"); + range_perm[26].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_26_read_access_26.q", + 4, 4, 0, "BkdrRegPathRtl"); + range_perm[26].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_26_write_access_26.q", + 8, 4, 0, "BkdrRegPathRtl"); + range_perm[26].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_26_execute_access_26.q", + 12, 4, 0, "BkdrRegPathRtl"); + range_perm[26].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_26_log_denied_access_26.q", + 16, 4, 0, "BkdrRegPathRtl"); + + range_perm[27] = + (ac_range_check_reg_range_perm:: + type_id::create("range_perm_27")); + range_perm[27].configure(.blk_parent(this)); + range_perm[27].build(csr_excl); + default_map.add_reg(.rg(range_perm[27]), + .offset(32'h208)); + range_perm[27].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_27_enable_27.q", + 0, 4, 0, "BkdrRegPathRtl"); + range_perm[27].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_27_read_access_27.q", + 4, 4, 0, "BkdrRegPathRtl"); + range_perm[27].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_27_write_access_27.q", + 8, 4, 0, "BkdrRegPathRtl"); + range_perm[27].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_27_execute_access_27.q", + 12, 4, 0, "BkdrRegPathRtl"); + range_perm[27].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_27_log_denied_access_27.q", + 16, 4, 0, "BkdrRegPathRtl"); + + range_perm[28] = + (ac_range_check_reg_range_perm:: + type_id::create("range_perm_28")); + range_perm[28].configure(.blk_parent(this)); + range_perm[28].build(csr_excl); + default_map.add_reg(.rg(range_perm[28]), + .offset(32'h20c)); + range_perm[28].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_28_enable_28.q", + 0, 4, 0, "BkdrRegPathRtl"); + range_perm[28].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_28_read_access_28.q", + 4, 4, 0, "BkdrRegPathRtl"); + range_perm[28].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_28_write_access_28.q", + 8, 4, 0, "BkdrRegPathRtl"); + range_perm[28].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_28_execute_access_28.q", + 12, 4, 0, "BkdrRegPathRtl"); + range_perm[28].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_28_log_denied_access_28.q", + 16, 4, 0, "BkdrRegPathRtl"); + + range_perm[29] = + (ac_range_check_reg_range_perm:: + type_id::create("range_perm_29")); + range_perm[29].configure(.blk_parent(this)); + range_perm[29].build(csr_excl); + default_map.add_reg(.rg(range_perm[29]), + .offset(32'h210)); + range_perm[29].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_29_enable_29.q", + 0, 4, 0, "BkdrRegPathRtl"); + range_perm[29].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_29_read_access_29.q", + 4, 4, 0, "BkdrRegPathRtl"); + range_perm[29].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_29_write_access_29.q", + 8, 4, 0, "BkdrRegPathRtl"); + range_perm[29].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_29_execute_access_29.q", + 12, 4, 0, "BkdrRegPathRtl"); + range_perm[29].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_29_log_denied_access_29.q", + 16, 4, 0, "BkdrRegPathRtl"); + + range_perm[30] = + (ac_range_check_reg_range_perm:: + type_id::create("range_perm_30")); + range_perm[30].configure(.blk_parent(this)); + range_perm[30].build(csr_excl); + default_map.add_reg(.rg(range_perm[30]), + .offset(32'h214)); + range_perm[30].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_30_enable_30.q", + 0, 4, 0, "BkdrRegPathRtl"); + range_perm[30].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_30_read_access_30.q", + 4, 4, 0, "BkdrRegPathRtl"); + range_perm[30].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_30_write_access_30.q", + 8, 4, 0, "BkdrRegPathRtl"); + range_perm[30].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_30_execute_access_30.q", + 12, 4, 0, "BkdrRegPathRtl"); + range_perm[30].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_30_log_denied_access_30.q", + 16, 4, 0, "BkdrRegPathRtl"); + + range_perm[31] = + (ac_range_check_reg_range_perm:: + type_id::create("range_perm_31")); + range_perm[31].configure(.blk_parent(this)); + range_perm[31].build(csr_excl); + default_map.add_reg(.rg(range_perm[31]), + .offset(32'h218)); + range_perm[31].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_31_enable_31.q", + 0, 4, 0, "BkdrRegPathRtl"); + range_perm[31].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_31_read_access_31.q", + 4, 4, 0, "BkdrRegPathRtl"); + range_perm[31].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_31_write_access_31.q", + 8, 4, 0, "BkdrRegPathRtl"); + range_perm[31].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_31_execute_access_31.q", + 12, 4, 0, "BkdrRegPathRtl"); + range_perm[31].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_31_log_denied_access_31.q", + 16, 4, 0, "BkdrRegPathRtl"); + + range_racl_policy_shadowed[0] = + (ac_range_check_reg_range_racl_policy_shadowed:: + type_id::create("range_racl_policy_shadowed_0")); + range_racl_policy_shadowed[0].configure(.blk_parent(this)); + range_racl_policy_shadowed[0].build(csr_excl); + default_map.add_reg(.rg(range_racl_policy_shadowed[0]), + .offset(32'h21c)); + range_racl_policy_shadowed[0].add_update_err_alert("recov_ctrl_update_err"); + + range_racl_policy_shadowed[0].add_storage_err_alert("fatal_fault"); + + range_racl_policy_shadowed[0].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_0_read_perm_0.committed_reg.q", + 0, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[0].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_0_read_perm_0.shadow_reg.q", + 0, 16, 0, "BkdrRegPathRtlShadow"); + range_racl_policy_shadowed[0].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_0_write_perm_0.committed_reg.q", + 16, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[0].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_0_write_perm_0.shadow_reg.q", + 16, 16, 0, "BkdrRegPathRtlShadow"); + + range_racl_policy_shadowed[0].set_is_shadowed(); + range_racl_policy_shadowed[1] = + (ac_range_check_reg_range_racl_policy_shadowed:: + type_id::create("range_racl_policy_shadowed_1")); + range_racl_policy_shadowed[1].configure(.blk_parent(this)); + range_racl_policy_shadowed[1].build(csr_excl); + default_map.add_reg(.rg(range_racl_policy_shadowed[1]), + .offset(32'h220)); + range_racl_policy_shadowed[1].add_update_err_alert("recov_ctrl_update_err"); + + range_racl_policy_shadowed[1].add_storage_err_alert("fatal_fault"); + + range_racl_policy_shadowed[1].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_1_read_perm_1.committed_reg.q", + 0, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[1].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_1_read_perm_1.shadow_reg.q", + 0, 16, 0, "BkdrRegPathRtlShadow"); + range_racl_policy_shadowed[1].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_1_write_perm_1.committed_reg.q", + 16, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[1].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_1_write_perm_1.shadow_reg.q", + 16, 16, 0, "BkdrRegPathRtlShadow"); + + range_racl_policy_shadowed[1].set_is_shadowed(); + range_racl_policy_shadowed[2] = + (ac_range_check_reg_range_racl_policy_shadowed:: + type_id::create("range_racl_policy_shadowed_2")); + range_racl_policy_shadowed[2].configure(.blk_parent(this)); + range_racl_policy_shadowed[2].build(csr_excl); + default_map.add_reg(.rg(range_racl_policy_shadowed[2]), + .offset(32'h224)); + range_racl_policy_shadowed[2].add_update_err_alert("recov_ctrl_update_err"); + + range_racl_policy_shadowed[2].add_storage_err_alert("fatal_fault"); + + range_racl_policy_shadowed[2].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_2_read_perm_2.committed_reg.q", + 0, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[2].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_2_read_perm_2.shadow_reg.q", + 0, 16, 0, "BkdrRegPathRtlShadow"); + range_racl_policy_shadowed[2].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_2_write_perm_2.committed_reg.q", + 16, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[2].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_2_write_perm_2.shadow_reg.q", + 16, 16, 0, "BkdrRegPathRtlShadow"); + + range_racl_policy_shadowed[2].set_is_shadowed(); + range_racl_policy_shadowed[3] = + (ac_range_check_reg_range_racl_policy_shadowed:: + type_id::create("range_racl_policy_shadowed_3")); + range_racl_policy_shadowed[3].configure(.blk_parent(this)); + range_racl_policy_shadowed[3].build(csr_excl); + default_map.add_reg(.rg(range_racl_policy_shadowed[3]), + .offset(32'h228)); + range_racl_policy_shadowed[3].add_update_err_alert("recov_ctrl_update_err"); + + range_racl_policy_shadowed[3].add_storage_err_alert("fatal_fault"); + + range_racl_policy_shadowed[3].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_3_read_perm_3.committed_reg.q", + 0, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[3].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_3_read_perm_3.shadow_reg.q", + 0, 16, 0, "BkdrRegPathRtlShadow"); + range_racl_policy_shadowed[3].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_3_write_perm_3.committed_reg.q", + 16, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[3].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_3_write_perm_3.shadow_reg.q", + 16, 16, 0, "BkdrRegPathRtlShadow"); + + range_racl_policy_shadowed[3].set_is_shadowed(); + range_racl_policy_shadowed[4] = + (ac_range_check_reg_range_racl_policy_shadowed:: + type_id::create("range_racl_policy_shadowed_4")); + range_racl_policy_shadowed[4].configure(.blk_parent(this)); + range_racl_policy_shadowed[4].build(csr_excl); + default_map.add_reg(.rg(range_racl_policy_shadowed[4]), + .offset(32'h22c)); + range_racl_policy_shadowed[4].add_update_err_alert("recov_ctrl_update_err"); + + range_racl_policy_shadowed[4].add_storage_err_alert("fatal_fault"); + + range_racl_policy_shadowed[4].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_4_read_perm_4.committed_reg.q", + 0, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[4].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_4_read_perm_4.shadow_reg.q", + 0, 16, 0, "BkdrRegPathRtlShadow"); + range_racl_policy_shadowed[4].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_4_write_perm_4.committed_reg.q", + 16, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[4].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_4_write_perm_4.shadow_reg.q", + 16, 16, 0, "BkdrRegPathRtlShadow"); + + range_racl_policy_shadowed[4].set_is_shadowed(); + range_racl_policy_shadowed[5] = + (ac_range_check_reg_range_racl_policy_shadowed:: + type_id::create("range_racl_policy_shadowed_5")); + range_racl_policy_shadowed[5].configure(.blk_parent(this)); + range_racl_policy_shadowed[5].build(csr_excl); + default_map.add_reg(.rg(range_racl_policy_shadowed[5]), + .offset(32'h230)); + range_racl_policy_shadowed[5].add_update_err_alert("recov_ctrl_update_err"); + + range_racl_policy_shadowed[5].add_storage_err_alert("fatal_fault"); + + range_racl_policy_shadowed[5].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_5_read_perm_5.committed_reg.q", + 0, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[5].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_5_read_perm_5.shadow_reg.q", + 0, 16, 0, "BkdrRegPathRtlShadow"); + range_racl_policy_shadowed[5].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_5_write_perm_5.committed_reg.q", + 16, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[5].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_5_write_perm_5.shadow_reg.q", + 16, 16, 0, "BkdrRegPathRtlShadow"); + + range_racl_policy_shadowed[5].set_is_shadowed(); + range_racl_policy_shadowed[6] = + (ac_range_check_reg_range_racl_policy_shadowed:: + type_id::create("range_racl_policy_shadowed_6")); + range_racl_policy_shadowed[6].configure(.blk_parent(this)); + range_racl_policy_shadowed[6].build(csr_excl); + default_map.add_reg(.rg(range_racl_policy_shadowed[6]), + .offset(32'h234)); + range_racl_policy_shadowed[6].add_update_err_alert("recov_ctrl_update_err"); + + range_racl_policy_shadowed[6].add_storage_err_alert("fatal_fault"); + + range_racl_policy_shadowed[6].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_6_read_perm_6.committed_reg.q", + 0, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[6].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_6_read_perm_6.shadow_reg.q", + 0, 16, 0, "BkdrRegPathRtlShadow"); + range_racl_policy_shadowed[6].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_6_write_perm_6.committed_reg.q", + 16, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[6].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_6_write_perm_6.shadow_reg.q", + 16, 16, 0, "BkdrRegPathRtlShadow"); + + range_racl_policy_shadowed[6].set_is_shadowed(); + range_racl_policy_shadowed[7] = + (ac_range_check_reg_range_racl_policy_shadowed:: + type_id::create("range_racl_policy_shadowed_7")); + range_racl_policy_shadowed[7].configure(.blk_parent(this)); + range_racl_policy_shadowed[7].build(csr_excl); + default_map.add_reg(.rg(range_racl_policy_shadowed[7]), + .offset(32'h238)); + range_racl_policy_shadowed[7].add_update_err_alert("recov_ctrl_update_err"); + + range_racl_policy_shadowed[7].add_storage_err_alert("fatal_fault"); + + range_racl_policy_shadowed[7].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_7_read_perm_7.committed_reg.q", + 0, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[7].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_7_read_perm_7.shadow_reg.q", + 0, 16, 0, "BkdrRegPathRtlShadow"); + range_racl_policy_shadowed[7].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_7_write_perm_7.committed_reg.q", + 16, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[7].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_7_write_perm_7.shadow_reg.q", + 16, 16, 0, "BkdrRegPathRtlShadow"); + + range_racl_policy_shadowed[7].set_is_shadowed(); + range_racl_policy_shadowed[8] = + (ac_range_check_reg_range_racl_policy_shadowed:: + type_id::create("range_racl_policy_shadowed_8")); + range_racl_policy_shadowed[8].configure(.blk_parent(this)); + range_racl_policy_shadowed[8].build(csr_excl); + default_map.add_reg(.rg(range_racl_policy_shadowed[8]), + .offset(32'h23c)); + range_racl_policy_shadowed[8].add_update_err_alert("recov_ctrl_update_err"); + + range_racl_policy_shadowed[8].add_storage_err_alert("fatal_fault"); + + range_racl_policy_shadowed[8].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_8_read_perm_8.committed_reg.q", + 0, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[8].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_8_read_perm_8.shadow_reg.q", + 0, 16, 0, "BkdrRegPathRtlShadow"); + range_racl_policy_shadowed[8].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_8_write_perm_8.committed_reg.q", + 16, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[8].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_8_write_perm_8.shadow_reg.q", + 16, 16, 0, "BkdrRegPathRtlShadow"); + + range_racl_policy_shadowed[8].set_is_shadowed(); + range_racl_policy_shadowed[9] = + (ac_range_check_reg_range_racl_policy_shadowed:: + type_id::create("range_racl_policy_shadowed_9")); + range_racl_policy_shadowed[9].configure(.blk_parent(this)); + range_racl_policy_shadowed[9].build(csr_excl); + default_map.add_reg(.rg(range_racl_policy_shadowed[9]), + .offset(32'h240)); + range_racl_policy_shadowed[9].add_update_err_alert("recov_ctrl_update_err"); + + range_racl_policy_shadowed[9].add_storage_err_alert("fatal_fault"); + + range_racl_policy_shadowed[9].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_9_read_perm_9.committed_reg.q", + 0, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[9].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_9_read_perm_9.shadow_reg.q", + 0, 16, 0, "BkdrRegPathRtlShadow"); + range_racl_policy_shadowed[9].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_9_write_perm_9.committed_reg.q", + 16, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[9].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_9_write_perm_9.shadow_reg.q", + 16, 16, 0, "BkdrRegPathRtlShadow"); + + range_racl_policy_shadowed[9].set_is_shadowed(); + range_racl_policy_shadowed[10] = + (ac_range_check_reg_range_racl_policy_shadowed:: + type_id::create("range_racl_policy_shadowed_10")); + range_racl_policy_shadowed[10].configure(.blk_parent(this)); + range_racl_policy_shadowed[10].build(csr_excl); + default_map.add_reg(.rg(range_racl_policy_shadowed[10]), + .offset(32'h244)); + range_racl_policy_shadowed[10].add_update_err_alert("recov_ctrl_update_err"); + + range_racl_policy_shadowed[10].add_storage_err_alert("fatal_fault"); + + range_racl_policy_shadowed[10].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_10_read_perm_10.committed_reg.q", + 0, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[10].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_10_read_perm_10.shadow_reg.q", + 0, 16, 0, "BkdrRegPathRtlShadow"); + range_racl_policy_shadowed[10].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_10_write_perm_10.committed_reg.q", + 16, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[10].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_10_write_perm_10.shadow_reg.q", + 16, 16, 0, "BkdrRegPathRtlShadow"); + + range_racl_policy_shadowed[10].set_is_shadowed(); + range_racl_policy_shadowed[11] = + (ac_range_check_reg_range_racl_policy_shadowed:: + type_id::create("range_racl_policy_shadowed_11")); + range_racl_policy_shadowed[11].configure(.blk_parent(this)); + range_racl_policy_shadowed[11].build(csr_excl); + default_map.add_reg(.rg(range_racl_policy_shadowed[11]), + .offset(32'h248)); + range_racl_policy_shadowed[11].add_update_err_alert("recov_ctrl_update_err"); + + range_racl_policy_shadowed[11].add_storage_err_alert("fatal_fault"); + + range_racl_policy_shadowed[11].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_11_read_perm_11.committed_reg.q", + 0, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[11].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_11_read_perm_11.shadow_reg.q", + 0, 16, 0, "BkdrRegPathRtlShadow"); + range_racl_policy_shadowed[11].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_11_write_perm_11.committed_reg.q", + 16, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[11].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_11_write_perm_11.shadow_reg.q", + 16, 16, 0, "BkdrRegPathRtlShadow"); + + range_racl_policy_shadowed[11].set_is_shadowed(); + range_racl_policy_shadowed[12] = + (ac_range_check_reg_range_racl_policy_shadowed:: + type_id::create("range_racl_policy_shadowed_12")); + range_racl_policy_shadowed[12].configure(.blk_parent(this)); + range_racl_policy_shadowed[12].build(csr_excl); + default_map.add_reg(.rg(range_racl_policy_shadowed[12]), + .offset(32'h24c)); + range_racl_policy_shadowed[12].add_update_err_alert("recov_ctrl_update_err"); + + range_racl_policy_shadowed[12].add_storage_err_alert("fatal_fault"); + + range_racl_policy_shadowed[12].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_12_read_perm_12.committed_reg.q", + 0, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[12].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_12_read_perm_12.shadow_reg.q", + 0, 16, 0, "BkdrRegPathRtlShadow"); + range_racl_policy_shadowed[12].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_12_write_perm_12.committed_reg.q", + 16, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[12].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_12_write_perm_12.shadow_reg.q", + 16, 16, 0, "BkdrRegPathRtlShadow"); + + range_racl_policy_shadowed[12].set_is_shadowed(); + range_racl_policy_shadowed[13] = + (ac_range_check_reg_range_racl_policy_shadowed:: + type_id::create("range_racl_policy_shadowed_13")); + range_racl_policy_shadowed[13].configure(.blk_parent(this)); + range_racl_policy_shadowed[13].build(csr_excl); + default_map.add_reg(.rg(range_racl_policy_shadowed[13]), + .offset(32'h250)); + range_racl_policy_shadowed[13].add_update_err_alert("recov_ctrl_update_err"); + + range_racl_policy_shadowed[13].add_storage_err_alert("fatal_fault"); + + range_racl_policy_shadowed[13].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_13_read_perm_13.committed_reg.q", + 0, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[13].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_13_read_perm_13.shadow_reg.q", + 0, 16, 0, "BkdrRegPathRtlShadow"); + range_racl_policy_shadowed[13].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_13_write_perm_13.committed_reg.q", + 16, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[13].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_13_write_perm_13.shadow_reg.q", + 16, 16, 0, "BkdrRegPathRtlShadow"); + + range_racl_policy_shadowed[13].set_is_shadowed(); + range_racl_policy_shadowed[14] = + (ac_range_check_reg_range_racl_policy_shadowed:: + type_id::create("range_racl_policy_shadowed_14")); + range_racl_policy_shadowed[14].configure(.blk_parent(this)); + range_racl_policy_shadowed[14].build(csr_excl); + default_map.add_reg(.rg(range_racl_policy_shadowed[14]), + .offset(32'h254)); + range_racl_policy_shadowed[14].add_update_err_alert("recov_ctrl_update_err"); + + range_racl_policy_shadowed[14].add_storage_err_alert("fatal_fault"); + + range_racl_policy_shadowed[14].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_14_read_perm_14.committed_reg.q", + 0, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[14].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_14_read_perm_14.shadow_reg.q", + 0, 16, 0, "BkdrRegPathRtlShadow"); + range_racl_policy_shadowed[14].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_14_write_perm_14.committed_reg.q", + 16, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[14].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_14_write_perm_14.shadow_reg.q", + 16, 16, 0, "BkdrRegPathRtlShadow"); + + range_racl_policy_shadowed[14].set_is_shadowed(); + range_racl_policy_shadowed[15] = + (ac_range_check_reg_range_racl_policy_shadowed:: + type_id::create("range_racl_policy_shadowed_15")); + range_racl_policy_shadowed[15].configure(.blk_parent(this)); + range_racl_policy_shadowed[15].build(csr_excl); + default_map.add_reg(.rg(range_racl_policy_shadowed[15]), + .offset(32'h258)); + range_racl_policy_shadowed[15].add_update_err_alert("recov_ctrl_update_err"); + + range_racl_policy_shadowed[15].add_storage_err_alert("fatal_fault"); + + range_racl_policy_shadowed[15].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_15_read_perm_15.committed_reg.q", + 0, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[15].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_15_read_perm_15.shadow_reg.q", + 0, 16, 0, "BkdrRegPathRtlShadow"); + range_racl_policy_shadowed[15].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_15_write_perm_15.committed_reg.q", + 16, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[15].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_15_write_perm_15.shadow_reg.q", + 16, 16, 0, "BkdrRegPathRtlShadow"); + + range_racl_policy_shadowed[15].set_is_shadowed(); + range_racl_policy_shadowed[16] = + (ac_range_check_reg_range_racl_policy_shadowed:: + type_id::create("range_racl_policy_shadowed_16")); + range_racl_policy_shadowed[16].configure(.blk_parent(this)); + range_racl_policy_shadowed[16].build(csr_excl); + default_map.add_reg(.rg(range_racl_policy_shadowed[16]), + .offset(32'h25c)); + range_racl_policy_shadowed[16].add_update_err_alert("recov_ctrl_update_err"); + + range_racl_policy_shadowed[16].add_storage_err_alert("fatal_fault"); + + range_racl_policy_shadowed[16].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_16_read_perm_16.committed_reg.q", + 0, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[16].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_16_read_perm_16.shadow_reg.q", + 0, 16, 0, "BkdrRegPathRtlShadow"); + range_racl_policy_shadowed[16].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_16_write_perm_16.committed_reg.q", + 16, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[16].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_16_write_perm_16.shadow_reg.q", + 16, 16, 0, "BkdrRegPathRtlShadow"); + + range_racl_policy_shadowed[16].set_is_shadowed(); + range_racl_policy_shadowed[17] = + (ac_range_check_reg_range_racl_policy_shadowed:: + type_id::create("range_racl_policy_shadowed_17")); + range_racl_policy_shadowed[17].configure(.blk_parent(this)); + range_racl_policy_shadowed[17].build(csr_excl); + default_map.add_reg(.rg(range_racl_policy_shadowed[17]), + .offset(32'h260)); + range_racl_policy_shadowed[17].add_update_err_alert("recov_ctrl_update_err"); + + range_racl_policy_shadowed[17].add_storage_err_alert("fatal_fault"); + + range_racl_policy_shadowed[17].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_17_read_perm_17.committed_reg.q", + 0, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[17].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_17_read_perm_17.shadow_reg.q", + 0, 16, 0, "BkdrRegPathRtlShadow"); + range_racl_policy_shadowed[17].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_17_write_perm_17.committed_reg.q", + 16, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[17].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_17_write_perm_17.shadow_reg.q", + 16, 16, 0, "BkdrRegPathRtlShadow"); + + range_racl_policy_shadowed[17].set_is_shadowed(); + range_racl_policy_shadowed[18] = + (ac_range_check_reg_range_racl_policy_shadowed:: + type_id::create("range_racl_policy_shadowed_18")); + range_racl_policy_shadowed[18].configure(.blk_parent(this)); + range_racl_policy_shadowed[18].build(csr_excl); + default_map.add_reg(.rg(range_racl_policy_shadowed[18]), + .offset(32'h264)); + range_racl_policy_shadowed[18].add_update_err_alert("recov_ctrl_update_err"); + + range_racl_policy_shadowed[18].add_storage_err_alert("fatal_fault"); + + range_racl_policy_shadowed[18].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_18_read_perm_18.committed_reg.q", + 0, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[18].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_18_read_perm_18.shadow_reg.q", + 0, 16, 0, "BkdrRegPathRtlShadow"); + range_racl_policy_shadowed[18].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_18_write_perm_18.committed_reg.q", + 16, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[18].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_18_write_perm_18.shadow_reg.q", + 16, 16, 0, "BkdrRegPathRtlShadow"); + + range_racl_policy_shadowed[18].set_is_shadowed(); + range_racl_policy_shadowed[19] = + (ac_range_check_reg_range_racl_policy_shadowed:: + type_id::create("range_racl_policy_shadowed_19")); + range_racl_policy_shadowed[19].configure(.blk_parent(this)); + range_racl_policy_shadowed[19].build(csr_excl); + default_map.add_reg(.rg(range_racl_policy_shadowed[19]), + .offset(32'h268)); + range_racl_policy_shadowed[19].add_update_err_alert("recov_ctrl_update_err"); + + range_racl_policy_shadowed[19].add_storage_err_alert("fatal_fault"); + + range_racl_policy_shadowed[19].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_19_read_perm_19.committed_reg.q", + 0, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[19].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_19_read_perm_19.shadow_reg.q", + 0, 16, 0, "BkdrRegPathRtlShadow"); + range_racl_policy_shadowed[19].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_19_write_perm_19.committed_reg.q", + 16, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[19].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_19_write_perm_19.shadow_reg.q", + 16, 16, 0, "BkdrRegPathRtlShadow"); + + range_racl_policy_shadowed[19].set_is_shadowed(); + range_racl_policy_shadowed[20] = + (ac_range_check_reg_range_racl_policy_shadowed:: + type_id::create("range_racl_policy_shadowed_20")); + range_racl_policy_shadowed[20].configure(.blk_parent(this)); + range_racl_policy_shadowed[20].build(csr_excl); + default_map.add_reg(.rg(range_racl_policy_shadowed[20]), + .offset(32'h26c)); + range_racl_policy_shadowed[20].add_update_err_alert("recov_ctrl_update_err"); + + range_racl_policy_shadowed[20].add_storage_err_alert("fatal_fault"); + + range_racl_policy_shadowed[20].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_20_read_perm_20.committed_reg.q", + 0, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[20].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_20_read_perm_20.shadow_reg.q", + 0, 16, 0, "BkdrRegPathRtlShadow"); + range_racl_policy_shadowed[20].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_20_write_perm_20.committed_reg.q", + 16, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[20].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_20_write_perm_20.shadow_reg.q", + 16, 16, 0, "BkdrRegPathRtlShadow"); + + range_racl_policy_shadowed[20].set_is_shadowed(); + range_racl_policy_shadowed[21] = + (ac_range_check_reg_range_racl_policy_shadowed:: + type_id::create("range_racl_policy_shadowed_21")); + range_racl_policy_shadowed[21].configure(.blk_parent(this)); + range_racl_policy_shadowed[21].build(csr_excl); + default_map.add_reg(.rg(range_racl_policy_shadowed[21]), + .offset(32'h270)); + range_racl_policy_shadowed[21].add_update_err_alert("recov_ctrl_update_err"); + + range_racl_policy_shadowed[21].add_storage_err_alert("fatal_fault"); + + range_racl_policy_shadowed[21].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_21_read_perm_21.committed_reg.q", + 0, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[21].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_21_read_perm_21.shadow_reg.q", + 0, 16, 0, "BkdrRegPathRtlShadow"); + range_racl_policy_shadowed[21].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_21_write_perm_21.committed_reg.q", + 16, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[21].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_21_write_perm_21.shadow_reg.q", + 16, 16, 0, "BkdrRegPathRtlShadow"); + + range_racl_policy_shadowed[21].set_is_shadowed(); + range_racl_policy_shadowed[22] = + (ac_range_check_reg_range_racl_policy_shadowed:: + type_id::create("range_racl_policy_shadowed_22")); + range_racl_policy_shadowed[22].configure(.blk_parent(this)); + range_racl_policy_shadowed[22].build(csr_excl); + default_map.add_reg(.rg(range_racl_policy_shadowed[22]), + .offset(32'h274)); + range_racl_policy_shadowed[22].add_update_err_alert("recov_ctrl_update_err"); + + range_racl_policy_shadowed[22].add_storage_err_alert("fatal_fault"); + + range_racl_policy_shadowed[22].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_22_read_perm_22.committed_reg.q", + 0, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[22].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_22_read_perm_22.shadow_reg.q", + 0, 16, 0, "BkdrRegPathRtlShadow"); + range_racl_policy_shadowed[22].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_22_write_perm_22.committed_reg.q", + 16, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[22].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_22_write_perm_22.shadow_reg.q", + 16, 16, 0, "BkdrRegPathRtlShadow"); + + range_racl_policy_shadowed[22].set_is_shadowed(); + range_racl_policy_shadowed[23] = + (ac_range_check_reg_range_racl_policy_shadowed:: + type_id::create("range_racl_policy_shadowed_23")); + range_racl_policy_shadowed[23].configure(.blk_parent(this)); + range_racl_policy_shadowed[23].build(csr_excl); + default_map.add_reg(.rg(range_racl_policy_shadowed[23]), + .offset(32'h278)); + range_racl_policy_shadowed[23].add_update_err_alert("recov_ctrl_update_err"); + + range_racl_policy_shadowed[23].add_storage_err_alert("fatal_fault"); + + range_racl_policy_shadowed[23].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_23_read_perm_23.committed_reg.q", + 0, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[23].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_23_read_perm_23.shadow_reg.q", + 0, 16, 0, "BkdrRegPathRtlShadow"); + range_racl_policy_shadowed[23].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_23_write_perm_23.committed_reg.q", + 16, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[23].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_23_write_perm_23.shadow_reg.q", + 16, 16, 0, "BkdrRegPathRtlShadow"); + + range_racl_policy_shadowed[23].set_is_shadowed(); + range_racl_policy_shadowed[24] = + (ac_range_check_reg_range_racl_policy_shadowed:: + type_id::create("range_racl_policy_shadowed_24")); + range_racl_policy_shadowed[24].configure(.blk_parent(this)); + range_racl_policy_shadowed[24].build(csr_excl); + default_map.add_reg(.rg(range_racl_policy_shadowed[24]), + .offset(32'h27c)); + range_racl_policy_shadowed[24].add_update_err_alert("recov_ctrl_update_err"); + + range_racl_policy_shadowed[24].add_storage_err_alert("fatal_fault"); + + range_racl_policy_shadowed[24].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_24_read_perm_24.committed_reg.q", + 0, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[24].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_24_read_perm_24.shadow_reg.q", + 0, 16, 0, "BkdrRegPathRtlShadow"); + range_racl_policy_shadowed[24].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_24_write_perm_24.committed_reg.q", + 16, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[24].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_24_write_perm_24.shadow_reg.q", + 16, 16, 0, "BkdrRegPathRtlShadow"); + + range_racl_policy_shadowed[24].set_is_shadowed(); + range_racl_policy_shadowed[25] = + (ac_range_check_reg_range_racl_policy_shadowed:: + type_id::create("range_racl_policy_shadowed_25")); + range_racl_policy_shadowed[25].configure(.blk_parent(this)); + range_racl_policy_shadowed[25].build(csr_excl); + default_map.add_reg(.rg(range_racl_policy_shadowed[25]), + .offset(32'h280)); + range_racl_policy_shadowed[25].add_update_err_alert("recov_ctrl_update_err"); + + range_racl_policy_shadowed[25].add_storage_err_alert("fatal_fault"); + + range_racl_policy_shadowed[25].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_25_read_perm_25.committed_reg.q", + 0, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[25].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_25_read_perm_25.shadow_reg.q", + 0, 16, 0, "BkdrRegPathRtlShadow"); + range_racl_policy_shadowed[25].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_25_write_perm_25.committed_reg.q", + 16, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[25].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_25_write_perm_25.shadow_reg.q", + 16, 16, 0, "BkdrRegPathRtlShadow"); + + range_racl_policy_shadowed[25].set_is_shadowed(); + range_racl_policy_shadowed[26] = + (ac_range_check_reg_range_racl_policy_shadowed:: + type_id::create("range_racl_policy_shadowed_26")); + range_racl_policy_shadowed[26].configure(.blk_parent(this)); + range_racl_policy_shadowed[26].build(csr_excl); + default_map.add_reg(.rg(range_racl_policy_shadowed[26]), + .offset(32'h284)); + range_racl_policy_shadowed[26].add_update_err_alert("recov_ctrl_update_err"); + + range_racl_policy_shadowed[26].add_storage_err_alert("fatal_fault"); + + range_racl_policy_shadowed[26].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_26_read_perm_26.committed_reg.q", + 0, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[26].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_26_read_perm_26.shadow_reg.q", + 0, 16, 0, "BkdrRegPathRtlShadow"); + range_racl_policy_shadowed[26].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_26_write_perm_26.committed_reg.q", + 16, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[26].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_26_write_perm_26.shadow_reg.q", + 16, 16, 0, "BkdrRegPathRtlShadow"); + + range_racl_policy_shadowed[26].set_is_shadowed(); + range_racl_policy_shadowed[27] = + (ac_range_check_reg_range_racl_policy_shadowed:: + type_id::create("range_racl_policy_shadowed_27")); + range_racl_policy_shadowed[27].configure(.blk_parent(this)); + range_racl_policy_shadowed[27].build(csr_excl); + default_map.add_reg(.rg(range_racl_policy_shadowed[27]), + .offset(32'h288)); + range_racl_policy_shadowed[27].add_update_err_alert("recov_ctrl_update_err"); + + range_racl_policy_shadowed[27].add_storage_err_alert("fatal_fault"); + + range_racl_policy_shadowed[27].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_27_read_perm_27.committed_reg.q", + 0, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[27].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_27_read_perm_27.shadow_reg.q", + 0, 16, 0, "BkdrRegPathRtlShadow"); + range_racl_policy_shadowed[27].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_27_write_perm_27.committed_reg.q", + 16, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[27].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_27_write_perm_27.shadow_reg.q", + 16, 16, 0, "BkdrRegPathRtlShadow"); + + range_racl_policy_shadowed[27].set_is_shadowed(); + range_racl_policy_shadowed[28] = + (ac_range_check_reg_range_racl_policy_shadowed:: + type_id::create("range_racl_policy_shadowed_28")); + range_racl_policy_shadowed[28].configure(.blk_parent(this)); + range_racl_policy_shadowed[28].build(csr_excl); + default_map.add_reg(.rg(range_racl_policy_shadowed[28]), + .offset(32'h28c)); + range_racl_policy_shadowed[28].add_update_err_alert("recov_ctrl_update_err"); + + range_racl_policy_shadowed[28].add_storage_err_alert("fatal_fault"); + + range_racl_policy_shadowed[28].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_28_read_perm_28.committed_reg.q", + 0, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[28].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_28_read_perm_28.shadow_reg.q", + 0, 16, 0, "BkdrRegPathRtlShadow"); + range_racl_policy_shadowed[28].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_28_write_perm_28.committed_reg.q", + 16, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[28].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_28_write_perm_28.shadow_reg.q", + 16, 16, 0, "BkdrRegPathRtlShadow"); + + range_racl_policy_shadowed[28].set_is_shadowed(); + range_racl_policy_shadowed[29] = + (ac_range_check_reg_range_racl_policy_shadowed:: + type_id::create("range_racl_policy_shadowed_29")); + range_racl_policy_shadowed[29].configure(.blk_parent(this)); + range_racl_policy_shadowed[29].build(csr_excl); + default_map.add_reg(.rg(range_racl_policy_shadowed[29]), + .offset(32'h290)); + range_racl_policy_shadowed[29].add_update_err_alert("recov_ctrl_update_err"); + + range_racl_policy_shadowed[29].add_storage_err_alert("fatal_fault"); + + range_racl_policy_shadowed[29].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_29_read_perm_29.committed_reg.q", + 0, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[29].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_29_read_perm_29.shadow_reg.q", + 0, 16, 0, "BkdrRegPathRtlShadow"); + range_racl_policy_shadowed[29].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_29_write_perm_29.committed_reg.q", + 16, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[29].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_29_write_perm_29.shadow_reg.q", + 16, 16, 0, "BkdrRegPathRtlShadow"); + + range_racl_policy_shadowed[29].set_is_shadowed(); + range_racl_policy_shadowed[30] = + (ac_range_check_reg_range_racl_policy_shadowed:: + type_id::create("range_racl_policy_shadowed_30")); + range_racl_policy_shadowed[30].configure(.blk_parent(this)); + range_racl_policy_shadowed[30].build(csr_excl); + default_map.add_reg(.rg(range_racl_policy_shadowed[30]), + .offset(32'h294)); + range_racl_policy_shadowed[30].add_update_err_alert("recov_ctrl_update_err"); + + range_racl_policy_shadowed[30].add_storage_err_alert("fatal_fault"); + + range_racl_policy_shadowed[30].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_30_read_perm_30.committed_reg.q", + 0, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[30].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_30_read_perm_30.shadow_reg.q", + 0, 16, 0, "BkdrRegPathRtlShadow"); + range_racl_policy_shadowed[30].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_30_write_perm_30.committed_reg.q", + 16, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[30].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_30_write_perm_30.shadow_reg.q", + 16, 16, 0, "BkdrRegPathRtlShadow"); + + range_racl_policy_shadowed[30].set_is_shadowed(); + range_racl_policy_shadowed[31] = + (ac_range_check_reg_range_racl_policy_shadowed:: + type_id::create("range_racl_policy_shadowed_31")); + range_racl_policy_shadowed[31].configure(.blk_parent(this)); + range_racl_policy_shadowed[31].build(csr_excl); + default_map.add_reg(.rg(range_racl_policy_shadowed[31]), + .offset(32'h298)); + range_racl_policy_shadowed[31].add_update_err_alert("recov_ctrl_update_err"); + + range_racl_policy_shadowed[31].add_storage_err_alert("fatal_fault"); + + range_racl_policy_shadowed[31].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_31_read_perm_31.committed_reg.q", + 0, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[31].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_31_read_perm_31.shadow_reg.q", + 0, 16, 0, "BkdrRegPathRtlShadow"); + range_racl_policy_shadowed[31].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_31_write_perm_31.committed_reg.q", + 16, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[31].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_31_write_perm_31.shadow_reg.q", + 16, 16, 0, "BkdrRegPathRtlShadow"); + + range_racl_policy_shadowed[31].set_is_shadowed(); + // assign locked reg to its regwen reg + range_regwen[0].add_lockable_reg_or_fld(range_base[0]); + range_regwen[1].add_lockable_reg_or_fld(range_base[1]); + range_regwen[2].add_lockable_reg_or_fld(range_base[2]); + range_regwen[3].add_lockable_reg_or_fld(range_base[3]); + range_regwen[4].add_lockable_reg_or_fld(range_base[4]); + range_regwen[5].add_lockable_reg_or_fld(range_base[5]); + range_regwen[6].add_lockable_reg_or_fld(range_base[6]); + range_regwen[7].add_lockable_reg_or_fld(range_base[7]); + range_regwen[8].add_lockable_reg_or_fld(range_base[8]); + range_regwen[9].add_lockable_reg_or_fld(range_base[9]); + range_regwen[10].add_lockable_reg_or_fld(range_base[10]); + range_regwen[11].add_lockable_reg_or_fld(range_base[11]); + range_regwen[12].add_lockable_reg_or_fld(range_base[12]); + range_regwen[13].add_lockable_reg_or_fld(range_base[13]); + range_regwen[14].add_lockable_reg_or_fld(range_base[14]); + range_regwen[15].add_lockable_reg_or_fld(range_base[15]); + range_regwen[16].add_lockable_reg_or_fld(range_base[16]); + range_regwen[17].add_lockable_reg_or_fld(range_base[17]); + range_regwen[18].add_lockable_reg_or_fld(range_base[18]); + range_regwen[19].add_lockable_reg_or_fld(range_base[19]); + range_regwen[20].add_lockable_reg_or_fld(range_base[20]); + range_regwen[21].add_lockable_reg_or_fld(range_base[21]); + range_regwen[22].add_lockable_reg_or_fld(range_base[22]); + range_regwen[23].add_lockable_reg_or_fld(range_base[23]); + range_regwen[24].add_lockable_reg_or_fld(range_base[24]); + range_regwen[25].add_lockable_reg_or_fld(range_base[25]); + range_regwen[26].add_lockable_reg_or_fld(range_base[26]); + range_regwen[27].add_lockable_reg_or_fld(range_base[27]); + range_regwen[28].add_lockable_reg_or_fld(range_base[28]); + range_regwen[29].add_lockable_reg_or_fld(range_base[29]); + range_regwen[30].add_lockable_reg_or_fld(range_base[30]); + range_regwen[31].add_lockable_reg_or_fld(range_base[31]); + range_regwen[0].add_lockable_reg_or_fld(range_limit[0]); + range_regwen[1].add_lockable_reg_or_fld(range_limit[1]); + range_regwen[2].add_lockable_reg_or_fld(range_limit[2]); + range_regwen[3].add_lockable_reg_or_fld(range_limit[3]); + range_regwen[4].add_lockable_reg_or_fld(range_limit[4]); + range_regwen[5].add_lockable_reg_or_fld(range_limit[5]); + range_regwen[6].add_lockable_reg_or_fld(range_limit[6]); + range_regwen[7].add_lockable_reg_or_fld(range_limit[7]); + range_regwen[8].add_lockable_reg_or_fld(range_limit[8]); + range_regwen[9].add_lockable_reg_or_fld(range_limit[9]); + range_regwen[10].add_lockable_reg_or_fld(range_limit[10]); + range_regwen[11].add_lockable_reg_or_fld(range_limit[11]); + range_regwen[12].add_lockable_reg_or_fld(range_limit[12]); + range_regwen[13].add_lockable_reg_or_fld(range_limit[13]); + range_regwen[14].add_lockable_reg_or_fld(range_limit[14]); + range_regwen[15].add_lockable_reg_or_fld(range_limit[15]); + range_regwen[16].add_lockable_reg_or_fld(range_limit[16]); + range_regwen[17].add_lockable_reg_or_fld(range_limit[17]); + range_regwen[18].add_lockable_reg_or_fld(range_limit[18]); + range_regwen[19].add_lockable_reg_or_fld(range_limit[19]); + range_regwen[20].add_lockable_reg_or_fld(range_limit[20]); + range_regwen[21].add_lockable_reg_or_fld(range_limit[21]); + range_regwen[22].add_lockable_reg_or_fld(range_limit[22]); + range_regwen[23].add_lockable_reg_or_fld(range_limit[23]); + range_regwen[24].add_lockable_reg_or_fld(range_limit[24]); + range_regwen[25].add_lockable_reg_or_fld(range_limit[25]); + range_regwen[26].add_lockable_reg_or_fld(range_limit[26]); + range_regwen[27].add_lockable_reg_or_fld(range_limit[27]); + range_regwen[28].add_lockable_reg_or_fld(range_limit[28]); + range_regwen[29].add_lockable_reg_or_fld(range_limit[29]); + range_regwen[30].add_lockable_reg_or_fld(range_limit[30]); + range_regwen[31].add_lockable_reg_or_fld(range_limit[31]); + range_regwen[0].add_lockable_reg_or_fld(range_perm[0]); + range_regwen[1].add_lockable_reg_or_fld(range_perm[1]); + range_regwen[2].add_lockable_reg_or_fld(range_perm[2]); + range_regwen[3].add_lockable_reg_or_fld(range_perm[3]); + range_regwen[4].add_lockable_reg_or_fld(range_perm[4]); + range_regwen[5].add_lockable_reg_or_fld(range_perm[5]); + range_regwen[6].add_lockable_reg_or_fld(range_perm[6]); + range_regwen[7].add_lockable_reg_or_fld(range_perm[7]); + range_regwen[8].add_lockable_reg_or_fld(range_perm[8]); + range_regwen[9].add_lockable_reg_or_fld(range_perm[9]); + range_regwen[10].add_lockable_reg_or_fld(range_perm[10]); + range_regwen[11].add_lockable_reg_or_fld(range_perm[11]); + range_regwen[12].add_lockable_reg_or_fld(range_perm[12]); + range_regwen[13].add_lockable_reg_or_fld(range_perm[13]); + range_regwen[14].add_lockable_reg_or_fld(range_perm[14]); + range_regwen[15].add_lockable_reg_or_fld(range_perm[15]); + range_regwen[16].add_lockable_reg_or_fld(range_perm[16]); + range_regwen[17].add_lockable_reg_or_fld(range_perm[17]); + range_regwen[18].add_lockable_reg_or_fld(range_perm[18]); + range_regwen[19].add_lockable_reg_or_fld(range_perm[19]); + range_regwen[20].add_lockable_reg_or_fld(range_perm[20]); + range_regwen[21].add_lockable_reg_or_fld(range_perm[21]); + range_regwen[22].add_lockable_reg_or_fld(range_perm[22]); + range_regwen[23].add_lockable_reg_or_fld(range_perm[23]); + range_regwen[24].add_lockable_reg_or_fld(range_perm[24]); + range_regwen[25].add_lockable_reg_or_fld(range_perm[25]); + range_regwen[26].add_lockable_reg_or_fld(range_perm[26]); + range_regwen[27].add_lockable_reg_or_fld(range_perm[27]); + range_regwen[28].add_lockable_reg_or_fld(range_perm[28]); + range_regwen[29].add_lockable_reg_or_fld(range_perm[29]); + range_regwen[30].add_lockable_reg_or_fld(range_perm[30]); + range_regwen[31].add_lockable_reg_or_fld(range_perm[31]); + range_regwen[0].add_lockable_reg_or_fld(range_racl_policy_shadowed[0]); + range_regwen[1].add_lockable_reg_or_fld(range_racl_policy_shadowed[1]); + range_regwen[2].add_lockable_reg_or_fld(range_racl_policy_shadowed[2]); + range_regwen[3].add_lockable_reg_or_fld(range_racl_policy_shadowed[3]); + range_regwen[4].add_lockable_reg_or_fld(range_racl_policy_shadowed[4]); + range_regwen[5].add_lockable_reg_or_fld(range_racl_policy_shadowed[5]); + range_regwen[6].add_lockable_reg_or_fld(range_racl_policy_shadowed[6]); + range_regwen[7].add_lockable_reg_or_fld(range_racl_policy_shadowed[7]); + range_regwen[8].add_lockable_reg_or_fld(range_racl_policy_shadowed[8]); + range_regwen[9].add_lockable_reg_or_fld(range_racl_policy_shadowed[9]); + range_regwen[10].add_lockable_reg_or_fld(range_racl_policy_shadowed[10]); + range_regwen[11].add_lockable_reg_or_fld(range_racl_policy_shadowed[11]); + range_regwen[12].add_lockable_reg_or_fld(range_racl_policy_shadowed[12]); + range_regwen[13].add_lockable_reg_or_fld(range_racl_policy_shadowed[13]); + range_regwen[14].add_lockable_reg_or_fld(range_racl_policy_shadowed[14]); + range_regwen[15].add_lockable_reg_or_fld(range_racl_policy_shadowed[15]); + range_regwen[16].add_lockable_reg_or_fld(range_racl_policy_shadowed[16]); + range_regwen[17].add_lockable_reg_or_fld(range_racl_policy_shadowed[17]); + range_regwen[18].add_lockable_reg_or_fld(range_racl_policy_shadowed[18]); + range_regwen[19].add_lockable_reg_or_fld(range_racl_policy_shadowed[19]); + range_regwen[20].add_lockable_reg_or_fld(range_racl_policy_shadowed[20]); + range_regwen[21].add_lockable_reg_or_fld(range_racl_policy_shadowed[21]); + range_regwen[22].add_lockable_reg_or_fld(range_racl_policy_shadowed[22]); + range_regwen[23].add_lockable_reg_or_fld(range_racl_policy_shadowed[23]); + range_regwen[24].add_lockable_reg_or_fld(range_racl_policy_shadowed[24]); + range_regwen[25].add_lockable_reg_or_fld(range_racl_policy_shadowed[25]); + range_regwen[26].add_lockable_reg_or_fld(range_racl_policy_shadowed[26]); + range_regwen[27].add_lockable_reg_or_fld(range_racl_policy_shadowed[27]); + range_regwen[28].add_lockable_reg_or_fld(range_racl_policy_shadowed[28]); + range_regwen[29].add_lockable_reg_or_fld(range_racl_policy_shadowed[29]); + range_regwen[30].add_lockable_reg_or_fld(range_racl_policy_shadowed[30]); + range_regwen[31].add_lockable_reg_or_fld(range_racl_policy_shadowed[31]); + + + // Create functional coverage for comportable IP-specific specialized registers. + // This function can only be called if it is a root block to get the correct gating condition + // and avoid creating duplicated cov. + if (this.get_parent() == null && en_dv_reg_cov) create_cov(); + endfunction : build + endclass : ac_range_check_reg_block + +endpackage diff --git a/hw/ip_templates/ac_range_check/dv/env/ac_range_check_scoreboard.sv b/hw/ip_templates/ac_range_check/dv/env/ac_range_check_scoreboard.sv new file mode 100644 index 0000000000000..b2bd178e1a487 --- /dev/null +++ b/hw/ip_templates/ac_range_check/dv/env/ac_range_check_scoreboard.sv @@ -0,0 +1,171 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class ac_range_check_scoreboard extends cip_base_scoreboard #( + .CFG_T(ac_range_check_env_cfg), + .RAL_T(ac_range_check_reg_block), + .COV_T(ac_range_check_env_cov) + ); + `uvm_component_utils(ac_range_check_scoreboard) + + // Local variables + + // TLM agent fifos + uvm_tlm_analysis_fifo #(tl_seq_item) tl_csr_fifo; + uvm_tlm_analysis_fifo #(tl_seq_item) tl_unfilt_fifo; + uvm_tlm_analysis_fifo #(tl_seq_item) tl_filt_fifo; + + // Local queues to hold incoming packets pending comparison + tl_seq_item tl_csr_q[$]; + tl_seq_item tl_unfilt_q[$]; + tl_seq_item tl_filt_q[$]; + + // Standard SV/UVM methods + extern function new(string name="", uvm_component parent=null); + extern function void build_phase(uvm_phase phase); + extern function void connect_phase(uvm_phase phase); + extern task run_phase(uvm_phase phase); + extern function void check_phase(uvm_phase phase); + + // Class specific methods + extern task process_tl_csr_fifo(); + extern task process_tl_unfilt_fifo(); + extern task process_tl_filt_fifo(); + extern task process_tl_access(tl_seq_item item, tl_channels_e channel, string ral_name); + extern function void reset(string kind = "HARD"); +endclass : ac_range_check_scoreboard + + +function ac_range_check_scoreboard::new(string name="", uvm_component parent=null); + super.new(name, parent); +endfunction : new + +function void ac_range_check_scoreboard::build_phase(uvm_phase phase); + super.build_phase(phase); + tl_csr_fifo = new("tl_csr_fifo", this); + tl_unfilt_fifo = new("tl_unfilt_fifo", this); + tl_filt_fifo = new("tl_filt_fifo", this); + // TODO: remove once support alert checking + do_alert_check = 0; +endfunction : build_phase + +function void ac_range_check_scoreboard::connect_phase(uvm_phase phase); + super.connect_phase(phase); +endfunction : connect_phase + +task ac_range_check_scoreboard::run_phase(uvm_phase phase); + super.run_phase(phase); + wait(cfg.under_reset); + forever begin + wait(!cfg.under_reset); + // This isolation fork is needed to ensure that "disable fork" call won't kill any other + // processes at the same level from the parent classes + fork begin : isolation_fork + fork + begin : main_thread + fork + process_tl_csr_fifo(); + process_tl_unfilt_fifo(); + process_tl_filt_fifo(); + join + wait fork; // To ensure it will be killed only when the reset will occur + end + begin : reset_thread + wait(cfg.under_reset); + end + join_any + disable fork; // Terminates all descendants and sub-descendants of isolation_fork + end join + end +endtask : run_phase + +task ac_range_check_scoreboard::process_tl_csr_fifo(); + tl_seq_item item; + forever begin + tl_csr_fifo.get(item); + `uvm_info(`gfn, $sformatf("received tl_csr item:\n%0s", item.sprint()), UVM_HIGH) + end +endtask : process_tl_csr_fifo + +task ac_range_check_scoreboard::process_tl_unfilt_fifo(); + tl_seq_item item; + forever begin + tl_unfilt_fifo.get(item); + `uvm_info(`gfn, $sformatf("received tl_unfilt item:\n%0s", item.sprint()), UVM_HIGH) + end +endtask : process_tl_unfilt_fifo + +task ac_range_check_scoreboard::process_tl_filt_fifo(); + tl_seq_item item; + forever begin + tl_filt_fifo.get(item); + `uvm_info(`gfn, $sformatf("received tl_filt item:\n%0s", item.sprint()), UVM_HIGH) + end +endtask : process_tl_filt_fifo + +task ac_range_check_scoreboard::process_tl_access(tl_seq_item item, + tl_channels_e channel, + string ral_name); + uvm_reg csr; + bit do_read_check = 1'b1; + bit write = item.is_write(); + uvm_reg_addr_t csr_addr = cfg.ral_models[ral_name].get_word_aligned_addr(item.a_addr); + + bit addr_phase_read = (!write && channel == AddrChannel); + bit addr_phase_write = ( write && channel == AddrChannel); + bit data_phase_read = (!write && channel == DataChannel); + bit data_phase_write = ( write && channel == DataChannel); + + // If access was to a valid csr, get the csr handle + if (csr_addr inside {cfg.ral_models[ral_name].csr_addrs}) begin + csr = cfg.ral_models[ral_name].default_map.get_reg_by_offset(csr_addr); + `DV_CHECK_NE_FATAL(csr, null) + end else begin + `uvm_fatal(`gfn, $sformatf("Access unexpected addr 0x%0h", csr_addr)) + end + + // If incoming access is a write to a valid csr, then make updates right away + if (addr_phase_write) begin + void'(csr.predict(.value(item.a_data), .kind(UVM_PREDICT_WRITE), .be(item.a_mask))); + end + + // Process the csr req: + // - for write, update local variable and fifo at address phase + // - for read, update predication at address phase and compare at data phase + case (csr.get_name()) + // Add individual case item for each csr + "intr_state": begin + // FIXME TODO MVy + do_read_check = 1'b0; + end + "intr_enable": begin + // FIXME TODO MVy + end + "intr_test": begin + // FIXME TODO MVy + end + default: begin + `uvm_fatal(`gfn, $sformatf("invalid csr: %0s", csr.get_full_name())) + end + endcase + + // On reads, if do_read_check, is set, then check mirrored_value against item.d_data + if (data_phase_read) begin + if (do_read_check) begin + `DV_CHECK_EQ(csr.get_mirrored_value(), item.d_data, + $sformatf("reg name: %0s", csr.get_full_name())) + end + void'(csr.predict(.value(item.d_data), .kind(UVM_PREDICT_READ))); + end +endtask : process_tl_access + +function void ac_range_check_scoreboard::reset(string kind = "HARD"); + super.reset(kind); + // Reset local fifos queues and variables +endfunction : reset + +function void ac_range_check_scoreboard::check_phase(uvm_phase phase); + super.check_phase(phase); + // Post test checks - ensure that all local fifos and queues are empty +endfunction : check_phase diff --git a/hw/ip_templates/ac_range_check/dv/env/ac_range_check_virtual_sequencer.sv b/hw/ip_templates/ac_range_check/dv/env/ac_range_check_virtual_sequencer.sv new file mode 100644 index 0000000000000..2f022b0c6debe --- /dev/null +++ b/hw/ip_templates/ac_range_check/dv/env/ac_range_check_virtual_sequencer.sv @@ -0,0 +1,21 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class ac_range_check_virtual_sequencer extends cip_base_virtual_sequencer #( + .CFG_T(ac_range_check_env_cfg), + .COV_T(ac_range_check_env_cov) + ); + `uvm_component_utils(ac_range_check_virtual_sequencer) + + tl_sequencer tl_csr_sqr; + tl_sequencer tl_unfilt_sqr; + tl_sequencer tl_filt_sqr; + + // Standard SV/UVM methods + extern function new(string name="", uvm_component parent=null); +endclass : ac_range_check_virtual_sequencer + +function ac_range_check_virtual_sequencer::new(string name="", uvm_component parent=null); + super.new(name, parent); +endfunction : new diff --git a/hw/ip_templates/ac_range_check/dv/env/seq_lib/ac_range_check_base_vseq.sv b/hw/ip_templates/ac_range_check/dv/env/seq_lib/ac_range_check_base_vseq.sv new file mode 100644 index 0000000000000..2a3dbb5072c73 --- /dev/null +++ b/hw/ip_templates/ac_range_check/dv/env/seq_lib/ac_range_check_base_vseq.sv @@ -0,0 +1,38 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class ac_range_check_base_vseq extends cip_base_vseq #( + .RAL_T (ac_range_check_reg_block), + .CFG_T (ac_range_check_env_cfg), + .COV_T (ac_range_check_env_cov), + .VIRTUAL_SEQUENCER_T (ac_range_check_virtual_sequencer) + ); + `uvm_object_utils(ac_range_check_base_vseq) + + // Various knobs to enable certain routines + bit do_ac_range_check_init = 1'b1; + + // Standard SV/UVM methods + extern function new(string name=""); + + // Class specific methods + extern task dut_init(string reset_kind = "HARD"); + extern task ac_range_check_init(); +endclass : ac_range_check_base_vseq + + +function ac_range_check_base_vseq::new(string name=""); + super.new(name); +endfunction : new + +task ac_range_check_base_vseq::dut_init(string reset_kind = "HARD"); + super.dut_init(); + if (do_ac_range_check_init) begin + ac_range_check_init(); + end +endtask : dut_init + +task ac_range_check_base_vseq::ac_range_check_init(); + `uvm_error(`gfn, "FIXME") +endtask : ac_range_check_init diff --git a/hw/ip_templates/ac_range_check/dv/env/seq_lib/ac_range_check_common_vseq.sv b/hw/ip_templates/ac_range_check/dv/env/seq_lib/ac_range_check_common_vseq.sv new file mode 100644 index 0000000000000..2a6c089863e2d --- /dev/null +++ b/hw/ip_templates/ac_range_check/dv/env/seq_lib/ac_range_check_common_vseq.sv @@ -0,0 +1,27 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class ac_range_check_common_vseq extends ac_range_check_base_vseq; + `uvm_object_utils(ac_range_check_common_vseq) + + // Constraints + extern constraint num_trans_c; + + // Standard SV/UVM methods + extern function new(string name=""); + extern task body(); +endclass : ac_range_check_common_vseq + + +constraint ac_range_check_common_vseq::num_trans_c { + num_trans inside {[1:2]}; +} + +function ac_range_check_common_vseq::new(string name=""); + super.new(name); +endfunction : new + +task ac_range_check_common_vseq::body(); + run_common_vseq_wrapper(num_trans); +endtask : body diff --git a/hw/ip_templates/ac_range_check/dv/env/seq_lib/ac_range_check_smoke_vseq.sv b/hw/ip_templates/ac_range_check/dv/env/seq_lib/ac_range_check_smoke_vseq.sv new file mode 100644 index 0000000000000..c6c70a470ab6b --- /dev/null +++ b/hw/ip_templates/ac_range_check/dv/env/seq_lib/ac_range_check_smoke_vseq.sv @@ -0,0 +1,20 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class ac_range_check_smoke_vseq extends ac_range_check_base_vseq; + `uvm_object_utils(ac_range_check_smoke_vseq) + + // Standard SV/UVM methods + extern function new(string name=""); + extern task body(); +endclass : ac_range_check_smoke_vseq + + +function ac_range_check_smoke_vseq::new(string name=""); + super.new(name); +endfunction : new + +task ac_range_check_smoke_vseq::body(); + `uvm_error(`gfn, "FIXME") +endtask : body diff --git a/hw/ip_templates/ac_range_check/dv/env/seq_lib/ac_range_check_vseq_list.sv b/hw/ip_templates/ac_range_check/dv/env/seq_lib/ac_range_check_vseq_list.sv new file mode 100644 index 0000000000000..5e7b497a396c3 --- /dev/null +++ b/hw/ip_templates/ac_range_check/dv/env/seq_lib/ac_range_check_vseq_list.sv @@ -0,0 +1,7 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +`include "ac_range_check_base_vseq.sv" +`include "ac_range_check_smoke_vseq.sv" +`include "ac_range_check_common_vseq.sv" diff --git a/hw/ip_templates/ac_range_check/dv/sva/ac_range_check_bind.sv b/hw/ip_templates/ac_range_check/dv/sva/ac_range_check_bind.sv new file mode 100644 index 0000000000000..87cc1a4fb823c --- /dev/null +++ b/hw/ip_templates/ac_range_check/dv/sva/ac_range_check_bind.sv @@ -0,0 +1,23 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +module ac_range_check_bind; + + bind ac_range_check tlul_assert #( + .EndpointType("Device") + ) tlul_assert_device ( + .clk_i, + .rst_ni, + .h2d (tl_i), + .d2h (tl_o) + ); + + bind ac_range_check ac_range_check_csr_assert_fpv ac_range_check_csr_assert ( + .clk_i, + .rst_ni, + .h2d (tl_i), + .d2h (tl_o) + ); + +endmodule diff --git a/hw/ip_templates/ac_range_check/dv/sva/ac_range_check_sva.core.tpl b/hw/ip_templates/ac_range_check/dv/sva/ac_range_check_sva.core.tpl new file mode 100644 index 0000000000000..f1fbfc74d2d35 --- /dev/null +++ b/hw/ip_templates/ac_range_check/dv/sva/ac_range_check_sva.core.tpl @@ -0,0 +1,38 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: ${instance_vlnv("lowrisc:dv:ac_range_check_sva:0.1")} +description: "AC_RANGE_CHECK assertion modules and bind file." +filesets: + files_dv: + depend: + - lowrisc:tlul:headers + - lowrisc:fpv:csr_assert_gen + files: + - ac_range_check_bind.sv + file_type: systemVerilogSource + + files_formal: + depend: + - ${instance_vlnv("lowrisc:ip:ac_range_check")} + +generate: + csr_assert_gen: + generator: csr_assert_gen + parameters: + spec: ../../data/ac_range_check.hjson + +targets: + default: &default_target + filesets: + - files_dv + generate: + - csr_assert_gen + + formal: + <<: *default_target + filesets: + - files_formal + - files_dv + toplevel: ac_range_check diff --git a/hw/ip_templates/ac_range_check/dv/tb/tb.sv b/hw/ip_templates/ac_range_check/dv/tb/tb.sv new file mode 100644 index 0000000000000..cb702657a54f3 --- /dev/null +++ b/hw/ip_templates/ac_range_check/dv/tb/tb.sv @@ -0,0 +1,92 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +module tb; + // Dep packages + import uvm_pkg::*; + import dv_utils_pkg::*; + import ac_range_check_env_pkg::*; + import ac_range_check_test_pkg::*; + + // Macro includes + `include "uvm_macros.svh" + `include "dv_macros.svh" + + wire clk; + wire rst_n; + wire [NUM_MAX_INTERRUPTS-1:0] interrupts; + wire rst_shadowed_n; + wire top_racl_pkg::racl_policy_vec_t racl_policies; + wire racl_error; + wire top_racl_pkg::racl_error_log_t racl_error_log; + wire intr_deny_cnt_reached; + wire prim_mubi_pkg::mubi8_t range_check_overwrite; + + // Interfaces + pins_if #(NUM_MAX_INTERRUPTS) intr_if (interrupts); + clk_rst_if clk_rst_if (.clk(clk), .rst_n(rst_n)); + rst_shadowed_if rst_shad_if (.rst_n(rst_n), .rst_shadowed_n(rst_shadowed_n)); + tl_if tl_csr_if (.clk(clk), .rst_n(rst_n)); + tl_if tl_unfilt_if (.clk(clk), .rst_n(rst_n)); + tl_if tl_filt_if (.clk(clk), .rst_n(rst_n)); + + `DV_ALERT_IF_CONNECT() + + // DUT + ac_range_check dut ( + // TODO MVy: should we keep the default values? Plan to verify with the others? As the TB will be impacted and should adopt a particular technique + // .AlertAsyncOn = , + // .EnableRacl = , + // .RaclErrorRsp = , + // .RaclPolicySelVec[NumRegs] = + // ) ( + .clk_i (clk ), + .rst_ni (rst_n ), + .rst_shadowed_ni (rst_shadowed_n ), + // Alerts + .alert_rx_i (alert_rx ), + .alert_tx_o (alert_tx ), + // RACL interface + .racl_policies_i (racl_policies ), + .racl_error_o (racl_error ), + .racl_error_log_o (racl_error_log ), + // Access range check interrupts + .intr_deny_cnt_reached_o (intr_deny_cnt_reached ), + // Bus interface + .tl_i (tl_csr_if.h2d ), + .tl_o (tl_csr_if.d2h ), + // Inter module signals + .range_check_overwrite_i (range_check_overwrite ), + // Incoming TLUL interface + .ctn_tl_h2d_i (tl_unfilt_if.h2d ), + .ctn_tl_d2h_o (tl_unfilt_if.d2h ), + // Filtered outgoing TLUL interface to the target if request is not squashed + .ctn_filtered_tl_h2d_o (tl_filt_if.h2d ), + .ctn_filtered_tl_d2h_i (tl_filt_if.d2h ) + ); + + // Manage inputs + // TODO should be driven dynamically by an io_agent (to be created TODO MVy) + assign range_check_overwrite = prim_mubi_pkg::MuBi8False; + assign racl_policies = top_racl_pkg::RACL_POLICY_VEC_DEFAULT; + + // Manage outputs + assign interrupts[DenyCntReached] = intr_deny_cnt_reached; + // TODO should be monitored dynamically by an io_agent (to be created TODO MVy) + // assign io_if.racl_error = racl_error; + // assign io_if.racl_error_log = racl_error_log; + + initial begin + clk_rst_if.set_active(); + uvm_config_db#(virtual clk_rst_if)::set(null, "*.env", "clk_rst_vif", clk_rst_if); + uvm_config_db#(virtual rst_shadowed_if)::set(null, "*.env", "rst_shadowed_vif", rst_shad_if); + uvm_config_db#(intr_vif)::set(null, "*.env", "intr_vif", intr_if); + uvm_config_db#(virtual tl_if)::set(null, "*.env.tl_csr_agt*", "tl_csr_vif", tl_csr_if); + uvm_config_db#(virtual tl_if)::set(null, "*.env.tl_unfilt_agt*", "tl_unfilt_vif", tl_unfilt_if); + uvm_config_db#(virtual tl_if)::set(null, "*.env.tl_filt_agt*", "tl_filt_vif", tl_filt_if); + $timeformat(-12, 0, " ps", 12); + run_test(); + end + +endmodule diff --git a/hw/ip_templates/ac_range_check/dv/tests/ac_range_check_base_test.sv b/hw/ip_templates/ac_range_check/dv/tests/ac_range_check_base_test.sv new file mode 100644 index 0000000000000..e732a5b5661d0 --- /dev/null +++ b/hw/ip_templates/ac_range_check/dv/tests/ac_range_check_base_test.sv @@ -0,0 +1,26 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class ac_range_check_base_test extends cip_base_test #( + .CFG_T(ac_range_check_env_cfg), + .ENV_T(ac_range_check_env) + ); + + `uvm_component_utils(ac_range_check_base_test) + + // The base class dv_base_test creates the following instances: + // - ac_range_check_env_cfg: cfg + // - ac_range_check_env: env + + // The base class also looks up UVM_TEST_SEQ plusarg to create and run that seq in the run_phase. + // As such, nothing more needs to be done + + // Standard SV/UVM methods + extern function new(string name="", uvm_component parent=null); +endclass : ac_range_check_base_test + + +function ac_range_check_base_test::new(string name="", uvm_component parent=null); + super.new(name, parent); +endfunction : new diff --git a/hw/ip_templates/ac_range_check/dv/tests/ac_range_check_test.core.tpl b/hw/ip_templates/ac_range_check/dv/tests/ac_range_check_test.core.tpl new file mode 100644 index 0000000000000..cf02edb0241fe --- /dev/null +++ b/hw/ip_templates/ac_range_check/dv/tests/ac_range_check_test.core.tpl @@ -0,0 +1,19 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: ${instance_vlnv("lowrisc:dv:ac_range_check_test:0.1")} +description: "AC_RANGE_CHECK DV UVM test" +filesets: + files_dv: + depend: + - ${instance_vlnv("lowrisc:dv:ac_range_check_env")} + files: + - ac_range_check_test_pkg.sv + - ac_range_check_base_test.sv: {is_include_file: true} + file_type: systemVerilogSource + +targets: + default: + filesets: + - files_dv diff --git a/hw/ip_templates/ac_range_check/dv/tests/ac_range_check_test_pkg.sv b/hw/ip_templates/ac_range_check/dv/tests/ac_range_check_test_pkg.sv new file mode 100644 index 0000000000000..a409d852dcd5d --- /dev/null +++ b/hw/ip_templates/ac_range_check/dv/tests/ac_range_check_test_pkg.sv @@ -0,0 +1,22 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +package ac_range_check_test_pkg; + // Dep packages + import uvm_pkg::*; + import cip_base_pkg::*; + import ac_range_check_env_pkg::*; + + // Macro includes + `include "uvm_macros.svh" + `include "dv_macros.svh" + + // Local types + + // Functions + + // Package sources + `include "ac_range_check_base_test.sv" + +endpackage diff --git a/hw/top_darjeeling/ip_autogen/ac_range_check/ac_range_check.core b/hw/top_darjeeling/ip_autogen/ac_range_check/ac_range_check.core index 8e8dc085bd528..c74c91756816e 100644 --- a/hw/top_darjeeling/ip_autogen/ac_range_check/ac_range_check.core +++ b/hw/top_darjeeling/ip_autogen/ac_range_check/ac_range_check.core @@ -12,6 +12,8 @@ filesets: - lowrisc:prim:mubi - lowrisc:prim:all - lowrisc:systems:top_racl_pkg + - lowrisc:prim:edge_detector + - lowrisc:prim:onehot files: - rtl/ac_range_check_reg_pkg.sv - rtl/ac_range_check_reg_top.sv diff --git a/hw/top_darjeeling/ip_autogen/ac_range_check/doc/checklist.md b/hw/top_darjeeling/ip_autogen/ac_range_check/doc/checklist.md new file mode 100644 index 0000000000000..f663bc000f973 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/ac_range_check/doc/checklist.md @@ -0,0 +1,275 @@ +--- +title: "AC_RANGE_CHECK Checklist" +--- + + +This checklist is for [Hardware Stage](/doc/project_governance/development_stages.md) transitions for the [AC_RANGE_CHECK peripheral.](../README.md) +All checklist items refer to the content in the [Checklist.](/doc/project_governance/checklist/README.md) + +## Design Checklist + +### D1 + +Type | Item | Resolution | Note/Collaterals +--------------|--------------------------------|-------------|------------------ +Documentation | [SPEC_COMPLETE][] | Not Started | [AC_RANGE_CHECK Design Spec](../README.md) +Documentation | [CSR_DEFINED][] | Not Started | +RTL | [CLKRST_CONNECTED][] | Not Started | +RTL | [IP_TOP][] | Not Started | +RTL | [IP_INSTANTIABLE][] | Not Started | +RTL | [PHYSICAL_MACROS_DEFINED_80][] | Not Started | +RTL | [FUNC_IMPLEMENTED][] | Not Started | +RTL | [ASSERT_KNOWN_ADDED][] | Not Started | +Code Quality | [LINT_SETUP][] | Not Started | +Security | [SEC_CM_SCOPED][] | Not Started | + +[SPEC_COMPLETE]: /doc/project_governance/checklist/README.md#spec_complete +[CSR_DEFINED]: /doc/project_governance/checklist/README.md#csr_defined +[CLKRST_CONNECTED]: /doc/project_governance/checklist/README.md#clkrst_connected +[IP_TOP]: /doc/project_governance/checklist/README.md#ip_top +[IP_INSTANTIABLE]: /doc/project_governance/checklist/README.md#ip_instantiable +[PHYSICAL_MACROS_DEFINED_80]: /doc/project_governance/checklist/README.md#physical_macros_defined_80 +[FUNC_IMPLEMENTED]: /doc/project_governance/checklist/README.md#func_implemented +[ASSERT_KNOWN_ADDED]: /doc/project_governance/checklist/README.md#assert_known_added +[LINT_SETUP]: /doc/project_governance/checklist/README.md#lint_setup +[SEC_CM_SCOPED]: /doc/project_governance/checklist/README.md#sec_cm_scoped + +### D2 + +Type | Item | Resolution | Note/Collaterals +--------------|---------------------------|-------------|------------------ +Documentation | [NEW_FEATURES][] | Not Started | +Documentation | [BLOCK_DIAGRAM][] | Not Started | +Documentation | [DOC_INTERFACE][] | Not Started | +Documentation | [DOC_INTEGRATION_GUIDE][] | Not Started | +Documentation | [MISSING_FUNC][] | Not Started | +Documentation | [FEATURE_FROZEN][] | Not Started | +RTL | [FEATURE_COMPLETE][] | Not Started | +RTL | [PORT_FROZEN][] | Not Started | +RTL | [ARCHITECTURE_FROZEN][] | Not Started | +RTL | [REVIEW_TODO][] | Not Started | +RTL | [STYLE_X][] | Not Started | +RTL | [CDC_SYNCMACRO][] | Not Started | +Code Quality | [LINT_PASS][] | Not Started | +Code Quality | [CDC_SETUP][] | Not Started | +Code Quality | [RDC_SETUP][] | Not Started | +Code Quality | [AREA_CHECK][] | Not Started | +Code Quality | [TIMING_CHECK][] | Not Started | +Security | [SEC_CM_DOCUMENTED][] | Not Started | + +[NEW_FEATURES]: /doc/project_governance/checklist/README.md#new_features +[BLOCK_DIAGRAM]: /doc/project_governance/checklist/README.md#block_diagram +[DOC_INTERFACE]: /doc/project_governance/checklist/README.md#doc_interface +[DOC_INTEGRATION_GUIDE]: /doc/project_governance/checklist/README.md#doc_integration_guide +[MISSING_FUNC]: /doc/project_governance/checklist/README.md#missing_func +[FEATURE_FROZEN]: /doc/project_governance/checklist/README.md#feature_frozen +[FEATURE_COMPLETE]: /doc/project_governance/checklist/README.md#feature_complete +[PORT_FROZEN]: /doc/project_governance/checklist/README.md#port_frozen +[ARCHITECTURE_FROZEN]: /doc/project_governance/checklist/README.md#architecture_frozen +[REVIEW_TODO]: /doc/project_governance/checklist/README.md#review_todo +[STYLE_X]: /doc/project_governance/checklist/README.md#style_x +[CDC_SYNCMACRO]: /doc/project_governance/checklist/README.md#cdc_syncmacro +[LINT_PASS]: /doc/project_governance/checklist/README.md#lint_pass +[CDC_SETUP]: /doc/project_governance/checklist/README.md#cdc_setup +[RDC_SETUP]: /doc/project_governance/checklist/README.md#rdc_setup +[AREA_CHECK]: /doc/project_governance/checklist/README.md#area_check +[TIMING_CHECK]: /doc/project_governance/checklist/README.md#timing_check +[SEC_CM_DOCUMENTED]: /doc/project_governance/checklist/README.md#sec_cm_documented + +### D2S + + Type | Item | Resolution | Note/Collaterals +--------------|------------------------------|-------------|------------------ +Security | [SEC_CM_ASSETS_LISTED][] | Not Started | +Security | [SEC_CM_IMPLEMENTED][] | Not Started | +Security | [SEC_CM_RND_CNST][] | Not Started | +Security | [SEC_CM_NON_RESET_FLOPS][] | Not Started | +Security | [SEC_CM_SHADOW_REGS][] | Not Started | +Security | [SEC_CM_RTL_REVIEWED][] | Not Started | +Security | [SEC_CM_COUNCIL_REVIEWED][] | Not Started | + +[SEC_CM_ASSETS_LISTED]: /doc/project_governance/checklist/README.md#sec_cm_assets_listed +[SEC_CM_IMPLEMENTED]: /doc/project_governance/checklist/README.md#sec_cm_implemented +[SEC_CM_RND_CNST]: /doc/project_governance/checklist/README.md#sec_cm_rnd_cnst +[SEC_CM_NON_RESET_FLOPS]: /doc/project_governance/checklist/README.md#sec_cm_non_reset_flops +[SEC_CM_SHADOW_REGS]: /doc/project_governance/checklist/README.md#sec_cm_shadow_regs +[SEC_CM_RTL_REVIEWED]: /doc/project_governance/checklist/README.md#sec_cm_rtl_reviewed +[SEC_CM_COUNCIL_REVIEWED]: /doc/project_governance/checklist/README.md#sec_cm_council_reviewed + +### D3 + + Type | Item | Resolution | Note/Collaterals +--------------|-------------------------|-------------|------------------ +Documentation | [NEW_FEATURES_D3][] | Not Started | +RTL | [TODO_COMPLETE][] | Not Started | +Code Quality | [LINT_COMPLETE][] | Not Started | +Code Quality | [CDC_COMPLETE][] | Not Started | +Code Quality | [RDC_COMPLETE][] | Not Started | +Review | [REVIEW_RTL][] | Not Started | +Review | [REVIEW_DELETED_FF][] | Not Started | +Review | [REVIEW_SW_CHANGE][] | Not Started | +Review | [REVIEW_SW_ERRATA][] | Not Started | +Review | Reviewer(s) | Not Started | +Review | Signoff date | Not Started | + +[NEW_FEATURES_D3]: /doc/project_governance/checklist/README.md#new_features_d3 +[TODO_COMPLETE]: /doc/project_governance/checklist/README.md#todo_complete +[LINT_COMPLETE]: /doc/project_governance/checklist/README.md#lint_complete +[CDC_COMPLETE]: /doc/project_governance/checklist/README.md#cdc_complete +[RDC_COMPLETE]: /doc/project_governance/checklist/README.md#rdc_complete +[REVIEW_RTL]: /doc/project_governance/checklist/README.md#review_rtl +[REVIEW_DELETED_FF]: /doc/project_governance/checklist/README.md#review_deleted_ff +[REVIEW_SW_CHANGE]: /doc/project_governance/checklist/README.md#review_sw_change +[REVIEW_SW_ERRATA]: /doc/project_governance/checklist/README.md#review_sw_errata + +## Verification Checklist + +### V1 + + Type | Item | Resolution | Note/Collaterals +--------------|---------------------------------------|-------------|------------------ +Documentation | [DV_DOC_DRAFT_COMPLETED][] | Not Started | [AC_RANGE_CHECK DV document](../dv/README.md) +Documentation | [TESTPLAN_COMPLETED][] | Not Started | [AC_RANGE_CHECK Testplan](../dv/README.md#testplan) +Testbench | [TB_TOP_CREATED][] | Not Started | +Testbench | [PRELIMINARY_ASSERTION_CHECKS_ADDED][]| Not Started | +Testbench | [SIM_TB_ENV_CREATED][] | Not Started | +Testbench | [SIM_RAL_MODEL_GEN_AUTOMATED][] | Not Started | +Testbench | [CSR_CHECK_GEN_AUTOMATED][] | Not Started | +Testbench | [TB_GEN_AUTOMATED][] | Not Started | +Tests | [SIM_SMOKE_TEST_PASSING][] | Not Started | +Tests | [SIM_CSR_MEM_TEST_SUITE_PASSING][] | Not Started | +Tests | [FPV_MAIN_ASSERTIONS_PROVEN][] | Not Started | +Tool Setup | [SIM_ALT_TOOL_SETUP][] | Not Started | +Regression | [SIM_SMOKE_REGRESSION_SETUP][] | Not Started | +Regression | [SIM_NIGHTLY_REGRESSION_SETUP][] | Not Started | +Regression | [FPV_REGRESSION_SETUP][] | Not Started | +Coverage | [SIM_COVERAGE_MODEL_ADDED][] | Not Started | +Code Quality | [TB_LINT_SETUP][] | Not Started | +Integration | [PRE_VERIFIED_SUB_MODULES_V1][] | Not Started | +Review | [DESIGN_SPEC_REVIEWED][] | Not Started | +Review | [TESTPLAN_REVIEWED][] | Not Started | +Review | [STD_TEST_CATEGORIES_PLANNED][] | Not Started | Exception (?) +Review | [V2_CHECKLIST_SCOPED][] | Not Started | + +[DV_DOC_DRAFT_COMPLETED]: /doc/project_governance/checklist/README.md#dv_doc_draft_completed +[TESTPLAN_COMPLETED]: /doc/project_governance/checklist/README.md#testplan_completed +[TB_TOP_CREATED]: /doc/project_governance/checklist/README.md#tb_top_created +[PRELIMINARY_ASSERTION_CHECKS_ADDED]: /doc/project_governance/checklist/README.md#preliminary_assertion_checks_added +[SIM_TB_ENV_CREATED]: /doc/project_governance/checklist/README.md#sim_tb_env_created +[SIM_RAL_MODEL_GEN_AUTOMATED]: /doc/project_governance/checklist/README.md#sim_ral_model_gen_automated +[CSR_CHECK_GEN_AUTOMATED]: /doc/project_governance/checklist/README.md#csr_check_gen_automated +[TB_GEN_AUTOMATED]: /doc/project_governance/checklist/README.md#tb_gen_automated +[SIM_SMOKE_TEST_PASSING]: /doc/project_governance/checklist/README.md#sim_smoke_test_passing +[SIM_CSR_MEM_TEST_SUITE_PASSING]: /doc/project_governance/checklist/README.md#sim_csr_mem_test_suite_passing +[FPV_MAIN_ASSERTIONS_PROVEN]: /doc/project_governance/checklist/README.md#fpv_main_assertions_proven +[SIM_ALT_TOOL_SETUP]: /doc/project_governance/checklist/README.md#sim_alt_tool_setup +[SIM_SMOKE_REGRESSION_SETUP]: /doc/project_governance/checklist/README.md#sim_smoke_regression_setup +[SIM_NIGHTLY_REGRESSION_SETUP]: /doc/project_governance/checklist/README.md#sim_nightly_regression_setup +[FPV_REGRESSION_SETUP]: /doc/project_governance/checklist/README.md#fpv_regression_setup +[SIM_COVERAGE_MODEL_ADDED]: /doc/project_governance/checklist/README.md#sim_coverage_model_added +[TB_LINT_SETUP]: /doc/project_governance/checklist/README.md#tb_lint_setup +[PRE_VERIFIED_SUB_MODULES_V1]: /doc/project_governance/checklist/README.md#pre_verified_sub_modules_v1 +[DESIGN_SPEC_REVIEWED]: /doc/project_governance/checklist/README.md#design_spec_reviewed +[TESTPLAN_REVIEWED]: /doc/project_governance/checklist/README.md#testplan_reviewed +[STD_TEST_CATEGORIES_PLANNED]: /doc/project_governance/checklist/README.md#std_test_categories_planned +[V2_CHECKLIST_SCOPED]: /doc/project_governance/checklist/README.md#v2_checklist_scoped + +### V2 + + Type | Item | Resolution | Note/Collaterals +--------------|-----------------------------------------|-------------|------------------ +Documentation | [DESIGN_DELTAS_CAPTURED_V2][] | Not Started | +Documentation | [DV_DOC_COMPLETED][] | Not Started | +Testbench | [FUNCTIONAL_COVERAGE_IMPLEMENTED][] | Not Started | +Testbench | [ALL_INTERFACES_EXERCISED][] | Not Started | +Testbench | [ALL_ASSERTION_CHECKS_ADDED][] | Not Started | +Testbench | [SIM_TB_ENV_COMPLETED][] | Not Started | +Tests | [SIM_ALL_TESTS_PASSING][] | Not Started | +Tests | [FPV_ALL_ASSERTIONS_WRITTEN][] | Not Started | +Tests | [FPV_ALL_ASSUMPTIONS_REVIEWED][] | Not Started | +Tests | [SIM_FW_SIMULATED][] | Not Started | +Regression | [SIM_NIGHTLY_REGRESSION_V2][] | Not Started | +Coverage | [SIM_CODE_COVERAGE_V2][] | Not Started | +Coverage | [SIM_FUNCTIONAL_COVERAGE_V2][] | Not Started | +Coverage | [FPV_CODE_COVERAGE_V2][] | Not Started | +Coverage | [FPV_COI_COVERAGE_V2][] | Not Started | +Integration | [PRE_VERIFIED_SUB_MODULES_V2][] | Not Started | +Issues | [NO_HIGH_PRIORITY_ISSUES_PENDING][] | Not Started | +Issues | [ALL_LOW_PRIORITY_ISSUES_ROOT_CAUSED][] | Not Started | +Review | [DV_DOC_TESTPLAN_REVIEWED][] | Not Started | +Review | [V3_CHECKLIST_SCOPED][] | Not Started | + +[DESIGN_DELTAS_CAPTURED_V2]: /doc/project_governance/checklist/README.md#design_deltas_captured_v2 +[DV_DOC_COMPLETED]: /doc/project_governance/checklist/README.md#dv_doc_completed +[FUNCTIONAL_COVERAGE_IMPLEMENTED]: /doc/project_governance/checklist/README.md#functional_coverage_implemented +[ALL_INTERFACES_EXERCISED]: /doc/project_governance/checklist/README.md#all_interfaces_exercised +[ALL_ASSERTION_CHECKS_ADDED]: /doc/project_governance/checklist/README.md#all_assertion_checks_added +[SIM_TB_ENV_COMPLETED]: /doc/project_governance/checklist/README.md#sim_tb_env_completed +[SIM_ALL_TESTS_PASSING]: /doc/project_governance/checklist/README.md#sim_all_tests_passing +[FPV_ALL_ASSERTIONS_WRITTEN]: /doc/project_governance/checklist/README.md#fpv_all_assertions_written +[FPV_ALL_ASSUMPTIONS_REVIEWED]: /doc/project_governance/checklist/README.md#fpv_all_assumptions_reviewed +[SIM_FW_SIMULATED]: /doc/project_governance/checklist/README.md#sim_fw_simulated +[SIM_NIGHTLY_REGRESSION_V2]: /doc/project_governance/checklist/README.md#sim_nightly_regression_v2 +[SIM_CODE_COVERAGE_V2]: /doc/project_governance/checklist/README.md#sim_code_coverage_v2 +[SIM_FUNCTIONAL_COVERAGE_V2]: /doc/project_governance/checklist/README.md#sim_functional_coverage_v2 +[FPV_CODE_COVERAGE_V2]: /doc/project_governance/checklist/README.md#fpv_code_coverage_v2 +[FPV_COI_COVERAGE_V2]: /doc/project_governance/checklist/README.md#fpv_coi_coverage_v2 +[PRE_VERIFIED_SUB_MODULES_V2]: /doc/project_governance/checklist/README.md#pre_verified_sub_modules_v2 +[NO_HIGH_PRIORITY_ISSUES_PENDING]: /doc/project_governance/checklist/README.md#no_high_priority_issues_pending +[ALL_LOW_PRIORITY_ISSUES_ROOT_CAUSED]:/doc/project_governance/checklist/README.md#all_low_priority_issues_root_caused +[DV_DOC_TESTPLAN_REVIEWED]: /doc/project_governance/checklist/README.md#dv_doc_testplan_reviewed +[V3_CHECKLIST_SCOPED]: /doc/project_governance/checklist/README.md#v3_checklist_scoped + +### V2S + + Type | Item | Resolution | Note/Collaterals +--------------|-----------------------------------------|-------------|------------------ +Documentation | [SEC_CM_TESTPLAN_COMPLETED][] | Not Started | +Tests | [FPV_SEC_CM_VERIFIED][] | Not Started | +Tests | [SIM_SEC_CM_VERIFIED][] | Not Started | +Coverage | [SIM_COVERAGE_REVIEWED][] | Not Started | +Review | [SEC_CM_DV_REVIEWED][] | Not Started | + +[SEC_CM_TESTPLAN_COMPLETED]: /doc/project_governance/checklist/README.md#sec_cm_testplan_completed +[FPV_SEC_CM_VERIFIED]: /doc/project_governance/checklist/README.md#fpv_sec_cm_verified +[SIM_SEC_CM_VERIFIED]: /doc/project_governance/checklist/README.md#sim_sec_cm_verified +[SIM_COVERAGE_REVIEWED]: /doc/project_governance/checklist/README.md#sim_coverage_reviewed +[SEC_CM_DV_REVIEWED]: /doc/project_governance/checklist/README.md#sec_cm_dv_reviewed + +### V3 + + Type | Item | Resolution | Note/Collaterals +--------------|-----------------------------------|-------------|------------------ +Documentation | [DESIGN_DELTAS_CAPTURED_V3][] | Not Started | +Tests | [X_PROP_ANALYSIS_COMPLETED][] | Not Started | +Tests | [FPV_ASSERTIONS_PROVEN_AT_V3][] | Not Started | +Regression | [SIM_NIGHTLY_REGRESSION_AT_V3][] | Not Started | +Coverage | [SIM_CODE_COVERAGE_AT_100][] | Not Started | +Coverage | [SIM_FUNCTIONAL_COVERAGE_AT_100][]| Not Started | +Coverage | [FPV_CODE_COVERAGE_AT_100][] | Not Started | +Coverage | [FPV_COI_COVERAGE_AT_100][] | Not Started | +Code Quality | [ALL_TODOS_RESOLVED][] | Not Started | +Code Quality | [NO_TOOL_WARNINGS_THROWN][] | Not Started | +Code Quality | [TB_LINT_COMPLETE][] | Not Started | +Integration | [PRE_VERIFIED_SUB_MODULES_V3][] | Not Started | +Issues | [NO_ISSUES_PENDING][] | Not Started | +Review | Reviewer(s) | Not Started | +Review | Signoff date | Not Started | + +[DESIGN_DELTAS_CAPTURED_V3]: /doc/project_governance/checklist/README.md#design_deltas_captured_v3 +[X_PROP_ANALYSIS_COMPLETED]: /doc/project_governance/checklist/README.md#x_prop_analysis_completed +[FPV_ASSERTIONS_PROVEN_AT_V3]: /doc/project_governance/checklist/README.md#fpv_assertions_proven_at_v3 +[SIM_NIGHTLY_REGRESSION_AT_V3]: /doc/project_governance/checklist/README.md#sim_nightly_regression_at_v3 +[SIM_CODE_COVERAGE_AT_100]: /doc/project_governance/checklist/README.md#sim_code_coverage_at_100 +[SIM_FUNCTIONAL_COVERAGE_AT_100]:/doc/project_governance/checklist/README.md#sim_functional_coverage_at_100 +[FPV_CODE_COVERAGE_AT_100]: /doc/project_governance/checklist/README.md#fpv_code_coverage_at_100 +[FPV_COI_COVERAGE_AT_100]: /doc/project_governance/checklist/README.md#fpv_coi_coverage_at_100 +[ALL_TODOS_RESOLVED]: /doc/project_governance/checklist/README.md#all_todos_resolved +[NO_TOOL_WARNINGS_THROWN]: /doc/project_governance/checklist/README.md#no_tool_warnings_thrown +[TB_LINT_COMPLETE]: /doc/project_governance/checklist/README.md#tb_lint_complete +[PRE_VERIFIED_SUB_MODULES_V3]: /doc/project_governance/checklist/README.md#pre_verified_sub_modules_v3 +[NO_ISSUES_PENDING]: /doc/project_governance/checklist/README.md#no_issues_pending diff --git a/hw/top_darjeeling/ip_autogen/ac_range_check/dv/README.md b/hw/top_darjeeling/ip_autogen/ac_range_check/dv/README.md new file mode 100644 index 0000000000000..3f18cdfe262c4 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/ac_range_check/dv/README.md @@ -0,0 +1,129 @@ +# AC_RANGE_CHECK DV document + +## Goals +* **DV** + * Verify all AC_RANGE_CHECK IP features by running dynamic simulations with a SV/UVM based testbench + * Develop and run all tests based on the [testplan](#testplan) below towards closing code and functional coverage on the IP and all of its sub-modules +* **FPV** + * Verify TileLink device protocol compliance with an SVA based testbench + +## Current status +* [Design & verification stage](../../../../README.md) + * [HW development stages](../../../../../doc/project_governance/development_stages.md) +* [Simulation results](https://reports.opentitan.org/hw/top_darjeeling/ip_autogen/ac_range_check/dv/latest/report.html) + +## Design features +For detailed information on `ac_range_check` design features, please see the [`ac_range_check` HWIP technical specification](../README.md). + +## Testbench architecture +The `ac_range_check` UVM DV testbench has been constructed based on the [CIP testbench architecture](../../../../dv/sv/cip_lib/README.md). + +### Block diagram +![Block diagram](./doc/tb.svg) + +### Top level testbench +Top level testbench is located at `hw/top_darjeeling/ip_autogen/ac_range_check/dv/tb/tb.sv`. +It instantiates the `ac_range_check` DUT module `hw/ip/ac_range_check/rtl/ac_range_check.sv`. +In addition, the testbench instantiates the following interfaces, connects them to the DUT and sets their handle into `uvm_config_db`: +* [Clock and reset interface](../../../../dv/sv/common_ifs/README.md) +* [Reset shadowed interface](../../../../dv/sv/common_ifs/README.md) // TODO add something in this doc about this interface. +* [TileLink host interface for the CSRs](../../../../dv/sv/tl_agent/README.md) +* [TileLink host interface for the Unfiltered CTN accesses](../../../../dv/sv/tl_agent/README.md) +* [TileLink device interface for the Filtered CTN accesses](../../../../dv/sv/tl_agent/README.md) +* Interrupts ([`pins_if`](../../../../dv/sv/common_ifs/README.md)) +* Alerts ([`alert_esc_if`](../../../../dv/sv/alert_esc_agent/README.md)) + + +### Common DV utility components +The following utilities provide generic helper tasks and functions to perform activities that are common across the project: +* [dv_utils_pkg](../../../../dv/sv/dv_utils/README.md) +* [csr_utils_pkg](../../../../dv/sv/csr_utils/README.md) + +### Compile-time configurations +[list compile time configurations, if any and what are they used for] + +### Global types & methods +All common types and methods defined at the package level can be found in `ac_range_check_env_pkg`. +Some of them in use are: +```systemverilog +[list a few parameters, types & methods; no need to mention all] +``` + +### TL_agent +* `ac_range_check` UVM environment instantiates a (already handled in CIP base env) [tl_agent](../../../../dv/sv/tl_agent/README.md) which provides the ability to drive and independently monitor random traffic via TL host interface into `ac_range_check` device, to access to the CSRs (Control/Status Registers). +* Host interface to the Unfiltered CTN accesses. +* Device interface to the Filtered CTN accesses. + +The `tl_agent` monitor supplies partial TileLink request packets as well as completed TileLink response packets over the TLM analysis port for further processing within the `ac_range_check` scoreboard. + +### Alert_agent +`ac_range_check` testbench instantiates (already handled in CIP base env) [alert_agents](../../../../dv/sv/alert_esc_agent/README.md): +[list alert names]. +The alert_agents provide the ability to drive and independently monitor alert handshakes via alert interfaces in AC_RANGE_CHECK device. + +### UVM RAL Model +The `ac_range_check` RAL model is created with the [`ralgen`](../../../../dv/tools/ralgen/README.md) FuseSoC generator script automatically when the simulation is at the build stage. + +It can be created manually by invoking [`regtool`](../../../../../util/reggen/doc/setup_and_use.md): + +#### Sequence cfg +An efficient way to develop test sequences is by providing some random variables that are used to configure the DUT / drive stimulus. +The random variables are constrained using weights and knobs that can be controlled. +These weights and knobs take on a "default" value that will result in the widest exploration of the design state space, when the test sequence is randomized and run as-is. +To steer the randomization towards a particular distribution or to achieve interesting combinations of the random variables, the test sequence can be extended to create a specialized variant. +In this extended sequence, nothing would need to be done, other than setting those weights and knobs appropriately. +This helps increase the likelihood of hitting the design corners that would otherwise be difficult to achieve, while maximizing reuse. + +This object aims to provide such run-time controls. + +#### Env cfg +The `ac_range_check_env_cfg`, environment configuration object provides access to the following elements: +* Build-time controls to configure the UVM environment composition during the `build_phase` +* Downstream agent configuration objects for ease of lookup from any environment component + * This includes the `tl_agent_cfg` objects for both TL interfaces +* All virtual interfaces that connect to the DUT listed above (retrieved from the `uvm_config_db`) +* Sequence configuration object described above + +All environment components contain a handle to an instance of this class (that was created in the test class via the parent `dv_base_test`). +By housing all of the above, all pertinent information is more easily shared with all environment components. + +### Stimulus strategy +#### Test sequences +All test sequences reside in `hw/top_darjeeling/ip_autogen/ac_range_check/dv/env/seq_lib`. +The `ac_range_check_base_vseq` virtual sequence is extended from `cip_base_vseq` and serves as a starting point. +All test sequences are extended from `ac_range_check_base_vseq`. +It provides commonly used handles, variables, functions and tasks that the test sequences can simple use / call. +Some of the most commonly used tasks / functions are as follows: From `hw/top_darjeeling/ip_autogen/ac_range_check/dv/env/seq/ac_range_check_base_vseq.sv`, +* task 1: +* task 2: + +#### Functional coverage +To ensure high quality constrained random stimulus, it is necessary to develop a functional coverage model. +The following covergroups have been developed to prove that the test intent has been adequately met: +* cg1: +* cg2: + +### Self-checking strategy +#### Scoreboard +It creates the following analysis ports to retrieve the data monitored by corresponding interface agents: +* analysis port1: +* analysis port2: + + +#### Assertions +* TLUL assertions: The `hw/top_darjeeling/ip_autogen/ac_range_check/dv/sva/ac_range_check_bind.sv` binds the `tlul_assert` [assertions](../../../../ip/tlul/doc/TlulProtocolChecker.md) to the IP to ensure TileLink interface protocol compliance. +* Unknown checks on DUT outputs: The RTL has assertions to ensure all outputs are initialized to known values after coming out of reset. +* assert prop 1: +* assert prop 2: + +## Building and running tests +We are using our in-house developed [regression tool](../../../../../util/dvsim/README.md) for building and running our tests and regressions. +Please take a look at the link for detailed information on the usage, capabilities, features and known issues. +Here's how to run a smoke test: +```console +$ cd $REPO_TOP +$ ./util/dvsim/dvsim.py hw/top_darjeeling/ip_autogen/ac_range_check/dv/ac_range_check_sim_cfg.hjson -i ac_range_check_smoke +``` + +## Testplan +[Testplan](../data/ac_range_check_testplan.hjson) diff --git a/hw/top_darjeeling/ip_autogen/ac_range_check/dv/ac_range_check_sim.core b/hw/top_darjeeling/ip_autogen/ac_range_check/dv/ac_range_check_sim.core new file mode 100644 index 0000000000000..d71b1bc3feb72 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/ac_range_check/dv/ac_range_check_sim.core @@ -0,0 +1,31 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:opentitan:top_darjeeling_ac_range_check_sim:0.1 +description: "AC_RANGE_CHECK DV sim target" +filesets: + files_rtl: + depend: + - lowrisc:ip:tlul + - lowrisc:opentitan:top_darjeeling_ac_range_check:0.1 + file_type: systemVerilogSource + + files_dv: + depend: + - lowrisc:opentitan:top_darjeeling_ac_range_check_test + - lowrisc:opentitan:top_darjeeling_ac_range_check_sva + files: + - tb/tb.sv + file_type: systemVerilogSource + +targets: + sim: &sim_target + toplevel: tb + filesets: + - files_rtl + - files_dv + default_tool: vcs + + lint: + <<: *sim_target diff --git a/hw/top_darjeeling/ip_autogen/ac_range_check/dv/ac_range_check_sim_cfg.hjson b/hw/top_darjeeling/ip_autogen/ac_range_check/dv/ac_range_check_sim_cfg.hjson new file mode 100644 index 0000000000000..30a5461b046da --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/ac_range_check/dv/ac_range_check_sim_cfg.hjson @@ -0,0 +1,63 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ + // Name of the sim cfg - typically same as the name of the DUT. + name: ac_range_check + + // Top level dut name (sv module). + dut: ac_range_check + + // Top level testbench name (sv module). + tb: tb + + // Simulator used to sign off this block + tool: xcelium + + // Fusesoc core file used for building the file list. + fusesoc_core: lowrisc:opentitan:top_darjeeling_ac_range_check_sim:0.1 + + // Testplan hjson file. + testplan: "{self_dir}/../data/ac_range_check_testplan.hjson" + + // Import additional common sim cfg files. + import_cfgs: [// Project wide common sim cfg file + "{proj_root}/hw/dv/tools/dvsim/common_sim_cfg.hjson", + // Common CIP test lists + "{proj_root}/hw/dv/tools/dvsim/tests/csr_tests.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/mem_tests.hjson", // TODO MVy needed? + "{proj_root}/hw/dv/tools/dvsim/tests/intr_test.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/alert_test.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/shadow_reg_errors_tests.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/tl_access_tests.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/sec_cm_tests.hjson", // TODO MVy needed? + "{proj_root}/hw/dv/tools/dvsim/tests/stress_tests.hjson"] + + // Add additional tops for simulation. + sim_tops: ["ac_range_check_bind"] + + // Default iterations for all tests - each test entry can override this. + reseed: 50 + + // Default UVM test and seq class name. + uvm_test: ac_range_check_base_test + uvm_test_seq: ac_range_check_base_vseq + + // List of test specifications. + tests: [ + { + name: ac_range_check_smoke + uvm_test_seq: ac_range_check_smoke_vseq + } + + // TODO: add more tests here + ] + + // List of regressions. + regressions: [ + { + name: smoke + tests: ["ac_range_check_smoke"] + } + ] +} diff --git a/hw/top_darjeeling/ip_autogen/ac_range_check/dv/env/ac_range_check_env.core b/hw/top_darjeeling/ip_autogen/ac_range_check/dv/env/ac_range_check_env.core new file mode 100644 index 0000000000000..a1c4e4ae64d78 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/ac_range_check/dv/env/ac_range_check_env.core @@ -0,0 +1,40 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:opentitan:top_darjeeling_ac_range_check_env:0.1 +description: "AC_RANGE_CHECK DV UVM environment" +filesets: + files_dv: + depend: + - lowrisc:dv:ralgen + - lowrisc:dv:cip_lib + - lowrisc:dv:dv_base_reg + - lowrisc:dv:dv_lib + files: + - ac_range_check_env_pkg.sv + - ac_range_check_ral_pkg.sv + - ac_range_check_env_cfg.sv: {is_include_file: true} + - ac_range_check_env_cov.sv: {is_include_file: true} + - ac_range_check_virtual_sequencer.sv: {is_include_file: true} + - ac_range_check_scoreboard.sv: {is_include_file: true} + - ac_range_check_env.sv: {is_include_file: true} + - seq_lib/ac_range_check_vseq_list.sv: {is_include_file: true} + - seq_lib/ac_range_check_base_vseq.sv: {is_include_file: true} + - seq_lib/ac_range_check_common_vseq.sv: {is_include_file: true} + - seq_lib/ac_range_check_smoke_vseq.sv: {is_include_file: true} + file_type: systemVerilogSource + +generate: + ral: + generator: ralgen + parameters: + name: ac_range_check + ip_hjson: ../../data/ac_range_check.hjson + +targets: + default: + filesets: + - files_dv + generate: + - ral diff --git a/hw/top_darjeeling/ip_autogen/ac_range_check/dv/env/ac_range_check_env.sv b/hw/top_darjeeling/ip_autogen/ac_range_check/dv/env/ac_range_check_env.sv new file mode 100644 index 0000000000000..ab3fc70d125d2 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/ac_range_check/dv/env/ac_range_check_env.sv @@ -0,0 +1,63 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class ac_range_check_env extends cip_base_env #( + .CFG_T (ac_range_check_env_cfg), + .COV_T (ac_range_check_env_cov), + .VIRTUAL_SEQUENCER_T(ac_range_check_virtual_sequencer), + .SCOREBOARD_T (ac_range_check_scoreboard) + ); + `uvm_component_utils(ac_range_check_env) + + tl_agent tl_csr_agt; + tl_agent tl_unfilt_agt; + tl_agent tl_filt_agt; + + // Standard SV/UVM methods + extern function new(string name="", uvm_component parent=null); + extern function void build_phase(uvm_phase phase); + extern function void connect_phase(uvm_phase phase); +endclass : ac_range_check_env + + +function ac_range_check_env::new(string name="", uvm_component parent=null); + super.new(name, parent); +endfunction : new + +function void ac_range_check_env::build_phase(uvm_phase phase); + super.build_phase(phase); + + // Create CSR TL agent + tl_csr_agt = tl_agent::type_id::create("tl_csr_agt", this); + uvm_config_db#(tl_agent_cfg)::set(this, "tl_csr_agt*", "cfg", cfg.tl_csr_agt_cfg); + cfg.tl_csr_agt_cfg.en_cov = cfg.en_cov; + + // Create Unfiltered TL agent + tl_unfilt_agt = tl_agent::type_id::create("tl_unfilt_agt", this); + uvm_config_db#(tl_agent_cfg)::set(this, "tl_unfilt_agt*", "cfg", cfg.tl_unfilt_agt_cfg); + cfg.tl_unfilt_agt_cfg.en_cov = cfg.en_cov; + + // Create Fltered TL agent + tl_filt_agt = tl_agent::type_id::create("tl_filt_agt", this); + uvm_config_db#(tl_agent_cfg)::set(this, "tl_filt_agt*", "cfg", cfg.tl_filt_agt_cfg); + cfg.tl_filt_agt_cfg.en_cov = cfg.en_cov; +endfunction : build_phase + +function void ac_range_check_env::connect_phase(uvm_phase phase); + super.connect_phase(phase); + if (cfg.en_scb) begin + tl_csr_agt.monitor.analysis_port.connect(scoreboard.tl_csr_fifo.analysis_export); + tl_unfilt_agt.monitor.analysis_port.connect(scoreboard.tl_unfilt_fifo.analysis_export); + tl_filt_agt.monitor.analysis_port.connect(scoreboard.tl_filt_fifo.analysis_export); + end + if (cfg.is_active && cfg.tl_csr_agt_cfg.is_active) begin + virtual_sequencer.tl_csr_sqr = tl_csr_agt.sequencer; + end + if (cfg.is_active && cfg.tl_unfilt_agt_cfg.is_active) begin + virtual_sequencer.tl_unfilt_sqr = tl_unfilt_agt.sequencer; + end + if (cfg.is_active && cfg.tl_filt_agt_cfg.is_active) begin + virtual_sequencer.tl_filt_sqr = tl_filt_agt.sequencer; + end +endfunction : connect_phase diff --git a/hw/top_darjeeling/ip_autogen/ac_range_check/dv/env/ac_range_check_env_cfg.sv b/hw/top_darjeeling/ip_autogen/ac_range_check/dv/env/ac_range_check_env_cfg.sv new file mode 100644 index 0000000000000..b4e1f6a6872bb --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/ac_range_check/dv/env/ac_range_check_env_cfg.sv @@ -0,0 +1,47 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class ac_range_check_env_cfg extends cip_base_env_cfg #(.RAL_T(ac_range_check_reg_block)); + + // External component config objects + rand tl_agent_cfg tl_csr_agt_cfg; + rand tl_agent_cfg tl_unfilt_agt_cfg; + rand tl_agent_cfg tl_filt_agt_cfg; + + `uvm_object_utils_begin(ac_range_check_env_cfg) + `uvm_field_object(tl_csr_agt_cfg, UVM_DEFAULT) + `uvm_field_object(tl_unfilt_agt_cfg, UVM_DEFAULT) + `uvm_field_object(tl_filt_agt_cfg, UVM_DEFAULT) + `uvm_object_utils_end + + // Standard SV/UVM methods + extern function new(string name=""); + + // Class specific methods + extern function void initialize(bit [31:0] csr_base_addr = '1); +endclass : ac_range_check_env_cfg + + +function ac_range_check_env_cfg::new(string name=""); + super.new(name); +endfunction : new + +function void ac_range_check_env_cfg::initialize(bit [31:0] csr_base_addr = '1); + list_of_alerts = ac_range_check_env_pkg::LIST_OF_ALERTS; + super.initialize(csr_base_addr); + // Create tl_csr agent config obj + tl_csr_agt_cfg = tl_agent_cfg::type_id::create("tl_csr_agt_cfg"); + // Create tl_unfilt agent config obj + tl_unfilt_agt_cfg = tl_agent_cfg::type_id::create("tl_unfilt_agt_cfg"); + // Create tl_filt agent config obj + tl_filt_agt_cfg = tl_agent_cfg::type_id::create("tl_filt_agt_cfg"); + + // Set num_interrupts + begin + uvm_reg rg = ral.get_reg_by_name("intr_state"); + if (rg != null) begin + num_interrupts = ral.intr_state.get_n_used_bits(); + end + end +endfunction : initialize diff --git a/hw/top_darjeeling/ip_autogen/ac_range_check/dv/env/ac_range_check_env_cov.sv b/hw/top_darjeeling/ip_autogen/ac_range_check/dv/env/ac_range_check_env_cov.sv new file mode 100644 index 0000000000000..c5068f7a7da75 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/ac_range_check/dv/env/ac_range_check_env_cov.sv @@ -0,0 +1,36 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +/** + * Covergoups that are dependent on run-time parameters that may be available + * only in build_phase can be defined here + * Covergroups may also be wrapped inside helper classes if needed. + */ + +class ac_range_check_env_cov extends cip_base_env_cov #(.CFG_T(ac_range_check_env_cfg)); + `uvm_component_utils(ac_range_check_env_cov) + + // The base class provides the following handles for use: + // ac_range_check_env_cfg: cfg + + // Covergroups + // TODO MVy [add covergroups here] + + // Standard SV/UVM methods + extern function new(string name, uvm_component parent); + extern function void build_phase(uvm_phase phase); +endclass : ac_range_check_env_cov + + +function ac_range_check_env_cov::new(string name, uvm_component parent); + super.new(name, parent); + // TODO MVy [instantiate covergroups here] +endfunction : new + +function void ac_range_check_env_cov::build_phase(uvm_phase phase); + super.build_phase(phase); + // TODO MVy [or instantiate covergroups here] + // Please instantiate sticky_intr_cov array of objects for all interrupts that are sticky + // See cip_base_env_cov for details +endfunction : build_phase diff --git a/hw/top_darjeeling/ip_autogen/ac_range_check/dv/env/ac_range_check_env_pkg.sv b/hw/top_darjeeling/ip_autogen/ac_range_check/dv/env/ac_range_check_env_pkg.sv new file mode 100644 index 0000000000000..ce22c57c0ff38 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/ac_range_check/dv/env/ac_range_check_env_pkg.sv @@ -0,0 +1,40 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +package ac_range_check_env_pkg; + // Dep packages + import uvm_pkg::*; + import top_pkg::*; + import dv_utils_pkg::*; + import tl_agent_pkg::*; + import dv_lib_pkg::*; + import cip_base_pkg::*; + import dv_base_reg_pkg::*; + import csr_utils_pkg::*; + import ac_range_check_ral_pkg::*; + + // Macro includes + `include "uvm_macros.svh" + `include "dv_macros.svh" + + // Parameters + // TODO MVy check order is correct + parameter uint NUM_ALERTS = 2; + parameter string LIST_OF_ALERTS[] = {"recov_ctrl_update_err", "fatal_fault"}; + + // Types + typedef enum int { + DenyCntReached = 0 + } ac_range_check_intr_e; + + // Functions + + // Package sources + `include "ac_range_check_env_cfg.sv" + `include "ac_range_check_env_cov.sv" + `include "ac_range_check_virtual_sequencer.sv" + `include "ac_range_check_scoreboard.sv" + `include "ac_range_check_env.sv" + `include "ac_range_check_vseq_list.sv" +endpackage : ac_range_check_env_pkg diff --git a/hw/top_darjeeling/ip_autogen/ac_range_check/dv/env/ac_range_check_ral_pkg.sv b/hw/top_darjeeling/ip_autogen/ac_range_check/dv/env/ac_range_check_ral_pkg.sv new file mode 100644 index 0000000000000..96836c25e8e43 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/ac_range_check/dv/env/ac_range_check_ral_pkg.sv @@ -0,0 +1,3595 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// UVM Registers auto-generated by `reggen` containing data structure +package ac_range_check_ral_pkg; + // dep packages + import uvm_pkg::*; + import dv_base_reg_pkg::*; + + // macro includes + `include "uvm_macros.svh" + + // Forward declare all register/memory/block classes + typedef class ac_range_check_reg_intr_state; + typedef class ac_range_check_reg_intr_enable; + typedef class ac_range_check_reg_intr_test; + typedef class ac_range_check_reg_alert_test; + typedef class ac_range_check_reg_log_config; + typedef class ac_range_check_reg_log_status; + typedef class ac_range_check_reg_log_address; + typedef class ac_range_check_reg_range_regwen; + typedef class ac_range_check_reg_range_base; + typedef class ac_range_check_reg_range_limit; + typedef class ac_range_check_reg_range_perm; + typedef class ac_range_check_reg_range_racl_policy_shadowed; + typedef class ac_range_check_reg_block; + + class ac_range_check_reg_intr_state extends dv_base_reg; + // fields + rand dv_base_reg_field deny_cnt_reached; + + `uvm_object_utils(ac_range_check_reg_intr_state) + + function new(string name = "ac_range_check_reg_intr_state", + int unsigned n_bits = 32, + int has_coverage = UVM_NO_COVERAGE); + super.new(name, n_bits, has_coverage); + endfunction : new + + virtual function void build(csr_excl_item csr_excl = null); + deny_cnt_reached = + (dv_base_reg_field:: + type_id::create("deny_cnt_reached")); + deny_cnt_reached.configure( + .parent(this), + .size(1), + .lsb_pos(0), + .access("W1C"), + .mubi_access("NONE"), + .volatile(1), + .reset(32'h0), + .has_reset(1), + .is_rand(1), + .individually_accessible(1)); + + deny_cnt_reached.set_original_access("W1C"); + endfunction : build + endclass : ac_range_check_reg_intr_state + + class ac_range_check_reg_intr_enable extends dv_base_reg; + // fields + rand dv_base_reg_field deny_cnt_reached; + + `uvm_object_utils(ac_range_check_reg_intr_enable) + + function new(string name = "ac_range_check_reg_intr_enable", + int unsigned n_bits = 32, + int has_coverage = UVM_NO_COVERAGE); + super.new(name, n_bits, has_coverage); + endfunction : new + + virtual function void build(csr_excl_item csr_excl = null); + deny_cnt_reached = + (dv_base_reg_field:: + type_id::create("deny_cnt_reached")); + deny_cnt_reached.configure( + .parent(this), + .size(1), + .lsb_pos(0), + .access("RW"), + .mubi_access("NONE"), + .volatile(0), + .reset(32'h0), + .has_reset(1), + .is_rand(1), + .individually_accessible(1)); + + deny_cnt_reached.set_original_access("RW"); + endfunction : build + endclass : ac_range_check_reg_intr_enable + + class ac_range_check_reg_intr_test extends dv_base_reg; + // fields + rand dv_base_reg_field deny_cnt_reached; + + `uvm_object_utils(ac_range_check_reg_intr_test) + + function new(string name = "ac_range_check_reg_intr_test", + int unsigned n_bits = 32, + int has_coverage = UVM_NO_COVERAGE); + super.new(name, n_bits, has_coverage); + endfunction : new + + virtual function void build(csr_excl_item csr_excl = null); + deny_cnt_reached = + (dv_base_reg_field:: + type_id::create("deny_cnt_reached")); + deny_cnt_reached.configure( + .parent(this), + .size(1), + .lsb_pos(0), + .access("WO"), + .mubi_access("NONE"), + .volatile(0), + .reset(32'h0), + .has_reset(1), + .is_rand(1), + .individually_accessible(1)); + + deny_cnt_reached.set_original_access("WO"); + set_is_ext_reg(1); + endfunction : build + endclass : ac_range_check_reg_intr_test + + class ac_range_check_reg_alert_test extends dv_base_reg; + // fields + rand dv_base_reg_field recov_ctrl_update_err; + rand dv_base_reg_field fatal_fault; + + `uvm_object_utils(ac_range_check_reg_alert_test) + + function new(string name = "ac_range_check_reg_alert_test", + int unsigned n_bits = 32, + int has_coverage = UVM_NO_COVERAGE); + super.new(name, n_bits, has_coverage); + endfunction : new + + virtual function void build(csr_excl_item csr_excl = null); + recov_ctrl_update_err = + (dv_base_reg_field:: + type_id::create("recov_ctrl_update_err")); + recov_ctrl_update_err.configure( + .parent(this), + .size(1), + .lsb_pos(0), + .access("WO"), + .mubi_access("NONE"), + .volatile(0), + .reset(32'h0), + .has_reset(1), + .is_rand(1), + .individually_accessible(1)); + + recov_ctrl_update_err.set_original_access("WO"); + fatal_fault = + (dv_base_reg_field:: + type_id::create("fatal_fault")); + fatal_fault.configure( + .parent(this), + .size(1), + .lsb_pos(1), + .access("WO"), + .mubi_access("NONE"), + .volatile(0), + .reset(32'h0), + .has_reset(1), + .is_rand(1), + .individually_accessible(1)); + + fatal_fault.set_original_access("WO"); + set_is_ext_reg(1); + endfunction : build + endclass : ac_range_check_reg_alert_test + + class ac_range_check_reg_log_config extends dv_base_reg; + // fields + rand dv_base_reg_field log_enable; + rand dv_base_reg_field log_clear; + rand dv_base_reg_field deny_cnt_threshold; + + `uvm_object_utils(ac_range_check_reg_log_config) + + function new(string name = "ac_range_check_reg_log_config", + int unsigned n_bits = 32, + int has_coverage = UVM_NO_COVERAGE); + super.new(name, n_bits, has_coverage); + endfunction : new + + virtual function void build(csr_excl_item csr_excl = null); + log_enable = + (dv_base_reg_field:: + type_id::create("log_enable")); + log_enable.configure( + .parent(this), + .size(1), + .lsb_pos(0), + .access("RW"), + .mubi_access("NONE"), + .volatile(0), + .reset(32'h0), + .has_reset(1), + .is_rand(1), + .individually_accessible(1)); + + log_enable.set_original_access("RW"); + log_clear = + (dv_base_reg_field:: + type_id::create("log_clear")); + log_clear.configure( + .parent(this), + .size(1), + .lsb_pos(1), + .access("RW"), + .mubi_access("NONE"), + .volatile(0), + .reset(32'h0), + .has_reset(1), + .is_rand(1), + .individually_accessible(1)); + + log_clear.set_original_access("RW"); + deny_cnt_threshold = + (dv_base_reg_field:: + type_id::create("deny_cnt_threshold")); + deny_cnt_threshold.configure( + .parent(this), + .size(8), + .lsb_pos(2), + .access("RW"), + .mubi_access("NONE"), + .volatile(0), + .reset(32'h0), + .has_reset(1), + .is_rand(1), + .individually_accessible(1)); + + deny_cnt_threshold.set_original_access("RW"); + endfunction : build + endclass : ac_range_check_reg_log_config + + class ac_range_check_reg_log_status extends dv_base_reg; + // fields + rand dv_base_reg_field deny_cnt; + rand dv_base_reg_field denied_read_access; + rand dv_base_reg_field denied_write_access; + rand dv_base_reg_field denied_execute_access; + rand dv_base_reg_field denied_no_match; + rand dv_base_reg_field denied_racl_read; + rand dv_base_reg_field denied_racl_write; + rand dv_base_reg_field denied_source_role; + rand dv_base_reg_field denied_ctn_uid; + rand dv_base_reg_field deny_range_index; + + `uvm_object_utils(ac_range_check_reg_log_status) + + function new(string name = "ac_range_check_reg_log_status", + int unsigned n_bits = 32, + int has_coverage = UVM_NO_COVERAGE); + super.new(name, n_bits, has_coverage); + endfunction : new + + virtual function void build(csr_excl_item csr_excl = null); + deny_cnt = + (dv_base_reg_field:: + type_id::create("deny_cnt")); + deny_cnt.configure( + .parent(this), + .size(8), + .lsb_pos(0), + .access("RO"), + .mubi_access("NONE"), + .volatile(1), + .reset(32'h0), + .has_reset(1), + .is_rand(1), + .individually_accessible(1)); + + deny_cnt.set_original_access("RO"); + denied_read_access = + (dv_base_reg_field:: + type_id::create("denied_read_access")); + denied_read_access.configure( + .parent(this), + .size(1), + .lsb_pos(8), + .access("RO"), + .mubi_access("NONE"), + .volatile(1), + .reset(32'h0), + .has_reset(1), + .is_rand(1), + .individually_accessible(1)); + + denied_read_access.set_original_access("RO"); + denied_write_access = + (dv_base_reg_field:: + type_id::create("denied_write_access")); + denied_write_access.configure( + .parent(this), + .size(1), + .lsb_pos(9), + .access("RO"), + .mubi_access("NONE"), + .volatile(1), + .reset(32'h0), + .has_reset(1), + .is_rand(1), + .individually_accessible(1)); + + denied_write_access.set_original_access("RO"); + denied_execute_access = + (dv_base_reg_field:: + type_id::create("denied_execute_access")); + denied_execute_access.configure( + .parent(this), + .size(1), + .lsb_pos(10), + .access("RO"), + .mubi_access("NONE"), + .volatile(1), + .reset(32'h0), + .has_reset(1), + .is_rand(1), + .individually_accessible(1)); + + denied_execute_access.set_original_access("RO"); + denied_no_match = + (dv_base_reg_field:: + type_id::create("denied_no_match")); + denied_no_match.configure( + .parent(this), + .size(1), + .lsb_pos(11), + .access("RO"), + .mubi_access("NONE"), + .volatile(1), + .reset(32'h0), + .has_reset(1), + .is_rand(1), + .individually_accessible(1)); + + denied_no_match.set_original_access("RO"); + denied_racl_read = + (dv_base_reg_field:: + type_id::create("denied_racl_read")); + denied_racl_read.configure( + .parent(this), + .size(1), + .lsb_pos(12), + .access("RO"), + .mubi_access("NONE"), + .volatile(1), + .reset(32'h0), + .has_reset(1), + .is_rand(1), + .individually_accessible(1)); + + denied_racl_read.set_original_access("RO"); + denied_racl_write = + (dv_base_reg_field:: + type_id::create("denied_racl_write")); + denied_racl_write.configure( + .parent(this), + .size(1), + .lsb_pos(13), + .access("RO"), + .mubi_access("NONE"), + .volatile(1), + .reset(32'h0), + .has_reset(1), + .is_rand(1), + .individually_accessible(1)); + + denied_racl_write.set_original_access("RO"); + denied_source_role = + (dv_base_reg_field:: + type_id::create("denied_source_role")); + denied_source_role.configure( + .parent(this), + .size(4), + .lsb_pos(14), + .access("RO"), + .mubi_access("NONE"), + .volatile(1), + .reset(32'h0), + .has_reset(1), + .is_rand(1), + .individually_accessible(1)); + + denied_source_role.set_original_access("RO"); + denied_ctn_uid = + (dv_base_reg_field:: + type_id::create("denied_ctn_uid")); + denied_ctn_uid.configure( + .parent(this), + .size(5), + .lsb_pos(18), + .access("RO"), + .mubi_access("NONE"), + .volatile(1), + .reset(32'h0), + .has_reset(1), + .is_rand(1), + .individually_accessible(1)); + + denied_ctn_uid.set_original_access("RO"); + deny_range_index = + (dv_base_reg_field:: + type_id::create("deny_range_index")); + deny_range_index.configure( + .parent(this), + .size(5), + .lsb_pos(23), + .access("RO"), + .mubi_access("NONE"), + .volatile(1), + .reset(32'h0), + .has_reset(1), + .is_rand(1), + .individually_accessible(1)); + + deny_range_index.set_original_access("RO"); + endfunction : build + endclass : ac_range_check_reg_log_status + + class ac_range_check_reg_log_address extends dv_base_reg; + // fields + rand dv_base_reg_field log_address; + + `uvm_object_utils(ac_range_check_reg_log_address) + + function new(string name = "ac_range_check_reg_log_address", + int unsigned n_bits = 32, + int has_coverage = UVM_NO_COVERAGE); + super.new(name, n_bits, has_coverage); + endfunction : new + + virtual function void build(csr_excl_item csr_excl = null); + log_address = + (dv_base_reg_field:: + type_id::create("log_address")); + log_address.configure( + .parent(this), + .size(32), + .lsb_pos(0), + .access("RO"), + .mubi_access("NONE"), + .volatile(1), + .reset(32'h0), + .has_reset(1), + .is_rand(1), + .individually_accessible(1)); + + log_address.set_original_access("RO"); + endfunction : build + endclass : ac_range_check_reg_log_address + + class ac_range_check_reg_range_regwen extends dv_base_reg; + // fields + rand dv_base_reg_field regwen; + + `uvm_object_utils(ac_range_check_reg_range_regwen) + + function new(string name = "ac_range_check_reg_range_regwen", + int unsigned n_bits = 32, + int has_coverage = UVM_NO_COVERAGE); + super.new(name, n_bits, has_coverage); + endfunction : new + + virtual function void build(csr_excl_item csr_excl = null); + regwen = + (dv_base_reg_field:: + type_id::create("regwen")); + regwen.configure( + .parent(this), + .size(4), + .lsb_pos(0), + .access("RW"), + .mubi_access("W0C"), + .volatile(0), + .reset(32'h6), + .has_reset(1), + .is_rand(1), + .individually_accessible(1)); + + regwen.set_original_access("RW"); + regwen.set_mubi_width(4); + endfunction : build + endclass : ac_range_check_reg_range_regwen + + class ac_range_check_reg_range_base extends dv_base_reg; + // fields + rand dv_base_reg_field base; + + `uvm_object_utils(ac_range_check_reg_range_base) + + function new(string name = "ac_range_check_reg_range_base", + int unsigned n_bits = 32, + int has_coverage = UVM_NO_COVERAGE); + super.new(name, n_bits, has_coverage); + endfunction : new + + virtual function void build(csr_excl_item csr_excl = null); + base = + (dv_base_reg_field:: + type_id::create("base")); + base.configure( + .parent(this), + .size(30), + .lsb_pos(2), + .access("RW"), + .mubi_access("NONE"), + .volatile(0), + .reset(32'h0), + .has_reset(1), + .is_rand(1), + .individually_accessible(1)); + + base.set_original_access("RW"); + endfunction : build + endclass : ac_range_check_reg_range_base + + class ac_range_check_reg_range_limit extends dv_base_reg; + // fields + rand dv_base_reg_field limit; + + `uvm_object_utils(ac_range_check_reg_range_limit) + + function new(string name = "ac_range_check_reg_range_limit", + int unsigned n_bits = 32, + int has_coverage = UVM_NO_COVERAGE); + super.new(name, n_bits, has_coverage); + endfunction : new + + virtual function void build(csr_excl_item csr_excl = null); + limit = + (dv_base_reg_field:: + type_id::create("limit")); + limit.configure( + .parent(this), + .size(30), + .lsb_pos(2), + .access("RW"), + .mubi_access("NONE"), + .volatile(0), + .reset(32'h0), + .has_reset(1), + .is_rand(1), + .individually_accessible(1)); + + limit.set_original_access("RW"); + endfunction : build + endclass : ac_range_check_reg_range_limit + + class ac_range_check_reg_range_perm extends dv_base_reg; + // fields + rand dv_base_reg_field enable; + rand dv_base_reg_field read_access; + rand dv_base_reg_field write_access; + rand dv_base_reg_field execute_access; + rand dv_base_reg_field log_denied_access; + + `uvm_object_utils(ac_range_check_reg_range_perm) + + function new(string name = "ac_range_check_reg_range_perm", + int unsigned n_bits = 32, + int has_coverage = UVM_NO_COVERAGE); + super.new(name, n_bits, has_coverage); + endfunction : new + + virtual function void build(csr_excl_item csr_excl = null); + enable = + (dv_base_reg_field:: + type_id::create("enable")); + enable.configure( + .parent(this), + .size(4), + .lsb_pos(0), + .access("RW"), + .mubi_access("RW"), + .volatile(0), + .reset(32'h9), + .has_reset(1), + .is_rand(1), + .individually_accessible(1)); + + enable.set_original_access("RW"); + enable.set_mubi_width(4); + read_access = + (dv_base_reg_field:: + type_id::create("read_access")); + read_access.configure( + .parent(this), + .size(4), + .lsb_pos(4), + .access("RW"), + .mubi_access("RW"), + .volatile(0), + .reset(32'h9), + .has_reset(1), + .is_rand(1), + .individually_accessible(1)); + + read_access.set_original_access("RW"); + read_access.set_mubi_width(4); + write_access = + (dv_base_reg_field:: + type_id::create("write_access")); + write_access.configure( + .parent(this), + .size(4), + .lsb_pos(8), + .access("RW"), + .mubi_access("RW"), + .volatile(0), + .reset(32'h9), + .has_reset(1), + .is_rand(1), + .individually_accessible(1)); + + write_access.set_original_access("RW"); + write_access.set_mubi_width(4); + execute_access = + (dv_base_reg_field:: + type_id::create("execute_access")); + execute_access.configure( + .parent(this), + .size(4), + .lsb_pos(12), + .access("RW"), + .mubi_access("RW"), + .volatile(0), + .reset(32'h9), + .has_reset(1), + .is_rand(1), + .individually_accessible(1)); + + execute_access.set_original_access("RW"); + execute_access.set_mubi_width(4); + log_denied_access = + (dv_base_reg_field:: + type_id::create("log_denied_access")); + log_denied_access.configure( + .parent(this), + .size(4), + .lsb_pos(16), + .access("RW"), + .mubi_access("RW"), + .volatile(0), + .reset(32'h6), + .has_reset(1), + .is_rand(1), + .individually_accessible(1)); + + log_denied_access.set_original_access("RW"); + log_denied_access.set_mubi_width(4); + endfunction : build + endclass : ac_range_check_reg_range_perm + + class ac_range_check_reg_range_racl_policy_shadowed extends dv_base_reg; + // fields + rand dv_base_reg_field read_perm; + rand dv_base_reg_field write_perm; + + `uvm_object_utils(ac_range_check_reg_range_racl_policy_shadowed) + + function new(string name = "ac_range_check_reg_range_racl_policy_shadowed", + int unsigned n_bits = 32, + int has_coverage = UVM_NO_COVERAGE); + super.new(name, n_bits, has_coverage); + endfunction : new + + virtual function void build(csr_excl_item csr_excl = null); + read_perm = + (dv_base_reg_field:: + type_id::create("read_perm")); + read_perm.configure( + .parent(this), + .size(16), + .lsb_pos(0), + .access("RW"), + .mubi_access("NONE"), + .volatile(0), + .reset(32'h0), + .has_reset(1), + .is_rand(1), + .individually_accessible(1)); + + read_perm.set_original_access("RW"); + write_perm = + (dv_base_reg_field:: + type_id::create("write_perm")); + write_perm.configure( + .parent(this), + .size(16), + .lsb_pos(16), + .access("RW"), + .mubi_access("NONE"), + .volatile(0), + .reset(32'h0), + .has_reset(1), + .is_rand(1), + .individually_accessible(1)); + + write_perm.set_original_access("RW"); + endfunction : build + endclass : ac_range_check_reg_range_racl_policy_shadowed + + class ac_range_check_reg_block extends dv_base_reg_block; + // registers + rand ac_range_check_reg_intr_state intr_state; + rand ac_range_check_reg_intr_enable intr_enable; + rand ac_range_check_reg_intr_test intr_test; + rand ac_range_check_reg_alert_test alert_test; + rand ac_range_check_reg_log_config log_config; + rand ac_range_check_reg_log_status log_status; + rand ac_range_check_reg_log_address log_address; + rand ac_range_check_reg_range_regwen range_regwen[32]; + rand ac_range_check_reg_range_base range_base[32]; + rand ac_range_check_reg_range_limit range_limit[32]; + rand ac_range_check_reg_range_perm range_perm[32]; + rand ac_range_check_reg_range_racl_policy_shadowed range_racl_policy_shadowed[32]; + + `uvm_object_utils(ac_range_check_reg_block) + + function new(string name = "ac_range_check_reg_block", + int has_coverage = UVM_NO_COVERAGE); + super.new(name, has_coverage); + endfunction : new + + virtual function void build(uvm_reg_addr_t base_addr, + csr_excl_item csr_excl = null); + // create default map + this.default_map = create_map(.name("default_map"), + .base_addr(base_addr), + .n_bytes(4), + .endian(UVM_LITTLE_ENDIAN)); + if (csr_excl == null) begin + csr_excl = csr_excl_item::type_id::create("csr_excl"); + this.csr_excl = csr_excl; + end + set_hdl_path_root("tb.dut", "BkdrRegPathRtl"); + set_hdl_path_root("tb.dut", "BkdrRegPathRtlShadow"); + // create registers + intr_state = + (ac_range_check_reg_intr_state:: + type_id::create("intr_state")); + intr_state.configure(.blk_parent(this)); + intr_state.build(csr_excl); + default_map.add_reg(.rg(intr_state), + .offset(32'h0)); + intr_state.add_hdl_path_slice( + "u_ac_range_check_reg.u_intr_state.q", + 0, 1, 0, "BkdrRegPathRtl"); + + // create register tags + csr_excl.add_excl(intr_state.get_full_name(), + CsrExclAll, CsrAllTests); + intr_enable = + (ac_range_check_reg_intr_enable:: + type_id::create("intr_enable")); + intr_enable.configure(.blk_parent(this)); + intr_enable.build(csr_excl); + default_map.add_reg(.rg(intr_enable), + .offset(32'h4)); + intr_enable.add_hdl_path_slice( + "u_ac_range_check_reg.u_intr_enable.q", + 0, 1, 0, "BkdrRegPathRtl"); + + intr_test = + (ac_range_check_reg_intr_test:: + type_id::create("intr_test")); + intr_test.configure(.blk_parent(this)); + intr_test.build(csr_excl); + default_map.add_reg(.rg(intr_test), + .offset(32'h8)); + intr_test.add_hdl_path_slice( + "u_ac_range_check_reg.u_intr_test.qs", + 0, 1, 0, "BkdrRegPathRtl"); + + // create register tags + csr_excl.add_excl(intr_test.get_full_name(), + CsrExclWrite, CsrNonInitTests); + alert_test = + (ac_range_check_reg_alert_test:: + type_id::create("alert_test")); + alert_test.configure(.blk_parent(this)); + alert_test.build(csr_excl); + default_map.add_reg(.rg(alert_test), + .offset(32'hc)); + alert_test.add_hdl_path_slice( + "u_ac_range_check_reg.u_alert_test_recov_ctrl_update_err.qs", + 0, 1, 0, "BkdrRegPathRtl"); + alert_test.add_hdl_path_slice( + "u_ac_range_check_reg.u_alert_test_fatal_fault.qs", + 1, 1, 0, "BkdrRegPathRtl"); + + log_config = + (ac_range_check_reg_log_config:: + type_id::create("log_config")); + log_config.configure(.blk_parent(this)); + log_config.build(csr_excl); + default_map.add_reg(.rg(log_config), + .offset(32'h10)); + log_config.add_hdl_path_slice( + "u_ac_range_check_reg.u_log_config_log_enable.q", + 0, 1, 0, "BkdrRegPathRtl"); + log_config.add_hdl_path_slice( + "u_ac_range_check_reg.u_log_config_log_clear.q", + 1, 1, 0, "BkdrRegPathRtl"); + log_config.add_hdl_path_slice( + "u_ac_range_check_reg.u_log_config_deny_cnt_threshold.q", + 2, 8, 0, "BkdrRegPathRtl"); + + log_status = + (ac_range_check_reg_log_status:: + type_id::create("log_status")); + log_status.configure(.blk_parent(this)); + log_status.build(csr_excl); + default_map.add_reg(.rg(log_status), + .offset(32'h14)); + log_status.add_hdl_path_slice( + "u_ac_range_check_reg.u_log_status_deny_cnt.q", + 0, 8, 0, "BkdrRegPathRtl"); + log_status.add_hdl_path_slice( + "u_ac_range_check_reg.u_log_status_denied_read_access.q", + 8, 1, 0, "BkdrRegPathRtl"); + log_status.add_hdl_path_slice( + "u_ac_range_check_reg.u_log_status_denied_write_access.q", + 9, 1, 0, "BkdrRegPathRtl"); + log_status.add_hdl_path_slice( + "u_ac_range_check_reg.u_log_status_denied_execute_access.q", + 10, 1, 0, "BkdrRegPathRtl"); + log_status.add_hdl_path_slice( + "u_ac_range_check_reg.u_log_status_denied_no_match.q", + 11, 1, 0, "BkdrRegPathRtl"); + log_status.add_hdl_path_slice( + "u_ac_range_check_reg.u_log_status_denied_racl_read.q", + 12, 1, 0, "BkdrRegPathRtl"); + log_status.add_hdl_path_slice( + "u_ac_range_check_reg.u_log_status_denied_racl_write.q", + 13, 1, 0, "BkdrRegPathRtl"); + log_status.add_hdl_path_slice( + "u_ac_range_check_reg.u_log_status_denied_source_role.q", + 14, 4, 0, "BkdrRegPathRtl"); + log_status.add_hdl_path_slice( + "u_ac_range_check_reg.u_log_status_denied_ctn_uid.q", + 18, 5, 0, "BkdrRegPathRtl"); + log_status.add_hdl_path_slice( + "u_ac_range_check_reg.u_log_status_deny_range_index.q", + 23, 5, 0, "BkdrRegPathRtl"); + + log_address = + (ac_range_check_reg_log_address:: + type_id::create("log_address")); + log_address.configure(.blk_parent(this)); + log_address.build(csr_excl); + default_map.add_reg(.rg(log_address), + .offset(32'h18)); + log_address.add_hdl_path_slice( + "u_ac_range_check_reg.u_log_address.q", + 0, 32, 0, "BkdrRegPathRtl"); + + range_regwen[0] = + (ac_range_check_reg_range_regwen:: + type_id::create("range_regwen_0")); + range_regwen[0].configure(.blk_parent(this)); + range_regwen[0].build(csr_excl); + default_map.add_reg(.rg(range_regwen[0]), + .offset(32'h1c)); + range_regwen[0].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_regwen_0.q", + 0, 4, 0, "BkdrRegPathRtl"); + + range_regwen[1] = + (ac_range_check_reg_range_regwen:: + type_id::create("range_regwen_1")); + range_regwen[1].configure(.blk_parent(this)); + range_regwen[1].build(csr_excl); + default_map.add_reg(.rg(range_regwen[1]), + .offset(32'h20)); + range_regwen[1].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_regwen_1.q", + 0, 4, 0, "BkdrRegPathRtl"); + + range_regwen[2] = + (ac_range_check_reg_range_regwen:: + type_id::create("range_regwen_2")); + range_regwen[2].configure(.blk_parent(this)); + range_regwen[2].build(csr_excl); + default_map.add_reg(.rg(range_regwen[2]), + .offset(32'h24)); + range_regwen[2].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_regwen_2.q", + 0, 4, 0, "BkdrRegPathRtl"); + + range_regwen[3] = + (ac_range_check_reg_range_regwen:: + type_id::create("range_regwen_3")); + range_regwen[3].configure(.blk_parent(this)); + range_regwen[3].build(csr_excl); + default_map.add_reg(.rg(range_regwen[3]), + .offset(32'h28)); + range_regwen[3].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_regwen_3.q", + 0, 4, 0, "BkdrRegPathRtl"); + + range_regwen[4] = + (ac_range_check_reg_range_regwen:: + type_id::create("range_regwen_4")); + range_regwen[4].configure(.blk_parent(this)); + range_regwen[4].build(csr_excl); + default_map.add_reg(.rg(range_regwen[4]), + .offset(32'h2c)); + range_regwen[4].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_regwen_4.q", + 0, 4, 0, "BkdrRegPathRtl"); + + range_regwen[5] = + (ac_range_check_reg_range_regwen:: + type_id::create("range_regwen_5")); + range_regwen[5].configure(.blk_parent(this)); + range_regwen[5].build(csr_excl); + default_map.add_reg(.rg(range_regwen[5]), + .offset(32'h30)); + range_regwen[5].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_regwen_5.q", + 0, 4, 0, "BkdrRegPathRtl"); + + range_regwen[6] = + (ac_range_check_reg_range_regwen:: + type_id::create("range_regwen_6")); + range_regwen[6].configure(.blk_parent(this)); + range_regwen[6].build(csr_excl); + default_map.add_reg(.rg(range_regwen[6]), + .offset(32'h34)); + range_regwen[6].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_regwen_6.q", + 0, 4, 0, "BkdrRegPathRtl"); + + range_regwen[7] = + (ac_range_check_reg_range_regwen:: + type_id::create("range_regwen_7")); + range_regwen[7].configure(.blk_parent(this)); + range_regwen[7].build(csr_excl); + default_map.add_reg(.rg(range_regwen[7]), + .offset(32'h38)); + range_regwen[7].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_regwen_7.q", + 0, 4, 0, "BkdrRegPathRtl"); + + range_regwen[8] = + (ac_range_check_reg_range_regwen:: + type_id::create("range_regwen_8")); + range_regwen[8].configure(.blk_parent(this)); + range_regwen[8].build(csr_excl); + default_map.add_reg(.rg(range_regwen[8]), + .offset(32'h3c)); + range_regwen[8].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_regwen_8.q", + 0, 4, 0, "BkdrRegPathRtl"); + + range_regwen[9] = + (ac_range_check_reg_range_regwen:: + type_id::create("range_regwen_9")); + range_regwen[9].configure(.blk_parent(this)); + range_regwen[9].build(csr_excl); + default_map.add_reg(.rg(range_regwen[9]), + .offset(32'h40)); + range_regwen[9].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_regwen_9.q", + 0, 4, 0, "BkdrRegPathRtl"); + + range_regwen[10] = + (ac_range_check_reg_range_regwen:: + type_id::create("range_regwen_10")); + range_regwen[10].configure(.blk_parent(this)); + range_regwen[10].build(csr_excl); + default_map.add_reg(.rg(range_regwen[10]), + .offset(32'h44)); + range_regwen[10].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_regwen_10.q", + 0, 4, 0, "BkdrRegPathRtl"); + + range_regwen[11] = + (ac_range_check_reg_range_regwen:: + type_id::create("range_regwen_11")); + range_regwen[11].configure(.blk_parent(this)); + range_regwen[11].build(csr_excl); + default_map.add_reg(.rg(range_regwen[11]), + .offset(32'h48)); + range_regwen[11].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_regwen_11.q", + 0, 4, 0, "BkdrRegPathRtl"); + + range_regwen[12] = + (ac_range_check_reg_range_regwen:: + type_id::create("range_regwen_12")); + range_regwen[12].configure(.blk_parent(this)); + range_regwen[12].build(csr_excl); + default_map.add_reg(.rg(range_regwen[12]), + .offset(32'h4c)); + range_regwen[12].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_regwen_12.q", + 0, 4, 0, "BkdrRegPathRtl"); + + range_regwen[13] = + (ac_range_check_reg_range_regwen:: + type_id::create("range_regwen_13")); + range_regwen[13].configure(.blk_parent(this)); + range_regwen[13].build(csr_excl); + default_map.add_reg(.rg(range_regwen[13]), + .offset(32'h50)); + range_regwen[13].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_regwen_13.q", + 0, 4, 0, "BkdrRegPathRtl"); + + range_regwen[14] = + (ac_range_check_reg_range_regwen:: + type_id::create("range_regwen_14")); + range_regwen[14].configure(.blk_parent(this)); + range_regwen[14].build(csr_excl); + default_map.add_reg(.rg(range_regwen[14]), + .offset(32'h54)); + range_regwen[14].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_regwen_14.q", + 0, 4, 0, "BkdrRegPathRtl"); + + range_regwen[15] = + (ac_range_check_reg_range_regwen:: + type_id::create("range_regwen_15")); + range_regwen[15].configure(.blk_parent(this)); + range_regwen[15].build(csr_excl); + default_map.add_reg(.rg(range_regwen[15]), + .offset(32'h58)); + range_regwen[15].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_regwen_15.q", + 0, 4, 0, "BkdrRegPathRtl"); + + range_regwen[16] = + (ac_range_check_reg_range_regwen:: + type_id::create("range_regwen_16")); + range_regwen[16].configure(.blk_parent(this)); + range_regwen[16].build(csr_excl); + default_map.add_reg(.rg(range_regwen[16]), + .offset(32'h5c)); + range_regwen[16].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_regwen_16.q", + 0, 4, 0, "BkdrRegPathRtl"); + + range_regwen[17] = + (ac_range_check_reg_range_regwen:: + type_id::create("range_regwen_17")); + range_regwen[17].configure(.blk_parent(this)); + range_regwen[17].build(csr_excl); + default_map.add_reg(.rg(range_regwen[17]), + .offset(32'h60)); + range_regwen[17].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_regwen_17.q", + 0, 4, 0, "BkdrRegPathRtl"); + + range_regwen[18] = + (ac_range_check_reg_range_regwen:: + type_id::create("range_regwen_18")); + range_regwen[18].configure(.blk_parent(this)); + range_regwen[18].build(csr_excl); + default_map.add_reg(.rg(range_regwen[18]), + .offset(32'h64)); + range_regwen[18].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_regwen_18.q", + 0, 4, 0, "BkdrRegPathRtl"); + + range_regwen[19] = + (ac_range_check_reg_range_regwen:: + type_id::create("range_regwen_19")); + range_regwen[19].configure(.blk_parent(this)); + range_regwen[19].build(csr_excl); + default_map.add_reg(.rg(range_regwen[19]), + .offset(32'h68)); + range_regwen[19].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_regwen_19.q", + 0, 4, 0, "BkdrRegPathRtl"); + + range_regwen[20] = + (ac_range_check_reg_range_regwen:: + type_id::create("range_regwen_20")); + range_regwen[20].configure(.blk_parent(this)); + range_regwen[20].build(csr_excl); + default_map.add_reg(.rg(range_regwen[20]), + .offset(32'h6c)); + range_regwen[20].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_regwen_20.q", + 0, 4, 0, "BkdrRegPathRtl"); + + range_regwen[21] = + (ac_range_check_reg_range_regwen:: + type_id::create("range_regwen_21")); + range_regwen[21].configure(.blk_parent(this)); + range_regwen[21].build(csr_excl); + default_map.add_reg(.rg(range_regwen[21]), + .offset(32'h70)); + range_regwen[21].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_regwen_21.q", + 0, 4, 0, "BkdrRegPathRtl"); + + range_regwen[22] = + (ac_range_check_reg_range_regwen:: + type_id::create("range_regwen_22")); + range_regwen[22].configure(.blk_parent(this)); + range_regwen[22].build(csr_excl); + default_map.add_reg(.rg(range_regwen[22]), + .offset(32'h74)); + range_regwen[22].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_regwen_22.q", + 0, 4, 0, "BkdrRegPathRtl"); + + range_regwen[23] = + (ac_range_check_reg_range_regwen:: + type_id::create("range_regwen_23")); + range_regwen[23].configure(.blk_parent(this)); + range_regwen[23].build(csr_excl); + default_map.add_reg(.rg(range_regwen[23]), + .offset(32'h78)); + range_regwen[23].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_regwen_23.q", + 0, 4, 0, "BkdrRegPathRtl"); + + range_regwen[24] = + (ac_range_check_reg_range_regwen:: + type_id::create("range_regwen_24")); + range_regwen[24].configure(.blk_parent(this)); + range_regwen[24].build(csr_excl); + default_map.add_reg(.rg(range_regwen[24]), + .offset(32'h7c)); + range_regwen[24].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_regwen_24.q", + 0, 4, 0, "BkdrRegPathRtl"); + + range_regwen[25] = + (ac_range_check_reg_range_regwen:: + type_id::create("range_regwen_25")); + range_regwen[25].configure(.blk_parent(this)); + range_regwen[25].build(csr_excl); + default_map.add_reg(.rg(range_regwen[25]), + .offset(32'h80)); + range_regwen[25].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_regwen_25.q", + 0, 4, 0, "BkdrRegPathRtl"); + + range_regwen[26] = + (ac_range_check_reg_range_regwen:: + type_id::create("range_regwen_26")); + range_regwen[26].configure(.blk_parent(this)); + range_regwen[26].build(csr_excl); + default_map.add_reg(.rg(range_regwen[26]), + .offset(32'h84)); + range_regwen[26].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_regwen_26.q", + 0, 4, 0, "BkdrRegPathRtl"); + + range_regwen[27] = + (ac_range_check_reg_range_regwen:: + type_id::create("range_regwen_27")); + range_regwen[27].configure(.blk_parent(this)); + range_regwen[27].build(csr_excl); + default_map.add_reg(.rg(range_regwen[27]), + .offset(32'h88)); + range_regwen[27].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_regwen_27.q", + 0, 4, 0, "BkdrRegPathRtl"); + + range_regwen[28] = + (ac_range_check_reg_range_regwen:: + type_id::create("range_regwen_28")); + range_regwen[28].configure(.blk_parent(this)); + range_regwen[28].build(csr_excl); + default_map.add_reg(.rg(range_regwen[28]), + .offset(32'h8c)); + range_regwen[28].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_regwen_28.q", + 0, 4, 0, "BkdrRegPathRtl"); + + range_regwen[29] = + (ac_range_check_reg_range_regwen:: + type_id::create("range_regwen_29")); + range_regwen[29].configure(.blk_parent(this)); + range_regwen[29].build(csr_excl); + default_map.add_reg(.rg(range_regwen[29]), + .offset(32'h90)); + range_regwen[29].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_regwen_29.q", + 0, 4, 0, "BkdrRegPathRtl"); + + range_regwen[30] = + (ac_range_check_reg_range_regwen:: + type_id::create("range_regwen_30")); + range_regwen[30].configure(.blk_parent(this)); + range_regwen[30].build(csr_excl); + default_map.add_reg(.rg(range_regwen[30]), + .offset(32'h94)); + range_regwen[30].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_regwen_30.q", + 0, 4, 0, "BkdrRegPathRtl"); + + range_regwen[31] = + (ac_range_check_reg_range_regwen:: + type_id::create("range_regwen_31")); + range_regwen[31].configure(.blk_parent(this)); + range_regwen[31].build(csr_excl); + default_map.add_reg(.rg(range_regwen[31]), + .offset(32'h98)); + range_regwen[31].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_regwen_31.q", + 0, 4, 0, "BkdrRegPathRtl"); + + range_base[0] = + (ac_range_check_reg_range_base:: + type_id::create("range_base_0")); + range_base[0].configure(.blk_parent(this)); + range_base[0].build(csr_excl); + default_map.add_reg(.rg(range_base[0]), + .offset(32'h9c)); + range_base[0].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_base_0.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_base[1] = + (ac_range_check_reg_range_base:: + type_id::create("range_base_1")); + range_base[1].configure(.blk_parent(this)); + range_base[1].build(csr_excl); + default_map.add_reg(.rg(range_base[1]), + .offset(32'ha0)); + range_base[1].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_base_1.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_base[2] = + (ac_range_check_reg_range_base:: + type_id::create("range_base_2")); + range_base[2].configure(.blk_parent(this)); + range_base[2].build(csr_excl); + default_map.add_reg(.rg(range_base[2]), + .offset(32'ha4)); + range_base[2].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_base_2.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_base[3] = + (ac_range_check_reg_range_base:: + type_id::create("range_base_3")); + range_base[3].configure(.blk_parent(this)); + range_base[3].build(csr_excl); + default_map.add_reg(.rg(range_base[3]), + .offset(32'ha8)); + range_base[3].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_base_3.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_base[4] = + (ac_range_check_reg_range_base:: + type_id::create("range_base_4")); + range_base[4].configure(.blk_parent(this)); + range_base[4].build(csr_excl); + default_map.add_reg(.rg(range_base[4]), + .offset(32'hac)); + range_base[4].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_base_4.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_base[5] = + (ac_range_check_reg_range_base:: + type_id::create("range_base_5")); + range_base[5].configure(.blk_parent(this)); + range_base[5].build(csr_excl); + default_map.add_reg(.rg(range_base[5]), + .offset(32'hb0)); + range_base[5].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_base_5.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_base[6] = + (ac_range_check_reg_range_base:: + type_id::create("range_base_6")); + range_base[6].configure(.blk_parent(this)); + range_base[6].build(csr_excl); + default_map.add_reg(.rg(range_base[6]), + .offset(32'hb4)); + range_base[6].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_base_6.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_base[7] = + (ac_range_check_reg_range_base:: + type_id::create("range_base_7")); + range_base[7].configure(.blk_parent(this)); + range_base[7].build(csr_excl); + default_map.add_reg(.rg(range_base[7]), + .offset(32'hb8)); + range_base[7].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_base_7.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_base[8] = + (ac_range_check_reg_range_base:: + type_id::create("range_base_8")); + range_base[8].configure(.blk_parent(this)); + range_base[8].build(csr_excl); + default_map.add_reg(.rg(range_base[8]), + .offset(32'hbc)); + range_base[8].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_base_8.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_base[9] = + (ac_range_check_reg_range_base:: + type_id::create("range_base_9")); + range_base[9].configure(.blk_parent(this)); + range_base[9].build(csr_excl); + default_map.add_reg(.rg(range_base[9]), + .offset(32'hc0)); + range_base[9].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_base_9.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_base[10] = + (ac_range_check_reg_range_base:: + type_id::create("range_base_10")); + range_base[10].configure(.blk_parent(this)); + range_base[10].build(csr_excl); + default_map.add_reg(.rg(range_base[10]), + .offset(32'hc4)); + range_base[10].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_base_10.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_base[11] = + (ac_range_check_reg_range_base:: + type_id::create("range_base_11")); + range_base[11].configure(.blk_parent(this)); + range_base[11].build(csr_excl); + default_map.add_reg(.rg(range_base[11]), + .offset(32'hc8)); + range_base[11].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_base_11.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_base[12] = + (ac_range_check_reg_range_base:: + type_id::create("range_base_12")); + range_base[12].configure(.blk_parent(this)); + range_base[12].build(csr_excl); + default_map.add_reg(.rg(range_base[12]), + .offset(32'hcc)); + range_base[12].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_base_12.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_base[13] = + (ac_range_check_reg_range_base:: + type_id::create("range_base_13")); + range_base[13].configure(.blk_parent(this)); + range_base[13].build(csr_excl); + default_map.add_reg(.rg(range_base[13]), + .offset(32'hd0)); + range_base[13].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_base_13.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_base[14] = + (ac_range_check_reg_range_base:: + type_id::create("range_base_14")); + range_base[14].configure(.blk_parent(this)); + range_base[14].build(csr_excl); + default_map.add_reg(.rg(range_base[14]), + .offset(32'hd4)); + range_base[14].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_base_14.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_base[15] = + (ac_range_check_reg_range_base:: + type_id::create("range_base_15")); + range_base[15].configure(.blk_parent(this)); + range_base[15].build(csr_excl); + default_map.add_reg(.rg(range_base[15]), + .offset(32'hd8)); + range_base[15].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_base_15.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_base[16] = + (ac_range_check_reg_range_base:: + type_id::create("range_base_16")); + range_base[16].configure(.blk_parent(this)); + range_base[16].build(csr_excl); + default_map.add_reg(.rg(range_base[16]), + .offset(32'hdc)); + range_base[16].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_base_16.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_base[17] = + (ac_range_check_reg_range_base:: + type_id::create("range_base_17")); + range_base[17].configure(.blk_parent(this)); + range_base[17].build(csr_excl); + default_map.add_reg(.rg(range_base[17]), + .offset(32'he0)); + range_base[17].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_base_17.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_base[18] = + (ac_range_check_reg_range_base:: + type_id::create("range_base_18")); + range_base[18].configure(.blk_parent(this)); + range_base[18].build(csr_excl); + default_map.add_reg(.rg(range_base[18]), + .offset(32'he4)); + range_base[18].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_base_18.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_base[19] = + (ac_range_check_reg_range_base:: + type_id::create("range_base_19")); + range_base[19].configure(.blk_parent(this)); + range_base[19].build(csr_excl); + default_map.add_reg(.rg(range_base[19]), + .offset(32'he8)); + range_base[19].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_base_19.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_base[20] = + (ac_range_check_reg_range_base:: + type_id::create("range_base_20")); + range_base[20].configure(.blk_parent(this)); + range_base[20].build(csr_excl); + default_map.add_reg(.rg(range_base[20]), + .offset(32'hec)); + range_base[20].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_base_20.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_base[21] = + (ac_range_check_reg_range_base:: + type_id::create("range_base_21")); + range_base[21].configure(.blk_parent(this)); + range_base[21].build(csr_excl); + default_map.add_reg(.rg(range_base[21]), + .offset(32'hf0)); + range_base[21].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_base_21.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_base[22] = + (ac_range_check_reg_range_base:: + type_id::create("range_base_22")); + range_base[22].configure(.blk_parent(this)); + range_base[22].build(csr_excl); + default_map.add_reg(.rg(range_base[22]), + .offset(32'hf4)); + range_base[22].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_base_22.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_base[23] = + (ac_range_check_reg_range_base:: + type_id::create("range_base_23")); + range_base[23].configure(.blk_parent(this)); + range_base[23].build(csr_excl); + default_map.add_reg(.rg(range_base[23]), + .offset(32'hf8)); + range_base[23].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_base_23.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_base[24] = + (ac_range_check_reg_range_base:: + type_id::create("range_base_24")); + range_base[24].configure(.blk_parent(this)); + range_base[24].build(csr_excl); + default_map.add_reg(.rg(range_base[24]), + .offset(32'hfc)); + range_base[24].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_base_24.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_base[25] = + (ac_range_check_reg_range_base:: + type_id::create("range_base_25")); + range_base[25].configure(.blk_parent(this)); + range_base[25].build(csr_excl); + default_map.add_reg(.rg(range_base[25]), + .offset(32'h100)); + range_base[25].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_base_25.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_base[26] = + (ac_range_check_reg_range_base:: + type_id::create("range_base_26")); + range_base[26].configure(.blk_parent(this)); + range_base[26].build(csr_excl); + default_map.add_reg(.rg(range_base[26]), + .offset(32'h104)); + range_base[26].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_base_26.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_base[27] = + (ac_range_check_reg_range_base:: + type_id::create("range_base_27")); + range_base[27].configure(.blk_parent(this)); + range_base[27].build(csr_excl); + default_map.add_reg(.rg(range_base[27]), + .offset(32'h108)); + range_base[27].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_base_27.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_base[28] = + (ac_range_check_reg_range_base:: + type_id::create("range_base_28")); + range_base[28].configure(.blk_parent(this)); + range_base[28].build(csr_excl); + default_map.add_reg(.rg(range_base[28]), + .offset(32'h10c)); + range_base[28].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_base_28.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_base[29] = + (ac_range_check_reg_range_base:: + type_id::create("range_base_29")); + range_base[29].configure(.blk_parent(this)); + range_base[29].build(csr_excl); + default_map.add_reg(.rg(range_base[29]), + .offset(32'h110)); + range_base[29].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_base_29.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_base[30] = + (ac_range_check_reg_range_base:: + type_id::create("range_base_30")); + range_base[30].configure(.blk_parent(this)); + range_base[30].build(csr_excl); + default_map.add_reg(.rg(range_base[30]), + .offset(32'h114)); + range_base[30].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_base_30.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_base[31] = + (ac_range_check_reg_range_base:: + type_id::create("range_base_31")); + range_base[31].configure(.blk_parent(this)); + range_base[31].build(csr_excl); + default_map.add_reg(.rg(range_base[31]), + .offset(32'h118)); + range_base[31].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_base_31.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_limit[0] = + (ac_range_check_reg_range_limit:: + type_id::create("range_limit_0")); + range_limit[0].configure(.blk_parent(this)); + range_limit[0].build(csr_excl); + default_map.add_reg(.rg(range_limit[0]), + .offset(32'h11c)); + range_limit[0].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_limit_0.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_limit[1] = + (ac_range_check_reg_range_limit:: + type_id::create("range_limit_1")); + range_limit[1].configure(.blk_parent(this)); + range_limit[1].build(csr_excl); + default_map.add_reg(.rg(range_limit[1]), + .offset(32'h120)); + range_limit[1].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_limit_1.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_limit[2] = + (ac_range_check_reg_range_limit:: + type_id::create("range_limit_2")); + range_limit[2].configure(.blk_parent(this)); + range_limit[2].build(csr_excl); + default_map.add_reg(.rg(range_limit[2]), + .offset(32'h124)); + range_limit[2].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_limit_2.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_limit[3] = + (ac_range_check_reg_range_limit:: + type_id::create("range_limit_3")); + range_limit[3].configure(.blk_parent(this)); + range_limit[3].build(csr_excl); + default_map.add_reg(.rg(range_limit[3]), + .offset(32'h128)); + range_limit[3].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_limit_3.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_limit[4] = + (ac_range_check_reg_range_limit:: + type_id::create("range_limit_4")); + range_limit[4].configure(.blk_parent(this)); + range_limit[4].build(csr_excl); + default_map.add_reg(.rg(range_limit[4]), + .offset(32'h12c)); + range_limit[4].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_limit_4.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_limit[5] = + (ac_range_check_reg_range_limit:: + type_id::create("range_limit_5")); + range_limit[5].configure(.blk_parent(this)); + range_limit[5].build(csr_excl); + default_map.add_reg(.rg(range_limit[5]), + .offset(32'h130)); + range_limit[5].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_limit_5.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_limit[6] = + (ac_range_check_reg_range_limit:: + type_id::create("range_limit_6")); + range_limit[6].configure(.blk_parent(this)); + range_limit[6].build(csr_excl); + default_map.add_reg(.rg(range_limit[6]), + .offset(32'h134)); + range_limit[6].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_limit_6.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_limit[7] = + (ac_range_check_reg_range_limit:: + type_id::create("range_limit_7")); + range_limit[7].configure(.blk_parent(this)); + range_limit[7].build(csr_excl); + default_map.add_reg(.rg(range_limit[7]), + .offset(32'h138)); + range_limit[7].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_limit_7.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_limit[8] = + (ac_range_check_reg_range_limit:: + type_id::create("range_limit_8")); + range_limit[8].configure(.blk_parent(this)); + range_limit[8].build(csr_excl); + default_map.add_reg(.rg(range_limit[8]), + .offset(32'h13c)); + range_limit[8].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_limit_8.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_limit[9] = + (ac_range_check_reg_range_limit:: + type_id::create("range_limit_9")); + range_limit[9].configure(.blk_parent(this)); + range_limit[9].build(csr_excl); + default_map.add_reg(.rg(range_limit[9]), + .offset(32'h140)); + range_limit[9].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_limit_9.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_limit[10] = + (ac_range_check_reg_range_limit:: + type_id::create("range_limit_10")); + range_limit[10].configure(.blk_parent(this)); + range_limit[10].build(csr_excl); + default_map.add_reg(.rg(range_limit[10]), + .offset(32'h144)); + range_limit[10].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_limit_10.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_limit[11] = + (ac_range_check_reg_range_limit:: + type_id::create("range_limit_11")); + range_limit[11].configure(.blk_parent(this)); + range_limit[11].build(csr_excl); + default_map.add_reg(.rg(range_limit[11]), + .offset(32'h148)); + range_limit[11].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_limit_11.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_limit[12] = + (ac_range_check_reg_range_limit:: + type_id::create("range_limit_12")); + range_limit[12].configure(.blk_parent(this)); + range_limit[12].build(csr_excl); + default_map.add_reg(.rg(range_limit[12]), + .offset(32'h14c)); + range_limit[12].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_limit_12.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_limit[13] = + (ac_range_check_reg_range_limit:: + type_id::create("range_limit_13")); + range_limit[13].configure(.blk_parent(this)); + range_limit[13].build(csr_excl); + default_map.add_reg(.rg(range_limit[13]), + .offset(32'h150)); + range_limit[13].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_limit_13.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_limit[14] = + (ac_range_check_reg_range_limit:: + type_id::create("range_limit_14")); + range_limit[14].configure(.blk_parent(this)); + range_limit[14].build(csr_excl); + default_map.add_reg(.rg(range_limit[14]), + .offset(32'h154)); + range_limit[14].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_limit_14.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_limit[15] = + (ac_range_check_reg_range_limit:: + type_id::create("range_limit_15")); + range_limit[15].configure(.blk_parent(this)); + range_limit[15].build(csr_excl); + default_map.add_reg(.rg(range_limit[15]), + .offset(32'h158)); + range_limit[15].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_limit_15.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_limit[16] = + (ac_range_check_reg_range_limit:: + type_id::create("range_limit_16")); + range_limit[16].configure(.blk_parent(this)); + range_limit[16].build(csr_excl); + default_map.add_reg(.rg(range_limit[16]), + .offset(32'h15c)); + range_limit[16].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_limit_16.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_limit[17] = + (ac_range_check_reg_range_limit:: + type_id::create("range_limit_17")); + range_limit[17].configure(.blk_parent(this)); + range_limit[17].build(csr_excl); + default_map.add_reg(.rg(range_limit[17]), + .offset(32'h160)); + range_limit[17].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_limit_17.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_limit[18] = + (ac_range_check_reg_range_limit:: + type_id::create("range_limit_18")); + range_limit[18].configure(.blk_parent(this)); + range_limit[18].build(csr_excl); + default_map.add_reg(.rg(range_limit[18]), + .offset(32'h164)); + range_limit[18].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_limit_18.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_limit[19] = + (ac_range_check_reg_range_limit:: + type_id::create("range_limit_19")); + range_limit[19].configure(.blk_parent(this)); + range_limit[19].build(csr_excl); + default_map.add_reg(.rg(range_limit[19]), + .offset(32'h168)); + range_limit[19].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_limit_19.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_limit[20] = + (ac_range_check_reg_range_limit:: + type_id::create("range_limit_20")); + range_limit[20].configure(.blk_parent(this)); + range_limit[20].build(csr_excl); + default_map.add_reg(.rg(range_limit[20]), + .offset(32'h16c)); + range_limit[20].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_limit_20.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_limit[21] = + (ac_range_check_reg_range_limit:: + type_id::create("range_limit_21")); + range_limit[21].configure(.blk_parent(this)); + range_limit[21].build(csr_excl); + default_map.add_reg(.rg(range_limit[21]), + .offset(32'h170)); + range_limit[21].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_limit_21.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_limit[22] = + (ac_range_check_reg_range_limit:: + type_id::create("range_limit_22")); + range_limit[22].configure(.blk_parent(this)); + range_limit[22].build(csr_excl); + default_map.add_reg(.rg(range_limit[22]), + .offset(32'h174)); + range_limit[22].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_limit_22.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_limit[23] = + (ac_range_check_reg_range_limit:: + type_id::create("range_limit_23")); + range_limit[23].configure(.blk_parent(this)); + range_limit[23].build(csr_excl); + default_map.add_reg(.rg(range_limit[23]), + .offset(32'h178)); + range_limit[23].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_limit_23.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_limit[24] = + (ac_range_check_reg_range_limit:: + type_id::create("range_limit_24")); + range_limit[24].configure(.blk_parent(this)); + range_limit[24].build(csr_excl); + default_map.add_reg(.rg(range_limit[24]), + .offset(32'h17c)); + range_limit[24].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_limit_24.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_limit[25] = + (ac_range_check_reg_range_limit:: + type_id::create("range_limit_25")); + range_limit[25].configure(.blk_parent(this)); + range_limit[25].build(csr_excl); + default_map.add_reg(.rg(range_limit[25]), + .offset(32'h180)); + range_limit[25].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_limit_25.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_limit[26] = + (ac_range_check_reg_range_limit:: + type_id::create("range_limit_26")); + range_limit[26].configure(.blk_parent(this)); + range_limit[26].build(csr_excl); + default_map.add_reg(.rg(range_limit[26]), + .offset(32'h184)); + range_limit[26].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_limit_26.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_limit[27] = + (ac_range_check_reg_range_limit:: + type_id::create("range_limit_27")); + range_limit[27].configure(.blk_parent(this)); + range_limit[27].build(csr_excl); + default_map.add_reg(.rg(range_limit[27]), + .offset(32'h188)); + range_limit[27].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_limit_27.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_limit[28] = + (ac_range_check_reg_range_limit:: + type_id::create("range_limit_28")); + range_limit[28].configure(.blk_parent(this)); + range_limit[28].build(csr_excl); + default_map.add_reg(.rg(range_limit[28]), + .offset(32'h18c)); + range_limit[28].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_limit_28.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_limit[29] = + (ac_range_check_reg_range_limit:: + type_id::create("range_limit_29")); + range_limit[29].configure(.blk_parent(this)); + range_limit[29].build(csr_excl); + default_map.add_reg(.rg(range_limit[29]), + .offset(32'h190)); + range_limit[29].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_limit_29.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_limit[30] = + (ac_range_check_reg_range_limit:: + type_id::create("range_limit_30")); + range_limit[30].configure(.blk_parent(this)); + range_limit[30].build(csr_excl); + default_map.add_reg(.rg(range_limit[30]), + .offset(32'h194)); + range_limit[30].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_limit_30.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_limit[31] = + (ac_range_check_reg_range_limit:: + type_id::create("range_limit_31")); + range_limit[31].configure(.blk_parent(this)); + range_limit[31].build(csr_excl); + default_map.add_reg(.rg(range_limit[31]), + .offset(32'h198)); + range_limit[31].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_limit_31.q", + 2, 30, 0, "BkdrRegPathRtl"); + + range_perm[0] = + (ac_range_check_reg_range_perm:: + type_id::create("range_perm_0")); + range_perm[0].configure(.blk_parent(this)); + range_perm[0].build(csr_excl); + default_map.add_reg(.rg(range_perm[0]), + .offset(32'h19c)); + range_perm[0].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_0_enable_0.q", + 0, 4, 0, "BkdrRegPathRtl"); + range_perm[0].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_0_read_access_0.q", + 4, 4, 0, "BkdrRegPathRtl"); + range_perm[0].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_0_write_access_0.q", + 8, 4, 0, "BkdrRegPathRtl"); + range_perm[0].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_0_execute_access_0.q", + 12, 4, 0, "BkdrRegPathRtl"); + range_perm[0].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_0_log_denied_access_0.q", + 16, 4, 0, "BkdrRegPathRtl"); + + range_perm[1] = + (ac_range_check_reg_range_perm:: + type_id::create("range_perm_1")); + range_perm[1].configure(.blk_parent(this)); + range_perm[1].build(csr_excl); + default_map.add_reg(.rg(range_perm[1]), + .offset(32'h1a0)); + range_perm[1].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_1_enable_1.q", + 0, 4, 0, "BkdrRegPathRtl"); + range_perm[1].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_1_read_access_1.q", + 4, 4, 0, "BkdrRegPathRtl"); + range_perm[1].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_1_write_access_1.q", + 8, 4, 0, "BkdrRegPathRtl"); + range_perm[1].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_1_execute_access_1.q", + 12, 4, 0, "BkdrRegPathRtl"); + range_perm[1].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_1_log_denied_access_1.q", + 16, 4, 0, "BkdrRegPathRtl"); + + range_perm[2] = + (ac_range_check_reg_range_perm:: + type_id::create("range_perm_2")); + range_perm[2].configure(.blk_parent(this)); + range_perm[2].build(csr_excl); + default_map.add_reg(.rg(range_perm[2]), + .offset(32'h1a4)); + range_perm[2].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_2_enable_2.q", + 0, 4, 0, "BkdrRegPathRtl"); + range_perm[2].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_2_read_access_2.q", + 4, 4, 0, "BkdrRegPathRtl"); + range_perm[2].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_2_write_access_2.q", + 8, 4, 0, "BkdrRegPathRtl"); + range_perm[2].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_2_execute_access_2.q", + 12, 4, 0, "BkdrRegPathRtl"); + range_perm[2].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_2_log_denied_access_2.q", + 16, 4, 0, "BkdrRegPathRtl"); + + range_perm[3] = + (ac_range_check_reg_range_perm:: + type_id::create("range_perm_3")); + range_perm[3].configure(.blk_parent(this)); + range_perm[3].build(csr_excl); + default_map.add_reg(.rg(range_perm[3]), + .offset(32'h1a8)); + range_perm[3].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_3_enable_3.q", + 0, 4, 0, "BkdrRegPathRtl"); + range_perm[3].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_3_read_access_3.q", + 4, 4, 0, "BkdrRegPathRtl"); + range_perm[3].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_3_write_access_3.q", + 8, 4, 0, "BkdrRegPathRtl"); + range_perm[3].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_3_execute_access_3.q", + 12, 4, 0, "BkdrRegPathRtl"); + range_perm[3].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_3_log_denied_access_3.q", + 16, 4, 0, "BkdrRegPathRtl"); + + range_perm[4] = + (ac_range_check_reg_range_perm:: + type_id::create("range_perm_4")); + range_perm[4].configure(.blk_parent(this)); + range_perm[4].build(csr_excl); + default_map.add_reg(.rg(range_perm[4]), + .offset(32'h1ac)); + range_perm[4].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_4_enable_4.q", + 0, 4, 0, "BkdrRegPathRtl"); + range_perm[4].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_4_read_access_4.q", + 4, 4, 0, "BkdrRegPathRtl"); + range_perm[4].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_4_write_access_4.q", + 8, 4, 0, "BkdrRegPathRtl"); + range_perm[4].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_4_execute_access_4.q", + 12, 4, 0, "BkdrRegPathRtl"); + range_perm[4].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_4_log_denied_access_4.q", + 16, 4, 0, "BkdrRegPathRtl"); + + range_perm[5] = + (ac_range_check_reg_range_perm:: + type_id::create("range_perm_5")); + range_perm[5].configure(.blk_parent(this)); + range_perm[5].build(csr_excl); + default_map.add_reg(.rg(range_perm[5]), + .offset(32'h1b0)); + range_perm[5].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_5_enable_5.q", + 0, 4, 0, "BkdrRegPathRtl"); + range_perm[5].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_5_read_access_5.q", + 4, 4, 0, "BkdrRegPathRtl"); + range_perm[5].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_5_write_access_5.q", + 8, 4, 0, "BkdrRegPathRtl"); + range_perm[5].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_5_execute_access_5.q", + 12, 4, 0, "BkdrRegPathRtl"); + range_perm[5].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_5_log_denied_access_5.q", + 16, 4, 0, "BkdrRegPathRtl"); + + range_perm[6] = + (ac_range_check_reg_range_perm:: + type_id::create("range_perm_6")); + range_perm[6].configure(.blk_parent(this)); + range_perm[6].build(csr_excl); + default_map.add_reg(.rg(range_perm[6]), + .offset(32'h1b4)); + range_perm[6].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_6_enable_6.q", + 0, 4, 0, "BkdrRegPathRtl"); + range_perm[6].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_6_read_access_6.q", + 4, 4, 0, "BkdrRegPathRtl"); + range_perm[6].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_6_write_access_6.q", + 8, 4, 0, "BkdrRegPathRtl"); + range_perm[6].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_6_execute_access_6.q", + 12, 4, 0, "BkdrRegPathRtl"); + range_perm[6].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_6_log_denied_access_6.q", + 16, 4, 0, "BkdrRegPathRtl"); + + range_perm[7] = + (ac_range_check_reg_range_perm:: + type_id::create("range_perm_7")); + range_perm[7].configure(.blk_parent(this)); + range_perm[7].build(csr_excl); + default_map.add_reg(.rg(range_perm[7]), + .offset(32'h1b8)); + range_perm[7].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_7_enable_7.q", + 0, 4, 0, "BkdrRegPathRtl"); + range_perm[7].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_7_read_access_7.q", + 4, 4, 0, "BkdrRegPathRtl"); + range_perm[7].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_7_write_access_7.q", + 8, 4, 0, "BkdrRegPathRtl"); + range_perm[7].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_7_execute_access_7.q", + 12, 4, 0, "BkdrRegPathRtl"); + range_perm[7].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_7_log_denied_access_7.q", + 16, 4, 0, "BkdrRegPathRtl"); + + range_perm[8] = + (ac_range_check_reg_range_perm:: + type_id::create("range_perm_8")); + range_perm[8].configure(.blk_parent(this)); + range_perm[8].build(csr_excl); + default_map.add_reg(.rg(range_perm[8]), + .offset(32'h1bc)); + range_perm[8].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_8_enable_8.q", + 0, 4, 0, "BkdrRegPathRtl"); + range_perm[8].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_8_read_access_8.q", + 4, 4, 0, "BkdrRegPathRtl"); + range_perm[8].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_8_write_access_8.q", + 8, 4, 0, "BkdrRegPathRtl"); + range_perm[8].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_8_execute_access_8.q", + 12, 4, 0, "BkdrRegPathRtl"); + range_perm[8].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_8_log_denied_access_8.q", + 16, 4, 0, "BkdrRegPathRtl"); + + range_perm[9] = + (ac_range_check_reg_range_perm:: + type_id::create("range_perm_9")); + range_perm[9].configure(.blk_parent(this)); + range_perm[9].build(csr_excl); + default_map.add_reg(.rg(range_perm[9]), + .offset(32'h1c0)); + range_perm[9].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_9_enable_9.q", + 0, 4, 0, "BkdrRegPathRtl"); + range_perm[9].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_9_read_access_9.q", + 4, 4, 0, "BkdrRegPathRtl"); + range_perm[9].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_9_write_access_9.q", + 8, 4, 0, "BkdrRegPathRtl"); + range_perm[9].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_9_execute_access_9.q", + 12, 4, 0, "BkdrRegPathRtl"); + range_perm[9].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_9_log_denied_access_9.q", + 16, 4, 0, "BkdrRegPathRtl"); + + range_perm[10] = + (ac_range_check_reg_range_perm:: + type_id::create("range_perm_10")); + range_perm[10].configure(.blk_parent(this)); + range_perm[10].build(csr_excl); + default_map.add_reg(.rg(range_perm[10]), + .offset(32'h1c4)); + range_perm[10].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_10_enable_10.q", + 0, 4, 0, "BkdrRegPathRtl"); + range_perm[10].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_10_read_access_10.q", + 4, 4, 0, "BkdrRegPathRtl"); + range_perm[10].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_10_write_access_10.q", + 8, 4, 0, "BkdrRegPathRtl"); + range_perm[10].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_10_execute_access_10.q", + 12, 4, 0, "BkdrRegPathRtl"); + range_perm[10].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_10_log_denied_access_10.q", + 16, 4, 0, "BkdrRegPathRtl"); + + range_perm[11] = + (ac_range_check_reg_range_perm:: + type_id::create("range_perm_11")); + range_perm[11].configure(.blk_parent(this)); + range_perm[11].build(csr_excl); + default_map.add_reg(.rg(range_perm[11]), + .offset(32'h1c8)); + range_perm[11].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_11_enable_11.q", + 0, 4, 0, "BkdrRegPathRtl"); + range_perm[11].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_11_read_access_11.q", + 4, 4, 0, "BkdrRegPathRtl"); + range_perm[11].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_11_write_access_11.q", + 8, 4, 0, "BkdrRegPathRtl"); + range_perm[11].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_11_execute_access_11.q", + 12, 4, 0, "BkdrRegPathRtl"); + range_perm[11].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_11_log_denied_access_11.q", + 16, 4, 0, "BkdrRegPathRtl"); + + range_perm[12] = + (ac_range_check_reg_range_perm:: + type_id::create("range_perm_12")); + range_perm[12].configure(.blk_parent(this)); + range_perm[12].build(csr_excl); + default_map.add_reg(.rg(range_perm[12]), + .offset(32'h1cc)); + range_perm[12].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_12_enable_12.q", + 0, 4, 0, "BkdrRegPathRtl"); + range_perm[12].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_12_read_access_12.q", + 4, 4, 0, "BkdrRegPathRtl"); + range_perm[12].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_12_write_access_12.q", + 8, 4, 0, "BkdrRegPathRtl"); + range_perm[12].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_12_execute_access_12.q", + 12, 4, 0, "BkdrRegPathRtl"); + range_perm[12].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_12_log_denied_access_12.q", + 16, 4, 0, "BkdrRegPathRtl"); + + range_perm[13] = + (ac_range_check_reg_range_perm:: + type_id::create("range_perm_13")); + range_perm[13].configure(.blk_parent(this)); + range_perm[13].build(csr_excl); + default_map.add_reg(.rg(range_perm[13]), + .offset(32'h1d0)); + range_perm[13].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_13_enable_13.q", + 0, 4, 0, "BkdrRegPathRtl"); + range_perm[13].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_13_read_access_13.q", + 4, 4, 0, "BkdrRegPathRtl"); + range_perm[13].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_13_write_access_13.q", + 8, 4, 0, "BkdrRegPathRtl"); + range_perm[13].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_13_execute_access_13.q", + 12, 4, 0, "BkdrRegPathRtl"); + range_perm[13].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_13_log_denied_access_13.q", + 16, 4, 0, "BkdrRegPathRtl"); + + range_perm[14] = + (ac_range_check_reg_range_perm:: + type_id::create("range_perm_14")); + range_perm[14].configure(.blk_parent(this)); + range_perm[14].build(csr_excl); + default_map.add_reg(.rg(range_perm[14]), + .offset(32'h1d4)); + range_perm[14].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_14_enable_14.q", + 0, 4, 0, "BkdrRegPathRtl"); + range_perm[14].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_14_read_access_14.q", + 4, 4, 0, "BkdrRegPathRtl"); + range_perm[14].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_14_write_access_14.q", + 8, 4, 0, "BkdrRegPathRtl"); + range_perm[14].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_14_execute_access_14.q", + 12, 4, 0, "BkdrRegPathRtl"); + range_perm[14].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_14_log_denied_access_14.q", + 16, 4, 0, "BkdrRegPathRtl"); + + range_perm[15] = + (ac_range_check_reg_range_perm:: + type_id::create("range_perm_15")); + range_perm[15].configure(.blk_parent(this)); + range_perm[15].build(csr_excl); + default_map.add_reg(.rg(range_perm[15]), + .offset(32'h1d8)); + range_perm[15].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_15_enable_15.q", + 0, 4, 0, "BkdrRegPathRtl"); + range_perm[15].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_15_read_access_15.q", + 4, 4, 0, "BkdrRegPathRtl"); + range_perm[15].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_15_write_access_15.q", + 8, 4, 0, "BkdrRegPathRtl"); + range_perm[15].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_15_execute_access_15.q", + 12, 4, 0, "BkdrRegPathRtl"); + range_perm[15].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_15_log_denied_access_15.q", + 16, 4, 0, "BkdrRegPathRtl"); + + range_perm[16] = + (ac_range_check_reg_range_perm:: + type_id::create("range_perm_16")); + range_perm[16].configure(.blk_parent(this)); + range_perm[16].build(csr_excl); + default_map.add_reg(.rg(range_perm[16]), + .offset(32'h1dc)); + range_perm[16].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_16_enable_16.q", + 0, 4, 0, "BkdrRegPathRtl"); + range_perm[16].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_16_read_access_16.q", + 4, 4, 0, "BkdrRegPathRtl"); + range_perm[16].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_16_write_access_16.q", + 8, 4, 0, "BkdrRegPathRtl"); + range_perm[16].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_16_execute_access_16.q", + 12, 4, 0, "BkdrRegPathRtl"); + range_perm[16].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_16_log_denied_access_16.q", + 16, 4, 0, "BkdrRegPathRtl"); + + range_perm[17] = + (ac_range_check_reg_range_perm:: + type_id::create("range_perm_17")); + range_perm[17].configure(.blk_parent(this)); + range_perm[17].build(csr_excl); + default_map.add_reg(.rg(range_perm[17]), + .offset(32'h1e0)); + range_perm[17].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_17_enable_17.q", + 0, 4, 0, "BkdrRegPathRtl"); + range_perm[17].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_17_read_access_17.q", + 4, 4, 0, "BkdrRegPathRtl"); + range_perm[17].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_17_write_access_17.q", + 8, 4, 0, "BkdrRegPathRtl"); + range_perm[17].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_17_execute_access_17.q", + 12, 4, 0, "BkdrRegPathRtl"); + range_perm[17].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_17_log_denied_access_17.q", + 16, 4, 0, "BkdrRegPathRtl"); + + range_perm[18] = + (ac_range_check_reg_range_perm:: + type_id::create("range_perm_18")); + range_perm[18].configure(.blk_parent(this)); + range_perm[18].build(csr_excl); + default_map.add_reg(.rg(range_perm[18]), + .offset(32'h1e4)); + range_perm[18].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_18_enable_18.q", + 0, 4, 0, "BkdrRegPathRtl"); + range_perm[18].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_18_read_access_18.q", + 4, 4, 0, "BkdrRegPathRtl"); + range_perm[18].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_18_write_access_18.q", + 8, 4, 0, "BkdrRegPathRtl"); + range_perm[18].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_18_execute_access_18.q", + 12, 4, 0, "BkdrRegPathRtl"); + range_perm[18].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_18_log_denied_access_18.q", + 16, 4, 0, "BkdrRegPathRtl"); + + range_perm[19] = + (ac_range_check_reg_range_perm:: + type_id::create("range_perm_19")); + range_perm[19].configure(.blk_parent(this)); + range_perm[19].build(csr_excl); + default_map.add_reg(.rg(range_perm[19]), + .offset(32'h1e8)); + range_perm[19].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_19_enable_19.q", + 0, 4, 0, "BkdrRegPathRtl"); + range_perm[19].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_19_read_access_19.q", + 4, 4, 0, "BkdrRegPathRtl"); + range_perm[19].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_19_write_access_19.q", + 8, 4, 0, "BkdrRegPathRtl"); + range_perm[19].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_19_execute_access_19.q", + 12, 4, 0, "BkdrRegPathRtl"); + range_perm[19].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_19_log_denied_access_19.q", + 16, 4, 0, "BkdrRegPathRtl"); + + range_perm[20] = + (ac_range_check_reg_range_perm:: + type_id::create("range_perm_20")); + range_perm[20].configure(.blk_parent(this)); + range_perm[20].build(csr_excl); + default_map.add_reg(.rg(range_perm[20]), + .offset(32'h1ec)); + range_perm[20].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_20_enable_20.q", + 0, 4, 0, "BkdrRegPathRtl"); + range_perm[20].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_20_read_access_20.q", + 4, 4, 0, "BkdrRegPathRtl"); + range_perm[20].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_20_write_access_20.q", + 8, 4, 0, "BkdrRegPathRtl"); + range_perm[20].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_20_execute_access_20.q", + 12, 4, 0, "BkdrRegPathRtl"); + range_perm[20].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_20_log_denied_access_20.q", + 16, 4, 0, "BkdrRegPathRtl"); + + range_perm[21] = + (ac_range_check_reg_range_perm:: + type_id::create("range_perm_21")); + range_perm[21].configure(.blk_parent(this)); + range_perm[21].build(csr_excl); + default_map.add_reg(.rg(range_perm[21]), + .offset(32'h1f0)); + range_perm[21].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_21_enable_21.q", + 0, 4, 0, "BkdrRegPathRtl"); + range_perm[21].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_21_read_access_21.q", + 4, 4, 0, "BkdrRegPathRtl"); + range_perm[21].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_21_write_access_21.q", + 8, 4, 0, "BkdrRegPathRtl"); + range_perm[21].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_21_execute_access_21.q", + 12, 4, 0, "BkdrRegPathRtl"); + range_perm[21].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_21_log_denied_access_21.q", + 16, 4, 0, "BkdrRegPathRtl"); + + range_perm[22] = + (ac_range_check_reg_range_perm:: + type_id::create("range_perm_22")); + range_perm[22].configure(.blk_parent(this)); + range_perm[22].build(csr_excl); + default_map.add_reg(.rg(range_perm[22]), + .offset(32'h1f4)); + range_perm[22].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_22_enable_22.q", + 0, 4, 0, "BkdrRegPathRtl"); + range_perm[22].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_22_read_access_22.q", + 4, 4, 0, "BkdrRegPathRtl"); + range_perm[22].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_22_write_access_22.q", + 8, 4, 0, "BkdrRegPathRtl"); + range_perm[22].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_22_execute_access_22.q", + 12, 4, 0, "BkdrRegPathRtl"); + range_perm[22].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_22_log_denied_access_22.q", + 16, 4, 0, "BkdrRegPathRtl"); + + range_perm[23] = + (ac_range_check_reg_range_perm:: + type_id::create("range_perm_23")); + range_perm[23].configure(.blk_parent(this)); + range_perm[23].build(csr_excl); + default_map.add_reg(.rg(range_perm[23]), + .offset(32'h1f8)); + range_perm[23].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_23_enable_23.q", + 0, 4, 0, "BkdrRegPathRtl"); + range_perm[23].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_23_read_access_23.q", + 4, 4, 0, "BkdrRegPathRtl"); + range_perm[23].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_23_write_access_23.q", + 8, 4, 0, "BkdrRegPathRtl"); + range_perm[23].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_23_execute_access_23.q", + 12, 4, 0, "BkdrRegPathRtl"); + range_perm[23].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_23_log_denied_access_23.q", + 16, 4, 0, "BkdrRegPathRtl"); + + range_perm[24] = + (ac_range_check_reg_range_perm:: + type_id::create("range_perm_24")); + range_perm[24].configure(.blk_parent(this)); + range_perm[24].build(csr_excl); + default_map.add_reg(.rg(range_perm[24]), + .offset(32'h1fc)); + range_perm[24].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_24_enable_24.q", + 0, 4, 0, "BkdrRegPathRtl"); + range_perm[24].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_24_read_access_24.q", + 4, 4, 0, "BkdrRegPathRtl"); + range_perm[24].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_24_write_access_24.q", + 8, 4, 0, "BkdrRegPathRtl"); + range_perm[24].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_24_execute_access_24.q", + 12, 4, 0, "BkdrRegPathRtl"); + range_perm[24].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_24_log_denied_access_24.q", + 16, 4, 0, "BkdrRegPathRtl"); + + range_perm[25] = + (ac_range_check_reg_range_perm:: + type_id::create("range_perm_25")); + range_perm[25].configure(.blk_parent(this)); + range_perm[25].build(csr_excl); + default_map.add_reg(.rg(range_perm[25]), + .offset(32'h200)); + range_perm[25].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_25_enable_25.q", + 0, 4, 0, "BkdrRegPathRtl"); + range_perm[25].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_25_read_access_25.q", + 4, 4, 0, "BkdrRegPathRtl"); + range_perm[25].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_25_write_access_25.q", + 8, 4, 0, "BkdrRegPathRtl"); + range_perm[25].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_25_execute_access_25.q", + 12, 4, 0, "BkdrRegPathRtl"); + range_perm[25].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_25_log_denied_access_25.q", + 16, 4, 0, "BkdrRegPathRtl"); + + range_perm[26] = + (ac_range_check_reg_range_perm:: + type_id::create("range_perm_26")); + range_perm[26].configure(.blk_parent(this)); + range_perm[26].build(csr_excl); + default_map.add_reg(.rg(range_perm[26]), + .offset(32'h204)); + range_perm[26].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_26_enable_26.q", + 0, 4, 0, "BkdrRegPathRtl"); + range_perm[26].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_26_read_access_26.q", + 4, 4, 0, "BkdrRegPathRtl"); + range_perm[26].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_26_write_access_26.q", + 8, 4, 0, "BkdrRegPathRtl"); + range_perm[26].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_26_execute_access_26.q", + 12, 4, 0, "BkdrRegPathRtl"); + range_perm[26].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_26_log_denied_access_26.q", + 16, 4, 0, "BkdrRegPathRtl"); + + range_perm[27] = + (ac_range_check_reg_range_perm:: + type_id::create("range_perm_27")); + range_perm[27].configure(.blk_parent(this)); + range_perm[27].build(csr_excl); + default_map.add_reg(.rg(range_perm[27]), + .offset(32'h208)); + range_perm[27].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_27_enable_27.q", + 0, 4, 0, "BkdrRegPathRtl"); + range_perm[27].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_27_read_access_27.q", + 4, 4, 0, "BkdrRegPathRtl"); + range_perm[27].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_27_write_access_27.q", + 8, 4, 0, "BkdrRegPathRtl"); + range_perm[27].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_27_execute_access_27.q", + 12, 4, 0, "BkdrRegPathRtl"); + range_perm[27].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_27_log_denied_access_27.q", + 16, 4, 0, "BkdrRegPathRtl"); + + range_perm[28] = + (ac_range_check_reg_range_perm:: + type_id::create("range_perm_28")); + range_perm[28].configure(.blk_parent(this)); + range_perm[28].build(csr_excl); + default_map.add_reg(.rg(range_perm[28]), + .offset(32'h20c)); + range_perm[28].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_28_enable_28.q", + 0, 4, 0, "BkdrRegPathRtl"); + range_perm[28].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_28_read_access_28.q", + 4, 4, 0, "BkdrRegPathRtl"); + range_perm[28].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_28_write_access_28.q", + 8, 4, 0, "BkdrRegPathRtl"); + range_perm[28].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_28_execute_access_28.q", + 12, 4, 0, "BkdrRegPathRtl"); + range_perm[28].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_28_log_denied_access_28.q", + 16, 4, 0, "BkdrRegPathRtl"); + + range_perm[29] = + (ac_range_check_reg_range_perm:: + type_id::create("range_perm_29")); + range_perm[29].configure(.blk_parent(this)); + range_perm[29].build(csr_excl); + default_map.add_reg(.rg(range_perm[29]), + .offset(32'h210)); + range_perm[29].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_29_enable_29.q", + 0, 4, 0, "BkdrRegPathRtl"); + range_perm[29].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_29_read_access_29.q", + 4, 4, 0, "BkdrRegPathRtl"); + range_perm[29].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_29_write_access_29.q", + 8, 4, 0, "BkdrRegPathRtl"); + range_perm[29].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_29_execute_access_29.q", + 12, 4, 0, "BkdrRegPathRtl"); + range_perm[29].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_29_log_denied_access_29.q", + 16, 4, 0, "BkdrRegPathRtl"); + + range_perm[30] = + (ac_range_check_reg_range_perm:: + type_id::create("range_perm_30")); + range_perm[30].configure(.blk_parent(this)); + range_perm[30].build(csr_excl); + default_map.add_reg(.rg(range_perm[30]), + .offset(32'h214)); + range_perm[30].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_30_enable_30.q", + 0, 4, 0, "BkdrRegPathRtl"); + range_perm[30].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_30_read_access_30.q", + 4, 4, 0, "BkdrRegPathRtl"); + range_perm[30].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_30_write_access_30.q", + 8, 4, 0, "BkdrRegPathRtl"); + range_perm[30].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_30_execute_access_30.q", + 12, 4, 0, "BkdrRegPathRtl"); + range_perm[30].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_30_log_denied_access_30.q", + 16, 4, 0, "BkdrRegPathRtl"); + + range_perm[31] = + (ac_range_check_reg_range_perm:: + type_id::create("range_perm_31")); + range_perm[31].configure(.blk_parent(this)); + range_perm[31].build(csr_excl); + default_map.add_reg(.rg(range_perm[31]), + .offset(32'h218)); + range_perm[31].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_31_enable_31.q", + 0, 4, 0, "BkdrRegPathRtl"); + range_perm[31].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_31_read_access_31.q", + 4, 4, 0, "BkdrRegPathRtl"); + range_perm[31].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_31_write_access_31.q", + 8, 4, 0, "BkdrRegPathRtl"); + range_perm[31].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_31_execute_access_31.q", + 12, 4, 0, "BkdrRegPathRtl"); + range_perm[31].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_perm_31_log_denied_access_31.q", + 16, 4, 0, "BkdrRegPathRtl"); + + range_racl_policy_shadowed[0] = + (ac_range_check_reg_range_racl_policy_shadowed:: + type_id::create("range_racl_policy_shadowed_0")); + range_racl_policy_shadowed[0].configure(.blk_parent(this)); + range_racl_policy_shadowed[0].build(csr_excl); + default_map.add_reg(.rg(range_racl_policy_shadowed[0]), + .offset(32'h21c)); + range_racl_policy_shadowed[0].add_update_err_alert("recov_ctrl_update_err"); + + range_racl_policy_shadowed[0].add_storage_err_alert("fatal_fault"); + + range_racl_policy_shadowed[0].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_0_read_perm_0.committed_reg.q", + 0, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[0].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_0_read_perm_0.shadow_reg.q", + 0, 16, 0, "BkdrRegPathRtlShadow"); + range_racl_policy_shadowed[0].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_0_write_perm_0.committed_reg.q", + 16, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[0].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_0_write_perm_0.shadow_reg.q", + 16, 16, 0, "BkdrRegPathRtlShadow"); + + range_racl_policy_shadowed[0].set_is_shadowed(); + range_racl_policy_shadowed[1] = + (ac_range_check_reg_range_racl_policy_shadowed:: + type_id::create("range_racl_policy_shadowed_1")); + range_racl_policy_shadowed[1].configure(.blk_parent(this)); + range_racl_policy_shadowed[1].build(csr_excl); + default_map.add_reg(.rg(range_racl_policy_shadowed[1]), + .offset(32'h220)); + range_racl_policy_shadowed[1].add_update_err_alert("recov_ctrl_update_err"); + + range_racl_policy_shadowed[1].add_storage_err_alert("fatal_fault"); + + range_racl_policy_shadowed[1].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_1_read_perm_1.committed_reg.q", + 0, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[1].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_1_read_perm_1.shadow_reg.q", + 0, 16, 0, "BkdrRegPathRtlShadow"); + range_racl_policy_shadowed[1].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_1_write_perm_1.committed_reg.q", + 16, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[1].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_1_write_perm_1.shadow_reg.q", + 16, 16, 0, "BkdrRegPathRtlShadow"); + + range_racl_policy_shadowed[1].set_is_shadowed(); + range_racl_policy_shadowed[2] = + (ac_range_check_reg_range_racl_policy_shadowed:: + type_id::create("range_racl_policy_shadowed_2")); + range_racl_policy_shadowed[2].configure(.blk_parent(this)); + range_racl_policy_shadowed[2].build(csr_excl); + default_map.add_reg(.rg(range_racl_policy_shadowed[2]), + .offset(32'h224)); + range_racl_policy_shadowed[2].add_update_err_alert("recov_ctrl_update_err"); + + range_racl_policy_shadowed[2].add_storage_err_alert("fatal_fault"); + + range_racl_policy_shadowed[2].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_2_read_perm_2.committed_reg.q", + 0, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[2].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_2_read_perm_2.shadow_reg.q", + 0, 16, 0, "BkdrRegPathRtlShadow"); + range_racl_policy_shadowed[2].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_2_write_perm_2.committed_reg.q", + 16, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[2].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_2_write_perm_2.shadow_reg.q", + 16, 16, 0, "BkdrRegPathRtlShadow"); + + range_racl_policy_shadowed[2].set_is_shadowed(); + range_racl_policy_shadowed[3] = + (ac_range_check_reg_range_racl_policy_shadowed:: + type_id::create("range_racl_policy_shadowed_3")); + range_racl_policy_shadowed[3].configure(.blk_parent(this)); + range_racl_policy_shadowed[3].build(csr_excl); + default_map.add_reg(.rg(range_racl_policy_shadowed[3]), + .offset(32'h228)); + range_racl_policy_shadowed[3].add_update_err_alert("recov_ctrl_update_err"); + + range_racl_policy_shadowed[3].add_storage_err_alert("fatal_fault"); + + range_racl_policy_shadowed[3].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_3_read_perm_3.committed_reg.q", + 0, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[3].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_3_read_perm_3.shadow_reg.q", + 0, 16, 0, "BkdrRegPathRtlShadow"); + range_racl_policy_shadowed[3].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_3_write_perm_3.committed_reg.q", + 16, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[3].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_3_write_perm_3.shadow_reg.q", + 16, 16, 0, "BkdrRegPathRtlShadow"); + + range_racl_policy_shadowed[3].set_is_shadowed(); + range_racl_policy_shadowed[4] = + (ac_range_check_reg_range_racl_policy_shadowed:: + type_id::create("range_racl_policy_shadowed_4")); + range_racl_policy_shadowed[4].configure(.blk_parent(this)); + range_racl_policy_shadowed[4].build(csr_excl); + default_map.add_reg(.rg(range_racl_policy_shadowed[4]), + .offset(32'h22c)); + range_racl_policy_shadowed[4].add_update_err_alert("recov_ctrl_update_err"); + + range_racl_policy_shadowed[4].add_storage_err_alert("fatal_fault"); + + range_racl_policy_shadowed[4].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_4_read_perm_4.committed_reg.q", + 0, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[4].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_4_read_perm_4.shadow_reg.q", + 0, 16, 0, "BkdrRegPathRtlShadow"); + range_racl_policy_shadowed[4].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_4_write_perm_4.committed_reg.q", + 16, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[4].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_4_write_perm_4.shadow_reg.q", + 16, 16, 0, "BkdrRegPathRtlShadow"); + + range_racl_policy_shadowed[4].set_is_shadowed(); + range_racl_policy_shadowed[5] = + (ac_range_check_reg_range_racl_policy_shadowed:: + type_id::create("range_racl_policy_shadowed_5")); + range_racl_policy_shadowed[5].configure(.blk_parent(this)); + range_racl_policy_shadowed[5].build(csr_excl); + default_map.add_reg(.rg(range_racl_policy_shadowed[5]), + .offset(32'h230)); + range_racl_policy_shadowed[5].add_update_err_alert("recov_ctrl_update_err"); + + range_racl_policy_shadowed[5].add_storage_err_alert("fatal_fault"); + + range_racl_policy_shadowed[5].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_5_read_perm_5.committed_reg.q", + 0, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[5].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_5_read_perm_5.shadow_reg.q", + 0, 16, 0, "BkdrRegPathRtlShadow"); + range_racl_policy_shadowed[5].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_5_write_perm_5.committed_reg.q", + 16, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[5].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_5_write_perm_5.shadow_reg.q", + 16, 16, 0, "BkdrRegPathRtlShadow"); + + range_racl_policy_shadowed[5].set_is_shadowed(); + range_racl_policy_shadowed[6] = + (ac_range_check_reg_range_racl_policy_shadowed:: + type_id::create("range_racl_policy_shadowed_6")); + range_racl_policy_shadowed[6].configure(.blk_parent(this)); + range_racl_policy_shadowed[6].build(csr_excl); + default_map.add_reg(.rg(range_racl_policy_shadowed[6]), + .offset(32'h234)); + range_racl_policy_shadowed[6].add_update_err_alert("recov_ctrl_update_err"); + + range_racl_policy_shadowed[6].add_storage_err_alert("fatal_fault"); + + range_racl_policy_shadowed[6].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_6_read_perm_6.committed_reg.q", + 0, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[6].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_6_read_perm_6.shadow_reg.q", + 0, 16, 0, "BkdrRegPathRtlShadow"); + range_racl_policy_shadowed[6].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_6_write_perm_6.committed_reg.q", + 16, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[6].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_6_write_perm_6.shadow_reg.q", + 16, 16, 0, "BkdrRegPathRtlShadow"); + + range_racl_policy_shadowed[6].set_is_shadowed(); + range_racl_policy_shadowed[7] = + (ac_range_check_reg_range_racl_policy_shadowed:: + type_id::create("range_racl_policy_shadowed_7")); + range_racl_policy_shadowed[7].configure(.blk_parent(this)); + range_racl_policy_shadowed[7].build(csr_excl); + default_map.add_reg(.rg(range_racl_policy_shadowed[7]), + .offset(32'h238)); + range_racl_policy_shadowed[7].add_update_err_alert("recov_ctrl_update_err"); + + range_racl_policy_shadowed[7].add_storage_err_alert("fatal_fault"); + + range_racl_policy_shadowed[7].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_7_read_perm_7.committed_reg.q", + 0, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[7].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_7_read_perm_7.shadow_reg.q", + 0, 16, 0, "BkdrRegPathRtlShadow"); + range_racl_policy_shadowed[7].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_7_write_perm_7.committed_reg.q", + 16, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[7].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_7_write_perm_7.shadow_reg.q", + 16, 16, 0, "BkdrRegPathRtlShadow"); + + range_racl_policy_shadowed[7].set_is_shadowed(); + range_racl_policy_shadowed[8] = + (ac_range_check_reg_range_racl_policy_shadowed:: + type_id::create("range_racl_policy_shadowed_8")); + range_racl_policy_shadowed[8].configure(.blk_parent(this)); + range_racl_policy_shadowed[8].build(csr_excl); + default_map.add_reg(.rg(range_racl_policy_shadowed[8]), + .offset(32'h23c)); + range_racl_policy_shadowed[8].add_update_err_alert("recov_ctrl_update_err"); + + range_racl_policy_shadowed[8].add_storage_err_alert("fatal_fault"); + + range_racl_policy_shadowed[8].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_8_read_perm_8.committed_reg.q", + 0, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[8].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_8_read_perm_8.shadow_reg.q", + 0, 16, 0, "BkdrRegPathRtlShadow"); + range_racl_policy_shadowed[8].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_8_write_perm_8.committed_reg.q", + 16, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[8].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_8_write_perm_8.shadow_reg.q", + 16, 16, 0, "BkdrRegPathRtlShadow"); + + range_racl_policy_shadowed[8].set_is_shadowed(); + range_racl_policy_shadowed[9] = + (ac_range_check_reg_range_racl_policy_shadowed:: + type_id::create("range_racl_policy_shadowed_9")); + range_racl_policy_shadowed[9].configure(.blk_parent(this)); + range_racl_policy_shadowed[9].build(csr_excl); + default_map.add_reg(.rg(range_racl_policy_shadowed[9]), + .offset(32'h240)); + range_racl_policy_shadowed[9].add_update_err_alert("recov_ctrl_update_err"); + + range_racl_policy_shadowed[9].add_storage_err_alert("fatal_fault"); + + range_racl_policy_shadowed[9].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_9_read_perm_9.committed_reg.q", + 0, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[9].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_9_read_perm_9.shadow_reg.q", + 0, 16, 0, "BkdrRegPathRtlShadow"); + range_racl_policy_shadowed[9].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_9_write_perm_9.committed_reg.q", + 16, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[9].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_9_write_perm_9.shadow_reg.q", + 16, 16, 0, "BkdrRegPathRtlShadow"); + + range_racl_policy_shadowed[9].set_is_shadowed(); + range_racl_policy_shadowed[10] = + (ac_range_check_reg_range_racl_policy_shadowed:: + type_id::create("range_racl_policy_shadowed_10")); + range_racl_policy_shadowed[10].configure(.blk_parent(this)); + range_racl_policy_shadowed[10].build(csr_excl); + default_map.add_reg(.rg(range_racl_policy_shadowed[10]), + .offset(32'h244)); + range_racl_policy_shadowed[10].add_update_err_alert("recov_ctrl_update_err"); + + range_racl_policy_shadowed[10].add_storage_err_alert("fatal_fault"); + + range_racl_policy_shadowed[10].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_10_read_perm_10.committed_reg.q", + 0, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[10].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_10_read_perm_10.shadow_reg.q", + 0, 16, 0, "BkdrRegPathRtlShadow"); + range_racl_policy_shadowed[10].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_10_write_perm_10.committed_reg.q", + 16, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[10].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_10_write_perm_10.shadow_reg.q", + 16, 16, 0, "BkdrRegPathRtlShadow"); + + range_racl_policy_shadowed[10].set_is_shadowed(); + range_racl_policy_shadowed[11] = + (ac_range_check_reg_range_racl_policy_shadowed:: + type_id::create("range_racl_policy_shadowed_11")); + range_racl_policy_shadowed[11].configure(.blk_parent(this)); + range_racl_policy_shadowed[11].build(csr_excl); + default_map.add_reg(.rg(range_racl_policy_shadowed[11]), + .offset(32'h248)); + range_racl_policy_shadowed[11].add_update_err_alert("recov_ctrl_update_err"); + + range_racl_policy_shadowed[11].add_storage_err_alert("fatal_fault"); + + range_racl_policy_shadowed[11].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_11_read_perm_11.committed_reg.q", + 0, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[11].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_11_read_perm_11.shadow_reg.q", + 0, 16, 0, "BkdrRegPathRtlShadow"); + range_racl_policy_shadowed[11].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_11_write_perm_11.committed_reg.q", + 16, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[11].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_11_write_perm_11.shadow_reg.q", + 16, 16, 0, "BkdrRegPathRtlShadow"); + + range_racl_policy_shadowed[11].set_is_shadowed(); + range_racl_policy_shadowed[12] = + (ac_range_check_reg_range_racl_policy_shadowed:: + type_id::create("range_racl_policy_shadowed_12")); + range_racl_policy_shadowed[12].configure(.blk_parent(this)); + range_racl_policy_shadowed[12].build(csr_excl); + default_map.add_reg(.rg(range_racl_policy_shadowed[12]), + .offset(32'h24c)); + range_racl_policy_shadowed[12].add_update_err_alert("recov_ctrl_update_err"); + + range_racl_policy_shadowed[12].add_storage_err_alert("fatal_fault"); + + range_racl_policy_shadowed[12].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_12_read_perm_12.committed_reg.q", + 0, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[12].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_12_read_perm_12.shadow_reg.q", + 0, 16, 0, "BkdrRegPathRtlShadow"); + range_racl_policy_shadowed[12].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_12_write_perm_12.committed_reg.q", + 16, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[12].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_12_write_perm_12.shadow_reg.q", + 16, 16, 0, "BkdrRegPathRtlShadow"); + + range_racl_policy_shadowed[12].set_is_shadowed(); + range_racl_policy_shadowed[13] = + (ac_range_check_reg_range_racl_policy_shadowed:: + type_id::create("range_racl_policy_shadowed_13")); + range_racl_policy_shadowed[13].configure(.blk_parent(this)); + range_racl_policy_shadowed[13].build(csr_excl); + default_map.add_reg(.rg(range_racl_policy_shadowed[13]), + .offset(32'h250)); + range_racl_policy_shadowed[13].add_update_err_alert("recov_ctrl_update_err"); + + range_racl_policy_shadowed[13].add_storage_err_alert("fatal_fault"); + + range_racl_policy_shadowed[13].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_13_read_perm_13.committed_reg.q", + 0, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[13].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_13_read_perm_13.shadow_reg.q", + 0, 16, 0, "BkdrRegPathRtlShadow"); + range_racl_policy_shadowed[13].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_13_write_perm_13.committed_reg.q", + 16, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[13].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_13_write_perm_13.shadow_reg.q", + 16, 16, 0, "BkdrRegPathRtlShadow"); + + range_racl_policy_shadowed[13].set_is_shadowed(); + range_racl_policy_shadowed[14] = + (ac_range_check_reg_range_racl_policy_shadowed:: + type_id::create("range_racl_policy_shadowed_14")); + range_racl_policy_shadowed[14].configure(.blk_parent(this)); + range_racl_policy_shadowed[14].build(csr_excl); + default_map.add_reg(.rg(range_racl_policy_shadowed[14]), + .offset(32'h254)); + range_racl_policy_shadowed[14].add_update_err_alert("recov_ctrl_update_err"); + + range_racl_policy_shadowed[14].add_storage_err_alert("fatal_fault"); + + range_racl_policy_shadowed[14].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_14_read_perm_14.committed_reg.q", + 0, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[14].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_14_read_perm_14.shadow_reg.q", + 0, 16, 0, "BkdrRegPathRtlShadow"); + range_racl_policy_shadowed[14].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_14_write_perm_14.committed_reg.q", + 16, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[14].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_14_write_perm_14.shadow_reg.q", + 16, 16, 0, "BkdrRegPathRtlShadow"); + + range_racl_policy_shadowed[14].set_is_shadowed(); + range_racl_policy_shadowed[15] = + (ac_range_check_reg_range_racl_policy_shadowed:: + type_id::create("range_racl_policy_shadowed_15")); + range_racl_policy_shadowed[15].configure(.blk_parent(this)); + range_racl_policy_shadowed[15].build(csr_excl); + default_map.add_reg(.rg(range_racl_policy_shadowed[15]), + .offset(32'h258)); + range_racl_policy_shadowed[15].add_update_err_alert("recov_ctrl_update_err"); + + range_racl_policy_shadowed[15].add_storage_err_alert("fatal_fault"); + + range_racl_policy_shadowed[15].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_15_read_perm_15.committed_reg.q", + 0, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[15].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_15_read_perm_15.shadow_reg.q", + 0, 16, 0, "BkdrRegPathRtlShadow"); + range_racl_policy_shadowed[15].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_15_write_perm_15.committed_reg.q", + 16, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[15].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_15_write_perm_15.shadow_reg.q", + 16, 16, 0, "BkdrRegPathRtlShadow"); + + range_racl_policy_shadowed[15].set_is_shadowed(); + range_racl_policy_shadowed[16] = + (ac_range_check_reg_range_racl_policy_shadowed:: + type_id::create("range_racl_policy_shadowed_16")); + range_racl_policy_shadowed[16].configure(.blk_parent(this)); + range_racl_policy_shadowed[16].build(csr_excl); + default_map.add_reg(.rg(range_racl_policy_shadowed[16]), + .offset(32'h25c)); + range_racl_policy_shadowed[16].add_update_err_alert("recov_ctrl_update_err"); + + range_racl_policy_shadowed[16].add_storage_err_alert("fatal_fault"); + + range_racl_policy_shadowed[16].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_16_read_perm_16.committed_reg.q", + 0, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[16].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_16_read_perm_16.shadow_reg.q", + 0, 16, 0, "BkdrRegPathRtlShadow"); + range_racl_policy_shadowed[16].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_16_write_perm_16.committed_reg.q", + 16, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[16].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_16_write_perm_16.shadow_reg.q", + 16, 16, 0, "BkdrRegPathRtlShadow"); + + range_racl_policy_shadowed[16].set_is_shadowed(); + range_racl_policy_shadowed[17] = + (ac_range_check_reg_range_racl_policy_shadowed:: + type_id::create("range_racl_policy_shadowed_17")); + range_racl_policy_shadowed[17].configure(.blk_parent(this)); + range_racl_policy_shadowed[17].build(csr_excl); + default_map.add_reg(.rg(range_racl_policy_shadowed[17]), + .offset(32'h260)); + range_racl_policy_shadowed[17].add_update_err_alert("recov_ctrl_update_err"); + + range_racl_policy_shadowed[17].add_storage_err_alert("fatal_fault"); + + range_racl_policy_shadowed[17].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_17_read_perm_17.committed_reg.q", + 0, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[17].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_17_read_perm_17.shadow_reg.q", + 0, 16, 0, "BkdrRegPathRtlShadow"); + range_racl_policy_shadowed[17].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_17_write_perm_17.committed_reg.q", + 16, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[17].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_17_write_perm_17.shadow_reg.q", + 16, 16, 0, "BkdrRegPathRtlShadow"); + + range_racl_policy_shadowed[17].set_is_shadowed(); + range_racl_policy_shadowed[18] = + (ac_range_check_reg_range_racl_policy_shadowed:: + type_id::create("range_racl_policy_shadowed_18")); + range_racl_policy_shadowed[18].configure(.blk_parent(this)); + range_racl_policy_shadowed[18].build(csr_excl); + default_map.add_reg(.rg(range_racl_policy_shadowed[18]), + .offset(32'h264)); + range_racl_policy_shadowed[18].add_update_err_alert("recov_ctrl_update_err"); + + range_racl_policy_shadowed[18].add_storage_err_alert("fatal_fault"); + + range_racl_policy_shadowed[18].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_18_read_perm_18.committed_reg.q", + 0, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[18].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_18_read_perm_18.shadow_reg.q", + 0, 16, 0, "BkdrRegPathRtlShadow"); + range_racl_policy_shadowed[18].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_18_write_perm_18.committed_reg.q", + 16, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[18].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_18_write_perm_18.shadow_reg.q", + 16, 16, 0, "BkdrRegPathRtlShadow"); + + range_racl_policy_shadowed[18].set_is_shadowed(); + range_racl_policy_shadowed[19] = + (ac_range_check_reg_range_racl_policy_shadowed:: + type_id::create("range_racl_policy_shadowed_19")); + range_racl_policy_shadowed[19].configure(.blk_parent(this)); + range_racl_policy_shadowed[19].build(csr_excl); + default_map.add_reg(.rg(range_racl_policy_shadowed[19]), + .offset(32'h268)); + range_racl_policy_shadowed[19].add_update_err_alert("recov_ctrl_update_err"); + + range_racl_policy_shadowed[19].add_storage_err_alert("fatal_fault"); + + range_racl_policy_shadowed[19].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_19_read_perm_19.committed_reg.q", + 0, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[19].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_19_read_perm_19.shadow_reg.q", + 0, 16, 0, "BkdrRegPathRtlShadow"); + range_racl_policy_shadowed[19].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_19_write_perm_19.committed_reg.q", + 16, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[19].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_19_write_perm_19.shadow_reg.q", + 16, 16, 0, "BkdrRegPathRtlShadow"); + + range_racl_policy_shadowed[19].set_is_shadowed(); + range_racl_policy_shadowed[20] = + (ac_range_check_reg_range_racl_policy_shadowed:: + type_id::create("range_racl_policy_shadowed_20")); + range_racl_policy_shadowed[20].configure(.blk_parent(this)); + range_racl_policy_shadowed[20].build(csr_excl); + default_map.add_reg(.rg(range_racl_policy_shadowed[20]), + .offset(32'h26c)); + range_racl_policy_shadowed[20].add_update_err_alert("recov_ctrl_update_err"); + + range_racl_policy_shadowed[20].add_storage_err_alert("fatal_fault"); + + range_racl_policy_shadowed[20].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_20_read_perm_20.committed_reg.q", + 0, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[20].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_20_read_perm_20.shadow_reg.q", + 0, 16, 0, "BkdrRegPathRtlShadow"); + range_racl_policy_shadowed[20].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_20_write_perm_20.committed_reg.q", + 16, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[20].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_20_write_perm_20.shadow_reg.q", + 16, 16, 0, "BkdrRegPathRtlShadow"); + + range_racl_policy_shadowed[20].set_is_shadowed(); + range_racl_policy_shadowed[21] = + (ac_range_check_reg_range_racl_policy_shadowed:: + type_id::create("range_racl_policy_shadowed_21")); + range_racl_policy_shadowed[21].configure(.blk_parent(this)); + range_racl_policy_shadowed[21].build(csr_excl); + default_map.add_reg(.rg(range_racl_policy_shadowed[21]), + .offset(32'h270)); + range_racl_policy_shadowed[21].add_update_err_alert("recov_ctrl_update_err"); + + range_racl_policy_shadowed[21].add_storage_err_alert("fatal_fault"); + + range_racl_policy_shadowed[21].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_21_read_perm_21.committed_reg.q", + 0, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[21].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_21_read_perm_21.shadow_reg.q", + 0, 16, 0, "BkdrRegPathRtlShadow"); + range_racl_policy_shadowed[21].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_21_write_perm_21.committed_reg.q", + 16, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[21].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_21_write_perm_21.shadow_reg.q", + 16, 16, 0, "BkdrRegPathRtlShadow"); + + range_racl_policy_shadowed[21].set_is_shadowed(); + range_racl_policy_shadowed[22] = + (ac_range_check_reg_range_racl_policy_shadowed:: + type_id::create("range_racl_policy_shadowed_22")); + range_racl_policy_shadowed[22].configure(.blk_parent(this)); + range_racl_policy_shadowed[22].build(csr_excl); + default_map.add_reg(.rg(range_racl_policy_shadowed[22]), + .offset(32'h274)); + range_racl_policy_shadowed[22].add_update_err_alert("recov_ctrl_update_err"); + + range_racl_policy_shadowed[22].add_storage_err_alert("fatal_fault"); + + range_racl_policy_shadowed[22].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_22_read_perm_22.committed_reg.q", + 0, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[22].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_22_read_perm_22.shadow_reg.q", + 0, 16, 0, "BkdrRegPathRtlShadow"); + range_racl_policy_shadowed[22].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_22_write_perm_22.committed_reg.q", + 16, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[22].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_22_write_perm_22.shadow_reg.q", + 16, 16, 0, "BkdrRegPathRtlShadow"); + + range_racl_policy_shadowed[22].set_is_shadowed(); + range_racl_policy_shadowed[23] = + (ac_range_check_reg_range_racl_policy_shadowed:: + type_id::create("range_racl_policy_shadowed_23")); + range_racl_policy_shadowed[23].configure(.blk_parent(this)); + range_racl_policy_shadowed[23].build(csr_excl); + default_map.add_reg(.rg(range_racl_policy_shadowed[23]), + .offset(32'h278)); + range_racl_policy_shadowed[23].add_update_err_alert("recov_ctrl_update_err"); + + range_racl_policy_shadowed[23].add_storage_err_alert("fatal_fault"); + + range_racl_policy_shadowed[23].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_23_read_perm_23.committed_reg.q", + 0, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[23].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_23_read_perm_23.shadow_reg.q", + 0, 16, 0, "BkdrRegPathRtlShadow"); + range_racl_policy_shadowed[23].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_23_write_perm_23.committed_reg.q", + 16, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[23].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_23_write_perm_23.shadow_reg.q", + 16, 16, 0, "BkdrRegPathRtlShadow"); + + range_racl_policy_shadowed[23].set_is_shadowed(); + range_racl_policy_shadowed[24] = + (ac_range_check_reg_range_racl_policy_shadowed:: + type_id::create("range_racl_policy_shadowed_24")); + range_racl_policy_shadowed[24].configure(.blk_parent(this)); + range_racl_policy_shadowed[24].build(csr_excl); + default_map.add_reg(.rg(range_racl_policy_shadowed[24]), + .offset(32'h27c)); + range_racl_policy_shadowed[24].add_update_err_alert("recov_ctrl_update_err"); + + range_racl_policy_shadowed[24].add_storage_err_alert("fatal_fault"); + + range_racl_policy_shadowed[24].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_24_read_perm_24.committed_reg.q", + 0, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[24].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_24_read_perm_24.shadow_reg.q", + 0, 16, 0, "BkdrRegPathRtlShadow"); + range_racl_policy_shadowed[24].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_24_write_perm_24.committed_reg.q", + 16, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[24].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_24_write_perm_24.shadow_reg.q", + 16, 16, 0, "BkdrRegPathRtlShadow"); + + range_racl_policy_shadowed[24].set_is_shadowed(); + range_racl_policy_shadowed[25] = + (ac_range_check_reg_range_racl_policy_shadowed:: + type_id::create("range_racl_policy_shadowed_25")); + range_racl_policy_shadowed[25].configure(.blk_parent(this)); + range_racl_policy_shadowed[25].build(csr_excl); + default_map.add_reg(.rg(range_racl_policy_shadowed[25]), + .offset(32'h280)); + range_racl_policy_shadowed[25].add_update_err_alert("recov_ctrl_update_err"); + + range_racl_policy_shadowed[25].add_storage_err_alert("fatal_fault"); + + range_racl_policy_shadowed[25].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_25_read_perm_25.committed_reg.q", + 0, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[25].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_25_read_perm_25.shadow_reg.q", + 0, 16, 0, "BkdrRegPathRtlShadow"); + range_racl_policy_shadowed[25].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_25_write_perm_25.committed_reg.q", + 16, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[25].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_25_write_perm_25.shadow_reg.q", + 16, 16, 0, "BkdrRegPathRtlShadow"); + + range_racl_policy_shadowed[25].set_is_shadowed(); + range_racl_policy_shadowed[26] = + (ac_range_check_reg_range_racl_policy_shadowed:: + type_id::create("range_racl_policy_shadowed_26")); + range_racl_policy_shadowed[26].configure(.blk_parent(this)); + range_racl_policy_shadowed[26].build(csr_excl); + default_map.add_reg(.rg(range_racl_policy_shadowed[26]), + .offset(32'h284)); + range_racl_policy_shadowed[26].add_update_err_alert("recov_ctrl_update_err"); + + range_racl_policy_shadowed[26].add_storage_err_alert("fatal_fault"); + + range_racl_policy_shadowed[26].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_26_read_perm_26.committed_reg.q", + 0, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[26].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_26_read_perm_26.shadow_reg.q", + 0, 16, 0, "BkdrRegPathRtlShadow"); + range_racl_policy_shadowed[26].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_26_write_perm_26.committed_reg.q", + 16, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[26].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_26_write_perm_26.shadow_reg.q", + 16, 16, 0, "BkdrRegPathRtlShadow"); + + range_racl_policy_shadowed[26].set_is_shadowed(); + range_racl_policy_shadowed[27] = + (ac_range_check_reg_range_racl_policy_shadowed:: + type_id::create("range_racl_policy_shadowed_27")); + range_racl_policy_shadowed[27].configure(.blk_parent(this)); + range_racl_policy_shadowed[27].build(csr_excl); + default_map.add_reg(.rg(range_racl_policy_shadowed[27]), + .offset(32'h288)); + range_racl_policy_shadowed[27].add_update_err_alert("recov_ctrl_update_err"); + + range_racl_policy_shadowed[27].add_storage_err_alert("fatal_fault"); + + range_racl_policy_shadowed[27].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_27_read_perm_27.committed_reg.q", + 0, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[27].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_27_read_perm_27.shadow_reg.q", + 0, 16, 0, "BkdrRegPathRtlShadow"); + range_racl_policy_shadowed[27].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_27_write_perm_27.committed_reg.q", + 16, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[27].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_27_write_perm_27.shadow_reg.q", + 16, 16, 0, "BkdrRegPathRtlShadow"); + + range_racl_policy_shadowed[27].set_is_shadowed(); + range_racl_policy_shadowed[28] = + (ac_range_check_reg_range_racl_policy_shadowed:: + type_id::create("range_racl_policy_shadowed_28")); + range_racl_policy_shadowed[28].configure(.blk_parent(this)); + range_racl_policy_shadowed[28].build(csr_excl); + default_map.add_reg(.rg(range_racl_policy_shadowed[28]), + .offset(32'h28c)); + range_racl_policy_shadowed[28].add_update_err_alert("recov_ctrl_update_err"); + + range_racl_policy_shadowed[28].add_storage_err_alert("fatal_fault"); + + range_racl_policy_shadowed[28].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_28_read_perm_28.committed_reg.q", + 0, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[28].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_28_read_perm_28.shadow_reg.q", + 0, 16, 0, "BkdrRegPathRtlShadow"); + range_racl_policy_shadowed[28].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_28_write_perm_28.committed_reg.q", + 16, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[28].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_28_write_perm_28.shadow_reg.q", + 16, 16, 0, "BkdrRegPathRtlShadow"); + + range_racl_policy_shadowed[28].set_is_shadowed(); + range_racl_policy_shadowed[29] = + (ac_range_check_reg_range_racl_policy_shadowed:: + type_id::create("range_racl_policy_shadowed_29")); + range_racl_policy_shadowed[29].configure(.blk_parent(this)); + range_racl_policy_shadowed[29].build(csr_excl); + default_map.add_reg(.rg(range_racl_policy_shadowed[29]), + .offset(32'h290)); + range_racl_policy_shadowed[29].add_update_err_alert("recov_ctrl_update_err"); + + range_racl_policy_shadowed[29].add_storage_err_alert("fatal_fault"); + + range_racl_policy_shadowed[29].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_29_read_perm_29.committed_reg.q", + 0, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[29].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_29_read_perm_29.shadow_reg.q", + 0, 16, 0, "BkdrRegPathRtlShadow"); + range_racl_policy_shadowed[29].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_29_write_perm_29.committed_reg.q", + 16, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[29].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_29_write_perm_29.shadow_reg.q", + 16, 16, 0, "BkdrRegPathRtlShadow"); + + range_racl_policy_shadowed[29].set_is_shadowed(); + range_racl_policy_shadowed[30] = + (ac_range_check_reg_range_racl_policy_shadowed:: + type_id::create("range_racl_policy_shadowed_30")); + range_racl_policy_shadowed[30].configure(.blk_parent(this)); + range_racl_policy_shadowed[30].build(csr_excl); + default_map.add_reg(.rg(range_racl_policy_shadowed[30]), + .offset(32'h294)); + range_racl_policy_shadowed[30].add_update_err_alert("recov_ctrl_update_err"); + + range_racl_policy_shadowed[30].add_storage_err_alert("fatal_fault"); + + range_racl_policy_shadowed[30].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_30_read_perm_30.committed_reg.q", + 0, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[30].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_30_read_perm_30.shadow_reg.q", + 0, 16, 0, "BkdrRegPathRtlShadow"); + range_racl_policy_shadowed[30].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_30_write_perm_30.committed_reg.q", + 16, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[30].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_30_write_perm_30.shadow_reg.q", + 16, 16, 0, "BkdrRegPathRtlShadow"); + + range_racl_policy_shadowed[30].set_is_shadowed(); + range_racl_policy_shadowed[31] = + (ac_range_check_reg_range_racl_policy_shadowed:: + type_id::create("range_racl_policy_shadowed_31")); + range_racl_policy_shadowed[31].configure(.blk_parent(this)); + range_racl_policy_shadowed[31].build(csr_excl); + default_map.add_reg(.rg(range_racl_policy_shadowed[31]), + .offset(32'h298)); + range_racl_policy_shadowed[31].add_update_err_alert("recov_ctrl_update_err"); + + range_racl_policy_shadowed[31].add_storage_err_alert("fatal_fault"); + + range_racl_policy_shadowed[31].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_31_read_perm_31.committed_reg.q", + 0, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[31].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_31_read_perm_31.shadow_reg.q", + 0, 16, 0, "BkdrRegPathRtlShadow"); + range_racl_policy_shadowed[31].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_31_write_perm_31.committed_reg.q", + 16, 16, 0, "BkdrRegPathRtl"); + range_racl_policy_shadowed[31].add_hdl_path_slice( + "u_ac_range_check_reg.u_range_racl_policy_shadowed_31_write_perm_31.shadow_reg.q", + 16, 16, 0, "BkdrRegPathRtlShadow"); + + range_racl_policy_shadowed[31].set_is_shadowed(); + // assign locked reg to its regwen reg + range_regwen[0].add_lockable_reg_or_fld(range_base[0]); + range_regwen[1].add_lockable_reg_or_fld(range_base[1]); + range_regwen[2].add_lockable_reg_or_fld(range_base[2]); + range_regwen[3].add_lockable_reg_or_fld(range_base[3]); + range_regwen[4].add_lockable_reg_or_fld(range_base[4]); + range_regwen[5].add_lockable_reg_or_fld(range_base[5]); + range_regwen[6].add_lockable_reg_or_fld(range_base[6]); + range_regwen[7].add_lockable_reg_or_fld(range_base[7]); + range_regwen[8].add_lockable_reg_or_fld(range_base[8]); + range_regwen[9].add_lockable_reg_or_fld(range_base[9]); + range_regwen[10].add_lockable_reg_or_fld(range_base[10]); + range_regwen[11].add_lockable_reg_or_fld(range_base[11]); + range_regwen[12].add_lockable_reg_or_fld(range_base[12]); + range_regwen[13].add_lockable_reg_or_fld(range_base[13]); + range_regwen[14].add_lockable_reg_or_fld(range_base[14]); + range_regwen[15].add_lockable_reg_or_fld(range_base[15]); + range_regwen[16].add_lockable_reg_or_fld(range_base[16]); + range_regwen[17].add_lockable_reg_or_fld(range_base[17]); + range_regwen[18].add_lockable_reg_or_fld(range_base[18]); + range_regwen[19].add_lockable_reg_or_fld(range_base[19]); + range_regwen[20].add_lockable_reg_or_fld(range_base[20]); + range_regwen[21].add_lockable_reg_or_fld(range_base[21]); + range_regwen[22].add_lockable_reg_or_fld(range_base[22]); + range_regwen[23].add_lockable_reg_or_fld(range_base[23]); + range_regwen[24].add_lockable_reg_or_fld(range_base[24]); + range_regwen[25].add_lockable_reg_or_fld(range_base[25]); + range_regwen[26].add_lockable_reg_or_fld(range_base[26]); + range_regwen[27].add_lockable_reg_or_fld(range_base[27]); + range_regwen[28].add_lockable_reg_or_fld(range_base[28]); + range_regwen[29].add_lockable_reg_or_fld(range_base[29]); + range_regwen[30].add_lockable_reg_or_fld(range_base[30]); + range_regwen[31].add_lockable_reg_or_fld(range_base[31]); + range_regwen[0].add_lockable_reg_or_fld(range_limit[0]); + range_regwen[1].add_lockable_reg_or_fld(range_limit[1]); + range_regwen[2].add_lockable_reg_or_fld(range_limit[2]); + range_regwen[3].add_lockable_reg_or_fld(range_limit[3]); + range_regwen[4].add_lockable_reg_or_fld(range_limit[4]); + range_regwen[5].add_lockable_reg_or_fld(range_limit[5]); + range_regwen[6].add_lockable_reg_or_fld(range_limit[6]); + range_regwen[7].add_lockable_reg_or_fld(range_limit[7]); + range_regwen[8].add_lockable_reg_or_fld(range_limit[8]); + range_regwen[9].add_lockable_reg_or_fld(range_limit[9]); + range_regwen[10].add_lockable_reg_or_fld(range_limit[10]); + range_regwen[11].add_lockable_reg_or_fld(range_limit[11]); + range_regwen[12].add_lockable_reg_or_fld(range_limit[12]); + range_regwen[13].add_lockable_reg_or_fld(range_limit[13]); + range_regwen[14].add_lockable_reg_or_fld(range_limit[14]); + range_regwen[15].add_lockable_reg_or_fld(range_limit[15]); + range_regwen[16].add_lockable_reg_or_fld(range_limit[16]); + range_regwen[17].add_lockable_reg_or_fld(range_limit[17]); + range_regwen[18].add_lockable_reg_or_fld(range_limit[18]); + range_regwen[19].add_lockable_reg_or_fld(range_limit[19]); + range_regwen[20].add_lockable_reg_or_fld(range_limit[20]); + range_regwen[21].add_lockable_reg_or_fld(range_limit[21]); + range_regwen[22].add_lockable_reg_or_fld(range_limit[22]); + range_regwen[23].add_lockable_reg_or_fld(range_limit[23]); + range_regwen[24].add_lockable_reg_or_fld(range_limit[24]); + range_regwen[25].add_lockable_reg_or_fld(range_limit[25]); + range_regwen[26].add_lockable_reg_or_fld(range_limit[26]); + range_regwen[27].add_lockable_reg_or_fld(range_limit[27]); + range_regwen[28].add_lockable_reg_or_fld(range_limit[28]); + range_regwen[29].add_lockable_reg_or_fld(range_limit[29]); + range_regwen[30].add_lockable_reg_or_fld(range_limit[30]); + range_regwen[31].add_lockable_reg_or_fld(range_limit[31]); + range_regwen[0].add_lockable_reg_or_fld(range_perm[0]); + range_regwen[1].add_lockable_reg_or_fld(range_perm[1]); + range_regwen[2].add_lockable_reg_or_fld(range_perm[2]); + range_regwen[3].add_lockable_reg_or_fld(range_perm[3]); + range_regwen[4].add_lockable_reg_or_fld(range_perm[4]); + range_regwen[5].add_lockable_reg_or_fld(range_perm[5]); + range_regwen[6].add_lockable_reg_or_fld(range_perm[6]); + range_regwen[7].add_lockable_reg_or_fld(range_perm[7]); + range_regwen[8].add_lockable_reg_or_fld(range_perm[8]); + range_regwen[9].add_lockable_reg_or_fld(range_perm[9]); + range_regwen[10].add_lockable_reg_or_fld(range_perm[10]); + range_regwen[11].add_lockable_reg_or_fld(range_perm[11]); + range_regwen[12].add_lockable_reg_or_fld(range_perm[12]); + range_regwen[13].add_lockable_reg_or_fld(range_perm[13]); + range_regwen[14].add_lockable_reg_or_fld(range_perm[14]); + range_regwen[15].add_lockable_reg_or_fld(range_perm[15]); + range_regwen[16].add_lockable_reg_or_fld(range_perm[16]); + range_regwen[17].add_lockable_reg_or_fld(range_perm[17]); + range_regwen[18].add_lockable_reg_or_fld(range_perm[18]); + range_regwen[19].add_lockable_reg_or_fld(range_perm[19]); + range_regwen[20].add_lockable_reg_or_fld(range_perm[20]); + range_regwen[21].add_lockable_reg_or_fld(range_perm[21]); + range_regwen[22].add_lockable_reg_or_fld(range_perm[22]); + range_regwen[23].add_lockable_reg_or_fld(range_perm[23]); + range_regwen[24].add_lockable_reg_or_fld(range_perm[24]); + range_regwen[25].add_lockable_reg_or_fld(range_perm[25]); + range_regwen[26].add_lockable_reg_or_fld(range_perm[26]); + range_regwen[27].add_lockable_reg_or_fld(range_perm[27]); + range_regwen[28].add_lockable_reg_or_fld(range_perm[28]); + range_regwen[29].add_lockable_reg_or_fld(range_perm[29]); + range_regwen[30].add_lockable_reg_or_fld(range_perm[30]); + range_regwen[31].add_lockable_reg_or_fld(range_perm[31]); + range_regwen[0].add_lockable_reg_or_fld(range_racl_policy_shadowed[0]); + range_regwen[1].add_lockable_reg_or_fld(range_racl_policy_shadowed[1]); + range_regwen[2].add_lockable_reg_or_fld(range_racl_policy_shadowed[2]); + range_regwen[3].add_lockable_reg_or_fld(range_racl_policy_shadowed[3]); + range_regwen[4].add_lockable_reg_or_fld(range_racl_policy_shadowed[4]); + range_regwen[5].add_lockable_reg_or_fld(range_racl_policy_shadowed[5]); + range_regwen[6].add_lockable_reg_or_fld(range_racl_policy_shadowed[6]); + range_regwen[7].add_lockable_reg_or_fld(range_racl_policy_shadowed[7]); + range_regwen[8].add_lockable_reg_or_fld(range_racl_policy_shadowed[8]); + range_regwen[9].add_lockable_reg_or_fld(range_racl_policy_shadowed[9]); + range_regwen[10].add_lockable_reg_or_fld(range_racl_policy_shadowed[10]); + range_regwen[11].add_lockable_reg_or_fld(range_racl_policy_shadowed[11]); + range_regwen[12].add_lockable_reg_or_fld(range_racl_policy_shadowed[12]); + range_regwen[13].add_lockable_reg_or_fld(range_racl_policy_shadowed[13]); + range_regwen[14].add_lockable_reg_or_fld(range_racl_policy_shadowed[14]); + range_regwen[15].add_lockable_reg_or_fld(range_racl_policy_shadowed[15]); + range_regwen[16].add_lockable_reg_or_fld(range_racl_policy_shadowed[16]); + range_regwen[17].add_lockable_reg_or_fld(range_racl_policy_shadowed[17]); + range_regwen[18].add_lockable_reg_or_fld(range_racl_policy_shadowed[18]); + range_regwen[19].add_lockable_reg_or_fld(range_racl_policy_shadowed[19]); + range_regwen[20].add_lockable_reg_or_fld(range_racl_policy_shadowed[20]); + range_regwen[21].add_lockable_reg_or_fld(range_racl_policy_shadowed[21]); + range_regwen[22].add_lockable_reg_or_fld(range_racl_policy_shadowed[22]); + range_regwen[23].add_lockable_reg_or_fld(range_racl_policy_shadowed[23]); + range_regwen[24].add_lockable_reg_or_fld(range_racl_policy_shadowed[24]); + range_regwen[25].add_lockable_reg_or_fld(range_racl_policy_shadowed[25]); + range_regwen[26].add_lockable_reg_or_fld(range_racl_policy_shadowed[26]); + range_regwen[27].add_lockable_reg_or_fld(range_racl_policy_shadowed[27]); + range_regwen[28].add_lockable_reg_or_fld(range_racl_policy_shadowed[28]); + range_regwen[29].add_lockable_reg_or_fld(range_racl_policy_shadowed[29]); + range_regwen[30].add_lockable_reg_or_fld(range_racl_policy_shadowed[30]); + range_regwen[31].add_lockable_reg_or_fld(range_racl_policy_shadowed[31]); + + + // Create functional coverage for comportable IP-specific specialized registers. + // This function can only be called if it is a root block to get the correct gating condition + // and avoid creating duplicated cov. + if (this.get_parent() == null && en_dv_reg_cov) create_cov(); + endfunction : build + endclass : ac_range_check_reg_block + +endpackage diff --git a/hw/top_darjeeling/ip_autogen/ac_range_check/dv/env/ac_range_check_scoreboard.sv b/hw/top_darjeeling/ip_autogen/ac_range_check/dv/env/ac_range_check_scoreboard.sv new file mode 100644 index 0000000000000..b2bd178e1a487 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/ac_range_check/dv/env/ac_range_check_scoreboard.sv @@ -0,0 +1,171 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class ac_range_check_scoreboard extends cip_base_scoreboard #( + .CFG_T(ac_range_check_env_cfg), + .RAL_T(ac_range_check_reg_block), + .COV_T(ac_range_check_env_cov) + ); + `uvm_component_utils(ac_range_check_scoreboard) + + // Local variables + + // TLM agent fifos + uvm_tlm_analysis_fifo #(tl_seq_item) tl_csr_fifo; + uvm_tlm_analysis_fifo #(tl_seq_item) tl_unfilt_fifo; + uvm_tlm_analysis_fifo #(tl_seq_item) tl_filt_fifo; + + // Local queues to hold incoming packets pending comparison + tl_seq_item tl_csr_q[$]; + tl_seq_item tl_unfilt_q[$]; + tl_seq_item tl_filt_q[$]; + + // Standard SV/UVM methods + extern function new(string name="", uvm_component parent=null); + extern function void build_phase(uvm_phase phase); + extern function void connect_phase(uvm_phase phase); + extern task run_phase(uvm_phase phase); + extern function void check_phase(uvm_phase phase); + + // Class specific methods + extern task process_tl_csr_fifo(); + extern task process_tl_unfilt_fifo(); + extern task process_tl_filt_fifo(); + extern task process_tl_access(tl_seq_item item, tl_channels_e channel, string ral_name); + extern function void reset(string kind = "HARD"); +endclass : ac_range_check_scoreboard + + +function ac_range_check_scoreboard::new(string name="", uvm_component parent=null); + super.new(name, parent); +endfunction : new + +function void ac_range_check_scoreboard::build_phase(uvm_phase phase); + super.build_phase(phase); + tl_csr_fifo = new("tl_csr_fifo", this); + tl_unfilt_fifo = new("tl_unfilt_fifo", this); + tl_filt_fifo = new("tl_filt_fifo", this); + // TODO: remove once support alert checking + do_alert_check = 0; +endfunction : build_phase + +function void ac_range_check_scoreboard::connect_phase(uvm_phase phase); + super.connect_phase(phase); +endfunction : connect_phase + +task ac_range_check_scoreboard::run_phase(uvm_phase phase); + super.run_phase(phase); + wait(cfg.under_reset); + forever begin + wait(!cfg.under_reset); + // This isolation fork is needed to ensure that "disable fork" call won't kill any other + // processes at the same level from the parent classes + fork begin : isolation_fork + fork + begin : main_thread + fork + process_tl_csr_fifo(); + process_tl_unfilt_fifo(); + process_tl_filt_fifo(); + join + wait fork; // To ensure it will be killed only when the reset will occur + end + begin : reset_thread + wait(cfg.under_reset); + end + join_any + disable fork; // Terminates all descendants and sub-descendants of isolation_fork + end join + end +endtask : run_phase + +task ac_range_check_scoreboard::process_tl_csr_fifo(); + tl_seq_item item; + forever begin + tl_csr_fifo.get(item); + `uvm_info(`gfn, $sformatf("received tl_csr item:\n%0s", item.sprint()), UVM_HIGH) + end +endtask : process_tl_csr_fifo + +task ac_range_check_scoreboard::process_tl_unfilt_fifo(); + tl_seq_item item; + forever begin + tl_unfilt_fifo.get(item); + `uvm_info(`gfn, $sformatf("received tl_unfilt item:\n%0s", item.sprint()), UVM_HIGH) + end +endtask : process_tl_unfilt_fifo + +task ac_range_check_scoreboard::process_tl_filt_fifo(); + tl_seq_item item; + forever begin + tl_filt_fifo.get(item); + `uvm_info(`gfn, $sformatf("received tl_filt item:\n%0s", item.sprint()), UVM_HIGH) + end +endtask : process_tl_filt_fifo + +task ac_range_check_scoreboard::process_tl_access(tl_seq_item item, + tl_channels_e channel, + string ral_name); + uvm_reg csr; + bit do_read_check = 1'b1; + bit write = item.is_write(); + uvm_reg_addr_t csr_addr = cfg.ral_models[ral_name].get_word_aligned_addr(item.a_addr); + + bit addr_phase_read = (!write && channel == AddrChannel); + bit addr_phase_write = ( write && channel == AddrChannel); + bit data_phase_read = (!write && channel == DataChannel); + bit data_phase_write = ( write && channel == DataChannel); + + // If access was to a valid csr, get the csr handle + if (csr_addr inside {cfg.ral_models[ral_name].csr_addrs}) begin + csr = cfg.ral_models[ral_name].default_map.get_reg_by_offset(csr_addr); + `DV_CHECK_NE_FATAL(csr, null) + end else begin + `uvm_fatal(`gfn, $sformatf("Access unexpected addr 0x%0h", csr_addr)) + end + + // If incoming access is a write to a valid csr, then make updates right away + if (addr_phase_write) begin + void'(csr.predict(.value(item.a_data), .kind(UVM_PREDICT_WRITE), .be(item.a_mask))); + end + + // Process the csr req: + // - for write, update local variable and fifo at address phase + // - for read, update predication at address phase and compare at data phase + case (csr.get_name()) + // Add individual case item for each csr + "intr_state": begin + // FIXME TODO MVy + do_read_check = 1'b0; + end + "intr_enable": begin + // FIXME TODO MVy + end + "intr_test": begin + // FIXME TODO MVy + end + default: begin + `uvm_fatal(`gfn, $sformatf("invalid csr: %0s", csr.get_full_name())) + end + endcase + + // On reads, if do_read_check, is set, then check mirrored_value against item.d_data + if (data_phase_read) begin + if (do_read_check) begin + `DV_CHECK_EQ(csr.get_mirrored_value(), item.d_data, + $sformatf("reg name: %0s", csr.get_full_name())) + end + void'(csr.predict(.value(item.d_data), .kind(UVM_PREDICT_READ))); + end +endtask : process_tl_access + +function void ac_range_check_scoreboard::reset(string kind = "HARD"); + super.reset(kind); + // Reset local fifos queues and variables +endfunction : reset + +function void ac_range_check_scoreboard::check_phase(uvm_phase phase); + super.check_phase(phase); + // Post test checks - ensure that all local fifos and queues are empty +endfunction : check_phase diff --git a/hw/top_darjeeling/ip_autogen/ac_range_check/dv/env/ac_range_check_virtual_sequencer.sv b/hw/top_darjeeling/ip_autogen/ac_range_check/dv/env/ac_range_check_virtual_sequencer.sv new file mode 100644 index 0000000000000..2f022b0c6debe --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/ac_range_check/dv/env/ac_range_check_virtual_sequencer.sv @@ -0,0 +1,21 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class ac_range_check_virtual_sequencer extends cip_base_virtual_sequencer #( + .CFG_T(ac_range_check_env_cfg), + .COV_T(ac_range_check_env_cov) + ); + `uvm_component_utils(ac_range_check_virtual_sequencer) + + tl_sequencer tl_csr_sqr; + tl_sequencer tl_unfilt_sqr; + tl_sequencer tl_filt_sqr; + + // Standard SV/UVM methods + extern function new(string name="", uvm_component parent=null); +endclass : ac_range_check_virtual_sequencer + +function ac_range_check_virtual_sequencer::new(string name="", uvm_component parent=null); + super.new(name, parent); +endfunction : new diff --git a/hw/top_darjeeling/ip_autogen/ac_range_check/dv/env/seq_lib/ac_range_check_base_vseq.sv b/hw/top_darjeeling/ip_autogen/ac_range_check/dv/env/seq_lib/ac_range_check_base_vseq.sv new file mode 100644 index 0000000000000..2a3dbb5072c73 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/ac_range_check/dv/env/seq_lib/ac_range_check_base_vseq.sv @@ -0,0 +1,38 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class ac_range_check_base_vseq extends cip_base_vseq #( + .RAL_T (ac_range_check_reg_block), + .CFG_T (ac_range_check_env_cfg), + .COV_T (ac_range_check_env_cov), + .VIRTUAL_SEQUENCER_T (ac_range_check_virtual_sequencer) + ); + `uvm_object_utils(ac_range_check_base_vseq) + + // Various knobs to enable certain routines + bit do_ac_range_check_init = 1'b1; + + // Standard SV/UVM methods + extern function new(string name=""); + + // Class specific methods + extern task dut_init(string reset_kind = "HARD"); + extern task ac_range_check_init(); +endclass : ac_range_check_base_vseq + + +function ac_range_check_base_vseq::new(string name=""); + super.new(name); +endfunction : new + +task ac_range_check_base_vseq::dut_init(string reset_kind = "HARD"); + super.dut_init(); + if (do_ac_range_check_init) begin + ac_range_check_init(); + end +endtask : dut_init + +task ac_range_check_base_vseq::ac_range_check_init(); + `uvm_error(`gfn, "FIXME") +endtask : ac_range_check_init diff --git a/hw/top_darjeeling/ip_autogen/ac_range_check/dv/env/seq_lib/ac_range_check_common_vseq.sv b/hw/top_darjeeling/ip_autogen/ac_range_check/dv/env/seq_lib/ac_range_check_common_vseq.sv new file mode 100644 index 0000000000000..2a6c089863e2d --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/ac_range_check/dv/env/seq_lib/ac_range_check_common_vseq.sv @@ -0,0 +1,27 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class ac_range_check_common_vseq extends ac_range_check_base_vseq; + `uvm_object_utils(ac_range_check_common_vseq) + + // Constraints + extern constraint num_trans_c; + + // Standard SV/UVM methods + extern function new(string name=""); + extern task body(); +endclass : ac_range_check_common_vseq + + +constraint ac_range_check_common_vseq::num_trans_c { + num_trans inside {[1:2]}; +} + +function ac_range_check_common_vseq::new(string name=""); + super.new(name); +endfunction : new + +task ac_range_check_common_vseq::body(); + run_common_vseq_wrapper(num_trans); +endtask : body diff --git a/hw/top_darjeeling/ip_autogen/ac_range_check/dv/env/seq_lib/ac_range_check_smoke_vseq.sv b/hw/top_darjeeling/ip_autogen/ac_range_check/dv/env/seq_lib/ac_range_check_smoke_vseq.sv new file mode 100644 index 0000000000000..c6c70a470ab6b --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/ac_range_check/dv/env/seq_lib/ac_range_check_smoke_vseq.sv @@ -0,0 +1,20 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class ac_range_check_smoke_vseq extends ac_range_check_base_vseq; + `uvm_object_utils(ac_range_check_smoke_vseq) + + // Standard SV/UVM methods + extern function new(string name=""); + extern task body(); +endclass : ac_range_check_smoke_vseq + + +function ac_range_check_smoke_vseq::new(string name=""); + super.new(name); +endfunction : new + +task ac_range_check_smoke_vseq::body(); + `uvm_error(`gfn, "FIXME") +endtask : body diff --git a/hw/top_darjeeling/ip_autogen/ac_range_check/dv/env/seq_lib/ac_range_check_vseq_list.sv b/hw/top_darjeeling/ip_autogen/ac_range_check/dv/env/seq_lib/ac_range_check_vseq_list.sv new file mode 100644 index 0000000000000..5e7b497a396c3 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/ac_range_check/dv/env/seq_lib/ac_range_check_vseq_list.sv @@ -0,0 +1,7 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +`include "ac_range_check_base_vseq.sv" +`include "ac_range_check_smoke_vseq.sv" +`include "ac_range_check_common_vseq.sv" diff --git a/hw/top_darjeeling/ip_autogen/ac_range_check/dv/sva/ac_range_check_bind.sv b/hw/top_darjeeling/ip_autogen/ac_range_check/dv/sva/ac_range_check_bind.sv new file mode 100644 index 0000000000000..87cc1a4fb823c --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/ac_range_check/dv/sva/ac_range_check_bind.sv @@ -0,0 +1,23 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +module ac_range_check_bind; + + bind ac_range_check tlul_assert #( + .EndpointType("Device") + ) tlul_assert_device ( + .clk_i, + .rst_ni, + .h2d (tl_i), + .d2h (tl_o) + ); + + bind ac_range_check ac_range_check_csr_assert_fpv ac_range_check_csr_assert ( + .clk_i, + .rst_ni, + .h2d (tl_i), + .d2h (tl_o) + ); + +endmodule diff --git a/hw/top_darjeeling/ip_autogen/ac_range_check/dv/sva/ac_range_check_sva.core b/hw/top_darjeeling/ip_autogen/ac_range_check/dv/sva/ac_range_check_sva.core new file mode 100644 index 0000000000000..a2a24d67fe8a3 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/ac_range_check/dv/sva/ac_range_check_sva.core @@ -0,0 +1,38 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:opentitan:top_darjeeling_ac_range_check_sva:0.1 +description: "AC_RANGE_CHECK assertion modules and bind file." +filesets: + files_dv: + depend: + - lowrisc:tlul:headers + - lowrisc:fpv:csr_assert_gen + files: + - ac_range_check_bind.sv + file_type: systemVerilogSource + + files_formal: + depend: + - lowrisc:opentitan:top_darjeeling_ac_range_check + +generate: + csr_assert_gen: + generator: csr_assert_gen + parameters: + spec: ../../data/ac_range_check.hjson + +targets: + default: &default_target + filesets: + - files_dv + generate: + - csr_assert_gen + + formal: + <<: *default_target + filesets: + - files_formal + - files_dv + toplevel: ac_range_check diff --git a/hw/top_darjeeling/ip_autogen/ac_range_check/dv/tb/tb.sv b/hw/top_darjeeling/ip_autogen/ac_range_check/dv/tb/tb.sv new file mode 100644 index 0000000000000..cb702657a54f3 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/ac_range_check/dv/tb/tb.sv @@ -0,0 +1,92 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +module tb; + // Dep packages + import uvm_pkg::*; + import dv_utils_pkg::*; + import ac_range_check_env_pkg::*; + import ac_range_check_test_pkg::*; + + // Macro includes + `include "uvm_macros.svh" + `include "dv_macros.svh" + + wire clk; + wire rst_n; + wire [NUM_MAX_INTERRUPTS-1:0] interrupts; + wire rst_shadowed_n; + wire top_racl_pkg::racl_policy_vec_t racl_policies; + wire racl_error; + wire top_racl_pkg::racl_error_log_t racl_error_log; + wire intr_deny_cnt_reached; + wire prim_mubi_pkg::mubi8_t range_check_overwrite; + + // Interfaces + pins_if #(NUM_MAX_INTERRUPTS) intr_if (interrupts); + clk_rst_if clk_rst_if (.clk(clk), .rst_n(rst_n)); + rst_shadowed_if rst_shad_if (.rst_n(rst_n), .rst_shadowed_n(rst_shadowed_n)); + tl_if tl_csr_if (.clk(clk), .rst_n(rst_n)); + tl_if tl_unfilt_if (.clk(clk), .rst_n(rst_n)); + tl_if tl_filt_if (.clk(clk), .rst_n(rst_n)); + + `DV_ALERT_IF_CONNECT() + + // DUT + ac_range_check dut ( + // TODO MVy: should we keep the default values? Plan to verify with the others? As the TB will be impacted and should adopt a particular technique + // .AlertAsyncOn = , + // .EnableRacl = , + // .RaclErrorRsp = , + // .RaclPolicySelVec[NumRegs] = + // ) ( + .clk_i (clk ), + .rst_ni (rst_n ), + .rst_shadowed_ni (rst_shadowed_n ), + // Alerts + .alert_rx_i (alert_rx ), + .alert_tx_o (alert_tx ), + // RACL interface + .racl_policies_i (racl_policies ), + .racl_error_o (racl_error ), + .racl_error_log_o (racl_error_log ), + // Access range check interrupts + .intr_deny_cnt_reached_o (intr_deny_cnt_reached ), + // Bus interface + .tl_i (tl_csr_if.h2d ), + .tl_o (tl_csr_if.d2h ), + // Inter module signals + .range_check_overwrite_i (range_check_overwrite ), + // Incoming TLUL interface + .ctn_tl_h2d_i (tl_unfilt_if.h2d ), + .ctn_tl_d2h_o (tl_unfilt_if.d2h ), + // Filtered outgoing TLUL interface to the target if request is not squashed + .ctn_filtered_tl_h2d_o (tl_filt_if.h2d ), + .ctn_filtered_tl_d2h_i (tl_filt_if.d2h ) + ); + + // Manage inputs + // TODO should be driven dynamically by an io_agent (to be created TODO MVy) + assign range_check_overwrite = prim_mubi_pkg::MuBi8False; + assign racl_policies = top_racl_pkg::RACL_POLICY_VEC_DEFAULT; + + // Manage outputs + assign interrupts[DenyCntReached] = intr_deny_cnt_reached; + // TODO should be monitored dynamically by an io_agent (to be created TODO MVy) + // assign io_if.racl_error = racl_error; + // assign io_if.racl_error_log = racl_error_log; + + initial begin + clk_rst_if.set_active(); + uvm_config_db#(virtual clk_rst_if)::set(null, "*.env", "clk_rst_vif", clk_rst_if); + uvm_config_db#(virtual rst_shadowed_if)::set(null, "*.env", "rst_shadowed_vif", rst_shad_if); + uvm_config_db#(intr_vif)::set(null, "*.env", "intr_vif", intr_if); + uvm_config_db#(virtual tl_if)::set(null, "*.env.tl_csr_agt*", "tl_csr_vif", tl_csr_if); + uvm_config_db#(virtual tl_if)::set(null, "*.env.tl_unfilt_agt*", "tl_unfilt_vif", tl_unfilt_if); + uvm_config_db#(virtual tl_if)::set(null, "*.env.tl_filt_agt*", "tl_filt_vif", tl_filt_if); + $timeformat(-12, 0, " ps", 12); + run_test(); + end + +endmodule diff --git a/hw/top_darjeeling/ip_autogen/ac_range_check/dv/tests/ac_range_check_base_test.sv b/hw/top_darjeeling/ip_autogen/ac_range_check/dv/tests/ac_range_check_base_test.sv new file mode 100644 index 0000000000000..e732a5b5661d0 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/ac_range_check/dv/tests/ac_range_check_base_test.sv @@ -0,0 +1,26 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class ac_range_check_base_test extends cip_base_test #( + .CFG_T(ac_range_check_env_cfg), + .ENV_T(ac_range_check_env) + ); + + `uvm_component_utils(ac_range_check_base_test) + + // The base class dv_base_test creates the following instances: + // - ac_range_check_env_cfg: cfg + // - ac_range_check_env: env + + // The base class also looks up UVM_TEST_SEQ plusarg to create and run that seq in the run_phase. + // As such, nothing more needs to be done + + // Standard SV/UVM methods + extern function new(string name="", uvm_component parent=null); +endclass : ac_range_check_base_test + + +function ac_range_check_base_test::new(string name="", uvm_component parent=null); + super.new(name, parent); +endfunction : new diff --git a/hw/top_darjeeling/ip_autogen/ac_range_check/dv/tests/ac_range_check_test.core b/hw/top_darjeeling/ip_autogen/ac_range_check/dv/tests/ac_range_check_test.core new file mode 100644 index 0000000000000..4919631b32638 --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/ac_range_check/dv/tests/ac_range_check_test.core @@ -0,0 +1,19 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:opentitan:top_darjeeling_ac_range_check_test:0.1 +description: "AC_RANGE_CHECK DV UVM test" +filesets: + files_dv: + depend: + - lowrisc:opentitan:top_darjeeling_ac_range_check_env + files: + - ac_range_check_test_pkg.sv + - ac_range_check_base_test.sv: {is_include_file: true} + file_type: systemVerilogSource + +targets: + default: + filesets: + - files_dv diff --git a/hw/top_darjeeling/ip_autogen/ac_range_check/dv/tests/ac_range_check_test_pkg.sv b/hw/top_darjeeling/ip_autogen/ac_range_check/dv/tests/ac_range_check_test_pkg.sv new file mode 100644 index 0000000000000..a409d852dcd5d --- /dev/null +++ b/hw/top_darjeeling/ip_autogen/ac_range_check/dv/tests/ac_range_check_test_pkg.sv @@ -0,0 +1,22 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +package ac_range_check_test_pkg; + // Dep packages + import uvm_pkg::*; + import cip_base_pkg::*; + import ac_range_check_env_pkg::*; + + // Macro includes + `include "uvm_macros.svh" + `include "dv_macros.svh" + + // Local types + + // Functions + + // Package sources + `include "ac_range_check_base_test.sv" + +endpackage diff --git a/hw/top_darjeeling/lint/top_darjeeling_dv_lint_cfgs.hjson b/hw/top_darjeeling/lint/top_darjeeling_dv_lint_cfgs.hjson index dae7527b0c4c7..46be20f40e2d6 100644 --- a/hw/top_darjeeling/lint/top_darjeeling_dv_lint_cfgs.hjson +++ b/hw/top_darjeeling/lint/top_darjeeling_dv_lint_cfgs.hjson @@ -28,6 +28,11 @@ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] rel_path: "hw/ip/mbx/lint/{tool}" }, + { name: ac_range_check + fusesoc_core: lowrisc:dv:ac_range_check_sim + import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] + rel_path: "hw/top_darjeeling/ip_autogen/ac_range_check/dv/lint/{tool}" // TODO MVy ask to Andreas as all are doing this but lint directory doesn't exist in here (see HMAC for eg) + }, { name: aes fusesoc_core: lowrisc:dv:aes_sim import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]