further ISA variant support, initial variable regclass work, based on rL314102

Author: asb

0001-Revert-upstreamed-RISC-V-changes.patch

@@ -205,10 +205,10 @@ index 0f777addb7b..d6123499a22 100644
  #include "llvm/BinaryFormat/ELFRelocs/Lanai.def"
      break;
 diff --git a/tools/llvm-objdump/llvm-objdump.cpp b/tools/llvm-objdump/llvm-objdump.cpp
-index 3cc95c1f760..266b556360b 100644
+index 7006c6393b6..09396466c40 100644
 --- a/tools/llvm-objdump/llvm-objdump.cpp
 +++ b/tools/llvm-objdump/llvm-objdump.cpp
-@@ -768,6 +768,7 @@ static std::error_code getRelocationValueString(const ELFObjectFile<ELFT> *Obj,
+@@ -750,6 +750,7 @@ static std::error_code getRelocationValueString(const ELFObjectFile<ELFT> *Obj,
    case ELF::EM_HEXAGON:
    case ELF::EM_MIPS:
    case ELF::EM_BPF:

0003-RISCV-Add-RISC-V-ELF-defines.patch

@@ -20,7 +20,7 @@ Differential Revision: https://reviews.llvm.org/D37065
  1 file changed, 14 insertions(+), 2 deletions(-)
 
 diff --git a/include/llvm/Target/Target.td b/include/llvm/Target/Target.td
-index 38d6ca0cc76..9cc2368cf0f 100644
+index 1cf90403842..533c5f48b53 100644
 --- a/include/llvm/Target/Target.td
 +++ b/include/llvm/Target/Target.td
 @@ -859,12 +859,16 @@ class InstrInfo {

0012-NFC-Ensure-TargetOpcode-instructions-are-compatible-.patch

@@ -24,10 +24,10 @@ Differential Revision: https://reviews.llvm.org/D37898
  2 files changed, 3 insertions(+), 2 deletions(-)
 
 diff --git a/include/llvm/Target/TargetLowering.h b/include/llvm/Target/TargetLowering.h
-index 30f60fa0b0a..7bce5e9127b 100644
+index ea3e3f7b049..d35acdfc92e 100644
 --- a/include/llvm/Target/TargetLowering.h
 +++ b/include/llvm/Target/TargetLowering.h
-@@ -2906,7 +2906,7 @@ public:
+@@ -2907,7 +2907,7 @@ public:
        RetTy = ResultType;
        Callee = Target;
        CallConv = CC;
@@ -36,7 +36,7 @@ index 30f60fa0b0a..7bce5e9127b 100644
        Args = std::move(ArgsList);
 
        DAG.getTargetLoweringInfo().markLibCallAttributes(
-@@ -2919,7 +2919,7 @@ public:
+@@ -2920,7 +2920,7 @@ public:
        RetTy = ResultType;
        Callee = Target;
        CallConv = CC;
@@ -46,10 +46,10 @@ index 30f60fa0b0a..7bce5e9127b 100644
        return *this;
      }
 diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
-index fb32487ac42..116208fa7dc 100644
+index b103792d00c..642ca52e0d1 100644
 --- a/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
 +++ b/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
-@@ -8046,6 +8046,7 @@ TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
+@@ -8056,6 +8056,7 @@ TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
      Entry.IsSwiftError = false;
      Entry.Alignment = Align;
      CLI.getArgs().insert(CLI.getArgs().begin(), Entry);

0024-TargetLowering-Correctly-track-NumFixedArgs-field-of.patch

@@ -4,15 +4,42 @@ Subject: [RISCV] Codegen support for the standard RV32M instruction set
  extension
 
 ---
+ lib/Target/RISCV/RISCVISelDAGToDAG.cpp |   8 ++-
  lib/Target/RISCV/RISCVISelLowering.cpp |  18 +++---
  lib/Target/RISCV/RISCVInstrInfoM.td    |  13 ++++
  lib/Target/RISCV/RISCVSubtarget.cpp    |  13 +++-
- lib/Target/RISCV/RISCVSubtarget.h      |  12 ++--
+ lib/Target/RISCV/RISCVSubtarget.h      |  13 ++--
  test/CodeGen/RISCV/div.ll              | 115 ++++++++++++++++++++-------------
  test/CodeGen/RISCV/mul.ll              | 106 ++++++++++++++++++++++--------
  test/CodeGen/RISCV/rem.ll              |  27 +++++---
- 7 files changed, 206 insertions(+), 98 deletions(-)
+ 8 files changed, 214 insertions(+), 99 deletions(-)
 
+diff --git a/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+index 69dbce95212..076a0d0cbbe 100644
+--- a/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
++++ b/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+@@ -26,14 +26,20 @@ using namespace llvm;
+ // SelectionDAG operations.
+ namespace {
+ class RISCVDAGToDAGISel final : public SelectionDAGISel {
++  const RISCVSubtarget *Subtarget;
+ public:
+   explicit RISCVDAGToDAGISel(RISCVTargetMachine &TargetMachine)
+-      : SelectionDAGISel(TargetMachine) {}
++      : SelectionDAGISel(TargetMachine), Subtarget(nullptr) {}
+ 
+   StringRef getPassName() const override {
+     return "RISCV DAG->DAG Pattern Instruction Selection";
+   }
+ 
++  bool runOnMachineFunction(MachineFunction &MF) override {
++    Subtarget = &MF.getSubtarget<RISCVSubtarget>();
++    return SelectionDAGISel::runOnMachineFunction(MF);
++  }
++
+   void Select(SDNode *Node) override;
+ 
+   bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
 diff --git a/lib/Target/RISCV/RISCVISelLowering.cpp b/lib/Target/RISCV/RISCVISelLowering.cpp
 index 03d12c22799..83c4ebf78b0 100644
 --- a/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -92,21 +119,26 @@ index 2dfec6158fd..d8340e792be 100644
 +      FrameLowering(initializeSubtargetDependencies(CPU, FS)),
 +      TLInfo(TM, *this) {}
 diff --git a/lib/Target/RISCV/RISCVSubtarget.h b/lib/Target/RISCV/RISCVSubtarget.h
-index daeaa34f877..5a4e31a8f69 100644
+index daeaa34f877..e5bb0546c8c 100644
 --- a/lib/Target/RISCV/RISCVSubtarget.h
 +++ b/lib/Target/RISCV/RISCVSubtarget.h
-@@ -34,10 +34,14 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
+@@ -30,14 +30,19 @@ class StringRef;
+ 
+ class RISCVSubtarget : public RISCVGenSubtargetInfo {
+   virtual void anchor();
++  bool HasStdExtM = false;
++  bool HasStdExtA = false;
++  bool HasStdExtF = false;
++  bool HasRV64 = false;
+   RISCVInstrInfo InstrInfo;
++  RISCVRegisterInfo RegInfo;
    RISCVFrameLowering FrameLowering;
    RISCVTargetLowering TLInfo;
    SelectionDAGTargetInfo TSInfo;
 -  bool HasStdExtM;
 -  bool HasStdExtA;
 -  bool HasStdExtF;
 -  bool HasRV64;
-+  bool HasStdExtM = false;
-+  bool HasStdExtA = false;
-+  bool HasStdExtF = false;
-+  bool HasRV64 = false;
 +
 +  /// Initializes using the passed in CPU and feature strings so that we can
 +  /// use initializer lists for subtarget initialization.

0041-RISCV-Codegen-support-for-the-standard-RV32M-instruc.patch

@@ -164,17 +164,17 @@ index 85ae1255d30..c325b58999f 100644
 
  def FADD_S    : FPALU_rr<0b0000000, 0b111, FPR32, FPR32, FPR32, "fadd.s">;
 diff --git a/lib/Target/RISCV/RISCVSubtarget.h b/lib/Target/RISCV/RISCVSubtarget.h
-index 5a4e31a8f69..cb366e7705e 100644
+index e5bb0546c8c..368cc592d0a 100644
 --- a/lib/Target/RISCV/RISCVSubtarget.h
 +++ b/lib/Target/RISCV/RISCVSubtarget.h
-@@ -37,6 +37,7 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
+@@ -33,6 +33,7 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
    bool HasStdExtM = false;
    bool HasStdExtA = false;
    bool HasStdExtF = false;
 +  bool HasStdExtD = false;
    bool HasRV64 = false;
- 
-   /// Initializes using the passed in CPU and feature strings so that we can
+   RISCVInstrInfo InstrInfo;
+   RISCVRegisterInfo RegInfo;
 diff --git a/test/MC/RISCV/rv32d-invalid.s b/test/MC/RISCV/rv32d-invalid.s
 new file mode 100644
 index 00000000000..3c3e265bd28