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dpgeorgedpgeorge
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stm32: Add support for dual-analog-pad "_C" pins on H7 MCUs.
This commit adds support for the dual-analog-pads on STM32H7 parts. These pads/pins are called PA0_C/PA1_C/PC2_C/PC3_C in the datasheet. They each have an analog switch that can optionally connect them to their normal pin (eg PA0). When the switch is open, the normal and _C pin are independent pins/pads. The approach taken in this commit to make these _C pins available to Python is: - put them in their own, independent row in the stm32h7_af.csv definition file, with only the ADC column defined (they are separate machine.Pin entities, and doing it this way keeps make-pins.py pretty clean) - allow a board to reference these pins in the board's pins.csv file by the name PA0_C etc (so a board can alias them, for example) - these pins (when enabled in pins.csv) now become available like any other machine.Pin through both machine.Pin.board and machine.Pin.cpu - BUT these _C pins have a separate pin type which doesn't have any methods, because they don't have any functionality - these _C pins can be used with machine.ADC to construct the appropriate ADC object, either by passing the string as machine.ADC("PA0_C") or by passing the object as machine.ADC(machine.Pin.cpu.PA0_C) - if a board defines both the normal and _C pin (eg both PA0 and PA0_C) in pins.csv then it must not define the analog switch to be closed (this is a sanity check for the build, because it doesn't make sense to close the switch and have two separate pins) Signed-off-by: Damien George <[email protected]>
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8 files changed

+101
-19
lines changed

8 files changed

+101
-19
lines changed

‎ports/stm32/boards/make-pins.py

Lines changed: 10 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -59,6 +59,12 @@ class Stm32Pin(boardgen.Pin):
5959
def __init__(self, cpu_pin_name):
6060
super().__init__(cpu_pin_name)
6161

62+
# Pins ending in "_C" correspond to the analog-only pad of a pair
63+
# of dual (analog) pads found on H7 MCUs (eg PA0 and PA0_C pair).
64+
self._analog_only = cpu_pin_name.endswith("_C")
65+
if self._analog_only:
66+
cpu_pin_name = cpu_pin_name[:-2]
67+
6268
# P<port><num> (already verified by validate_cpu_pin_name).
6369
self._port = cpu_pin_name[1]
6470
self._pin = int(cpu_pin_name[2:])
@@ -129,11 +135,6 @@ def add_adc(self, adc):
129135
# be the P for one channel, and the N for a different channel.
130136
# e.g. "ADC123_INP12/ADC123_INN11".
131137
for adc_name in adc.split("/"):
132-
if adc_name.startswith("C_"):
133-
# Currently unsupported, H7 dual-pad. The C_ADC entries should
134-
# only be available directly from machine.ADC (not via the pin
135-
# object).
136-
continue
137138
m = re.match("ADC([1-5]+)_(IN[NP]?)([0-9]+)$", adc_name)
138139
if not m:
139140
raise boardgen.PinGeneratorError(
@@ -167,8 +168,9 @@ def definition(self):
167168
)
168169

169170
# PIN(p_port, p_pin, p_af, p_adc_num, p_adc_channel)
170-
return "PIN({:s}, {:d}, pin_{:s}_af, {:s}, {:d})".format(
171-
self._port, self._pin, self.name(), adc_units_bitfield, self._adc_channel
171+
pin_macro = "PIN_ANALOG" if self._analog_only else "PIN"
172+
return "{:s}({:s}, {:d}, pin_{:s}_af, {:s}, {:d})".format(
173+
pin_macro, self._port, self._pin, self.name(), adc_units_bitfield, self._adc_channel
172174
)
173175

174176
# This will be called at the start of the output (after the prefix). Use
@@ -210,7 +212,7 @@ def print_source(self, out_source):
210212
def validate_cpu_pin_name(cpu_pin_name):
211213
boardgen.Pin.validate_cpu_pin_name(cpu_pin_name)
212214

213-
if not re.match("P[A-K][0-9]+$", cpu_pin_name):
215+
if not re.match("P[A-K][0-9]+(_C)?$", cpu_pin_name):
214216
raise boardgen.PinGeneratorError("Invalid cpu pin name '{}'".format(cpu_pin_name))
215217

216218

‎ports/stm32/boards/stm32f4xx_prefix.c

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -30,3 +30,21 @@
3030
.adc_num = p_adc_num, \
3131
.adc_channel = p_adc_channel, \
3232
}
33+
34+
#if MICROPY_HW_ENABLE_ANALOG_ONLY_PINS
35+
#define PIN_ANALOG(p_port, p_pin, p_af, p_adc_num, p_adc_channel) \
36+
{ \
37+
{ &pin_analog_type }, \
38+
.name = MP_QSTR_##p_port##p_pin##_C, \
39+
.port = PORT_##p_port, \
40+
.pin = (p_pin), \
41+
.num_af = (sizeof(p_af) / sizeof(pin_af_obj_t)), \
42+
.pin_mask = (1 << ((p_pin) & 0x0f)), \
43+
.gpio = GPIO##p_port, \
44+
.af = p_af, \
45+
.adc_num = p_adc_num, \
46+
.adc_channel = p_adc_channel, \
47+
}
48+
#else
49+
#define PIN_ANALOG DUAL_PAD_SUPPORT_NOT_ENABLED__CONFIGURE__MICROPY_HW_ANALOG_SWITCH_Pxy
50+
#endif

‎ports/stm32/boards/stm32h723_af.csv

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -34,8 +34,10 @@ PortB,PB14, ,TIM1_CH2N ,TIM12_CH1
3434
PortB,PB15,RTC_REFIN ,TIM1_CH3N ,TIM12_CH2 ,TIM8_CH3N ,USART1_RX ,SPI2_MOSI/I2S2_SDO ,DFSDM1_CKIN2 , ,UART4_CTS ,SDMMC2_D1 , , ,FMC_D11/FMC_AD11 , ,LCD_G7 ,EVENTOUT,
3535
PortC,PC0 , ,FMC_D12/FMC_AD12 , ,DFSDM1_CKIN0 , , ,DFSDM1_DATIN4 , ,SAI4_FS_B ,FMC_A25 ,OTG_HS_ULPI_STP ,LCD_G2 ,FMC_SDNWE , ,LCD_R5 ,EVENTOUT,ADC123_INP10
3636
PortC,PC1 ,TRACED0 ,SAI4_D1 ,SAI1_D1 ,DFSDM1_DATIN0 ,DFSDM1_CKIN4 ,SPI2_MOSI/I2S2_SDO ,SAI1_SD_A , ,SAI4_SD_A ,SDMMC2_CK ,OCTOSPIM_P1_IO4 ,ETH_MDC ,MDIOS_MDC , ,LCD_G5 ,EVENTOUT,ADC123_INP11/ADC123_INN10
37-
PortC,PC2 ,PWR_DEEPSLEEP, , ,DFSDM1_CKIN1 ,OCTOSPIM_P1_IO5 ,SPI2_MISO/I2S2_SDI ,DFSDM1_CKOUT , , ,OCTOSPIM_P1_IO2 ,OTG_HS_ULPI_DIR ,ETH_MII_TXD2 ,FMC_SDNE0 , , ,EVENTOUT,ADC123_INP12/ADC123_INN11/C_ADC3_INN1/C_ADC3_INP0
38-
PortC,PC3 ,PWR_SLEEP , , ,DFSDM1_DATIN1 ,OCTOSPIM_P1_IO6 ,SPI2_MOSI/I2S2_SDO , , , ,OCTOSPIM_P1_IO0 ,OTG_HS_ULPI_NXT ,ETH_MII_TX_CLK ,FMC_SDCKE0 , , ,EVENTOUT,ADC12_INP13/ADC12_INN12/C_ADC3_INP1
37+
PortC,PC2 ,PWR_DEEPSLEEP, , ,DFSDM1_CKIN1 ,OCTOSPIM_P1_IO5 ,SPI2_MISO/I2S2_SDI ,DFSDM1_CKOUT , , ,OCTOSPIM_P1_IO2 ,OTG_HS_ULPI_DIR ,ETH_MII_TXD2 ,FMC_SDNE0 , , ,EVENTOUT,ADC123_INP12/ADC123_INN11
38+
PortC,PC2_C, , , , , , , , , , , , , , , , ,ADC3_INN1/ADC3_INP0
39+
PortC,PC3 ,PWR_SLEEP , , ,DFSDM1_DATIN1 ,OCTOSPIM_P1_IO6 ,SPI2_MOSI/I2S2_SDO , , , ,OCTOSPIM_P1_IO0 ,OTG_HS_ULPI_NXT ,ETH_MII_TX_CLK ,FMC_SDCKE0 , , ,EVENTOUT,ADC12_INP13/ADC12_INN12
40+
PortC,PC3_C, , , , , , , , , , , , , , , , ,ADC3_INP1
3941
PortC,PC4 ,PWR_DEEPSLEEP,FMC_A22 , ,DFSDM1_CKIN2 , ,I2S1_MCK , , , ,SPDIFRX1_IN3 ,SDMMC2_CKIN ,ETH_MII_RXD0/ETH_RMII_RXD0 ,FMC_SDNE0 , ,LCD_R7 ,EVENTOUT,ADC12_INP4
4042
PortC,PC5 ,PWR_SLEEP ,SAI4_D3 ,SAI1_D3 ,DFSDM1_DATIN2 ,PSSI_D15 , , , , ,SPDIFRX1_IN4 ,OCTOSPIM_P1_DQS ,ETH_MII_RXD1/ETH_RMII_RXD1 ,FMC_SDCKE0 ,COMP1_OUT ,LCD_DE ,EVENTOUT,ADC12_INP8/ADC12_INN4
4143
PortC,PC6 , , ,TIM3_CH1 ,TIM8_CH1 ,DFSDM1_CKIN3 ,I2S2_MCK , ,USART6_TX ,SDMMC1_D0DIR ,FMC_NWAIT ,SDMMC2_D6 , ,SDMMC1_D6 ,DCMI_D0/PSSI_D0 ,LCD_HSYNC ,EVENTOUT,

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