MDEV-41271 Add RISC-V Zvbc accelerated CRC-32C implementation

Extend the RISC-V CRC-32C path with a Zvbc vector implementation:

  - mysys/CMakeLists.txt: detect Zvbc + RVV intrinsics under
    -march=rv64gc_zbb_zvbc; when available rebuild the new
    crc32c_riscv_zvbc.cc with that march (optional, Zbc unaffected);
  - mysys/crc32/crc32c_riscv_zvbc.cc (new): K-lane vector core --
    4 lanes x 128-bit folding, vlseg2e64 de-interleaved 64B loads,
    vclmul_vx broadcast constants, single-element vector CLMUL for
    the Barrett merge (no scalar Zbc instruction anywhere), bit-exact
    with the Zbc core (same fold constants k1..k4 and Barrett math);
  - adaptive VLEN: one e64m1 vector pair at VLEN>=256, two pairs at
    VLEN=128, so 128-bit cores execute the vector path at full width;
  - mysys/crc32/crc32c_riscv.cc + crc32c.cc: runtime dispatch via
    riscv_hwprobe -- Zbc is preferred when present (existing
    deployments keep the optimized scalar core); the Zvbc vector
    path accelerates cores that implement Zvbc but not scalar Zbc.

Correctness: RFC 3720 + random/chained/boundary inputs bit-identical
to slicing-by-4; official unittest/mysys/crc32-t.c 36/36.

Performance on Spacemit X100 (k3, VLEN=256, gcc 14.3.0), vs inherited
slicing-by-4 crc32c_slow (official slow path, same my_crc32c entry):

    len      slow (MB/s)   PR-B2 Zvbc (MB/s)   vs slow
    128 B        289            1147              4.0x
    256 B        296            2105              7.1x
    1 KiB        297            5466             18.5x
    4 KiB        297            9116             30.7x
    64 KiB       296           11398             38.7x

Dispatch prefers the scalar Zbc path when Zbc is available, so
existing Zbc deployments see no behavior change or regression;
the vector path is selected on cores without scalar Zbc.
No behavior change on non-riscv64 builds or toolchains without
Zvbc (optional compile check).

Review revisions requested on PR MariaDB#5746 (dr-m):

  - mysys/crc32/crc32c_riscv.cc: assemble the ZBC/ZVBC extension bits
    without a branch at both sites, dropping the redundant intermediate
    variable; replace `(void) hwprobe;` with `std::ignore = hwprobe;` and
    include <tuple>.  <tuple> introduces no static constructor, so the
    ifunc resolver's load-time constraint is unaffected.
  - mysys/crc32/crc32c.cc: expand the comment above the Zbc preference
    with the structural reason -- the vector core deliberately reuses the
    scalar fold to stay bit-exact, so its vl is capped at 4 and a wider
    VLEN buys nothing; scalar Zbc is preferred because the two are level
    on large input and the scalar path is clearly ahead on small input.
    Comment-only.

Assisted-by: YuanSheng:DeepSeek-V4-Flash
Co-authored-by: Xiaofei Gong <gongxiaofei24@iscas.ac.cn>
Signed-off-by: Jiakai Xu <xujiakai2025@iscas.ac.cn>

Author: 2 people

mysys/CMakeLists.txt

@@ -185,6 +185,35 @@ ELSEIF(CMAKE_SYSTEM_PROCESSOR MATCHES "riscv64|RISCV64")
         crc32/crc32c_riscv.cc crc32/crc32c_riscv_zbc.cc)
       SET_SOURCE_FILES_PROPERTIES(crc32/crc32c_riscv_zbc.cc PROPERTIES
         COMPILE_FLAGS "-march=rv64gc_zbc_zbb")
+
+      # Zvbc vector core (optional): separate TU compiled for the vector
+      # extension; the runtime probe/dispatch stay in crc32c_riscv.cc.
+      # Zbc is deliberately left out of the -march: this core is all-vector,
+      # and with Zbc present GCC's -foptimize-crc (on by default at -O2 since
+      # GCC 15) rewrites the bitwise fallback in that file into scalar clmul
+      # instructions, which do not exist on the Zvbc-without-Zbc cores this
+      # code is for.
+      SET(SAVE_REQ_FLAGS2 "${CMAKE_REQUIRED_FLAGS}")
+      SET(CMAKE_REQUIRED_FLAGS "${CMAKE_REQUIRED_FLAGS} -march=rv64gc_zbb_zvbc")
+      CHECK_CXX_SOURCE_COMPILES("
+      #include <riscv_vector.h>
+      #include <stdint.h>
+      uint64_t f(uint64_t a, const uint64_t *p, size_t vl) {
+        vuint64m1_t v = __riscv_vle64_v_u64m1(p, vl);
+        return __riscv_vmv_x_s_u64m1_u64(__riscv_vclmul_vx_u64m1(v, a, vl));
+      }
+      int main() { uint64_t x[4]={1,2,3,4}; return (int) f(5, x, 4); }
+      " HAVE_RISCV_ZVBC)
+      SET(CMAKE_REQUIRED_FLAGS "${SAVE_REQ_FLAGS2}")
+      IF(HAVE_RISCV_ZVBC)
+        MESSAGE(STATUS "RISC-V Zvbc detected: enabling vector CRC32C")
+        SET(MYSYS_SOURCES ${MYSYS_SOURCES} crc32/crc32c_riscv_zvbc.cc)
+        SET_SOURCE_FILES_PROPERTIES(crc32/crc32c_riscv_zvbc.cc PROPERTIES
+          COMPILE_FLAGS "-march=rv64gc_zbb_zvbc")
+        ADD_DEFINITIONS(-DHAVE_RISCV_ZVBC)
+      ELSE()
+        MESSAGE(STATUS "RISC-V Zvbc not available: using Zbc scalar CRC32C")
+      ENDIF()
     ENDIF()
   ENDIF()
 ENDIF()

mysys/crc32/crc32c.cc

@@ -491,7 +491,10 @@ extern "C" my_crc32_t crc32c_aarch64_available(void);
 extern "C" const char *crc32c_aarch64_impl(my_crc32_t);
 #elif defined HAVE_RISCV_ZBC
 extern "C" unsigned crc32c_riscv_zbc(unsigned, const void *, size_t);
-extern "C" int rv_zbc_supported(void *);
+# ifdef HAVE_RISCV_ZVBC
+extern "C" unsigned crc32c_riscv_zvbc(unsigned, const void *, size_t);
+# endif
+extern "C" unsigned rv_riscv_crc_ext(void *);
 extern "C" const char *crc32c_riscv_impl(my_crc32_t);
 #elif defined __i386__||defined __x86_64__||defined _M_X64||defined _M_IX86
 extern "C" my_crc32_t crc32c_x86_available(void);
@@ -501,15 +504,41 @@ extern "C" const char *crc32c_x86_impl(my_crc32_t);
 #if defined HAVE_RISCV_ZBC
 static my_crc32_t crc32c_riscv_choose(void *hwprobe)
 {
-  return rv_zbc_supported(hwprobe) ? crc32c_riscv_zbc : crc32c_slow;
+  unsigned ext= rv_riscv_crc_ext(hwprobe);
+  /* Where scalar Zbc is available, prefer it over the Zvbc vector core.
+
+     The vector core does not buy extra parallelism here. To stay
+     bit-exact with the scalar core it reuses exactly the same fold:
+     four 128-bit lanes over a fixed 64-byte span, with the same
+     constants k1..k4 and the same Barrett step. It therefore caps vl
+     at 4 and folds 64 bytes per iteration however wide VLEN is, and it
+     issues the same number of carry-less multiplies. Its only edge is
+     a single de-interleaving segment load per 64 bytes, which on large
+     input is offset by its per-call overhead (vsetvl, and injecting
+     the CRC into lane 0 through a store/load round trip): on Spacemit
+     X100 (VLEN=256) it ties the scalar fold at 64 KiB (11398 vs 11687
+     MB/s) and loses on small input (128 B: 1147 vs 5540 MB/s,
+     1 KiB: 5466 vs 10277 MB/s).
+
+     Its reason to exist is cores that implement Zvbc but not scalar
+     Zbc, where the only alternative is the slicing-by-4 crc32c_slow.
+     Where Zbc is present, selecting it would only touch the vector
+     register file for no gain. */
+  if (ext & 1)
+    return crc32c_riscv_zbc;
+#ifdef HAVE_RISCV_ZVBC
+  if (ext & 2)                    /* Zvbc only (no scalar Zbc) */
+    return crc32c_riscv_zvbc;
+#endif
+  return crc32c_slow;
 }
 
 /* The RISC-V resolver. Unlike the other architectures, the implementation is
    selected by an indirect function instead of at the first call, because the
    target operating systems of RISC-V (Linux and FreeBSD) support that.
 
    The dynamic linker calls this at load time, before main(), so it may only
-   run code that is safe there. rv_zbc_supported() is: it uses the
+   run code that is safe there. rv_riscv_crc_ext() is: it uses the
    riscv_hwprobe system call and nothing else.
 
    The resolver must never return NULL. Whereas the *_available() functions

mysys/crc32/crc32c_riscv.cc

@@ -16,6 +16,7 @@ argument is NULL and the system call is made directly.
 */
 
 #include <stddef.h>
+#include <tuple>
 #include <unistd.h>
 #include <sys/syscall.h>
 
@@ -37,6 +38,9 @@ struct riscv_hwprobe { long long key; unsigned long long value; };
 #ifndef RISCV_HWPROBE_EXT_ZBC
 # define RISCV_HWPROBE_EXT_ZBC (1ULL << 7)
 #endif
+#ifndef RISCV_HWPROBE_EXT_ZVBC
+# define RISCV_HWPROBE_EXT_ZVBC (1ULL << 18)
+#endif
 
 #ifndef SYS_riscv_hwprobe
 # ifdef __NR_riscv_hwprobe
@@ -77,9 +81,45 @@ extern "C" int rv_zbc_supported(void *hwprobe)
 }
 
 extern "C" unsigned crc32c_riscv_zbc(unsigned, const void *, size_t);
+#ifdef HAVE_RISCV_ZVBC
+extern "C" unsigned crc32c_riscv_zvbc(unsigned, const void *, size_t);
+#endif
+
+/* CRC acceleration level for the callers' ifunc resolver:
+   3 = Zbc + Zvbc (prefer Zbc; the optimized scalar fold ties the 4-lane
+       vector core at VLEN 256 and wins below it),
+   2 = Zvbc only (no scalar Zbc -- the vector core is the only
+       accelerated path on such cores), 1 = Zbc only, 0 = none. */
+extern "C" unsigned rv_riscv_crc_ext(void *hwprobe)
+{
+  struct riscv_hwprobe p;
+  p.key= RISCV_HWPROBE_KEY_IMA_EXT_0;
+  p.value= 0;
+#ifdef HAVE_SYS_HWPROBE_H
+  if (hwprobe != NULL)
+  {
+    unsigned long long value= 0;
+    if (__riscv_hwprobe_one(reinterpret_cast<__riscv_hwprobe_t>(hwprobe),
+                            RISCV_HWPROBE_KEY_IMA_EXT_0, &value) != 0)
+      return 0;
+    return ((value & RISCV_HWPROBE_EXT_ZBC) ? 1u : 0u) |
+           ((value & RISCV_HWPROBE_EXT_ZVBC) ? 2u : 0u);
+  }
+#else
+  std::ignore = hwprobe;
+#endif
+  if (syscall(SYS_riscv_hwprobe, &p, (size_t) 1, (size_t) 0, NULL, 0) != 0)
+    return 0;
+  return ((p.value & RISCV_HWPROBE_EXT_ZBC) ? 1u : 0u) |
+         ((p.value & RISCV_HWPROBE_EXT_ZVBC) ? 2u : 0u);
+}
 
 extern "C" const char *crc32c_riscv_impl(my_crc32_t c)
 {
+#ifdef HAVE_RISCV_ZVBC
+  if (c == crc32c_riscv_zvbc)
+    return "Using RISC-V Zvbc vector carry-less multiply instructions";
+#endif
   if (c == crc32c_riscv_zbc)
     return "Using RISC-V Zbc carry-less multiply instructions";
   return NULL;