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dig2dec.cmp
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-- Copyright (C) 2017 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Intel Program License
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
-- the Intel FPGA IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Intel and sold by Intel or its authorized distributors. Please
-- refer to the applicable agreement for further details.
-- Generated by Quartus Prime Version 17.1 (Build Build 590 10/25/2017)
-- Created on Fri Dec 22 11:31:45 2017
COMPONENT dig2dec
PORT
(
vol : IN UNSIGNED(15 DOWNTO 0);
seg4 : OUT UNSIGNED(3 DOWNTO 0);
seg3 : OUT UNSIGNED(3 DOWNTO 0);
seg2 : OUT UNSIGNED(3 DOWNTO 0);
seg1 : OUT UNSIGNED(3 DOWNTO 0);
seg0 : OUT UNSIGNED(3 DOWNTO 0)
);
END COMPONENT;