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Add integration tests for disassembler
Test both disassembling a file (assembled from source for the test), and disassembling a byte sequence provided on the command line. Source code to be assembled and expected disassembler listings are provided in the tests/fixtures directory.
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Diff for: ‎.github/workflows/run_tests.yaml

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@@ -91,3 +91,10 @@ jobs:
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export PATH=$PATH:${{ steps.fetch_binutils.outputs.bin_dir }}
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cd tests
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./02_compat_rtc_tests.sh
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- name: Run disassembler tests
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id: disassembler_tests
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run: |
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export PATH=$PATH:${{ steps.build_micropython.outputs.bin_dir }}
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cd tests
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./03_disassembler_tests.sh

Diff for: ‎tests/03_disassembler_tests.sh

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#!/bin/bash
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set -e
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test_disassembling_a_file() {
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local verbose
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if [ "$1" == verbose ]; then
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verbose=-v
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echo -e "Testing disassembling a file in VERBOSE mode"
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else
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echo -e "Testing disassembling a file in NORMAL mode"
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fi
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testname=all_opcodes
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fixture=fixtures/${testname}.S
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echo -e "\tBuilding $fixture using micropython-esp32-ulp"
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log_file="${testname}.log"
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ulp_file="fixtures/${testname}.ulp"
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micropython -m esp32_ulp $fixture 1>$log_file # generates $ulp_file
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lst_file="${testname}.lst"
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lst_file_fixture=fixtures/${testname}${verbose}.lst
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echo -e "\tDisassembling $ulp_file using micropython-esp32-ulp disassembler"
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micropython tools/disassemble.py $verbose $ulp_file > $lst_file
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if ! diff $lst_file_fixture $lst_file 1>/dev/null; then
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echo -e "\tDisassembled output differs from expected output!"
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echo ""
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echo "Disassembly test failed for $fixture"
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echo "micropython-esp32-ulp log:"
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cat $log_file
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echo "Diff of disassembly: expected vs actual"
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diff -u $lst_file_fixture $lst_file
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fi
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}
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test_disassembling_a_manual_sequence() {
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local verbose
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if [ "$1" == verbose ]; then
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verbose=-v
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echo -e "Testing disassembling a manual byte sequence in VERBOSE mode"
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else
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echo -e "Testing disassembling a manual byte sequence in NORMAL mode"
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fi
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sequence="e1af 8c72 0100 0068 2705 cc19 0005 681d 0000 00a0 0000 0074"
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lst_file="manual_bytes.lst"
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lst_file_fixture=fixtures/manual_bytes${verbose}.lst
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echo -e "\tDisassembling manual byte sequence using micropython-esp32-ulp disassembler"
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micropython tools/disassemble.py $verbose -m $sequence > $lst_file
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if ! diff $lst_file_fixture $lst_file 1>/dev/null; then
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echo -e "\tDisassembled output differs from expected output!"
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echo ""
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echo "Disassembly test failed for manual byte sequence"
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echo "Diff of disassembly: expected vs actual"
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diff -u $lst_file_fixture $lst_file
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fi
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}
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test_disassembling_a_file
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test_disassembling_a_file verbose
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test_disassembling_a_manual_sequence
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test_disassembling_a_manual_sequence verbose

Diff for: ‎tests/fixtures/all_opcodes-v.lst

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header
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ULP magic : b'ulp\x00' (0x00706c75)
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.text offset : 12 (0x0c)
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.text size : 164 (0xa4)
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.data offset : 176 (0xb0)
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.data size : 8 (0x08)
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.bss size : 0 (0x00)
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----------------------------------------
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.text
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0000 230d8810 REG_WR 0x123, 1, 2, 3
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addr = 35 (0x23)
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data = 3
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high = 1
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low = 2
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opcode = 1
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periph_sel = 1
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0004 21030421 REG_RD 0x321, 2, 1
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addr = 33 (0x21)
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high = 2
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low = 1
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opcode = 2
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periph_sel = 3
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unused = 0
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0008 03001130 I2C_RD 3, 2, 1, 0
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data = 0
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high = 2
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i2c_sel = 0
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low = 1
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opcode = 3
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rw = 0
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sub_addr = 3
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unused = 0
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000c 00011339 I2C_WR 0, 2, 3, 4
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data = 1
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high = 2
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i2c_sel = 4
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low = 3
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opcode = 3
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rw = 1
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sub_addr = 0
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unused = 0
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0010 00000040 NOP
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cycles = 0
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opcode = 4
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unused = 0
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0014 07000040 WAIT 7
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cycles = 7
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opcode = 4
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unused = 0
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0018 07000050 ADC r3, 1, 0
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cycles = 0
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dreg = 3
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mux = 1
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opcode = 5
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sar_sel = 0
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unused1 = 0
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unused2 = 0
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001c 0b000068 ST r3, r2, 0
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dreg = 2
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offset = 0
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opcode = 6
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sreg = 3
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sub_opcode = 4
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unused1 = 0
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unused2 = 0
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0020 06000070 ADD r2, r1, r0
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dreg = 2
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opcode = 7
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sel = 0 (ADD)
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sreg = 1
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sub_opcode = 0
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treg = 0
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unused = 0
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0024 06002070 SUB r2, r1, r0
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dreg = 2
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opcode = 7
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sel = 1 (SUB)
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sreg = 1
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sub_opcode = 0
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treg = 0
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unused = 0
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0028 06004070 AND r2, r1, r0
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dreg = 2
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opcode = 7
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sel = 2 (AND)
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sreg = 1
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sub_opcode = 0
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treg = 0
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unused = 0
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002c 06006070 OR r2, r1, r0
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dreg = 2
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opcode = 7
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sel = 3 (OR)
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sreg = 1
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sub_opcode = 0
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treg = 0
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unused = 0
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0030 16008070 MOVE r2, r1
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dreg = 2
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opcode = 7
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sel = 4 (MOVE)
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sreg = 1
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sub_opcode = 0
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treg = 1
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unused = 0
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0034 0600a070 LSH r2, r1, r0
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dreg = 2
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opcode = 7
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sel = 5 (LSH)
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sreg = 1
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sub_opcode = 0
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treg = 0
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unused = 0
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0038 0600c070 RSH r2, r1, r0
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dreg = 2
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opcode = 7
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sel = 6 (RSH)
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sreg = 1
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sub_opcode = 0
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treg = 0
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unused = 0
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003c 06000072 ADD r2, r1, 0
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dreg = 2
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imm = 0
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opcode = 7
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sel = 0 (ADD)
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sreg = 1
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sub_opcode = 1
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unused = 0
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0040 06002072 SUB r2, r1, 0
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dreg = 2
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imm = 0
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opcode = 7
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sel = 1 (SUB)
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sreg = 1
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sub_opcode = 1
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unused = 0
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0044 06004072 AND r2, r1, 0
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dreg = 2
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imm = 0
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opcode = 7
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sel = 2 (AND)
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sreg = 1
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sub_opcode = 1
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unused = 0
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0048 06006072 OR r2, r1, 0
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dreg = 2
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imm = 0
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opcode = 7
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sel = 3 (OR)
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sreg = 1
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sub_opcode = 1
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unused = 0
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004c 01008072 MOVE r1, 0
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dreg = 1
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imm = 0
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opcode = 7
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sel = 4 (MOVE)
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sreg = 0
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sub_opcode = 1
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unused = 0
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0050 0600a072 LSH r2, r1, 0
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dreg = 2
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imm = 0
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opcode = 7
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sel = 5 (LSH)
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sreg = 1
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sub_opcode = 1
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unused = 0
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0054 0600c072 RSH r2, r1, 0
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dreg = 2
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imm = 0
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opcode = 7
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sel = 6 (RSH)
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sreg = 1
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sub_opcode = 1
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unused = 0
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0058 00004074 STAGE_RST
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imm = 0
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opcode = 7
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sel = 2 (STAGE_RST)
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sub_opcode = 2
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unused1 = 0
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unused2 = 0
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005c 70000074 STAGE_INC 7
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imm = 7
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opcode = 7
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sel = 0 (STAGE_INC)
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sub_opcode = 2
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unused1 = 0
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unused2 = 0
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0060 30002074 STAGE_DEC 3
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imm = 3
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opcode = 7
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sel = 1 (STAGE_DEC)
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sub_opcode = 2
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unused1 = 0
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unused2 = 0
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0064 00002080 JUMP r0
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addr = 0
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dreg = 0
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opcode = 8
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reg = 1
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sub_opcode = 0
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type = 0 (--)
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unused = 0
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0068 01006080 JUMP r1, EQ
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addr = 0
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dreg = 1
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opcode = 8
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reg = 1
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sub_opcode = 0
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type = 1 (EQ)
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unused = 0
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006c 0200a080 JUMP r2, OV
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addr = 0
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dreg = 2
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opcode = 8
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reg = 1
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sub_opcode = 0
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type = 2 (OV)
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unused = 0
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0070 00000080 JUMP 0
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addr = 0
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dreg = 0
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opcode = 8
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reg = 0
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sub_opcode = 0
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type = 0 (--)
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unused = 0
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0074 00004080 JUMP 0, EQ
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addr = 0
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dreg = 0
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opcode = 8
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reg = 0
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sub_opcode = 0
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type = 1 (EQ)
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unused = 0
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0078 00008080 JUMP 0, OV
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addr = 0
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dreg = 0
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opcode = 8
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reg = 0
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sub_opcode = 0
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type = 2 (OV)
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unused = 0
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007c 01000082 JUMPR 0, 1, LT
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cmp = 0 (LT)
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imm = 1
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offset = 0
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opcode = 8
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sign = 0
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sub_opcode = 1
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0080 05000382 JUMPR 1, 5, GE
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cmp = 1 (GE)
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imm = 5
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offset = 1
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opcode = 8
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sign = 0
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sub_opcode = 1
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0084 01000084 JUMPS 0, 1, LT
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cmp = 0 (LT)
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imm = 1
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offset = 0
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opcode = 8
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sign = 0
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sub_opcode = 2
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unused = 0
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0088 05800284 JUMPS 1, 5, GE
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cmp = 1 (GE)
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imm = 5
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offset = 1
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opcode = 8
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sign = 0
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sub_opcode = 2
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unused = 0
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008c 09000584 JUMPS 2, 9, LE
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cmp = 2 (LE)
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imm = 9
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offset = 2
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opcode = 8
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sign = 0
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sub_opcode = 2
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unused = 0
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0090 01000090 WAKE
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opcode = 9
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sub_opcode = 0
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unused = 0
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wakeup = 1
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0094 07000092 SLEEP 7
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cycle_sel = 7
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opcode = 9
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sub_opcode = 1
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unused = 0
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0098 090000a0 TSENS r1, 2
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delay = 2
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dreg = 1
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opcode = 10 (0x0a)
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unused = 0
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009c 000000b0 HALT
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opcode = 11 (0x0b)
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unused = 0
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00a0 060000d0 LD r2, r1, 0
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dreg = 2
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offset = 0
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opcode = 13 (0x0d)
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sreg = 1
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unused1 = 0
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unused2 = 0
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----------------------------------------
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.data
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00a4 00000000 <empty>
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00a8 fecadec0 <non-empty>

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