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rsr_mul.S
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#include "common.i"
.global rsr_mul
.type rsr_mul, @function
.text
.macro ACCUM_RST_L
// MOVW R26, R24 // X = R
MOVW R28, R22 // Y = L
MOVW R30, R20 // Z = H
LDD R2, Y+0 // R2 <- L[0], R_1[0] = R2
LDD R3, Y+1
LDD R4, Y+2
LDD R5, Y+3
LDD R6, Y+4
LDD R7, Y+5
LDD R8, Y+6
LDD R9, Y+7
LDD R10, Y+8
LDD R11, Y+9
LDD R12, Y+10
LDD R13, Y+11 // R13 <- L[11], R_1[11] = R13
CLR R14 // CARRY 를 위한 레지스터 0으로 세팅
CLC // CARRY FLAG 0으로 세팅
LDD R0, Y+24
ADD R2, R0
LDD R0, Y+25
ADC R3, R0
LDD R0, Y+26
ADC R4, R0
LDD R0, Y+27
ADC R5, R0
LDD R0, Y+28
ADC R6, R0
LDD R0, Y+29
ADC R7, R0
LDD R0, Y+30
ADC R8, R0
LDD R0, Y+31
ADC R9, R0
LDD R0, Y+32
ADC R10, R0
LDD R0, Y+33
ADC R11, R0
LDD R0, Y+34
ADC R12, R0
LDD R0, Y+35
ADC R13, R0
ADC R14, R1 // L35까지 더하고 발생한 캐리 저장, R14 = R14 + R1 + CARRY, R1은 ZERO
LDD R0, Z+0 // R0 <- H[0]
ADD R2, R0 // R_1[0] <- L[0] + H[0]
LDD R0, Z+1
ADC R3, R0
LDD R0, Z+2
ADC R4, R0
LDD R0, Z+3
ADC R5, R0
LDD R0, Z+4
ADC R6, R0
LDD R0, Z+5
ADC R7, R0
LDD R0, Z+6
ADC R8, R0
LDD R0, Z+7
ADC R9, R0
LDD R0, Z+8
ADC R10, R0
LDD R0, Z+9
ADC R11, R0
LDD R0, Z+10
ADC R12, R0
LDD R0, Z+11
ADC R13, R0 // R_11[0] <- L[11] + H[11]
ADC R14, R1 // 11번째 인덱스에서 발생한 캐리 저장, R1은 ZERO
LDD R0, Z+24
ADD R2, R0
LDD R0, Z+25
ADC R3, R0
LDD R0, Z+26
ADC R4, R0
LDD R0, Z+27
ADC R5, R0
LDD R0, Z+28
ADC R6, R0
LDD R0, Z+29
ADC R7, R0
LDD R0, Z+30
ADC R8, R0
LDD R0, Z+31
ADC R9, R0
LDD R0, Z+32
ADC R10, R0
LDD R0, Z+33
ADC R11, R0
LDD R0, Z+34
ADC R12, R0
LDD R0, Z+35
ADC R13, R0
ADC R14, R1 // L35까지 더하고 발생한 캐리 저장, R1은 ZERO
MOVW R28, R24 // Y = R
STD Y+0, R2
STD Y+1, R3
STD Y+2, R4
STD Y+3, R5
STD Y+4, R6
STD Y+5, R7
STD Y+6, R8
STD Y+7, R9
STD Y+8, R10
STD Y+9, R11
STD Y+10, R12
STD Y+11, R13
STD Y+48, R14 // R[48]에 첫번째 CARRY 처리, R0~R11 CARRY
STD Y+24, R2
STD Y+25, R3
STD Y+26, R4
STD Y+27, R5
STD Y+28, R6
STD Y+29, R7
STD Y+30, R8
STD Y+31, R9
STD Y+32, R10
STD Y+33, R11
STD Y+34, R12
STD Y+35, R13
STD Y+52, R14 // R24~R35 CARRY
.endm
.macro ACCUM_RST_R
// MOVW R26, R24 // X = R
MOVW R28, R22 // Y = L
// MOVW R30, R20 // Z = H
LDD R2, Y+12
LDD R3, Y+13
LDD R4, Y+14
LDD R5, Y+15
LDD R6, Y+16
LDD R7, Y+17
LDD R8, Y+18
LDD R9, Y+19
LDD R10, Y+20
LDD R11, Y+21
LDD R12, Y+22
LDD R13, Y+23
CLR R14 // CARRY REGISTER 초기화
CLC // CARRY FLAG 0으로 세팅
LDD R0, Y+36
ADD R2, R0
LDD R0, Y+37
ADC R3, R0
LDD R0, Y+38
ADC R4, R0
LDD R0, Y+39
ADC R5, R0
LDD R0, Y+40
ADC R6, R0
LDD R0, Y+41
ADC R7, R0
LDD R0, Y+42
ADC R8, R0
LDD R0, Y+43
ADC R9, R0
LDD R0, Y+44
ADC R10, R0
LDD R0, Y+45
ADC R11, R0
LDD R0, Y+46
ADC R12, R0
LDD R0, Y+47
ADC R13, R0
ADC R14, R1
LDD R0, Z+12
ADD R2, R0
LDD R0, Z+13
ADC R3, R0
LDD R0, Z+14
ADC R4, R0
LDD R0, Z+15
ADC R5, R0
LDD R0, Z+16
ADC R6, R0
LDD R0, Z+17
ADC R7, R0
LDD R0, Z+18
ADC R8, R0
LDD R0, Z+19
ADC R9, R0
LDD R0, Z+20
ADC R10, R0
LDD R0, Z+21
ADC R11, R0
LDD R0, Z+22
ADC R12, R0
LDD R0, Z+23
ADC R13, R0
ADC R14, R1
LDD R0, Z+36
ADD R2, R0
LDD R0, Z+37
ADC R3, R0
LDD R0, Z+38
ADC R4, R0
LDD R0, Z+39
ADC R5, R0
LDD R0, Z+40
ADC R6, R0
LDD R0, Z+41
ADC R7, R0
LDD R0, Z+42
ADC R8, R0
LDD R0, Z+43
ADC R9, R0
LDD R0, Z+44
ADC R10, R0
LDD R0, Z+45
ADC R11, R0
LDD R0, Z+46
ADC R12, R0
LDD R0, Z+47
ADC R13, R0
ADC R14, R1
MOVW R28, R24 // Y = R
STD Y+12, R2
STD Y+13, R3
STD Y+14, R4
STD Y+15, R5
STD Y+16, R6
STD Y+17, R7
STD Y+18, R8
STD Y+19, R9
STD Y+20, R10
STD Y+21, R11
STD Y+22, R12
STD Y+23, R13
STD Y+50, R14 // R12~R23 CARRY
STD Y+36, R2
STD Y+37, R3
STD Y+38, R4
STD Y+39, R5
STD Y+40, R6
STD Y+41, R7
STD Y+42, R8
STD Y+43, R9
STD Y+44, R10
STD Y+45, R11
STD Y+46, R12
STD Y+47, R13
STD Y+54, R14 // R36~R47 CARRY
.endm
rsr_mul:
PUSH_REGS
ACCUM_RST_L
ACCUM_RST_R
POP_REGS
RET