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scripts: west_commands: create_board: initial support for nRF54H20
Add initial support for nRF54H20 based boards. Signed-off-by: Gerard Marull-Paretas <[email protected]>
1 parent b6211b8 commit 5bae20b

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‎scripts/west_commands/create_board/config.yml

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@@ -71,6 +71,30 @@ products:
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arch: arm
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ram: 188
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flash: 324
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- series: nrf54h
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socs:
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- name: nrf54h20
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variants:
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- name: ckaa
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cores:
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- name: cpuapp
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arch: arm
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ram: 256
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flash: 296
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- name: cpurad
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arch: arm
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ram: 192
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flash: 256
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- name: cpuppr
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arch: riscv
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ram: 62
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flash: 62
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xip: true
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- name: cpuflpr
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arch: riscv
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ram: 46
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flash: 46
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xip: true
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- series: nrf91
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socs:
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- name: nrf9131

‎scripts/west_commands/create_board/ncs_create_board.py

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@@ -185,6 +185,14 @@ def do_run(self, args, unknown_args):
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tmpl = TEMPLATE_DIR / series / "board-shared_sram.dtsi"
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shutil.copy(tmpl, out_dir / f"{ input['board'] }-shared_sram.dtsi")
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# nrf54H specific files
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if series == "nrf54h":
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tmpl = TEMPLATE_DIR / series / "board-ipc_conf.dtsi"
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shutil.copy(tmpl, out_dir / f"{ input['board'] }-ipc_conf.dtsi")
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tmpl = TEMPLATE_DIR / series / "board-memory_map.dtsi"
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shutil.copy(tmpl, out_dir / f"{ input['board'] }-memory_map.dtsi")
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# nrf91 specific files
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if series == "nrf91":
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tmpl = env.get_template("board-partitioning.dtsi.jinja2")
@@ -205,7 +213,11 @@ def do_run(self, args, unknown_args):
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with open(out_dir / f"{ name }_defconfig", "w") as f:
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f.write(tmpl.render(target=target))
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tmpl = env.get_template("board.dts.jinja2")
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if not target["xip"]:
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tmpl = env.get_template("board.dts.jinja2")
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else:
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tmpl = env.get_template("board-xip.dts.jinja2")
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with open(out_dir / f"{name}.dts", "w") as f:
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f.write(tmpl.render(target=target))
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‎scripts/west_commands/create_board/schema.json

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@@ -39,6 +39,7 @@
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"nRF52840-QFAA",
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"nRF52840-QIAA",
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"nRF5340-QKAA",
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"nRF54H20-CKAA",
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"nRF54L15-QFAA",
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"nRF9131-LACA",
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"nRF9151-LACA",

‎scripts/west_commands/create_board/templates/nrf54h/Kconfig.board.jinja2

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config BOARD_{{ board | upper }}
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select SOC_NRF54H20_CPUAPP if BOARD_{{ board | upper }}_NRF54H20_CPUAPP
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select SOC_NRF54H20_CPURAD if BOARD_{{ board | upper }}_NRF54H20_CPURAD
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select SOC_NRF54H20_CPUPPR if BOARD_{{ board | upper }}_NRF54H20_CPUPPR || \
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BOARD_{{ board | upper }}_NRF54H20_CPUPPR_XIP
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select SOC_NRF54H20_CPUFLPR if BOARD_{{ board | upper }}_NRF54H20_CPUFLPR || \
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BOARD_{{ board | upper }}_NRF54H20_CPUFLPR_XIP

‎scripts/west_commands/create_board/templates/nrf54h/Kconfig.defconfig.jinja2

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if BOARD_{{ board | upper }}_NRF54H20_CPUAPP
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config BT_HCI_IPC
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default y if BT
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endif # BOARD_{{ board | upper }}_NRF54H20_CPUAPP
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if BOARD_{{ board | upper }}_NRF54H20_CPURAD
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config BT_CTLR
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default y if BT
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endif # BOARD_{{ board | upper }}_NRF54H20_CPURAD

‎scripts/west_commands/create_board/templates/nrf54h/board-common.dtsi

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#include "{{ board }}-memory_map.dtsi"
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#include "{{ board }}-ipc_conf.dtsi"
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#include "{{ board }}-pinctrl.dtsi"
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&hfxo {
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status = "okay";
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accuracy-ppm = <30>;
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startup-time-us = <850>;
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mode = "crystal";
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};
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&lfxo {
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status = "okay";
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accuracy-ppm = <20>;
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startup-time-us = <600000>;
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mode = "crystal";
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};

‎scripts/west_commands/create_board/templates/nrf54h/board-ipc_conf.dtsi

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/ {
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ipc {
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cpusec_cpuapp_ipc: ipc-1-2 {
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compatible = "zephyr,ipc-icmsg";
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status = "disabled";
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dcache-alignment = <32>;
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mboxes = <&cpusec_bellboard 12>,
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<&cpuapp_bellboard 0>;
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};
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cpusec_cpurad_ipc: ipc-1-3 {
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compatible = "zephyr,ipc-icmsg";
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status = "disabled";
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dcache-alignment = <32>;
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mboxes = <&cpusec_bellboard 18>,
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<&cpurad_bellboard 0>;
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};
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cpuapp_cpurad_ipc: ipc-2-3 {
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compatible = "zephyr,ipc-icbmsg";
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dcache-alignment = <32>;
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status = "disabled";
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mboxes = <&cpuapp_bellboard 18>,
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<&cpurad_bellboard 12>;
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};
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cpuapp_cpusys_ipc: ipc-2-12 {
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compatible = "zephyr,ipc-icmsg";
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status = "disabled";
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dcache-alignment = <32>;
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mboxes = <&cpuapp_bellboard 6>,
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<&cpusys_vevif 12>;
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};
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cpuapp_cpuppr_ipc: ipc-2-13 {
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compatible = "zephyr,ipc-icmsg";
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status = "disabled";
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dcache-alignment = <32>;
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mboxes = <&cpuapp_bellboard 13>,
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<&cpuppr_vevif 12>;
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};
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cpuapp_cpuflpr_ipc: ipc-2-14 {
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compatible = "zephyr,ipc-icmsg";
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status = "disabled";
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dcache-alignment = <32>;
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mboxes = <&cpuapp_bellboard 14>,
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<&cpuflpr_vevif 16>;
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};
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cpurad_cpusys_ipc: ipc-3-12 {
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compatible = "zephyr,ipc-icmsg";
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status = "disabled";
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dcache-alignment = <32>;
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mboxes = <&cpurad_bellboard 6>,
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<&cpusys_vevif 18>;
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};
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};
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};

‎scripts/west_commands/create_board/templates/nrf54h/board-memory_map.dtsi

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#include <zephyr/dt-bindings/memory-attr/memory-attr.h>
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&suit_storage_partition {
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reg = <0xe1eb000 DT_SIZE_K(24)>;
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};
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/ {
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reserved-memory {
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cpuapp_ram0x_region: memory@2f010000 {
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compatible = "nordic,owned-memory";
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reg = <0x2f010000 DT_SIZE_K(260)>;
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status = "disabled";
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nordic,access = <NRF_OWNER_ID_APPLICATION NRF_PERM_RWS>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x2f010000 0x41000>;
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cpusec_cpuapp_ipc_shm: memory@0 {
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reg = <0x0 DT_SIZE_K(2)>;
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};
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cpuapp_cpusec_ipc_shm: memory@800 {
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reg = <0x800 DT_SIZE_K(2)>;
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};
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cpuapp_data: memory@1000 {
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reg = <0x1000 DT_SIZE_K(256)>;
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};
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};
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cpurad_ram0x_region: memory@2f051000 {
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compatible = "nordic,owned-memory";
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reg = <0x2f051000 DT_SIZE_K(4)>;
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status = "disabled";
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nordic,access = <NRF_OWNER_ID_RADIOCORE NRF_PERM_RWS>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x2f051000 0x1000>;
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cpusec_cpurad_ipc_shm: memory@0 {
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reg = <0x0 DT_SIZE_K(2)>;
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};
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cpurad_cpusec_ipc_shm: memory@800 {
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reg = <0x800 DT_SIZE_K(2)>;
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};
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};
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etr_buf_ram0x_region: memory@2f0be000 {
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compatible = "nordic,owned-memory";
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reg = <0x2f0be000 DT_SIZE_K(4)>;
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status = "disabled";
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nordic,access = <NRF_OWNER_ID_APPLICATION NRF_PERM_RWS>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x2f0be000 0x1000>;
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/* TODO In future move this region to cpuapp_ram0x_region. */
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etr_buffer: memory@0 {
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reg = <0x0 DT_SIZE_K(4)>;
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};
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};
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cpuapp_cpurad_ram0x_region: memory@2f0bf000 {
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compatible = "nordic,owned-memory";
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reg = <0x2f0bf000 DT_SIZE_K(4)>;
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status = "disabled";
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nordic,access = <NRF_OWNER_ID_APPLICATION NRF_PERM_RW>,
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<NRF_OWNER_ID_RADIOCORE NRF_PERM_RW>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x2f0bf000 0x1000>;
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cpuapp_cpurad_ipc_shm: memory@0 {
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reg = <0x0 DT_SIZE_K(2)>;
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};
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cpurad_cpuapp_ipc_shm: memory@800 {
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reg = <0x800 DT_SIZE_K(2)>;
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};
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};
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cpuapp_cpusys_ipc_shm: memory@2f88fce0 {
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reg = <0x2f88fce0 0x80>;
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};
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cpusys_cpuapp_ipc_shm: memory@2f88fd60 {
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reg = <0x2f88fd60 0x80>;
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};
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cpurad_cpusys_ipc_shm: memory@2f88fe00 {
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reg = <0x2f88fe00 0x80>;
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};
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cpusys_cpurad_ipc_shm: memory@2f88fe80 {
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reg = <0x2f88fe80 0x80>;
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};
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/*
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* NOTE: FLPR has a direct bridge with RAM21 that bypasses MPC.
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* This means that when this region is marked as non-executable,
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* only FLPR can execute code from it.
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*/
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ram21_region: memory@2f890000 {
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compatible = "nordic,owned-memory";
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status = "disabled";
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reg = <0x2f890000 DT_SIZE_K(64)>;
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nordic,access = <NRF_OWNER_ID_APPLICATION NRF_PERM_RWS>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x2f890000 0x10000>;
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cpuflpr_code_data: memory@0 {
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reg = <0x0 DT_SIZE_K(46)>;
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};
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cpuapp_cpuflpr_ipc_shm: memory@b800 {
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reg = <0xb800 DT_SIZE_K(1)>;
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};
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cpuflpr_cpuapp_ipc_shm: memory@bc00 {
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reg = <0xbc00 DT_SIZE_K(1)>;
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};
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dma_fast_region: memory@c000 {
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compatible = "zephyr,memory-region";
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reg = <0xc000 DT_SIZE_K(16)>;
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status = "disabled";
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#memory-region-cells = <0>;
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zephyr,memory-region = "DMA_RAM21";
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zephyr,memory-attr = <( DT_MEM_DMA | DT_MEM_CACHEABLE )>;
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};
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};
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cpuppr_ram3x_region: memory@2fc00000 {
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compatible = "nordic,owned-memory";
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reg = <0x2fc00000 DT_SIZE_K(64)>;
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status = "disabled";
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nordic,access = <NRF_OWNER_ID_APPLICATION NRF_PERM_RWX>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x2fc00000 0x10000>;
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cpuppr_code_data: memory@0 {
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reg = <0x0 DT_SIZE_K(62)>;
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};
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cpuapp_cpuppr_ipc_shm: memory@f800 {
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reg = <0xf800 DT_SIZE_K(1)>;
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};
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cpuppr_cpuapp_ipc_shm: memory@fc00 {
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reg = <0xfc00 DT_SIZE_K(1)>;
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};
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};
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cpuapp_dma_region: memory@2fc12000 {
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compatible = "nordic,owned-memory", "zephyr,memory-region";
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reg = <0x2fc12000 DT_SIZE_K(4)>;
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status = "disabled";
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#memory-region-cells = <0>;
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nordic,access = <NRF_OWNER_ID_APPLICATION NRF_PERM_RW>;
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zephyr,memory-region = "DMA_RAM3x_APP";
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zephyr,memory-attr = <( DT_MEM_DMA )>;
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};
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cpurad_dma_region: memory@2fc13000 {
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compatible = "nordic,owned-memory", "zephyr,memory-region";
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reg = <0x2fc13000 DT_SIZE_K(1)>;
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status = "disabled";
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#memory-region-cells = <0>;
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nordic,access = <NRF_OWNER_ID_RADIOCORE NRF_PERM_RW>;
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zephyr,memory-region = "DMA_RAM3x_RAD";
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zephyr,memory-attr = <( DT_MEM_DMA )>;
175+
};
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};
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};
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&mram1x {
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cpurad_rx_partitions: cpurad-rx-partitions {
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compatible = "nordic,owned-partitions", "fixed-partitions";
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status = "disabled";
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nordic,access = <NRF_OWNER_ID_RADIOCORE NRF_PERM_RXS>;
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#address-cells = <1>;
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#size-cells = <1>;
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cpurad_slot0_partition: partition@66000 {
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reg = <0x66000 DT_SIZE_K(256)>;
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};
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};
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cpuapp_rx_partitions: cpuapp-rx-partitions {
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compatible = "nordic,owned-partitions", "fixed-partitions";
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status = "disabled";
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nordic,access = <NRF_OWNER_ID_APPLICATION NRF_PERM_RXS>;
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#address-cells = <1>;
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#size-cells = <1>;
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cpuapp_slot0_partition: partition@a6000 {
200+
reg = <0xa6000 DT_SIZE_K(248)>;
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};
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cpuppr_code_partition: partition@e4000 {
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reg = <0xe4000 DT_SIZE_K(64)>;
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};
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cpuflpr_code_partition: partition@f4000 {
208+
reg = <0xf4000 DT_SIZE_K(48)>;
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};
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};
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cpuapp_rw_partitions: cpuapp-rw-partitions {
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compatible = "nordic,owned-partitions", "fixed-partitions";
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status = "disabled";
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nordic,access = <NRF_OWNER_ID_APPLICATION NRF_PERM_RWS>;
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#address-cells = <1>;
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#size-cells = <1>;
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dfu_partition: partition@100000 {
220+
reg = < 0x100000 DT_SIZE_K(908) >;
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};
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storage_partition: partition@1e3000 {
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reg = < 0x1e3000 DT_SIZE_K(24) >;
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};
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};
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};

‎scripts/west_commands/create_board/templates/nrf54h/board-pinctrl.dtsi

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&pinctrl {
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};

‎scripts/west_commands/create_board/templates/nrf54h/board-xip.dts.jinja2

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#include "{{ board }}_nrf54h20_{{ target["core"] }}.dts"

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