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172 | 172 | #define NRF_FUN_GRTC_CLKOUT_FAST 55U
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173 | 173 | /** GRTC slow clock output */
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174 | 174 | #define NRF_FUN_GRTC_CLKOUT_32K 56U
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175 |
| -/** SDP_MSPI CK */ |
| 175 | +/** SDP_MSPI clock pin */ |
176 | 176 | #define NRF_FUN_SDP_MSPI_SCK 57U
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177 |
| -/** SDP_MSPI DQ0 */ |
| 177 | +/** SDP_MSPI data pin 0 */ |
178 | 178 | #define NRF_FUN_SDP_MSPI_DQ0 58U
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179 |
| -/** SDP_MSPI DQ1 */ |
| 179 | +/** SDP_MSPI data pin 1 */ |
180 | 180 | #define NRF_FUN_SDP_MSPI_DQ1 59U
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181 |
| -/** SDP_MSPI DQ2 */ |
| 181 | +/** SDP_MSPI data pin 2 */ |
182 | 182 | #define NRF_FUN_SDP_MSPI_DQ2 60U
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183 |
| -/** SDP_MSPI DQ3 */ |
| 183 | +/** SDP_MSPI data pin 3 */ |
184 | 184 | #define NRF_FUN_SDP_MSPI_DQ3 61U
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185 |
| -/** SDP_MSPI DQ4 */ |
| 185 | +/** SDP_MSPI data pin 4 */ |
186 | 186 | #define NRF_FUN_SDP_MSPI_DQ4 62U
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187 |
| -/** SDP_MSPI DQ5 */ |
| 187 | +/** SDP_MSPI data pin 5 */ |
188 | 188 | #define NRF_FUN_SDP_MSPI_DQ5 63U
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189 |
| -/** SDP_MSPI DQ6 */ |
| 189 | +/** SDP_MSPI data pin 6 */ |
190 | 190 | #define NRF_FUN_SDP_MSPI_DQ6 64U
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191 |
| -/** SDP_MSPI DQ7 */ |
| 191 | +/** SDP_MSPI data pin 7 */ |
192 | 192 | #define NRF_FUN_SDP_MSPI_DQ7 65U
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193 |
| -/** SDP_MSPI CS0 */ |
| 193 | +/** SDP_MSPI chip select 0 */ |
194 | 194 | #define NRF_FUN_SDP_MSPI_CS0 66U
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195 |
| -/** SDP_MSPI CS1 */ |
| 195 | +/** SDP_MSPI chip select 1 */ |
196 | 196 | #define NRF_FUN_SDP_MSPI_CS1 67U
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197 |
| -/** SDP_MSPI CS2 */ |
| 197 | +/** SDP_MSPI chip select 2 */ |
198 | 198 | #define NRF_FUN_SDP_MSPI_CS2 68U
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199 |
| -/** SDP_MSPI CS3 */ |
| 199 | +/** SDP_MSPI chip select 3 */ |
200 | 200 | #define NRF_FUN_SDP_MSPI_CS3 69U
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201 |
| -/** SDP_MSPI CS4 */ |
| 201 | +/** SDP_MSPI chip select 4 */ |
202 | 202 | #define NRF_FUN_SDP_MSPI_CS4 70U
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| 203 | +/** High-Performance Framework MSPI clock pin */ |
| 204 | +#define NRF_FUN_HPF_MSPI_SCK NRF_FUN_SDP_MSPI_SCK |
| 205 | +/** High-Performance Framework MSPI data pin 0 */ |
| 206 | +#define NRF_FUN_HPF_MSPI_DQ0 NRF_FUN_SDP_MSPI_DQ0 |
| 207 | +/** High-Performance Framework MSPI data pin 1 */ |
| 208 | +#define NRF_FUN_HPF_MSPI_DQ1 NRF_FUN_SDP_MSPI_DQ1 |
| 209 | +/** High-Performance Framework MSPI data pin 2 */ |
| 210 | +#define NRF_FUN_HPF_MSPI_DQ2 NRF_FUN_SDP_MSPI_DQ2 |
| 211 | +/** High-Performance Framework MSPI data pin 3 */ |
| 212 | +#define NRF_FUN_HPF_MSPI_DQ3 NRF_FUN_SDP_MSPI_DQ3 |
| 213 | +/** High-Performance Framework MSPI data pin 4 */ |
| 214 | +#define NRF_FUN_HPF_MSPI_DQ4 NRF_FUN_SDP_MSPI_DQ4 |
| 215 | +/** High-Performance Framework MSPI data pin 5 */ |
| 216 | +#define NRF_FUN_HPF_MSPI_DQ5 NRF_FUN_SDP_MSPI_DQ5 |
| 217 | +/** High-Performance Framework MSPI data pin 6 */ |
| 218 | +#define NRF_FUN_HPF_MSPI_DQ6 NRF_FUN_SDP_MSPI_DQ6 |
| 219 | +/** High-Performance Framework MSPI data pin 7 */ |
| 220 | +#define NRF_FUN_HPF_MSPI_DQ7 NRF_FUN_SDP_MSPI_DQ7 |
| 221 | +/** High-Performance Framework MSPI chip select pin 0 */ |
| 222 | +#define NRF_FUN_HPF_MSPI_CS0 NRF_FUN_SDP_MSPI_CS0 |
| 223 | +/** High-Performance Framework MSPI chip select pin 1 */ |
| 224 | +#define NRF_FUN_HPF_MSPI_CS1 NRF_FUN_SDP_MSPI_CS1 |
| 225 | +/** High-Performance Framework MSPI chip select pin 2 */ |
| 226 | +#define NRF_FUN_HPF_MSPI_CS2 NRF_FUN_SDP_MSPI_CS2 |
| 227 | +/** High-Performance Framework MSPI chip select pin 3 */ |
| 228 | +#define NRF_FUN_HPF_MSPI_CS3 NRF_FUN_SDP_MSPI_CS3 |
| 229 | +/** High-Performance Framework MSPI chip select pin 4 */ |
| 230 | +#define NRF_FUN_HPF_MSPI_CS4 NRF_FUN_SDP_MSPI_CS4 |
203 | 231 | /** TDM SCK in master mode */
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204 | 232 | #define NRF_FUN_TDM_SCK_M 71U
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205 | 233 | /** TDM SCK in slave mode */
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