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[nrf noup] drivers: pinctrl: rename SDP to HPF
nrf-squash! [nrf noup] drivers: pinctrl: Add SDP MSPI pin configuration Change name SDP to a new one: HPF. Signed-off-by: Magdalena Pastula <[email protected]>
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-50
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2 files changed

+78
-50
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‎drivers/pinctrl/pinctrl_nrf.c

+22-22
Original file line numberDiff line numberDiff line change
@@ -112,17 +112,17 @@ static const nrf_gpio_pin_drive_t drive_modes[NRF_DRIVE_COUNT] = {
112112
#define NRF_PSEL_TDM(reg, line) ((NRF_TDM_Type *)reg)->PSEL.line
113113
#endif
114114

115-
#if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrfe_mspi_controller) || \
116-
defined(CONFIG_MSPI_NRFE) || \
115+
#if DT_HAS_COMPAT_STATUS_OKAY(nordic_hpf_mspi_controller) || \
116+
defined(CONFIG_MSPI_HPF) || \
117117
DT_ANY_COMPAT_HAS_PROP_STATUS_OKAY(nordic_nrf_vpr_coprocessor, pinctrl_0)
118118
#if defined(CONFIG_SOC_SERIES_NRF54LX)
119-
#define NRF_PSEL_SDP_MSPI(psel) \
119+
#define NRF_PSEL_HPF_MSPI(psel) \
120120
nrf_gpio_pin_control_select(psel, NRF_GPIO_PIN_SEL_VPR);
121121
#elif defined(CONFIG_SOC_SERIES_NRF54HX)
122122
/* On nRF54H, pin routing is controlled by secure domain, via UICR. */
123-
#define NRF_PSEL_SDP_MSPI(psel)
123+
#define NRF_PSEL_HPF_MSPI(psel)
124124
#endif
125-
#endif /* DT_HAS_COMPAT_STATUS_OKAY(nordic_nrfe_mspi_controller) || ... */
125+
#endif /* DT_HAS_COMPAT_STATUS_OKAY(nordic_hpf_mspi_controller) || ... */
126126

127127
int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
128128
uintptr_t reg)
@@ -477,26 +477,26 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
477477
input = NRF_GPIO_PIN_INPUT_CONNECT;
478478
break;
479479
#endif /* defined(NRF_PSEL_TWIS) */
480-
#if defined(NRF_PSEL_SDP_MSPI)
481-
case NRF_FUN_SDP_MSPI_CS0:
482-
case NRF_FUN_SDP_MSPI_CS1:
483-
case NRF_FUN_SDP_MSPI_CS2:
484-
case NRF_FUN_SDP_MSPI_CS3:
485-
case NRF_FUN_SDP_MSPI_CS4:
486-
case NRF_FUN_SDP_MSPI_SCK:
487-
case NRF_FUN_SDP_MSPI_DQ0:
488-
case NRF_FUN_SDP_MSPI_DQ1:
489-
case NRF_FUN_SDP_MSPI_DQ2:
490-
case NRF_FUN_SDP_MSPI_DQ3:
491-
case NRF_FUN_SDP_MSPI_DQ4:
492-
case NRF_FUN_SDP_MSPI_DQ5:
493-
case NRF_FUN_SDP_MSPI_DQ6:
494-
case NRF_FUN_SDP_MSPI_DQ7:
495-
NRF_PSEL_SDP_MSPI(psel);
480+
#if defined(NRF_PSEL_HPF_MSPI)
481+
case NRF_FUN_HPF_MSPI_CS0:
482+
case NRF_FUN_HPF_MSPI_CS1:
483+
case NRF_FUN_HPF_MSPI_CS2:
484+
case NRF_FUN_HPF_MSPI_CS3:
485+
case NRF_FUN_HPF_MSPI_CS4:
486+
case NRF_FUN_HPF_MSPI_SCK:
487+
case NRF_FUN_HPF_MSPI_DQ0:
488+
case NRF_FUN_HPF_MSPI_DQ1:
489+
case NRF_FUN_HPF_MSPI_DQ2:
490+
case NRF_FUN_HPF_MSPI_DQ3:
491+
case NRF_FUN_HPF_MSPI_DQ4:
492+
case NRF_FUN_HPF_MSPI_DQ5:
493+
case NRF_FUN_HPF_MSPI_DQ6:
494+
case NRF_FUN_HPF_MSPI_DQ7:
495+
NRF_PSEL_HPF_MSPI(psel);
496496
dir = NRF_GPIO_PIN_DIR_OUTPUT;
497497
input = NRF_GPIO_PIN_INPUT_CONNECT;
498498
break;
499-
#endif /* defined(NRF_PSEL_SDP_MSPI) */
499+
#endif /* defined(NRF_PSEL_HPF_MSPI) */
500500
default:
501501
return -ENOTSUP;
502502
}

‎include/zephyr/dt-bindings/pinctrl/nrf-pinctrl.h

+56-28
Original file line numberDiff line numberDiff line change
@@ -172,34 +172,62 @@
172172
#define NRF_FUN_GRTC_CLKOUT_FAST 55U
173173
/** GRTC slow clock output */
174174
#define NRF_FUN_GRTC_CLKOUT_32K 56U
175-
/** SDP_MSPI CK */
176-
#define NRF_FUN_SDP_MSPI_SCK 57U
177-
/** SDP_MSPI DQ0 */
178-
#define NRF_FUN_SDP_MSPI_DQ0 58U
179-
/** SDP_MSPI DQ1 */
180-
#define NRF_FUN_SDP_MSPI_DQ1 59U
181-
/** SDP_MSPI DQ2 */
182-
#define NRF_FUN_SDP_MSPI_DQ2 60U
183-
/** SDP_MSPI DQ3 */
184-
#define NRF_FUN_SDP_MSPI_DQ3 61U
185-
/** SDP_MSPI DQ4 */
186-
#define NRF_FUN_SDP_MSPI_DQ4 62U
187-
/** SDP_MSPI DQ5 */
188-
#define NRF_FUN_SDP_MSPI_DQ5 63U
189-
/** SDP_MSPI DQ6 */
190-
#define NRF_FUN_SDP_MSPI_DQ6 64U
191-
/** SDP_MSPI DQ7 */
192-
#define NRF_FUN_SDP_MSPI_DQ7 65U
193-
/** SDP_MSPI CS0 */
194-
#define NRF_FUN_SDP_MSPI_CS0 66U
195-
/** SDP_MSPI CS1 */
196-
#define NRF_FUN_SDP_MSPI_CS1 67U
197-
/** SDP_MSPI CS2 */
198-
#define NRF_FUN_SDP_MSPI_CS2 68U
199-
/** SDP_MSPI CS3 */
200-
#define NRF_FUN_SDP_MSPI_CS3 69U
201-
/** SDP_MSPI CS4 */
202-
#define NRF_FUN_SDP_MSPI_CS4 70U
175+
/** High-Performance Framework MSPI clock pin */
176+
#define NRF_FUN_HPF_MSPI_SCK 57U
177+
/** High-Performance Framework MSPI data pin 0 */
178+
#define NRF_FUN_HPF_MSPI_DQ0 58U
179+
/** High-Performance Framework MSPI data pin 1 */
180+
#define NRF_FUN_HPF_MSPI_DQ1 59U
181+
/** High-Performance Framework MSPI data pin 2 */
182+
#define NRF_FUN_HPF_MSPI_DQ2 60U
183+
/** High-Performance Framework MSPI data pin 3 */
184+
#define NRF_FUN_HPF_MSPI_DQ3 61U
185+
/** High-Performance Framework MSPI data pin 4 */
186+
#define NRF_FUN_HPF_MSPI_DQ4 62U
187+
/** High-Performance Framework MSPI data pin 5 */
188+
#define NRF_FUN_HPF_MSPI_DQ5 63U
189+
/** High-Performance Framework MSPI data pin 6 */
190+
#define NRF_FUN_HPF_MSPI_DQ6 64U
191+
/** High-Performance Framework MSPI data pin 7 */
192+
#define NRF_FUN_HPF_MSPI_DQ7 65U
193+
/** High-Performance Framework MSPI chip select pin 0 */
194+
#define NRF_FUN_HPF_MSPI_CS0 66U
195+
/** High-Performance Framework MSPI chip select pin 1 */
196+
#define NRF_FUN_HPF_MSPI_CS1 67U
197+
/** High-Performance Framework MSPI chip select pin 2 */
198+
#define NRF_FUN_HPF_MSPI_CS2 68U
199+
/** High-Performance Framework MSPI chip select pin 3 */
200+
#define NRF_FUN_HPF_MSPI_CS3 69U
201+
/** High-Performance Framework MSPI chip select pin 4 */
202+
#define NRF_FUN_HPF_MSPI_CS4 70U
203+
/** SDP_MSPI clock pin */
204+
#define NRF_FUN_SDP_MSPI_SCK NRF_FUN_HPF_MSPI_SCK
205+
/** SDP_MSPI data pin 0 */
206+
#define NRF_FUN_SDP_MSPI_DQ0 NRF_FUN_HPF_MSPI_DQ0
207+
/** SDP_MSPI data pin 1 */
208+
#define NRF_FUN_SDP_MSPI_DQ1 NRF_FUN_HPF_MSPI_DQ1
209+
/** SDP_MSPI data pin 2 */
210+
#define NRF_FUN_SDP_MSPI_DQ2 NRF_FUN_HPF_MSPI_DQ2
211+
/** SDP_MSPI data pin 3 */
212+
#define NRF_FUN_SDP_MSPI_DQ3 NRF_FUN_HPF_MSPI_DQ3
213+
/** SDP_MSPI data pin 4 */
214+
#define NRF_FUN_SDP_MSPI_DQ4 NRF_FUN_HPF_MSPI_DQ4
215+
/** SDP_MSPI data pin 5 */
216+
#define NRF_FUN_SDP_MSPI_DQ5 NRF_FUN_HPF_MSPI_DQ5
217+
/** SDP_MSPI data pin 6 */
218+
#define NRF_FUN_SDP_MSPI_DQ6 NRF_FUN_HPF_MSPI_DQ6
219+
/** SDP_MSPI data pin 7 */
220+
#define NRF_FUN_SDP_MSPI_DQ7 NRF_FUN_HPF_MSPI_DQ7
221+
/** HPF_MSPI chip select 0 */
222+
#define NRF_FUN_SDP_MSPI_CS0 NRF_FUN_HPF_MSPI_CS0
223+
/** HPF_MSPI chip select 1 */
224+
#define NRF_FUN_SDP_MSPI_CS1 NRF_FUN_HPF_MSPI_CS1
225+
/** HPF_MSPI chip select 2 */
226+
#define NRF_FUN_SDP_MSPI_CS2 NRF_FUN_HPF_MSPI_CS2
227+
/** HPF_MSPI chip select 3 */
228+
#define NRF_FUN_SDP_MSPI_CS3 NRF_FUN_HPF_MSPI_CS3
229+
/** HPF_MSPI chip select 4 */
230+
#define NRF_FUN_SDP_MSPI_CS4 NRF_FUN_HPF_MSPI_CS4
203231
/** TDM SCK in master mode */
204232
#define NRF_FUN_TDM_SCK_M 71U
205233
/** TDM SCK in slave mode */

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