soc: nordic: nrf54h: power: Changes needed to enable soft off

Add missing settings in LRCCONF needed before soft off.
Add releasing GRTC request.

Add enabling of DCACHE and ICACHE memory blocks during init. It is a
default register value but we can enter init when waken up from soft off
and in that case values there will coming from power off sequence and not
from HW device reset.

Signed-off-by: Krzysztof Chruściński <[email protected]>

Author: nordic-krch

soc/nordic/nrf54h/power.c

@@ -65,7 +65,14 @@ void nrf_poweroff(void)
 #if !defined(CONFIG_SOC_NRF54H20_CPURAD)
 	/* Disable retention */
 	nrf_lrcconf_retain_set(NRF_LRCCONF010, NRF_LRCCONF_POWER_MAIN, false);
+	nrf_lrcconf_poweron_force_set(NRF_LRCCONF010, NRF_LRCCONF_POWER_MAIN, false);
+#else
+	/* Active power domain (fast clock domain). */
 	nrf_lrcconf_retain_set(NRF_LRCCONF010, NRF_LRCCONF_POWER_DOMAIN_0, false);
+	nrf_lrcconf_poweron_force_set(NRF_LRCCONF010, NRF_LRCCONF_POWER_DOMAIN_0, false);
+	/* Radio power domain (slow clock domain). */
+	nrf_lrcconf_retain_set(NRF_LRCCONF010, NRF_LRCCONF_POWER_DOMAIN_1, false);
+	nrf_lrcconf_poweron_force_set(NRF_LRCCONF010, NRF_LRCCONF_POWER_DOMAIN_1, false);
 #endif
 	common_suspend();
 

soc/nordic/nrf54h/soc.c

@@ -129,7 +129,16 @@ static int nordicsemi_nrf54h_init(void)
 {
 	int err;
 
+	if (IS_ENABLED(CONFIG_ICACHE)) {
+		nrf_memconf_ramblock_control_enable_set(NRF_MEMCONF, RAMBLOCK_POWER_ID,
+						RAMBLOCK_CONTROL_BIT_ICACHE, true);
+	}
 	sys_cache_instr_enable();
+
+	if (IS_ENABLED(CONFIG_DCACHE)) {
+		nrf_memconf_ramblock_control_enable_set(NRF_MEMCONF, RAMBLOCK_POWER_ID,
+						RAMBLOCK_CONTROL_BIT_DCACHE, true);
+	}
 	sys_cache_data_enable();
 
 	power_domain_init();