diff --git a/.checkpatch.conf b/.checkpatch.conf index accee08b149..a6d9a31f11d 100644 --- a/.checkpatch.conf +++ b/.checkpatch.conf @@ -5,7 +5,6 @@ --min-conf-desc-length=1 --typedefsfile=scripts/checkpatch/typedefsfile ---ignore BRACES --ignore PRINTK_WITHOUT_KERN_LEVEL --ignore SPLIT_STRING --ignore VOLATILE diff --git a/.clang-format b/.clang-format index 2b438bf57cc..940f22994b8 100644 --- a/.clang-format +++ b/.clang-format @@ -46,6 +46,7 @@ ForEachMacros: - 'SYS_DLIST_FOR_EACH_CONTAINER_SAFE' - 'SYS_DLIST_FOR_EACH_NODE' - 'SYS_DLIST_FOR_EACH_NODE_SAFE' + - 'SYS_SEM_LOCK' - 'SYS_SFLIST_FOR_EACH_CONTAINER' - 'SYS_SFLIST_FOR_EACH_CONTAINER_SAFE' - 'SYS_SFLIST_FOR_EACH_NODE' @@ -79,6 +80,8 @@ ForEachMacros: - 'HTTP_SERVER_CONTENT_TYPE_FOREACH' - 'HTTP_SERVICE_FOREACH' - 'HTTP_SERVICE_FOREACH_RESOURCE' + - 'I3C_BUS_FOR_EACH_I3CDEV' + - 'I3C_BUS_FOR_EACH_I2CDEV' IfMacros: - 'CHECKIF' # Disabled for now, see bug https://github.com/zephyrproject-rtos/zephyr/issues/48520 @@ -101,5 +104,11 @@ SpaceBeforeParens: ControlStatementsExceptControlMacros SortIncludes: Never UseTab: ForContinuationAndIndentation WhitespaceSensitiveMacros: + - COND_CODE_0 + - COND_CODE_1 + - IF_DISABLED + - IF_ENABLED + - LISTIFY - STRINGIFY - Z_STRINGIFY + - DT_FOREACH_PROP_ELEM_SEP diff --git a/.github/SECURITY.md b/.github/SECURITY.md index 42354f627cf..ba2dedb99e4 100644 --- a/.github/SECURITY.md +++ b/.github/SECURITY.md @@ -8,11 +8,11 @@ updates: - The most recent release, and the release prior to that. - Active LTS releases. -At this time, with the latest release of v3.6, the supported +At this time, with the latest release of v4.0, the supported versions are: - - v3.7: Current LTS - - v3.6: Prior release + - v4.0: Current release + - v3.7: Prior release and Current LTS - v2.7: Prior LTS ## Reporting process diff --git a/.github/workflows/assigner.yml b/.github/workflows/assigner.yml index 6e4e01c8ea1..be3696c4d30 100644 --- a/.github/workflows/assigner.yml +++ b/.github/workflows/assigner.yml @@ -24,8 +24,7 @@ jobs: steps: - name: Install Python dependencies run: | - sudo pip3 install -U setuptools wheel pip - pip3 install -U PyGithub>=1.55 west + pip install -U PyGithub>=1.55 west - name: Check out source code uses: actions/checkout@v4 diff --git a/.github/workflows/backport_issue_check.yml b/.github/workflows/backport_issue_check.yml index ecaaf352827..2d2c4fda6a8 100644 --- a/.github/workflows/backport_issue_check.yml +++ b/.github/workflows/backport_issue_check.yml @@ -25,8 +25,7 @@ jobs: - name: Install Python dependencies run: | - sudo pip3 install -U setuptools wheel pip - pip3 install -U pygithub + pip install -U pygithub - name: Run backport issue checker env: diff --git a/.github/workflows/bsim-tests.yaml b/.github/workflows/bsim-tests.yaml index 0c50ca5d6fd..66d47c68a1c 100644 --- a/.github/workflows/bsim-tests.yaml +++ b/.github/workflows/bsim-tests.yaml @@ -12,12 +12,14 @@ on: - "dts/*/nordic/**" - "tests/bluetooth/common/testlib/**" - "samples/bluetooth/**" - - "boards/posix/**" - - "soc/posix/**" + - "boards/native/**" + - "soc/native/**" - "arch/posix/**" - "include/zephyr/arch/posix/**" - "scripts/native_simulator/**" - "samples/net/sockets/echo_*/**" + - "modules/hal_nordic/**" + - "modules/mbedtls/**" - "modules/openthread/**" - "subsys/net/l2/openthread/**" - "include/zephyr/net/openthread.h" @@ -36,7 +38,7 @@ jobs: runs-on: group: zephyr-runner-v2-linux-x64-4xlarge container: - image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.26.14.20240823 + image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.27.4.20241026 options: '--entrypoint /bin/bash' env: ZEPHYR_TOOLCHAIN_VARIANT: zephyr @@ -76,7 +78,9 @@ jobs: git config --global user.email "bot@zephyrproject.org" git config --global user.name "Zephyr Bot" rm -fr ".git/rebase-apply" + rm -fr ".git/rebase-merge" git rebase origin/${BASE_REF} + git clean -f -d git log --pretty=oneline | head -n 10 west init -l . || true west config manifest.group-filter -- +ci @@ -94,14 +98,16 @@ jobs: .github/workflows/bsim-tests.yaml .github/workflows/bsim-tests-publish.yaml west.yml - boards/posix/ - soc/posix/ + boards/native/ + soc/native/ arch/posix/ include/zephyr/arch/posix/ scripts/native_simulator/ tests/bsim/* boards/nordic/nrf5*/*dt* dts/*/nordic/ + modules/mbedtls/** + modules/hal_nordic/** - name: Check if Bluethooth files changed uses: tj-actions/changed-files@v45 @@ -166,7 +172,7 @@ jobs: - name: Merge Test Results run: | - pip3 install junitparser junit2html + pip install junitparser junit2html junitparser merge --glob "./bsim_*/*bsim_results.*.xml" "./twister-out/twister.xml" junit.xml junit2html junit.xml junit.html diff --git a/.github/workflows/bug_snapshot.yaml b/.github/workflows/bug_snapshot.yaml index b4f9022bf28..f10dc718b6e 100644 --- a/.github/workflows/bug_snapshot.yaml +++ b/.github/workflows/bug_snapshot.yaml @@ -25,8 +25,7 @@ jobs: - name: Install Python dependencies run: | - sudo pip3 install -U setuptools wheel pip - pip3 install -U pygithub + pip install -U pygithub - name: Snapshot bugs env: diff --git a/.github/workflows/clang.yaml b/.github/workflows/clang.yaml index e88141a9e23..11d249cd937 100644 --- a/.github/workflows/clang.yaml +++ b/.github/workflows/clang.yaml @@ -12,7 +12,7 @@ jobs: runs-on: group: zephyr-runner-v2-linux-x64-4xlarge container: - image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.26.14.20240823 + image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.27.4.20241026 options: '--entrypoint /bin/bash' strategy: fail-fast: false @@ -61,7 +61,9 @@ jobs: git config --global user.email "bot@zephyrproject.org" git config --global user.name "Zephyr Bot" rm -fr ".git/rebase-apply" + rm -fr ".git/rebase-merge" git rebase origin/${BASE_REF} + git clean -f -d git log --pretty=oneline | head -n 10 west init -l . || true west config --global update.narrow true @@ -106,13 +108,13 @@ jobs: export ZEPHYR_TOOLCHAIN_VARIANT=llvm # check if we need to run a full twister or not based on files changed - python3 ./scripts/ci/test_plan.py --platform ${{ matrix.platform }} -c origin/${BASE_REF}.. + python3 ./scripts/ci/test_plan.py --no-detailed-test-id --platform ${{ matrix.platform }} -c origin/${BASE_REF}.. # We can limit scope to just what has changed if [ -s testplan.json ]; then echo "report_needed=1" >> $GITHUB_OUTPUT # Full twister but with options based on changes - ./scripts/twister --force-color --inline-logs -M -N -v --load-tests testplan.json --retry-failed 2 + ./scripts/twister --no-detailed-test-id --force-color --inline-logs -M -N -v --load-tests testplan.json --retry-failed 2 else # if nothing is run, skip reporting step echo "report_needed=0" >> $GITHUB_OUTPUT @@ -142,7 +144,7 @@ jobs: path: artifacts - name: Merge Test Results run: | - pip3 install junitparser junit2html + pip install junitparser junit2html junitparser merge artifacts/*/twister.xml junit.xml junit2html junit.xml junit-clang.html diff --git a/.github/workflows/codecov.yaml b/.github/workflows/codecov.yaml index aa81056cdfd..d03ced6e474 100644 --- a/.github/workflows/codecov.yaml +++ b/.github/workflows/codecov.yaml @@ -14,7 +14,7 @@ jobs: runs-on: group: zephyr-runner-v2-linux-x64-4xlarge container: - image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.26.14.20240823 + image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.27.4.20241026 options: '--entrypoint /bin/bash' strategy: fail-fast: false @@ -34,7 +34,7 @@ jobs: CCACHE_REMOTE_STORAGE: "redis://cache-*.keydb-cache.svc.cluster.local|shards=1,2,3" CCACHE_REMOTE_ONLY: "true" # `--specs` is ignored because ccache is unable to resovle the toolchain specs file path. - CCACHE_IGNOREOPTIONS: '--specs=*' + CCACHE_IGNOREOPTIONS: '-specs=* --specs=*' steps: - name: Apply container owner mismatch workaround run: | @@ -101,7 +101,7 @@ jobs: export ZEPHYR_BASE=${PWD} export ZEPHYR_TOOLCHAIN_VARIANT=zephyr mkdir -p coverage/reports - pip3 install gcovr==6.0 + pip install gcovr==6.0 ./scripts/twister -E ${{matrix.normalized}}-testplan.json ls -la ./scripts/twister \ @@ -182,7 +182,7 @@ jobs: - name: Merge coverage files run: | pushd ./coverage/reports - pip3 install gcovr==6.0 + pip install gcovr==6.0 gcovr ${{ steps.get-coverage-files.outputs.mergefiles }} --merge-mode-functions=separate --json merged.json gcovr ${{ steps.get-coverage-files.outputs.mergefiles }} --merge-mode-functions=separate --cobertura merged.xml popd diff --git a/.github/workflows/coding_guidelines.yml b/.github/workflows/coding_guidelines.yml index 1bc6ee2e666..9ab2bc974b1 100644 --- a/.github/workflows/coding_guidelines.yml +++ b/.github/workflows/coding_guidelines.yml @@ -21,9 +21,8 @@ jobs: - name: Install python dependencies run: | - pip3 install unidiff - pip3 install wheel - pip3 install sh + pip install unidiff + pip install sh - name: Install Packages run: | @@ -40,7 +39,10 @@ jobs: git config --global user.email "actions@zephyrproject.org" git config --global user.name "Github Actions" git remote -v + rm -fr ".git/rebase-apply" + rm -fr ".git/rebase-merge" git rebase origin/${BASE_REF} + git clean -f -d source zephyr-env.sh # debug ls -la diff --git a/.github/workflows/compliance.yml b/.github/workflows/compliance.yml index c8ffedcb77b..56927365550 100644 --- a/.github/workflows/compliance.yml +++ b/.github/workflows/compliance.yml @@ -23,6 +23,23 @@ jobs: ref: ${{ github.event.pull_request.head.sha }} fetch-depth: 0 + - name: Rebase onto the target branch + env: + BASE_REF: ${{ github.base_ref }} + run: | + git config --global user.email "you@example.com" + git config --global user.name "Your Name" + git remote -v + # Ensure there's no merge commits in the PR + #[[ "$(git rev-list --merges --count origin/${BASE_REF}..)" == "0" ]] || \ + #(echo "::error ::Merge commits not allowed, rebase instead";false) + rm -fr ".git/rebase-apply" + rm -fr ".git/rebase-merge" + git rebase origin/${BASE_REF} + git clean -f -d + # debug + git log --pretty=oneline | head -n 10 + - name: Set up Python uses: actions/setup-python@v5 with: @@ -36,24 +53,11 @@ jobs: - name: Install python dependencies run: | - pip3 install setuptools - pip3 install wheel - pip3 install python-magic lxml junitparser gitlint pylint pykwalify yamllint clang-format unidiff sphinx-lint - pip3 install west + pip install -r scripts/requirements-compliance.txt + pip install west - name: west setup - env: - BASE_REF: ${{ github.base_ref }} run: | - git config --global user.email "you@example.com" - git config --global user.name "Your Name" - git remote -v - # Ensure there's no merge commits in the PR - #[[ "$(git rev-list --merges --count origin/${BASE_REF}..)" == "0" ]] || \ - #(echo "::error ::Merge commits not allowed, rebase instead";false) - git rebase origin/${BASE_REF} - # debug - git log --pretty=oneline | head -n 10 west init -l . || true west config manifest.group-filter -- +ci,-optional west update -o=--depth=1 -n 2>&1 1> west.update.log || west update -o=--depth=1 -n 2>&1 1> west.update2.log @@ -78,8 +82,8 @@ jobs: git log --pretty=oneline | head -n 10 # Increase rename limit to allow for large PRs git config diff.renameLimit 10000 - ./scripts/ci/check_compliance.py --annotate -e KconfigBasic -e Kconfig \ - -e KconfigBasicNoModules -e ModulesMaintainers -c origin/${BASE_REF}.. + ./scripts/ci/check_compliance.py --annotate -e KconfigBasic -e ClangFormat \ + -e Kconfig -e KconfigBasicNoModules -e ModulesMaintainers -c origin/${BASE_REF}.. - name: upload-results uses: actions/upload-artifact@v4 diff --git a/.github/workflows/daily_test_version.yml b/.github/workflows/daily_test_version.yml index 1886b4a8c80..3a43ac64300 100644 --- a/.github/workflows/daily_test_version.yml +++ b/.github/workflows/daily_test_version.yml @@ -25,7 +25,7 @@ jobs: - name: install-pip run: | - pip3 install gitpython + pip install gitpython - name: checkout uses: actions/checkout@v4 diff --git a/.github/workflows/devicetree_checks.yml b/.github/workflows/devicetree_checks.yml index 060a5d95973..345eb5b7db0 100644 --- a/.github/workflows/devicetree_checks.yml +++ b/.github/workflows/devicetree_checks.yml @@ -26,7 +26,7 @@ jobs: runs-on: ${{ matrix.os }} strategy: matrix: - python-version: ['3.10', '3.11', '3.12'] + python-version: ['3.10', '3.11', '3.12', '3.13'] os: [ubuntu-22.04, macos-14, windows-2022] steps: - name: checkout @@ -62,8 +62,7 @@ jobs: ${{ runner.os }}-pip-${{ matrix.python-version }} - name: install python dependencies run: | - pip3 install wheel - pip3 install pytest pyyaml tox + pip install pytest pyyaml tox - name: run tox working-directory: scripts/dts/python-devicetree run: | diff --git a/.github/workflows/do_not_merge.yml b/.github/workflows/do_not_merge.yml index b6954e288c9..b2bbefdc6fe 100644 --- a/.github/workflows/do_not_merge.yml +++ b/.github/workflows/do_not_merge.yml @@ -6,14 +6,14 @@ on: jobs: do-not-merge: - if: ${{ contains(github.event.*.labels.*.name, 'DNM') || - contains(github.event.*.labels.*.name, 'TSC') || - contains(github.event.*.labels.*.name, 'Architecture Review') || - contains(github.event.*.labels.*.name, 'dev-review') }} name: Prevent Merging runs-on: ubuntu-22.04 steps: - name: Check for label + if: ${{ contains(github.event.*.labels.*.name, 'DNM') || + contains(github.event.*.labels.*.name, 'TSC') || + contains(github.event.*.labels.*.name, 'Architecture Review') || + contains(github.event.*.labels.*.name, 'dev-review') }} run: | echo "Pull request is labeled as 'DNM', 'TSC', 'Architecture Review' or 'dev-review'." echo "This workflow fails so that the pull request cannot be merged." diff --git a/.github/workflows/doc-build.yml b/.github/workflows/doc-build.yml index 1872a824604..69c7b787c45 100644 --- a/.github/workflows/doc-build.yml +++ b/.github/workflows/doc-build.yml @@ -42,6 +42,7 @@ jobs: with: files: | doc/ + boards/**/doc/ **.rst include/ kernel/include/kernel_arch_interface.h @@ -93,7 +94,10 @@ jobs: run: | git config --global user.email "actions@zephyrproject.org" git config --global user.name "Github Actions" + rm -fr ".git/rebase-apply" + rm -fr ".git/rebase-merge" git rebase origin/${BASE_REF} + git clean -f -d git log --graph --oneline HEAD...${PR_HEAD} - name: cache-pip @@ -104,11 +108,10 @@ jobs: - name: install-pip run: | - sudo pip3 install -U setuptools wheel pip - pip3 install -r doc/requirements.txt - pip3 install west==${WEST_VERSION} - pip3 install cmake==${CMAKE_VERSION} - pip3 install coverxygen + pip install -r doc/requirements.txt + pip install west==${WEST_VERSION} + pip install cmake==${CMAKE_VERSION} + pip install coverxygen - name: west setup run: | @@ -219,10 +222,9 @@ jobs: - name: install-pip run: | - pip3 install -U setuptools wheel pip - pip3 install -r doc/requirements.txt - pip3 install west==${WEST_VERSION} - pip3 install cmake==${CMAKE_VERSION} + pip install -r doc/requirements.txt + pip install west==${WEST_VERSION} + pip install cmake==${CMAKE_VERSION} - name: west setup run: | diff --git a/.github/workflows/doc-publish-pr.yml b/.github/workflows/doc-publish-pr.yml index b202b0a790a..786bd14aed2 100644 --- a/.github/workflows/doc-publish-pr.yml +++ b/.github/workflows/doc-publish-pr.yml @@ -21,16 +21,24 @@ jobs: steps: - name: Download artifacts + id: download-artifacts uses: dawidd6/action-download-artifact@v6 with: workflow: doc-build.yml run_id: ${{ github.event.workflow_run.id }} + if_no_artifact_found: ignore - name: Load PR number - run: | - echo "PR_NUM=$(> $GITHUB_ENV + if: steps.download-artifacts.outputs.found_artifact == 'true' + uses: actions/github-script@v7 + with: + script: | + let fs = require("fs"); + let pr_number = Number(fs.readFileSync("./pr_num/pr_num")); + core.exportVariable("PR_NUM", pr_number); - name: Check PR number + if: steps.download-artifacts.outputs.found_artifact == 'true' id: check-pr uses: carpentries/actions/check-valid-pr@v0.14.0 with: @@ -38,12 +46,15 @@ jobs: sha: ${{ github.event.workflow_run.head_sha }} - name: Validate PR number - if: steps.check-pr.outputs.VALID != 'true' + if: | + steps.download-artifacts.outputs.found_artifact == 'true' && + steps.check-pr.outputs.VALID != 'true' run: | echo "ABORT: PR number validation failed!" exit 1 - name: Uncompress HTML docs + if: steps.download-artifacts.outputs.found_artifact == 'true' run: | tar xf html-output/html-output.tar.xz -C html-output if [ -f api-coverage/api-coverage.tar.xz ]; then @@ -51,6 +62,7 @@ jobs: fi - name: Configure AWS Credentials + if: steps.download-artifacts.outputs.found_artifact == 'true' uses: aws-actions/configure-aws-credentials@v4 with: aws-access-key-id: ${{ vars.AWS_BUILDS_ZEPHYR_PR_ACCESS_KEY_ID }} @@ -58,6 +70,7 @@ jobs: aws-region: us-east-1 - name: Upload to AWS S3 + if: steps.download-artifacts.outputs.found_artifact == 'true' env: HEAD_BRANCH: ${{ github.event.workflow_run.head_branch }} run: | diff --git a/.github/workflows/errno.yml b/.github/workflows/errno.yml index b1f7e6f4e62..d3fe1b0dcae 100644 --- a/.github/workflows/errno.yml +++ b/.github/workflows/errno.yml @@ -10,7 +10,7 @@ jobs: check-errno: runs-on: ubuntu-22.04 container: - image: ghcr.io/zephyrproject-rtos/ci:v0.26.13 + image: ghcr.io/zephyrproject-rtos/ci:v0.27.4 steps: - name: Apply container owner mismatch workaround diff --git a/.github/workflows/footprint-tracking.yml b/.github/workflows/footprint-tracking.yml index 08b858af477..78f761cb545 100644 --- a/.github/workflows/footprint-tracking.yml +++ b/.github/workflows/footprint-tracking.yml @@ -26,8 +26,11 @@ jobs: group: zephyr-runner-v2-linux-x64-4xlarge if: github.repository_owner == 'zephyrproject-rtos' container: - image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.26.14.20240823 + image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.27.4.20241026 options: '--entrypoint /bin/bash' + defaults: + run: + shell: bash strategy: fail-fast: false env: @@ -55,7 +58,7 @@ jobs: run: | sudo apt-get update sudo apt-get install -y python3-venv - sudo pip3 install -U setuptools wheel pip gitpython + pip install -U gitpython - name: checkout uses: actions/checkout@v4 @@ -91,5 +94,35 @@ jobs: run: | python3 -m venv .venv . .venv/bin/activate - pip3 install awscli + pip install awscli aws s3 sync --quiet footprint_data/ s3://testing.zephyrproject.org/footprint_data/ + + - name: Transform Footprint data to Twister JSON reports + run: | + shopt -s globstar + export ZEPHYR_BASE=${PWD} + python3 ./scripts/footprint/pack_as_twister.py -vvv \ + --plan ./scripts/footprint/plan.txt \ + --test-name='name.feature' \ + ./footprint_data/**/ + + - name: Upload to ElasticSearch + env: + ELASTICSEARCH_KEY: ${{ secrets.ELASTICSEARCH_KEY }} + ELASTICSEARCH_SERVER: "https://elasticsearch.zephyrproject.io:443" + ELASTICSEARCH_INDEX: ${{ vars.FOOTPRINT_TRACKING_INDEX }} + run: | + shopt -s globstar + pip install -U elasticsearch + run_date=`date --iso-8601=minutes` + python3 ./scripts/ci/upload_test_results_es.py -r ${run_date} \ + --flatten footprint \ + --flatten-list-names "{'children':'name'}" \ + --transform "{ 'footprint_name': '^(?P([^\/]+\/){0,2})(?P([^\/]*\/)*)(?P[^\/]*)$' }" \ + --run-id "${{ github.run_id }}" \ + --run-attempt "${{ github.run_attempt }}" \ + --run-workflow "footprint-tracking:${{ github.event_name }}" \ + --run-branch "${{ github.ref_name }}" \ + -i ${ELASTICSEARCH_INDEX} \ + ./footprint_data/**/twister_footprint.json + # diff --git a/.github/workflows/hello_world_multiplatform.yaml b/.github/workflows/hello_world_multiplatform.yaml index 08fd42d7866..59d622149a2 100644 --- a/.github/workflows/hello_world_multiplatform.yaml +++ b/.github/workflows/hello_world_multiplatform.yaml @@ -12,8 +12,7 @@ on: - v*-branch - collab-* paths: - - 'scripts/build/**' - - 'scripts/requirements*.txt' + - 'scripts/**' - '.github/workflows/hello_world_multiplatform.yaml' - 'SDK_VERSION' @@ -45,7 +44,10 @@ jobs: run: | git config --global user.email "actions@zephyrproject.org" git config --global user.name "Github Actions" + rm -fr ".git/rebase-apply" + rm -fr ".git/rebase-merge" git rebase origin/${BASE_REF} + git clean -f -d git log --graph --oneline HEAD...${PR_HEAD} - name: Set up Python @@ -68,7 +70,7 @@ jobs: elif [ "${{ runner.os }}" = "Windows" ]; then EXTRA_TWISTER_FLAGS="-P native_sim --short-build-path -O/tmp/twister-out" fi - ./scripts/twister --force-color --inline-logs -T samples/hello_world -v $EXTRA_TWISTER_FLAGS + ./scripts/twister --force-color --inline-logs -T samples/hello_world -T samples/cpp/hello_world -v $EXTRA_TWISTER_FLAGS - name: Upload artifacts if: failure() @@ -77,3 +79,4 @@ jobs: if-no-files-found: ignore path: zephyr/twister-out/*/samples/hello_world/sample.basic.helloworld/build.log + zephyr/twister-out/*/samples/cpp/hello_world/sample.cpp.helloworld/build.log diff --git a/.github/workflows/manifest.yml b/.github/workflows/manifest.yml index 76b80f66504..c3bdc4ff6c8 100644 --- a/.github/workflows/manifest.yml +++ b/.github/workflows/manifest.yml @@ -20,13 +20,13 @@ jobs: BASE_REF: ${{ github.base_ref }} working-directory: zephyrproject/zephyr run: | - pip3 install west + pip install west git config --global user.email "you@example.com" git config --global user.name "Your Name" west init -l . || true - name: Manifest - uses: zephyrproject-rtos/action-manifest@v1.3.1 + uses: zephyrproject-rtos/action-manifest@v1.7.0 with: github-token: ${{ secrets.ZB_GITHUB_TOKEN }} manifest-path: 'west.yml' diff --git a/.github/workflows/pylib_tests.yml b/.github/workflows/pylib_tests.yml index 8827acebdb4..bf9d8289212 100644 --- a/.github/workflows/pylib_tests.yml +++ b/.github/workflows/pylib_tests.yml @@ -25,7 +25,7 @@ jobs: runs-on: ${{ matrix.os }} strategy: matrix: - python-version: ['3.10', '3.11', '3.12'] + python-version: ['3.10', '3.11', '3.12', '3.13'] os: [ubuntu-22.04] steps: - name: checkout @@ -44,7 +44,7 @@ jobs: ${{ runner.os }}-pip-${{ matrix.python-version }} - name: install-packages run: | - pip3 install -r scripts/requirements-base.txt -r scripts/requirements-build-test.txt + pip install -r scripts/requirements-base.txt -r scripts/requirements-build-test.txt - name: Run pytest for build_helpers env: ZEPHYR_BASE: ./ diff --git a/.github/workflows/scripts_tests.yml b/.github/workflows/scripts_tests.yml index 86db35ae02e..06e12ada528 100644 --- a/.github/workflows/scripts_tests.yml +++ b/.github/workflows/scripts_tests.yml @@ -25,7 +25,7 @@ jobs: runs-on: ${{ matrix.os }} strategy: matrix: - python-version: ['3.10', '3.11', '3.12'] + python-version: ['3.10', '3.11', '3.12', '3.13'] os: [ubuntu-20.04] steps: - name: checkout @@ -42,7 +42,10 @@ jobs: run: | git config --global user.email "actions@zephyrproject.org" git config --global user.name "Github Actions" + rm -fr ".git/rebase-apply" + rm -fr ".git/rebase-merge" git rebase origin/${BASE_REF} + git clean -f -d git log --graph --oneline HEAD...${PR_HEAD} - name: Set up Python ${{ matrix.python-version }} @@ -61,7 +64,7 @@ jobs: - name: install-packages run: | - pip3 install -r scripts/requirements-base.txt -r scripts/requirements-build-test.txt + pip install -r scripts/requirements-base.txt -r scripts/requirements-build-test.txt - name: Run pytest env: diff --git a/.github/workflows/stats_merged_prs.yml b/.github/workflows/stats_merged_prs.yml index cd874b65b1a..0f86958e47b 100644 --- a/.github/workflows/stats_merged_prs.yml +++ b/.github/workflows/stats_merged_prs.yml @@ -20,5 +20,5 @@ jobs: ELASTICSEARCH_SERVER: "https://elasticsearch.zephyrproject.io:443" PR_STAT_ES_INDEX: ${{ vars.PR_STAT_ES_INDEX }} run: | - pip3 install pygithub elasticsearch + pip install pygithub elasticsearch python3 ./scripts/ci/stats/merged_prs.py --pull-request ${{ github.event.pull_request.number }} --repo ${{ github.repository }} diff --git a/.github/workflows/twister-prep.yaml b/.github/workflows/twister-prep.yaml new file mode 100644 index 00000000000..51bc771059d --- /dev/null +++ b/.github/workflows/twister-prep.yaml @@ -0,0 +1,147 @@ +name: Prepare For a Twister Run + +on: + workflow_call: + outputs: + subset: + description: subset + value: ${{ jobs.prep_push.outputs.subset != '' && jobs.prep_push.outputs.subset || jobs.prep_pr.outputs.subset }} + size: + description: size + value: ${{ jobs.prep_push.outputs.size != '' && jobs.prep_push.outputs.size || jobs.prep_pr.outputs.size }} + fullrun: + description: fullrun + value: ${{ jobs.prep_push.outputs.fullrun != '' && jobs.prep_push.outputs.fullrun || jobs.prep_pr.outputs.size }} + +jobs: + prep_pr: + if: github.repository_owner == 'zephyrproject-rtos' && github.event_name == 'pull_request_target' + runs-on: + group: zephyr-runner-v2-linux-x64-4xlarge + container: + image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.27.4.20241026 + options: '--entrypoint /bin/bash' + outputs: + subset: ${{ steps.output-services.outputs.subset }} + size: ${{ steps.output-services.outputs.size }} + fullrun: ${{ steps.output-services.outputs.fullrun }} + env: + MATRIX_SIZE: 10 + PUSH_MATRIX_SIZE: 20 + DAILY_MATRIX_SIZE: 80 + BSIM_OUT_PATH: /opt/bsim/ + BSIM_COMPONENTS_PATH: /opt/bsim/components + TESTS_PER_BUILDER: 700 + COMMIT_RANGE: ${{ github.event.pull_request.base.sha }}..${{ github.event.pull_request.head.sha }} + BASE_REF: ${{ github.base_ref }} + steps: + - name: Apply container owner mismatch workaround + run: | + # FIXME: The owner UID of the GITHUB_WORKSPACE directory may not + # match the container user UID because of the way GitHub + # Actions runner is implemented. Remove this workaround when + # GitHub comes up with a fundamental fix for this problem. + git config --global --add safe.directory ${GITHUB_WORKSPACE} + + - name: Print cloud service information + run: | + echo "ZEPHYR_RUNNER_CLOUD_PROVIDER = ${ZEPHYR_RUNNER_CLOUD_PROVIDER}" + echo "ZEPHYR_RUNNER_CLOUD_NODE = ${ZEPHYR_RUNNER_CLOUD_NODE}" + echo "ZEPHYR_RUNNER_CLOUD_POD = ${ZEPHYR_RUNNER_CLOUD_POD}" + + - name: Clone cached Zephyr repository + continue-on-error: true + run: | + git clone --shared /repo-cache/zephyrproject/zephyr . + git remote set-url origin ${GITHUB_SERVER_URL}/${GITHUB_REPOSITORY} + + - name: Checkout + uses: actions/checkout@v4 + with: + ref: ${{ github.event.pull_request.head.sha }} + fetch-depth: 0 + persist-credentials: false + + - name: Environment Setup + run: | + git config --global user.email "bot@zephyrproject.org" + git config --global user.name "Zephyr Bot" + rm -fr ".git/rebase-apply" + rm -fr ".git/rebase-merge" + git rebase origin/${BASE_REF} + git clean -f -d + git log --pretty=oneline | head -n 10 + west init -l . || true + west config manifest.group-filter -- +ci,+optional + west config --global update.narrow true + west update --path-cache /repo-cache/zephyrproject 2>&1 1> west.update.log || west update --path-cache /repo-cache/zephyrproject 2>&1 1> west.update.log || ( rm -rf ../modules ../bootloader ../tools && west update --path-cache /repo-cache/zephyrproject) + west forall -c 'git reset --hard HEAD' + + echo "ZEPHYR_SDK_INSTALL_DIR=/opt/toolchains/zephyr-sdk-$( cat SDK_VERSION )" >> $GITHUB_ENV + + - name: Generate Test Plan with Twister + id: test-plan + run: | + export ZEPHYR_BASE=${PWD} + export ZEPHYR_TOOLCHAIN_VARIANT=zephyr + python3 ./scripts/ci/test_plan.py -c origin/${BASE_REF}.. --no-detailed-test-id --pull-request -t $TESTS_PER_BUILDER + if [ -s .testplan ]; then + cat .testplan >> $GITHUB_ENV + else + echo "TWISTER_NODES=${MATRIX_SIZE}" >> $GITHUB_ENV + fi + rm -f testplan.json .testplan + + - name: Determine matrix size + id: output-services + run: | + if [ -n "${TWISTER_NODES}" ]; then + subset="[$(seq -s',' 1 ${TWISTER_NODES})]" + else + subset="[$(seq -s',' 1 ${MATRIX_SIZE})]" + fi + size=${TWISTER_NODES} + + echo "subset=${subset}" >> $GITHUB_OUTPUT + echo "size=${size}" >> $GITHUB_OUTPUT + echo "fullrun=${TWISTER_FULL}" >> $GITHUB_OUTPUT + + prep_push: + if: github.repository_owner == 'zephyrproject-rtos' && (github.event_name == 'push' || github.event_name == 'schedule') + runs-on: ubuntu-22.04 + outputs: + subset: ${{ steps.output-services.outputs.subset }} + size: ${{ steps.output-services.outputs.size }} + fullrun: ${{ steps.output-services.outputs.fullrun }} + env: + MATRIX_SIZE: 10 + PUSH_MATRIX_SIZE: 20 + DAILY_MATRIX_SIZE: 80 + BSIM_OUT_PATH: /opt/bsim/ + BSIM_COMPONENTS_PATH: /opt/bsim/components + TESTS_PER_BUILDER: 700 + COMMIT_RANGE: ${{ github.event.pull_request.base.sha }}..${{ github.event.pull_request.head.sha }} + BASE_REF: ${{ github.base_ref }} + steps: + - name: Print cloud service information + run: | + echo "ZEPHYR_RUNNER_CLOUD_PROVIDER = ${ZEPHYR_RUNNER_CLOUD_PROVIDER}" + echo "ZEPHYR_RUNNER_CLOUD_NODE = ${ZEPHYR_RUNNER_CLOUD_NODE}" + echo "ZEPHYR_RUNNER_CLOUD_POD = ${ZEPHYR_RUNNER_CLOUD_POD}" + + - name: Determine matrix size + id: output-services + run: | + if [ "${{github.event_name}}" = "push" ]; then + subset="[$(seq -s',' 1 ${PUSH_MATRIX_SIZE})]" + size=${MATRIX_SIZE} + elif [ "${{github.event_name}}" = "schedule" -a "${{github.repository}}" = "zephyrproject-rtos/zephyr" ]; then + subset="[$(seq -s',' 1 ${DAILY_MATRIX_SIZE})]" + size=${DAILY_MATRIX_SIZE} + else + size=0 + fi + + echo "subset=${subset}" >> $GITHUB_OUTPUT + echo "size=${size}" >> $GITHUB_OUTPUT + echo "fullrun=${TWISTER_FULL}" >> $GITHUB_OUTPUT diff --git a/.github/workflows/twister-publish.yaml b/.github/workflows/twister-publish.yaml new file mode 100644 index 00000000000..3695d060726 --- /dev/null +++ b/.github/workflows/twister-publish.yaml @@ -0,0 +1,53 @@ +name: Publish Twister Test Results + +on: + workflow_run: + workflows: ["Run tests with twister"] + branches: + - main + types: + - completed + +jobs: + upload-to-elasticsearch: + if: | + github.repository == 'zephyrproject-rtos/zephyr' && + github.event.workflow_run.event != 'pull_request_target' + env: + ELASTICSEARCH_KEY: ${{ secrets.ELASTICSEARCH_KEY }} + ELASTICSEARCH_SERVER: "https://elasticsearch.zephyrproject.io:443" + runs-on: ubuntu-22.04 + steps: + # Needed for elasticearch and upload script + - name: Checkout + uses: actions/checkout@v4 + with: + fetch-depth: 0 + persist-credentials: false + + - name: Download Artifacts + id: download-artifacts + uses: dawidd6/action-download-artifact@v6 + with: + path: artifacts + workflow: twister.yml + run_id: ${{ github.event.workflow_run.id }} + if_no_artifact_found: ignore + + - name: Upload to elasticsearch + if: steps.download-artifacts.outputs.found_artifact == 'true' + run: | + pip install elasticsearch + # set run date on upload to get consistent and unified data across the matrix. + run_date=`date --iso-8601=minutes` + if [ "${{github.event.workflow_run.event}}" = "push" ]; then + python3 ./scripts/ci/upload_test_results_es.py -r ${run_date} \ + --run-attempt ${{github.run_attempt}} \ + --run-branch ${{github.ref_name}} \ + --index zephyr-main-ci-push-1 artifacts/*/*/twister.json + elif [ "${{github.event.workflow_run.event}}" = "schedule" ]; then + python3 ./scripts/ci/upload_test_results_es.py -r ${run_date} \ + --run-attempt ${{github.run_attempt}} \ + --run-branch ${{github.ref_name}} \ + --index zephyr-main-ci-weekly-1 artifacts/*/*/twister.json + fi diff --git a/.github/workflows/twister.yaml b/.github/workflows/twister.yaml index cc3c9e3ffdf..8d3b29fa433 100644 --- a/.github/workflows/twister.yaml +++ b/.github/workflows/twister.yaml @@ -21,107 +21,7 @@ concurrency: jobs: twister-build-prep: - if: github.repository_owner == 'zephyrproject-rtos' - runs-on: - group: zephyr-runner-v2-linux-x64-4xlarge - container: - image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.26.14.20240823 - options: '--entrypoint /bin/bash' - outputs: - subset: ${{ steps.output-services.outputs.subset }} - size: ${{ steps.output-services.outputs.size }} - fullrun: ${{ steps.output-services.outputs.fullrun }} - env: - MATRIX_SIZE: 10 - PUSH_MATRIX_SIZE: 20 - DAILY_MATRIX_SIZE: 80 - BSIM_OUT_PATH: /opt/bsim/ - BSIM_COMPONENTS_PATH: /opt/bsim/components - TESTS_PER_BUILDER: 700 - COMMIT_RANGE: ${{ github.event.pull_request.base.sha }}..${{ github.event.pull_request.head.sha }} - BASE_REF: ${{ github.base_ref }} - steps: - - name: Apply container owner mismatch workaround - run: | - # FIXME: The owner UID of the GITHUB_WORKSPACE directory may not - # match the container user UID because of the way GitHub - # Actions runner is implemented. Remove this workaround when - # GitHub comes up with a fundamental fix for this problem. - git config --global --add safe.directory ${GITHUB_WORKSPACE} - - - name: Print cloud service information - run: | - echo "ZEPHYR_RUNNER_CLOUD_PROVIDER = ${ZEPHYR_RUNNER_CLOUD_PROVIDER}" - echo "ZEPHYR_RUNNER_CLOUD_NODE = ${ZEPHYR_RUNNER_CLOUD_NODE}" - echo "ZEPHYR_RUNNER_CLOUD_POD = ${ZEPHYR_RUNNER_CLOUD_POD}" - - - name: Clone cached Zephyr repository - if: github.event_name == 'pull_request_target' - continue-on-error: true - run: | - git clone --shared /repo-cache/zephyrproject/zephyr . - git remote set-url origin ${GITHUB_SERVER_URL}/${GITHUB_REPOSITORY} - - - name: Checkout - if: github.event_name == 'pull_request_target' - uses: actions/checkout@v4 - with: - ref: ${{ github.event.pull_request.head.sha }} - fetch-depth: 0 - persist-credentials: false - - - name: Environment Setup - if: github.event_name == 'pull_request_target' - run: | - git config --global user.email "bot@zephyrproject.org" - git config --global user.name "Zephyr Bot" - rm -fr ".git/rebase-apply" - git rebase origin/${BASE_REF} - git log --pretty=oneline | head -n 10 - west init -l . || true - west config manifest.group-filter -- +ci,+optional - west config --global update.narrow true - west update --path-cache /repo-cache/zephyrproject 2>&1 1> west.update.log || west update --path-cache /repo-cache/zephyrproject 2>&1 1> west.update.log || ( rm -rf ../modules ../bootloader ../tools && west update --path-cache /repo-cache/zephyrproject) - west forall -c 'git reset --hard HEAD' - - echo "ZEPHYR_SDK_INSTALL_DIR=/opt/toolchains/zephyr-sdk-$( cat SDK_VERSION )" >> $GITHUB_ENV - - - name: Generate Test Plan with Twister - if: github.event_name == 'pull_request_target' - id: test-plan - run: | - export ZEPHYR_BASE=${PWD} - export ZEPHYR_TOOLCHAIN_VARIANT=zephyr - python3 ./scripts/ci/test_plan.py -c origin/${BASE_REF}.. --pull-request -t $TESTS_PER_BUILDER - if [ -s .testplan ]; then - cat .testplan >> $GITHUB_ENV - else - echo "TWISTER_NODES=${MATRIX_SIZE}" >> $GITHUB_ENV - fi - rm -f testplan.json .testplan - - - name: Determine matrix size - id: output-services - run: | - if [ "${{github.event_name}}" = "pull_request_target" ]; then - if [ -n "${TWISTER_NODES}" ]; then - subset="[$(seq -s',' 1 ${TWISTER_NODES})]" - else - subset="[$(seq -s',' 1 ${MATRIX_SIZE})]" - fi - size=${TWISTER_NODES} - elif [ "${{github.event_name}}" = "push" ]; then - subset="[$(seq -s',' 1 ${PUSH_MATRIX_SIZE})]" - size=${MATRIX_SIZE} - elif [ "${{github.event_name}}" = "schedule" -a "${{github.repository}}" = "zephyrproject-rtos/zephyr" ]; then - subset="[$(seq -s',' 1 ${DAILY_MATRIX_SIZE})]" - size=${DAILY_MATRIX_SIZE} - else - size=0 - fi - echo "subset=${subset}" >> $GITHUB_OUTPUT - echo "size=${size}" >> $GITHUB_OUTPUT - echo "fullrun=${TWISTER_FULL}" >> $GITHUB_OUTPUT + uses: ./.github/workflows/twister-prep.yaml twister-build: runs-on: @@ -129,7 +29,7 @@ jobs: needs: twister-build-prep if: needs.twister-build-prep.outputs.size != 0 container: - image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.26.14.20240823 + image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.27.4.20241026 options: '--entrypoint /bin/bash' strategy: fail-fast: false @@ -141,15 +41,16 @@ jobs: CCACHE_REMOTE_STORAGE: "redis://cache-*.keydb-cache.svc.cluster.local|shards=1,2,3" CCACHE_REMOTE_ONLY: "true" # `--specs` is ignored because ccache is unable to resolve the toolchain specs file path. - CCACHE_IGNOREOPTIONS: '--specs=*' + CCACHE_IGNOREOPTIONS: '-specs=* --specs=*' BSIM_OUT_PATH: /opt/bsim/ BSIM_COMPONENTS_PATH: /opt/bsim/components - TWISTER_COMMON: ' --force-color --inline-logs -v -N -M --retry-failed 3 --timeout-multiplier 2 ' - DAILY_OPTIONS: ' -M --build-only --all --show-footprint' + TWISTER_COMMON: '--no-detailed-test-id --force-color --inline-logs -v -N -M --retry-failed 3 --timeout-multiplier 2 ' + WEEKLY_OPTIONS: ' -M --build-only --all --show-footprint --report-filtered' PR_OPTIONS: ' --clobber-output --integration' - PUSH_OPTIONS: ' --clobber-output -M --show-footprint' + PUSH_OPTIONS: ' --clobber-output -M --show-footprint --report-filtered' COMMIT_RANGE: ${{ github.event.pull_request.base.sha }}..${{ github.event.pull_request.head.sha }} BASE_REF: ${{ github.base_ref }} + LLVM_TOOLCHAIN_PATH: /usr/lib/llvm-16 steps: - name: Print cloud service information run: | @@ -184,10 +85,13 @@ jobs: git config --global user.email "bot@zephyrproject.org" git config --global user.name "Zephyr Builder" rm -fr ".git/rebase-apply" + rm -fr ".git/rebase-merge" git rebase origin/${BASE_REF} + git clean -f -d git log --pretty=oneline | head -n 10 fi echo "$HOME/.local/bin" >> $GITHUB_PATH + echo "$HOME/.cargo/bin" >> $GITHUB_PATH west init -l . || true west config manifest.group-filter -- +ci,+optional @@ -201,6 +105,8 @@ jobs: run: | cmake --version gcc --version + cargo --version + rustup target list --installed ls -la echo "github.ref: ${{ github.ref }}" echo "github.base_ref: ${{ github.base_ref }}" @@ -225,6 +131,7 @@ jobs: - if: github.event_name == 'push' name: Run Tests with Twister (Push) + id: run_twister run: | export ZEPHYR_BASE=${PWD} export ZEPHYR_TOOLCHAIN_VARIANT=zephyr @@ -238,11 +145,12 @@ jobs: - if: github.event_name == 'pull_request_target' name: Run Tests with Twister (Pull Request) + id: run_twister_pr run: | rm -f testplan.json export ZEPHYR_BASE=${PWD} export ZEPHYR_TOOLCHAIN_VARIANT=zephyr - python3 ./scripts/ci/test_plan.py -c origin/${BASE_REF}.. --pull-request + python3 ./scripts/ci/test_plan.py -c origin/${BASE_REF}.. --pull-request --no-detailed-test-id ./scripts/twister --subset ${{matrix.subset}}/${{ strategy.job-total }} --load-tests testplan.json ${TWISTER_COMMON} ${PR_OPTIONS} if [ "${{matrix.subset}}" = "1" -a ${{needs.twister-build-prep.outputs.fullrun}} = 'True' ]; then ./scripts/zephyr_module.py --twister-out module_tests.args @@ -253,14 +161,15 @@ jobs: - if: github.event_name == 'schedule' name: Run Tests with Twister (Daily) + id: run_twister_sched run: | export ZEPHYR_BASE=${PWD} export ZEPHYR_TOOLCHAIN_VARIANT=zephyr - ./scripts/twister --subset ${{matrix.subset}}/${{ strategy.job-total }} ${TWISTER_COMMON} ${DAILY_OPTIONS} + ./scripts/twister --subset ${{matrix.subset}}/${{ strategy.job-total }} ${TWISTER_COMMON} ${WEEKLY_OPTIONS} if [ "${{matrix.subset}}" = "1" ]; then ./scripts/zephyr_module.py --twister-out module_tests.args if [ -s module_tests.args ]; then - ./scripts/twister +module_tests.args --outdir module_tests ${TWISTER_COMMON} ${DAILY_OPTIONS} + ./scripts/twister +module_tests.args --outdir module_tests ${TWISTER_COMMON} ${WEEKLY_OPTIONS} fi fi @@ -289,7 +198,7 @@ jobs: timestamp="$(date)" version="$(git describe --abbrev=12 --always)" echo -e "# Generated at $timestamp ($version)\n" > $FREEZE_FILE - pip3 freeze | tee -a $FREEZE_FILE + pip freeze | tee -a $FREEZE_FILE - if: matrix.subset == 1 && github.event_name == 'push' name: Upload the list of Python packages @@ -301,45 +210,21 @@ jobs: twister-test-results: name: "Publish Unit Tests Results" - env: - ELASTICSEARCH_KEY: ${{ secrets.ELASTICSEARCH_KEY }} - ELASTICSEARCH_SERVER: "https://elasticsearch.zephyrproject.io:443" - needs: twister-build + needs: + - twister-build runs-on: ubuntu-22.04 # the build-and-test job might be skipped, we don't need to run this job then if: success() || failure() steps: - # Needed for elasticearch and upload script - - if: github.event_name == 'push' || github.event_name == 'schedule' - name: Checkout - uses: actions/checkout@v4 - with: - fetch-depth: 0 - persist-credentials: false - - name: Download Artifacts uses: actions/download-artifact@v4 with: path: artifacts - - if: github.event_name == 'push' || github.event_name == 'schedule' - name: Upload to elasticsearch - run: | - pip3 install elasticsearch - # set run date on upload to get consistent and unified data across the matrix. - run_date=`date --iso-8601=minutes` - if [ "${{github.event_name}}" = "push" ]; then - python3 ./scripts/ci/upload_test_results_es.py -r ${run_date} \ - --index zephyr-main-ci-push-1 artifacts/*/*/twister.json - elif [ "${{github.event_name}}" = "schedule" ]; then - python3 ./scripts/ci/upload_test_results_es.py -r ${run_date} \ - --index zephyr-main-ci-weekly-1 artifacts/*/*/twister.json - fi - - name: Merge Test Results run: | - pip3 install junitparser junit2html + pip install junitparser junit2html junitparser merge artifacts/*/*/twister.xml junit.xml junit2html junit.xml junit.html diff --git a/.github/workflows/twister_tests.yml b/.github/workflows/twister_tests.yml index fa6737badb8..66409bce876 100644 --- a/.github/workflows/twister_tests.yml +++ b/.github/workflows/twister_tests.yml @@ -32,7 +32,7 @@ jobs: runs-on: ${{ matrix.os }} strategy: matrix: - python-version: ['3.10', '3.11', '3.12'] + python-version: ['3.10', '3.11', '3.12', '3.13'] os: [ubuntu-22.04] steps: - name: checkout @@ -51,7 +51,7 @@ jobs: ${{ runner.os }}-pip-${{ matrix.python-version }} - name: install-packages run: | - pip3 install -r scripts/requirements-base.txt -r scripts/requirements-build-test.txt -r scripts/requirements-run-test.txt + pip install -r scripts/requirements-base.txt -r scripts/requirements-build-test.txt -r scripts/requirements-run-test.txt - name: Run pytest for twisterlib env: ZEPHYR_BASE: ./ diff --git a/.github/workflows/twister_tests_blackbox.yml b/.github/workflows/twister_tests_blackbox.yml index b19bce0c535..cd24a2a39ae 100644 --- a/.github/workflows/twister_tests_blackbox.yml +++ b/.github/workflows/twister_tests_blackbox.yml @@ -21,10 +21,10 @@ jobs: runs-on: ${{ matrix.os }} strategy: matrix: - python-version: ['3.10', '3.11', '3.12'] + python-version: ['3.10', '3.11', '3.12', '3.13'] os: [ubuntu-22.04] container: - image: ghcr.io/zephyrproject-rtos/ci:v0.26.13 + image: ghcr.io/zephyrproject-rtos/ci:v0.27.4 steps: - name: Apply Container Owner Mismatch Workaround diff --git a/.github/workflows/west_cmds.yml b/.github/workflows/west_cmds.yml index d910bf15a29..3d4802f0170 100644 --- a/.github/workflows/west_cmds.yml +++ b/.github/workflows/west_cmds.yml @@ -29,7 +29,7 @@ jobs: runs-on: ${{ matrix.os }} strategy: matrix: - python-version: ['3.10', '3.11', '3.12'] + python-version: ['3.10', '3.11', '3.12', '3.13'] os: [ubuntu-22.04, macos-14, windows-2022] steps: - name: checkout @@ -65,8 +65,7 @@ jobs: ${{ runner.os }}-pip-${{ matrix.python-version }} - name: install pytest run: | - pip3 install wheel - pip3 install pytest west pyelftools canopen natsort progress mypy intelhex psutil ply pyserial + pip install pytest west pyelftools canopen natsort progress mypy intelhex psutil ply pyserial anytree - name: run pytest-win if: runner.os == 'Windows' run: | diff --git a/.gitignore b/.gitignore index 266b95a424a..b545443db31 100644 --- a/.gitignore +++ b/.gitignore @@ -59,6 +59,17 @@ venv .clangd new.info +# Cargo drops lock files in projects to capture resolved dependencies. +# We don't want to record these. +Cargo.lock + +# Cargo encourages a .cargo/config.toml file to symlink to a generated file. Don't save these. +.cargo/ + +# Normal west builds will place the Rust target directory under the build directory. However, +# sometimes IDEs and such will litter these target directories as well. +target/ + # CI output compliance.xml _error.types @@ -91,5 +102,7 @@ MaintainersFormat.txt ModulesMaintainers.txt Nits.txt Pylint.txt +Ruff.txt SphinxLint.txt +TextEncoding.txt YAMLLint.txt diff --git a/.ruff-excludes.toml b/.ruff-excludes.toml new file mode 100644 index 00000000000..ac26af8b3c8 --- /dev/null +++ b/.ruff-excludes.toml @@ -0,0 +1,1796 @@ +# SPDX-License-Identifier: Apache-2.0 + +# This list is generated, it contains all python scripts that existed before ruff was introduced, +# remove entries for files that pass CI compliance testing. + +[lint.per-file-ignores] +"./arch/x86/gen_gdt.py" = [ + "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports + "UP031", # https://docs.astral.sh/ruff/rules/printf-string-formatting +] +"./arch/x86/gen_idt.py" = [ + "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports + "UP030", # https://docs.astral.sh/ruff/rules/format-literals + "UP031", # https://docs.astral.sh/ruff/rules/printf-string-formatting +] +"./arch/x86/gen_mmu.py" = [ + "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports + "UP031", # https://docs.astral.sh/ruff/rules/printf-string-formatting + "UP034", # https://docs.astral.sh/ruff/rules/extraneous-parentheses + "UP039", # https://docs.astral.sh/ruff/rules/unnecessary-class-parentheses +] +"./arch/x86/zefi/zefi.py" = [ + "E501", # https://docs.astral.sh/ruff/rules/line-too-long + "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports + "SIM115", # https://docs.astral.sh/ruff/rules/open-file-with-context-handler + "UP031", # https://docs.astral.sh/ruff/rules/printf-string-formatting +] +"./arch/xtensa/core/gen_vectors.py" = [ + "F541", # https://docs.astral.sh/ruff/rules/f-string-missing-placeholders + "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports + "UP031", # https://docs.astral.sh/ruff/rules/printf-string-formatting +] +"./arch/xtensa/core/gen_zsr.py" = [ + "SIM401", # https://docs.astral.sh/ruff/rules/if-else-block-instead-of-dict-get +] +"./arch/xtensa/core/xtensa_intgen.py" = [ + "E713", # https://docs.astral.sh/ruff/rules/not-in-test + "E741", # https://docs.astral.sh/ruff/rules/ambiguous-variable-name + "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports + "SIM115", # https://docs.astral.sh/ruff/rules/open-file-with-context-handler + "UP031", # https://docs.astral.sh/ruff/rules/printf-string-formatting +] +"./boards/microchip/mec172xevb_assy6906/support/mec172x_remote_flasher.py" = [ + "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports +] +"./doc/_scripts/redirects.py" = [ + "E501", # https://docs.astral.sh/ruff/rules/line-too-long +] +"./modules/mbedtls/create_psa_files.py" = [ + "E101", # https://docs.astral.sh/ruff/rules/mixed-spaces-and-tabs + "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports + "UP006", # https://docs.astral.sh/ruff/rules/non-pep585-annotation + "UP015", # https://docs.astral.sh/ruff/rules/redundant-open-modes + "UP032", # https://docs.astral.sh/ruff/rules/f-string + "UP035", # https://docs.astral.sh/ruff/rules/deprecated-import +] +"./samples/modules/tflite-micro/magic_wand/train/data_augmentation.py" = [ + "B007", # https://docs.astral.sh/ruff/rules/unused-loop-control-variable + "B905", # https://docs.astral.sh/ruff/rules/zip-without-explicit-strict + "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports + "UP010", # https://docs.astral.sh/ruff/rules/unnecessary-future-import +] +"./samples/modules/tflite-micro/magic_wand/train/data_augmentation_test.py" = [ + "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports + "UP010", # https://docs.astral.sh/ruff/rules/unnecessary-future-import +] +"./samples/modules/tflite-micro/magic_wand/train/data_load.py" = [ + "B007", # https://docs.astral.sh/ruff/rules/unused-loop-control-variable + "B020", # https://docs.astral.sh/ruff/rules/loop-variable-overrides-iterator + "B905", # https://docs.astral.sh/ruff/rules/zip-without-explicit-strict + "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports + "UP004", # https://docs.astral.sh/ruff/rules/useless-object-inheritance + "UP010", # https://docs.astral.sh/ruff/rules/unnecessary-future-import + "UP015", # https://docs.astral.sh/ruff/rules/redundant-open-modes +] +"./samples/modules/tflite-micro/magic_wand/train/data_load_test.py" = [ + "B007", # https://docs.astral.sh/ruff/rules/unused-loop-control-variable + "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports + "UP010", # https://docs.astral.sh/ruff/rules/unnecessary-future-import +] +"./samples/modules/tflite-micro/magic_wand/train/data_prepare.py" = [ + "B007", # https://docs.astral.sh/ruff/rules/unused-loop-control-variable + "E501", # https://docs.astral.sh/ruff/rules/line-too-long + "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports + "UP009", # https://docs.astral.sh/ruff/rules/utf8-encoding-declaration + "UP010", # https://docs.astral.sh/ruff/rules/unnecessary-future-import + "UP015", # https://docs.astral.sh/ruff/rules/redundant-open-modes + "UP031", # https://docs.astral.sh/ruff/rules/printf-string-formatting +] +"./samples/modules/tflite-micro/magic_wand/train/data_prepare_test.py" = [ + "B007", # https://docs.astral.sh/ruff/rules/unused-loop-control-variable + "F821", # https://docs.astral.sh/ruff/rules/undefined-name + "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports + "UP010", # https://docs.astral.sh/ruff/rules/unnecessary-future-import + "UP015", # https://docs.astral.sh/ruff/rules/redundant-open-modes + "UP031", # https://docs.astral.sh/ruff/rules/printf-string-formatting +] +"./samples/modules/tflite-micro/magic_wand/train/data_split.py" = [ + "B007", # https://docs.astral.sh/ruff/rules/unused-loop-control-variable + "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports + "UP009", # https://docs.astral.sh/ruff/rules/utf8-encoding-declaration + "UP010", # https://docs.astral.sh/ruff/rules/unnecessary-future-import + "UP015", # https://docs.astral.sh/ruff/rules/redundant-open-modes +] +"./samples/modules/tflite-micro/magic_wand/train/data_split_person.py" = [ + "B007", # https://docs.astral.sh/ruff/rules/unused-loop-control-variable + "E501", # https://docs.astral.sh/ruff/rules/line-too-long + "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports + "UP009", # https://docs.astral.sh/ruff/rules/utf8-encoding-declaration + "UP010", # https://docs.astral.sh/ruff/rules/unnecessary-future-import +] +"./samples/modules/tflite-micro/magic_wand/train/data_split_person_test.py" = [ + "E501", # https://docs.astral.sh/ruff/rules/line-too-long + "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports + "UP010", # https://docs.astral.sh/ruff/rules/unnecessary-future-import +] +"./samples/modules/tflite-micro/magic_wand/train/data_split_test.py" = [ + "B007", # https://docs.astral.sh/ruff/rules/unused-loop-control-variable + "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports + "UP010", # https://docs.astral.sh/ruff/rules/unnecessary-future-import + "UP015", # https://docs.astral.sh/ruff/rules/redundant-open-modes +] +"./samples/modules/tflite-micro/magic_wand/train/train.py" = [ + "B007", # https://docs.astral.sh/ruff/rules/unused-loop-control-variable + "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports + "SIM113", # https://docs.astral.sh/ruff/rules/enumerate-for-loop + "SIM115", # https://docs.astral.sh/ruff/rules/open-file-with-context-handler + "UP010", # https://docs.astral.sh/ruff/rules/unnecessary-future-import + "UP031", # https://docs.astral.sh/ruff/rules/printf-string-formatting + "UP032", # https://docs.astral.sh/ruff/rules/f-string +] +"./samples/modules/tflite-micro/magic_wand/train/train_test.py" = [ + "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports + "UP010", # https://docs.astral.sh/ruff/rules/unnecessary-future-import +] +"./samples/net/cellular_modem/server/te_udp_echo.py" = [ + "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports + "UP039", # https://docs.astral.sh/ruff/rules/unnecessary-class-parentheses +] +"./samples/net/cellular_modem/server/te_udp_receive.py" = [ + "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports + "UP039", # https://docs.astral.sh/ruff/rules/unnecessary-class-parentheses +] +"./samples/sensor/sensor_shell/pytest/test_sensor_shell.py" = [ + "E501", # https://docs.astral.sh/ruff/rules/line-too-long +] +"./samples/subsys/testsuite/pytest/basic/pytest/test_sample.py" = [ + "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports + "SIM112", # https://docs.astral.sh/ruff/rules/uncapitalized-environment-variables +] +"./scripts/build/check_init_priorities.py" = [ + "E501", # https://docs.astral.sh/ruff/rules/line-too-long + "F401", # https://docs.astral.sh/ruff/rules/unused-import + "F541", # https://docs.astral.sh/ruff/rules/f-string-missing-placeholders + "SIM115", # https://docs.astral.sh/ruff/rules/open-file-with-context-handler + "UP031", # https://docs.astral.sh/ruff/rules/printf-string-formatting + "UP039", # https://docs.astral.sh/ruff/rules/unnecessary-class-parentheses +] +"./scripts/build/check_init_priorities_test.py" = [ + "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports + "UP026", # https://docs.astral.sh/ruff/rules/deprecated-mock-import +] +"./scripts/build/elf_parser.py" = [ + "E501", # https://docs.astral.sh/ruff/rules/line-too-long + "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports + "SIM115", # https://docs.astral.sh/ruff/rules/open-file-with-context-handler + "UP032", # https://docs.astral.sh/ruff/rules/f-string +] +"./scripts/build/file2hex.py" = [ + "B023", # https://docs.astral.sh/ruff/rules/function-uses-loop-variable + "B905", # https://docs.astral.sh/ruff/rules/zip-without-explicit-strict +] +"./scripts/build/gen_app_partitions.py" = [ + "E501", # https://docs.astral.sh/ruff/rules/line-too-long + "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports + "UP030", # https://docs.astral.sh/ruff/rules/format-literals + "UP032", # https://docs.astral.sh/ruff/rules/f-string +] +"./scripts/build/gen_cfb_font_header.py" = [ + "E101", # https://docs.astral.sh/ruff/rules/mixed-spaces-and-tabs + "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports + "UP032", # https://docs.astral.sh/ruff/rules/f-string +] +"./scripts/build/gen_device_deps.py" = [ + "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports + "UP032", # https://docs.astral.sh/ruff/rules/f-string +] +"./scripts/build/gen_image_info.py" = [ + "F541", # https://docs.astral.sh/ruff/rules/f-string-missing-placeholders + "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports + "SIM115", # https://docs.astral.sh/ruff/rules/open-file-with-context-handler +] +"./scripts/build/gen_isr_tables.py" = [ + "E501", # https://docs.astral.sh/ruff/rules/line-too-long + "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports + "UP032", # https://docs.astral.sh/ruff/rules/f-string +] +"./scripts/build/gen_isr_tables_parser_carrays.py" = [ + "E501", # https://docs.astral.sh/ruff/rules/line-too-long + "F541", # https://docs.astral.sh/ruff/rules/f-string-missing-placeholders + "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports + "UP030", # https://docs.astral.sh/ruff/rules/format-literals + "UP031", # https://docs.astral.sh/ruff/rules/printf-string-formatting + "UP032", # https://docs.astral.sh/ruff/rules/f-string +] +"./scripts/build/gen_isr_tables_parser_local.py" = [ + "E501", # https://docs.astral.sh/ruff/rules/line-too-long + "F541", # https://docs.astral.sh/ruff/rules/f-string-missing-placeholders + "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports + "UP030", # https://docs.astral.sh/ruff/rules/format-literals + "UP031", # https://docs.astral.sh/ruff/rules/printf-string-formatting + "UP032", # https://docs.astral.sh/ruff/rules/f-string +] +"./scripts/build/gen_kobject_list.py" = [ + "E101", # https://docs.astral.sh/ruff/rules/mixed-spaces-and-tabs + "E501", # https://docs.astral.sh/ruff/rules/line-too-long + "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports + "SIM102", # https://docs.astral.sh/ruff/rules/collapsible-if + "SIM115", # https://docs.astral.sh/ruff/rules/open-file-with-context-handler + "SIM401", # https://docs.astral.sh/ruff/rules/if-else-block-instead-of-dict-get + "UP015", # https://docs.astral.sh/ruff/rules/redundant-open-modes + "UP031", # https://docs.astral.sh/ruff/rules/printf-string-formatting + "UP032", # https://docs.astral.sh/ruff/rules/f-string + "W191", # https://docs.astral.sh/ruff/rules/tab-indentation +] +"./scripts/build/gen_kobject_placeholders.py" = [ + "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports + "SIM115", # https://docs.astral.sh/ruff/rules/open-file-with-context-handler +] +"./scripts/build/gen_offset_header.py" = [ + "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports + "SIM115", # https://docs.astral.sh/ruff/rules/open-file-with-context-handler + "UP031", # https://docs.astral.sh/ruff/rules/printf-string-formatting +] +"./scripts/build/gen_relocate_app.py" = [ + "B028", # https://docs.astral.sh/ruff/rules/no-explicit-stacklevel + "E101", # https://docs.astral.sh/ruff/rules/mixed-spaces-and-tabs + "E501", # https://docs.astral.sh/ruff/rules/line-too-long + "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports + "SIM102", # https://docs.astral.sh/ruff/rules/collapsible-if + "SIM401", # https://docs.astral.sh/ruff/rules/if-else-block-instead-of-dict-get + "UP006", # https://docs.astral.sh/ruff/rules/non-pep585-annotation + "UP035", # https://docs.astral.sh/ruff/rules/deprecated-import + "UP037", # https://docs.astral.sh/ruff/rules/quoted-annotation +] +"./scripts/build/gen_strerror_table.py" = [ + "F541", # https://docs.astral.sh/ruff/rules/f-string-missing-placeholders + "SIM105", # https://docs.astral.sh/ruff/rules/suppressible-exception + "UP015", # https://docs.astral.sh/ruff/rules/redundant-open-modes +] +"./scripts/build/gen_strsignal_table.py" = [ + "SIM105", # https://docs.astral.sh/ruff/rules/suppressible-exception + "UP015", # https://docs.astral.sh/ruff/rules/redundant-open-modes +] +"./scripts/build/gen_symtab.py" = [ + "B007", # https://docs.astral.sh/ruff/rules/unused-loop-control-variable + "E501", # https://docs.astral.sh/ruff/rules/line-too-long + "F541", # https://docs.astral.sh/ruff/rules/f-string-missing-placeholders + "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports + "UP031", # https://docs.astral.sh/ruff/rules/printf-string-formatting +] +"./scripts/build/gen_syscalls.py" = [ + "E501", # https://docs.astral.sh/ruff/rules/line-too-long + "E713", # https://docs.astral.sh/ruff/rules/not-in-test + "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports + "UP015", # https://docs.astral.sh/ruff/rules/redundant-open-modes + "UP031", # https://docs.astral.sh/ruff/rules/printf-string-formatting + "UP032", # https://docs.astral.sh/ruff/rules/f-string +] +"./scripts/build/llext_inject_slids.py" = [ + "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports + "SIM113", # https://docs.astral.sh/ruff/rules/enumerate-for-loop + "SIM115", # https://docs.astral.sh/ruff/rules/open-file-with-context-handler + "UP039", # https://docs.astral.sh/ruff/rules/unnecessary-class-parentheses +] +"./scripts/build/llext_prepare_exptab.py" = [ + "E501", # https://docs.astral.sh/ruff/rules/line-too-long + "F541", # https://docs.astral.sh/ruff/rules/f-string-missing-placeholders + "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports + "SIM113", # https://docs.astral.sh/ruff/rules/enumerate-for-loop + "SIM115", # https://docs.astral.sh/ruff/rules/open-file-with-context-handler + "UP039", # https://docs.astral.sh/ruff/rules/unnecessary-class-parentheses +] +"./scripts/build/mergehex.py" = [ + "B904", # https://docs.astral.sh/ruff/rules/raise-without-from-inside-except + "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports + "UP032", # https://docs.astral.sh/ruff/rules/f-string +] +"./scripts/build/parse_syscalls.py" = [ + "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports + "UP015", # https://docs.astral.sh/ruff/rules/redundant-open-modes + "UP031", # https://docs.astral.sh/ruff/rules/printf-string-formatting +] +"./scripts/build/process_gperf.py" = [ + "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports + "UP015", # https://docs.astral.sh/ruff/rules/redundant-open-modes + "UP031", # https://docs.astral.sh/ruff/rules/printf-string-formatting +] +"./scripts/build/subfolder_list.py" = [ + "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports + "UP015", # https://docs.astral.sh/ruff/rules/redundant-open-modes +] +"./scripts/build/uf2conv.py" = [ + "B011", # https://docs.astral.sh/ruff/rules/assert-false + "E501", # https://docs.astral.sh/ruff/rules/line-too-long + "E711", # https://docs.astral.sh/ruff/rules/none-comparison + "E722", # https://docs.astral.sh/ruff/rules/bare-except + "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports + "SIM102", # https://docs.astral.sh/ruff/rules/collapsible-if + "SIM103", # https://docs.astral.sh/ruff/rules/needless-bool + "SIM118", # https://docs.astral.sh/ruff/rules/in-dict-keys + "UP015", # https://docs.astral.sh/ruff/rules/redundant-open-modes + "UP031", # https://docs.astral.sh/ruff/rules/printf-string-formatting + "UP032", # https://docs.astral.sh/ruff/rules/f-string +] +"./scripts/ci/check_compliance.py" = [ + "B904", # https://docs.astral.sh/ruff/rules/raise-without-from-inside-except + "E501", # https://docs.astral.sh/ruff/rules/line-too-long + "E741", # https://docs.astral.sh/ruff/rules/ambiguous-variable-name + "F401", # https://docs.astral.sh/ruff/rules/unused-import + "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports + "SIM112", # https://docs.astral.sh/ruff/rules/uncapitalized-environment-variables + "UP015", # https://docs.astral.sh/ruff/rules/redundant-open-modes +] +"./scripts/ci/coverage/coverage_analysis.py" = [ + "E501", # https://docs.astral.sh/ruff/rules/line-too-long + "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports + "UP015", # https://docs.astral.sh/ruff/rules/redundant-open-modes +] +"./scripts/ci/errno.py" = [ + "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports + "UP015", # https://docs.astral.sh/ruff/rules/redundant-open-modes +] +"./scripts/ci/guideline_check.py" = [ + "E501", # https://docs.astral.sh/ruff/rules/line-too-long + "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports + "UP032", # https://docs.astral.sh/ruff/rules/f-string +] +"./scripts/ci/stats/merged_prs.py" = [ + "E501", # https://docs.astral.sh/ruff/rules/line-too-long + "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports +] +"./scripts/ci/test_plan.py" = [ + "B006", # https://docs.astral.sh/ruff/rules/mutable-argument-default + "E401", # https://docs.astral.sh/ruff/rules/multiple-imports-on-one-line + "E402", # https://docs.astral.sh/ruff/rules/module-import-not-at-top-of-file + "E501", # https://docs.astral.sh/ruff/rules/line-too-long + "F541", # https://docs.astral.sh/ruff/rules/f-string-missing-placeholders + "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports + "SIM102", # https://docs.astral.sh/ruff/rules/collapsible-if + "UP015", # https://docs.astral.sh/ruff/rules/redundant-open-modes + "UP032", # https://docs.astral.sh/ruff/rules/f-string +] +"./scripts/ci/upload_test_results_es.py" = [ + "E501", # https://docs.astral.sh/ruff/rules/line-too-long + "E713", # https://docs.astral.sh/ruff/rules/not-in-test + "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports + "UP015", # https://docs.astral.sh/ruff/rules/redundant-open-modes +] +"./scripts/ci/version_mgr.py" = [ + "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports + 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https://docs.astral.sh/ruff/rules/printf-string-formatting + "UP032", # https://docs.astral.sh/ruff/rules/f-string +] +"./scripts/coredump/coredump_serial_log_parser.py" = [ + "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports + "SIM115", # https://docs.astral.sh/ruff/rules/open-file-with-context-handler + "UP015", # https://docs.astral.sh/ruff/rules/redundant-open-modes +] +"./scripts/coredump/gdbstubs/arch/arm64.py" = [ + "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports + "UP039", # https://docs.astral.sh/ruff/rules/unnecessary-class-parentheses +] +"./scripts/coredump/gdbstubs/arch/arm_cortex_m.py" = [ + "E501", # https://docs.astral.sh/ruff/rules/line-too-long + "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports + "UP039", # https://docs.astral.sh/ruff/rules/unnecessary-class-parentheses +] +"./scripts/coredump/gdbstubs/arch/risc_v.py" = [ + "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports + "UP039", # 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"UP007", # https://docs.astral.sh/ruff/rules/non-pep604-annotation + "UP015", # https://docs.astral.sh/ruff/rules/redundant-open-modes + "UP032", # https://docs.astral.sh/ruff/rules/f-string + "UP035", # https://docs.astral.sh/ruff/rules/deprecated-import + "UP037", # https://docs.astral.sh/ruff/rules/quoted-annotation +] +"./scripts/dts/python-devicetree/src/devicetree/grutils.py" = [ + "E501", # https://docs.astral.sh/ruff/rules/line-too-long + "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports + "UP032", # https://docs.astral.sh/ruff/rules/f-string +] +"./scripts/dts/python-devicetree/tests/test_dtlib.py" = [ + "B011", # https://docs.astral.sh/ruff/rules/assert-false + "B905", # https://docs.astral.sh/ruff/rules/zip-without-explicit-strict + "E101", # https://docs.astral.sh/ruff/rules/mixed-spaces-and-tabs + "E501", # https://docs.astral.sh/ruff/rules/line-too-long + "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports + "SIM115", # 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https://docs.astral.sh/ruff/rules/line-too-long + "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports + "SIM118", # https://docs.astral.sh/ruff/rules/in-dict-keys + "UP015", # https://docs.astral.sh/ruff/rules/redundant-open-modes +] +"./scripts/gen_gcov_files.py" = [ + "SIM105", # https://docs.astral.sh/ruff/rules/suppressible-exception + "UP015", # https://docs.astral.sh/ruff/rules/redundant-open-modes + "UP031", # https://docs.astral.sh/ruff/rules/printf-string-formatting +] +"./scripts/generate_usb_vif/generate_vif.py" = [ + "E501", # https://docs.astral.sh/ruff/rules/line-too-long + "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports + "SIM103", # https://docs.astral.sh/ruff/rules/needless-bool + "UP038", # https://docs.astral.sh/ruff/rules/non-pep604-isinstance +] +"./scripts/get_maintainer.py" = [ + "B904", # https://docs.astral.sh/ruff/rules/raise-without-from-inside-except + "E501", # https://docs.astral.sh/ruff/rules/line-too-long + "I001", # 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https://docs.astral.sh/ruff/rules/undefined-local-with-import-star + "F405", # https://docs.astral.sh/ruff/rules/undefined-local-with-import-star-usage + "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports + "UP024", # https://docs.astral.sh/ruff/rules/os-error-alias + "UP032", # https://docs.astral.sh/ruff/rules/f-string + "UP038", # https://docs.astral.sh/ruff/rules/non-pep604-isinstance +] +"./scripts/kconfig/hardenconfig.py" = [ + "E501", # https://docs.astral.sh/ruff/rules/line-too-long + "UP032", # https://docs.astral.sh/ruff/rules/f-string +] +"./scripts/kconfig/kconfigfunctions.py" = [ + "B011", # https://docs.astral.sh/ruff/rules/assert-false + "SIM114", # https://docs.astral.sh/ruff/rules/if-with-same-arms + "SIM118", # https://docs.astral.sh/ruff/rules/in-dict-keys + "UP032", # https://docs.astral.sh/ruff/rules/f-string +] +"./scripts/kconfig/kconfiglib.py" = [ + "B904", # https://docs.astral.sh/ruff/rules/raise-without-from-inside-except + "E501", # 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https://docs.astral.sh/ruff/rules/zip-without-explicit-strict + "E402", # https://docs.astral.sh/ruff/rules/module-import-not-at-top-of-file + "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports + "SIM105", # https://docs.astral.sh/ruff/rules/suppressible-exception + "UP010", # https://docs.astral.sh/ruff/rules/unnecessary-future-import + "UP024", # https://docs.astral.sh/ruff/rules/os-error-alias + "UP032", # https://docs.astral.sh/ruff/rules/f-string + "UP036", # https://docs.astral.sh/ruff/rules/outdated-version-block + "UP038", # https://docs.astral.sh/ruff/rules/non-pep604-isinstance +] +"./scripts/list_boards.py" = [ + "E731", # https://docs.astral.sh/ruff/rules/lambda-assignment + "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports + "SIM102", # https://docs.astral.sh/ruff/rules/collapsible-if + "UP006", # https://docs.astral.sh/ruff/rules/non-pep585-annotation + "UP007", # https://docs.astral.sh/ruff/rules/non-pep604-annotation + "UP015", # https://docs.astral.sh/ruff/rules/redundant-open-modes + "UP032", # https://docs.astral.sh/ruff/rules/f-string + "UP035", # https://docs.astral.sh/ruff/rules/deprecated-import +] +"./scripts/list_hardware.py" = [ + "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports + "UP006", # https://docs.astral.sh/ruff/rules/non-pep585-annotation + "UP015", # https://docs.astral.sh/ruff/rules/redundant-open-modes + "UP032", # https://docs.astral.sh/ruff/rules/f-string + "UP035", # https://docs.astral.sh/ruff/rules/deprecated-import +] +"./scripts/logging/dictionary/database_gen.py" = [ + "E713", # https://docs.astral.sh/ruff/rules/not-in-test + "E741", # https://docs.astral.sh/ruff/rules/ambiguous-variable-name + "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports + "SIM102", # https://docs.astral.sh/ruff/rules/collapsible-if + "SIM103", # https://docs.astral.sh/ruff/rules/needless-bool + "SIM113", # https://docs.astral.sh/ruff/rules/enumerate-for-loop + "SIM115", # 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https://docs.astral.sh/ruff/rules/line-too-long + "F541", # https://docs.astral.sh/ruff/rules/f-string-missing-placeholders + "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports +] +"./tests/net/lib/lwm2m/interop/pytest/test_bootstrap.py" = [ + "E501", # https://docs.astral.sh/ruff/rules/line-too-long + "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports +] +"./tests/net/lib/lwm2m/interop/pytest/test_lwm2m.py" = [ + "E501", # https://docs.astral.sh/ruff/rules/line-too-long + "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports + "SIM118", # https://docs.astral.sh/ruff/rules/in-dict-keys + "UP018", # https://docs.astral.sh/ruff/rules/native-literals +] +"./tests/net/lib/lwm2m/interop/pytest/test_nosec.py" = [ + "E501", # https://docs.astral.sh/ruff/rules/line-too-long + "I001", # https://docs.astral.sh/ruff/rules/unsorted-imports +] +"./tests/net/lib/lwm2m/interop/pytest/test_portfolio.py" = [ + "E501", # https://docs.astral.sh/ruff/rules/line-too-long + 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"./arch/xtensa/core/gen_vectors.py", + "./arch/xtensa/core/gen_zsr.py", + "./arch/xtensa/core/xtensa_intgen.py", + "./boards/microchip/mec172xevb_assy6906/support/mec172x_remote_flasher.py", + "./doc/_extensions/zephyr/api_overview.py", + "./doc/_extensions/zephyr/application.py", + "./doc/_extensions/zephyr/doxybridge.py", + "./doc/_extensions/zephyr/doxyrunner.py", + "./doc/_extensions/zephyr/doxytooltip/__init__.py", + "./doc/_extensions/zephyr/dtcompatible-role.py", + "./doc/_extensions/zephyr/external_content.py", + "./doc/_extensions/zephyr/gh_utils.py", + "./doc/_extensions/zephyr/html_redirects.py", + "./doc/_extensions/zephyr/kconfig/__init__.py", + "./doc/_extensions/zephyr/link-roles.py", + "./doc/_scripts/gen_boards_catalog.py", + "./doc/_scripts/gen_devicetree_rest.py", + "./doc/_scripts/redirects.py", + "./doc/conf.py", + "./doc/develop/test/twister/sample_blackbox_test.py", + "./modules/mbedtls/create_psa_files.py", + "./samples/boards/nordic/coresight_stm/pytest/test_stm.py", + "./samples/modules/tflite-micro/magic_wand/train/data_augmentation.py", + "./samples/modules/tflite-micro/magic_wand/train/data_augmentation_test.py", + "./samples/modules/tflite-micro/magic_wand/train/data_load.py", + "./samples/modules/tflite-micro/magic_wand/train/data_load_test.py", + "./samples/modules/tflite-micro/magic_wand/train/data_prepare.py", + "./samples/modules/tflite-micro/magic_wand/train/data_prepare_test.py", + "./samples/modules/tflite-micro/magic_wand/train/data_split.py", + "./samples/modules/tflite-micro/magic_wand/train/data_split_person.py", + "./samples/modules/tflite-micro/magic_wand/train/data_split_person_test.py", + "./samples/modules/tflite-micro/magic_wand/train/data_split_test.py", + "./samples/modules/tflite-micro/magic_wand/train/train.py", + "./samples/modules/tflite-micro/magic_wand/train/train_test.py", + "./samples/modules/thrift/hello/client/hello_client.py", + "./samples/net/cellular_modem/server/te_udp_echo.py", + "./samples/net/cellular_modem/server/te_udp_receive.py", + "./samples/net/cloud/aws_iot_mqtt/src/creds/convert_keys.py", + "./samples/sensor/sensor_shell/pytest/test_sensor_shell.py", + "./samples/subsys/profiling/perf/pytest/test_perf.py", + "./samples/subsys/testsuite/pytest/basic/pytest/conftest.py", + "./samples/subsys/testsuite/pytest/basic/pytest/test_sample.py", + "./samples/subsys/zbus/remote_mock/remote_mock.py", + "./scripts/build/check_init_priorities.py", + "./scripts/build/check_init_priorities_test.py", + "./scripts/build/elf_parser.py", + "./scripts/build/file2hex.py", + "./scripts/build/gen_app_partitions.py", + "./scripts/build/gen_cfb_font_header.py", + "./scripts/build/gen_device_deps.py", + "./scripts/build/gen_image_info.py", + "./scripts/build/gen_isr_tables.py", + "./scripts/build/gen_isr_tables_parser_carrays.py", + "./scripts/build/gen_isr_tables_parser_local.py", + "./scripts/build/gen_kobject_list.py", + "./scripts/build/gen_kobject_placeholders.py", + "./scripts/build/gen_offset_header.py", + "./scripts/build/gen_relocate_app.py", + "./scripts/build/gen_strerror_table.py", + "./scripts/build/gen_strsignal_table.py", + "./scripts/build/gen_symtab.py", + "./scripts/build/gen_syscalls.py", + "./scripts/build/llext_inject_slids.py", + "./scripts/build/llext_prepare_exptab.py", + "./scripts/build/mergehex.py", + "./scripts/build/parse_syscalls.py", + "./scripts/build/process_gperf.py", + "./scripts/build/subfolder_list.py", + "./scripts/build/uf2conv.py", + "./scripts/check_maintainers.py", + "./scripts/ci/check_compliance.py", + "./scripts/ci/coverage/coverage_analysis.py", + "./scripts/ci/errno.py", + "./scripts/ci/guideline_check.py", + "./scripts/ci/stats/merged_prs.py", + "./scripts/ci/test_plan.py", + "./scripts/ci/upload_test_results_es.py", + "./scripts/ci/version_mgr.py", + "./scripts/coredump/coredump_gdbserver.py", + "./scripts/coredump/coredump_parser/elf_parser.py", + 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"./scripts/footprint/fpdiff.py", + "./scripts/footprint/pack_as_twister.py", + "./scripts/footprint/track.py", + "./scripts/footprint/upload_data.py", + "./scripts/gen_gcov_files.py", + "./scripts/generate_usb_vif/constants/xml_constants.py", + "./scripts/generate_usb_vif/generate_vif.py", + "./scripts/get_maintainer.py", + "./scripts/github_helpers.py", + "./scripts/gitlint/zephyr_commit_rules.py", + "./scripts/kconfig/guiconfig.py", + "./scripts/kconfig/hardenconfig.py", + "./scripts/kconfig/kconfig.py", + "./scripts/kconfig/kconfigfunctions.py", + "./scripts/kconfig/kconfiglib.py", + "./scripts/kconfig/lint.py", + "./scripts/kconfig/menuconfig.py", + "./scripts/list_boards.py", + "./scripts/list_hardware.py", + "./scripts/list_shields.py", + "./scripts/logging/dictionary/database_gen.py", + "./scripts/logging/dictionary/dictionary_parser/data_types.py", + "./scripts/logging/dictionary/dictionary_parser/log_database.py", + "./scripts/logging/dictionary/dictionary_parser/log_parser.py", + "./scripts/logging/dictionary/dictionary_parser/log_parser_v1.py", + "./scripts/logging/dictionary/dictionary_parser/log_parser_v3.py", + "./scripts/logging/dictionary/dictionary_parser/utils.py", + "./scripts/logging/dictionary/log_parser.py", + "./scripts/logging/dictionary/log_parser_uart.py", + "./scripts/make_bugs_pickle.py", + "./scripts/net/enumerate_http_status.py", + "./scripts/profiling/stackcollapse.py", + "./scripts/pylib/build_helpers/domains.py", + "./scripts/pylib/pytest-twister-harness/src/twister_harness/device/binary_adapter.py", + "./scripts/pylib/pytest-twister-harness/src/twister_harness/device/device_adapter.py", + "./scripts/pylib/pytest-twister-harness/src/twister_harness/device/fifo_handler.py", + "./scripts/pylib/pytest-twister-harness/src/twister_harness/device/hardware_adapter.py", + "./scripts/pylib/pytest-twister-harness/src/twister_harness/device/qemu_adapter.py", + "./scripts/pylib/pytest-twister-harness/src/twister_harness/fixtures.py", + "./scripts/pylib/pytest-twister-harness/src/twister_harness/helpers/mcumgr.py", + "./scripts/pylib/pytest-twister-harness/src/twister_harness/helpers/shell.py", + "./scripts/pylib/pytest-twister-harness/src/twister_harness/plugin.py", + "./scripts/pylib/pytest-twister-harness/src/twister_harness/twister_harness_config.py", + "./scripts/pylib/pytest-twister-harness/tests/conftest.py", + "./scripts/pylib/pytest-twister-harness/tests/device/binary_adapter_test.py", + "./scripts/pylib/pytest-twister-harness/tests/device/hardware_adapter_test.py", + "./scripts/pylib/pytest-twister-harness/tests/device/qemu_adapter_test.py", + "./scripts/pylib/pytest-twister-harness/tests/helpers/shell_test.py", + "./scripts/pylib/pytest-twister-harness/tests/plugin_test.py", + "./scripts/pylib/twister/expr_parser.py", + "./scripts/pylib/twister/scl.py", + "./scripts/pylib/twister/twisterlib/cmakecache.py", + "./scripts/pylib/twister/twisterlib/config_parser.py", + "./scripts/pylib/twister/twisterlib/coverage.py", + "./scripts/pylib/twister/twisterlib/environment.py", + "./scripts/pylib/twister/twisterlib/error.py", + "./scripts/pylib/twister/twisterlib/handlers.py", + "./scripts/pylib/twister/twisterlib/hardwaremap.py", + "./scripts/pylib/twister/twisterlib/harness.py", + "./scripts/pylib/twister/twisterlib/jobserver.py", + "./scripts/pylib/twister/twisterlib/log_helper.py", + "./scripts/pylib/twister/twisterlib/package.py", + "./scripts/pylib/twister/twisterlib/platform.py", + "./scripts/pylib/twister/twisterlib/quarantine.py", + "./scripts/pylib/twister/twisterlib/reports.py", + "./scripts/pylib/twister/twisterlib/runner.py", + "./scripts/pylib/twister/twisterlib/size_calc.py", + "./scripts/pylib/twister/twisterlib/statuses.py", + "./scripts/pylib/twister/twisterlib/testinstance.py", + "./scripts/pylib/twister/twisterlib/testplan.py", + "./scripts/pylib/twister/twisterlib/testsuite.py", + "./scripts/pylib/twister/twisterlib/twister_main.py", + "./scripts/pylint/checkers/argparse-checker.py", + "./scripts/release/bug_bash.py", + "./scripts/release/list_backports.py", + "./scripts/release/list_devicetree_bindings_changes.py", + "./scripts/set_assignees.py", + "./scripts/snippets.py", + "./scripts/support/quartus-flash.py", + "./scripts/tests/twister/conftest.py", + "./scripts/tests/twister/pytest_integration/test_harness_pytest.py", + "./scripts/tests/twister/test_cmakecache.py", + "./scripts/tests/twister/test_config_parser.py", + "./scripts/tests/twister/test_environment.py", + "./scripts/tests/twister/test_errors.py", + "./scripts/tests/twister/test_handlers.py", + "./scripts/tests/twister/test_hardwaremap.py", + "./scripts/tests/twister/test_harness.py", + "./scripts/tests/twister/test_jobserver.py", + "./scripts/tests/twister/test_log_helper.py", + "./scripts/tests/twister/test_platform.py", + "./scripts/tests/twister/test_quarantine.py", + "./scripts/tests/twister/test_runner.py", + "./scripts/tests/twister/test_scl.py", + "./scripts/tests/twister/test_testinstance.py", + "./scripts/tests/twister/test_testplan.py", + "./scripts/tests/twister/test_testsuite.py", + "./scripts/tests/twister/test_twister.py", + "./scripts/tests/twister_blackbox/conftest.py", + "./scripts/tests/twister_blackbox/test_addon.py", + "./scripts/tests/twister_blackbox/test_config.py", + "./scripts/tests/twister_blackbox/test_coverage.py", + "./scripts/tests/twister_blackbox/test_data/tests/pytest/pytest/conftest.py", + "./scripts/tests/twister_blackbox/test_data/tests/pytest/pytest/test_sample.py", + "./scripts/tests/twister_blackbox/test_device.py", + "./scripts/tests/twister_blackbox/test_disable.py", + "./scripts/tests/twister_blackbox/test_error.py", + "./scripts/tests/twister_blackbox/test_filter.py", + "./scripts/tests/twister_blackbox/test_footprint.py", + "./scripts/tests/twister_blackbox/test_hardwaremap.py", + "./scripts/tests/twister_blackbox/test_outfile.py", + "./scripts/tests/twister_blackbox/test_output.py", + "./scripts/tests/twister_blackbox/test_platform.py", + "./scripts/tests/twister_blackbox/test_printouts.py", + "./scripts/tests/twister_blackbox/test_quarantine.py", + "./scripts/tests/twister_blackbox/test_report.py", + "./scripts/tests/twister_blackbox/test_runner.py", + "./scripts/tests/twister_blackbox/test_shuffle.py", + "./scripts/tests/twister_blackbox/test_testlist.py", + "./scripts/tests/twister_blackbox/test_testplan.py", + "./scripts/tests/twister_blackbox/test_tooling.py", + "./scripts/tracing/parse_ctf.py", + "./scripts/tracing/trace_capture_uart.py", + "./scripts/tracing/trace_capture_usb.py", + "./scripts/utils/board_v1_to_v2.py", + "./scripts/utils/convert_guidelines.py", + "./scripts/utils/gen_util_macros.py", + "./scripts/utils/migrate_includes.py", + "./scripts/utils/migrate_mcumgr_kconfigs.py", + "./scripts/utils/migrate_posix_kconfigs.py", + "./scripts/utils/ntc_thermistor_table.py", + "./scripts/utils/pinctrl_nrf_migrate.py", + "./scripts/utils/twister_to_list.py", + "./scripts/west_commands/bindesc.py", + "./scripts/west_commands/blobs.py", + "./scripts/west_commands/boards.py", + "./scripts/west_commands/build.py", + "./scripts/west_commands/build_helpers.py", + "./scripts/west_commands/completion.py", + "./scripts/west_commands/debug.py", + "./scripts/west_commands/export.py", + "./scripts/west_commands/fetchers/__init__.py", + "./scripts/west_commands/fetchers/core.py", + "./scripts/west_commands/fetchers/http.py", + "./scripts/west_commands/flash.py", + "./scripts/west_commands/robot.py", + "./scripts/west_commands/run_common.py", + "./scripts/west_commands/run_tests.py", + "./scripts/west_commands/runners/__init__.py", + "./scripts/west_commands/runners/blackmagicprobe.py", + "./scripts/west_commands/runners/bossac.py", + "./scripts/west_commands/runners/canopen_program.py", + "./scripts/west_commands/runners/core.py", + "./scripts/west_commands/runners/dediprog.py", + "./scripts/west_commands/runners/dfu.py", + "./scripts/west_commands/runners/esp32.py", + "./scripts/west_commands/runners/ezflashcli.py", + "./scripts/west_commands/runners/gd32isp.py", + "./scripts/west_commands/runners/hifive1.py", + "./scripts/west_commands/runners/intel_adsp.py", + "./scripts/west_commands/runners/intel_cyclonev.py", + "./scripts/west_commands/runners/jlink.py", + "./scripts/west_commands/runners/linkserver.py", + "./scripts/west_commands/runners/mdb.py", + "./scripts/west_commands/runners/misc.py", + "./scripts/west_commands/runners/native.py", + "./scripts/west_commands/runners/nios2.py", + "./scripts/west_commands/runners/nrf_common.py", + "./scripts/west_commands/runners/nrfjprog.py", + "./scripts/west_commands/runners/nrfutil.py", + "./scripts/west_commands/runners/nsim.py", + "./scripts/west_commands/runners/nxp_s32dbg.py", + "./scripts/west_commands/runners/openocd.py", + "./scripts/west_commands/runners/probe_rs.py", + "./scripts/west_commands/runners/pyocd.py", + "./scripts/west_commands/runners/qemu.py", + "./scripts/west_commands/runners/renode-robot.py", + "./scripts/west_commands/runners/renode.py", + "./scripts/west_commands/runners/silabs_commander.py", + "./scripts/west_commands/runners/spi_burn.py", + "./scripts/west_commands/runners/stm32cubeprogrammer.py", + "./scripts/west_commands/runners/stm32flash.py", + "./scripts/west_commands/runners/teensy.py", + "./scripts/west_commands/runners/trace32.py", + "./scripts/west_commands/runners/uf2.py", + "./scripts/west_commands/runners/xsdb.py", + "./scripts/west_commands/runners/xtensa.py", + "./scripts/west_commands/sdk.py", + "./scripts/west_commands/shields.py", + "./scripts/west_commands/sign.py", + "./scripts/west_commands/simulate.py", + "./scripts/west_commands/spdx.py", + "./scripts/west_commands/tests/conftest.py", + "./scripts/west_commands/tests/test_blackmagicprobe.py", + "./scripts/west_commands/tests/test_bossac.py", + "./scripts/west_commands/tests/test_build.py", + "./scripts/west_commands/tests/test_canopen_program.py", + "./scripts/west_commands/tests/test_dediprog.py", + "./scripts/west_commands/tests/test_dfu_util.py", + "./scripts/west_commands/tests/test_gd32isp.py", + "./scripts/west_commands/tests/test_imports.py", + "./scripts/west_commands/tests/test_mdb.py", + "./scripts/west_commands/tests/test_nrf.py", + "./scripts/west_commands/tests/test_nxp_s32dbg.py", + "./scripts/west_commands/tests/test_pyocd.py", + "./scripts/west_commands/tests/test_stm32cubeprogrammer.py", + "./scripts/west_commands/tests/test_stm32flash.py", + "./scripts/west_commands/tests/test_twister.py", + "./scripts/west_commands/twister_cmd.py", + "./scripts/west_commands/zcmake.py", + "./scripts/west_commands/zephyr_ext_common.py", + "./scripts/west_commands/zspdx/cmakefileapi.py", + "./scripts/west_commands/zspdx/cmakefileapijson.py", + "./scripts/west_commands/zspdx/licenses.py", + "./scripts/west_commands/zspdx/walker.py", + "./scripts/west_commands/zspdx/writer.py", + "./scripts/zephyr_module.py", + "./soc/aspeed/ast10x0/tools/gen_uart_booting_image.py", + "./soc/intel/intel_adsp/tools/cavstool.py", + "./soc/intel/intel_adsp/tools/cavstool_client.py", + "./soc/intel/intel_adsp/tools/remote-fw-service.py", + "./soc/intel/intel_ish/utils/build_ish_firmware.py", + "./soc/microchip/mec/common/spigen/mec_spi_gen.py", + "./soc/nuvoton/npcm/common/esiost/esiost.py", + "./soc/nuvoton/npcm/common/esiost/esiost_args.py", + "./soc/nuvoton/npcx/common/ecst/ecst.py", + "./soc/nuvoton/npcx/common/ecst/ecst_args.py", + "./soc/silabs/silabs_sim3/sim3u/gen_crossbar_config.py", + "./tests/boot/with_mcumgr/pytest/test_downgrade_prevention.py", + "./tests/boot/with_mcumgr/pytest/test_upgrade.py", + "./tests/boot/with_mcumgr/pytest/west_sign_wrapper.py", + "./tests/drivers/can/host/pytest/can_shell.py", + "./tests/drivers/can/host/pytest/conftest.py", + "./tests/drivers/can/host/pytest/test_can.py", + "./tests/kernel/timer/timer_behavior/pytest/saleae_logic2.py", + "./tests/kernel/timer/timer_behavior/pytest/test_timer.py", + "./tests/misc/check_init_priorities/validate_check_init_priorities_output.py", + "./tests/misc/llext-edk/pytest/test_edk.py", + "./tests/net/lib/lwm2m/interop/pytest/conftest.py", + "./tests/net/lib/lwm2m/interop/pytest/leshan.py", + "./tests/net/lib/lwm2m/interop/pytest/test_blockwise.py", + "./tests/net/lib/lwm2m/interop/pytest/test_bootstrap.py", + "./tests/net/lib/lwm2m/interop/pytest/test_lwm2m.py", + "./tests/net/lib/lwm2m/interop/pytest/test_nosec.py", + "./tests/net/lib/lwm2m/interop/pytest/test_portfolio.py", + "./tests/net/socket/tls_configurations/pytest/test_app_vs_openssl.py", + "./tests/net/socket/udp/generate-c-string.py", + "./tests/subsys/debug/gdbstub/pytest/test_gdbstub.py", + "./tests/subsys/logging/dictionary/pytest/test_logging_dictionary.py", + "./tests/ztest/ztest_param/pytest/test_parameters.py", +] diff --git a/.ruff.toml b/.ruff.toml new file mode 100644 index 00000000000..c9be3b43104 --- /dev/null +++ b/.ruff.toml @@ -0,0 +1,30 @@ +# Copyright (c) 2024 Basalte bv +# SPDX-License-Identifier: Apache-2.0 + +extend = ".ruff-excludes.toml" + +line-length = 100 +target-version = "py310" + +[lint] +select = [ + # zephyr-keep-sorted-start + "B", # flake8-bugbear + "E", # pycodestyle + "F", # pyflakes + "I", # isort + "SIM", # flake8-simplify + "UP", # pyupgrade + "W", # pycodestyle warnings + # zephyr-keep-sorted-stop +] + +ignore = [ + # zephyr-keep-sorted-start + "SIM108", # Allow if-else blocks instead of forcing ternary operator + # zephyr-keep-sorted-stop +] + +[format] +quote-style = "preserve" +line-ending = "lf" diff --git a/CMakeLists.txt b/CMakeLists.txt index 64c0f1f8ef5..5bd9348cb57 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -88,6 +88,7 @@ set(SYSCALL_LIST_H_TARGET syscall_list_h_target) set(DRIVER_VALIDATION_H_TARGET driver_validation_h_target) set(KOBJ_TYPES_H_TARGET kobj_types_h_target) set(PARSE_SYSCALLS_TARGET parse_syscalls_target) +set(DEVICE_API_LD_TARGET device_api_ld_target) define_property(GLOBAL PROPERTY PROPERTY_OUTPUT_FORMAT BRIEF_DOCS " " FULL_DOCS " ") set_property( GLOBAL PROPERTY PROPERTY_OUTPUT_FORMAT elf32-little${ARCH}) # BFD format @@ -152,6 +153,7 @@ zephyr_compile_options($<$:$:$>) + zephyr_compile_options($<$:$>) zephyr_compile_options($<$:$>) zephyr_link_libraries($) endif() @@ -173,6 +175,12 @@ endif() # @Intent: Set compiler flags to detect general stack overflows across all functions if(CONFIG_STACK_CANARIES) zephyr_compile_options($) +elseif(CONFIG_STACK_CANARIES_STRONG) + zephyr_compile_options($) +elseif(CONFIG_STACK_CANARIES_ALL) + zephyr_compile_options($) +elseif(CONFIG_STACK_CANARIES_EXPLICIT) + zephyr_compile_options($) endif() # @Intent: Obtain compiler optimizations flags and store in variables @@ -597,6 +605,8 @@ add_custom_command( COMMAND_EXPAND_LISTS ) add_custom_target(version_h DEPENDS ${PROJECT_BINARY_DIR}/include/generated/zephyr/version.h) +zephyr_get(KERNEL_VERSION_CUSTOMIZATION SYSBUILD LOCAL) +set_property(TARGET version_h PROPERTY KERNEL_VERSION_CUSTOMIZATION ${KERNEL_VERSION_CUSTOMIZATION}) if(EXISTS ${APPLICATION_SOURCE_DIR}/VERSION) add_custom_command( @@ -615,6 +625,8 @@ if(EXISTS ${APPLICATION_SOURCE_DIR}/VERSION) app_version_h DEPENDS ${PROJECT_BINARY_DIR}/include/generated/zephyr/app_version.h) add_dependencies(zephyr_interface app_version_h) + zephyr_get(APP_VERSION_CUSTOMIZATION SYSBUILD LOCAL) + set_property(TARGET app_version_h PROPERTY APP_VERSION_CUSTOMIZATION ${APP_VERSION_CUSTOMIZATION}) endif() # Unfortunately, the order in which CMakeLists.txt code is processed @@ -836,7 +848,12 @@ if(CONFIG_LEGACY_GENERATED_INCLUDE_PATH) ${CMAKE_CURRENT_BINARY_DIR}/include/generated/syscall_list.h) endif() -add_custom_command(OUTPUT include/generated/zephyr/syscall_dispatch.c ${syscall_list_h} +add_custom_command( + OUTPUT + include/generated/zephyr/syscall_dispatch.c + include/generated/zephyr/syscall_exports_llext.c + syscall_weakdefs_llext.c + ${syscall_list_h} # Also, some files are written to include/generated/zephyr/syscalls/ COMMAND ${PYTHON_EXECUTABLE} @@ -844,7 +861,8 @@ add_custom_command(OUTPUT include/generated/zephyr/syscall_dispatch.c ${syscall_ --json-file ${syscalls_json} # Read this file --base-output include/generated/zephyr/syscalls # Write to this dir --syscall-dispatch include/generated/zephyr/syscall_dispatch.c # Write this file - --syscall-export-llext include/generated/zephyr/syscall_export_llext.c + --syscall-exports-llext include/generated/zephyr/syscall_exports_llext.c + --syscall-weakdefs-llext syscall_weakdefs_llext.c # compiled in CMake library 'syscall_weakdefs' --syscall-list ${syscall_list_h} $<$:--gen-mrsh-files> ${SYSCALL_LONG_REGISTERS_ARG} @@ -877,6 +895,37 @@ add_custom_target(${DRIVER_VALIDATION_H_TARGET} DEPENDS ${DRV_VALIDATION}) include(${ZEPHYR_BASE}/cmake/kobj.cmake) gen_kobj(KOBJ_INCLUDE_PATH) +# Generate sections for kernel device subsystems +set( + DEVICE_API_LD_SECTIONS + ${CMAKE_CURRENT_BINARY_DIR}/include/generated/device-api-sections.ld + ) + +set(DEVICE_API_LINKER_SECTIONS_CMAKE + ${CMAKE_CURRENT_BINARY_DIR}/include/generated/device-api-sections.cmake +) + +add_custom_command( + OUTPUT ${DEVICE_API_LD_SECTIONS} ${DEVICE_API_LINKER_SECTIONS_CMAKE} + COMMAND + ${PYTHON_EXECUTABLE} + ${ZEPHYR_BASE}/scripts/build/gen_iter_sections.py + --alignment ${CONFIG_LINKER_ITERABLE_SUBALIGN} + --input ${struct_tags_json} + --tag __subsystem + --ld-output ${DEVICE_API_LD_SECTIONS} + --cmake-output ${DEVICE_API_LINKER_SECTIONS_CMAKE} + DEPENDS + ${ZEPHYR_BASE}/scripts/build/gen_iter_sections.py + ${struct_tags_json} + WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR} + ) + +add_custom_target(${DEVICE_API_LD_TARGET} + DEPENDS ${DEVICE_API_LD_SECTIONS} + ${DEVICE_API_LINKER_SECTIONS_CMAKE} +) + # Add a pseudo-target that is up-to-date when all generated headers # are up-to-date. @@ -907,6 +956,7 @@ add_dependencies(zephyr_interface ${SYSCALL_LIST_H_TARGET} ${DRIVER_VALIDATION_H_TARGET} ${KOBJ_TYPES_H_TARGET} + ${DEVICE_API_LD_TARGET} ) add_custom_command( @@ -971,6 +1021,16 @@ else() set(NO_WHOLE_ARCHIVE_LIBS kernel) endif() +if(CONFIG_LLEXT) + # LLEXT exports symbols for all syscalls, including unimplemented ones. + # Weak definitions for these must be added at the end of the link order + # to avoid shadowing actual implementations. + add_library(syscall_weakdefs syscall_weakdefs_llext.c) + add_dependencies(syscall_weakdefs zephyr_generated_headers) + target_link_libraries(syscall_weakdefs zephyr_interface) + list(APPEND NO_WHOLE_ARCHIVE_LIBS syscall_weakdefs) +endif() + get_property(OUTPUT_FORMAT GLOBAL PROPERTY PROPERTY_OUTPUT_FORMAT) if (CONFIG_CODE_DATA_RELOCATION) @@ -1034,14 +1094,6 @@ if(CONFIG_USERSPACE) set(PROCESS_GPERF ${ZEPHYR_BASE}/scripts/build/process_gperf.py) endif() -get_property(GLOBAL_CSTD GLOBAL PROPERTY CSTD) -if(DEFINED GLOBAL_CSTD) - message(DEPRECATION - "Global CSTD property is deprecated, see Kconfig.zephyr for C Standard options.") - set(CSTD ${GLOBAL_CSTD}) - list(APPEND CMAKE_C_COMPILE_FEATURES ${compile_features_${CSTD}}) -endif() - # @Intent: Obtain compiler specific flag for specifying the c standard zephyr_compile_options( $<$:$${CSTD}> diff --git a/CODEOWNERS b/CODEOWNERS deleted file mode 100644 index 8ba6e3c5b78..00000000000 --- a/CODEOWNERS +++ /dev/null @@ -1,492 +0,0 @@ -# CODEOWNERS for autoreview assigning in github - -# https://help.github.com/en/articles/about-code-owners#codeowners-syntax - -# Order is important; for each modified file, the last matching -# pattern takes the most precedence. -# That is, with the last pattern being -# *.rst @nashif -# if only .rst files are being modified, only nashif is -# automatically requested for review, but you can manually -# add others as needed. - -# Do not use wildcard on all source yet -# -# +++++++++++ NOTE ++++++++++++++++ -# -# Please use the MAINTAINERS file to add yourself in an area or to add a new -# component or code. This file is going to be deprecated and currently only had -# entries that are not covered by the MAINTAINERS file. - -/.github/test-spec.yml @nrfconnect/ncs-test-leads -/soc/arm/aspeed/ @aspeeddylan -/soc/atmel/ @nandojve -/soc/arm/bcm*/ @sbranden -/soc/arm/ene/ @ene-steven -/soc/arm/infineon_cat1/ @ifyall @npal-cy -/soc/arm/infineon_xmc/ @parthitce -/soc/arm/silabs_exx32/efm32pg1b/ @rdmeneze -/soc/arm/silabs_exx32/efr32mg21/ @l-alfred -/soc/arm/st_stm32/stm32mp1/ @arnopo -/soc/arm/st_stm32/stm32h7/*stm32h735* @benediktibk -/soc/arm/st_stm32/stm32l4/*stm32l451* @benediktibk -/soc/arm/ti_simplelink/cc13x2_cc26x2/ @bwitherspoon -/soc/arm/ti_simplelink/cc32xx/ @vanti -/soc/arm/ti_simplelink/msp432p4xx/ @Mani-Sadhasivam -/soc/arm/xilinx_zynq7000/ @ibirnbaum -/soc/arm/xilinx_zynqmp/ @stephanosio -/soc/arm/renesas_rcar/ @aaillet -/soc/riscv/openisa*/ @dleach02 -/soc/riscv/riscv-privileged/andes_v5/ @cwshu @kevinwang821020 @jimmyzhe -/soc/riscv/riscv-privileged/neorv32/ @henrikbrixandersen -/soc/riscv/riscv-privileged/gd32vf103/ @soburi -/soc/starfive/jh71xx/ @pfarwsi -/soc/riscv/riscv-privileged/niosv/ @sweeaun -/boards/adafruit/feather_nrf52840/ @jacobw -/boards/ene/ @ene-steven -/boards/arm/96b_argonkey/ @avisconti -/boards/arm/96b_avenger96/ @Mani-Sadhasivam -/boards/arm/96b_carbon/ @idlethread -/boards/arm/96b_meerkat96/ @Mani-Sadhasivam -/boards/arm/96b_nitrogen/ @idlethread -/boards/arm/96b_neonkey/ @Mani-Sadhasivam -/boards/arm/96b_stm32_sensor_mez/ @Mani-Sadhasivam -/boards/arm/96b_wistrio/ @Mani-Sadhasivam -/boards/arm/acn52832/ @sven-hm -/boards/arm/arduino_mkrzero/ @soburi -/boards/arm/bbc_microbit_v2/ @LingaoM -/boards/arm/blackpill_f401ce/ @coderkalyan -/boards/arm/blackpill_f411ce/ @coderkalyan -/boards/arm/bt*10/ @greg-leach -/boards/arm/cc1352r1_launchxl/ @bwitherspoon -/boards/arm/cc26x2r1_launchxl/ @bwitherspoon -/boards/arm/cc3220sf_launchxl/ @vanti -/boards/arm/cy8ckit_062_ble/ @ifyall @npal-cy -/boards/arm/cy8ckit_062s4/ @DaWei8823 -/boards/arm/cy8ckit_062_wifi_bt/ @ifyall @npal-cy -/boards/arm/cy8cproto_062_4343w/ @ifyall @npal-cy -/boards/arm/efm32pg_stk3401a/ @rdmeneze -/boards/arm/faze/ @mbittan @simonguinot -/boards/arm/frdm*/ @mmahadevan108 @dleach02 -/boards/arm/gd32*/ @nandojve -/boards/arm/google_*/ @jackrosenthal -/boards/arm/hexiwear*/ @mmahadevan108 @dleach02 -/boards/arm/ip_k66f/ @parthitce @lmajewski -/boards/arm/legend/ @mbittan @simonguinot -/boards/arm/lpcxpresso*/ @mmahadevan108 @dleach02 -/boards/arm/mimx8mm_evk/ @Mani-Sadhasivam -/boards/arm/mimx8mm_phyboard_polis @pefech -/boards/arm/mimxrt*/ @mmahadevan108 @dleach02 -/boards/arm/mps2_an385/ @fvincenzo -/boards/arm/msp_exp432p401r_launchxl/ @Mani-Sadhasivam -/boards/arm/npcx7m6fb_evb/ @MulinChao @ChiHuaL -/boards/arm/nrf*/ @carlescufi @lemrey -/boards/arm/nucleo_f401re/ @idlethread -/boards/arm/nuvoton_pfm_m487/ @ssekar15 -/boards/arm/qemu_cortex_a9/ @ibirnbaum -/boards/arm/qemu_cortex_r*/ @stephanosio -/boards/arm/qemu_cortex_m*/ @ioannisg @stephanosio -/boards/arm/quick_feather/ @fkokosinski @kgugala -/boards/arm/rak4631_nrf52840/ @gpaquet85 -/boards/arm/rak5010_nrf52840/ @gpaquet85 -/boards/arm/rpi_pico/ @yonsch -/boards/arm/ronoth_lodev/ @NorthernDean -/boards/arm/xmc45_relax_kit/ @parthitce -/boards/atmel/ @nandojve -/boards/arm/scobc_module1/ @yashi -/boards/arm/v2m_beetle/ @fvincenzo -/boards/arm/olimexino_stm32/ @ydamigos -/boards/arm/s32*/ @manuargue -/boards/arm/sensortile_box/ @avisconti -/boards/arm/steval_fcu001v1/ @Navin-Sankar -/boards/arm/stm32l1_disco/ @karlp -/boards/arm/stm32h735g_disco/ @benediktibk -/boards/arm/stm32f3_disco/ @ydamigos -/boards/arm/rcar_*/ @aaillet -/boards/arm/ubx_bmd345eval_nrf52840/ @Navin-Sankar @brec-u-blox -/boards/arm/nrf5340_audio_dk_nrf5340 @koffes @alexsven @erikrobstad @rick1082 @gWacey -/boards/arm/stm32_min_dev/ @sidcha -/boards/ezurio/* @rerickson1 -/boards/riscv/rv32m1_vega/ @dleach02 -/boards/riscv/adp_xc7k_ae350/ @cwshu @kevinwang821020 @jimmyzhe -/boards/riscv/longan_nano/ @soburi -/boards/riscv/neorv32/ @henrikbrixandersen -/boards/riscv/niosv*/ @sweeaun -/boards/riscv/sparkfun_red_v_things_plus/ @soburi -/boards/riscv/stamp_c3/ @soburi -/boards/starfive/visionfive2/ @kanakshilledar @pfarwsi -/boards/shields/atmel_rf2xx/ @nandojve -/boards/shields/esp_8266/ @nandojve -/boards/shields/inventek_eswifi/ @nandojve -/boards/xtensa/odroid_go/ @ydamigos -/boards/xtensa/nxp_adsp_imx8/ @iuliana-prodan @dbaluta -/boards/xtensa/kincony_kc868_a32/ @bbilas -/boards/arm64/qemu_cortex_a53/ @carlocaione -/boards/arm64/bcm958402m2_a72/ @abhishek-brcm -/boards/arm64/mimx8mm_evk/ @MrVan @JiafeiPan -/boards/arm64/mimx8mp_evk/ @MrVan @JiafeiPan -/boards/arm64/mimx8mn_evk/ @JiafeiPan -/boards/arm64/mimx93_evk/ @JiafeiPan -/boards/arm64/nxp_ls1046ardb/ @JiafeiPan -/boards/arm64/xenvm/ @lorc @firscity -/boards/arm64/fvp_baser_aemv8r/ @povergoing -/boards/arm64/fvp_base_revc_2xaemv8a/ @carlocaione -/boards/arm64/intel_socfpga_agilex_socdk/ @siclim @ngboonkhai -/boards/arm64/intel_socfpga_agilex5_socdk/ @teikheng @gdengi -/boards/arm64/rcar_*/ @lorc @xakep-amatop -# All cmake related files -/doc/develop/tools/coccinelle.rst @himanshujha199640 @JuliaLawall -/doc/services/device_mgmt/smp_protocol.rst @de-nordic @nordicjm -/doc/services/device_mgmt/smp_groups/ @de-nordic @nordicjm -/doc/services/sensing/ @lixuzha @ghu0510 @qianruh -/doc/CMakeLists.txt @carlescufi -/doc/_scripts/ @carlescufi -/drivers/*/*sam4l* @nandojve -/drivers/*/*cc13xx_cc26xx* @bwitherspoon -/drivers/*/*gd32* @nandojve -/drivers/*/*mcux* @mmahadevan108 @dleach02 -/drivers/*/*native_posix* @aescolar @daor-oti -/drivers/*/*lpc11u6x* @mbittan @simonguinot -/drivers/*/*npcx* @MulinChao @ChiHuaL -/drivers/*/*andes* @cwshu @kevinwang821020 @jimmyzhe -/drivers/*/*ifx_cat1* @ifyall @npal-cy -/drivers/*/*neorv32* @henrikbrixandersen -/drivers/*/*_s32* @manuargue -/drivers/adc/adc_ads1x1x.c @XenuIsWatching -/drivers/adc/adc_stm32.c @cybertale -/drivers/adc/adc_rpi_pico.c @soburi -/drivers/adc/*ads114s0x* @benediktibk -/drivers/adc/*max11102_17* @benediktibk -/drivers/adc/*kb1200* @ene-steven -/drivers/adc/adc_ad559x.c @bbilas -/drivers/audio/*nrfx* @anangl -/drivers/auxdisplay/*pt6314* @xingrz -/drivers/auxdisplay/* @thedjnK -/drivers/bbram/* @yperess @sjg20 @jackrosenthal -/drivers/bluetooth/ @alwa-nordic @jhedberg @Vudentz -/drivers/bluetooth/hci/hci_esp32.c @sylvioalves -/drivers/can/*mcp2515* @karstenkoenig -/drivers/can/*rcar* @aaillet -/drivers/clock_control/*agilex* @siclim @gdengi -/drivers/clock_control/*nrf* @nordic-krch -/drivers/clock_control/*esp32* @extremegtx @sylvioalves -/drivers/clock_control/*cpg_mssr* @aaillet -/drivers/console/ipm_console.c @finikorg -/drivers/console/semihost_console.c @luozhongyao -/drivers/console/jailhouse_debug_console.c @MrVan -/drivers/counter/counter_cmos.c @dcpleung -/drivers/counter/counter_ll_stm32_timer.c @kentjhall -/drivers/counter/*esp32* @sylvioalves -/drivers/counter/dw_timer.c @pbalsundar -/drivers/counter/counter_timer_shell.c @pbalsundar -/drivers/crypto/*nrf_ecb* @maciekfabia @anangl -/drivers/display/*rm68200* @mmahadevan108 -/drivers/display/display_ili9342c.* @extremegtx -/drivers/dac/*ad56xx* @benediktibk -/drivers/dac/dac_ad559x.c @bbilas -/drivers/dai/ @kv2019i @marcinszkudlinski @abonislawski -/drivers/dai/intel/ @kv2019i @marcinszkudlinski @abonislawski -/drivers/dai/intel/ssp/ @kv2019i @marcinszkudlinski @abonislawski -/drivers/dai/intel/dmic/ @marcinszkudlinski @abonislawski -/drivers/dai/intel/alh/ @abonislawski -/drivers/dma/dma_dw_axi.c @pbalsundar -/drivers/dma/*dw* @tbursztyka -/drivers/dma/*dw_common* @abonislawski -/drivers/dma/*sam0* @Sizurka -/drivers/dma/dma_stm32* @cybertale @lowlander -/drivers/dma/*pl330* @raveenp -/drivers/dma/*iproc_pax* @raveenp -/drivers/dma/*intel_adsp* @teburd @abonislawski -/drivers/dma/*rpi_pico* @soburi -/drivers/dma/*xmc4xxx* @talih0 -/drivers/eeprom/eeprom_stm32.c @KwonTae-young -/drivers/entropy/*b91* @andy-liu-telink -/drivers/entropy/*bt_hci* @JordanYates -/drivers/entropy/*rv32m1* @dleach02 -/drivers/ethernet/*dwmac* @npitre -/drivers/ethernet/*stm32* @Nukersson @lochej -/drivers/ethernet/*w5500* @parthitce -/drivers/ethernet/*xlnx_gem* @ibirnbaum -/drivers/ethernet/*smsc91x* @sgrrzhf -/drivers/ethernet/*adin2111* @GeorgeCGV -/drivers/ethernet/*oa_tc6* @lmajewski -/drivers/ethernet/*lan865x* @lmajewski -/drivers/ethernet/dwc_xgmac @Smale-12048867 -/drivers/ethernet/dwc_xgmac/dwc_xgmac @Smale-12048867 -/drivers/ethernet/phy/ @rlubos @tbursztyka @arvinf @jukkar -/drivers/ethernet/phy/*adin2111* @GeorgeCGV -/drivers/mdio/*adin2111* @GeorgeCGV -/drivers/flash/*stm32_qspi* @lmajewski -/drivers/flash/*b91* @andy-liu-telink -/drivers/flash/*cadence* @ngboonkhai -/drivers/flash/*cc13xx_cc26xx* @pepe2k -/drivers/flash/*nrf* @de-nordic -/drivers/flash/*esp32* @sylvioalves -/drivers/flash/flash_cadence_nand* @nbalabak -/drivers/gpio/*b91* @andy-liu-telink -/drivers/gpio/*lmp90xxx* @henrikbrixandersen -/drivers/gpio/*nct38xx* @MulinChao @ChiHuaL -/drivers/gpio/*eos_s3* @fkokosinski @kgugala -/drivers/gpio/*rcar* @aaillet -/drivers/gpio/*esp32* @sylvioalves -/drivers/gpio/*rpi_pico* @yonsch -/drivers/gpio/*xlnx_ps* @ibirnbaum -/drivers/gpio/*ads114s0x* @benediktibk -/drivers/gpio/*bd8lb600fs* @benediktibk -/drivers/gpio/*pcal64xxa* @benediktibk -/drivers/gpio/*kb1200* @ene-steven -/drivers/gpio/gpio_altera_pio.c @shilinte -/drivers/gpio/gpio_ad559x.c @bbilas -/drivers/i2c/i2c_common.c @sjg20 -/drivers/i2c/i2c_emul.c @sjg20 -/drivers/i2c/i2c_ite_enhance.c @GTLin08 -/drivers/i2c/i2c_ite_it8xxx2.c @GTLin08 -/drivers/i2c/i2c_shell.c @nashif -/drivers/i2c/Kconfig.i2c_emul @sjg20 -/drivers/i2c/Kconfig.it8xxx2 @GTLin08 -/drivers/i2c/target/*eeprom* @henrikbrixandersen -/drivers/i2c/Kconfig.test @mbolivar-ampere -/drivers/i2c/i2c_test.c @mbolivar-ampere -/drivers/i2c/*rcar* @aaillet -/drivers/i2c/*kb1200* @ene-steven -/drivers/i2s/i2s_ll_stm32* @avisconti -/drivers/i2s/*nrfx* @anangl -/drivers/i3c/i3c_cdns.c @XenuIsWatching -/drivers/ieee802154/ @rlubos @tbursztyka @jukkar @fgrandel -/drivers/ieee802154/*b91* @andy-liu-telink -/drivers/ieee802154/ieee802154_nrf5* @ankuns -/drivers/ieee802154/ieee802154_rf2xx* @tbursztyka @nandojve -/drivers/ieee802154/ieee802154_cc13xx* @bwitherspoon @cfriedt @vaishnavachath -/drivers/interrupt_controller/ @dcpleung @nashif -/drivers/interrupt_controller/intc_gic.c @stephanosio -/drivers/interrupt_controller/*esp32* @sylvioalves -/drivers/interrupt_controller/intc_nuclei_eclic.c @soburi -/drivers/ipm/ipm_mhu* @karl-zh -/drivers/ipm/Kconfig.nrfx @masz-nordic -/drivers/ipm/Kconfig.nrfx_ipc_channel @masz-nordic -/drivers/ipm/ipm_cavs* @dcpleung @andyross -/drivers/ipm/ipm_nrfx_ipc.c @masz-nordic -/drivers/ipm/ipm_nrfx_ipc.h @masz-nordic -/drivers/ipm/ipm_stm32_ipcc.c @arnopo -/drivers/ipm/ipm_stm32_hsem.c @cameled -/drivers/ipm/ipm_esp32.c @uLipe -/drivers/ipm/ipm_ivshmem.c @uLipe -/drivers/kscan/*xec* @franciscomunoz @sjvasanth1 -/drivers/kscan/*ft5336* @MaureenHelm -/drivers/kscan/*ht16k33* @henrikbrixandersen -/drivers/led_strip/ @mbolivar-ampere -/drivers/mfd/mfd_ad559x.c @bbilas -/drivers/mfd/mfd_max20335.c @bbilas -/drivers/misc/ft8xx/ @hubertmis -/drivers/modem/hl7800.c @rerickson1 -/drivers/modem/simcom-sim7080.c @lgehreke -/drivers/modem/simcom-sim7080.h @lgehreke -/drivers/modem/Kconfig.hl7800 @rerickson1 -/drivers/modem/Kconfig.simcom-sim7080 @lgehreke -/drivers/pinctrl/*esp32* @sylvioalves -/drivers/pinctrl/*it8xxx2* @ite -/drivers/pinctrl/*kb1200* @ene-steven -/drivers/pm_cpu_ops/psci_shell.c @nbalabak @gdengi -/drivers/power_domain/ @ceolin -/drivers/ps2/*xec* @franciscomunoz @sjvasanth1 -/drivers/ps2/*npcx* @MulinChao @ChiHuaL -/drivers/pwm/*b91* @andy-liu-telink -/drivers/pwm/*pca9685* @nixward -/drivers/pwm/*rpi_pico* @burumaj -/drivers/pwm/*rv32m1* @henrikbrixandersen -/drivers/pwm/*sam0* @nzmichaelh -/drivers/pwm/*test* @JordanYates -/drivers/pwm/*xlnx* @henrikbrixandersen -/drivers/pwm/pwm_capture.c @henrikbrixandersen -/drivers/pwm/pwm_shell.c @henrikbrixandersen -/drivers/pwm/*gecko* @sun681 -/drivers/pwm/*it8xxx2* @RuibinChang -/drivers/pwm/*esp32* @LucasTambor -/drivers/pwm/*rcar* @aaillet -/drivers/pwm/*max31790* @benediktibk -/drivers/pwm/*kb1200* @ene-steven -/drivers/regulator/* @gmarull -/drivers/regulator/regulator_max20335.c @bbilas -/drivers/regulator/regulator_pca9420.c @danieldegrasse -/drivers/regulator/regulator_rpi_pico.c @soburi -/drivers/regulator/regulator_shell.c @danieldegrasse -/drivers/reset/reset_intel_socfpga.c @nbalabak -/drivers/reset/Kconfig.intel_socfpga @nbalabak -/drivers/sensor/ams_iAQcore/ @alexanderwachter -/drivers/sensor/ens210/ @alexanderwachter -/drivers/sensor/grow_r502a/ @DineshDK03 -/drivers/sensor/hts*/ @avisconti -/drivers/sensor/ina23*/ @bbilas -/drivers/sensor/lis*/ @avisconti -/drivers/sensor/lps*/ @avisconti -/drivers/sensor/lsm*/ @avisconti -/drivers/sensor/mpr/ @sven-hm -/drivers/sensor/qdec_stm32/ @valeriosetti -/drivers/sensor/rpi_pico_temp/ @soburi -/drivers/sensor/st*/ @avisconti -/drivers/sensor/veaa_x_3/ @jeppenodgaard @MaureenHelm -/drivers/sensor/ene_tack_kb1200/ @ene-steven -/drivers/serial/*b91* @andy-liu-telink -/drivers/serial/uart_altera_jtag.c @nashif @gohshunjing -/drivers/serial/uart_altera.c @gohshunjing -/drivers/serial/*ns16550* @dcpleung @nashif @gdengi -/drivers/serial/*nrfx* @anangl -/drivers/serial/Kconfig.mcux_iuart @Mani-Sadhasivam -/drivers/serial/uart_mcux_iuart.c @Mani-Sadhasivam -/drivers/serial/Kconfig.rtt @carlescufi @pkral78 -/drivers/serial/uart_rtt.c @carlescufi @pkral78 -/drivers/serial/*rpi_pico* @yonsch -/drivers/serial/Kconfig.xlnx @wjliang -/drivers/serial/uart_xlnx_ps.c @wjliang -/drivers/serial/uart_xlnx_uartlite.c @henrikbrixandersen -/drivers/serial/*xmc4xxx* @parthitce -/drivers/serial/*numicro* @ssekar15 -/drivers/serial/*apbuart* @julius-barendt -/drivers/serial/*rcar* @aaillet -/drivers/serial/Kconfig.xen @lorc @firscity -/drivers/serial/uart_hvc_xen.c @lorc @firscity -/drivers/serial/uart_hvc_xen_consoleio.c @lorc @firscity -/drivers/serial/Kconfig.it8xxx2 @GTLin08 -/drivers/serial/uart_ite_it8xxx2.c @GTLin08 -/drivers/serial/*intel_lw* @shilinte -/drivers/serial/*kb1200* @ene-steven -/drivers/disk/sdmmc_stm32.c @anthonybrandon -/drivers/ptp_clock/ @tbursztyka @jukkar -/drivers/spi/*b91* @andy-liu-telink -/drivers/spi/spi_rv32m1_lpspi* @karstenkoenig -/drivers/spi/*esp32* @sylvioalves -/drivers/spi/*pl022* @soburi -/drivers/sdhc/ @danieldegrasse -/drivers/sdhc/sdhc_cdns* @roymurlidhar @tanmaykathpalia -/drivers/timer/*arm_arch* @carlocaione -/drivers/timer/*cortex_m_systick* @anangl -/drivers/timer/*altera_avalon* @nashif -/drivers/timer/*riscv_machine* @kgugala @pgielda -/drivers/timer/*ite_it8xxx2* @ite -/drivers/timer/*xlnx_psttc* @wjliang @stephanosio -/drivers/timer/*cc13xx_cc26xx_rtc* @vanti -/drivers/timer/*cavs* @dcpleung -/drivers/timer/*leon_gptimer* @julius-barendt -/drivers/timer/*mips_cp0* @frantony -/drivers/timer/*rcar_cmt* @aaillet -/drivers/timer/*esp32_sys* @uLipe -/drivers/timer/*sam0_rtc* @bendiscz -/drivers/timer/*xtensa* @dcpleung -/drivers/timer/*rv32m1_lptmr* @mbolivar -/drivers/timer/*nrf_rtc* @anangl -/drivers/timer/*hpet* @dcpleung -/drivers/usb/device/usb_dc_stm32.c @ydamigos @loicpoulain -/drivers/i2c/*b91* @andy-liu-telink -/drivers/i2c/i2c_ll_stm32* @ydamigos -/drivers/i2c/i2c_rv32m1_lpi2c* @henrikbrixandersen -/drivers/i2c/*sam0* @Sizurka -/drivers/i2c/i2c_dw* @dcpleung -/drivers/i2c/*tca954x* @kurddt -/drivers/*/*xec* @franciscomunoz @albertofloyd @sjvasanth1 -/drivers/watchdog/*gecko* @oanerer -/drivers/watchdog/*sifive* @katsuster -/drivers/watchdog/wdt_handlers.c @dcpleung @nashif -/drivers/watchdog/*cc32xx* @pavlohamov -/drivers/watchdog/wdt_ite_it8xxx2.c @RuibinChang -/drivers/watchdog/Kconfig.it8xxx2 @RuibinChang -/drivers/watchdog/wdt_counter.c @nordic-krch -/drivers/watchdog/*rpi_pico* @thedjnK -/drivers/watchdog/*dw* @softwarecki @pbalsundar -/drivers/watchdog/*ifx* @sreeramIfx -/drivers/watchdog/*kb1200* @ene-steven -/drivers/wifi/esp_at/ @mniestroj -/drivers/wifi/eswifi/ @loicpoulain @nandojve -/drivers/wifi/winc1500/ @kludentwo -/drivers/virtualization/ @tbursztyka -/dts/arm/acsip/ @NorthernDean -/dts/arm/aspeed/ @aspeeddylan -/dts/arm/atmel/ @galak @nandojve -/dts/arm/broadcom/ @sbranden -/dts/arm/cypress/ @ifyall @npal-cy -/dts/arm/ene/kb1200 @ene-steven -/dts/arm/gd/ @nandojve -/dts/arm/infineon/xmc4* @parthitce @ifyall @npal-cy -/dts/arm/infineon/psoc6/ @ifyall @npal-cy -/dts/arm64/armv8-r.dtsi @povergoing -/dts/arm64/intel/*intel_socfpga* @siclim -/dts/arm64/nxp/ @JiafeiPan -/dts/arm64/renesas/ @lorc @xakep-amatop -/dts/arm/quicklogic/ @fkokosinski @kgugala -/dts/arm/seeed_studio/ @str4t0m -/dts/arm/st/h7/*stm32h735* @benediktibk -/dts/arm/st/l4/*stm32l451* @benediktibk -/dts/arm/ti/cc13?2* @bwitherspoon -/dts/arm/ti/cc26?2* @bwitherspoon -/dts/arm/ti/cc3235* @vanti -/dts/arm/nordic/ @anangl @carlescufi -/dts/arm/nuvoton/ @ssekar15 @MulinChao @ChiHuaL -/dts/arm/nxp/ @mmahadevan108 @dleach02 -/dts/arm/nxp/nxp_s32* @manuargue -/dts/arm/microchip/ @franciscomunoz @albertofloyd @sjvasanth1 -/dts/arm/rpi_pico/ @yonsch -/dts/arm/silabs/efm32_pg_1b.dtsi @rdmeneze -/dts/arm/silabs/efm32gg11b* @oanerer -/dts/arm/silabs/efr32bg13p* @mnkp -/dts/arm/silabs/efr32bg22* @kgugala @fkokosinski @pczarnecki -/dts/arm/silabs/efr32xg13p* @mnkp -/dts/arm/silabs/efm32pg1b* @rdmeneze -/dts/arm/silabs/efr32mg21* @l-alfred -/dts/arm/silabs/efr32fg13* @yonsch -/dts/riscv/ite/ @ite -/dts/riscv/microchip/microchip-miv.dtsi @galak -/dts/riscv/openisa/rv32m1* @dleach02 -/dts/riscv/starfive/ @rajnesh-kanwal @pfarwsi -/dts/riscv/andes/andes_v5* @cwshu @kevinwang821020 @jimmyzhe -/dts/riscv/niosv/ @sweeaun -/dts/arm/armv*m.dtsi @galak @ioannisg -/dts/arm/armv7-a.dtsi @ibirnbaum -/dts/arm/armv7-r.dtsi @bbolen @stephanosio -/dts/arm/xilinx/ @bbolen @stephanosio -/dts/arm/renesas/rcar/ @aaillet -/dts/xtensa/xtensa.dtsi @ydamigos -/dts/xtensa/intel/ @dcpleung -/dts/xtensa/espressif/ @sylvioalves -/dts/xtensa/nxp/ @iuliana-prodan @dbaluta -/dts/bindings/can/ @alexanderwachter @henrikbrixandersen -/dts/bindings/i2c/zephyr*i2c-emul*.yaml @sjg20 -/dts/bindings/adc/st*stm32-adc.yaml @cybertale -/dts/bindings/adc/*ads114s08.yaml @benediktibk -/dts/bindings/adc/*max111* @benediktibk -/dts/bindings/modem/*hl7800.yaml @rerickson1 -/dts/bindings/serial/ns16550.yaml @dcpleung @nashif -/dts/bindings/counter/snps,dw-timers.yaml @pbalsundar -/dts/bindings/wifi/*esp-at.yaml @mniestroj -/dts/bindings/*/*gd32* @nandojve -/dts/bindings/*/*sam* @nandojve -/dts/bindings/*/*npcx* @MulinChao @ChiHuaL -/dts/bindings/*/*psoc6* @ifyall @npal-cy -/dts/bindings/*/*infineon*cat1* @ifyall @npal-cy -/dts/bindings/*/nordic* @anangl -/dts/bindings/*/nxp* @mmahadevan108 @dleach02 -/dts/bindings/*/nxp*s32* @manuargue -/dts/bindings/*/openisa* @dleach02 -/dts/bindings/*/raspberrypi*pico* @yonsch -/dts/bindings/sensor/ams* @alexanderwachter -/dts/bindings/*/sifive* @mateusz-holenko @kgugala @pgielda -/dts/bindings/*/andes* @cwshu @kevinwang821020 @jimmyzhe -/dts/bindings/*/neorv32* @henrikbrixandersen -/dts/bindings/*/*lan91c111* @sgrrzhf -/dts/bindings/i3c/ @dcpleung -/dts/bindings/pm_cpu_ops/* @carlocaione -/dts/bindings/ethernet/*gem.yaml @ibirnbaum -/dts/bindings/auxdisplay/*pt6314.yaml @xingrz -/dts/bindings/auxdisplay/* @thedjnK -/dts/bindings/sensor/*bme680* @BoschSensortec -/dts/bindings/sensor/*ina23* @bbilas -/dts/bindings/sensor/st* @avisconti -/dts/bindings/sensor/zephyr,sensing.yaml @lixuzha @ghu0510 @qianruh -/dts/bindings/sensor/zephyr,sensing*.yaml @lixuzha @ghu0510 @qianruh -/dts/bindings/smbus/ @finikorg -/dts/bindings/sip_svc/ @maheshraotm -/dts/bindings/cpu/intel,niosv.yaml @sweeaun -/dts/bindings/reset/intel,socfpga-reset.yaml @nbalabak -/dts/bindings/gpio/*pcal64* @benediktibk -/dts/bindings/gpio/*bd8lb600fs* @benediktibk -/dts/bindings/gpio/*ads114s0x* @benediktibk -/dts/bindings/pwm/*max31790* @benediktibk -/dts/bindings/dac/*ad56* @benediktibk diff --git a/Kconfig.zephyr b/Kconfig.zephyr index 510769d8aa7..2d8031260ce 100644 --- a/Kconfig.zephyr +++ b/Kconfig.zephyr @@ -448,6 +448,7 @@ config CODING_GUIDELINE_CHECK config NATIVE_LIBC bool select FULL_LIBC_SUPPORTED + select TC_PROVIDES_POSIX_C_LANG_SUPPORT_R help Zephyr will use the host system C library. @@ -470,9 +471,11 @@ config NATIVE_APPLICATION default y if ARCH_POSIX depends on !NATIVE_LIBRARY select NATIVE_BUILD + select DEPRECATED help Build as a native application that can run on the host and using - resources and libraries provided by the host. + resources and libraries provided by the host. This option is deprecated + and will be removed in Zephyr v4.3 config NATIVE_LIBRARY bool @@ -790,7 +793,8 @@ config BUILD_OUTPUT_UF2_FAMILY_ID default "0xada52840" if SOC_NRF52840_QIAA default "0x4fb2d5bd" if SOC_SERIES_IMXRT10XX || SOC_SERIES_IMXRT11XX default "0x2abc77ec" if SOC_SERIES_LPC55XXX - default "0xe48bff56" if SOC_SERIES_RP2XXX + default "0xe48bff56" if SOC_SERIES_RP2040 + default "0xe48bff57" if SOC_SERIES_RP2350 default "0x68ed2b88" if SOC_SERIES_SAMD21 default "0x55114460" if SOC_SERIES_SAMD51 default "0x647824b6" if SOC_SERIES_STM32F0X @@ -1046,32 +1050,6 @@ config IS_BOOTLOADER This option indicates that Zephyr will act as a bootloader to execute a separate Zephyr image payload. -config BOOTLOADER_SRAM_SIZE - int "SRAM reserved for bootloader [DEPRECATED]" - default 0 - depends on !XIP || IS_BOOTLOADER - depends on ARM || XTENSA - help - This option specifies the amount of SRAM (measure in kB) reserved for - a bootloader image, when either: - - the Zephyr image itself is to act as the bootloader, or - - Zephyr is a !XIP image, which implicitly assumes existence of a - bootloader that loads the Zephyr !XIP image onto SRAM. - - This option is deprecated, users should transition to using DTS to set this, if needed. - To be removed after Zephyr 3.7 release. - -config BOOTLOADER_SRAM_SIZE_DEPRECATED - bool - default y - select DEPRECATED - depends on BOOTLOADER_SRAM_SIZE != 0 - depends on !XIP || IS_BOOTLOADER - depends on ARM || XTENSA - help - Non-prompt symbol to indicate that the deprecated BOOTLOADER_SRAM_SIZE Kconfig has a - non-0 value. Please transition to using devicetree. - config BOOTLOADER_BOSSA bool "BOSSA bootloader support" select USE_DT_CODE_PARTITION diff --git a/MAINTAINERS.yml b/MAINTAINERS.yml index fdc0a25a5f1..bd36809edf2 100644 --- a/MAINTAINERS.yml +++ b/MAINTAINERS.yml @@ -133,6 +133,7 @@ ARC arch: - evgeniy-paltsev collaborators: - abrodkin + - tagunil files: - arch/arc/ - include/zephyr/arch/arc/ @@ -158,6 +159,7 @@ ARM arch: - MaureenHelm - stephanosio - bbolen + - wearyzen files: - arch/arm/ - arch/arm/core/offsets/ @@ -194,6 +196,8 @@ ARM Platforms: status: maintained maintainers: - ithinuel + collaborators: + - wearyzen files: - boards/arm/mps*/ - boards/arm/v2m_*/ @@ -305,34 +309,34 @@ Bluetooth HCI: status: maintained maintainers: - jhedberg - - jori-nordic + - alwa-nordic collaborators: - hermabe - - alwa-nordic - Thalley - sjanc - theob-pro - HoZHel + - cvinayak files: - include/zephyr/drivers/bluetooth/ + - include/zephyr/drivers/bluetooth.h - drivers/bluetooth/ - samples/bluetooth/hci_*/ - tests/bsim/bluetooth/hci_uart/ - dts/bindings/bluetooth/ labels: - - "area: Bluetooth Host" + - "area: Bluetooth HCI" - "area: Bluetooth" tests: - bluetooth -Bluetooth controller: +Bluetooth Controller: status: maintained maintainers: - cvinayak collaborators: - carlescufi - thoh-ot - - kruithofa - ppryga - mtpr-ot - wopu-ot @@ -345,9 +349,6 @@ Bluetooth controller: - subsys/bluetooth/common/ - subsys/bluetooth/controller/ - subsys/bluetooth/crypto/ - - subsys/bluetooth/shell/ll.c - - subsys/bluetooth/shell/ll.h - - subsys/bluetooth/shell/ticker.c - tests/bluetooth/controller/ - tests/bsim/bluetooth/ll/ labels: @@ -359,14 +360,15 @@ Bluetooth controller: Bluetooth Host: status: maintained maintainers: - - jori-nordic - jhedberg + - alwa-nordic collaborators: - hermabe - - alwa-nordic - - Thalley + - rugeGerritsen - sjanc + - Thalley - theob-pro + - cvinayak files: - doc/connectivity/bluetooth/ - include/zephyr/bluetooth/ @@ -376,7 +378,6 @@ Bluetooth Host: - subsys/bluetooth/host/ - subsys/bluetooth/lib/ - subsys/bluetooth/services/ - - subsys/bluetooth/shell/ - subsys/bluetooth/CMakeLists.txt - subsys/bluetooth/Kconfig* - tests/bluetooth/ @@ -394,28 +395,29 @@ Bluetooth Host: - doc/connectivity/bluetooth/img/ctlr* - doc/connectivity/bluetooth/api/audio/ - doc/connectivity/bluetooth/api/mesh/ - - doc/connectivity/bluetooth/api/shell/iso.rst - doc/connectivity/bluetooth/api/controller.rst + - doc/connectivity/bluetooth/shell/classic/a2dp.rst + - doc/connectivity/bluetooth/shell/host/iso.rst + - doc/connectivity/bluetooth/shell/audio/ - samples/bluetooth/bap*/ - samples/bluetooth/cap*/ + - samples/bluetooth/ccp*/ - samples/bluetooth/hap*/ - samples/bluetooth/hci_*/ - samples/bluetooth/pbp*/ - samples/bluetooth/tmap*/ - samples/bluetooth/iso_*/ - samples/bluetooth/mesh*/ - - subsys/bluetooth/shell/bredr.c - - subsys/bluetooth/shell/iso.c - - subsys/bluetooth/shell/ll.c - - subsys/bluetooth/shell/ll.h - - subsys/bluetooth/shell/ticker.c - subsys/bluetooth/Kconfig.iso - subsys/bluetooth/host/iso.c - subsys/bluetooth/host/iso_internal.h + - subsys/bluetooth/host/shell/iso.c - tests/bluetooth/audio/ - tests/bluetooth/controller/ - tests/bluetooth/mesh*/ - tests/bluetooth/qualification/ + - tests/bluetooth/shell/audio.conf + - tests/bluetooth/shell/mesh.conf - tests/bluetooth/tester/ - tests/bsim/bluetooth/audio/ - tests/bsim/bluetooth/audio_samples/ @@ -446,6 +448,7 @@ Bluetooth Mesh: - samples/bluetooth/mesh*/ - subsys/bluetooth/mesh/ - tests/bluetooth/mesh*/ + - tests/bluetooth/shell/mesh.conf - tests/bsim/bluetooth/mesh/ labels: - "area: Bluetooth Mesh" @@ -464,11 +467,11 @@ Bluetooth Audio: - sjanc - asbjornsabo - fredrikdanebjer - - kruithofa - larsgk - pin-zephyr - niym-ot - jthm-ot + - babrsn files: - subsys/bluetooth/audio/ - include/zephyr/bluetooth/audio/ @@ -479,8 +482,10 @@ Bluetooth Audio: - tests/bluetooth/tester/overlay-le-audio.conf - tests/bluetooth/tester/src/audio/ - doc/connectivity/bluetooth/api/audio/ + - doc/connectivity/bluetooth/shell/audio/ - samples/bluetooth/bap*/ - samples/bluetooth/cap*/ + - samples/bluetooth/ccp*/ - samples/bluetooth/hap*/ - samples/bluetooth/pbp*/ - samples/bluetooth/tmap*/ @@ -496,11 +501,10 @@ Bluetooth Classic: - lylezhu2012 collaborators: - jhedberg - - sjanc files: + - doc/connectivity/bluetooth/shell/classic/a2dp.rst - subsys/bluetooth/common/ - subsys/bluetooth/host/classic/ - - subsys/bluetooth/shell/bredr.c - include/zephyr/bluetooth/classic/ labels: - "area: Bluetooth Classic" @@ -514,14 +518,16 @@ Bluetooth ISO: - Thalley collaborators: - jhedberg + - rugeGerritsen + - cvinayak files: - include/zephyr/bluetooth/iso.h - - doc/connectivity/bluetooth/api/shell/iso.rst + - doc/connectivity/bluetooth/shell/host/iso.rst - samples/bluetooth/iso_*/ - - subsys/bluetooth/shell/iso.c - subsys/bluetooth/Kconfig.iso - subsys/bluetooth/host/iso.c - subsys/bluetooth/host/iso_internal.h + - subsys/bluetooth/host/shell/iso.c labels: - "area: Bluetooth ISO" - "area: Bluetooth" @@ -576,6 +582,9 @@ Build system: - misc/generated/ - snippets/ - modules/Kconfig.sysbuild + - scripts/list_boards.py + - scripts/list_hardware.py + - scripts/schemas/*-schema.yml labels: - "area: Build System" tests: @@ -884,8 +893,10 @@ Devicetree: collaborators: - decsny - galak + - rruuaanng files-regex: - - dts/bindings/.*zephyr.* + - ^dts/bindings/.*zephyr.* + - ^dts/bindings/[^,]+$ files: - scripts/dts/ - dts/common/ @@ -920,6 +931,7 @@ Disk: - subsys/sd/ - tests/subsys/sd/ - tests/drivers/disk/ + - tests/drivers/build_all/disk/ - include/zephyr/sd/ - dts/bindings/sd/ - dts/bindings/mmc/ @@ -1005,8 +1017,8 @@ Documentation Infrastructure: Release Notes: status: maintained maintainers: - - dkalowsk - - mmahadevan108 + - fabiobaltieri + - kartben collaborators: - kartben files: @@ -1019,8 +1031,6 @@ Release Notes: status: maintained maintainers: - anangl - collaborators: - - decsny files: - drivers/adc/ - include/zephyr/drivers/adc.h @@ -1055,6 +1065,7 @@ Release Notes: - yperess files: - tests/drivers/bbram/ + - tests/drivers/build_all/bbram/ - drivers/bbram/ - include/zephyr/drivers/bbram.h - doc/hardware/peripherals/bbram.rst @@ -1227,6 +1238,7 @@ Release Notes: - samples/drivers/crypto/ - tests/crypto/ - doc/services/crypto/ + - tests/drivers/build_all/crypto/ labels: - "area: Crypto / RNG" tests: @@ -1378,6 +1390,7 @@ Release Notes: - decsny - lmajewski - pdgendt + - maass-hamburg files: - drivers/ethernet/ - include/zephyr/dt-bindings/ethernet/ @@ -1385,6 +1398,8 @@ Release Notes: - dts/bindings/ethernet/ - tests/drivers/ethernet/ - include/zephyr/drivers/ethernet/ + - include/zephyr/net/phy.h + - include/zephyr/net/ethernet.h labels: - "area: Ethernet" tests: @@ -1394,6 +1409,8 @@ Release Notes: status: maintained maintainers: - de-nordic + collaborators: + - rghaddab files: - drivers/flash/ - dts/bindings/flash_controller/ @@ -1405,6 +1422,7 @@ Release Notes: - doc/hardware/peripherals/flash.rst - include/zephyr/drivers/flash/ - tests/drivers/flash_simulator/ + - tests/drivers/build_all/flash/ labels: - "area: Flash" tests: @@ -1580,9 +1598,7 @@ Release Notes: - drivers.i3c "Drivers: IEEE 802.15.4": - status: maintained - maintainers: - - fgrandel + status: odd fixes collaborators: - rlubos - ankuns @@ -1631,10 +1647,12 @@ Release Notes: status: odd fixes collaborators: - decsny + - maass-hamburg files: - doc/hardware/peripherals/mdio.rst - drivers/mdio/ - include/zephyr/drivers/mdio.h + - include/zephyr/net/mdio.h - tests/drivers/build_all/mdio/ - dts/bindings/mdio/ labels: @@ -1767,7 +1785,6 @@ Release Notes: maintainers: - simonguinot collaborators: - - mbolivar-ampere - soburi - thedjnK files: @@ -2017,6 +2034,7 @@ Release Notes: - tristan-google - ubieda - jeppenodgaard + - asemjonovs files: - drivers/sensor/ - include/zephyr/drivers/sensor.h @@ -2071,6 +2089,11 @@ Release Notes: status: maintained maintainers: - jilaypandya + collaborators: + - bjarki-andreasen + - dipakgmx + - fabiobaltieri + - faxe1008 files: - drivers/stepper/ - include/zephyr/drivers/stepper.h @@ -2101,6 +2124,7 @@ Release Notes: collaborators: - loicpoulain - josuah + - ngphibang files: - drivers/video/ - include/zephyr/drivers/video.h @@ -2127,6 +2151,7 @@ Release Notes: - include/zephyr/drivers/w1.h - include/zephyr/drivers/sensor/w1_sensor.h - tests/drivers/w1/ + - tests/drivers/build_all/w1/ - samples/drivers/w1/ labels: - "area: W1" @@ -2159,6 +2184,7 @@ Release Notes: - rlubos - kludentwo - krish2718 + - MaochenWang1 files: - drivers/wifi/ - dts/bindings/wifi/ @@ -2200,6 +2226,16 @@ Release Notes: labels: - "area: Wi-Fi" +"Drivers: Wi-Fi NXP": + status: maintained + maintainers: + - dleach02 + - MaochenWang1 + files: + - drivers/wifi/nxp/ + labels: + - "platform: NXP Drivers" + "Drivers: Memory Management": status: maintained maintainers: @@ -2293,18 +2329,6 @@ Filesystems: tests: - filesystem -"Filesystems: FatFs reentrant support": - status: maintained - maintainers: - - ox11 - files: - - modules/fatfs/zfs_ffsystem.c - - tests/subsys/fs/fat_fs_api/src/test_fat_file_reentrant.c - labels: - - "area: File System" - tests: - - filesystem.fat - Formatted Output: status: maintained maintainers: @@ -2380,6 +2404,8 @@ Input: IPC: status: maintained maintainers: + - doki-nordic + collaborators: - carlocaione - arnopo files: @@ -2651,8 +2677,8 @@ MAINTAINERS file: status: maintained maintainers: - MaureenHelm - collaborators: - nashif + collaborators: - stephanosio files: - MAINTAINERS.yml @@ -2734,6 +2760,7 @@ hawkBit: - maass-hamburg files: - subsys/mgmt/hawkbit/ + - include/zephyr/mgmt/hawkbit/ - include/zephyr/mgmt/hawkbit.h - samples/subsys/mgmt/hawkbit/ labels: @@ -2806,14 +2833,17 @@ Networking: - doc/connectivity/networking/api/ieee802154.rst - doc/connectivity/networking/api/ptp.rst - doc/connectivity/networking/api/wifi.rst + - doc/connectivity/networking/api/http*.rst - include/zephyr/net/gptp.h - include/zephyr/net/ieee802154*.h - include/zephyr/net/ptp.h - include/zephyr/net/wifi*.h - include/zephyr/net/buf.h - include/zephyr/net/dhcpv4*.h + - include/zephyr/net/http/ - samples/net/gptp/ - samples/net/sockets/coap_*/ + - samples/net/sockets/*http*/ - samples/net/lwm2m_client/ - samples/net/wifi/ - samples/net/dhcpv4_client/ @@ -2822,12 +2852,14 @@ Networking: - subsys/net/l2/wifi/ - subsys/net/lib/coap/ - subsys/net/lib/config/ieee802154* + - subsys/net/lib/http/ - subsys/net/lib/lwm2m/ - subsys/net/lib/ptp/ - subsys/net/lib/tls_credentials/ - subsys/net/lib/dhcpv4/ - tests/net/dhcpv4/ - tests/net/ieee802154/ + - tests/net/lib/http*/ - tests/net/wifi/ labels: - "area: Networking" @@ -2923,8 +2955,6 @@ Networking: status: maintained maintainers: - jukkar - collaborators: - - fgrandel files: - doc/connectivity/networking/api/gptp.rst - include/zephyr/net/gptp.h @@ -2991,14 +3021,12 @@ Networking: - subsys/net/lib/ptp/ - samples/net/ptp/ labels: - - "area: Networking" + - "area: PTP" tests: - sample.net.ptp "Networking: Native IEEE 802.15.4": - status: maintained - maintainers: - - fgrandel + status: odd fixes collaborators: - rlubos - jukkar @@ -3040,6 +3068,7 @@ Networking: collaborators: - rlubos - krish2718 + - MaochenWang1 files: - doc/connectivity/networking/api/wifi.rst - include/zephyr/net/wifi*.h @@ -3052,6 +3081,25 @@ Networking: tests: - net.wifi +"Networking: HTTP": + status: maintained + maintainers: + - jukkar + - rlubos + collaborators: + - mrodgers-witekio + files: + - doc/connectivity/networking/api/http*.rst + - include/zephyr/net/http/ + - subsys/net/lib/http/ + - samples/net/sockets/*http*/ + - tests/net/lib/http*/ + labels: + - "area: Networking" + - "area: HTTP" + tests: + - net.http + NIOS-2 arch: status: maintained maintainers: @@ -3103,6 +3151,18 @@ Open AMP: tests: - sample.ipc.openamp +PHYTEC Platforms: + status: maintained + maintainers: + - dnltz + collaborators: + - jonas-rem + - pefech + files: + - boards/phytec/ + labels: + - "platform: PHYTEC" + POSIX API layer: status: maintained maintainers: @@ -3126,6 +3186,7 @@ Power management: status: maintained maintainers: - ceolin + - bjarki-andreasen collaborators: - nashif - teburd @@ -3318,7 +3379,7 @@ Shields: SPARC arch: status: odd fixes collaborators: - - julius-barendt + - tbr-tt files: - arch/sparc/ - include/zephyr/arch/sparc/ @@ -3330,7 +3391,7 @@ SPARC arch: Gaisler Platforms: status: odd fixes collaborators: - - julius-barendt + - tbr-tt files: - dts/sparc/gaisler/ - soc/gaisler/ @@ -3481,20 +3542,22 @@ Nuvoton NPCM Platforms: - soc/nuvoton/npcm/ - boards/nuvoton/npcm*/ - dts/arm/nuvoton/ + - drivers/*/*_npcm* + - include/zephyr/dt-bindings/*/npcm_* labels: - "platform: Nuvoton NPCM" Raspberry Pi Pico Platforms: status: maintained maintainers: - - yonsch - collaborators: - soburi + collaborators: + - yonsch files: - boards/raspberrypi/ - boards/adafruit/kb2040/ - boards/sparkfun/pro_micro_rp2040/ - - dts/arm/rpi_pico/ + - dts/arm/raspberrypi/rpi_pico/ - dts/bindings/*/raspberrypi,pico* - drivers/*/*rpi_pico - drivers/*/*rpi_pico*/ @@ -3515,7 +3578,9 @@ Silabs Platforms: - boards/silabs/ - dts/arm/silabs/ - dts/bindings/*/silabs* - - drivers/*/*_gecko* + - drivers/*/*gecko* + - drivers/bluetooth/hci/hci_silabs_* + - drivers/*/*silabs* labels: - "platform: Silabs" @@ -3534,12 +3599,26 @@ Silabs SiM3U Platforms: - drivers/*/Kconfig.si32 - dts/arm/silabs/sim3u* - dts/bindings/*/*silabs,si32* + - include/zephyr/dt-bindings/pinctrl/*si32* - soc/silabs/silabs_sim3/ labels: - "platform: Silabs SiM3U" description: >- SiM3U SoCs, dts files, and related drivers. Boards based on SiM3U SoCs. +Gardena Platforms: + status: maintained + maintainers: + - rettichschnidi + collaborators: + - M1cha + files: + - boards/gardena/ + labels: + - "platform: Gardena" + description: >- + Gardena board(s). + Intel Platforms (X86): status: maintained maintainers: @@ -3628,11 +3707,9 @@ NXP Drivers: - dleach02 - mmahadevan108 collaborators: - - danieldegrasse - decsny - manuargue - dbaluta - - MarkWangChinese files-regex: - ^drivers/.*nxp.* - ^drivers/.*mcux.* @@ -3643,7 +3720,7 @@ NXP Drivers: - drivers/*/*.mcux - drivers/*/*.nxp - drivers/*/*nxp* - - drivers/*/*kinetis* + - drivers/*/*/*kinetis* - drivers/misc/*/nxp* - include/zephyr/dt-bindings/*/*nxp* - include/zephyr/dt-bindings/*/*mcux* @@ -3653,19 +3730,32 @@ NXP Drivers: - include/zephyr/drivers/*/*mcux* - arch/arm/core/mpu/nxp_mpu.c - dts/bindings/*/nxp* + files-exclude: + - drivers/wifi/nxp/ + - drivers/usb/*/*mcux* files-regex-exclude: - .*s32.* labels: - "platform: NXP Drivers" description: NXP Drivers +NXP MCUX USB: + status: maintained + maintainers: + - mmahadevan108 + - MarkWangChinese + files: + - drivers/usb/*/*mcux* + labels: + - "platform: NXP Drivers" + description: NXP MCUX USB shim drivers + NXP Platforms (MCU): status: maintained maintainers: - dleach02 - mmahadevan108 collaborators: - - danieldegrasse - DerekSnell - yvanderv - EmilioCBen @@ -3685,6 +3775,8 @@ NXP Platforms (MCU): - soc/nxp/mcx/ - dts/arm/nxp/ - samples/boards/nxp*/ + files-exclude: + - dts/arm/nxp/nxp_imx* files-regex-exclude: - .*s32.* labels: @@ -3725,11 +3817,10 @@ NXP Platforms (MPU): - dleach02 - dbaluta - iuliana-prodan - - danieldegrasse - - decsny - yvanderv files: - dts/arm64/nxp/ + - dts/arm/nxp/nxp_imx* - soc/nxp/imx/ - soc/nxp/layerscape/ files-regex: @@ -3765,7 +3856,8 @@ Microchip MEC Platforms: - drivers/*/*mchp*.c - tests/boards/mec15xxevb_assy6853/ - tests/boards/mec172xevb_assy6906/ - - dts/bindings/*/microchip,* + - dts/bindings/*/microchip,mec* + - dts/bindings/*/microchip,xec* labels: - "platform: Microchip MEC" @@ -3932,6 +4024,7 @@ STM32 Platforms: - GeorgeCGV - marwaiehm-st - mathieuchopstm + - djiatsaf-st files: - boards/st/ - drivers/*/*stm32*.c @@ -3942,11 +4035,37 @@ STM32 Platforms: - dts/bindings/*/*stm32* - soc/st/stm32/ - samples/boards/st/ + files-exclude: + - boards/st/*wb*/ + - drivers/bluetooth/hci/*stm32*.c + - soc/st/stm32/stm32wb*/ labels: - "platform: STM32" description: >- - STM32 SOCs, dts files and related drivers. ST nucleo, disco and eval - boards. + STM32 SOCs, dts files and related drivers. ST development boards. + +STM32 Wireless Platforms: + status: maintained + maintainers: + - erwango + collaborators: + - asm5878 + - HoZHel + - benothmn-st + - mathieuchopstm + files: + - boards/shields/x_nucleo_bnrg2a1/ + - boards/shields/x_nucleo_idb05a1/ + - boards/shields/x_nucleo_wb05kn1/ + - boards/st/*wb*/ + - drivers/bluetooth/hci/*stm32*.c + - drivers/bluetooth/hci/hci_spi_st.c + - soc/st/stm32/stm32wb*/ + labels: + - "platform: STM32" + description: >- + STM32WB SOCs, dts files and related drivers. STM32WB development boards + and ST bluetooth shields. Espressif Platforms: status: maintained @@ -3966,7 +4085,7 @@ Espressif Platforms: - dts/riscv/espressif/ - dts/bindings/*/*esp32* - samples/boards/espressif/ - - tests/boards/espressif_esp32/ + - tests/boards/espressif/ - drivers/*/*esp32*/ labels: - "platform: ESP32" @@ -4022,8 +4141,6 @@ TI K3 Platforms: - gramsay0 - dnltz files: - - boards/phytec/phyboard_lyra/ - - boards/phytec/phyboard_electra/ - boards/ti/*am62*/ - drivers/*/*ti_k3* - dts/bindings/*/ti,k3* @@ -4044,8 +4161,12 @@ Xilinx Platforms: collaborators: - henrikbrixandersen - ibirnbaum + - michalsimek files: + - boards/amd/ + - drivers/*/*xilinx* - drivers/*/*xlnx* + - drivers/*/*zynq* - dts/*/xilinx/ - dts/bindings/*/*xlnx* - include/zephyr/*/*/*xlnx* @@ -4124,6 +4245,20 @@ RTIO: tests: - rtio +Secure storage: + status: maintained + maintainers: + - tomi-font + files: + - subsys/secure_storage/ + - samples/psa/ + - doc/services/secure_storage.rst + - tests/subsys/secure_storage/ + labels: + - "area: Secure storage" + tests: + - psa.secure_storage + Storage: status: odd fixes files: @@ -4136,6 +4271,17 @@ Storage: tests: - storage +Storage ZMS: + status: maintained + maintainers: + - rghaddab + files: + - subsys/fs/zms/ + - include/zephyr/fs/zms.h + - samples/subsys/fs/zms/ + - tests/subsys/fs/zms/ + - doc/services/storage/zms/zms.rst + Sysbuild: status: maintained maintainers: @@ -4288,6 +4434,7 @@ USB: - samples/subsys/usb/ - subsys/usb/ - tests/subsys/usb/ + - tests/drivers/build_all/usb/ - tests/drivers/usb/ - tests/drivers/udc/ - doc/connectivity/usb/ @@ -4365,12 +4512,13 @@ VFS: - filesystem West: - status: odd fixes + status: maintained + maintainers: + - pdgendt collaborators: - - mbolivar-ampere + - mbolivar - carlescufi - swinslow - - pdgendt files: - scripts/west-commands.yml - scripts/west_commands/ @@ -4537,6 +4685,17 @@ West: labels: - "area: CMSIS-NN" +"West project: cmsis_6": + status: maintained + maintainers: + - ithinuel + collaborators: + - tomi-font + - wearyzen + files: [] + labels: + - "area: CMSIS_6" + "West project: edtt": status: maintained maintainers: @@ -4627,6 +4786,9 @@ West: status: maintained maintainers: - kristofer-jonsson-arm + - ithinuel + collaborators: + - wearyzen files: - drivers/misc/ethos_u/ - modules/hal_ethos_u/ @@ -4679,11 +4841,6 @@ West: collaborators: - hubertmis - nordic-krch - - krish2718 - - sachinthegreen - - udaynordic - - rajb9 - - srkanordic files: - modules/hal_nordic/ labels: @@ -4704,7 +4861,7 @@ West: - dleach02 - mmahadevan108 collaborators: - - danieldegrasse + - decsny - manuargue - PetervdPerk-NXP - bperseghetti @@ -4752,6 +4909,8 @@ West: "West project: hal_rpi_pico": status: maintained maintainers: + - soburi + collaborators: - yonsch files: - modules/hal_rpi_pico/ @@ -4770,7 +4929,7 @@ West: - mnkp - rettichschnidi files: - - modules/Kconfig.silabs + - modules/hal_silabs/ labels: - "platform: Silabs" @@ -4791,11 +4950,25 @@ West: - FRASTM - gautierg-st - marwaiehm-st + - asm5878 + - HoZHel + - benothmn-st files: - modules/Kconfig.stm32 labels: - "platform: STM32" +"West project: hal_tdk": + status: maintained + maintainers: + - afontaine-invn + collaborators: + - rbuisson-invn + - gjabouley-invn + - sriccardi-invn + files: + - modules/hal_tdk/Kconfig + "West project: hal_telink": status: maintained maintainers: @@ -4813,6 +4986,14 @@ West: labels: - "platform: TI" +"West project: hal_wch": + status: maintained + maintainers: + - nzmichaelh + - kholia + files: + - modules/hal_wch/ + "West project: hal_wurthelektronik": status: maintained maintainers: @@ -4844,6 +5025,14 @@ West: labels: - "platform: Intel" +"West project: zephyr-lang-rust": + status: maintained + maintainers: + - d3zd3z + files: [] + labels: + - "area: Rust" + "West project: libmetal": status: odd fixes collaborators: @@ -4890,6 +5079,7 @@ West: collaborators: - brgl - pdgendt + - uLipe files: - modules/lvgl/ - tests/lib/gui/lvgl/ @@ -4914,6 +5104,7 @@ West: - ceolin collaborators: - ithinuel + - wearyzen - valeriosetti - tomi-font files: @@ -4925,6 +5116,7 @@ West: tests: - benchmark.crypto.mbedtls - crypto.mbedtls + - psa.secure_storage "West project: mcuboot": status: maintained @@ -4985,6 +5177,10 @@ West: maintainers: - krish2718 - sachinthegreen + collaborators: + - udaynordic + - rajb9 + - srkanordic files: - modules/nrf_wifi/ labels: @@ -5097,6 +5293,7 @@ West: collaborators: - Vge0rge - ithinuel + - wearyzen - valeriosetti - tomi-font files: @@ -5107,6 +5304,7 @@ West: - "area: TF-M" tests: - trusted-firmware-m + - psa.secure_storage "West project: tf-m-tests": status: maintained @@ -5115,6 +5313,7 @@ West: collaborators: - Vge0rge - ithinuel + - wearyzen files: [] labels: - "area: TF-M" @@ -5127,6 +5326,7 @@ West: collaborators: - carlocaione - ithinuel + - wearyzen files: - modules/trusted-firmware-a/ labels: @@ -5139,6 +5339,7 @@ West: collaborators: - Vge0rge - ithinuel + - wearyzen files: [] labels: - "area: TF-M" @@ -5175,10 +5376,14 @@ West: maintainers: - krish2718 - jukkar + collaborators: + - MaochenWang1 files: - modules/hostap/ labels: - "area: Wi-Fi" + tests: + - net.wifi Xtensa arch: status: maintained @@ -5195,7 +5400,6 @@ Xtensa arch: - boards/qemu/xtensa/ - boards/cdns/xt-sim/ - soc/cdns/dc233c/ - - soc/cdns/dc233c/ - soc/cdns/xtensa_sample_controller/ - tests/arch/xtensa/ labels: @@ -5306,6 +5510,8 @@ Testing with Renode: - fkokosinski files: - cmake/emu/renode.cmake + - soc/renode/ + - boards/renode/ - boards/**/*/support/*.repl - boards/**/*/support/*.resc labels: @@ -5334,6 +5540,7 @@ zbus: - lyakh - pillo79 files: + - cmake/llext-edk.cmake - samples/subsys/llext/ - include/zephyr/llext/ - tests/subsys/llext/ diff --git a/README.rst b/README.rst index 2b44d5ed4a5..9472db6d5ee 100644 --- a/README.rst +++ b/README.rst @@ -10,15 +10,9 @@

- - - - - - - - - + + + The Zephyr Project is a scalable real-time operating system (RTOS) supporting diff --git a/SDK_VERSION b/SDK_VERSION index 74aaa3f38cf..c5523bd09b1 100644 --- a/SDK_VERSION +++ b/SDK_VERSION @@ -1 +1 @@ -0.16.8 +0.17.0 diff --git a/VERSION b/VERSION index 83bbbb1d942..b170abf44be 100644 --- a/VERSION +++ b/VERSION @@ -1,5 +1,5 @@ -VERSION_MAJOR = 3 -VERSION_MINOR = 7 +VERSION_MAJOR = 4 +VERSION_MINOR = 0 PATCHLEVEL = 99 VERSION_TWEAK = 0 EXTRAVERSION = diff --git a/arch/Kconfig b/arch/Kconfig index da35a1b2751..94e9a540a08 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -50,11 +50,12 @@ config ARM64 select ARCH_HAS_THREAD_LOCAL_STORAGE select USE_SWITCH select USE_SWITCH_SUPPORTED - select IRQ_OFFLOAD_NESTED if IRQ_OFFLOAD select BARRIER_OPERATIONS_ARCH select ARCH_HAS_DIRECTED_IPIS select ARCH_HAS_DEMAND_PAGING select ARCH_HAS_DEMAND_MAPPING + select ARCH_SUPPORTS_EVICTION_TRACKING + select EVICTION_TRACKING if DEMAND_PAGING help ARM64 (AArch64) architecture @@ -83,6 +84,7 @@ config X86 select ARCH_IS_SET select ATOMIC_OPERATIONS_BUILTIN select ARCH_SUPPORTS_COREDUMP + select ARCH_SUPPORTS_COREDUMP_PRIV_STACKS select ARCH_SUPPORTS_ROM_START if !X86_64 select CPU_HAS_MMU select ARCH_MEM_DOMAIN_DATA if USERSPACE && !X86_COMMON_PAGE_TABLE @@ -91,7 +93,7 @@ config X86 select ARCH_HAS_TIMING_FUNCTIONS select ARCH_HAS_THREAD_LOCAL_STORAGE select ARCH_HAS_DEMAND_PAGING if !X86_64 - select IRQ_OFFLOAD_NESTED if IRQ_OFFLOAD + select ARCH_HAS_DEMAND_MAPPING if ARCH_HAS_DEMAND_PAGING select NEED_LIBC_MEM_PARTITION if USERSPACE && TIMING_FUNCTIONS \ && !BOARD_HAS_TIMING_FUNCTIONS \ && !SOC_HAS_TIMING_FUNCTIONS @@ -114,11 +116,11 @@ config RISCV bool select ARCH_IS_SET select ARCH_SUPPORTS_COREDUMP + select ARCH_SUPPORTS_COREDUMP_PRIV_STACKS select ARCH_SUPPORTS_ROM_START if !SOC_FAMILY_ESPRESSIF_ESP32 select ARCH_SUPPORTS_EMPTY_IRQ_SPURIOUS select ARCH_HAS_CODE_DATA_RELOCATION select ARCH_HAS_THREAD_LOCAL_STORAGE - select IRQ_OFFLOAD_NESTED if IRQ_OFFLOAD select USE_SWITCH_SUPPORTED select USE_SWITCH select SCHED_IPI_SUPPORTED if SMP @@ -133,7 +135,6 @@ config XTENSA select ARCH_IS_SET select USE_SWITCH select USE_SWITCH_SUPPORTED - select IRQ_OFFLOAD_NESTED if IRQ_OFFLOAD select ARCH_HAS_CODE_DATA_RELOCATION select ARCH_HAS_TIMING_FUNCTIONS select ARCH_MEM_DOMAIN_DATA if USERSPACE @@ -448,9 +449,8 @@ config ISR_TABLES_LOCAL_DECLARATION_SUPPORTED depends on "$(ZEPHYR_TOOLCHAIN_VARIANT)" = "zephyr" || "$(ZEPHYR_TOOLCHAIN_VARIANT)" = "gnuarmemb" config ISR_TABLES_LOCAL_DECLARATION - bool "ISR tables created locally and placed by linker [EXPERIMENTAL]" + bool "ISR tables created locally and placed by linker" depends on ISR_TABLES_LOCAL_DECLARATION_SUPPORTED - select EXPERIMENTAL help Enable new scheme of interrupt tables generation. This is totally different generator that would create tables entries locally @@ -576,11 +576,12 @@ config IRQ_OFFLOAD config IRQ_OFFLOAD_NESTED bool "irq_offload() supports nested IRQs" depends on IRQ_OFFLOAD + default y if ARM64 || X86 || RISCV || XTENSA help - When set by the arch layer, indicates that irq_offload() may - legally be called in interrupt context to cause a - synchronous nested interrupt on the current CPU. Not all - hardware is capable. + When set by the platform layers, indicates that + irq_offload() may legally be called in interrupt context to + cause a synchronous nested interrupt on the current CPU. + Not all hardware is capable. config EXCEPTION_DEBUG bool "Unhandled exception debugging" @@ -679,6 +680,9 @@ config ARCH_SUPPORTS_COREDUMP config ARCH_SUPPORTS_COREDUMP_THREADS bool +config ARCH_SUPPORTS_COREDUMP_PRIV_STACKS + bool + config ARCH_SUPPORTS_ARCH_HW_INIT bool @@ -688,6 +692,12 @@ config ARCH_SUPPORTS_ROM_START config ARCH_SUPPORTS_EMPTY_IRQ_SPURIOUS bool +config ARCH_SUPPORTS_EVICTION_TRACKING + bool + help + Architecture code supports page tracking for eviction algorithms + when demand paging is enabled. + config ARCH_HAS_EXTRA_EXCEPTION_INFO bool @@ -819,7 +829,7 @@ config CPU_CACHE_INCOHERENT help This hidden configuration should be selected when the CPU has incoherent cache. This applies to intra-CPU multiprocessing - incoherence and makes only sense when MP_NUM_CPUS > 1. + incoherence and makes only sense when MP_MAX_NUM_CPUS > 1. config CPU_HAS_ICACHE bool @@ -1025,7 +1035,7 @@ config CACHE_DOUBLEMAP point to the same cached/uncached memory at different locations. This applies to intra-CPU multiprocessing incoherence and makes only - sense when MP_NUM_CPUS > 1. + sense when MP_MAX_NUM_CPUS > 1. config CACHE_MANAGEMENT bool "Cache management features" @@ -1134,3 +1144,9 @@ config ARCH_HAS_CUSTOM_BUSY_WAIT It's possible that an architecture port cannot or does not want to use the provided k_busy_wait(), but instead must do something custom. It must enable this option in that case. + +config ARCH_HAS_CUSTOM_CURRENT_IMPL + bool + help + Select when architecture implements arch_current_thread() & + arch_current_thread_set(). diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig index a27b09659ac..d44ca272b11 100644 --- a/arch/arc/Kconfig +++ b/arch/arc/Kconfig @@ -262,7 +262,7 @@ config ARC_CURRENT_THREAD_USE_NO_TLS RGF_NUM_BANKS the parameter is disabled by-default because banks syncronization requires significant time, and it slows down performance. ARCMWDT works with tls pointer in different way then GCC. Optimized access to - TLS pointer via _current variable does not provide significant advantages + TLS pointer via the _current symbol does not provide significant advantages in case of MetaWare. config GEN_ISR_TABLES @@ -343,6 +343,15 @@ config ARC_NORMAL_FIRMWARE resources of the ARC processors, and, therefore, it shall avoid accessing them. +config ARC_VPX_COOPERATIVE_SHARING + bool "Cooperative sharing of ARC VPX vector registers" + select SCHED_CPU_MASK if MP_MAX_NUM_CPUS > 1 + help + This option enables the cooperative sharing of the ARC VPX vector + registers. Threads that want to use those registers must successfully + call arc_vpx_lock() before using them, and call arc_vpx_unlock() + when done using them. + source "arch/arc/core/dsp/Kconfig" menu "ARC MPU Options" @@ -374,9 +383,7 @@ config ARC_EXCEPTION_STACK_SIZE endmenu config ARC_EARLY_SOC_INIT - bool "Make early stage SoC-specific initialization [DEPRECATED]" - select SOC_RESET_HOOK - select DEPRECATED + bool "Make early stage SoC-specific initialization" help Call SoC per-core setup code on early stage initialization (before C runtime initialization). Setup code is called in form of diff --git a/arch/arc/core/CMakeLists.txt b/arch/arc/core/CMakeLists.txt index 00c9f775038..5b81f527480 100644 --- a/arch/arc/core/CMakeLists.txt +++ b/arch/arc/core/CMakeLists.txt @@ -34,3 +34,5 @@ add_subdirectory_ifdef(CONFIG_ARC_CORE_MPU mpu) add_subdirectory_ifdef(CONFIG_ARC_SECURE_FIRMWARE secureshield) zephyr_linker_sources(ROM_START SORT_KEY 0x0vectors vector_table.ld) + +zephyr_library_sources_ifdef(CONFIG_LLEXT elf.c) diff --git a/arch/arc/core/elf.c b/arch/arc/core/elf.c new file mode 100644 index 00000000000..9f9f1073431 --- /dev/null +++ b/arch/arc/core/elf.c @@ -0,0 +1,80 @@ +/* + * Copyright (c) 2024 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include + +LOG_MODULE_REGISTER(elf, CONFIG_LLEXT_LOG_LEVEL); + +#define R_ARC_32 4 +#define R_ARC_B26 5 /* AKA R_ARC_64 */ +#define R_ARC_S25W_PCREL 17 +#define R_ARC_32_ME 27 + +/* ARCompact insns packed in memory have Middle Endian encoding */ +#define ME(x) (((x & 0xffff0000) >> 16) | ((x & 0xffff) << 16)) + +/** + * @brief Architecture specific function for relocating shared elf + * + * Elf files contain a series of relocations described in multiple sections. + * These relocation instructions are architecture specific and each architecture + * supporting modules must implement this. + * + * The relocation codes are well documented: + * https://github.com/foss-for-synopsys-dwc-arc-processors/arc-ABI-manual/blob/master/ARCv2_ABI.pdf + * https://github.com/zephyrproject-rtos/binutils-gdb + */ +int arch_elf_relocate(elf_rela_t *rel, uintptr_t loc, uintptr_t sym_base_addr, const char *sym_name, + uintptr_t load_bias) +{ + int ret = 0; + uint32_t insn = UNALIGNED_GET((uint32_t *)loc); + uint32_t value; + + sym_base_addr += rel->r_addend; + + int reloc_type = ELF32_R_TYPE(rel->r_info); + + switch (reloc_type) { + case R_ARC_32: + case R_ARC_B26: + UNALIGNED_PUT(sym_base_addr, (uint32_t *)loc); + break; + case R_ARC_S25W_PCREL: + /* ((S + A) - P) >> 2 + * S = symbol address + * A = addend + * P = relative offset to PCL + */ + value = (sym_base_addr + rel->r_addend - (loc & ~0x3)) >> 2; + + insn = ME(insn); + + /* disp25w */ + insn = insn & ~0x7fcffcf; + insn |= ((value >> 0) & 0x01ff) << 18; + insn |= ((value >> 9) & 0x03ff) << 6; + insn |= ((value >> 19) & 0x000f) << 0; + + insn = ME(insn); + + UNALIGNED_PUT(insn, (uint32_t *)loc); + break; + case R_ARC_32_ME: + UNALIGNED_PUT(ME(sym_base_addr), (uint32_t *)loc); + break; + default: + LOG_ERR("unknown relocation: %u\n", reloc_type); + ret = -ENOEXEC; + break; + } + + return ret; +} diff --git a/arch/arc/core/reset.S b/arch/arc/core/reset.S index 63fa6438ce4..a2b038d387e 100644 --- a/arch/arc/core/reset.S +++ b/arch/arc/core/reset.S @@ -16,9 +16,8 @@ #include #include #include - -#if defined(CONFIG_SOC_RESET_HOOK) -GTEXT(soc_reset_hook) +#ifdef CONFIG_ARC_EARLY_SOC_INIT + #include #endif GDATA(z_interrupt_stacks) @@ -113,8 +112,8 @@ done_icache_invalidate: done_dcache_invalidate: -#ifdef CONFIG_SOC_RESET_HOOK - bl soc_reset_hook +#ifdef CONFIG_ARC_EARLY_SOC_INIT + soc_early_asm_init_percpu #endif _dsp_extension_probe diff --git a/arch/arc/core/smp.c b/arch/arc/core/smp.c index e8463b7b53b..1b06c2ac7d1 100644 --- a/arch/arc/core/smp.c +++ b/arch/arc/core/smp.c @@ -16,6 +16,7 @@ #include #include #include +#include #include volatile struct { @@ -115,6 +116,11 @@ void arch_secondary_cpu_init(int cpu_num) DT_IRQ(DT_NODELABEL(ici), priority), 0); irq_enable(DT_IRQN(DT_NODELABEL(ici))); #endif + +#ifdef CONFIG_SOC_PER_CORE_INIT_HOOK + soc_per_core_init_hook(); +#endif /* CONFIG_SOC_PER_CORE_INIT_HOOK */ + /* call the function set by arch_cpu_start */ fn = arc_cpu_init[cpu_num].fn; diff --git a/arch/arc/core/thread.c b/arch/arc/core/thread.c index 1c85a416ca6..4b1d836103e 100644 --- a/arch/arc/core/thread.c +++ b/arch/arc/core/thread.c @@ -19,10 +19,15 @@ #include #endif -#if defined(CONFIG_ARC_DSP) && defined(CONFIG_DSP_SHARING) +#if defined(CONFIG_ARC_VPX_COOPERATIVE_SHARING) || defined(CONFIG_DSP_SHARING) #include static struct k_spinlock lock; #endif + +#if defined(CONFIG_ARC_VPX_COOPERATIVE_SHARING) +static struct k_sem vpx_sem[CONFIG_MP_MAX_NUM_CPUS]; +#endif + /* initial stack frame */ struct init_stack_frame { uintptr_t pc; @@ -320,3 +325,65 @@ void arc_dsp_enable(struct k_thread *thread, unsigned int options) k_spin_unlock(&lock, key); } #endif /* CONFIG_ARC_DSP && CONFIG_DSP_SHARING */ + +#if defined(CONFIG_ARC_VPX_COOPERATIVE_SHARING) +int arc_vpx_lock(k_timeout_t timeout) +{ + k_spinlock_key_t key; + unsigned int id; + + key = k_spin_lock(&lock); + + id = _current_cpu->id; +#if (CONFIG_MP_MAX_NUM_CPUS > 1) && defined(CONFIG_SCHED_CPU_MASK) + __ASSERT(!arch_is_in_isr() && (_current->base.cpu_mask == BIT(id)), ""); +#endif + k_spin_unlock(&lock, key); + + /* + * It is assumed that the thread is (still) pinned to + * the same CPU identified by . + */ + + return k_sem_take(&vpx_sem[id], timeout); +} + +void arc_vpx_unlock(void) +{ + k_spinlock_key_t key; + unsigned int id; + + key = k_spin_lock(&lock); +#if (CONFIG_MP_MAX_NUM_CPUS > 1) && defined(CONFIG_SCHED_CPU_MASK) + __ASSERT(!arch_is_in_isr() && (_current->base.cpu_mask == BIT(id)), ""); +#endif + id = _current_cpu->id; + k_spin_unlock(&lock, key); + + /* + * It is assumed that this thread is (still) pinned to + * the CPU identified by , and that it is the same CPU + * used by arc_vpx_lock(). + */ + + k_sem_give(&vpx_sem[id]); +} + +void arc_vpx_unlock_force(unsigned int id) +{ + __ASSERT(id < CONFIG_MP_MAX_NUM_CPUS, ""); + + k_sem_give(&vpx_sem[id]); +} + +static int arc_vpx_sem_init(void) +{ + for (unsigned int i = 0; i < CONFIG_MP_MAX_NUM_CPUS; i++) { + k_sem_init(vpx_sem, 1, 1); + } + + return 0; +} + +SYS_INIT(arc_vpx_sem_init, PRE_KERNEL_2, CONFIG_KERNEL_INIT_PRIORITY_OBJECTS); +#endif diff --git a/arch/arc/include/kernel_arch_func.h b/arch/arc/include/kernel_arch_func.h index ca382a274f4..73bd352a249 100644 --- a/arch/arc/include/kernel_arch_func.h +++ b/arch/arc/include/kernel_arch_func.h @@ -26,6 +26,8 @@ #include +#include + #ifdef __cplusplus extern "C" { #endif @@ -33,6 +35,10 @@ extern "C" { static ALWAYS_INLINE void arch_kernel_init(void) { z_irq_setup(); + +#ifdef CONFIG_SOC_PER_CORE_INIT_HOOK + soc_per_core_init_hook(); +#endif /* CONFIG_SOC_PER_CORE_INIT_HOOK */ } diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index c28cf8d29f9..3ce78334cb6 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -155,12 +155,12 @@ config CPU_HAS_ARM_MPU This option is enabled when the CPU has a Memory Protection Unit (MPU) in ARM flavor. -config CPU_HAS_NXP_MPU +config CPU_HAS_NXP_SYSMPU bool select CPU_HAS_MPU help - This option is enabled when the CPU has a Memory Protection Unit (MPU) - in NXP flavor. + This option is enabled when the CPU has an NXP System Memory Protection + Unit (SYSMPU). config CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS bool "Custom fixed SoC MPU region definition" diff --git a/arch/arm/core/cortex_a_r/CMakeLists.txt b/arch/arm/core/cortex_a_r/CMakeLists.txt index d4e18a614f0..7d18e0e610d 100644 --- a/arch/arm/core/cortex_a_r/CMakeLists.txt +++ b/arch/arm/core/cortex_a_r/CMakeLists.txt @@ -24,4 +24,4 @@ zephyr_library_sources_ifdef(CONFIG_SEMIHOST semihost.c) zephyr_library_sources_ifdef(CONFIG_THREAD_LOCAL_STORAGE __aeabi_read_tp.S) zephyr_library_sources_ifdef(CONFIG_ARCH_CACHE cache.c) zephyr_library_sources_ifdef(CONFIG_USE_SWITCH switch.S) -zephyr_library_sources_ifndef(CONFIG_USE_SWITCH swap.c swap_helper.S exc_exit.S) +zephyr_library_sources_ifndef(CONFIG_USE_SWITCH swap_helper.S exc_exit.S) diff --git a/arch/arm/core/cortex_a_r/Kconfig b/arch/arm/core/cortex_a_r/Kconfig index 2ee3c945644..409968ca6c7 100644 --- a/arch/arm/core/cortex_a_r/Kconfig +++ b/arch/arm/core/cortex_a_r/Kconfig @@ -111,6 +111,32 @@ config CPU_CORTEX_R52 help This option signifies the use of a Cortex-R52 CPU +config CPU_CORTEX_R52_CACHE_SEGREGATION + bool "Control segregation of L1 I/D-Cache ways between Flash and AXIM" + depends on CPU_CORTEX_R52 + help + Control segregation of L1 I/D-Cache ways between Flash and AXIM. + Updates to the cache segregation controls are only permitted before the caches + have ever been enabled, following a system reset, otherwise the update is ignored. + +config CPU_CORTEX_R52_ICACHE_FLASH_WAY + int "L1 I-Cache Flash way" + depends on CPU_CORTEX_R52_CACHE_SEGREGATION + range 0 4 + default 0 + help + Configure L1 I-Cache ways for Flash interface. Default is reset value, all + I-Cache ways are allocated for AXIM interface. + +config CPU_CORTEX_R52_DCACHE_FLASH_WAY + int "L1 D-Cache Flash way" + depends on CPU_CORTEX_R52_CACHE_SEGREGATION + range 0 4 + default 0 + help + Configure L1 D-Cache ways for Flash interface. Default is reset value, + all D-Cache ways are allocated for AXIM interface. + if CPU_AARCH32_CORTEX_R config ARMV7_R diff --git a/arch/arm/core/cortex_a_r/__aeabi_read_tp.S b/arch/arm/core/cortex_a_r/__aeabi_read_tp.S index 40874c4a1fa..bafd7e8e3ec 100644 --- a/arch/arm/core/cortex_a_r/__aeabi_read_tp.S +++ b/arch/arm/core/cortex_a_r/__aeabi_read_tp.S @@ -14,5 +14,5 @@ SECTION_FUNC(text, __aeabi_read_tp) /* * TPIDRURW will be used as a base pointer point to TLS aera. */ - mrc 15, 0, r0, c13, c0, 2 + mrc p15, 0, r0, c13, c0, 2 bx lr diff --git a/arch/arm/core/cortex_a_r/prep_c.c b/arch/arm/core/cortex_a_r/prep_c.c index 74d0855a620..a10588a4927 100644 --- a/arch/arm/core/cortex_a_r/prep_c.c +++ b/arch/arm/core/cortex_a_r/prep_c.c @@ -1,5 +1,6 @@ /* * Copyright (c) 2013-2014 Wind River Systems, Inc. + * Copyright 2024 Arm Limited and/or its affiliates * * SPDX-License-Identifier: Apache-2.0 */ @@ -28,24 +29,6 @@ #include #endif -#if defined(__GNUC__) -/* - * GCC can detect if memcpy is passed a NULL argument, however one of - * the cases of relocate_vector_table() it is valid to pass NULL, so we - * suppress the warning for this case. We need to do this before - * string.h is included to get the declaration of memcpy. - */ -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wnonnull" -#endif - -#include - -#if defined(CONFIG_SW_VECTOR_RELAY) || defined(CONFIG_SW_VECTOR_RELAY_CLIENT) -Z_GENERIC_SECTION(.vt_pointer_section) __attribute__((used)) -void *_vector_table_pointer; -#endif - #ifdef CONFIG_ARM_MPU extern void z_arm_mpu_init(void); extern void z_arm_configure_static_mpu_regions(void); @@ -53,38 +36,6 @@ extern void z_arm_configure_static_mpu_regions(void); extern int z_arm_mmu_init(void); #endif -#if defined(CONFIG_AARCH32_ARMV8_R) - -#define VECTOR_ADDRESS ((uintptr_t)_vector_start) - -static inline void relocate_vector_table(void) -{ - write_sctlr(read_sctlr() & ~HIVECS); - write_vbar(VECTOR_ADDRESS & VBAR_MASK); - barrier_isync_fence_full(); -} - -#else -#define VECTOR_ADDRESS 0 - -void __weak relocate_vector_table(void) -{ -#if defined(CONFIG_XIP) && (CONFIG_FLASH_BASE_ADDRESS != 0) || \ - !defined(CONFIG_XIP) && (CONFIG_SRAM_BASE_ADDRESS != 0) - write_sctlr(read_sctlr() & ~HIVECS); - size_t vector_size = (size_t)_vector_end - (size_t)_vector_start; - (void)memcpy(VECTOR_ADDRESS, _vector_start, vector_size); -#elif defined(CONFIG_SW_VECTOR_RELAY) || defined(CONFIG_SW_VECTOR_RELAY_CLIENT) - _vector_table_pointer = _vector_start; -#endif -} - -#if defined(__GNUC__) -#pragma GCC diagnostic pop -#endif - -#endif /* CONFIG_AARCH32_ARMV8_R */ - #if defined(CONFIG_CPU_HAS_FPU) static inline void z_arm_floating_point_init(void) @@ -111,7 +62,6 @@ static inline void z_arm_floating_point_init(void) __set_CPACR(reg_val); barrier_isync_fence_full(); -#if !defined(CONFIG_FPU_SHARING) /* * FPEXC: Floating-Point Exception Control register * comp. ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition, @@ -133,7 +83,6 @@ static inline void z_arm_floating_point_init(void) */ __set_FPEXC(FPEXC_EN); #endif -#endif } #endif /* CONFIG_CPU_HAS_FPU */ @@ -155,7 +104,6 @@ void z_prep_c(void) /* Initialize tpidruro with our struct _cpu instance address */ write_tpidruro((uintptr_t)&_kernel.cpus[0]); - relocate_vector_table(); #if defined(CONFIG_CPU_HAS_FPU) z_arm_floating_point_init(); #endif diff --git a/arch/arm/core/cortex_a_r/reboot.c b/arch/arm/core/cortex_a_r/reboot.c index dac892cf518..b5cea619f09 100644 --- a/arch/arm/core/cortex_a_r/reboot.c +++ b/arch/arm/core/cortex_a_r/reboot.c @@ -1,5 +1,6 @@ /* * Copyright (c) 2013-2014 Wind River Systems, Inc. + * Copyright 2024 Arm Limited and/or its affiliates * * SPDX-License-Identifier: Apache-2.0 */ @@ -12,6 +13,56 @@ #include #include #include +#include + +#if defined(CONFIG_AARCH32_ARMV8_R) + +#define VECTOR_ADDRESS ((uintptr_t)_vector_start) + +static inline void relocate_vector_table(void) +{ + write_sctlr(read_sctlr() & ~HIVECS); + write_vbar(VECTOR_ADDRESS & VBAR_MASK); + barrier_isync_fence_full(); +} + +#else + +#if defined(__GNUC__) +/* + * GCC can detect if memcpy is passed a NULL argument, however one of + * the cases of relocate_vector_table() it is valid to pass NULL, so we + * suppress the warning for this case. We need to do this before + * string.h is included to get the declaration of memcpy. + */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wnonnull" +#endif /* __GNUC__ */ + +#include + +#define VECTOR_ADDRESS 0 + +void __weak relocate_vector_table(void) +{ +#if defined(CONFIG_XIP) && (CONFIG_FLASH_BASE_ADDRESS != 0) || \ + !defined(CONFIG_XIP) && (CONFIG_SRAM_BASE_ADDRESS != 0) + write_sctlr(read_sctlr() & ~HIVECS); + size_t vector_size = (size_t)_vector_end - (size_t)_vector_start; + (void)memcpy(VECTOR_ADDRESS, _vector_start, vector_size); +#endif +} + +#if defined(__GNUC__) +#pragma GCC diagnostic pop +#endif + +#endif /* !CONFIG_AARCH32_ARMV8_R */ + +void z_arm_relocate_vector_table(void) +{ + relocate_vector_table(); +} /** * diff --git a/arch/arm/core/cortex_a_r/reset.S b/arch/arm/core/cortex_a_r/reset.S index efb04d249ec..b5b899194e0 100644 --- a/arch/arm/core/cortex_a_r/reset.S +++ b/arch/arm/core/cortex_a_r/reset.S @@ -1,6 +1,7 @@ /* * Copyright (c) 2013-2014 Wind River Systems, Inc. * Copyright (c) 2019 Stephanos Ioannidis + * Copyright 2024 Arm Limited and/or its affiliates * * SPDX-License-Identifier: Apache-2.0 */ @@ -55,9 +56,12 @@ SECTION_SUBSEC_FUNC(TEXT, _reset_section, __start) cmp r0, #MODE_HYP bne EL1_Reset_Handler - /* Init HSCTLR see Armv8-R AArch32 architecture profile */ - ldr r0, =(HSCTLR_RES1 | SCTLR_I_BIT | SCTLR_C_BIT) - mcr p15, 4, r0, c1, c0, 0 + /* + * The HSCTLR register provides top-level control of system operation in Hyp mode. + * Since the OS is not running in Hyp mode, and considering the Armv8-R AArch32 + * architecture profile, there's no need to modify HSCTLR configuration unless + * Fast Interrupts need to be enabled. + */ /* Init HACTLR: Enable EL1 access to all IMP DEF registers */ ldr r0, =HACTLR_INIT @@ -199,6 +203,12 @@ EL1_Reset_Handler: #endif /* CONFIG_DCLS */ +#if defined(CONFIG_CPU_CORTEX_R52_CACHE_SEGREGATION) + ldr r0, =IMP_CSCTLR(CONFIG_CPU_CORTEX_R52_ICACHE_FLASH_WAY, + CONFIG_CPU_CORTEX_R52_DCACHE_FLASH_WAY) + mcr p15, 1, r0, c9, c1, 0 +#endif + ldr r0, =arm_cpu_boot_params #if CONFIG_MP_MAX_NUM_CPUS > 1 @@ -319,4 +329,6 @@ _primary_core: bl z_arm_tcm_disable_ecc #endif + bl z_arm_relocate_vector_table + bx r4 diff --git a/arch/arm/core/cortex_a_r/smp.c b/arch/arm/core/cortex_a_r/smp.c index 6579cb4adde..d0e31acb1ed 100644 --- a/arch/arm/core/cortex_a_r/smp.c +++ b/arch/arm/core/cortex_a_r/smp.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2023 Arm Limited (or its affiliates). All rights reserved. + * Copyright (c) 2023, 2024 Arm Limited (or its affiliates). * SPDX-License-Identifier: Apache-2.0 */ @@ -12,6 +12,7 @@ #include "zephyr/cache.h" #include "zephyr/kernel/thread_stack.h" #include "zephyr/toolchain/gcc.h" +#include #define INV_MPID UINT32_MAX @@ -139,10 +140,14 @@ void arch_cpu_start(int cpu_num, k_thread_stack_t *stack, int sz, arch_cpustart_ arm_cpu_boot_params.arg = arg; arm_cpu_boot_params.cpu_num = cpu_num; + /* we need the barrier here to make sure the above changes to + * arm_cpu_boot_params are completed before we set the mpid + */ + barrier_dsync_fence_full(); + /* store mpid last as this is our synchronization point */ arm_cpu_boot_params.mpid = cpu_mpid; - barrier_dsync_fence_full(); sys_cache_data_invd_range( (void *)&arm_cpu_boot_params, sizeof(arm_cpu_boot_params)); @@ -194,6 +199,10 @@ void arch_secondary_cpu_init(void) */ #endif +#ifdef CONFIG_SOC_PER_CORE_INIT_HOOK + soc_per_core_init_hook(); +#endif /* CONFIG_SOC_PER_CORE_INIT_HOOK */ + fn = arm_cpu_boot_params.fn; arg = arm_cpu_boot_params.arg; barrier_dsync_fence_full(); diff --git a/arch/arm/core/cortex_a_r/swap.c b/arch/arm/core/cortex_a_r/swap.c deleted file mode 100644 index 2f7faba741a..00000000000 --- a/arch/arm/core/cortex_a_r/swap.c +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (c) 2018 Linaro, Limited - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include - -#include - -/* The 'key' actually represents the BASEPRI register - * prior to disabling interrupts via the BASEPRI mechanism. - * - * arch_swap() itself does not do much. - */ -int arch_swap(unsigned int key) -{ - /* store off key and return value */ - _current->arch.basepri = key; - _current->arch.swap_return_value = -EAGAIN; - - z_arm_cortex_r_svc(); - irq_unlock(key); - - /* Context switch is performed here. Returning implies the - * thread has been context-switched-in again. - */ - return _current->arch.swap_return_value; -} diff --git a/arch/arm/core/cortex_a_r/swap_helper.S b/arch/arm/core/cortex_a_r/swap_helper.S index 548bb446aa3..a41e1ab5942 100644 --- a/arch/arm/core/cortex_a_r/swap_helper.S +++ b/arch/arm/core/cortex_a_r/swap_helper.S @@ -126,7 +126,7 @@ out_fp_inactive: * TPIDRURW is used as a base pointer to all * thread variables with offsets added by toolchain. */ - mcr 15, 0, r0, c13, c0, 2 + mcr p15, 0, r0, c13, c0, 2 #endif #if defined(CONFIG_ARM_STORE_EXC_RETURN) @@ -336,12 +336,14 @@ _context_switch: _oops: /* - * Pass the exception frame to z_do_kernel_oops. r0 contains the - * exception reason. + * Pass the exception frame to z_do_kernel_oops. */ cps #MODE_SYS mov r0, sp cps #MODE_SVC + /* Zero callee_regs and exc_return (only used on Cortex-M) */ + mov r1, #0 + mov r2, #0 bl z_do_kernel_oops b z_arm_int_exit diff --git a/arch/arm/core/cortex_a_r/switch.S b/arch/arm/core/cortex_a_r/switch.S index 800d46bbf94..4d5a6a627b1 100644 --- a/arch/arm/core/cortex_a_r/switch.S +++ b/arch/arm/core/cortex_a_r/switch.S @@ -150,10 +150,12 @@ offload: _oops: /* - * Pass the exception frame to z_do_kernel_oops. r0 contains the - * exception reason. + * Pass the exception frame to z_do_kernel_oops. */ mov r0, sp + /* Zero callee_regs and exc_return (only used on Cortex-M) */ + mov r1, #0 + mov r2, #0 bl z_do_kernel_oops inv: diff --git a/arch/arm/core/cortex_m/CMakeLists.txt b/arch/arm/core/cortex_m/CMakeLists.txt index b220e6c81e8..05723811929 100644 --- a/arch/arm/core/cortex_m/CMakeLists.txt +++ b/arch/arm/core/cortex_m/CMakeLists.txt @@ -11,7 +11,6 @@ zephyr_library_sources( scb.c thread_abort.c vector_table.S - swap.c swap_helper.S irq_manage.c prep_c.c diff --git a/arch/arm/core/cortex_m/fault.c b/arch/arm/core/cortex_m/fault.c index 4e604ba8033..56d5be60f4c 100644 --- a/arch/arm/core/cortex_m/fault.c +++ b/arch/arm/core/cortex_m/fault.c @@ -35,59 +35,11 @@ LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL); #define PR_FAULT_INFO(...) #endif -#if defined(CONFIG_ARM_MPU) && defined(CONFIG_CPU_HAS_NXP_MPU) +#if defined(CONFIG_ARM_MPU) && defined(CONFIG_CPU_HAS_NXP_SYSMPU) #define EMN(edr) (((edr) & SYSMPU_EDR_EMN_MASK) >> SYSMPU_EDR_EMN_SHIFT) #define EACD(edr) (((edr) & SYSMPU_EDR_EACD_MASK) >> SYSMPU_EDR_EACD_SHIFT) #endif -/* Exception Return (EXC_RETURN) is provided in LR upon exception entry. - * It is used to perform an exception return and to detect possible state - * transition upon exception. - */ - -/* Prefix. Indicates that this is an EXC_RETURN value. - * This field reads as 0b11111111. - */ -#define EXC_RETURN_INDICATOR_PREFIX (0xFF << 24) -/* bit[0]: Exception Secure. The security domain the exception was taken to. */ -#define EXC_RETURN_EXCEPTION_SECURE_Pos 0 -#define EXC_RETURN_EXCEPTION_SECURE_Msk \ - BIT(EXC_RETURN_EXCEPTION_SECURE_Pos) -#define EXC_RETURN_EXCEPTION_SECURE_Non_Secure 0 -#define EXC_RETURN_EXCEPTION_SECURE_Secure EXC_RETURN_EXCEPTION_SECURE_Msk -/* bit[2]: Stack Pointer selection. */ -#define EXC_RETURN_SPSEL_Pos 2 -#define EXC_RETURN_SPSEL_Msk BIT(EXC_RETURN_SPSEL_Pos) -#define EXC_RETURN_SPSEL_MAIN 0 -#define EXC_RETURN_SPSEL_PROCESS EXC_RETURN_SPSEL_Msk -/* bit[3]: Mode. Indicates the Mode that was stacked from. */ -#define EXC_RETURN_MODE_Pos 3 -#define EXC_RETURN_MODE_Msk BIT(EXC_RETURN_MODE_Pos) -#define EXC_RETURN_MODE_HANDLER 0 -#define EXC_RETURN_MODE_THREAD EXC_RETURN_MODE_Msk -/* bit[4]: Stack frame type. Indicates whether the stack frame is a standard - * integer only stack frame or an extended floating-point stack frame. - */ -#define EXC_RETURN_STACK_FRAME_TYPE_Pos 4 -#define EXC_RETURN_STACK_FRAME_TYPE_Msk BIT(EXC_RETURN_STACK_FRAME_TYPE_Pos) -#define EXC_RETURN_STACK_FRAME_TYPE_EXTENDED 0 -#define EXC_RETURN_STACK_FRAME_TYPE_STANDARD EXC_RETURN_STACK_FRAME_TYPE_Msk -/* bit[5]: Default callee register stacking. Indicates whether the default - * stacking rules apply, or whether the callee registers are already on the - * stack. - */ -#define EXC_RETURN_CALLEE_STACK_Pos 5 -#define EXC_RETURN_CALLEE_STACK_Msk BIT(EXC_RETURN_CALLEE_STACK_Pos) -#define EXC_RETURN_CALLEE_STACK_SKIPPED 0 -#define EXC_RETURN_CALLEE_STACK_DEFAULT EXC_RETURN_CALLEE_STACK_Msk -/* bit[6]: Secure or Non-secure stack. Indicates whether a Secure or - * Non-secure stack is used to restore stack frame on exception return. - */ -#define EXC_RETURN_RETURN_STACK_Pos 6 -#define EXC_RETURN_RETURN_STACK_Msk BIT(EXC_RETURN_RETURN_STACK_Pos) -#define EXC_RETURN_RETURN_STACK_Non_Secure 0 -#define EXC_RETURN_RETURN_STACK_Secure EXC_RETURN_RETURN_STACK_Msk - /* Integrity signature for an ARMv8-M implementation */ #if defined(CONFIG_ARMV7_M_ARMV8_M_FP) #define INTEGRITY_SIGNATURE_STD 0xFEFA125BUL @@ -440,7 +392,7 @@ static int bus_fault(struct arch_esf *esf, int from_hard_fault, bool *recoverabl } #endif /* !defined(CONFIG_ARMV7_M_ARMV8_M_FP) */ -#if defined(CONFIG_ARM_MPU) && defined(CONFIG_CPU_HAS_NXP_MPU) +#if defined(CONFIG_ARM_MPU) && defined(CONFIG_CPU_HAS_NXP_SYSMPU) uint32_t sperr = SYSMPU->CESR & SYSMPU_CESR_SPERR_MASK; uint32_t mask = BIT(31); int i; @@ -475,7 +427,7 @@ static int bus_fault(struct arch_esf *esf, int from_hard_fault, bool *recoverabl /* Note: we can assume the fault originated * from the same security state for ARM * platforms implementing the NXP MPU - * (CONFIG_CPU_HAS_NXP_MPU=y). + * (CONFIG_CPU_HAS_NXP_SYSMPU=y). * * As we only assess thread stack corruption, * we only process the error further, if the @@ -531,7 +483,7 @@ static int bus_fault(struct arch_esf *esf, int from_hard_fault, bool *recoverabl } SYSMPU->CESR &= ~sperr; } -#endif /* defined(CONFIG_ARM_MPU) && defined(CONFIG_CPU_HAS_NXP_MPU) */ +#endif /* defined(CONFIG_ARM_MPU) && defined(CONFIG_CPU_HAS_NXP_SYSMPU) */ /* clear BFSR sticky bits */ SCB->CFSR |= SCB_CFSR_BUSFAULTSR_Msk; @@ -1112,9 +1064,7 @@ void z_arm_fault(uint32_t msp, uint32_t psp, uint32_t exc_return, __ASSERT(esf != NULL, "ESF could not be retrieved successfully. Shall never occur."); -#ifdef CONFIG_DEBUG_COREDUMP - z_arm_coredump_fault_sp = POINTER_TO_UINT(esf); -#endif + z_arm_set_fault_sp(esf, exc_return); reason = fault_handle(esf, fault, &recoverable); if (recoverable) { diff --git a/arch/arm/core/cortex_m/pm_s2ram.S b/arch/arm/core/cortex_m/pm_s2ram.S index aed8cf5b692..d15bfea0432 100644 --- a/arch/arm/core/cortex_m/pm_s2ram.S +++ b/arch/arm/core/cortex_m/pm_s2ram.S @@ -14,6 +14,145 @@ #include #include +/** + * Macro expanding to an integer literal equal to the offset of + * field `sr_name` in `struct __cpu_context`. This macro has to + * be implemented in C, because GEN_OFFSET_SYM provides offsets + * as C preprocessor definitions - there are not visible to the + * assembler. + * + * See also: `arch/arm/core/offsets/offsets_aarch32.c` + */ +#define CPU_CTX_SR_OFFSET(sr_name) \ + ___cpu_context_t_ ## sr_name ## _OFFSET + +/** + * Macros used to save / load a special register in __cpu_context. + * These also have to be implemented in C due to CPU_CTX_SR_OFFSET. + */ +#define SAVE_SPECIAL_REG(sr_name, cpu_ctx_reg, tmp_reg) \ + mrs tmp_reg, sr_name; \ + str tmp_reg, [cpu_ctx_reg, # CPU_CTX_SR_OFFSET(sr_name)]; + +#define RESTORE_SPECIAL_REG(sr_name, cpu_ctx_reg, tmp_reg) \ + ldr tmp_reg, [cpu_ctx_reg, # CPU_CTX_SR_OFFSET(sr_name)]; \ + msr sr_name, tmp_reg; + +/* + * The following macros could be written as assembler macros, but C is used + * for portability (assembler macro syntax may differ between toolchains). + */ + +/* + * Pushes registers r4~r12 and lr on the stack. + * r0 is unmodified but other GPRs may be overwritten. + */ +#if !defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE) +/* `push` on ARMv6-M / ARMv8-M Baseline: + * only r0~r7 and lr may be pushed + */ +#define PUSH_GPRS \ + push {r4-r7}; \ + mov r1, r8; \ + mov r2, r9; \ + mov r3, r10; \ + mov r4, r11; \ + mov r5, r12; \ + push {r1-r5, lr} +#else +/* `push` on ARMv7-M and ARMv8-M Mainline: no limitation */ +#define PUSH_GPRS \ + push {r4-r12, lr} +#endif /* !CONFIG_ARMV7_M_ARMV8_M_MAINLINE */ + +/* + * Pops registers r4~r12 and lr from the stack + * r0 is unmodified but other GPRs may be overwritten. + */ +#if !defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE) +/* `pop` on ARMv6-M / ARMv8-M Baseline: + * can only pop to r0~r7 and pc (not lr!) + */ +#define POP_GPRS \ + pop {r1-r6}; \ + mov lr, r6; \ + mov r12, r5; \ + mov r11, r4; \ + mov r10, r3; \ + mov r9, r2; \ + mov r8, r1; \ + pop {r4-r7} +#else +/* `pop` on ARMv7-M and ARMv8-M Mainline: no limitation */ +#define POP_GPRS \ + pop {r4-r12, lr} +#endif /* !CONFIG_ARMV7_M_ARMV8_M_MAINLINE */ + + +#if defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE) +/* Registers present only on ARMv7-M and ARMv8-M Mainline */ +#define SAVE_FM_BP_REGS(cpu_ctx, tmp_reg) \ + SAVE_SPECIAL_REG(faultmask, cpu_ctx, tmp_reg) \ + SAVE_SPECIAL_REG(basepri, cpu_ctx, tmp_reg) + +#define RESTORE_FM_BP_REGS(cpu_ctx, tmp_reg) \ + RESTORE_SPECIAL_REG(faultmask, cpu_ctx, tmp_reg) \ + RESTORE_SPECIAL_REG(basepri, cpu_ctx, tmp_reg) +#else +/* Registers not present: do nothing */ +#define SAVE_FM_BP_REGS(cpu_ctx, tmp_reg) +#define RESTORE_FM_BP_REGS(cpu_ctx, tmp_reg) +#endif /* CONFIG_ARMV7_M_ARMV8_M_MAINLINE */ + +#if defined(CONFIG_CPU_CORTEX_M_HAS_SPLIM) +/* Registers present only on certain ARMv8-M implementations */ +#define SAVE_SPLIM_REGS(cpu_ctx, tmp_reg) \ + SAVE_SPECIAL_REG(msplim, cpu_ctx, tmp_reg) \ + SAVE_SPECIAL_REG(psplim, cpu_ctx, tmp_reg) + +#define RESTORE_SPLIM_REGS(cpu_ctx, tmp_reg) \ + RESTORE_SPECIAL_REG(msplim, cpu_ctx, tmp_reg) \ + RESTORE_SPECIAL_REG(psplim, cpu_ctx, tmp_reg) +#else +/* Registers not present: do nothing */ +#define SAVE_SPLIM_REGS(cpu_ctx, tmp_reg) +#define RESTORE_SPLIM_REGS(cpu_ctx, tmp_reg) +#endif /* CONFIG_CPU_CORTEX_M_HAS_SPLIM */ + +/* + * Saves the CPU's special registers in the `struct __cpu_context` + * pointed to by the `cpu_ctx` register. + * The `tmp_reg` register is overwritten as part of this process. + */ +#define SAVE_SPECIAL_REGISTERS(cpu_ctx, tmp_reg) \ + SAVE_SPECIAL_REG(msp, cpu_ctx, tmp_reg) \ + SAVE_SPECIAL_REG(psp, cpu_ctx, tmp_reg) \ + SAVE_SPECIAL_REG(primask, cpu_ctx, tmp_reg) \ + SAVE_SPLIM_REGS( cpu_ctx, tmp_reg) \ + SAVE_FM_BP_REGS( cpu_ctx, tmp_reg) \ + SAVE_SPECIAL_REG(control, cpu_ctx, tmp_reg) + +/* + * Restores the CPU's special registers from the `struct __cpu_context` + * pointed to by the `cpu_ctx` register. + * The `tmp_reg` register is overwritten as part of this process. + * + * N.B.: ISB at the end is required because "Software must use an ISB + * barrier instruction to ensure a write to the CONTROL register takes + * effect before the next instruction is executed." + * + * If this macro is modified, make sure CONTROL is always the last + * restored register, and that an ISB follows the MSR instruction. + */ +#define RESTORE_SPECIAL_REGISTERS(cpu_ctx, tmp_reg) \ + RESTORE_SPECIAL_REG(msp, cpu_ctx, tmp_reg) \ + RESTORE_SPECIAL_REG(psp, cpu_ctx, tmp_reg) \ + RESTORE_SPECIAL_REG(primask, cpu_ctx, tmp_reg) \ + RESTORE_SPLIM_REGS( cpu_ctx, tmp_reg) \ + RESTORE_FM_BP_REGS( cpu_ctx, tmp_reg) \ + RESTORE_SPECIAL_REG(control, cpu_ctx, tmp_reg) \ + isb + _ASM_FILE_PROLOGUE GTEXT(pm_s2ram_mark_set) @@ -26,7 +165,7 @@ SECTION_FUNC(TEXT, arch_pm_s2ram_suspend) * * r0: address of the system_off function */ - push {r4-r12, lr} + PUSH_GPRS /* Move system_off to protected register. */ mov r4, r0 @@ -34,38 +173,7 @@ SECTION_FUNC(TEXT, arch_pm_s2ram_suspend) /* Store CPU context */ ldr r1, =_cpu_context - mrs r2, msp - str r2, [r1, #___cpu_context_t_msp_OFFSET] - - mrs r2, msplim - str r2, [r1, #___cpu_context_t_msplim_OFFSET] - - mrs r2, psp - str r2, [r1, #___cpu_context_t_psp_OFFSET] - - mrs r2, psplim - str r2, [r1, #___cpu_context_t_psplim_OFFSET] - - mrs r2, apsr - str r2, [r1, #___cpu_context_t_apsr_OFFSET] - - mrs r2, ipsr - str r2, [r1, #___cpu_context_t_ipsr_OFFSET] - - mrs r2, epsr - str r2, [r1, #___cpu_context_t_epsr_OFFSET] - - mrs r2, primask - str r2, [r1, #___cpu_context_t_primask_OFFSET] - - mrs r2, faultmask - str r2, [r1, #___cpu_context_t_faultmask_OFFSET] - - mrs r2, basepri - str r2, [r1, #___cpu_context_t_basepri_OFFSET] - - mrs r2, control - str r2, [r1, #___cpu_context_t_control_OFFSET] + SAVE_SPECIAL_REGISTERS(/* ctx: */ r1, /* tmp: */ r2) /* * Mark entering suspend to RAM. @@ -100,7 +208,7 @@ SECTION_FUNC(TEXT, arch_pm_s2ram_suspend) */ mov r0, r4 - pop {r4-r12, lr} + POP_GPRS bx lr @@ -122,44 +230,12 @@ resume: */ ldr r0, =_cpu_context - ldr r1, [r0, #___cpu_context_t_msp_OFFSET] - msr msp, r1 - - ldr r1, [r0, #___cpu_context_t_msplim_OFFSET] - msr msplim, r1 - - ldr r1, [r0, #___cpu_context_t_psp_OFFSET] - msr psp, r1 - - ldr r1, [r0, #___cpu_context_t_psplim_OFFSET] - msr psplim, r1 - - ldr r1, [r0, #___cpu_context_t_apsr_OFFSET] - msr apsr_nzcvq, r1 - - ldr r1, [r0, #___cpu_context_t_ipsr_OFFSET] - msr ipsr, r1 - - ldr r1, [r0, #___cpu_context_t_epsr_OFFSET] - msr epsr, r1 + RESTORE_SPECIAL_REGISTERS(/* ctx: */ r0, /* tmp: */ r1) - ldr r1, [r0, #___cpu_context_t_primask_OFFSET] - msr primask, r1 - - ldr r1, [r0, #___cpu_context_t_faultmask_OFFSET] - msr faultmask, r1 - - ldr r1, [r0, #___cpu_context_t_basepri_OFFSET] - msr basepri, r1 - - ldr r1, [r0, #___cpu_context_t_control_OFFSET] - msr control, r1 - isb - - pop {r4-r12, lr} + POP_GPRS /* * Set the return value and return */ - mov r0, #0 + movs r0, #0 bx lr diff --git a/arch/arm/core/cortex_m/prep_c.c b/arch/arm/core/cortex_m/prep_c.c index 10f78c44a25..ae59960584c 100644 --- a/arch/arm/core/cortex_m/prep_c.c +++ b/arch/arm/core/cortex_m/prep_c.c @@ -45,9 +45,16 @@ void *_vector_table_pointer; #define VECTOR_ADDRESS ((uintptr_t)_vector_start) +/* In some Cortex-M3 implementations SCB_VTOR bit[29] is called the TBLBASE bit */ +#ifdef SCB_VTOR_TBLBASE_Msk +#define VTOR_MASK (SCB_VTOR_TBLBASE_Msk | SCB_VTOR_TBLOFF_Msk) +#else +#define VTOR_MASK SCB_VTOR_TBLOFF_Msk +#endif + static inline void relocate_vector_table(void) { - SCB->VTOR = VECTOR_ADDRESS & SCB_VTOR_TBLOFF_Msk; + SCB->VTOR = VECTOR_ADDRESS & VTOR_MASK; barrier_dsync_fence_full(); barrier_isync_fence_full(); } diff --git a/arch/arm/core/cortex_m/scb.c b/arch/arm/core/cortex_m/scb.c index e3c35073ea3..a511a8de9b1 100644 --- a/arch/arm/core/cortex_m/scb.c +++ b/arch/arm/core/cortex_m/scb.c @@ -23,7 +23,7 @@ #include #include -#if defined(CONFIG_CPU_HAS_NXP_MPU) +#if defined(CONFIG_CPU_HAS_NXP_SYSMPU) #include #endif @@ -62,7 +62,7 @@ void z_arm_clear_arm_mpu_config(void) ARM_MPU_ClrRegion(i); } } -#elif CONFIG_CPU_HAS_NXP_MPU +#elif CONFIG_CPU_HAS_NXP_SYSMPU void z_arm_clear_arm_mpu_config(void) { int i; @@ -76,7 +76,7 @@ void z_arm_clear_arm_mpu_config(void) SYSMPU_RegionEnable(SYSMPU, i, false); } } -#endif /* CONFIG_CPU_HAS_NXP_MPU */ +#endif /* CONFIG_CPU_HAS_NXP_SYSMPU */ #endif /* CONFIG_ARM_MPU */ #if defined(CONFIG_INIT_ARCH_HW_AT_BOOT) diff --git a/arch/arm/core/cortex_m/swap.c b/arch/arm/core/cortex_m/swap.c deleted file mode 100644 index 027fb47a01f..00000000000 --- a/arch/arm/core/cortex_m/swap.c +++ /dev/null @@ -1,110 +0,0 @@ -/* - * Copyright (c) 2018 Linaro, Limited - * Copyright (c) 2023 Arm Limited - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include - -#include - -/* The 'key' actually represents the BASEPRI register - * prior to disabling interrupts via the BASEPRI mechanism. - * - * arch_swap() itself does not do much. - * - * It simply stores the intlock key (the BASEPRI value) parameter into - * current->basepri, and then triggers a PendSV exception, which does - * the heavy lifting of context switching. - - * This is the only place we have to save BASEPRI since the other paths to - * z_arm_pendsv all come from handling an interrupt, which means we know the - * interrupts were not locked: in that case the BASEPRI value is 0. - * - * Given that arch_swap() is called to effect a cooperative context switch, - * only the caller-saved integer registers need to be saved in the thread of the - * outgoing thread. This is all performed by the hardware, which stores it in - * its exception stack frame, created when handling the z_arm_pendsv exception. - * - * On ARMv6-M, the intlock key is represented by the PRIMASK register, - * as BASEPRI is not available. - */ -int arch_swap(unsigned int key) -{ - /* store off key and return value */ - _current->arch.basepri = key; - _current->arch.swap_return_value = -EAGAIN; - - /* set pending bit to make sure we will take a PendSV exception */ - SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk; - - /* clear mask or enable all irqs to take a pendsv */ - irq_unlock(0); - - /* Context switch is performed here. Returning implies the - * thread has been context-switched-in again. - */ - return _current->arch.swap_return_value; -} - -uintptr_t z_arm_pendsv_c(uintptr_t exc_ret) -{ - /* Store LSB of LR (EXC_RETURN) to the thread's 'mode' word. */ - IF_ENABLED(CONFIG_ARM_STORE_EXC_RETURN, - (_kernel.cpus[0].current->arch.mode_exc_return = (uint8_t)exc_ret;)); - - /* Protect the kernel state while we play with the thread lists */ - uint32_t basepri = arch_irq_lock(); - - /* fetch the thread to run from the ready queue cache */ - struct k_thread *current = _kernel.cpus[0].current = _kernel.ready_q.cache; - - /* - * Clear PendSV so that if another interrupt comes in and - * decides, with the new kernel state based on the new thread - * being context-switched in, that it needs to reschedule, it - * will take, but that previously pended PendSVs do not take, - * since they were based on the previous kernel state and this - * has been handled. - */ - SCB->ICSR = SCB_ICSR_PENDSVCLR_Msk; - - /* For Cortex-M, store TLS pointer in a global variable, - * as it lacks the process ID or thread ID register - * to be used by toolchain to access thread data. - */ - IF_ENABLED(CONFIG_THREAD_LOCAL_STORAGE, - (extern uintptr_t z_arm_tls_ptr; z_arm_tls_ptr = current->tls)); - - IF_ENABLED(CONFIG_ARM_STORE_EXC_RETURN, - (exc_ret = (exc_ret & 0xFFFFFF00) | current->arch.mode_exc_return)); - - /* Restore previous interrupt disable state (irq_lock key) - * (We clear the arch.basepri field after restoring state) - */ - basepri = current->arch.basepri; - current->arch.basepri = 0; - - arch_irq_unlock(basepri); - -#if defined(CONFIG_MPU_STACK_GUARD) || defined(CONFIG_USERSPACE) - /* Re-program dynamic memory map */ - z_arm_configure_dynamic_mpu_regions(current); -#endif - - /* restore mode */ - IF_ENABLED(CONFIG_USERSPACE, ({ - CONTROL_Type ctrl = {.w = __get_CONTROL()}; - /* exit privileged state when returning to thread mode. */ - ctrl.b.nPRIV = 0; - /* __set_CONTROL inserts an ISB which is may not be necessary here - * (stack pointer may not be touched), but it's recommended to avoid - * executing pre-fetched instructions with the previous privilege. - */ - __set_CONTROL(ctrl.w | current->arch.mode); - })); - - return exc_ret; -} diff --git a/arch/arm/core/cortex_m/swap_helper.S b/arch/arm/core/cortex_m/swap_helper.S index c2cb3ef7f2f..c6207084b5e 100644 --- a/arch/arm/core/cortex_m/swap_helper.S +++ b/arch/arm/core/cortex_m/swap_helper.S @@ -27,7 +27,6 @@ _ASM_FILE_PROLOGUE GTEXT(z_arm_svc) GTEXT(z_arm_pendsv) GTEXT(z_do_kernel_oops) -GTEXT(z_arm_pendsv_c) #if defined(CONFIG_USERSPACE) GTEXT(z_arm_do_syscall) #endif @@ -118,20 +117,125 @@ out_fp_endif: #error Unknown ARM architecture #endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */ - mov r4, lr - mov r0, lr - bl z_arm_pendsv_c - mov lr, r4 + /* Protect the kernel state while we play with the thread lists */ +#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) + cpsid i +#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE) + movs.n r0, #_EXC_IRQ_DEFAULT_PRIO + msr BASEPRI_MAX, r0 + isb /* Make the effect of disabling interrupts be realized immediately */ +#else +#error Unknown ARM architecture +#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */ - ldr r1, =_kernel - ldr r2, [r1, #_kernel_offset_to_current] + /* + * Prepare to clear PendSV with interrupts unlocked, but + * don't clear it yet. PendSV must not be cleared until + * the new thread is context-switched in since all decisions + * to pend PendSV have been taken with the current kernel + * state and this is what we're handling currently. + */ + ldr r7, =_SCS_ICSR + ldr r6, =_SCS_ICSR_UNPENDSV + + /* _kernel is still in r1 */ + + /* fetch the thread to run from the ready queue cache */ + ldr r2, [r1, #_kernel_offset_to_ready_q_cache] + + str r2, [r1, #_kernel_offset_to_current] + + /* + * Clear PendSV so that if another interrupt comes in and + * decides, with the new kernel state based on the new thread + * being context-switched in, that it needs to reschedule, it + * will take, but that previously pended PendSVs do not take, + * since they were based on the previous kernel state and this + * has been handled. + */ + + /* _SCS_ICSR is still in r7 and _SCS_ICSR_UNPENDSV in r6 */ + str r6, [r7, #0] + +#if defined(CONFIG_THREAD_LOCAL_STORAGE) + /* Grab the TLS pointer */ + ldr r4, =_thread_offset_to_tls + adds r4, r2, r4 + ldr r0, [r4] + + /* For Cortex-M, store TLS pointer in a global variable, + * as it lacks the process ID or thread ID register + * to be used by toolchain to access thread data. + */ + ldr r4, =z_arm_tls_ptr + str r0, [r4] +#endif #if defined(CONFIG_ARM_STORE_EXC_RETURN) /* Restore EXC_RETURN value. */ - mov lr, r0 + ldrsb lr, [r2, #_thread_offset_to_mode_exc_return] +#endif + + /* Restore previous interrupt disable state (irq_lock key) + * (We clear the arch.basepri field after restoring state) + */ +#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) && (_thread_offset_to_basepri > 124) + /* Doing it this way since the offset to thread->arch.basepri can in + * some configurations be larger than the maximum of 124 for ldr/str + * immediate offsets. + */ + ldr r4, =_thread_offset_to_basepri + adds r4, r2, r4 + + ldr r0, [r4] + movs.n r3, #0 + str r3, [r4] +#else + ldr r0, [r2, #_thread_offset_to_basepri] + movs r3, #0 + str r3, [r2, #_thread_offset_to_basepri] #endif #if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) + /* BASEPRI not available, previous interrupt disable state + * maps to PRIMASK. + * + * Only enable interrupts if value is 0, meaning interrupts + * were enabled before irq_lock was called. + */ + cmp r0, #0 + bne _thread_irq_disabled + cpsie i +_thread_irq_disabled: + +#if defined(CONFIG_MPU_STACK_GUARD) || defined(CONFIG_USERSPACE) + /* Re-program dynamic memory map */ + push {r2,lr} + mov r0, r2 + bl z_arm_configure_dynamic_mpu_regions + pop {r2,r3} + mov lr, r3 +#endif + +#ifdef CONFIG_USERSPACE + /* restore mode */ + ldr r3, =_thread_offset_to_mode + adds r3, r2, r3 + ldr r0, [r3] + mrs r3, CONTROL + movs.n r1, #1 + bics r3, r1 + orrs r3, r0 + msr CONTROL, r3 + + /* ISB is not strictly necessary here (stack pointer is not being + * touched), but it's recommended to avoid executing pre-fetched + * instructions with the previous privilege. + */ + isb + +#endif + ldr r4, =_thread_offset_to_callee_saved adds r0, r2, r4 @@ -149,6 +253,9 @@ out_fp_endif: subs r0, #36 ldmia r0!, {r4-r7} #elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE) + /* restore BASEPRI for the incoming thread */ + msr BASEPRI, r0 + #ifdef CONFIG_FPU_SHARING /* Assess whether switched-in thread had been using the FP registers. */ tst lr, #_EXC_RETURN_FTYPE_Msk @@ -178,6 +285,30 @@ in_fp_endif: isb #endif +#if defined(CONFIG_MPU_STACK_GUARD) || defined(CONFIG_USERSPACE) + /* Re-program dynamic memory map */ + push {r2,lr} + mov r0, r2 /* _current thread */ + bl z_arm_configure_dynamic_mpu_regions + pop {r2,lr} +#endif + +#ifdef CONFIG_USERSPACE + /* restore mode */ + ldr r0, [r2, #_thread_offset_to_mode] + mrs r3, CONTROL + bic r3, #1 + orr r3, r0 + msr CONTROL, r3 + + /* ISB is not strictly necessary here (stack pointer is not being + * touched), but it's recommended to avoid executing pre-fetched + * instructions with the previous privilege. + */ + isb + +#endif + /* load callee-saved + psp from thread */ add r0, r2, #_thread_offset_to_callee_saved ldmia r0, {r4-r11, ip} @@ -300,6 +431,7 @@ _stack_frame_endif: /* exception return is done in z_arm_int_exit() */ ldr r0, =z_arm_int_exit bx r0 + #endif _oops: @@ -315,6 +447,7 @@ _oops: mov r1, sp /* pointer to _callee_saved_t */ #endif /* CONFIG_ARMV7_M_ARMV8_M_MAINLINE */ #endif /* CONFIG_EXTRA_EXCEPTION_INFO */ + mov r2, lr /* EXC_RETURN */ bl z_do_kernel_oops /* return from SVC exception is done here */ #if defined(CONFIG_EXTRA_EXCEPTION_INFO) diff --git a/arch/arm/core/cortex_m/thread.c b/arch/arm/core/cortex_m/thread.c index fa500032d3c..c88fd8e41a0 100644 --- a/arch/arm/core/cortex_m/thread.c +++ b/arch/arm/core/cortex_m/thread.c @@ -522,7 +522,7 @@ void arch_switch_to_main_thread(struct k_thread *main_thread, char *stack_ptr, { z_arm_prepare_switch_to_main(); - _current = main_thread; + z_current_thread_set(main_thread); #if defined(CONFIG_THREAD_LOCAL_STORAGE) /* On Cortex-M, TLS uses a global variable as pointer to @@ -576,19 +576,19 @@ void arch_switch_to_main_thread(struct k_thread *main_thread, char *stack_ptr, "mov r4, %0\n" /* force _main to be stored in a register */ "msr PSP, %1\n" /* __set_PSP(stack_ptr) */ - "mov r0, #0\n" /* arch_irq_unlock(0) */ + "movs r0, #0\n" /* arch_irq_unlock(0) */ "ldr r3, =arch_irq_unlock_outlined\n" "blx r3\n" "mov r0, r4\n" /* z_thread_entry(_main, NULL, NULL, NULL) */ - "mov r1, #0\n" - "mov r2, #0\n" - "mov r3, #0\n" + "movs r1, #0\n" + "movs r2, #0\n" + "movs r3, #0\n" "ldr r4, =z_thread_entry\n" "bx r4\n" /* We don’t intend to return, so there is no need to link. */ - : "+r" (_main) - : "r" (stack_ptr) - : "r0", "r1", "r2", "r3", "r4", "ip", "lr"); + : + : "r" (_main), "r" (stack_ptr) + : "r0", "r1", "r2", "r3", "r4", "ip", "lr", "memory"); CODE_UNREACHABLE; } diff --git a/arch/arm/core/cortex_m/timing.c b/arch/arm/core/cortex_m/timing.c index 3b847af02ac..6cb157552ac 100644 --- a/arch/arm/core/cortex_m/timing.c +++ b/arch/arm/core/cortex_m/timing.c @@ -28,8 +28,7 @@ */ static inline uint64_t z_arm_dwt_freq_get(void) { -#if defined(CONFIG_SOC_FAMILY_NORDIC_NRF) || \ - defined(CONFIG_SOC_SERIES_IMXRT6XX) +#if defined(CONFIG_CMSIS_CORE_HAS_SYSTEM_CORE_CLOCK) /* * DWT frequency is taken directly from the * System Core clock (CPU) frequency, if the @@ -104,7 +103,7 @@ timing_t arch_timing_counter_get(void) uint64_t arch_timing_cycles_get(volatile timing_t *const start, volatile timing_t *const end) { - return (*end - *start); + return ((uint32_t)*end - (uint32_t)*start); } uint64_t arch_timing_freq_get(void) diff --git a/arch/arm/core/fatal.c b/arch/arm/core/fatal.c index 4532e238f05..d64855b6b8e 100644 --- a/arch/arm/core/fatal.c +++ b/arch/arm/core/fatal.c @@ -101,8 +101,9 @@ void z_arm_fatal_error(unsigned int reason, const struct arch_esf *esf) * * @param esf exception frame * @param callee_regs Callee-saved registers (R4-R11) + * @param exc_return EXC_RETURN value present in LR after exception entry. */ -void z_do_kernel_oops(const struct arch_esf *esf, _callee_saved_t *callee_regs) +void z_do_kernel_oops(const struct arch_esf *esf, _callee_saved_t *callee_regs, uint32_t exc_return) { #if !(defined(CONFIG_EXTRA_EXCEPTION_INFO) && defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)) ARG_UNUSED(callee_regs); @@ -110,6 +111,8 @@ void z_do_kernel_oops(const struct arch_esf *esf, _callee_saved_t *callee_regs) /* Stacked R0 holds the exception reason. */ unsigned int reason = esf->basic.r0; + z_arm_set_fault_sp(esf, exc_return); + #if defined(CONFIG_USERSPACE) if (z_arm_preempted_thread_in_user_mode(esf)) { /* diff --git a/arch/arm/core/mpu/CMakeLists.txt b/arch/arm/core/mpu/CMakeLists.txt index 1df6561ee52..69f23e5be88 100644 --- a/arch/arm/core/mpu/CMakeLists.txt +++ b/arch/arm/core/mpu/CMakeLists.txt @@ -4,11 +4,11 @@ zephyr_library() zephyr_library_sources( arm_core_mpu.c) zephyr_library_sources_ifdef(CONFIG_CPU_HAS_ARM_MPU arm_mpu.c) -zephyr_library_sources_ifdef(CONFIG_CPU_HAS_NXP_MPU nxp_mpu.c) +zephyr_library_sources_ifdef(CONFIG_CPU_HAS_NXP_SYSMPU nxp_mpu.c) if(CONFIG_CPU_CORTEX_M AND NOT CONFIG_CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS) zephyr_library_sources_ifdef(CONFIG_CPU_HAS_ARM_MPU arm_mpu_regions.c) - zephyr_library_sources_ifdef(CONFIG_CPU_HAS_NXP_MPU nxp_mpu_regions.c) + zephyr_library_sources_ifdef(CONFIG_CPU_HAS_NXP_SYSMPU nxp_mpu_regions.c) endif() if (CONFIG_CPU_AARCH32_CORTEX_R) diff --git a/arch/arm/core/mpu/Kconfig b/arch/arm/core/mpu/Kconfig index c6d1bdc7da0..0c1fbbf4c0f 100644 --- a/arch/arm/core/mpu/Kconfig +++ b/arch/arm/core/mpu/Kconfig @@ -11,7 +11,7 @@ config ARM_MPU select SRAM_REGION_PERMISSIONS select THREAD_STACK_INFO select ARCH_HAS_EXECUTABLE_PAGE_BIT - select MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT if !(CPU_HAS_NXP_MPU || ARMV8_M_BASELINE || ARMV8_M_MAINLINE || AARCH32_ARMV8_R) + select MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT if !(CPU_HAS_NXP_SYSMPU || ARMV8_M_BASELINE || ARMV8_M_MAINLINE || AARCH32_ARMV8_R) select MPU_REQUIRES_NON_OVERLAPPING_REGIONS if CPU_HAS_ARM_MPU && (ARMV8_M_BASELINE || ARMV8_M_MAINLINE || AARCH32_ARMV8_R) select MPU_GAP_FILLING if AARCH32_ARMV8_R select ARCH_MEM_DOMAIN_SUPPORTS_ISOLATED_STACKS diff --git a/arch/arm/core/mpu/arm_core_mpu_dev.h b/arch/arm/core/mpu/arm_core_mpu_dev.h index 254d6d9dda3..4e8fa648ad3 100644 --- a/arch/arm/core/mpu/arm_core_mpu_dev.h +++ b/arch/arm/core/mpu/arm_core_mpu_dev.h @@ -76,7 +76,7 @@ struct k_thread; */ #if (defined(CONFIG_MPU_REQUIRES_NON_OVERLAPPING_REGIONS) && \ defined(CONFIG_MPU_GAP_FILLING)) \ - || defined(CONFIG_CPU_HAS_NXP_MPU) + || defined(CONFIG_CPU_HAS_NXP_SYSMPU) /* * When dynamic regions may not be defined on top of statically * allocated memory regions, defining a region for a supervisor @@ -96,7 +96,7 @@ struct k_thread; * using a single MPU region. */ #define ARM_CORE_MPU_NUM_MPU_REGIONS_FOR_MPU_STACK_GUARD 1 -#endif /* CONFIG_MPU_REQUIRES_NON_OVERLAPPING_REGIONS || CPU_HAS_NXP_MPU */ +#endif /* CONFIG_MPU_REQUIRES_NON_OVERLAPPING_REGIONS || CPU_HAS_NXP_SYSMPU */ #endif /* CONFIG_USERSPACE */ diff --git a/arch/arm/core/mpu/arm_mpu.c b/arch/arm/core/mpu/arm_mpu.c index 3f9cf095754..f121e57e392 100644 --- a/arch/arm/core/mpu/arm_mpu.c +++ b/arch/arm/core/mpu/arm_mpu.c @@ -37,6 +37,13 @@ BUILD_ASSERT((DT_FOREACH_STATUS_OKAY_NODE_VARGS( NODE_HAS_PROP_AND_OR, zephyr_memory_region_mpu) false) == false, "`zephyr,memory-region-mpu` was deprecated in favor of `zephyr,memory-attr`"); +#define NULL_PAGE_DETECT_NODE_FINDER(node_id, prop) \ + (DT_NODE_HAS_PROP(node_id, prop) && (DT_REG_ADDR(node_id) == 0) && \ + (DT_REG_SIZE(node_id) >= CONFIG_CORTEX_M_NULL_POINTER_EXCEPTION_PAGE_SIZE)) || + +#define DT_NULL_PAGE_DETECT_NODE_EXIST \ + (DT_FOREACH_STATUS_OKAY_NODE_VARGS(NULL_PAGE_DETECT_NODE_FINDER, zephyr_memory_attr) false) + /* * Global status variable holding the number of HW MPU region indices, which * have been reserved by the MPU driver to program the static (fixed) memory @@ -470,7 +477,9 @@ int z_arm_mpu_init(void) */ #if defined(CONFIG_NULL_POINTER_EXCEPTION_DETECTION_MPU) #if (defined(CONFIG_ARMV8_M_BASELINE) || defined(CONFIG_ARMV8_M_MAINLINE)) && \ - (CONFIG_FLASH_BASE_ADDRESS > CONFIG_CORTEX_M_NULL_POINTER_EXCEPTION_PAGE_SIZE) + (CONFIG_FLASH_BASE_ADDRESS > CONFIG_CORTEX_M_NULL_POINTER_EXCEPTION_PAGE_SIZE) && \ + (!DT_NULL_PAGE_DETECT_NODE_EXIST) + #pragma message "Null-Pointer exception detection cannot be configured on un-mapped flash areas" #else const struct z_arm_mpu_partition unmap_region = { diff --git a/arch/arm/core/mpu/arm_mpu_regions.c b/arch/arm/core/mpu/arm_mpu_regions.c index cfe1230c907..383fd573513 100644 --- a/arch/arm/core/mpu/arm_mpu_regions.c +++ b/arch/arm/core/mpu/arm_mpu_regions.c @@ -13,6 +13,7 @@ #endif static const struct arm_mpu_region mpu_regions[] = { +#ifdef CONFIG_XIP /* Region 0 */ MPU_REGION_ENTRY("FLASH_0", CONFIG_FLASH_BASE_ADDRESS, @@ -22,6 +23,8 @@ static const struct arm_mpu_region mpu_regions[] = { #else REGION_FLASH_ATTR(REGION_FLASH_SIZE)), #endif +#endif + /* Region 1 */ MPU_REGION_ENTRY("SRAM_0", #if USE_PARTITION_MANAGER diff --git a/arch/arm/core/offsets/offsets_aarch32.c b/arch/arm/core/offsets/offsets_aarch32.c index 4399377134d..693546630b0 100644 --- a/arch/arm/core/offsets/offsets_aarch32.c +++ b/arch/arm/core/offsets/offsets_aarch32.c @@ -83,17 +83,21 @@ GEN_OFFSET_SYM(_thread_stack_info_t, start); */ #if defined(CONFIG_PM_S2RAM) GEN_OFFSET_SYM(_cpu_context_t, msp); -GEN_OFFSET_SYM(_cpu_context_t, msplim); GEN_OFFSET_SYM(_cpu_context_t, psp); -GEN_OFFSET_SYM(_cpu_context_t, psplim); -GEN_OFFSET_SYM(_cpu_context_t, apsr); -GEN_OFFSET_SYM(_cpu_context_t, ipsr); -GEN_OFFSET_SYM(_cpu_context_t, epsr); - GEN_OFFSET_SYM(_cpu_context_t, primask); +GEN_OFFSET_SYM(_cpu_context_t, control); + +#if defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE) +/* Registers present only on ARMv7-M and ARMv8-M Mainline */ GEN_OFFSET_SYM(_cpu_context_t, faultmask); GEN_OFFSET_SYM(_cpu_context_t, basepri); -GEN_OFFSET_SYM(_cpu_context_t, control); +#endif /* CONFIG_ARMV7_M_ARMV8_M_MAINLINE */ + +#if defined(CONFIG_CPU_CORTEX_M_HAS_SPLIM) +/* Registers present only on certain ARMv8-M implementations */ +GEN_OFFSET_SYM(_cpu_context_t, msplim); +GEN_OFFSET_SYM(_cpu_context_t, psplim); +#endif /* CONFIG_CPU_CORTEX_M_HAS_SPLIM */ #endif /* CONFIG_PM_S2RAM */ #endif /* _ARM_OFFSETS_INC_ */ diff --git a/arch/arm/include/cortex_a_r/exception.h b/arch/arm/include/cortex_a_r/exception.h index 6daa9c106ee..4326444f112 100644 --- a/arch/arm/include/cortex_a_r/exception.h +++ b/arch/arm/include/cortex_a_r/exception.h @@ -43,6 +43,15 @@ static ALWAYS_INLINE bool arch_is_in_nested_exception(const struct arch_esf *esf return (arch_curr_cpu()->arch.exc_depth > 1U) ? (true) : (false); } +/** + * @brief No current implementation where core dump is not supported + * + * @param esf exception frame + * @param exc_return EXC_RETURN value present in LR after exception entry. + */ +static ALWAYS_INLINE void z_arm_set_fault_sp(const struct arch_esf *esf, uint32_t exc_return) +{} + #if defined(CONFIG_USERSPACE) /* * This function is used by privileged code to determine if the thread diff --git a/arch/arm/include/cortex_a_r/kernel_arch_func.h b/arch/arm/include/cortex_a_r/kernel_arch_func.h index 3486d7d4d4e..7a100db07dd 100644 --- a/arch/arm/include/cortex_a_r/kernel_arch_func.h +++ b/arch/arm/include/cortex_a_r/kernel_arch_func.h @@ -20,6 +20,8 @@ #ifndef ZEPHYR_ARCH_ARM_INCLUDE_CORTEX_A_R_KERNEL_ARCH_FUNC_H_ #define ZEPHYR_ARCH_ARM_INCLUDE_CORTEX_A_R_KERNEL_ARCH_FUNC_H_ +#include + #ifdef __cplusplus extern "C" { #endif @@ -28,10 +30,28 @@ extern "C" { static ALWAYS_INLINE void arch_kernel_init(void) { +#ifdef CONFIG_SOC_PER_CORE_INIT_HOOK + soc_per_core_init_hook(); +#endif /* CONFIG_SOC_PER_CORE_INIT_HOOK */ } #ifndef CONFIG_USE_SWITCH +static ALWAYS_INLINE int arch_swap(unsigned int key) +{ + /* store off key and return value */ + _current->arch.basepri = key; + _current->arch.swap_return_value = -EAGAIN; + + z_arm_cortex_r_svc(); + irq_unlock(key); + + /* Context switch is performed here. Returning implies the + * thread has been context-switched-in again. + */ + return _current->arch.swap_return_value; +} + static ALWAYS_INLINE void arch_thread_return_value_set(struct k_thread *thread, unsigned int value) { diff --git a/arch/arm/include/cortex_m/exception.h b/arch/arm/include/cortex_m/exception.h index 89bdd4b83e9..c021d59d764 100644 --- a/arch/arm/include/cortex_m/exception.h +++ b/arch/arm/include/cortex_m/exception.h @@ -39,6 +39,54 @@ extern volatile irq_offload_routine_t offload_routine; */ #define AIRCR_VECT_KEY_PERMIT_WRITE 0x05FAUL +/* Exception Return (EXC_RETURN) is provided in LR upon exception entry. + * It is used to perform an exception return and to detect possible state + * transition upon exception. + */ + +/* Prefix. Indicates that this is an EXC_RETURN value. + * This field reads as 0b11111111. + */ +#define EXC_RETURN_INDICATOR_PREFIX (0xFF << 24) +/* bit[0]: Exception Secure. The security domain the exception was taken to. */ +#define EXC_RETURN_EXCEPTION_SECURE_Pos 0 +#define EXC_RETURN_EXCEPTION_SECURE_Msk \ + BIT(EXC_RETURN_EXCEPTION_SECURE_Pos) +#define EXC_RETURN_EXCEPTION_SECURE_Non_Secure 0 +#define EXC_RETURN_EXCEPTION_SECURE_Secure EXC_RETURN_EXCEPTION_SECURE_Msk +/* bit[2]: Stack Pointer selection. */ +#define EXC_RETURN_SPSEL_Pos 2 +#define EXC_RETURN_SPSEL_Msk BIT(EXC_RETURN_SPSEL_Pos) +#define EXC_RETURN_SPSEL_MAIN 0 +#define EXC_RETURN_SPSEL_PROCESS EXC_RETURN_SPSEL_Msk +/* bit[3]: Mode. Indicates the Mode that was stacked from. */ +#define EXC_RETURN_MODE_Pos 3 +#define EXC_RETURN_MODE_Msk BIT(EXC_RETURN_MODE_Pos) +#define EXC_RETURN_MODE_HANDLER 0 +#define EXC_RETURN_MODE_THREAD EXC_RETURN_MODE_Msk +/* bit[4]: Stack frame type. Indicates whether the stack frame is a standard + * integer only stack frame or an extended floating-point stack frame. + */ +#define EXC_RETURN_STACK_FRAME_TYPE_Pos 4 +#define EXC_RETURN_STACK_FRAME_TYPE_Msk BIT(EXC_RETURN_STACK_FRAME_TYPE_Pos) +#define EXC_RETURN_STACK_FRAME_TYPE_EXTENDED 0 +#define EXC_RETURN_STACK_FRAME_TYPE_STANDARD EXC_RETURN_STACK_FRAME_TYPE_Msk +/* bit[5]: Default callee register stacking. Indicates whether the default + * stacking rules apply, or whether the callee registers are already on the + * stack. + */ +#define EXC_RETURN_CALLEE_STACK_Pos 5 +#define EXC_RETURN_CALLEE_STACK_Msk BIT(EXC_RETURN_CALLEE_STACK_Pos) +#define EXC_RETURN_CALLEE_STACK_SKIPPED 0 +#define EXC_RETURN_CALLEE_STACK_DEFAULT EXC_RETURN_CALLEE_STACK_Msk +/* bit[6]: Secure or Non-secure stack. Indicates whether a Secure or + * Non-secure stack is used to restore stack frame on exception return. + */ +#define EXC_RETURN_RETURN_STACK_Pos 6 +#define EXC_RETURN_RETURN_STACK_Msk BIT(EXC_RETURN_RETURN_STACK_Pos) +#define EXC_RETURN_RETURN_STACK_Non_Secure 0 +#define EXC_RETURN_RETURN_STACK_Secure EXC_RETURN_RETURN_STACK_Msk + /* * The current executing vector is found in the IPSR register. All * IRQs and system exceptions are considered as interrupt context. @@ -184,6 +232,43 @@ static ALWAYS_INLINE void z_arm_clear_faults(void) #endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */ } +/** + * @brief Set z_arm_coredump_fault_sp to stack pointer value expected by GDB + * + * @param esf exception frame + * @param exc_return EXC_RETURN value present in LR after exception entry. + */ +static ALWAYS_INLINE void z_arm_set_fault_sp(const struct arch_esf *esf, uint32_t exc_return) +{ +#ifdef CONFIG_DEBUG_COREDUMP + z_arm_coredump_fault_sp = POINTER_TO_UINT(esf); +#if defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE) || defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) + /* Gdb expects a stack pointer that does not include the exception stack frame in order to + * unwind. So adjust the stack pointer accordingly. + */ + z_arm_coredump_fault_sp += sizeof(esf->basic); + +#if defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING) + /* Assess whether thread had been using the FP registers and add size of additional + * registers if necessary + */ + if ((exc_return & EXC_RETURN_STACK_FRAME_TYPE_STANDARD) == + EXC_RETURN_STACK_FRAME_TYPE_EXTENDED) { + z_arm_coredump_fault_sp += sizeof(esf->fpu); + } +#endif /* CONFIG_FPU && CONFIG_FPU_SHARING */ + +#if !(defined(CONFIG_ARMV8_M_MAINLINE) || defined(CONFIG_ARMV8_M_BASELINE)) + if ((esf->basic.xpsr & SCB_CCR_STKALIGN_Msk) == SCB_CCR_STKALIGN_Msk) { + /* Adjust stack alignment after PSR bit[9] detected */ + z_arm_coredump_fault_sp |= 0x4; + } +#endif /* !CONFIG_ARMV8_M_MAINLINE */ + +#endif /* CONFIG_ARMV7_M_ARMV8_M_MAINLINE || CONFIG_ARMV6_M_ARMV8_M_BASELINE */ +#endif /* CONFIG_DEBUG_COREDUMP */ +} + /** * @brief Assess whether a debug monitor event should be treated as an error * diff --git a/arch/arm/include/cortex_m/kernel_arch_func.h b/arch/arm/include/cortex_m/kernel_arch_func.h index 132c056c910..2a24103a32d 100644 --- a/arch/arm/include/cortex_m/kernel_arch_func.h +++ b/arch/arm/include/cortex_m/kernel_arch_func.h @@ -20,6 +20,8 @@ #ifndef ZEPHYR_ARCH_ARM_INCLUDE_CORTEX_M_KERNEL_ARCH_FUNC_H_ #define ZEPHYR_ARCH_ARM_INCLUDE_CORTEX_M_KERNEL_ARCH_FUNC_H_ +#include + #ifdef __cplusplus extern "C" { #endif @@ -53,6 +55,10 @@ static ALWAYS_INLINE void arch_kernel_init(void) */ z_arm_configure_static_mpu_regions(); #endif /* CONFIG_ARM_MPU */ + +#ifdef CONFIG_SOC_PER_CORE_INIT_HOOK + soc_per_core_init_hook(); +#endif /* CONFIG_SOC_PER_CORE_INIT_HOOK */ } static ALWAYS_INLINE void @@ -78,6 +84,25 @@ extern FUNC_NORETURN void z_arm_userspace_enter(k_thread_entry_t user_entry, extern void z_arm_fatal_error(unsigned int reason, const struct arch_esf *esf); +static ALWAYS_INLINE int arch_swap(unsigned int key) +{ + /* store off key and return value */ + _current->arch.basepri = key; + _current->arch.swap_return_value = -EAGAIN; + + /* set pending bit to make sure we will take a PendSV exception */ + SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk; + + /* clear mask or enable all irqs to take a pendsv */ + irq_unlock(0); + + /* Context switch is performed here. Returning implies the + * thread has been context-switched-in again. + */ + return _current->arch.swap_return_value; +} + + #endif /* _ASMLANGUAGE */ #ifdef __cplusplus diff --git a/arch/arm64/core/smp.c b/arch/arm64/core/smp.c index bbb7f963431..fd9d457ea7d 100644 --- a/arch/arm64/core/smp.c +++ b/arch/arm64/core/smp.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include #include "boot.h" @@ -163,6 +164,10 @@ void arch_secondary_cpu_init(int cpu_num) #endif #endif +#ifdef CONFIG_SOC_PER_CORE_INIT_HOOK + soc_per_core_init_hook(); +#endif /* CONFIG_SOC_PER_CORE_INIT_HOOK */ + fn = arm64_cpu_boot_params.fn; arg = arm64_cpu_boot_params.arg; barrier_dsync_fence_full(); diff --git a/arch/arm64/core/xen/enlighten.c b/arch/arm64/core/xen/enlighten.c index 91bf014b762..164947a09ff 100644 --- a/arch/arm64/core/xen/enlighten.c +++ b/arch/arm64/core/xen/enlighten.c @@ -42,7 +42,7 @@ static int xen_map_shared_info(const shared_info_t *shared_page) return HYPERVISOR_memory_op(XENMEM_add_to_physmap, &xatp); } -int xen_enlighten_init(void) +static int xen_enlighten_init(void) { int ret = 0; shared_info_t *info = (shared_info_t *) shared_info_buf; @@ -66,3 +66,5 @@ int xen_enlighten_init(void) return 0; } + +SYS_INIT(xen_enlighten_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE); diff --git a/arch/arm64/include/kernel_arch_func.h b/arch/arm64/include/kernel_arch_func.h index d2c346be1f0..f9a2ffb9821 100644 --- a/arch/arm64/include/kernel_arch_func.h +++ b/arch/arm64/include/kernel_arch_func.h @@ -22,19 +22,20 @@ #include +#include + #ifdef __cplusplus extern "C" { #endif #ifndef _ASMLANGUAGE -extern void xen_enlighten_init(void); - static ALWAYS_INLINE void arch_kernel_init(void) { -#ifdef CONFIG_XEN - xen_enlighten_init(); -#endif + +#ifdef CONFIG_SOC_PER_CORE_INIT_HOOK + soc_per_core_init_hook(); +#endif /* CONFIG_SOC_PER_CORE_INIT_HOOK */ } static inline void arch_switch(void *switch_to, void **switched_from) diff --git a/arch/common/nocache.ld b/arch/common/nocache.ld index 24e81cdefcf..a4e500e8b17 100644 --- a/arch/common/nocache.ld +++ b/arch/common/nocache.ld @@ -7,12 +7,6 @@ /* Copied from linker.ld */ -#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_nocache_ram), okay) -#define NOCACHE_REGION LINKER_DT_NODE_REGION_NAME_TOKEN(DT_CHOSEN(zephyr_nocache_ram)) -#else -#define NOCACHE_REGION RAMABLE_REGION -#endif - /* Non-cached region of RAM */ SECTION_DATA_PROLOGUE(_NOCACHE_SECTION_NAME,(NOLOAD),) { @@ -33,5 +27,5 @@ SECTION_DATA_PROLOGUE(_NOCACHE_SECTION_NAME,(NOLOAD),) MPU_ALIGN(_nocache_ram_size); #endif _nocache_ram_end = .; -} GROUP_DATA_LINK_IN(NOCACHE_REGION, NOCACHE_REGION) +} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION) _nocache_ram_size = _nocache_ram_end - _nocache_ram_start; diff --git a/arch/common/ramfunc.ld b/arch/common/ramfunc.ld index 3894dbfef43..45dea79d6b6 100644 --- a/arch/common/ramfunc.ld +++ b/arch/common/ramfunc.ld @@ -9,6 +9,7 @@ SECTION_DATA_PROLOGUE(.ramfunc,,) { + __ramfunc_region_start = .; MPU_ALIGN(__ramfunc_size); __ramfunc_start = .; *(.ramfunc) diff --git a/arch/mips/core/isr.S b/arch/mips/core/isr.S index 86d05d19833..f2f2f342053 100644 --- a/arch/mips/core/isr.S +++ b/arch/mips/core/isr.S @@ -70,6 +70,7 @@ GTEXT(_Fault) GTEXT(_k_neg_eagain) GTEXT(z_thread_mark_switched_in) +GTEXT(z_thread_mark_switched_out) /* exports */ GTEXT(__isr_vec) @@ -209,6 +210,9 @@ on_thread_stack: #endif /* CONFIG_PREEMPT_ENABLED */ reschedule: +#ifdef CONFIG_INSTRUMENT_THREAD_SWITCHING + jal z_thread_mark_switched_out +#endif /* * Check if the current thread is the same as the thread on the ready Q. If * so, do not reschedule. diff --git a/arch/mips/include/kernel_arch_func.h b/arch/mips/include/kernel_arch_func.h index b01cc1a4c65..63ed7a65cf2 100644 --- a/arch/mips/include/kernel_arch_func.h +++ b/arch/mips/include/kernel_arch_func.h @@ -19,6 +19,8 @@ #include +#include + #ifdef __cplusplus extern "C" { #endif @@ -26,6 +28,9 @@ extern "C" { #ifndef _ASMLANGUAGE static ALWAYS_INLINE void arch_kernel_init(void) { +#ifdef CONFIG_SOC_PER_CORE_INIT_HOOK + soc_per_core_init_hook(); +#endif /* CONFIG_SOC_PER_CORE_INIT_HOOK */ } static ALWAYS_INLINE void @@ -42,6 +47,8 @@ static inline bool arch_is_in_isr(void) return _current_cpu->nested != 0U; } +int arch_swap(unsigned int key); + #ifdef CONFIG_IRQ_OFFLOAD void z_irq_do_offload(void); #endif diff --git a/arch/nios2/core/timing.c b/arch/nios2/core/timing.c index 9deb469a07f..80ee73c6f06 100644 --- a/arch/nios2/core/timing.c +++ b/arch/nios2/core/timing.c @@ -41,7 +41,13 @@ timing_t arch_timing_counter_get(void) uint64_t arch_timing_cycles_get(volatile timing_t *const start, volatile timing_t *const end) { - return (*end - *start); + timing_t start_ = *start; + timing_t end_ = *end; + + if (end_ >= start_) { + return (end_ - start_); + } + return (end_ + NIOS2_SUBTRACT_CLOCK_CYCLES(start_)); } uint64_t arch_timing_freq_get(void) diff --git a/arch/nios2/include/kernel_arch_func.h b/arch/nios2/include/kernel_arch_func.h index 2df268a1c62..c325ea49b49 100644 --- a/arch/nios2/include/kernel_arch_func.h +++ b/arch/nios2/include/kernel_arch_func.h @@ -22,6 +22,8 @@ #include +#include + #ifdef __cplusplus extern "C" { #endif @@ -30,6 +32,9 @@ extern "C" { static ALWAYS_INLINE void arch_kernel_init(void) { +#ifdef CONFIG_SOC_PER_CORE_INIT_HOOK + soc_per_core_init_hook(); +#endif /* CONFIG_SOC_PER_CORE_INIT_HOOK */ } static ALWAYS_INLINE void @@ -46,6 +51,8 @@ static inline bool arch_is_in_isr(void) return _kernel.cpus[0].nested != 0U; } +int arch_swap(unsigned int key); + #ifdef CONFIG_IRQ_OFFLOAD void z_irq_do_offload(void); #endif diff --git a/arch/posix/core/swap.c b/arch/posix/core/swap.c index d4ec5e50b5e..cf13ab4d4d3 100644 --- a/arch/posix/core/swap.c +++ b/arch/posix/core/swap.c @@ -50,7 +50,7 @@ int arch_swap(unsigned int key) _current->callee_saved.thread_status; - _current = _kernel.ready_q.cache; + z_current_thread_set(_kernel.ready_q.cache); #if CONFIG_INSTRUMENT_THREAD_SWITCHING z_thread_mark_switched_in(); #endif @@ -94,7 +94,7 @@ void arch_switch_to_main_thread(struct k_thread *main_thread, char *stack_ptr, z_thread_mark_switched_out(); #endif - _current = _kernel.ready_q.cache; + z_current_thread_set(_kernel.ready_q.cache); #ifdef CONFIG_INSTRUMENT_THREAD_SWITCHING z_thread_mark_switched_in(); diff --git a/arch/posix/core/thread.c b/arch/posix/core/thread.c index 4e443e2283b..050d075fe57 100644 --- a/arch/posix/core/thread.c +++ b/arch/posix/core/thread.c @@ -96,6 +96,25 @@ void posix_arch_thread_entry(void *pa_thread_status) z_thread_entry(ptr->entry_point, ptr->arg1, ptr->arg2, ptr->arg3); } +#if defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING) +int arch_float_disable(struct k_thread *thread) +{ + ARG_UNUSED(thread); + + /* Posix always has FPU enabled so cannot be disabled */ + return -ENOTSUP; +} + +int arch_float_enable(struct k_thread *thread, unsigned int options) +{ + ARG_UNUSED(thread); + ARG_UNUSED(options); + + /* Posix always has FPU enabled so nothing to do here */ + return 0; +} +#endif /* CONFIG_FPU && CONFIG_FPU_SHARING */ + #if defined(CONFIG_ARCH_HAS_THREAD_ABORT) void z_impl_k_thread_abort(k_tid_t thread) { diff --git a/arch/posix/include/kernel_arch_func.h b/arch/posix/include/kernel_arch_func.h index bb8d36a089c..ceba8a85093 100644 --- a/arch/posix/include/kernel_arch_func.h +++ b/arch/posix/include/kernel_arch_func.h @@ -12,6 +12,8 @@ #include +#include + #ifndef _ASMLANGUAGE #ifdef __cplusplus @@ -20,7 +22,9 @@ extern "C" { static inline void arch_kernel_init(void) { - /* Nothing to be done */ +#ifdef CONFIG_SOC_PER_CORE_INIT_HOOK + soc_per_core_init_hook(); +#endif /* CONFIG_SOC_PER_CORE_INIT_HOOK */ } static ALWAYS_INLINE void @@ -38,6 +42,8 @@ static inline bool arch_is_in_isr(void) return _kernel.cpus[0].nested != 0U; } +int arch_swap(unsigned int key); + #endif /* _ASMLANGUAGE */ #endif /* ZEPHYR_ARCH_POSIX_INCLUDE_KERNEL_ARCH_FUNC_H_ */ diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 8f524c23fc1..83e3ef86d07 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -1,4 +1,5 @@ # Copyright (c) 2016 Jean-Paul Etienne +# Copyright (c) 2024 Antmicro # SPDX-License-Identifier: Apache-2.0 menu "RISCV Options" @@ -15,9 +16,13 @@ config FLOAT_HARD help This option enables the hard-float calling convention. +choice RISCV_GP_PURPOSE + prompt "Purpose of the global pointer (GP) register" + default RISCV_GP if RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING + config RISCV_GP bool "RISC-V global pointer relative addressing" - default n + depends on RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING help Use global pointer relative addressing for small globals declared anywhere in the executable. It can benefit performance and reduce @@ -27,6 +32,17 @@ config RISCV_GP global pointer at program start or earlier than any instruction using GP relative addressing. +config RISCV_CURRENT_VIA_GP + bool "Store current thread into the global pointer (GP) register" + depends on MP_MAX_NUM_CPUS > 1 + select ARCH_HAS_CUSTOM_CURRENT_IMPL + help + Store the current thread's pointer into the global pointer (GP) register. + When is enabled, calls to `_current` & `k_sched_current_thread_query()` will + be reduced to a single register read. + +endchoice # RISCV_GP_PURPOSE + config RISCV_ALWAYS_SWITCH_THROUGH_ECALL bool "Do not use mret outside a trap handler context" depends on MULTITHREADING @@ -37,6 +53,31 @@ config RISCV_ALWAYS_SWITCH_THROUGH_ECALL and most people should say n here to minimize context switching overhead. +choice RISCV_SMP_IPI_IMPL + prompt "RISC-V SMP IPI implementation" + depends on SMP + default RISCV_SMP_IPI_CLINT if DT_HAS_SIFIVE_CLINT0_ENABLED + default RISCV_SMP_IPI_CUSTOM + +config RISCV_SMP_IPI_CLINT + bool "CLINT-based IPI" + depends on DT_HAS_SIFIVE_CLINT0_ENABLED + help + Use CLINT-based IPI implementation. + +config RISCV_SMP_IPI_CUSTOM + bool "Custom IPI implementation" + help + Allow custom IPI implementation. + + When this is selected, the following functions must be provided: + - arch_sched_directed_ipi() + - arch_flush_fpu_ipi() if CONFIG_FPU_SHARING + - arch_spin_relax() if CONFIG_FPU_SHARING + - arch_smp_init() + +endchoice # RISCV_SMP_IPI_IMPL + menu "RISCV Processor Options" config INCLUDE_RESET_VECTOR @@ -117,6 +158,12 @@ config RISCV_SOC_HAS_CUSTOM_SYS_IO the RISC-V SoC needs to do something different and more than reading and writing the registers. +config RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING + bool + help + Selected when SoC has implemented the initialization of global pointer (GP) + at program start, or earlier than any instruction using GP relative addressing. + config RISCV_SOC_CONTEXT_SAVE bool "SOC-based context saving in IRQ handlers" select RISCV_SOC_OFFSETS @@ -316,7 +363,6 @@ endif #RISCV_PMP config PMP_STACK_GUARD def_bool y - depends on MULTITHREADING depends on HW_STACK_PROTECTION config PMP_STACK_GUARD_MIN_SIZE @@ -355,6 +401,15 @@ config NULL_POINTER_EXCEPTION_REGION_SIZE endif # NULL_POINTER_EXCEPTION_DETECTION_PMP +config RISCV_IMPRECISE_FPU_STATE_TRACKING + bool "Imprecise implementation of FPU state tracking" + depends on FPU + help + According to the RISC-V Instruction Set Manual: Volume II, Version 20240411 + (Section 3.1.6.6), some implementations may choose to track the dirtiness of + the floating-point register state imprecisely by reporting the state to be + dirty even when it has not been modified. This option reflects that. + endmenu config MAIN_STACK_SIZE diff --git a/arch/riscv/core/CMakeLists.txt b/arch/riscv/core/CMakeLists.txt index 3e97d36d7f8..52a748c3247 100644 --- a/arch/riscv/core/CMakeLists.txt +++ b/arch/riscv/core/CMakeLists.txt @@ -17,6 +17,12 @@ if ((CONFIG_MP_MAX_NUM_CPUS GREATER 1) OR (CONFIG_SMP)) zephyr_library_sources(smp.c) endif () +if (CONFIG_SMP) + zephyr_library_sources(ipi.c) + + zephyr_library_sources_ifdef(CONFIG_RISCV_SMP_IPI_CLINT ipi_clint.c) +endif() + zephyr_library_sources_ifdef(CONFIG_FPU_SHARING fpu.c fpu.S) zephyr_library_sources_ifdef(CONFIG_DEBUG_COREDUMP coredump.c) zephyr_library_sources_ifdef(CONFIG_IRQ_OFFLOAD irq_offload.c) @@ -27,3 +33,4 @@ zephyr_library_sources_ifdef(CONFIG_USERSPACE userspace.S) zephyr_library_sources_ifdef(CONFIG_SEMIHOST semihost.c) zephyr_library_sources_ifdef(CONFIG_ARCH_STACKWALK stacktrace.c) zephyr_linker_sources(ROM_START SORT_KEY 0x0vectors vector_table.ld) +zephyr_library_sources_ifdef(CONFIG_LLEXT elf.c) diff --git a/arch/riscv/core/coredump.c b/arch/riscv/core/coredump.c index 70d7a9976d4..003c7b9fce9 100644 --- a/arch/riscv/core/coredump.c +++ b/arch/riscv/core/coredump.c @@ -5,6 +5,7 @@ */ #include +#include #include #ifndef CONFIG_64BIT @@ -116,3 +117,21 @@ uint16_t arch_coredump_tgt_code_get(void) { return COREDUMP_TGT_RISC_V; } + +#if defined(CONFIG_DEBUG_COREDUMP_DUMP_THREAD_PRIV_STACK) +void arch_coredump_priv_stack_dump(struct k_thread *thread) +{ + uintptr_t start_addr, end_addr; + + /* See: zephyr/include/zephyr/arch/riscv/arch.h */ + if (IS_ENABLED(CONFIG_PMP_POWER_OF_TWO_ALIGNMENT)) { + start_addr = thread->arch.priv_stack_start + Z_RISCV_STACK_GUARD_SIZE; + } else { + start_addr = thread->stack_info.start - CONFIG_PRIVILEGED_STACK_SIZE; + } + end_addr = Z_STACK_PTR_ALIGN(thread->arch.priv_stack_start + K_KERNEL_STACK_RESERVED + + CONFIG_PRIVILEGED_STACK_SIZE); + + coredump_memory_dump(start_addr, end_addr); +} +#endif /* CONFIG_DEBUG_COREDUMP_DUMP_THREAD_PRIV_STACK */ diff --git a/arch/riscv/core/elf.c b/arch/riscv/core/elf.c new file mode 100644 index 00000000000..4f981083b94 --- /dev/null +++ b/arch/riscv/core/elf.c @@ -0,0 +1,373 @@ +/** @file + * @brief Architecture-specific relocations for RISC-V instruction sets. + */ +/* + * Copyright (c) 2024 CISPA Helmholtz Center for Information Security gGmbH + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include +#include +#include +#include + +#include + +#include + +LOG_MODULE_REGISTER(elf, CONFIG_LLEXT_LOG_LEVEL); + +/* + * RISC-V relocations commonly use pairs of U-type and I-type instructions. + * U-type instructions have 20-bit immediates, I-type instructions have 12-bit immediates. + * Immediates in RISC-V are always sign-extended. + * Thereby, this type of relocation can reach any address within a 2^31-1 byte range. + */ +#define RISCV_MAX_JUMP_DISTANCE_U_PLUS_I_TYPE INT32_MAX + +/* S-type has 12-bit signed immediate */ +#define RISCV_MAX_JUMP_DISTANCE_S_TYPE ((1 << 11) - 1) + +/* I-type has 12-bit signed immediate also */ +#define RISCV_MAX_JUMP_DISTANCE_I_TYPE ((1 << 11) - 1) + +/* B-type has 13-bit signed immediate */ +#define RISCV_MAX_JUMP_DISTANCE_B_TYPE ((1 << 12) - 1) + +/* CB-type has 9-bit signed immediate */ +#define RISCV_MAX_JUMP_DISTANCE_CB_TYPE ((1 << 8) - 1) + +/* CJ-type has 12-bit signed immediate (last bit implicit 0) */ +#define RISCV_MAX_JUMP_DISTANCE_CJ_TYPE ((1 << 11) - 1) + +static inline int riscv_relocation_fits(long long jump_target, long long max_distance, + elf_word reloc_type) +{ + if (llabs(jump_target) > max_distance) { + LOG_ERR("%lld byte relocation is not possible for type %" PRIu64 " (max %lld)!", + jump_target, (uint64_t)reloc_type, max_distance); + return -ENOEXEC; /* jump too far */ + } + + return 0; +} + +static long long last_u_type_jump_target; + +/** + * @brief RISC-V specific function for relocating partially linked ELF binaries + * + * This implementation follows the official RISC-V specification: + * https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-elf.adoc + * + */ +int arch_elf_relocate(elf_rela_t *rel, uintptr_t loc_unsigned, uintptr_t sym_base_addr_unsigned, + const char *sym_name, uintptr_t load_bias) +{ + /* FIXME currently, RISC-V relocations all fit in ELF_32_R_TYPE */ + elf_word reloc_type = ELF32_R_TYPE(rel->r_info); + /* + * The RISC-V specification uses the following symbolic names for the relocations: + * + * A - addend (rel->r_addend) + * B - base address (load_bias) + * G - global offset table (not supported yet) + * P - position of the relocation (loc) + * S - symbol value (sym_base_addr) + * V - value at the relocation position (*loc) + * GP - value of __global_pointer$ (not supported yet) + * TLSMODULE - TLS module for the object (not supported yet) + * TLSOFFSET - TLS static block for the object (not supported yet) + */ + intptr_t loc = (intptr_t)loc_unsigned; + uint8_t *loc8 = (uint8_t *)loc, tmp8; + uint16_t *loc16 = (uint16_t *)loc, tmp16; + uint32_t *loc32 = (uint32_t *)loc, tmp32; + uint64_t *loc64 = (uint64_t *)loc, tmp64; + /* uint32_t or uint64_t */ + r_riscv_wordclass_t *loc_word = (r_riscv_wordclass_t *)loc; + uint32_t modified_operand; + uint16_t modified_compressed_operand; + int32_t imm8; + long long original_imm8, jump_target; + int16_t compressed_imm8; + __typeof__(rel->r_addend) target_alignment = 1; + const intptr_t sym_base_addr = (intptr_t)sym_base_addr_unsigned; + + LOG_DBG("Relocating symbol %s at %p with base address %p load address %p type %" PRIu64, + sym_name, (void *)loc, (void *)sym_base_addr, (void *)load_bias, + (uint64_t)reloc_type); + + /* FIXME not all types of relocations currently supported, especially TLS */ + + switch (reloc_type) { + case R_RISCV_NONE: + break; + case R_RISCV_32: + jump_target = sym_base_addr + rel->r_addend; /* S + A */ + UNALIGNED_PUT((uint32_t)jump_target, loc32); + return riscv_relocation_fits(jump_target, INT32_MAX, reloc_type); + case R_RISCV_64: + /* full 64-bit range, need no range check */ + UNALIGNED_PUT(sym_base_addr + rel->r_addend, loc64); /* S + A */ + break; + case R_RISCV_RELATIVE: + /* either full 32-bit or 64-bit range, need no range check */ + UNALIGNED_PUT(load_bias + rel->r_addend, loc_word); /* B + A */ + break; + case R_RISCV_JUMP_SLOT: + /* either full 32-bit or 64-bit range, need no range check */ + UNALIGNED_PUT(sym_base_addr, loc_word); /* S */ + break; + case R_RISCV_BRANCH: + jump_target = sym_base_addr + rel->r_addend - loc; /* S + A - P */ + modified_operand = UNALIGNED_GET(loc32); + imm8 = jump_target; + modified_operand = R_RISCV_CLEAR_BTYPE_IMM8(modified_operand); + modified_operand = R_RISCV_SET_BTYPE_IMM8(modified_operand, imm8); + UNALIGNED_PUT(modified_operand, loc32); + return riscv_relocation_fits(jump_target, RISCV_MAX_JUMP_DISTANCE_B_TYPE, + reloc_type); + case R_RISCV_JAL: + jump_target = sym_base_addr + rel->r_addend - loc; /* S + A - P */ + modified_operand = UNALIGNED_GET(loc32); + imm8 = jump_target; + modified_operand = R_RISCV_CLEAR_JTYPE_IMM8(modified_operand); + modified_operand = R_RISCV_SET_JTYPE_IMM8(modified_operand, imm8); + UNALIGNED_PUT(modified_operand, loc32); + return riscv_relocation_fits(jump_target, RISCV_MAX_JUMP_DISTANCE_U_PLUS_I_TYPE, + reloc_type); + case R_RISCV_CALL: + case R_RISCV_CALL_PLT: + case R_RISCV_PCREL_HI20: + modified_operand = UNALIGNED_GET(loc32); + jump_target = sym_base_addr + rel->r_addend - loc; /* S + A - P */ + imm8 = jump_target; + /* bit 12 of the immediate goes to I-type instruction and might + * change the sign of the number + */ + /* in order to avoid that, we add 1 to the upper immediate if bit 12 is one */ + /* see RISC-V la pseudo instruction */ + imm8 += imm8 & 0x800; + + original_imm8 = imm8; + + modified_operand = R_RISCV_CLEAR_UTYPE_IMM8(modified_operand); + modified_operand = R_RISCV_SET_UTYPE_IMM8(modified_operand, imm8); + UNALIGNED_PUT(modified_operand, loc32); + + if (reloc_type != R_RISCV_PCREL_HI20) { + /* PCREL_HI20 is only U-type, not truly U+I-type */ + /* for the others, need to also modify following I-type */ + loc32++; + + imm8 = jump_target; + + modified_operand = UNALIGNED_GET(loc32); + modified_operand = R_RISCV_CLEAR_ITYPE_IMM8(modified_operand); + modified_operand = R_RISCV_SET_ITYPE_IMM8(modified_operand, imm8); + UNALIGNED_PUT(modified_operand, loc32); + } + + last_u_type_jump_target = jump_target; + + return riscv_relocation_fits(jump_target, RISCV_MAX_JUMP_DISTANCE_U_PLUS_I_TYPE, + reloc_type); + case R_RISCV_PCREL_LO12_I: + /* need the same jump target as preceding U-type relocation */ + if (last_u_type_jump_target == 0) { + LOG_ERR("R_RISCV_PCREL_LO12_I relocation without preceding U-type " + "relocation!"); + return -ENOEXEC; + } + modified_operand = UNALIGNED_GET(loc32); + jump_target = last_u_type_jump_target; /* S - P */ + last_u_type_jump_target = 0; + imm8 = jump_target; + modified_operand = R_RISCV_CLEAR_ITYPE_IMM8(modified_operand); + modified_operand = R_RISCV_SET_ITYPE_IMM8(modified_operand, imm8); + UNALIGNED_PUT(modified_operand, loc32); + return riscv_relocation_fits(jump_target, RISCV_MAX_JUMP_DISTANCE_U_PLUS_I_TYPE, + reloc_type); + break; + case R_RISCV_PCREL_LO12_S: + /* need the same jump target as preceding U-type relocation */ + if (last_u_type_jump_target == 0) { + LOG_ERR("R_RISCV_PCREL_LO12_I relocation without preceding U-type " + "relocation!"); + return -ENOEXEC; + } + modified_operand = UNALIGNED_GET(loc32); + jump_target = last_u_type_jump_target; /* S - P */ + last_u_type_jump_target = 0; + imm8 = jump_target; + modified_operand = R_RISCV_CLEAR_STYPE_IMM8(modified_operand); + modified_operand = R_RISCV_SET_STYPE_IMM8(modified_operand, imm8); + UNALIGNED_PUT(modified_operand, loc32); + return riscv_relocation_fits(jump_target, RISCV_MAX_JUMP_DISTANCE_U_PLUS_I_TYPE, + reloc_type); + case R_RISCV_HI20: + jump_target = sym_base_addr + rel->r_addend; /* S + A */ + modified_operand = UNALIGNED_GET(loc32); + imm8 = jump_target; + /* bit 12 of the immediate goes to I-type instruction and might + * change the sign of the number + */ + /* in order to avoid that, we add 1 to the upper immediate if bit 12 is one*/ + /* see RISC-V la pseudo instruction */ + original_imm8 = imm8; + imm8 += imm8 & 0x800; + modified_operand = R_RISCV_CLEAR_UTYPE_IMM8(modified_operand); + modified_operand = R_RISCV_SET_UTYPE_IMM8(modified_operand, imm8); + UNALIGNED_PUT(modified_operand, loc32); + return riscv_relocation_fits(jump_target, RISCV_MAX_JUMP_DISTANCE_U_PLUS_I_TYPE, + reloc_type); + case R_RISCV_LO12_I: + modified_operand = UNALIGNED_GET(loc32); + jump_target = sym_base_addr + rel->r_addend; /* S + A */ + imm8 = jump_target; + /* this is always used with R_RISCV_HI20 */ + modified_operand = R_RISCV_CLEAR_ITYPE_IMM8(modified_operand); + modified_operand = R_RISCV_SET_ITYPE_IMM8(modified_operand, imm8); + UNALIGNED_PUT(modified_operand, loc32); + return riscv_relocation_fits(jump_target, RISCV_MAX_JUMP_DISTANCE_U_PLUS_I_TYPE, + reloc_type); + case R_RISCV_LO12_S: + modified_operand = UNALIGNED_GET(loc32); + imm8 = sym_base_addr + rel->r_addend; /* S + A */ + /* + * S-type is used for stores/loads etc. + * size check is done at compile time, as it depends on the size of + * the structure we are trying to load/store + */ + modified_operand = R_RISCV_CLEAR_STYPE_IMM8(modified_operand); + modified_operand = R_RISCV_SET_STYPE_IMM8(modified_operand, imm8); + UNALIGNED_PUT(modified_operand, loc32); + break; + /* for add/sub/set, compiler needs to ensure that the ELF sections are close enough */ + case R_RISCV_ADD8: + tmp8 = UNALIGNED_GET(loc8); + tmp8 += sym_base_addr + rel->r_addend; /* V + S + A */ + UNALIGNED_PUT(tmp8, loc8); + break; + case R_RISCV_ADD16: + tmp16 = UNALIGNED_GET(loc16); + tmp16 += sym_base_addr + rel->r_addend; /* V + S + A */ + UNALIGNED_PUT(tmp16, loc16); + break; + case R_RISCV_ADD32: + tmp32 = UNALIGNED_GET(loc32); + tmp32 += sym_base_addr + rel->r_addend; /* V + S + A */ + UNALIGNED_PUT(tmp32, loc32); + break; + case R_RISCV_ADD64: + tmp64 = UNALIGNED_GET(loc64); + tmp64 += sym_base_addr + rel->r_addend; /* V + S + A */ + UNALIGNED_PUT(tmp64, loc64); + break; + case R_RISCV_SUB8: + tmp8 = UNALIGNED_GET(loc8); + tmp8 -= sym_base_addr + rel->r_addend; /* V - S - A */ + UNALIGNED_PUT(tmp8, loc8); + break; + case R_RISCV_SUB16: + tmp16 = UNALIGNED_GET(loc16); + tmp16 -= sym_base_addr + rel->r_addend; /* V - S - A */ + UNALIGNED_PUT(tmp16, loc16); + break; + case R_RISCV_SUB32: + tmp32 = UNALIGNED_GET(loc32); + tmp32 -= sym_base_addr + rel->r_addend; /* V - S - A */ + UNALIGNED_PUT(tmp32, loc32); + break; + case R_RISCV_SUB64: + tmp64 = UNALIGNED_GET(loc64); + tmp64 -= sym_base_addr + rel->r_addend; /* V - S - A */ + UNALIGNED_PUT(tmp64, loc64); + break; + case R_RISCV_SUB6: + tmp8 = UNALIGNED_GET(loc8) & (0x1F); + UNALIGNED_PUT(tmp8, loc8); + tmp8 = tmp8 - sym_base_addr - rel->r_addend; /* V - S - A */ + tmp8 = tmp8 & (0x1F); + tmp8 = tmp8 | UNALIGNED_GET(loc8); + UNALIGNED_PUT(tmp8, loc8); + break; + case R_RISCV_SET6: + tmp8 = UNALIGNED_GET(loc8) & (0x1F); + UNALIGNED_PUT(tmp8, loc8); + tmp8 = sym_base_addr + rel->r_addend; /* S + A */ + tmp8 = tmp8 | UNALIGNED_GET(loc8); + UNALIGNED_PUT(tmp8, loc8); + break; + case R_RISCV_SET8: + tmp8 = sym_base_addr + rel->r_addend; /* S + A */ + UNALIGNED_PUT(tmp8, loc8); + break; + case R_RISCV_SET16: + tmp16 = sym_base_addr + rel->r_addend; /* S + A */ + UNALIGNED_PUT(tmp16, loc16); + break; + case R_RISCV_SET32: + tmp32 = sym_base_addr + rel->r_addend; /* S + A */ + UNALIGNED_PUT(tmp32, loc32); + break; + case R_RISCV_32_PCREL: + jump_target = sym_base_addr + rel->r_addend - loc; /* S + A - P */ + tmp32 = jump_target; + UNALIGNED_PUT(tmp32, loc32); + return riscv_relocation_fits(jump_target, RISCV_MAX_JUMP_DISTANCE_U_PLUS_I_TYPE, + reloc_type); + case R_RISCV_PLT32: + jump_target = sym_base_addr + rel->r_addend - loc; /* S + A - P */ + tmp32 = jump_target; + UNALIGNED_PUT(tmp32, loc32); + return riscv_relocation_fits(jump_target, RISCV_MAX_JUMP_DISTANCE_U_PLUS_I_TYPE, + reloc_type); + case R_RISCV_RVC_BRANCH: + jump_target = sym_base_addr + rel->r_addend - loc; /* S + A - P */ + modified_compressed_operand = UNALIGNED_GET(loc16); + compressed_imm8 = jump_target; + modified_compressed_operand = + R_RISCV_CLEAR_CBTYPE_IMM8(modified_compressed_operand); + modified_compressed_operand = + R_RISCV_SET_CBTYPE_IMM8(modified_compressed_operand, compressed_imm8); + UNALIGNED_PUT(modified_compressed_operand, loc16); + return riscv_relocation_fits(jump_target, RISCV_MAX_JUMP_DISTANCE_CB_TYPE, + reloc_type); + case R_RISCV_RVC_JUMP: + jump_target = sym_base_addr + rel->r_addend - loc; /* S + A - P */ + modified_compressed_operand = UNALIGNED_GET(loc16); + compressed_imm8 = jump_target; + modified_compressed_operand = + R_RISCV_CLEAR_CJTYPE_IMM8(modified_compressed_operand); + modified_compressed_operand = + R_RISCV_SET_CJTYPE_IMM8(modified_compressed_operand, compressed_imm8); + UNALIGNED_PUT(modified_compressed_operand, loc16); + return riscv_relocation_fits(jump_target, RISCV_MAX_JUMP_DISTANCE_CJ_TYPE, + reloc_type); + case R_RISCV_ALIGN: + /* we are supposed to move the symbol such that it is aligned to the next power of + * two >= addend + */ + /* this involves moving the symbol */ + while (target_alignment < rel->r_addend) { + target_alignment *= 2; + } + LOG_ERR("Symbol %s with location %p requires alignment to %" PRIu64 " bytes!", + sym_name, (void *)loc, (uint64_t)target_alignment); + LOG_ERR("Alignment relocation is currently not supported!"); + return -ENOEXEC; + /* ignored, this is primarily intended for removing instructions during link-time + * optimization + */ + case R_RISCV_RELAX: + break; + default: + LOG_ERR("Unsupported relocation type: %" PRIu64 " for symbol: %s", + (uint64_t)reloc_type, sym_name); + return -ENOEXEC; + } + + return 0; +} diff --git a/arch/riscv/core/fatal.c b/arch/riscv/core/fatal.c index d5cbd2f4dc1..879ffab9a80 100644 --- a/arch/riscv/core/fatal.c +++ b/arch/riscv/core/fatal.c @@ -172,11 +172,21 @@ static bool bad_stack_pointer(struct arch_esf *esf) } #endif /* CONFIG_USERSPACE */ +#if CONFIG_MULTITHREADING if (sp >= _current->stack_info.start - K_KERNEL_STACK_RESERVED && sp < _current->stack_info.start - K_KERNEL_STACK_RESERVED + Z_RISCV_STACK_GUARD_SIZE) { return true; } +#else + uintptr_t isr_stack = (uintptr_t)z_interrupt_stacks; + uintptr_t main_stack = (uintptr_t)z_main_stack; + + if ((sp >= isr_stack && sp < isr_stack + Z_RISCV_STACK_GUARD_SIZE) || + (sp >= main_stack && sp < main_stack + Z_RISCV_STACK_GUARD_SIZE)) { + return true; + } +#endif /* CONFIG_MULTITHREADING */ #endif /* CONFIG_PMP_STACK_GUARD */ #ifdef CONFIG_USERSPACE diff --git a/arch/riscv/core/ipi.c b/arch/riscv/core/ipi.c new file mode 100644 index 00000000000..c2683b61701 --- /dev/null +++ b/arch/riscv/core/ipi.c @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2021 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#include + +void arch_sched_broadcast_ipi(void) +{ + arch_sched_directed_ipi(IPI_ALL_CPUS_MASK); +} diff --git a/arch/riscv/core/ipi_clint.c b/arch/riscv/core/ipi_clint.c new file mode 100644 index 00000000000..e5f12566653 --- /dev/null +++ b/arch/riscv/core/ipi_clint.c @@ -0,0 +1,101 @@ +/* + * Copyright (c) 2021 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +#include + +#define CLINT_NODE DT_NODELABEL(clint) +#if !DT_NODE_EXISTS(CLINT_NODE) +#error "Label 'clint' is not defined in the devicetree." +#endif +#define MSIP_BASE DT_REG_ADDR_RAW(CLINT_NODE) +#define MSIP(hartid) ((volatile uint32_t *)MSIP_BASE)[hartid] + +static atomic_val_t cpu_pending_ipi[CONFIG_MP_MAX_NUM_CPUS]; +#define IPI_SCHED 0 +#define IPI_FPU_FLUSH 1 + +void arch_sched_directed_ipi(uint32_t cpu_bitmap) +{ + unsigned int key = arch_irq_lock(); + unsigned int id = _current_cpu->id; + unsigned int num_cpus = arch_num_cpus(); + + for (unsigned int i = 0; i < num_cpus; i++) { + if ((i != id) && _kernel.cpus[i].arch.online && ((cpu_bitmap & BIT(i)) != 0)) { + atomic_set_bit(&cpu_pending_ipi[i], IPI_SCHED); + MSIP(_kernel.cpus[i].arch.hartid) = 1; + } + } + + arch_irq_unlock(key); +} + +#ifdef CONFIG_FPU_SHARING +void arch_flush_fpu_ipi(unsigned int cpu) +{ + atomic_set_bit(&cpu_pending_ipi[cpu], IPI_FPU_FLUSH); + MSIP(_kernel.cpus[cpu].arch.hartid) = 1; +} +#endif /* CONFIG_FPU_SHARING */ + +static void sched_ipi_handler(const void *unused) +{ + ARG_UNUSED(unused); + + MSIP(csr_read(mhartid)) = 0; + + atomic_val_t pending_ipi = atomic_clear(&cpu_pending_ipi[_current_cpu->id]); + + if (pending_ipi & ATOMIC_MASK(IPI_SCHED)) { + z_sched_ipi(); + } +#ifdef CONFIG_FPU_SHARING + if (pending_ipi & ATOMIC_MASK(IPI_FPU_FLUSH)) { + /* disable IRQs */ + csr_clear(mstatus, MSTATUS_IEN); + /* perform the flush */ + arch_flush_local_fpu(); + /* + * No need to re-enable IRQs here as long as + * this remains the last case. + */ + } +#endif /* CONFIG_FPU_SHARING */ +} + +#ifdef CONFIG_FPU_SHARING +/* + * Make sure there is no pending FPU flush request for this CPU while + * waiting for a contended spinlock to become available. This prevents + * a deadlock when the lock we need is already taken by another CPU + * that also wants its FPU content to be reinstated while such content + * is still live in this CPU's FPU. + */ +void arch_spin_relax(void) +{ + atomic_val_t *pending_ipi = &cpu_pending_ipi[_current_cpu->id]; + + if (atomic_test_and_clear_bit(pending_ipi, IPI_FPU_FLUSH)) { + /* + * We may not be in IRQ context here hence cannot use + * arch_flush_local_fpu() directly. + */ + arch_float_disable(_current_cpu->arch.fpu_owner); + } +} +#endif /* CONFIG_FPU_SHARING */ + +int arch_smp_init(void) +{ + + IRQ_CONNECT(RISCV_IRQ_MSOFT, 0, sched_ipi_handler, NULL, 0); + irq_enable(RISCV_IRQ_MSOFT); + + return 0; +} diff --git a/arch/riscv/core/isr.S b/arch/riscv/core/isr.S index 7e885da93a4..11787d3b324 100644 --- a/arch/riscv/core/isr.S +++ b/arch/riscv/core/isr.S @@ -163,6 +163,16 @@ SECTION_FUNC(exception.entry, _isr_wrapper) lr t0, ___cpu_t_current_OFFSET(s0) lr tp, _thread_offset_to_tls(t0) + /* Make sure global pointer is sane */ +#ifdef CONFIG_RISCV_GP + .option push + .option norelax + la gp, __global_pointer$ + .option pop +#elif defined(CONFIG_RISCV_CURRENT_VIA_GP) + lr gp, ___cpu_t_current_OFFSET(s0) +#endif /* CONFIG_RISCV_GP / CONFIG_RISCV_CURRENT_VIA_GP */ + /* Clear our per-thread usermode flag */ lui t0, %tprel_hi(is_user_mode) add t0, t0, tp, %tprel_add(is_user_mode) @@ -348,7 +358,7 @@ no_fp: /* increment _current->arch.exception_depth */ li t1, RISCV_EXC_ECALLU beq t0, t1, is_user_syscall -#ifdef CONFIG_PMP_STACK_GUARD +#if defined(CONFIG_PMP_STACK_GUARD) && defined(CONFIG_MULTITHREADING) /* * Determine if we come from user space. If so, reconfigure the PMP for * kernel mode stack guard. @@ -389,7 +399,7 @@ is_kernel_syscall: addi t0, t0, 4 sr t0, __struct_arch_esf_mepc_OFFSET(sp) -#ifdef CONFIG_PMP_STACK_GUARD +#if defined(CONFIG_PMP_STACK_GUARD) && defined(CONFIG_MULTITHREADING) /* Re-activate PMP for m-mode */ li t1, MSTATUS_MPP csrc mstatus, t1 @@ -443,6 +453,12 @@ do_fault: 1: mv a1, sp #ifdef CONFIG_EXCEPTION_DEBUG + /* + * Restore the s0 we saved early in ISR entry + * so it shows up properly in the CSF. + */ + lr s0, __struct_arch_esf_s0_OFFSET(sp) + /* Allocate space for caller-saved registers on current thread stack */ addi sp, sp, -__callee_saved_t_SIZEOF @@ -494,7 +510,7 @@ do_irq_offload: #ifdef CONFIG_USERSPACE is_user_syscall: -#ifdef CONFIG_PMP_STACK_GUARD +#if defined(CONFIG_PMP_STACK_GUARD) && defined(CONFIG_MULTITHREADING) /* * We came from userspace and need to reconfigure the * PMP for kernel mode stack guard. @@ -564,7 +580,7 @@ valid_syscall_id: is_interrupt: -#ifdef CONFIG_PMP_STACK_GUARD +#if defined(CONFIG_PMP_STACK_GUARD) && defined(CONFIG_MULTITHREADING) #ifdef CONFIG_USERSPACE /* * If we came from userspace then we need to reconfigure the @@ -734,7 +750,7 @@ fp_trap_exit: and t0, t2, t1 bnez t0, 1f -#ifdef CONFIG_PMP_STACK_GUARD +#if defined(CONFIG_PMP_STACK_GUARD) && defined(CONFIG_MULTITHREADING) /* Remove kernel stack guard and Reconfigure PMP for user mode */ lr a0, ___cpu_t_current_OFFSET(s0) call z_riscv_pmp_usermode_enable diff --git a/arch/riscv/core/pmp.c b/arch/riscv/core/pmp.c index e41eb8d4bb0..e29c8abd76d 100644 --- a/arch/riscv/core/pmp.c +++ b/arch/riscv/core/pmp.c @@ -348,8 +348,8 @@ static unsigned int global_pmp_end_index; */ void z_riscv_pmp_init(void) { - unsigned long pmp_addr[5]; - unsigned long pmp_cfg[2]; + unsigned long pmp_addr[CONFIG_PMP_SLOTS]; + unsigned long pmp_cfg[CONFIG_PMP_SLOTS / PMPCFG_STRIDE]; unsigned int index = 0; /* The read-only area is always there for every mode */ @@ -370,6 +370,7 @@ void z_riscv_pmp_init(void) #endif #ifdef CONFIG_PMP_STACK_GUARD +#ifdef CONFIG_MULTITHREADING /* * Set the stack guard for this CPU's IRQ stack by making the bottom * addresses inaccessible. This will never change so we do it here @@ -396,6 +397,21 @@ void z_riscv_pmp_init(void) /* And forget about that last entry as we won't need it later */ index--; +#else + /* Without multithreading setup stack guards for IRQ and main stacks */ + set_pmp_entry(&index, PMP_NONE | PMP_L, + (uintptr_t)z_interrupt_stacks, + Z_RISCV_STACK_GUARD_SIZE, + pmp_addr, pmp_cfg, ARRAY_SIZE(pmp_addr)); + + set_pmp_entry(&index, PMP_NONE | PMP_L, + (uintptr_t)z_main_stack, + Z_RISCV_STACK_GUARD_SIZE, + pmp_addr, pmp_cfg, ARRAY_SIZE(pmp_addr)); + + /* Write those entries to PMP regs. */ + write_pmp_entries(0, index, true, pmp_addr, pmp_cfg, ARRAY_SIZE(pmp_addr)); +#endif /* CONFIG_MULTITHREADING */ #else /* Write those entries to PMP regs. */ write_pmp_entries(0, index, true, pmp_addr, pmp_cfg, ARRAY_SIZE(pmp_addr)); @@ -419,7 +435,6 @@ void z_riscv_pmp_init(void) } #endif - __ASSERT(index <= PMPCFG_STRIDE, "provision for one global word only"); global_pmp_cfg[0] = pmp_cfg[0]; global_pmp_last_addr = pmp_addr[index - 1]; global_pmp_end_index = index; @@ -454,6 +469,7 @@ static inline unsigned int z_riscv_pmp_thread_init(unsigned long *pmp_addr, #ifdef CONFIG_PMP_STACK_GUARD +#ifdef CONFIG_MULTITHREADING /** * @brief Prepare the PMP stackguard content for given thread. * @@ -511,6 +527,8 @@ void z_riscv_pmp_stackguard_enable(struct k_thread *thread) csr_set(mstatus, MSTATUS_MPRV); } +#endif /* CONFIG_MULTITHREADING */ + /** * @brief Remove PMP stackguard content to actual PMP registers */ diff --git a/arch/riscv/core/smp.c b/arch/riscv/core/smp.c index 4ef287c4a7a..8607215cab3 100644 --- a/arch/riscv/core/smp.c +++ b/arch/riscv/core/smp.c @@ -7,11 +7,11 @@ #include #include #include -#include #include #include #include #include +#include volatile struct { arch_cpustart_t fn; @@ -74,102 +74,13 @@ void arch_secondary_cpu_init(int hartid) #endif #ifdef CONFIG_SMP irq_enable(RISCV_IRQ_MSOFT); -#endif +#endif /* CONFIG_SMP */ +#ifdef CONFIG_PLIC_IRQ_AFFINITY + /* Enable on secondary cores so that they can respond to PLIC */ + irq_enable(RISCV_IRQ_MEXT); +#endif /* CONFIG_PLIC_IRQ_AFFINITY */ +#ifdef CONFIG_SOC_PER_CORE_INIT_HOOK + soc_per_core_init_hook(); +#endif /* CONFIG_SOC_PER_CORE_INIT_HOOK */ riscv_cpu_init[cpu_num].fn(riscv_cpu_init[cpu_num].arg); } - -#ifdef CONFIG_SMP - -#define MSIP_BASE 0x2000000UL -#define MSIP(hartid) ((volatile uint32_t *)MSIP_BASE)[hartid] - -static atomic_val_t cpu_pending_ipi[CONFIG_MP_MAX_NUM_CPUS]; -#define IPI_SCHED 0 -#define IPI_FPU_FLUSH 1 - -void arch_sched_directed_ipi(uint32_t cpu_bitmap) -{ - unsigned int key = arch_irq_lock(); - unsigned int id = _current_cpu->id; - unsigned int num_cpus = arch_num_cpus(); - - for (unsigned int i = 0; i < num_cpus; i++) { - if ((i != id) && _kernel.cpus[i].arch.online && - ((cpu_bitmap & BIT(i)) != 0)) { - atomic_set_bit(&cpu_pending_ipi[i], IPI_SCHED); - MSIP(_kernel.cpus[i].arch.hartid) = 1; - } - } - - arch_irq_unlock(key); -} - -void arch_sched_broadcast_ipi(void) -{ - arch_sched_directed_ipi(IPI_ALL_CPUS_MASK); -} - -#ifdef CONFIG_FPU_SHARING -void arch_flush_fpu_ipi(unsigned int cpu) -{ - atomic_set_bit(&cpu_pending_ipi[cpu], IPI_FPU_FLUSH); - MSIP(_kernel.cpus[cpu].arch.hartid) = 1; -} -#endif - -static void sched_ipi_handler(const void *unused) -{ - ARG_UNUSED(unused); - - MSIP(csr_read(mhartid)) = 0; - - atomic_val_t pending_ipi = atomic_clear(&cpu_pending_ipi[_current_cpu->id]); - - if (pending_ipi & ATOMIC_MASK(IPI_SCHED)) { - z_sched_ipi(); - } -#ifdef CONFIG_FPU_SHARING - if (pending_ipi & ATOMIC_MASK(IPI_FPU_FLUSH)) { - /* disable IRQs */ - csr_clear(mstatus, MSTATUS_IEN); - /* perform the flush */ - arch_flush_local_fpu(); - /* - * No need to re-enable IRQs here as long as - * this remains the last case. - */ - } -#endif -} - -#ifdef CONFIG_FPU_SHARING -/* - * Make sure there is no pending FPU flush request for this CPU while - * waiting for a contended spinlock to become available. This prevents - * a deadlock when the lock we need is already taken by another CPU - * that also wants its FPU content to be reinstated while such content - * is still live in this CPU's FPU. - */ -void arch_spin_relax(void) -{ - atomic_val_t *pending_ipi = &cpu_pending_ipi[_current_cpu->id]; - - if (atomic_test_and_clear_bit(pending_ipi, IPI_FPU_FLUSH)) { - /* - * We may not be in IRQ context here hence cannot use - * arch_flush_local_fpu() directly. - */ - arch_float_disable(_current_cpu->arch.fpu_owner); - } -} -#endif - -int arch_smp_init(void) -{ - - IRQ_CONNECT(RISCV_IRQ_MSOFT, 0, sched_ipi_handler, NULL, 0); - irq_enable(RISCV_IRQ_MSOFT); - - return 0; -} -#endif /* CONFIG_SMP */ diff --git a/arch/riscv/core/thread.c b/arch/riscv/core/thread.c index 2fecc68a077..896f8e5199d 100644 --- a/arch/riscv/core/thread.c +++ b/arch/riscv/core/thread.c @@ -15,7 +15,7 @@ /* * Per-thread (TLS) variable indicating whether execution is in user mode. */ -__thread uint8_t is_user_mode; +Z_THREAD_LOCAL uint8_t is_user_mode; #endif void arch_new_thread(struct k_thread *thread, k_thread_stack_t *stack, diff --git a/arch/riscv/include/kernel_arch_func.h b/arch/riscv/include/kernel_arch_func.h index c5ed6ff3f7f..a8fc863c75d 100644 --- a/arch/riscv/include/kernel_arch_func.h +++ b/arch/riscv/include/kernel_arch_func.h @@ -18,6 +18,8 @@ #include #include +#include + #ifdef __cplusplus extern "C" { #endif @@ -53,6 +55,9 @@ static ALWAYS_INLINE void arch_kernel_init(void) #ifdef CONFIG_RISCV_PMP z_riscv_pmp_init(); #endif +#ifdef CONFIG_SOC_PER_CORE_INIT_HOOK + soc_per_core_init_hook(); +#endif /* CONFIG_SOC_PER_CORE_INIT_HOOK */ } static ALWAYS_INLINE void diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig index a3746f147f9..1a17bf1eddd 100644 --- a/arch/sparc/Kconfig +++ b/arch/sparc/Kconfig @@ -26,6 +26,12 @@ config NUM_IRQS int default 32 +config SPARC_SVT + bool "Single-vector trapping" + help + Use Single-vector trapping (SVT). Defined by SPARC-V8 Embedded (V8E) + Architecture Specification and available in some LEON processors. + config SPARC_CASA bool "CASA instructions" help diff --git a/arch/sparc/core/CMakeLists.txt b/arch/sparc/core/CMakeLists.txt index 82ff7906638..cc458404ed8 100644 --- a/arch/sparc/core/CMakeLists.txt +++ b/arch/sparc/core/CMakeLists.txt @@ -13,8 +13,9 @@ zephyr_library_sources( thread.c window_trap.S sw_trap_set_pil.S - trap_table_mvt.S ) +zephyr_library_sources_ifdef(CONFIG_SPARC_SVT trap_table_svt.S) +zephyr_library_sources_ifndef(CONFIG_SPARC_SVT trap_table_mvt.S) zephyr_library_sources_ifdef(CONFIG_IRQ_OFFLOAD irq_offload.c) zephyr_library_sources_ifdef(CONFIG_THREAD_LOCAL_STORAGE tls.c) diff --git a/arch/sparc/core/reset_trap.S b/arch/sparc/core/reset_trap.S index dd4046c47bc..6f1f6c037e3 100644 --- a/arch/sparc/core/reset_trap.S +++ b/arch/sparc/core/reset_trap.S @@ -12,6 +12,18 @@ GTEXT(__sparc_trap_reset) SECTION_FUNC(TEXT, __sparc_trap_reset) +#ifdef CONFIG_SPARC_SVT +#ifdef CONFIG_SOC_SPARC_LEON + /* On LEON, enable single vector trapping by setting ASR17.SV. */ + rd %asr17, %g1 + set (1<<13), %g2 + or %g1, %g2, %g1 + wr %g1, %asr17 +#else +#error "Don't know how to enable SVT on this SOC" +#endif +#endif + set __sparc_trap_table, %g1 wr %g1, %tbr wr 2, %wim diff --git a/arch/sparc/core/trap_table_svt.S b/arch/sparc/core/trap_table_svt.S new file mode 100644 index 00000000000..461cc5a51df --- /dev/null +++ b/arch/sparc/core/trap_table_svt.S @@ -0,0 +1,138 @@ +/* + * Copyright (c) 2023 Frontgrade Gaisler AB + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* + * This file contains the trap entry for SPARC operating with + * single-vector trap model, defined in SPARC V8E. The processor + * redirects execution to a single entry on any trap event. From + * there, two levels of look-up tables are used to find the trap + * handler. + * + * - Execution time is constant. + * - Condition flags are not modified. + * - Provides handler with PSR in l0, TBR in l6 + * - This SVT implementation is less than 400 bytes long. (An MVT + * table is always 4096 bytes long.) + * + * See trap_table_mvt.S for information about SPARC trap types. + */ + +#include +#include +#include + +#ifdef CONFIG_IRQ_OFFLOAD + #define IRQ_OFFLOAD_HANDLER __sparc_trap_irq_offload +#else + #define IRQ_OFFLOAD_HANDLER __sparc_trap_fault +#endif + +GTEXT(__sparc_trap_table) +GTEXT(__start) + +SECTION_SUBSEC_FUNC(TEXT, traptable, __sparc_trap_table) +__start: + rd %psr, %l0 + mov %tbr, %l6 + + and %l6, 0xf00, %l7 + srl %l7, 6, %l7 + set __sparc_trap_table_svt_level0, %l4 + ld [%l4 + %l7], %l4 + + and %l6, 0x0f0, %l7 + srl %l7, 2, %l7 + ld [%l4 + %l7], %l4 + + srl %l6, 4, %l3 + jmp %l4 + and %l3, 0xf, %l3 /* Interrupt level */ + +__sparc_trap_svt_in_trap: + ta 0x00 + nop + +SECTION_VAR(RODATA, __sparc_trap_table_svt_tables) + .align 4 +__sparc_trap_table_svt_level0: + .word __sparc_trap_table_svt_00 + .word __sparc_trap_table_svt_10 + .word __sparc_trap_table_svt_allbad + .word __sparc_trap_table_svt_allbad + .word __sparc_trap_table_svt_allbad + .word __sparc_trap_table_svt_allbad + .word __sparc_trap_table_svt_allbad + .word __sparc_trap_table_svt_allbad + .word __sparc_trap_table_svt_80 + .word __sparc_trap_table_svt_allbad + .word __sparc_trap_table_svt_allbad + .word __sparc_trap_table_svt_allbad + .word __sparc_trap_table_svt_allbad + .word __sparc_trap_table_svt_allbad + .word __sparc_trap_table_svt_allbad + .word __sparc_trap_table_svt_allbad + +__sparc_trap_table_svt_00: + .word __sparc_trap_reset + .word __sparc_trap_fault + .word __sparc_trap_fault + .word __sparc_trap_fault + .word __sparc_trap_fault + .word __sparc_trap_window_overflow + .word __sparc_trap_window_underflow +__sparc_trap_table_svt_allbad: + .word __sparc_trap_fault + .word __sparc_trap_fault + .word __sparc_trap_fault + .word __sparc_trap_fault + .word __sparc_trap_fault + .word __sparc_trap_fault + .word __sparc_trap_fault + .word __sparc_trap_fault + .word __sparc_trap_fault + .word __sparc_trap_fault + .word __sparc_trap_fault + .word __sparc_trap_fault + .word __sparc_trap_fault + .word __sparc_trap_fault + .word __sparc_trap_fault + .word __sparc_trap_fault + +__sparc_trap_table_svt_10: + .word __sparc_trap_fault + .word __sparc_trap_interrupt + .word __sparc_trap_interrupt + .word __sparc_trap_interrupt + .word __sparc_trap_interrupt + .word __sparc_trap_interrupt + .word __sparc_trap_interrupt + .word __sparc_trap_interrupt + .word __sparc_trap_interrupt + .word __sparc_trap_interrupt + .word __sparc_trap_interrupt + .word __sparc_trap_interrupt + .word __sparc_trap_interrupt + .word __sparc_trap_interrupt + .word __sparc_trap_interrupt + .word __sparc_trap_interrupt + +__sparc_trap_table_svt_80: + .word __sparc_trap_svt_in_trap + .word __sparc_trap_fault + .word __sparc_trap_fault + .word __sparc_trap_flush_windows + .word __sparc_trap_fault + .word __sparc_trap_fault + .word __sparc_trap_fault + .word __sparc_trap_fault + .word __sparc_trap_fault + .word __sparc_trap_sw_set_pil + .word __sparc_trap_fault + .word __sparc_trap_fault + .word __sparc_trap_fault + .word IRQ_OFFLOAD_HANDLER + .word __sparc_trap_fault + .word __sparc_trap_except_reason diff --git a/arch/sparc/include/kernel_arch_func.h b/arch/sparc/include/kernel_arch_func.h index 8b79b130ad6..fc59fdf7aa6 100644 --- a/arch/sparc/include/kernel_arch_func.h +++ b/arch/sparc/include/kernel_arch_func.h @@ -17,6 +17,8 @@ #include +#include + #ifdef __cplusplus extern "C" { #endif @@ -24,6 +26,9 @@ extern "C" { #ifndef _ASMLANGUAGE static ALWAYS_INLINE void arch_kernel_init(void) { +#ifdef CONFIG_SOC_PER_CORE_INIT_HOOK + soc_per_core_init_hook(); +#endif /* CONFIG_SOC_PER_CORE_INIT_HOOK */ } void z_sparc_context_switch(struct k_thread *newt, struct k_thread *oldt); diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 52ef70a0d13..46f32f92728 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -417,15 +417,6 @@ config X86_DISABLE_SSBD Even if enabled, will have no effect on CPUs that do not require this feature. -config DISABLE_SSBD - bool "Disable Speculative Store Bypass [DEPRECATED]" - depends on USERSPACE - default y if !X86_NO_SPECTRE_V4 - select X86_DISABLE_SSBD - select DEPRECATED - help - Deprecated. Use CONFIG_X86_DISABLE_SSBD instead. - config X86_ENABLE_EXTENDED_IBRS bool "Extended IBRS" depends on USERSPACE @@ -435,15 +426,6 @@ config X86_ENABLE_EXTENDED_IBRS Speculation 'always on' feature. This mitigates Indirect Branch Control vulnerabilities (aka Spectre V2). -config ENABLE_EXTENDED_IBRS - bool "Extended IBRS [DEPRECATED]" - depends on USERSPACE - default y if !X86_NO_SPECTRE_V2 - select X86_ENABLE_EXTENDED_IBRS - select DEPRECATED - help - Deprecated. Use CONFIG_X86_ENABLE_EXTENDED_IBRS instead. - config X86_BOUNDS_CHECK_BYPASS_MITIGATION bool depends on USERSPACE diff --git a/arch/x86/core/ia32/coredump.c b/arch/x86/core/ia32/coredump.c index fb7d0fcfd8c..c443dc4091b 100644 --- a/arch/x86/core/ia32/coredump.c +++ b/arch/x86/core/ia32/coredump.c @@ -5,6 +5,7 @@ */ #include +#include #include #define ARCH_HDR_VER 1 @@ -80,3 +81,22 @@ uint16_t arch_coredump_tgt_code_get(void) { return COREDUMP_TGT_X86; } + +#if defined(CONFIG_DEBUG_COREDUMP_DUMP_THREAD_PRIV_STACK) +void arch_coredump_priv_stack_dump(struct k_thread *thread) +{ + struct z_x86_thread_stack_header *hdr_stack_obj; + uintptr_t start_addr, end_addr; + +#if defined(CONFIG_THREAD_STACK_MEM_MAPPED) + hdr_stack_obj = (struct z_x86_thread_stack_header *)thread->stack_info.mapped.addr; +#else + hdr_stack_obj = (struct z_x86_thread_stack_header *)thread->stack_obj; +#endif /* CONFIG_THREAD_STACK_MEM_MAPPED) */ + + start_addr = (uintptr_t)&hdr_stack_obj->privilege_stack[0]; + end_addr = start_addr + sizeof(hdr_stack_obj->privilege_stack); + + coredump_memory_dump(start_addr, end_addr); +} +#endif /* CONFIG_DEBUG_COREDUMP_DUMP_THREAD_PRIV_STACK */ diff --git a/arch/x86/core/intel64/coredump.c b/arch/x86/core/intel64/coredump.c index 65a9306ca07..68aa04888ee 100644 --- a/arch/x86/core/intel64/coredump.c +++ b/arch/x86/core/intel64/coredump.c @@ -5,6 +5,7 @@ */ #include +#include #include #define ARCH_HDR_VER 1 @@ -106,3 +107,22 @@ uint16_t arch_coredump_tgt_code_get(void) { return COREDUMP_TGT_X86_64; } + +#if defined(CONFIG_DEBUG_COREDUMP_DUMP_THREAD_PRIV_STACK) +void arch_coredump_priv_stack_dump(struct k_thread *thread) +{ + struct z_x86_thread_stack_header *hdr_stack_obj; + uintptr_t start_addr, end_addr; + +#if defined(CONFIG_THREAD_STACK_MEM_MAPPED) + hdr_stack_obj = (struct z_x86_thread_stack_header *)thread->stack_info.mapped.addr; +#else + hdr_stack_obj = (struct z_x86_thread_stack_header *)thread->stack_obj; +#endif /* CONFIG_THREAD_STACK_MEM_MAPPED) */ + + start_addr = (uintptr_t)&hdr_stack_obj->privilege_stack[0]; + end_addr = start_addr + sizeof(hdr_stack_obj->privilege_stack); + + coredump_memory_dump(start_addr, end_addr); +} +#endif /* CONFIG_DEBUG_COREDUMP_DUMP_THREAD_PRIV_STACK */ diff --git a/arch/x86/core/intel64/irq_offload.c b/arch/x86/core/intel64/irq_offload.c index 03ae8a9439b..b38dab33ceb 100644 --- a/arch/x86/core/intel64/irq_offload.c +++ b/arch/x86/core/intel64/irq_offload.c @@ -18,8 +18,8 @@ extern void (*x86_irq_funcs[NR_IRQ_VECTORS])(const void *arg); extern const void *x86_irq_args[NR_IRQ_VECTORS]; -static void (*irq_offload_funcs[CONFIG_MP_NUM_CPUS])(const void *arg); -static const void *irq_offload_args[CONFIG_MP_NUM_CPUS]; +static void (*irq_offload_funcs[CONFIG_MP_MAX_NUM_CPUS])(const void *arg); +static const void *irq_offload_args[CONFIG_MP_MAX_NUM_CPUS]; static void dispatcher(const void *arg) { diff --git a/arch/x86/core/x86_mmu.c b/arch/x86/core/x86_mmu.c index 566dd2cdfd4..e4188b8670f 100644 --- a/arch/x86/core/x86_mmu.c +++ b/arch/x86/core/x86_mmu.c @@ -1281,6 +1281,12 @@ static pentry_t flags_to_entry(uint32_t flags) entry_flags |= ENTRY_XD; } + if (IS_ENABLED(CONFIG_DEMAND_MAPPING) && (flags & K_MEM_MAP_UNPAGED) != 0U) { + /* same state as in arch_mem_page_out() */ + entry_flags &= ~MMU_P; + entry_flags |= MMU_A; + } + return entry_flags; } diff --git a/arch/x86/include/ia32/kernel_arch_func.h b/arch/x86/include/ia32/kernel_arch_func.h index a0521fca3da..686bc18989b 100644 --- a/arch/x86/include/ia32/kernel_arch_func.h +++ b/arch/x86/include/ia32/kernel_arch_func.h @@ -14,13 +14,17 @@ #include /* For size_t */ +#include + #ifdef __cplusplus extern "C" { #endif static inline void arch_kernel_init(void) { - /* No-op on this arch */ +#ifdef CONFIG_SOC_PER_CORE_INIT_HOOK + soc_per_core_init_hook(); +#endif /* CONFIG_SOC_PER_CORE_INIT_HOOK */ } static ALWAYS_INLINE void @@ -33,6 +37,8 @@ arch_thread_return_value_set(struct k_thread *thread, unsigned int value) extern void arch_cpu_atomic_idle(unsigned int key); +int arch_swap(unsigned int key); + /* ASM code to fiddle with registers to enable the MMU with PAE paging */ void z_x86_enable_paging(void); diff --git a/arch/x86/include/intel64/kernel_arch_func.h b/arch/x86/include/intel64/kernel_arch_func.h index abf022fe5fd..da553fd08ac 100644 --- a/arch/x86/include/intel64/kernel_arch_func.h +++ b/arch/x86/include/intel64/kernel_arch_func.h @@ -8,6 +8,8 @@ #include +#include + #ifndef _ASMLANGUAGE extern void z_x86_switch(void *switch_to, void **switched_from); @@ -27,7 +29,9 @@ extern void z_x86_ipi_setup(void); static inline void arch_kernel_init(void) { - /* nothing */; +#ifdef CONFIG_SOC_PER_CORE_INIT_HOOK + soc_per_core_init_hook(); +#endif /* CONFIG_SOC_PER_CORE_INIT_HOOK */ } FUNC_NORETURN void z_x86_cpu_init(struct x86_cpuboot *cpuboot); diff --git a/arch/x86/intel64.cmake b/arch/x86/intel64.cmake index fcc075addc2..04e9a256f36 100644 --- a/arch/x86/intel64.cmake +++ b/arch/x86/intel64.cmake @@ -2,6 +2,7 @@ # SPDX-License-Identifier: Apache-2.0 zephyr_cc_option(-m64) +zephyr_cc_option(-mno-red-zone) set_property(GLOBAL PROPERTY PROPERTY_OUTPUT_ARCH "i386:x86-64") set_property(GLOBAL PROPERTY PROPERTY_OUTPUT_FORMAT "elf64-x86-64") diff --git a/arch/xtensa/CMakeLists.txt b/arch/xtensa/CMakeLists.txt index 21de223d4ec..75885573405 100644 --- a/arch/xtensa/CMakeLists.txt +++ b/arch/xtensa/CMakeLists.txt @@ -7,5 +7,5 @@ add_subdirectory(core) if (CONFIG_XTENSA_INSECURE_USERSPACE) message(WARNING " This userspace implementation uses the window ABI this means that the kernel - will spill registers in behave of the userpsace. Use it carefully.") + will spill registers on behalf of the userspace. Use it carefully.") endif() diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig index 8722c879e8b..b69d8bcf02b 100644 --- a/arch/xtensa/Kconfig +++ b/arch/xtensa/Kconfig @@ -283,7 +283,7 @@ config XTENSA_SYSCALL_USE_HELPER default y if "$(ZEPHYR_TOOLCHAIN_VARIANT)" = "xt-clang" depends on (XTENSA_MMU || XTENSA_MPU) && USERSPACE help - Use syscall helpers for passing more then 3 arguments. + Use syscall helpers for passing more than 3 arguments. This is a workaround for toolchains where they have issue modeling register usage. diff --git a/arch/xtensa/core/CMakeLists.txt b/arch/xtensa/core/CMakeLists.txt index d03e3641b42..7d7e260ca0b 100644 --- a/arch/xtensa/core/CMakeLists.txt +++ b/arch/xtensa/core/CMakeLists.txt @@ -53,7 +53,7 @@ set(CORE_ISA_DM ${CMAKE_BINARY_DIR}/zephyr/include/generated/zephyr/core-isa-dM. set(CORE_ISA_IN ${CMAKE_BINARY_DIR}/zephyr/include/generated/core-isa-dM.c) file(WRITE ${CORE_ISA_IN} "#include \n") add_custom_command(OUTPUT ${CORE_ISA_DM} - COMMAND ${CMAKE_C_COMPILER} -E -dM -U__XCC__ + COMMAND ${CMAKE_C_COMPILER} -E -dM -U__XCC__ ${XTENSA_CORE_LOCAL_C_FLAG} -I${ZEPHYR_XTENSA_MODULE_DIR}/zephyr/soc/${CONFIG_SOC} -I${SOC_FULL_DIR} ${CORE_ISA_IN} -o ${CORE_ISA_DM}) diff --git a/arch/xtensa/core/coredump.c b/arch/xtensa/core/coredump.c index 0ee1f8992a6..8e4b08ee2fa 100644 --- a/arch/xtensa/core/coredump.c +++ b/arch/xtensa/core/coredump.c @@ -5,6 +5,7 @@ */ #include +#include #include #include #include @@ -189,3 +190,18 @@ uint16_t arch_coredump_tgt_code_get(void) { return COREDUMP_TGT_XTENSA; } + +#if defined(CONFIG_DEBUG_COREDUMP_DUMP_THREAD_PRIV_STACK) +void arch_coredump_priv_stack_dump(struct k_thread *thread) +{ + struct xtensa_thread_stack_header *hdr_stack_obj; + uintptr_t start_addr, end_addr; + + hdr_stack_obj = (struct xtensa_thread_stack_header *)thread->stack_obj; + + start_addr = (uintptr_t)&hdr_stack_obj->privilege_stack[0]; + end_addr = start_addr + sizeof(hdr_stack_obj->privilege_stack); + + coredump_memory_dump(start_addr, end_addr); +} +#endif /* CONFIG_DEBUG_COREDUMP_DUMP_THREAD_PRIV_STACK */ diff --git a/arch/xtensa/core/elf.c b/arch/xtensa/core/elf.c index e85fab84c69..17337f4a7bc 100644 --- a/arch/xtensa/core/elf.c +++ b/arch/xtensa/core/elf.c @@ -6,11 +6,22 @@ #include #include +#include #include #include -LOG_MODULE_DECLARE(llext); +LOG_MODULE_DECLARE(llext, CONFIG_LLEXT_LOG_LEVEL); +/* + * ELF relocation tables on Xtensa contain relocations of different types. They + * specify how the relocation should be performed. Which relocations are used + * depends on the type of the ELF object (e.g. shared or partially linked + * object), structure of the object (single or multiple source files), compiler + * flags used (e.g. -fPIC), etc. Also not all relocation table entries should be + * acted upon. Some of them describe relocations that have already been + * resolved by the linker. We have to distinguish them from actionable + * relocations and only need to handle the latter ones. + */ #define R_XTENSA_NONE 0 #define R_XTENSA_32 1 #define R_XTENSA_RTLD 2 @@ -18,43 +29,139 @@ LOG_MODULE_DECLARE(llext); #define R_XTENSA_JMP_SLOT 4 #define R_XTENSA_RELATIVE 5 #define R_XTENSA_PLT 6 +#define R_XTENSA_ASM_EXPAND 11 +#define R_XTENSA_SLOT0_OP 20 + +static void xtensa_elf_relocate(struct llext_loader *ldr, struct llext *ext, + const elf_rela_t *rel, uintptr_t addr, + uint8_t *loc, int type, uint32_t stb) +{ + elf_word *got_entry = (elf_word *)loc; + + switch (type) { + case R_XTENSA_RELATIVE: + ; + /* Relocate a local symbol: Xtensa specific. Seems to only be used with PIC */ + unsigned int sh_ndx; + + for (sh_ndx = 0; sh_ndx < ext->sect_cnt; sh_ndx++) { + if (ext->sect_hdrs[sh_ndx].sh_addr <= *got_entry && + *got_entry < + ext->sect_hdrs[sh_ndx].sh_addr + ext->sect_hdrs[sh_ndx].sh_size) + break; + } + + if (sh_ndx == ext->sect_cnt) { + LOG_ERR("%#x not found in any of the sections", *got_entry); + return; + } + + *got_entry += (uintptr_t)llext_loaded_sect_ptr(ldr, ext, sh_ndx) - + ext->sect_hdrs[sh_ndx].sh_addr; + break; + case R_XTENSA_GLOB_DAT: + case R_XTENSA_JMP_SLOT: + if (stb == STB_GLOBAL) { + *got_entry = addr; + } + break; + case R_XTENSA_32: + /* Used for both LOCAL and GLOBAL bindings */ + *got_entry += addr; + break; + case R_XTENSA_SLOT0_OP: + /* Apparently only actionable with LOCAL bindings */ + ; + elf_sym_t rsym; + int ret = llext_seek(ldr, ldr->sects[LLEXT_MEM_SYMTAB].sh_offset + + ELF_R_SYM(rel->r_info) * sizeof(elf_sym_t)); + + if (!ret) { + ret = llext_read(ldr, &rsym, sizeof(elf_sym_t)); + } + if (ret) { + LOG_ERR("Failed to read a symbol table entry, LLEXT linking might fail."); + return; + } + + /* + * So far in all observed use-cases + * llext_loaded_sect_ptr(ldr, ext, rsym.st_shndx) was already + * available as the "addr" argument of this function, supplied + * by arch_elf_relocate_local() from its non-STT_SECTION branch. + */ + uintptr_t link_addr = (uintptr_t)llext_loaded_sect_ptr(ldr, ext, rsym.st_shndx) + + rsym.st_value + rel->r_addend; + ssize_t value = (link_addr - (((uintptr_t)got_entry + 3) & ~3)) >> 2; + + /* Check the opcode */ + if ((loc[0] & 0xf) == 1 && !loc[1] && !loc[2]) { + /* L32R: low nibble is 1 */ + loc[1] = value & 0xff; + loc[2] = (value >> 8) & 0xff; + } else if ((loc[0] & 0xf) == 5 && !(loc[0] & 0xc0) && !loc[1] && !loc[2]) { + /* CALLn: low nibble is 5 */ + loc[0] = (loc[0] & 0x3f) | ((value << 6) & 0xc0); + loc[1] = (value >> 2) & 0xff; + loc[2] = (value >> 10) & 0xff; + } else { + LOG_DBG("%p: unhandled OPC or no relocation %02x%02x%02x inf %#x offs %#x", + (void *)loc, loc[2], loc[1], loc[0], + rel->r_info, rel->r_offset); + break; + } + + break; + case R_XTENSA_ASM_EXPAND: + /* Nothing to do */ + break; + default: + LOG_DBG("Unsupported relocation type %u", type); + + return; + } + + LOG_DBG("Applied relocation to %#x type %u at %p", + *(uint32_t *)((uintptr_t)got_entry & ~3), type, (void *)got_entry); +} /** - * @brief Architecture specific function for relocating shared elf - * - * Elf files contain a series of relocations described in multiple sections. - * These relocation instructions are architecture specific and each architecture - * supporting modules must implement this. + * @brief Architecture specific function for STB_LOCAL ELF relocations */ -void arch_elf_relocate_local(struct llext_loader *ldr, struct llext *ext, - const elf_rela_t *rel, const elf_sym_t *sym, size_t got_offset) +void arch_elf_relocate_local(struct llext_loader *ldr, struct llext *ext, const elf_rela_t *rel, + const elf_sym_t *sym, uint8_t *rel_addr, + const struct llext_load_param *ldr_parm) { - uint8_t *text = ext->mem[LLEXT_MEM_TEXT]; int type = ELF32_R_TYPE(rel->r_info); - elf_word *got_entry = (elf_word *)(text + got_offset); uintptr_t sh_addr; if (ELF_ST_TYPE(sym->st_info) == STT_SECTION) { - elf_shdr_t *shdr = llext_peek(ldr, ldr->hdr.e_shoff + - sym->st_shndx * ldr->hdr.e_shentsize); - sh_addr = shdr->sh_addr ? : (uintptr_t)llext_peek(ldr, shdr->sh_offset); + elf_shdr_t *shdr = ext->sect_hdrs + sym->st_shndx; + + /* shdr->sh_addr is NULL when not built for a specific address */ + sh_addr = shdr->sh_addr && + (!ldr_parm->section_detached || !ldr_parm->section_detached(shdr)) ? + shdr->sh_addr : (uintptr_t)llext_loaded_sect_ptr(ldr, ext, sym->st_shndx); } else { sh_addr = ldr->sects[LLEXT_MEM_TEXT].sh_addr; } - switch (type) { - case R_XTENSA_RELATIVE: - /* Relocate a local symbol: Xtensa specific */ - *got_entry += (uintptr_t)text - sh_addr; - break; - case R_XTENSA_32: - *got_entry += sh_addr; - break; - default: - LOG_DBG("unsupported relocation type %u", type); + xtensa_elf_relocate(ldr, ext, rel, sh_addr, rel_addr, type, ELF_ST_BIND(sym->st_info)); +} - return; +/** + * @brief Architecture specific function for STB_GLOBAL ELF relocations + */ +void arch_elf_relocate_global(struct llext_loader *ldr, struct llext *ext, const elf_rela_t *rel, + const elf_sym_t *sym, uint8_t *rel_addr, const void *link_addr) +{ + int type = ELF32_R_TYPE(rel->r_info); + + /* For global relocations we expect the initial value for R_XTENSA_RELATIVE to be zero */ + if (type == R_XTENSA_RELATIVE && *(elf_word *)rel_addr) { + LOG_WRN("global: non-zero relative value %#x", *(elf_word *)rel_addr); } - LOG_DBG("relocation to %#x type %u at %p", *got_entry, type, (void *)got_entry); + xtensa_elf_relocate(ldr, ext, rel, (uintptr_t)link_addr, rel_addr, type, + ELF_ST_BIND(sym->st_info)); } diff --git a/arch/xtensa/core/prep_c.c b/arch/xtensa/core/prep_c.c index 990915c5a46..6dbab69f50f 100644 --- a/arch/xtensa/core/prep_c.c +++ b/arch/xtensa/core/prep_c.c @@ -13,6 +13,13 @@ extern FUNC_NORETURN void z_cstart(void); /* defined by the SoC in case of CONFIG_SOC_HAS_RUNTIME_NUM_CPUS=y */ extern void soc_num_cpus_init(void); +/* Make sure the platform configuration matches what the toolchain + * thinks the hardware is doing. + */ +#ifdef CONFIG_DCACHE_LINE_SIZE +BUILD_ASSERT(CONFIG_DCACHE_LINE_SIZE == XCHAL_DCACHE_LINESIZE); +#endif + /** * * @brief Prepare to and run C code diff --git a/arch/xtensa/core/startup/reset_vector.S b/arch/xtensa/core/startup/reset_vector.S index 31877614ccd..21f4b25e77e 100644 --- a/arch/xtensa/core/startup/reset_vector.S +++ b/arch/xtensa/core/startup/reset_vector.S @@ -104,7 +104,7 @@ _ResetHandler: /* Read PWRSTAT */ movi a2, XDM_MISC_PWRSTAT /* Save area address - retained for later */ - movi a3, _xtos_pso_savearea + movi a3, xthal_pso_savearea /* Signature for compare - retained for later */ movi a5, CORE_STATE_SIGNATURE /* PWRSTAT value - retained for later */ @@ -229,7 +229,7 @@ _ResetHandler: * MEMCTL register was already restored earlier, and as a side * effect, registers a3, a5, a7 are now preloaded with values * that we will use here. - * a3 - pointer to save area base address (_xtos_pso_savearea) + * a3 - pointer to save area base address (xthal_pso_savearea) * a5 - saved state signature (CORE_STATE_SIGNATURE) * a7 - contents of PWRSTAT register */ @@ -343,11 +343,11 @@ _ResetHandler: /* make shutoff routine return zero */ movi a2, 0 - movi a3, _xtos_pso_savearea + movi a3, xthal_pso_savearea /* Here, as below for _start, call0 is used as an unlimited-range * jump. */ - call0 _xtos_core_restore_nw + call0 xthal_core_restore_nw /* (does not return) */ .Lcoldstart: #endif diff --git a/arch/xtensa/core/syscall_helper.c b/arch/xtensa/core/syscall_helper.c index 24feda91c80..f9673e67814 100644 --- a/arch/xtensa/core/syscall_helper.c +++ b/arch/xtensa/core/syscall_helper.c @@ -12,10 +12,10 @@ #include #ifdef CONFIG_XTENSA_SYSCALL_USE_HELPER -uintptr_t xtensa_syscall_helper(uintptr_t arg1, uintptr_t arg2, - uintptr_t arg3, uintptr_t arg4, - uintptr_t arg5, uintptr_t arg6, - uintptr_t call_id) +uintptr_t xtensa_syscall_helper_args_6(uintptr_t arg1, uintptr_t arg2, + uintptr_t arg3, uintptr_t arg4, + uintptr_t arg5, uintptr_t arg6, + uintptr_t call_id) { register uintptr_t a2 __asm__("%a2") = call_id; register uintptr_t a6 __asm__("%a6") = arg1; @@ -33,6 +33,101 @@ uintptr_t xtensa_syscall_helper(uintptr_t arg1, uintptr_t arg2, return a2; } + +uintptr_t xtensa_syscall_helper_args_5(uintptr_t arg1, uintptr_t arg2, + uintptr_t arg3, uintptr_t arg4, + uintptr_t arg5, uintptr_t call_id) +{ + register uintptr_t a2 __asm__("%a2") = call_id; + register uintptr_t a6 __asm__("%a6") = arg1; + register uintptr_t a3 __asm__("%a3") = arg2; + register uintptr_t a4 __asm__("%a4") = arg3; + register uintptr_t a5 __asm__("%a5") = arg4; + register uintptr_t a8 __asm__("%a8") = arg5; + + __asm__ volatile("syscall\n\t" + : "=r" (a2) + : "r" (a2), "r" (a6), "r" (a3), "r" (a4), + "r" (a5), "r" (a8) + : "memory"); + + return a2; +} + +uintptr_t xtensa_syscall_helper_args_4(uintptr_t arg1, uintptr_t arg2, + uintptr_t arg3, uintptr_t arg4, + uintptr_t call_id) +{ + register uintptr_t a2 __asm__("%a2") = call_id; + register uintptr_t a6 __asm__("%a6") = arg1; + register uintptr_t a3 __asm__("%a3") = arg2; + register uintptr_t a4 __asm__("%a4") = arg3; + register uintptr_t a5 __asm__("%a5") = arg4; + + __asm__ volatile("syscall\n\t" + : "=r" (a2) + : "r" (a2), "r" (a6), "r" (a3), "r" (a4), + "r" (a5) + : "memory"); + + return a2; +} + +uintptr_t xtensa_syscall_helper_args_3(uintptr_t arg1, uintptr_t arg2, + uintptr_t arg3, uintptr_t call_id) +{ + register uintptr_t a2 __asm__("%a2") = call_id; + register uintptr_t a6 __asm__("%a6") = arg1; + register uintptr_t a3 __asm__("%a3") = arg2; + register uintptr_t a4 __asm__("%a4") = arg3; + + __asm__ volatile("syscall\n\t" + : "=r" (a2) + : "r" (a2), "r" (a6), "r" (a3), "r" (a4) + : "memory"); + + return a2; +} + +uintptr_t xtensa_syscall_helper_args_2(uintptr_t arg1, uintptr_t arg2, + uintptr_t call_id) +{ + register uintptr_t a2 __asm__("%a2") = call_id; + register uintptr_t a6 __asm__("%a6") = arg1; + register uintptr_t a3 __asm__("%a3") = arg2; + + __asm__ volatile("syscall\n\t" + : "=r" (a2) + : "r" (a2), "r" (a6), "r" (a3) + : "memory"); + + return a2; +} + +uintptr_t xtensa_syscall_helper_args_1(uintptr_t arg1, uintptr_t call_id) +{ + register uintptr_t a2 __asm__("%a2") = call_id; + register uintptr_t a6 __asm__("%a6") = arg1; + + __asm__ volatile("syscall\n\t" + : "=r" (a2) + : "r" (a2), "r" (a6) + : "memory"); + + return a2; +} + +uintptr_t xtensa_syscall_helper_args_0(uintptr_t call_id) +{ + register uintptr_t a2 __asm__("%a2") = call_id; + + __asm__ volatile("syscall\n\t" + : "=r" (a2) + : "r" (a2) + : "memory"); + + return a2; +} #endif /* CONFIG_XTENSA_SYSCALL_USE_HELPER */ #if XCHAL_HAVE_THREADPTR == 0 diff --git a/arch/xtensa/core/thread.c b/arch/xtensa/core/thread.c index f59c8274994..f9b8179173d 100644 --- a/arch/xtensa/core/thread.c +++ b/arch/xtensa/core/thread.c @@ -22,7 +22,7 @@ LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL); /* * Per-thread (TLS) variable indicating whether execution is in user mode. */ -__thread uint32_t is_user_mode; +Z_THREAD_LOCAL uint32_t is_user_mode; #endif #endif /* CONFIG_USERSPACE */ diff --git a/arch/xtensa/include/kernel_arch_func.h b/arch/xtensa/include/kernel_arch_func.h index 4b5bac74ead..5e735dedfff 100644 --- a/arch/xtensa/include/kernel_arch_func.h +++ b/arch/xtensa/include/kernel_arch_func.h @@ -14,6 +14,7 @@ #include #include #include +#include #include #ifdef __cplusplus @@ -25,14 +26,16 @@ K_KERNEL_STACK_ARRAY_DECLARE(z_interrupt_stacks, CONFIG_MP_MAX_NUM_CPUS, static ALWAYS_INLINE void arch_kernel_init(void) { - +#ifdef CONFIG_SOC_PER_CORE_INIT_HOOK + soc_per_core_init_hook(); +#endif /* CONFIG_SOC_PER_CORE_INIT_HOOK */ } void xtensa_switch(void *switch_to, void **switched_from); static ALWAYS_INLINE void arch_switch(void *switch_to, void **switched_from) { - return xtensa_switch(switch_to, switched_from); + xtensa_switch(switch_to, switched_from); } #ifdef CONFIG_KERNEL_COHERENCE diff --git a/boards/01space/esp32c3_042_oled/Kconfig b/boards/01space/esp32c3_042_oled/Kconfig new file mode 100644 index 00000000000..c6a99b1032d --- /dev/null +++ b/boards/01space/esp32c3_042_oled/Kconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 4096 diff --git a/boards/01space/esp32c3_042_oled/Kconfig.defconfig b/boards/01space/esp32c3_042_oled/Kconfig.defconfig deleted file mode 100644 index 4171bb04bc2..00000000000 --- a/boards/01space/esp32c3_042_oled/Kconfig.defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright 2022 Google LLC -# SPDX-License-Identifier: Apache-2.0 - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 65535 if WIFI && BT - default 51200 if WIFI - default 40960 if BT - default 4096 diff --git a/boards/01space/esp32c3_042_oled/Kconfig.esp32c3_042_oled b/boards/01space/esp32c3_042_oled/Kconfig.esp32c3_042_oled index 8b0fbf42eab..ca56668cfee 100644 --- a/boards/01space/esp32c3_042_oled/Kconfig.esp32c3_042_oled +++ b/boards/01space/esp32c3_042_oled/Kconfig.esp32c3_042_oled @@ -2,4 +2,4 @@ # SPDX-License-Identifier: Apache-2.0 config BOARD_ESP32C3_042_OLED - select SOC_ESP32C3_FX4 + select SOC_ESP32C3_FH4 diff --git a/boards/01space/esp32c3_042_oled/doc/index.rst b/boards/01space/esp32c3_042_oled/doc/index.rst index b8f3cbe7bc9..29fcfc78615 100644 --- a/boards/01space/esp32c3_042_oled/doc/index.rst +++ b/boards/01space/esp32c3_042_oled/doc/index.rst @@ -1,7 +1,4 @@ -.. _01space_esp32c3_042_oled: - -ESP32C3 0.42 OLED -################# +.. zephyr:board:: esp32c3_042_oled Overview ******** @@ -11,12 +8,6 @@ RISC-V WiFi/Bluetooth dual-mode chip. For more details see the `01space ESP32C3 0.42 OLED`_ Github repo. -.. figure:: img/esp32c3_042_oled.webp - :align: center - :alt: 01space ESP32C3 0.42 OLED - - 01space ESP32C3 0.42 OLED - Hardware ******** diff --git a/boards/01space/esp32c3_042_oled/esp32c3_042_oled.dts b/boards/01space/esp32c3_042_oled/esp32c3_042_oled.dts index c7680c0b152..70f83f398e7 100644 --- a/boards/01space/esp32c3_042_oled/esp32c3_042_oled.dts +++ b/boards/01space/esp32c3_042_oled/esp32c3_042_oled.dts @@ -9,12 +9,13 @@ #include #include "esp32c3_042_oled-pinctrl.dtsi" +#include / { model = "01space ESP32C3 0.42 OLED"; chosen { - zephyr,sram = &sram0; + zephyr,sram = &sram1; zephyr,console = &usb_serial; zephyr,shell-uart = &usb_serial; zephyr,flash = &flash0; @@ -104,37 +105,3 @@ &esp32_bt_hci { status = "okay"; }; - -&flash0 { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x0000F000>; - read-only; - }; - - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 0x00100000>; - }; - - slot1_partition: partition@110000 { - label = "image-1"; - reg = <0x00110000 0x00100000>; - }; - - scratch_partition: partition@210000 { - label = "image-scratch"; - reg = <0x00210000 0x00040000>; - }; - - storage_partition: partition@250000 { - label = "storage"; - reg = <0x00250000 0x00006000>; - }; - }; -}; diff --git a/boards/01space/esp32c3_042_oled/esp32c3_042_oled.yaml b/boards/01space/esp32c3_042_oled/esp32c3_042_oled.yaml index 4f9e9c93778..579094df443 100644 --- a/boards/01space/esp32c3_042_oled/esp32c3_042_oled.yaml +++ b/boards/01space/esp32c3_042_oled/esp32c3_042_oled.yaml @@ -11,8 +11,4 @@ supported: - spi - uart - watchdog -testing: - ignore_tags: - - net - - bluetooth vendor: 01space diff --git a/boards/96boards/aerocore2/96b_aerocore2.dts b/boards/96boards/aerocore2/96b_aerocore2.dts index dd5f8d8a895..028887cef16 100644 --- a/boards/96boards/aerocore2/96b_aerocore2.dts +++ b/boards/96boards/aerocore2/96b_aerocore2.dts @@ -179,7 +179,7 @@ zephyr_udc0: &usbotg_fs { pinctrl-0 = <&adc1_in10_pc0 &adc1_in11_pc1 &adc1_in12_pc2 &adc1_in13_pc3>; pinctrl-names = "default"; - st,adc-clock-source = ; + st,adc-clock-source = "SYNC"; st,adc-prescaler = <2>; status = "okay"; }; diff --git a/boards/96boards/argonkey/96b_argonkey.dts b/boards/96boards/argonkey/96b_argonkey.dts index a7c02dcb881..e19b022c26a 100644 --- a/boards/96boards/argonkey/96b_argonkey.dts +++ b/boards/96boards/argonkey/96b_argonkey.dts @@ -71,7 +71,9 @@ div-m = <8>; mul-n = <192>; div-r = <3>; - status = "okay"; + div-q = <4>; + clocks = <&clk_hse>; + status = "okay"; /* 48MHz on PLLI2SQ */ }; &rcc { diff --git a/boards/96boards/avenger96/96b_avenger96.yaml b/boards/96boards/avenger96/96b_avenger96.yaml index 5d50bcd6943..ef14d1b879d 100644 --- a/boards/96boards/avenger96/96b_avenger96.yaml +++ b/boards/96boards/avenger96/96b_avenger96.yaml @@ -14,7 +14,6 @@ testing: - cmsis_rtos_v2 - net - mpu - - tinycrypt - crypto - aes - cmm diff --git a/boards/96boards/carbon/Kconfig.defconfig b/boards/96boards/carbon/Kconfig.defconfig index 2cf1bbdc6fc..a680c5e19f8 100644 --- a/boards/96boards/carbon/Kconfig.defconfig +++ b/boards/96boards/carbon/Kconfig.defconfig @@ -9,21 +9,8 @@ config SPI_STM32_INTERRUPT default y depends on SPI -if BT - -config SPI - default y - -config BT_SPI - default y - -endif # BT - endif # BOARD_96B_CARBON_STM32F401XE if BOARD_96B_CARBON_NRF51822 -config BT_CTLR - default BT - endif # BOARD_96B_CARBON_NRF51822 diff --git a/boards/96boards/meerkat96/96b_meerkat96_mcimx7d_m4_defconfig b/boards/96boards/meerkat96/96b_meerkat96_mcimx7d_m4_defconfig index 90dfb85138a..d421425ca19 100644 --- a/boards/96boards/meerkat96/96b_meerkat96_mcimx7d_m4_defconfig +++ b/boards/96boards/meerkat96/96b_meerkat96_mcimx7d_m4_defconfig @@ -12,7 +12,4 @@ CONFIG_UART_INTERRUPT_DRIVEN=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y -# pinctrl -CONFIG_PINCTRL=y - CONFIG_XIP=y diff --git a/boards/96boards/neonkey/doc/index.rst b/boards/96boards/neonkey/doc/index.rst index df9fb1619c1..b69b94a4712 100644 --- a/boards/96boards/neonkey/doc/index.rst +++ b/boards/96boards/neonkey/doc/index.rst @@ -216,6 +216,8 @@ GDB instance. To reattach, just follow the same steps above, till References ********** +.. target-notes:: + .. _96Boards website: https://www.96boards.org/product/neonkey/ diff --git a/boards/96boards/nitrogen/Kconfig.defconfig b/boards/96boards/nitrogen/Kconfig.defconfig index c1686a82539..19571eb4ef4 100644 --- a/boards/96boards/nitrogen/Kconfig.defconfig +++ b/boards/96boards/nitrogen/Kconfig.defconfig @@ -5,7 +5,4 @@ if BOARD_96B_NITROGEN -config BT_CTLR - default BT - endif # BOARD_96B_NITROGEN diff --git a/boards/96boards/stm32_sensor_mez/96b_stm32_sensor_mez.dts b/boards/96boards/stm32_sensor_mez/96b_stm32_sensor_mez.dts index 80281ae098d..f20a91c6aca 100644 --- a/boards/96boards/stm32_sensor_mez/96b_stm32_sensor_mez.dts +++ b/boards/96boards/stm32_sensor_mez/96b_stm32_sensor_mez.dts @@ -75,7 +75,9 @@ div-m = <8>; mul-n = <192>; div-r = <3>; - status = "okay"; + div-q = <4>; + clocks = <&clk_hse>; + status = "okay"; /* 48MHz on PLLI2SQ */ }; &rcc { diff --git a/boards/96boards/wistrio/doc/96b_wistrio.rst b/boards/96boards/wistrio/doc/96b_wistrio.rst index 8db31fcf6cb..9fe756efe6b 100644 --- a/boards/96boards/wistrio/doc/96b_wistrio.rst +++ b/boards/96boards/wistrio/doc/96b_wistrio.rst @@ -189,6 +189,8 @@ GDB instance. To reattach, just follow the same steps above, till References ********** +.. target-notes:: + .. _AN2606: https://www.st.com/resource/en/application_note/cd00167594.pdf diff --git a/boards/Kconfig b/boards/Kconfig index 8f186b32caf..40e8e5006e1 100644 --- a/boards/Kconfig +++ b/boards/Kconfig @@ -128,6 +128,20 @@ config QEMU_EXTRA_FLAGS to setup devices, for example to allocate interface for Zephyr GDBstub over serial with `-serial tcp:127.0.0.1:5678,server` +config BOARD_REQUIRES_SERIAL_BACKEND_CDC_ACM + bool + help + Indicates that a board has no other capabilities than to use the CDC + ACM UART as a backend for logging or shell. + +config BOARD_SERIAL_BACKEND_CDC_ACM + bool "Board uses USB CDC ACM UART as serial backend" + depends on BOARD_REQUIRES_SERIAL_BACKEND_CDC_ACM + default y + help + USB stack and CDC ACM UART are configured and initialized at boot + time to be used as a backend for logging or shell. + # There might not be any board options, hence the optional source osource "$(KCONFIG_BOARD_DIR)/Kconfig" endmenu diff --git a/boards/aconno/acn52832/Kconfig.defconfig b/boards/aconno/acn52832/Kconfig.defconfig index 10c5ce95ed8..57fd066809c 100644 --- a/boards/aconno/acn52832/Kconfig.defconfig +++ b/boards/aconno/acn52832/Kconfig.defconfig @@ -5,7 +5,4 @@ if BOARD_ACN52832 -config BT_CTLR - default BT - endif # BOARD_ACN52832 diff --git a/boards/aconno/acn52832/doc/index.rst b/boards/aconno/acn52832/doc/index.rst index ff0c98cd91a..3e773c91a2a 100644 --- a/boards/aconno/acn52832/doc/index.rst +++ b/boards/aconno/acn52832/doc/index.rst @@ -1,7 +1,4 @@ -.. _acn52832: - -acn52832 -######## +.. zephyr:board:: acn52832 Overview ******** diff --git a/boards/acrn/acrn/acrn.dts b/boards/acrn/acrn/acrn.dts index dbd30373e34..8d7376daf70 100644 --- a/boards/acrn/acrn/acrn.dts +++ b/boards/acrn/acrn/acrn.dts @@ -46,3 +46,7 @@ status = "okay"; current-speed = <115200>; }; + +&cpu { + compatible = "intel,x86_64"; +}; diff --git a/boards/acrn/acrn/acrn_defconfig b/boards/acrn/acrn/acrn_defconfig index 0ec5c2b2564..9a3ce5de7c7 100644 --- a/boards/acrn/acrn/acrn_defconfig +++ b/boards/acrn/acrn/acrn_defconfig @@ -13,4 +13,3 @@ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=25000000 CONFIG_BUILD_OUTPUT_BIN=y CONFIG_SHELL_BACKEND_SERIAL_INTERRUPT_DRIVEN=n CONFIG_KERNEL_VM_SIZE=0x1000000 -CONFIG_BUILD_NO_GAP_FILL=y diff --git a/boards/acrn/acrn/acrn_ehl_crb_defconfig b/boards/acrn/acrn/acrn_ehl_crb_defconfig index f7b256d2c84..9f81e9975a4 100644 --- a/boards/acrn/acrn/acrn_ehl_crb_defconfig +++ b/boards/acrn/acrn/acrn_ehl_crb_defconfig @@ -13,7 +13,6 @@ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=1900000000 CONFIG_BUILD_OUTPUT_BIN=y CONFIG_SHELL_BACKEND_SERIAL_INTERRUPT_DRIVEN=n CONFIG_KERNEL_VM_SIZE=0x1000000 -CONFIG_BUILD_NO_GAP_FILL=y CONFIG_APIC_TSC_DEADLINE_TIMER=y CONFIG_APIC_TIMER_IRQ_PRIORITY=1 CONFIG_SMP=y diff --git a/boards/actinius/icarus/doc/index.rst b/boards/actinius/icarus/doc/index.rst index 8092c53c8c9..4ac623efe2f 100644 --- a/boards/actinius/icarus/doc/index.rst +++ b/boards/actinius/icarus/doc/index.rst @@ -1,17 +1,8 @@ -.. _actinius_icarus: - -Actinius Icarus -############### +.. zephyr:board:: actinius_icarus Overview ******** -.. figure:: img/Icarus_front.jpg - :align: center - :alt: Icarus IoT Dev Board - - Icarus IoT Dev Board (nRF9160 Feather) - The Icarus is a cost-effective cellular IoT board in Adafruit's Feather/FeatherWing form factor. It is built around Nordic Semi's nRF9160 modem and combines LTE-M, NB-IoT, GPS, accelerometer, USB, LiPo charger as well as diff --git a/boards/actinius/icarus_bee/doc/index.rst b/boards/actinius/icarus_bee/doc/index.rst index 630d0aa07c7..32378c92d45 100644 --- a/boards/actinius/icarus_bee/doc/index.rst +++ b/boards/actinius/icarus_bee/doc/index.rst @@ -1,17 +1,8 @@ -.. _actinius_icarus_bee: - -Actinius Icarus Bee -################### +.. zephyr:board:: actinius_icarus_bee Overview ******** -.. figure:: img/icarus-bee.jpg - :align: center - :alt: Icarus Bee - - Icarus Bee (nRF9160 Bee) - The Icarus Bee is a cellular IoT board in Bee/xBee form factor. It is built around Nordic Semi's nRF9160 modem and combines LTE-M, NB-IoT, GPS, accelerometer, SPI Flash, RGB LED, Button, diff --git a/boards/actinius/icarus_som/doc/index.rst b/boards/actinius/icarus_som/doc/index.rst index f3206e63fe3..ea4f47a4cf3 100644 --- a/boards/actinius/icarus_som/doc/index.rst +++ b/boards/actinius/icarus_som/doc/index.rst @@ -1,17 +1,8 @@ -.. _actinius_icarus_som: - -Actinius Icarus SoM -################### +.. zephyr:board:: actinius_icarus_som Overview ******** -.. figure:: img/icarus-som.jpg - :align: center - :alt: Icarus SoM - - Icarus SoM (nRF9160) - The Icarus SoM is a coin-sized, easy-to-solder cellular IoT Module built around Nordic Semi's nRF9160 modem and combines LTE-M, NB-IoT, GPS, accelerometer as well as an eSIM and option for diff --git a/boards/actinius/icarus_som_dk/doc/img/icarus-som-dk.jpg b/boards/actinius/icarus_som_dk/doc/img/icarus_som_dk.jpg similarity index 100% rename from boards/actinius/icarus_som_dk/doc/img/icarus-som-dk.jpg rename to boards/actinius/icarus_som_dk/doc/img/icarus_som_dk.jpg diff --git a/boards/actinius/icarus_som_dk/doc/img/icarus-som-dk-block-diagram.jpg b/boards/actinius/icarus_som_dk/doc/img/icarus_som_dk_block_diagram.jpg similarity index 100% rename from boards/actinius/icarus_som_dk/doc/img/icarus-som-dk-block-diagram.jpg rename to boards/actinius/icarus_som_dk/doc/img/icarus_som_dk_block_diagram.jpg diff --git a/boards/actinius/icarus_som_dk/doc/index.rst b/boards/actinius/icarus_som_dk/doc/index.rst index c0d0a940339..bca73ddbde7 100644 --- a/boards/actinius/icarus_som_dk/doc/index.rst +++ b/boards/actinius/icarus_som_dk/doc/index.rst @@ -1,18 +1,8 @@ -.. _actinius_icarus_som_dk: - -Actinius Icarus SoM DK -###################### +.. zephyr:board:: actinius_icarus_som_dk Overview ******** -.. figure:: img/icarus-som-dk.jpg - :width: 450px - :align: center - :alt: Icarus SoM DK - - Icarus SoM Development Kit (nRF9160) - The Icarus SoM DK is a single board development kit for evaluation and development on the Icarus SoM (`Icarus SoM Docs`_). The Icarus SoM features the nRF9160 SiP from Nordic Semiconductor, @@ -42,7 +32,7 @@ following devices (provided directly by Nordic): * :abbr:`WDT (Watchdog Timer)` * :abbr:`IDAU (Implementation Defined Attribution Unit)` -.. figure:: img/icarus-som-dk-block-diagram.jpg +.. figure:: img/icarus_som_dk_block_diagram.jpg :width: 450px :align: center :alt: Icarus SoM DK Block Diagram diff --git a/boards/adafruit/feather_m0_basic_proto/doc/index.rst b/boards/adafruit/feather_m0_basic_proto/doc/index.rst index a01fe241d59..20d1cd4750a 100644 --- a/boards/adafruit/feather_m0_basic_proto/doc/index.rst +++ b/boards/adafruit/feather_m0_basic_proto/doc/index.rst @@ -1,7 +1,4 @@ -.. _adafruit_feather_m0_basic_proto: - -Adafruit Feather M0 Basic Proto -############################### +.. zephyr:board:: adafruit_feather_m0_basic_proto Overview ******** @@ -11,10 +8,6 @@ board with an onboard battery connector and charger for 3.7 V lithium polymer batteries, charging status indicator and user LEDs, native USB connector, 20 I/O pins, and a small prototyping area. -.. image:: img/adafruit_feather_m0_basic_proto.jpg - :align: center - :alt: Adafruit Feather M0 Basic Proto - Hardware ******** diff --git a/boards/adafruit/feather_m0_lora/doc/index.rst b/boards/adafruit/feather_m0_lora/doc/index.rst index 92d63b36ce3..7a3e9fc78bf 100644 --- a/boards/adafruit/feather_m0_lora/doc/index.rst +++ b/boards/adafruit/feather_m0_lora/doc/index.rst @@ -1,7 +1,4 @@ -.. _adafruit_feather_m0_lora: - -Adafruit Feather M0 LoRa -######################## +.. zephyr:board:: adafruit_feather_m0_lora Overview ******** @@ -11,10 +8,6 @@ boards with an onboard battery connector and charger for 3.7 V lithium polymer batteries, charging status indicator and user LEDs, native USB connector, 20 I/O pins, and a LoRa radio module from Semtech. -.. image:: img/adafruit_feather_m0_lora.jpg - :align: center - :alt: Adafruit Feather M0 LoRa - Hardware ******** diff --git a/boards/adafruit/feather_m4_express/Kconfig.adafruit_feather_m4_express b/boards/adafruit/feather_m4_express/Kconfig.adafruit_feather_m4_express new file mode 100644 index 00000000000..747fade8f4a --- /dev/null +++ b/boards/adafruit/feather_m4_express/Kconfig.adafruit_feather_m4_express @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Daikin Comfort Technologies North America, Inc. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ADAFRUIT_FEATHER_M4_EXPRESS + select SOC_SAMD51J19A diff --git a/boards/adafruit/feather_m4_express/adafruit_feather_m4_express-pinctrl.dtsi b/boards/adafruit/feather_m4_express/adafruit_feather_m4_express-pinctrl.dtsi new file mode 100644 index 00000000000..a96cf644f40 --- /dev/null +++ b/boards/adafruit/feather_m4_express/adafruit_feather_m4_express-pinctrl.dtsi @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2022, Gerson Fernando Budke + * Copyright (c) 2024 Daikin Comfort Technologies North America, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + sercom1_spi_default: sercom1_spi_default { + group1 { + pinmux = , + , + ; + }; + }; + + sercom2_i2c_default: sercom3_i2c_default { + group1 { + pinmux = , + ; + }; + }; + + sercom5_uart_default: sercom5_uart_default { + group1 { + pinmux = , + ; + }; + }; + + pwm0_default: pwm0_default { + group1 { + pinmux = ; + }; + }; + + tc0_default: tc0_default { + group1 { + pinmux = ; + }; + }; + + usb_dc_default: usb_dc_default { + group1 { + pinmux = , + ; + }; + }; +}; diff --git a/boards/adafruit/feather_m4_express/adafruit_feather_m4_express.dts b/boards/adafruit/feather_m4_express/adafruit_feather_m4_express.dts new file mode 100644 index 00000000000..a77a3d2b7ae --- /dev/null +++ b/boards/adafruit/feather_m4_express/adafruit_feather_m4_express.dts @@ -0,0 +1,123 @@ +/* + * Copyright (c) 2020 Google LLC. + * Copyright (c) 2024 Daikin Comfort Technologies North America, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "adafruit_feather_m4_express-pinctrl.dtsi" + +/ { + model = "Adafruit Feather M4 Express"; + compatible = "adafruit,feather-m4-express"; + + chosen { + zephyr,console = &sercom5; + zephyr,shell-uart = &sercom5; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,code-partition = &code_partition; + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + led0 = &led0; + pwm-0 = &tcc0; + pwm-1 = &tc0; + }; + + leds { + compatible = "gpio-leds"; + led0: led_0 { + gpios = <&porta 23 0>; + label = "LED"; + }; + }; +}; + +&cpu0 { + clock-frequency = <120000000>; +}; + +&sercom5 { + status = "okay"; + compatible = "atmel,sam0-uart"; + current-speed = <115200>; + rxpo = <1>; + txpo = <0>; + pinctrl-0 = <&sercom5_uart_default>; + pinctrl-names = "default"; +}; + +&sercom1 { + status = "okay"; + compatible = "atmel,sam0-spi"; + dipo = <3>; + dopo = <0>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&sercom1_spi_default>; + pinctrl-names = "default"; +}; + +&tcc0 { + status = "okay"; + compatible = "atmel,sam0-tcc-pwm"; + prescaler = <8>; + #pwm-cells = <2>; + pinctrl-0 = <&pwm0_default>; + pinctrl-names = "default"; +}; + +&tc0 { + status = "okay"; + compatible = "atmel,sam0-tc-pwm"; + prescaler = <1024>; + #pwm-cells = <2>; + channels = <2>; + counter-size = <16>; + pinctrl-0 = <&tc0_default>; + pinctrl-names = "default"; +}; + +zephyr_udc0: &usb0 { + status = "okay"; + pinctrl-0 = <&usb_dc_default>; + pinctrl-names = "default"; +}; + +&dmac { + status = "okay"; +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "uf2"; + reg = <0x00000000 DT_SIZE_K(16)>; + read-only; + }; + + code_partition: partition@4000 { + label = "code"; + reg = <0x4000 DT_SIZE_K(512-16-16)>; + read-only; + }; + + /* + * The final 16 KiB is reserved for the application. + * Storage partition will be used by FCB/LittleFS/NVS + * if enabled. + */ + storage_partition: partition@7c000 { + label = "storage"; + reg = <0x7c000 DT_SIZE_K(16)>; + }; + }; +}; diff --git a/boards/adafruit/feather_m4_express/adafruit_feather_m4_express.yaml b/boards/adafruit/feather_m4_express/adafruit_feather_m4_express.yaml new file mode 100644 index 00000000000..a8d50925d9f --- /dev/null +++ b/boards/adafruit/feather_m4_express/adafruit_feather_m4_express.yaml @@ -0,0 +1,20 @@ +identifier: adafruit_feather_m4_express +name: Adafruit Feather M4 Express +type: mcu +arch: arm +ram: 192 +flash: 512 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - dma + - gpio + - hwinfo + - pwm + - spi + - uart + - usb_device + - watchdog +vendor: adafruit diff --git a/boards/adafruit/feather_m4_express/adafruit_feather_m4_express_defconfig b/boards/adafruit/feather_m4_express/adafruit_feather_m4_express_defconfig new file mode 100644 index 00000000000..5cb651c5bb6 --- /dev/null +++ b/boards/adafruit/feather_m4_express/adafruit_feather_m4_express_defconfig @@ -0,0 +1,17 @@ +# Copyright (c) 2024 Daikin Comfort Technologies North America, Inc. +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SOC_ATMEL_SAMD5X_OSCULP32K_AS_MAIN=y + +CONFIG_BOOTLOADER_BOSSA=y +CONFIG_BOOTLOADER_BOSSA_ADAFRUIT_UF2=y +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_BUILD_OUTPUT_UF2=y + +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/adafruit/feather_m4_express/board.cmake b/boards/adafruit/feather_m4_express/board.cmake new file mode 100644 index 00000000000..e240a42f36a --- /dev/null +++ b/boards/adafruit/feather_m4_express/board.cmake @@ -0,0 +1,5 @@ +# Copyright (c) 2020 Google LLC. +# SPDX-License-Identifier: Apache-2.0 + +include(${ZEPHYR_BASE}/boards/common/bossac.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/adafruit/feather_m4_express/board.yml b/boards/adafruit/feather_m4_express/board.yml new file mode 100644 index 00000000000..5b9961e1f9e --- /dev/null +++ b/boards/adafruit/feather_m4_express/board.yml @@ -0,0 +1,6 @@ +board: + name: adafruit_feather_m4_express + full_name: Feather M4 Express + vendor: adafruit + socs: + - name: samd51j19a diff --git a/boards/adafruit/feather_m4_express/doc/img/adafruit_feather_m4_express.webp b/boards/adafruit/feather_m4_express/doc/img/adafruit_feather_m4_express.webp new file mode 100644 index 00000000000..62ad405f9de Binary files /dev/null and b/boards/adafruit/feather_m4_express/doc/img/adafruit_feather_m4_express.webp differ diff --git a/boards/adafruit/feather_m4_express/doc/index.rst b/boards/adafruit/feather_m4_express/doc/index.rst new file mode 100644 index 00000000000..a4178626eee --- /dev/null +++ b/boards/adafruit/feather_m4_express/doc/index.rst @@ -0,0 +1,201 @@ +.. zephyr:board:: adafruit_feather_m4_express + +Overview +******** + +The Adafruit Feather M4 Express is a compact, lightweight +ARM development board with an onboard mini NeoPixel, 2 MiB +of SPI flash, charging status indicator and user LEDs, USB +connector, 21 GPIO pins and a small prototyping area. + +Hardware +******** + +- ATSAMD51J19A ARM Cortex-M4 processor at 120 MHz +- 512 KiB of flash memory and 192 KiB of RAM +- 2 MiB of SPI flash +- Internal trimmed 8 MHz oscillator +- A user LED +- An RGB NeoPixel LED +- Native USB port +- One reset button + +Supported Features +================== + +The ``adafruit_feather_m4_express`` board target supports the following +hardware features: + ++-----------+------------+------------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+==========================================+ +| SYSTICK | on-chip | systick | ++-----------+------------+------------------------------------------+ +| WDT | on-chip | Watchdog | ++-----------+------------+------------------------------------------+ +| GPIO | on-chip | I/O ports | ++-----------+------------+------------------------------------------+ +| USART | on-chip | Serial ports | ++-----------+------------+------------------------------------------+ +| SPI | on-chip | Serial Peripheral Interface ports | ++-----------+------------+------------------------------------------+ +| TRNG | on-chip | True Random Number Generator | ++-----------+------------+------------------------------------------+ +| HWINFO | on-chip | Unique 128 bit serial number | ++-----------+------------+------------------------------------------+ +| RTC | on-chip | Real-Time Counter | ++-----------+------------+------------------------------------------+ +| USB | on-chip | USB device | ++-----------+------------+------------------------------------------+ +| WDT | on-chip | Watchdog Timer | ++-----------+------------+------------------------------------------+ +| PWM | on-chip | PWM | ++-----------+------------+------------------------------------------+ + +Other hardware features are not currently supported by Zephyr. + +The default configuration can be found in the Kconfig file +:zephyr_file:`boards/adafruit/feather_m4_express/adafruit_feather_m4_express_defconfig`. + +Zephyr can use the default Cortex-M SYSTICK timer or the SAM0 specific RTC. +To use the RTC, set :code:`CONFIG_CORTEX_M_SYSTICK=n` and set +:code:`CONFIG_SYS_CLOCK_TICKS_PER_SEC` to no more than 32 kHZ divided by 7, +i.e. no more than 4500. + +Connections and IOs +=================== + +The `Adafruit Learning System`_ has detailed information about +the board including `pinouts`_ and the `schematic`_. + +System Clock +============ + +The SAMD51 MCU is configured to use the 32 kHz internal oscillator +with the on-chip PLL generating the 120 MHz system clock. + +Serial Port +=========== + +The SAMD51 MCU has 6 SERCOM based USARTs. On the Feather, SERCOM5 is +the Zephyr console and is available on pins 0 (RX) and 1 (TX). + +SPI Port +======== + +The SAMD51 MCU has 6 SERCOM based SPIs. On the Feather, SERCOM1 can be put +into SPI mode and used to connect to devices over the SCK (SCLK), MO (MOSI), and +MI (MISO) pins. + +PWM +=== + +The SAMD51 has three PWM generators with up to six channels each. :code:`TCC_0` +has a resolution of 24 bits and all other generators are 16 bit. :code:`TCC_1` +pin 2 is mapped to PA18 (D7) and pin 3 is mapped to PA19 (D9). + +USB Device Port +=============== + +The SAMD51 MCU has a USB device port that can be used to communicate +with a host PC. See the :ref:`usb` sample applications for +more, such as the :zephyr:code-sample:`usb-cdc-acm` sample which sets up a virtual +serial port that echos characters back to the host PC. + +Programming and Debugging +************************* + +The Feather ships with a the BOSSA compatible UF2 bootloader. The +bootloader can be entered by quickly tapping the reset button twice. + +Additionally, if :kconfig:option:`CONFIG_USB_CDC_ACM` is enabled then the +bootloader will be entered automatically when you run :code:`west flash`. + +Flashing +======== + +#. Build the Zephyr kernel and the :zephyr:code-sample:`hello_world` sample application: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: adafruit_feather_m4_express + :goals: build + :compact: + +#. Connect the feather to your host computer using USB + +#. Connect a 3.3 V USB to serial adapter to the board and to the + host. See the `Serial Port`_ section above for the board's pin + connections. + +#. Run your favorite terminal program to listen for output. Under Linux the + terminal should be :code:`/dev/ttyUSB0`. For example: + + .. code-block:: console + + $ minicom -D /dev/ttyUSB0 -o + + The -o option tells minicom not to send the modem initialization + string. Connection should be configured as follows: + + - Speed: 115200 + - Data: 8 bits + - Parity: None + - Stop bits: 1 + +#. Tap the reset button twice quickly to enter bootloader mode + +#. Flash the image: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: adafruit_feather_m4_express + :goals: flash + :compact: + + You should see "Hello World! adafruit_feather_m4_express" in your terminal. + +Debugging +========= + +In addition to the built-in bootloader, the Feather can be flashed and +debugged using a SWD probe such as the Segger J-Link. + +#. Connect the board to the probe by connecting the :code:`SWCLK`, + :code:`SWDIO`, :code:`RESET`, :code:`GND`, and :code:`3V3` pins on the + Feather to the :code:`SWCLK`, :code:`SWDIO`, :code:`RESET`, :code:`GND`, + and :code:`VTref` pins on the `J-Link`_. + +#. Flash the image: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: adafruit_feather_m4_express + :goals: flash + :flash-args: -r openocd + :compact: + +#. Start debugging: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: adafruit_feather_m4_express + :goals: debug + :compact: + +References +********** + +.. target-notes:: + +.. _Adafruit Learning System: + https://learn.adafruit.com/adafruit-feather-m4-express-atsamd51 + +.. _pinouts: + https://learn.adafruit.com/adafruit-feather-m4-express-atsamd51/pinouts + +.. _schematic: + https://learn.adafruit.com/adafruit-feather-m4-express-atsamd51/downloads + +.. _J-Link: + https://www.segger.com/products/debug-probes/j-link/technology/interface-description/ diff --git a/boards/adafruit/feather_m4_express/pre_dt_board.cmake b/boards/adafruit/feather_m4_express/pre_dt_board.cmake new file mode 100644 index 00000000000..9be9a0b9771 --- /dev/null +++ b/boards/adafruit/feather_m4_express/pre_dt_board.cmake @@ -0,0 +1,7 @@ +# Copyright (c) 2021 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +# Suppress "unique_unit_address_if_enabled" to handle the following overlaps: +# - /soc/pinmux@41004400 & /soc/gpio@41004400 +# - /soc/pinmux@41004480 & /soc/gpio@41004480 +list(APPEND EXTRA_DTC_FLAGS "-Wno-unique_unit_address_if_enabled") diff --git a/boards/adafruit/feather_m4_express/support/openocd.cfg b/boards/adafruit/feather_m4_express/support/openocd.cfg new file mode 100644 index 00000000000..9990cf9036a --- /dev/null +++ b/boards/adafruit/feather_m4_express/support/openocd.cfg @@ -0,0 +1,21 @@ +source [find interface/jlink.cfg] + +transport select swd + +set CHIPNAME atsamd51j19a +source [find target/atsame5x.cfg] + +# TODO(http://openocd.zylin.com/#/c/5706/): lower the clock speed to workaround +# an erase timeout. +adapter speed 500 +reset_config srst_only + +$_TARGETNAME configure -event gdb-attach { + echo "Debugger attaching: halting execution" + reset halt +} + +$_TARGETNAME configure -event gdb-detach { + echo "Debugger detaching: resuming execution" + resume +} diff --git a/boards/adafruit/feather_nrf52840/Kconfig.defconfig b/boards/adafruit/feather_nrf52840/Kconfig.defconfig index 5e42fcfb8aa..f6351510d2f 100644 --- a/boards/adafruit/feather_nrf52840/Kconfig.defconfig +++ b/boards/adafruit/feather_nrf52840/Kconfig.defconfig @@ -6,7 +6,10 @@ if BOARD_ADAFRUIT_FEATHER_NRF52840 -config BT_CTLR - default BT +if BOARD_ADAFRUIT_FEATHER_NRF52840_NRF52840_UF2 || BOARD_ADAFRUIT_FEATHER_NRF52840_NRF52840_SENSE_UF2 + +source "boards/common/usb/Kconfig.cdc_acm_serial.defconfig" + +endif endif # BOARD_ADAFRUIT_FEATHER_NRF52840 diff --git a/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840_flash_uf2.dtsi b/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840_flash_uf2.dtsi deleted file mode 100644 index 805b853ce31..00000000000 --- a/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840_flash_uf2.dtsi +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright (c) 2024 Jacob Winther - * - * SPDX-License-Identifier: Apache-2.0 - * - * Default flash layout for nrf52840 using UF2 - */ - -/ { - chosen { - zephyr,sram = &sram0; - zephyr,flash = &flash0; - zephyr,code-partition = &code_partition; - }; -}; - -&flash0 { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* To enable flashing with UF2 bootloader, we - * must reserve a partition for SoftDevice. - * See https://learn.adafruit.com/ - * introducing-the-adafruit-nrf52840-feather?view=all#hathach-memory-map - */ - reserved_partition_0: partition@0 { - label = "SoftDevice"; - read-only; - reg = <0x000000000 DT_SIZE_K(152)>; - }; - code_partition: partition@26000 { - label = "Application"; - reg = <0x00026000 DT_SIZE_K(796)>; - }; - - /* - * The flash starting at 0x000ed000 and ending at - * 0x000f4000 is reserved for use by the application. - */ - storage_partition: partition@ed000 { - label = "storage"; - reg = <0x0000ed000 DT_SIZE_K(28)>; - }; - - boot_partition: partition@f4000 { - label = "UF2"; - read-only; - reg = <0x000f4000 DT_SIZE_K(48)>; - }; - }; -}; diff --git a/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840_nrf52840_sense.yaml b/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840_nrf52840_sense.yaml index 276870f44d3..e4a94b6bb36 100644 --- a/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840_nrf52840_sense.yaml +++ b/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840_nrf52840_sense.yaml @@ -9,7 +9,6 @@ toolchain: supported: - adc - usb_device - - usb_cdc - ble - watchdog - counter diff --git a/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840_nrf52840_sense_uf2.dts b/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840_nrf52840_sense_uf2.dts index 0ad7ee1e960..faafb8381fe 100644 --- a/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840_nrf52840_sense_uf2.dts +++ b/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840_nrf52840_sense_uf2.dts @@ -7,20 +7,13 @@ /dts-v1/; #include "adafruit_feather_nrf52840_common.dtsi" -#include "adafruit_feather_nrf52840_flash_uf2.dtsi" +#include +#include <../boards/common/usb/cdc_acm_serial.dtsi> / { model = "Adafruit Feather nRF52840 Sense"; compatible = "adafruit,feather-nrf52840-sense-uf2"; - chosen { - zephyr,console = &cdc_acm_uart0; - zephyr,shell-uart = &cdc_acm_uart0; - zephyr,uart-mcumgr = &cdc_acm_uart0; - zephyr,bt-mon-uart = &cdc_acm_uart0; - zephyr,bt-c2h-uart = &cdc_acm_uart0; - }; - leds { led0: led_0 { gpios = <&gpio1 9 0>; @@ -34,9 +27,3 @@ reg = <0x44>; }; }; - -zephyr_udc0: &usbd { - cdc_acm_uart0: cdc_acm_uart0 { - compatible = "zephyr,cdc-acm-uart"; - }; -}; diff --git a/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840_nrf52840_sense_uf2.yaml b/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840_nrf52840_sense_uf2.yaml index 08eb1eaa7f1..a5f095b336b 100644 --- a/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840_nrf52840_sense_uf2.yaml +++ b/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840_nrf52840_sense_uf2.yaml @@ -9,7 +9,6 @@ toolchain: supported: - adc - usb_device - - usb_cdc - ble - watchdog - counter diff --git a/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840_nrf52840_sense_uf2_defconfig b/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840_nrf52840_sense_uf2_defconfig index 18c22c337d0..42f7298af55 100644 --- a/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840_nrf52840_sense_uf2_defconfig +++ b/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840_nrf52840_sense_uf2_defconfig @@ -17,11 +17,5 @@ CONFIG_UART_CONSOLE=y CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC=y CONFIG_CLOCK_CONTROL_NRF_K32SRC_500PPM=y -# Logger cannot use itself to log -CONFIG_USB_CDC_ACM_LOG_LEVEL_OFF=y - -# Enable USB -CONFIG_USB_DEVICE_STACK=y - # Build UF2 by default, supported by the Adafruit nRF52 Bootloader CONFIG_BUILD_OUTPUT_UF2=y diff --git a/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840_nrf52840_uf2.dts b/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840_nrf52840_uf2.dts index 33f2d3e598c..f4c30d6aec0 100644 --- a/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840_nrf52840_uf2.dts +++ b/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840_nrf52840_uf2.dts @@ -6,29 +6,16 @@ /dts-v1/; #include "adafruit_feather_nrf52840_common.dtsi" -#include "adafruit_feather_nrf52840_flash_uf2.dtsi" +#include +#include <../boards/common/usb/cdc_acm_serial.dtsi> / { model = "Adafruit Feather nRF52840 Express"; compatible = "adafruit,feather-nrf52840-uf2"; - chosen { - zephyr,console = &cdc_acm_uart0; - zephyr,shell-uart = &cdc_acm_uart0; - zephyr,uart-mcumgr = &cdc_acm_uart0; - zephyr,bt-mon-uart = &cdc_acm_uart0; - zephyr,bt-c2h-uart = &cdc_acm_uart0; - }; - leds { led0: led_0 { gpios = <&gpio1 15 0>; }; }; }; - -zephyr_udc0: &usbd { - cdc_acm_uart0: cdc_acm_uart0 { - compatible = "zephyr,cdc-acm-uart"; - }; -}; diff --git a/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840_nrf52840_uf2_defconfig b/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840_nrf52840_uf2_defconfig index f6ec2097646..a40094157e3 100644 --- a/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840_nrf52840_uf2_defconfig +++ b/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840_nrf52840_uf2_defconfig @@ -13,11 +13,5 @@ CONFIG_SERIAL=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y -# Logger cannot use itself to log -CONFIG_USB_CDC_ACM_LOG_LEVEL_OFF=y - -# Enable USB -CONFIG_USB_DEVICE_STACK=y - # Build UF2 by default, supported by the Adafruit nRF52 Bootloader CONFIG_BUILD_OUTPUT_UF2=y diff --git a/boards/adafruit/feather_nrf52840/doc/index.rst b/boards/adafruit/feather_nrf52840/doc/index.rst index 7ab630978d4..6f2477e673f 100644 --- a/boards/adafruit/feather_nrf52840/doc/index.rst +++ b/boards/adafruit/feather_nrf52840/doc/index.rst @@ -1,7 +1,4 @@ -.. _adafruit_feather_nrf52840: - -Adafruit Feather nRF52840 (Express, Sense) -########################################## +.. zephyr:board:: adafruit_feather_nrf52840 Overview ******** diff --git a/boards/adafruit/feather_stm32f405/adafruit_feather_stm32f405.yaml b/boards/adafruit/feather_stm32f405/adafruit_feather_stm32f405.yaml index f71d8d7cab3..858b4fcf6db 100644 --- a/boards/adafruit/feather_stm32f405/adafruit_feather_stm32f405.yaml +++ b/boards/adafruit/feather_stm32f405/adafruit_feather_stm32f405.yaml @@ -11,7 +11,6 @@ flash: 1024 supported: - i2c - spi - - usb - feather_serial - feather_i2c - feather_spi diff --git a/boards/adafruit/feather_stm32f405/doc/index.rst b/boards/adafruit/feather_stm32f405/doc/index.rst index 47d70537e69..0cc6c327760 100644 --- a/boards/adafruit/feather_stm32f405/doc/index.rst +++ b/boards/adafruit/feather_stm32f405/doc/index.rst @@ -1,7 +1,4 @@ -.. _adafruit_feather_stm32f405: - -Adafruit Feather STM32F405 Express -################################## +.. zephyr:board:: adafruit_feather_stm32f405 Overview ******** @@ -12,10 +9,6 @@ devices labeled as Feathers or FeatherWings. The board is equipped with a lithium ion battery charger, native USB C connector, 2MB of external flash memory, and SD card socket. -.. image:: img/adafruit_feather_stm32f405.jpg - :align: center - :alt: Adafruit Feather STM32F405 Express - Hardware ******** diff --git a/boards/adafruit/grand_central_m4_express/adafruit_grand_central_m4_express.dts b/boards/adafruit/grand_central_m4_express/adafruit_grand_central_m4_express.dts index 5cc038332b1..24ffdf89acf 100644 --- a/boards/adafruit/grand_central_m4_express/adafruit_grand_central_m4_express.dts +++ b/boards/adafruit/grand_central_m4_express/adafruit_grand_central_m4_express.dts @@ -72,6 +72,7 @@ mmc { status = "okay"; compatible = "zephyr,sdmmc-disk"; + disk-name = "SD"; }; }; }; diff --git a/boards/adafruit/grand_central_m4_express/doc/index.rst b/boards/adafruit/grand_central_m4_express/doc/index.rst index 0244fa73f87..4bab8889967 100644 --- a/boards/adafruit/grand_central_m4_express/doc/index.rst +++ b/boards/adafruit/grand_central_m4_express/doc/index.rst @@ -1,7 +1,4 @@ -.. _adafruit_grand_central_m4_express: - -Adafruit Grand Central M4 Express -################################# +.. zephyr:board:: adafruit_grand_central_m4_express Overview ******** @@ -10,13 +7,6 @@ The Adafruit Grand Central M4 Express is an ARM development board with the form factor of an Arduino Mega. It features 70 GPIO pins, a microSDHC slot and 8MiB of QSPI Flash. -.. figure:: img/adafruit_grand_central_m4_express.webp - :width: 800px - :align: center - :alt: Adafruit Grand Central M4 Express - - Adafruit Grand Central M4 Express (Credit: Kattni Rembor / Adafruit) - Hardware ******** diff --git a/boards/adafruit/itsybitsy/Kconfig b/boards/adafruit/itsybitsy/Kconfig deleted file mode 100644 index 8aa3368ffd6..00000000000 --- a/boards/adafruit/itsybitsy/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -# Adafruit ItsyBitsy nRF52840 Express board configuration - -# Copyright (c) 2022 Embla Flatlandsmo -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_SERIAL_BACKEND_CDC_ACM - bool "USB CDC" - default y - depends on BOARD_ADAFRUIT_ITSYBITSY diff --git a/boards/adafruit/itsybitsy/Kconfig.defconfig b/boards/adafruit/itsybitsy/Kconfig.defconfig index b637497e148..02cbfc35fe2 100644 --- a/boards/adafruit/itsybitsy/Kconfig.defconfig +++ b/boards/adafruit/itsybitsy/Kconfig.defconfig @@ -5,49 +5,6 @@ if BOARD_ADAFRUIT_ITSYBITSY -config BT_CTLR - default BT - -if BOARD_SERIAL_BACKEND_CDC_ACM - -config USB_DEVICE_STACK - default y - -config USB_CDC_ACM - default SERIAL - -config UART_CONSOLE - default CONSOLE - -config USB_DEVICE_INITIALIZE_AT_BOOT - default y if CONSOLE - -config SHELL_BACKEND_SERIAL_CHECK_DTR - default SHELL - depends on UART_LINE_CTRL - -config UART_LINE_CTRL - default SHELL - -config USB_DEVICE_REMOTE_WAKEUP - default n - -if LOG - -# Logger cannot use itself to log -config USB_CDC_ACM_LOG_LEVEL - default 0 - -# Set USB log level to error only -config USB_DEVICE_LOG_LEVEL - default 1 - -# Wait 1500ms at startup for logging -config LOG_PROCESS_THREAD_STARTUP_DELAY_MS - default 1500 - -endif # LOG - -endif # BOARD_SERIAL_BACKEND_CDC_ACM +source "boards/common/usb/Kconfig.cdc_acm_serial.defconfig" endif # BOARD_ADAFRUIT_ITSYBITSY diff --git a/boards/adafruit/itsybitsy/adafruit_itsybitsy_nrf52840.dts b/boards/adafruit/itsybitsy/adafruit_itsybitsy_nrf52840.dts index 087ddc17307..a4ff029e93b 100644 --- a/boards/adafruit/itsybitsy/adafruit_itsybitsy_nrf52840.dts +++ b/boards/adafruit/itsybitsy/adafruit_itsybitsy_nrf52840.dts @@ -6,6 +6,7 @@ /dts-v1/; #include +#include #include "adafruit_itsybitsy_nrf52840-pinctrl.dtsi" #include #include @@ -15,14 +16,6 @@ compatible = "adafruit,itsybitsy-nrf52840"; chosen { - zephyr,console = &cdc_acm_uart0; - zephyr,shell-uart = &cdc_acm_uart0; - zephyr,uart-mcumgr = &cdc_acm_uart0; - zephyr,bt-mon-uart = &cdc_acm_uart0; - zephyr,bt-c2h-uart = &cdc_acm_uart0; - zephyr,sram = &sram0; - zephyr,flash = &flash0; - zephyr,code-partition = &code_partition; zephyr,ieee802154 = &ieee802154; }; @@ -142,41 +135,6 @@ status = "okay"; }; -&flash0 { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* To enable flashing with UF2 bootloader, we - * must reserve a partition for SoftDevice. - * See https://learn.adafruit.com/introducing-the-adafruit-nrf52840-feather?view=all#hathach-memory-map - */ - reserved_partition_0: partition@0 { - label = "SoftDevice"; - reg = <0x000000000 DT_SIZE_K(152)>; - }; - code_partition: partition@26000 { - label = "Application"; - reg = <0x00026000 DT_SIZE_K(796)>; - }; - - /* - * The flash starting at 0x000ed000 and ending at - * 0x000f4000 is reserved for use by the application. - */ - storage_partition: partition@ed000 { - label = "storage"; - reg = <0x0000ed000 DT_SIZE_K(28)>; - }; - - boot_partition: partition@f4000 { - label = "UF2"; - reg = <0x000f4000 DT_SIZE_K(48)>; - }; - }; -}; - &gd25q16 { partitions { compatible = "fixed-partitions"; @@ -192,8 +150,6 @@ zephyr_udc0: &usbd { compatible = "nordic,nrf-usbd"; status = "okay"; - - cdc_acm_uart0: cdc_acm_uart0 { - compatible = "zephyr,cdc-acm-uart"; - }; }; + +#include <../boards/common/usb/cdc_acm_serial.dtsi> diff --git a/boards/adafruit/itsybitsy/doc/index.rst b/boards/adafruit/itsybitsy/doc/index.rst index c2e4330c04d..3fbcb918adb 100644 --- a/boards/adafruit/itsybitsy/doc/index.rst +++ b/boards/adafruit/itsybitsy/doc/index.rst @@ -1,7 +1,4 @@ -.. _adafruit_itsybitsy_nrf52840: - -Adafruit ItsyBitsy nRF52840 -########################### +.. zephyr:board:: adafruit_itsybitsy Overview ******** @@ -29,10 +26,6 @@ This development kit has the following features: * :abbr:`USB (Universal Serial Bus)` * :abbr:`WDT (Watchdog Timer)` -.. image:: img/adafruit_itsybitsy_nrf52840.jpeg - :align: center - :alt: Adafruit ItsyBitsy nRF52840 Express - Hardware ******** - nRF52840 ARM Cortex-M4F CPU at 64MHz diff --git a/boards/adafruit/itsybitsy_m4_express/doc/index.rst b/boards/adafruit/itsybitsy_m4_express/doc/index.rst index 2ab1f7a5853..31e19cb8a99 100644 --- a/boards/adafruit/itsybitsy_m4_express/doc/index.rst +++ b/boards/adafruit/itsybitsy_m4_express/doc/index.rst @@ -1,7 +1,4 @@ -.. _adafruit_itsybitsy_m4_express: - -Adafruit ItsyBitsy M4 Express -############################# +.. zephyr:board:: adafruit_itsybitsy_m4_express Overview ******** @@ -10,10 +7,6 @@ The Adafruit ItsyBitsy M4 express is a small (36 mm x 18 mm) ARM development board with an onboard RGB LED, USB port, 2 MiB of SPI flash, and range of I/O broken out onto 23 GPIO pins. -.. image:: img/adafruit_itsybitsy_m4_express.jpg - :align: center - :alt: Adafruit ItsyBitsy M4 Express - Hardware ******** diff --git a/boards/adafruit/kb2040/Kconfig b/boards/adafruit/kb2040/Kconfig new file mode 100644 index 00000000000..b17df8fa389 --- /dev/null +++ b/boards/adafruit/kb2040/Kconfig @@ -0,0 +1,5 @@ +# Copyright (c) 2022 Peter Johanson +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ADAFRUIT_KB2040 + select RP2_FLASH_W25Q080 diff --git a/boards/adafruit/kb2040/Kconfig.defconfig b/boards/adafruit/kb2040/Kconfig.defconfig index e17682abac0..7cf4aec08f0 100644 --- a/boards/adafruit/kb2040/Kconfig.defconfig +++ b/boards/adafruit/kb2040/Kconfig.defconfig @@ -3,9 +3,6 @@ if BOARD_ADAFRUIT_KB2040 -config RP2_FLASH_W25Q080 - default y - if I2C_DW config I2C_DW_CLOCK_SPEED diff --git a/boards/adafruit/kb2040/adafruit_kb2040-pinctrl.dtsi b/boards/adafruit/kb2040/adafruit_kb2040-pinctrl.dtsi index cf1289acedc..79681bb8ad3 100644 --- a/boards/adafruit/kb2040/adafruit_kb2040-pinctrl.dtsi +++ b/boards/adafruit/kb2040/adafruit_kb2040-pinctrl.dtsi @@ -48,9 +48,6 @@ }; }; - clocks_default: clocks_default { - }; - ws2812_pio0_default: ws2812_pio0_default { ws2812 { pinmux = ; diff --git a/boards/adafruit/kb2040/adafruit_kb2040.dts b/boards/adafruit/kb2040/adafruit_kb2040.dts index 45ff45595d2..d7de09cddac 100644 --- a/boards/adafruit/kb2040/adafruit_kb2040.dts +++ b/boards/adafruit/kb2040/adafruit_kb2040.dts @@ -7,7 +7,7 @@ /dts-v1/; -#include +#include #include "adafruit_kb2040-pinctrl.dtsi" #include "sparkfun_pro_micro_connector.dtsi" #include @@ -56,11 +56,6 @@ }; }; -&clocks { - pinctrl-0 = <&clocks_default>; - pinctrl-names = "default"; -}; - &uart0 { current-speed = <115200>; status = "okay"; @@ -127,3 +122,7 @@ zephyr_udc0: &usbd { regulator-always-on; regulator-allowed-modes = ; }; + +&xosc { + startup-delay-multiplier = <64>; +}; diff --git a/boards/adafruit/kb2040/doc/index.rst b/boards/adafruit/kb2040/doc/index.rst index 58b53aec815..f1b5d998dc8 100644 --- a/boards/adafruit/kb2040/doc/index.rst +++ b/boards/adafruit/kb2040/doc/index.rst @@ -1,7 +1,4 @@ -.. _adafruit_kb2040: - -Adafruit KB2040 -############### +.. zephyr:board:: adafruit_kb2040 Overview ******** @@ -27,13 +24,6 @@ Hardware - On-board RGB LED - 1 Watchdog timer peripheral - -.. figure:: img/kb2040.jpg - :align: center - :alt: Adafruit KB2040 - - Adafruit KB2040 (Image courtesy of Adafruit) - Supported Features ================== diff --git a/boards/adafruit/nrf52_adafruit_feather/Kconfig.defconfig b/boards/adafruit/nrf52_adafruit_feather/Kconfig.defconfig index 48cb9d7332d..b1259e40915 100644 --- a/boards/adafruit/nrf52_adafruit_feather/Kconfig.defconfig +++ b/boards/adafruit/nrf52_adafruit_feather/Kconfig.defconfig @@ -5,7 +5,4 @@ if BOARD_NRF52_ADAFRUIT_FEATHER -config BT_CTLR - default BT - endif # BOARD_NRF52_ADAFRUIT_FEATHER diff --git a/boards/adafruit/nrf52_adafruit_feather/doc/index.rst b/boards/adafruit/nrf52_adafruit_feather/doc/index.rst index 1fff89aaeab..c84bc73f62b 100644 --- a/boards/adafruit/nrf52_adafruit_feather/doc/index.rst +++ b/boards/adafruit/nrf52_adafruit_feather/doc/index.rst @@ -1,7 +1,4 @@ -.. _nrf52_adafruit_feather: - -nRF52 Adafruit Feather -###################### +.. zephyr:board:: nrf52_adafruit_feather Overview ******** @@ -18,12 +15,6 @@ the following devices: * RADIO (Bluetooth Low Energy) * Segger RTT (RTT Console) -.. figure:: img/nrf52_adafruit_feather.jpg - :align: center - :alt: nRF52 Adafruit Feather Board - - nRF52 Adafruit Feather Board (Credit: Adafruit) - More information about the board and its features can be found at the `Adafruit Feather nRF52 Bluefruit Learning Guide`_. The `Nordic Semiconductor Infocenter`_ contains the processor's information and the datasheet. diff --git a/boards/adafruit/qt_py_esp32s3/Kconfig b/boards/adafruit/qt_py_esp32s3/Kconfig new file mode 100644 index 00000000000..eff63767823 --- /dev/null +++ b/boards/adafruit/qt_py_esp32s3/Kconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Ian Wakely + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 4096 if BOARD_ADAFRUIT_QT_PY_ESP32S3_ESP32S3_PROCPU + default 256 if BOARD_ADAFRUIT_QT_PY_ESP32S3_ESP32S3_APPCPU diff --git a/boards/adafruit/qt_py_esp32s3/Kconfig.adafruit_qt_py_esp32s3 b/boards/adafruit/qt_py_esp32s3/Kconfig.adafruit_qt_py_esp32s3 new file mode 100644 index 00000000000..9d5e991b572 --- /dev/null +++ b/boards/adafruit/qt_py_esp32s3/Kconfig.adafruit_qt_py_esp32s3 @@ -0,0 +1,9 @@ +# Adafruit ESP32S3 board configuration + +# Copyright (c) 2024 Ian Wakely + +config BOARD_ADAFRUIT_QT_PY_ESP32S3 + select SOC_ESP32S3_WROOM_N8 if "$(BOARD_REVISION)" = "" + select SOC_ESP32S3_WROOM_N4R2 if "$(BOARD_REVISION)" = "psram" + select SOC_ESP32S3_PROCPU if BOARD_ADAFRUIT_QT_PY_ESP32S3_ESP32S3_PROCPU + select SOC_ESP32S3_APPCPU if BOARD_ADAFRUIT_QT_PY_ESP32S3_ESP32S3_APPCPU diff --git a/boards/adafruit/qt_py_esp32s3/Kconfig.sysbuild b/boards/adafruit/qt_py_esp32s3/Kconfig.sysbuild new file mode 100644 index 00000000000..3a2d17ac5cf --- /dev/null +++ b/boards/adafruit/qt_py_esp32s3/Kconfig.sysbuild @@ -0,0 +1,10 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +choice BOOTLOADER + default BOOTLOADER_MCUBOOT +endchoice + +choice BOOT_SIGNATURE_TYPE + default BOOT_SIGNATURE_TYPE_NONE +endchoice diff --git a/boards/adafruit/qt_py_esp32s3/adafruit_qt_py_esp32s3-pinctrl.dtsi b/boards/adafruit/qt_py_esp32s3/adafruit_qt_py_esp32s3-pinctrl.dtsi new file mode 100644 index 00000000000..8c59416d21b --- /dev/null +++ b/boards/adafruit/qt_py_esp32s3/adafruit_qt_py_esp32s3-pinctrl.dtsi @@ -0,0 +1,67 @@ +/* + * Copyright 2022 Google LLC + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +&pinctrl { + uart0_default: uart0_default { + group1 { + pinmux = ; + output-high; + }; + group2 { + pinmux = ; + bias-pull-up; + }; + }; + + spim2_default: spim2_default { + group1 { + pinmux = , + ; + }; + group2 { + pinmux = ; + output-low; + }; + }; + + spim3_ws2812_led: spim3_ws2812_led { + group1 { + pinmux = ; + output-low; + }; + }; + + i2c0_default: i2c0_default { + group1 { + pinmux = , + ; + bias-pull-up; + drive-open-drain; + output-high; + }; + }; + + i2c1_default: i2c1_default { + group1 { + pinmux = , + ; + bias-pull-up; + drive-open-drain; + output-high; + }; + }; + + twai_default: twai_default { + group1 { + pinmux = , + ; + }; + }; +}; diff --git a/boards/adafruit/qt_py_esp32s3/adafruit_qt_py_esp32s3_appcpu.dts b/boards/adafruit/qt_py_esp32s3/adafruit_qt_py_esp32s3_appcpu.dts new file mode 100644 index 00000000000..876a6d78fc6 --- /dev/null +++ b/boards/adafruit/qt_py_esp32s3/adafruit_qt_py_esp32s3_appcpu.dts @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2024 Ian Wakely + */ + +/dts-v1/; + +#include +#include "adafruit_qt_py_esp32s3-pinctrl.dtsi" +#include + +/ { + model = "Adafruit QT Py ESP32S3 APPCPU"; + compatible = "espressif,esp32s3"; + + chosen { + zephyr,sram = &sram1; + zephyr,ipc_shm = &shm0; + zephyr,ipc = &ipm0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_appcpu_partition; + }; +}; + +&trng0 { + status = "okay"; +}; + +&ipm0 { + status = "okay"; +}; diff --git a/boards/adafruit/qt_py_esp32s3/adafruit_qt_py_esp32s3_appcpu.yaml b/boards/adafruit/qt_py_esp32s3/adafruit_qt_py_esp32s3_appcpu.yaml new file mode 100644 index 00000000000..70b5253574c --- /dev/null +++ b/boards/adafruit/qt_py_esp32s3/adafruit_qt_py_esp32s3_appcpu.yaml @@ -0,0 +1,27 @@ +identifier: adafruit_qt_py_esp32s3/esp32s3/appcpu +name: Adafruit QT Py ESP32S3 APPCPU +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - uart +testing: + ignore_tags: + - net + - bluetooth + - flash + - cpp + - posix + - watchdog + - logging + - kernel + - pm + - gpio + - crypto + - eeprom + - heap + - cmsis_rtos + - jwt + - zdsp +vendor: adafruit diff --git a/boards/adafruit/qt_py_esp32s3/adafruit_qt_py_esp32s3_appcpu_defconfig b/boards/adafruit/qt_py_esp32s3/adafruit_qt_py_esp32s3_appcpu_defconfig new file mode 100644 index 00000000000..9abf2ff0430 --- /dev/null +++ b/boards/adafruit/qt_py_esp32s3/adafruit_qt_py_esp32s3_appcpu_defconfig @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 +CONFIG_CLOCK_CONTROL=y diff --git a/boards/adafruit/qt_py_esp32s3/adafruit_qt_py_esp32s3_appcpu_psram.overlay b/boards/adafruit/qt_py_esp32s3/adafruit_qt_py_esp32s3_appcpu_psram.overlay new file mode 100644 index 00000000000..ac1ec4af1b1 --- /dev/null +++ b/boards/adafruit/qt_py_esp32s3/adafruit_qt_py_esp32s3_appcpu_psram.overlay @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2024 Ian Wakely + */ + +/delete-node/ &flash0; + +/ { + model = "Adafruit QT Py ESP32S3 PSRAM APPCPU"; + + soc { + flash: flash-controller@60002000 { + compatible = "espressif,esp32-flash-controller"; + reg = <0x60002000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + /* 4MB flash */ + flash0: flash@0 { + compatible = "soc-nv-flash"; + erase-block-size = <4096>; + write-block-size = <4>; + reg = <0x0 DT_SIZE_M(4)>; + }; + }; + }; +}; + +/* 2MB psram */ +&psram0 { + reg = <0x3c000000 DT_SIZE_M(2)>; + status = "okay"; +}; + +#include diff --git a/boards/adafruit/qt_py_esp32s3/adafruit_qt_py_esp32s3_appcpu_psram.yaml b/boards/adafruit/qt_py_esp32s3/adafruit_qt_py_esp32s3_appcpu_psram.yaml new file mode 100644 index 00000000000..4d3dba70d68 --- /dev/null +++ b/boards/adafruit/qt_py_esp32s3/adafruit_qt_py_esp32s3_appcpu_psram.yaml @@ -0,0 +1,27 @@ +identifier: adafruit_qt_py_esp32s3@psram/esp32s3/appcpu +name: Adafruit QT Py ESP32S3 PSRAM APPCPU +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - uart +testing: + ignore_tags: + - net + - bluetooth + - flash + - cpp + - posix + - watchdog + - logging + - kernel + - pm + - gpio + - crypto + - eeprom + - heap + - cmsis_rtos + - jwt + - zdsp +vendor: adafruit diff --git a/boards/adafruit/qt_py_esp32s3/adafruit_qt_py_esp32s3_procpu.dts b/boards/adafruit/qt_py_esp32s3/adafruit_qt_py_esp32s3_procpu.dts new file mode 100644 index 00000000000..ac757645e5b --- /dev/null +++ b/boards/adafruit/qt_py_esp32s3/adafruit_qt_py_esp32s3_procpu.dts @@ -0,0 +1,149 @@ +/* + * Copyright (c) 2023 Seeed Studio inc. + * Copyright (c) 2024 Ian Wakely + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include +#include "adafruit_qt_py_esp32s3-pinctrl.dtsi" +#include "seeed_xiao_connector.dtsi" +#include + +/ { + model = "Adafruit QT Py ESP32S3 PROCPU"; + compatible = "seeed,xiao-esp32s3"; + + chosen { + zephyr,sram = &sram1; + zephyr,console = &usb_serial; + zephyr,shell-uart = &usb_serial; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + zephyr,bt-hci = &esp32_bt_hci; + }; + + aliases { + i2c-0 = &i2c0; + watchdog0 = &wdt0; + led-strip = &led_strip; + sw0 = &button0; + }; + + buttons { + compatible = "gpio-keys"; + button0: button_0 { + gpios = <&gpio0 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "User button"; + zephyr,code = ; + }; + }; +}; + +&usb_serial { + status = "okay"; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = ; + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; +}; + +&i2c1 { + status = "okay"; + clock-frequency = ; + pinctrl-0 = <&i2c1_default>; + pinctrl-names = "default"; +}; + +&trng0 { + status = "okay"; +}; + +&spi2 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim2_default>; + pinctrl-names = "default"; +}; + +&spi3 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim3_ws2812_led>; + pinctrl-names = "default"; + + line-idle-low; + + led_strip: ws2812@0 { + compatible = "worldsemi,ws2812-spi"; + + /* SPI */ + reg = <0>; /* ignored, but necessary for SPI bindings */ + spi-max-frequency = <6400000>; + + /* WS2812 */ + chain-length = <1>; + spi-cpha; + spi-one-frame = <0xf0>; /* 11110000: 625 ns high and 625 ns low */ + spi-zero-frame = <0xc0>; /* 11000000: 312.5 ns high and 937.5 ns low */ + color-mapping = ; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; + + /* + * Unlike some of the other Adafruit boards, the neopixel on this board has + * its positive side hooked up to a GPIO pin rather than a positive voltage + * rail to save on power. This will enable the LED on board initialization. + */ + neopixel-power-enable { + gpio-hog; + gpios = <6 GPIO_ACTIVE_HIGH>; + output-high; + }; +}; + +&wdt0 { + status = "okay"; +}; + +&twai { + pinctrl-0 = <&twai_default>; + pinctrl-names = "default"; +}; + +&timer0 { + status = "okay"; +}; + +&timer1 { + status = "okay"; +}; + +&esp32_bt_hci { + status = "okay"; +}; diff --git a/boards/adafruit/qt_py_esp32s3/adafruit_qt_py_esp32s3_procpu.yaml b/boards/adafruit/qt_py_esp32s3/adafruit_qt_py_esp32s3_procpu.yaml new file mode 100644 index 00000000000..b3d1cd326eb --- /dev/null +++ b/boards/adafruit/qt_py_esp32s3/adafruit_qt_py_esp32s3_procpu.yaml @@ -0,0 +1,19 @@ +identifier: adafruit_qt_py_esp32s3/esp32s3/procpu +name: Adafruit QT Py ESP32S3 PROCPU +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - gpio + - uart + - i2c + - i2s + - spi + - can + - counter + - watchdog + - entropy + - pwm + - dma +vendor: adafruit diff --git a/boards/adafruit/qt_py_esp32s3/adafruit_qt_py_esp32s3_procpu_defconfig b/boards/adafruit/qt_py_esp32s3/adafruit_qt_py_esp32s3_procpu_defconfig new file mode 100644 index 00000000000..6539bd42e59 --- /dev/null +++ b/boards/adafruit/qt_py_esp32s3/adafruit_qt_py_esp32s3_procpu_defconfig @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_GPIO=y diff --git a/boards/adafruit/qt_py_esp32s3/adafruit_qt_py_esp32s3_procpu_psram.overlay b/boards/adafruit/qt_py_esp32s3/adafruit_qt_py_esp32s3_procpu_psram.overlay new file mode 100644 index 00000000000..5ab0be63c3f --- /dev/null +++ b/boards/adafruit/qt_py_esp32s3/adafruit_qt_py_esp32s3_procpu_psram.overlay @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2024 Ian Wakely + */ + +/delete-node/ &flash0; + +/ { + model = "Adafruit QT Py ESP32S3 PSRAM PROCPU"; + + soc { + flash: flash-controller@60002000 { + compatible = "espressif,esp32-flash-controller"; + reg = <0x60002000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + /* 4MB flash */ + flash0: flash@0 { + compatible = "soc-nv-flash"; + erase-block-size = <4096>; + write-block-size = <4>; + reg = <0x0 DT_SIZE_M(4)>; + }; + }; + }; +}; + +/* 2MB psram */ +&psram0 { + reg = <0x3c000000 DT_SIZE_M(2)>; + status = "okay"; +}; + +#include diff --git a/boards/adafruit/qt_py_esp32s3/adafruit_qt_py_esp32s3_procpu_psram.yaml b/boards/adafruit/qt_py_esp32s3/adafruit_qt_py_esp32s3_procpu_psram.yaml new file mode 100644 index 00000000000..37e6a7f15d6 --- /dev/null +++ b/boards/adafruit/qt_py_esp32s3/adafruit_qt_py_esp32s3_procpu_psram.yaml @@ -0,0 +1,19 @@ +identifier: adafruit_qt_py_esp32s3@psram/esp32s3/procpu +name: Adafruit QT Py ESP32S3 PSRAM PROCPU +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - gpio + - uart + - i2c + - i2s + - spi + - can + - counter + - watchdog + - entropy + - pwm + - dma +vendor: adafruit diff --git a/boards/adafruit/qt_py_esp32s3/board.cmake b/boards/adafruit/qt_py_esp32s3/board.cmake new file mode 100644 index 00000000000..2f04d1fe886 --- /dev/null +++ b/boards/adafruit/qt_py_esp32s3/board.cmake @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +if(NOT "${OPENOCD}" MATCHES "^${ESPRESSIF_TOOLCHAIN_PATH}/.*") + set(OPENOCD OPENOCD-NOTFOUND) +endif() +find_program(OPENOCD openocd PATHS ${ESPRESSIF_TOOLCHAIN_PATH}/openocd-esp32/bin NO_DEFAULT_PATH) + +include(${ZEPHYR_BASE}/boards/common/esp32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/adafruit/qt_py_esp32s3/board.yml b/boards/adafruit/qt_py_esp32s3/board.yml new file mode 100644 index 00000000000..c9b26924f8c --- /dev/null +++ b/boards/adafruit/qt_py_esp32s3/board.yml @@ -0,0 +1,12 @@ +board: + name: adafruit_qt_py_esp32s3 + full_name: QT Py ESP32-S3 + vendor: adafruit + socs: + - name: esp32s3 + revision: + format: "custom" + default: "" + revisions: + - name: "" + - name: "psram" diff --git a/boards/adafruit/qt_py_esp32s3/doc/img/adafruit_qt_py_esp32s3.webp b/boards/adafruit/qt_py_esp32s3/doc/img/adafruit_qt_py_esp32s3.webp new file mode 100644 index 00000000000..43637d31a6f Binary files /dev/null and b/boards/adafruit/qt_py_esp32s3/doc/img/adafruit_qt_py_esp32s3.webp differ diff --git a/boards/adafruit/qt_py_esp32s3/doc/index.rst b/boards/adafruit/qt_py_esp32s3/doc/index.rst new file mode 100644 index 00000000000..1c1f6e04eee --- /dev/null +++ b/boards/adafruit/qt_py_esp32s3/doc/index.rst @@ -0,0 +1,291 @@ +.. zephyr:board:: adafruit_qt_py_esp32s3 + +Overview +******** + +An Adafruit based Xiao compatible board based on the ESP32-S3, which is great +for IoT projects and prototyping with new sensors. + +For more details see the `Adafruit QT Py ESP32S3`_ product page. + +Hardware +******** + +This board comes in 2 variants, both based on the ESP32-S3 with WiFi and BLE +support. The default variant supporting 8MB of flash with no PSRAM, while the +``psram`` variant supporting 4MB of flash with 2MB of PSRAM. Both boards have a +USB-C port for programming and debugging and is based on a standard XIAO 14 +pin pinout. + +In addition to the Xiao compatible pinout, it also has a RGB NeoPixel for +status and debugging, a reset button, and a button for entering the ROM +bootloader or user input. Like many other Adafruit boards, it has a +`SparkFun Qwiic`_-compatible `STEMMA QT`_ connector for the I2C bus so you +don't even need to solder. + +ESP32-S3 is a low-power MCU-based system on a chip (SoC) with integrated +2.4 GHz Wi-Fi and Bluetooth® Low Energy (Bluetooth LE). It consists of +high-performance dual-core microprocessor (Xtensa® 32-bit LX7), a low power +coprocessor, a Wi-Fi baseband, a Bluetooth LE baseband, RF module, and +numerous peripherals. + +Supported Features +================== + +Current Zephyr's Adafruit QT Py ESP32-S3 board supports the following features: + ++------------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++============+============+=====================================+ +| UART | on-chip | serial port | ++------------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++------------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++------------+------------+-------------------------------------+ +| USB-JTAG | on-chip | hardware interface | ++------------+------------+-------------------------------------+ +| SPI Master | on-chip | spi | ++------------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++------------+------------+-------------------------------------+ +| I2S | on-chip | i2s | ++------------+------------+-------------------------------------+ +| TWAI/CAN | on-chip | can | ++------------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++------------+------------+-------------------------------------+ +| Timers | on-chip | counter | ++------------+------------+-------------------------------------+ +| Watchdog | on-chip | watchdog | ++------------+------------+-------------------------------------+ +| TRNG | on-chip | entropy | ++------------+------------+-------------------------------------+ +| LEDC | on-chip | pwm | ++------------+------------+-------------------------------------+ +| MCPWM | on-chip | pwm | ++------------+------------+-------------------------------------+ +| PCNT | on-chip | qdec | ++------------+------------+-------------------------------------+ +| GDMA | on-chip | dma | ++------------+------------+-------------------------------------+ +| Wi-Fi | on-chip | | ++------------+------------+-------------------------------------+ +| Bluetooth | on-chip | | ++------------+------------+-------------------------------------+ + +Prerequisites +------------- + +Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the +command below to retrieve those files. + +.. code-block:: console + + west blobs fetch hal_espressif + +.. note:: + + It is recommended running the command above after :file:`west update`. + +Building & Flashing +******************* + +Simple boot +=========== + +The board could be loaded using the single binary image, without 2nd stage +bootloader. It is the default option when building the application without +additional configuration. + +.. note:: + + Simple boot does not provide any security features nor OTA updates. + +MCUboot bootloader +================== + +User may choose to use MCUboot bootloader instead. In that case the bootloader +must be built (and flashed) at least once. + +There are two options to be used when building an application: + +1. Sysbuild +2. Manual build + +.. note:: + + User can select the MCUboot bootloader by adding the following line + to the board default configuration file. + + .. code:: cfg + + CONFIG_BOOTLOADER_MCUBOOT=y + +Sysbuild +======== + +The sysbuild makes possible to build and flash all necessary images needed to +bootstrap the board with the ESP32 SoC. + +To build the sample application using sysbuild use the command: + +.. zephyr-app-commands:: + :tool: west + :zephyr-app: samples/hello_world + :board: adafruit_qt_py_esp32s3 + :goals: build + :west-args: --sysbuild + :compact: + +By default, the ESP32 sysbuild creates bootloader (MCUboot) and application +images. But it can be configured to create other kind of images. + +Build directory structure created by sysbuild is different from traditional +Zephyr build. Output is structured by the domain subdirectories: + +.. code-block:: + + build/ + ├── hello_world + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + ├── mcuboot + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + └── domains.yaml + +.. note:: + + With ``--sysbuild`` option the bootloader will be re-build and re-flash + every time the pristine build is used. + +For more information about the system build please read the :ref:`sysbuild` documentation. + +Manual build +============ + +During the development cycle, it is intended to build & flash as quickly possible. +For that reason, images can be built one at a time using traditional build. + +The instructions following are relevant for both manual build and sysbuild. +The only difference is the structure of the build directory. + +.. note:: + + Remember that bootloader (MCUboot) needs to be flash at least once. + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +.. tabs:: + + .. group-tab:: QT Py ESP32S3 + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: adafruit_qt_py_esp32s3/esp32s3/procpu + :goals: build + + .. group-tab:: QT Py ESP32S3 with PSRAM + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: adafruit_qt_py_esp32s3@psram/esp32s3/procpu + :goals: build + +The usual ``flash`` target will work with the ``adafruit_qt_py_esp32s3`` board +configuration. Here is an example for the :zephyr:code-sample:`hello_world` +application. + +.. tabs:: + + .. group-tab:: QT Py ESP32S3 + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: adafruit_qt_py_esp32s3/esp32s3/procpu + :goals: flash + + .. group-tab:: QT Py ESP32S3 with PSRAM + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: adafruit_qt_py_esp32s3@psram/esp32s3/procpu + :goals: flash + +Open the serial monitor using the following command: + +.. code-block:: shell + + west espressif monitor + +After the board has automatically reset and booted, you should see the following +message in the monitor: + +.. code-block:: console + + ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** + Hello World! adafruit_qt_py_esp32s3/esp32s3/procpu + +Debugging +********* + +ESP32-S3 support on OpenOCD is available at `OpenOCD ESP32`_. + +ESP32-S3 has a built-in JTAG circuitry and can be debugged without any +additional chip. Only an USB cable connected to the D+/D- pins is necessary. + +Further documentation can be obtained from the SoC vendor +in `JTAG debugging for ESP32-S3`_. + +Here is an example for building the :zephyr:code-sample:`hello_world` application. + +.. tabs:: + + .. group-tab:: QT Py ESP32S3 + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: adafruit_qt_py_esp32s3/esp32s3/procpu + :goals: debug + + .. group-tab:: QT Py ESP32S3 with PSRAM + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: adafruit_qt_py_esp32s3@psram/esp32s3/procpu + :goals: debug + +You can debug an application in the usual way. Here is an example for +the :zephyr:code-sample:`hello_world` application. + +.. tabs:: + + .. group-tab:: QT Py ESP32S3 + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: adafruit_qt_py_esp32s3/esp32s3/procpu + :goals: debug + + .. group-tab:: QT Py ESP32S3 with PSRAM + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: adafruit_qt_py_esp32s3@psram/esp32s3/procpu + :goals: debug + +References +********** + +.. target-notes:: + +.. _`Adafruit QT Py ESP32S3`: https://www.adafruit.com/product/5426 +.. _`Adafruit QT Py ESP32S3 - PSRAM`: https://www.adafruit.com/product/5700 +.. _`JTAG debugging for ESP32-S3`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32s3/api-guides/jtag-debugging/ +.. _`OpenOCD ESP32`: https://github.com/espressif/openocd-esp32/releases +.. _`SparkFun Qwiic`: https://www.sparkfun.com/qwiic +.. _`STEMMA QT`: https://learn.adafruit.com/introducing-adafruit-stemma-qt diff --git a/boards/adafruit/qt_py_esp32s3/revision.cmake b/boards/adafruit/qt_py_esp32s3/revision.cmake new file mode 100644 index 00000000000..26aeb65f775 --- /dev/null +++ b/boards/adafruit/qt_py_esp32s3/revision.cmake @@ -0,0 +1,3 @@ +if(DEFINED BOARD_REVISION AND NOT BOARD_REVISION STREQUAL "psram") + message(FATAL_ERROR "Invalid board revision, ${BOARD_REVISION}, valid revisions are: (for non-PSRAM version), psram") +endif() diff --git a/boards/adafruit/qt_py_esp32s3/seeed_xiao_connector.dtsi b/boards/adafruit/qt_py_esp32s3/seeed_xiao_connector.dtsi new file mode 100644 index 00000000000..39880f7c942 --- /dev/null +++ b/boards/adafruit/qt_py_esp32s3/seeed_xiao_connector.dtsi @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2024 Ian Wakely + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + xiao_d: connector { + compatible = "seeed,xiao-gpio"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpio0 18 0>, /* D0 */ + <1 0 &gpio0 17 0>, /* D1 */ + <2 0 &gpio0 9 0>, /* D2 */ + <3 0 &gpio0 8 0>, /* D3 */ + <4 0 &gpio0 7 0>, /* D4 */ + <5 0 &gpio0 6 0>, /* D5 */ + <6 0 &gpio0 5 0>, /* D6 */ + <7 0 &gpio0 16 0>, /* D7 */ + <8 0 &gpio1 4 0>, /* D8 */ + <9 0 &gpio1 5 0>, /* D9 */ + <10 0 &gpio1 3 0>; /* D10 */ + }; +}; + +xiao_spi: &spi2 {}; +xiao_i2c: &i2c0 {}; +xiao_serial: &uart0 {}; +xiao_adc: &adc0 {}; diff --git a/boards/adafruit/qt_py_esp32s3/support/openocd.cfg b/boards/adafruit/qt_py_esp32s3/support/openocd.cfg new file mode 100644 index 00000000000..2f740b4a36a --- /dev/null +++ b/boards/adafruit/qt_py_esp32s3/support/openocd.cfg @@ -0,0 +1,7 @@ +set ESP_RTOS none +set ESP32_ONLYCPU 1 + +# Source the JTAG interface configuration file +source [find interface/esp_usb_jtag.cfg] +# Source the ESP32-S3 configuration file +source [find target/esp32s3.cfg] diff --git a/boards/adafruit/qt_py_rp2040/Kconfig b/boards/adafruit/qt_py_rp2040/Kconfig new file mode 100644 index 00000000000..88483e605c8 --- /dev/null +++ b/boards/adafruit/qt_py_rp2040/Kconfig @@ -0,0 +1,5 @@ +# Copyright (c) 2022 Peter Johanson +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ADAFRUIT_QT_PY_RP2040 + select RP2_FLASH_W25Q080 diff --git a/boards/adafruit/qt_py_rp2040/Kconfig.defconfig b/boards/adafruit/qt_py_rp2040/Kconfig.defconfig index 22d40318634..09706fc65fd 100644 --- a/boards/adafruit/qt_py_rp2040/Kconfig.defconfig +++ b/boards/adafruit/qt_py_rp2040/Kconfig.defconfig @@ -3,9 +3,6 @@ if BOARD_ADAFRUIT_QT_PY_RP2040 -config RP2_FLASH_W25Q080 - default y - if I2C_DW config I2C_DW_CLOCK_SPEED diff --git a/boards/adafruit/qt_py_rp2040/adafruit_qt_py_rp2040-pinctrl.dtsi b/boards/adafruit/qt_py_rp2040/adafruit_qt_py_rp2040-pinctrl.dtsi index d2e84ae41f8..561db005e65 100644 --- a/boards/adafruit/qt_py_rp2040/adafruit_qt_py_rp2040-pinctrl.dtsi +++ b/boards/adafruit/qt_py_rp2040/adafruit_qt_py_rp2040-pinctrl.dtsi @@ -59,9 +59,6 @@ }; }; - clocks_default: clocks_default { - }; - ws2812_pio1_default: ws2812_pio1_default { ws2812 { pinmux = ; diff --git a/boards/adafruit/qt_py_rp2040/adafruit_qt_py_rp2040.dts b/boards/adafruit/qt_py_rp2040/adafruit_qt_py_rp2040.dts index 0209c1b86cd..3f87e4188b2 100644 --- a/boards/adafruit/qt_py_rp2040/adafruit_qt_py_rp2040.dts +++ b/boards/adafruit/qt_py_rp2040/adafruit_qt_py_rp2040.dts @@ -7,7 +7,7 @@ /dts-v1/; -#include +#include #include "adafruit_qt_py_rp2040-pinctrl.dtsi" #include "seeed_xiao_connector.dtsi" #include @@ -56,11 +56,6 @@ }; }; -&clocks { - pinctrl-0 = <&clocks_default>; - pinctrl-names = "default"; -}; - &uart1 { current-speed = <115200>; status = "okay"; @@ -157,3 +152,7 @@ zephyr_udc0: &usbd { regulator-always-on; regulator-allowed-modes = ; }; + +&xosc { + startup-delay-multiplier = <64>; +}; diff --git a/boards/adafruit/qt_py_rp2040/doc/index.rst b/boards/adafruit/qt_py_rp2040/doc/index.rst index bf081c029b7..0db8b4e4034 100644 --- a/boards/adafruit/qt_py_rp2040/doc/index.rst +++ b/boards/adafruit/qt_py_rp2040/doc/index.rst @@ -1,7 +1,4 @@ -.. _adafruit_qt_py_rp2040: - -Adafruit QT Py RP2040 -##################### +.. zephyr:board:: adafruit_qt_py_rp2040 Overview ******** @@ -27,13 +24,6 @@ Hardware - On-board RGB LED - 1 Watchdog timer peripheral - -.. figure:: img/qtpy_rp2040.jpg - :align: center - :alt: Adafruit QT Py RP2040 - - Adafruit QT Py RP2040 (Image courtesy of Adafruit) - Supported Features ================== diff --git a/boards/adafruit/trinket_m0/doc/index.rst b/boards/adafruit/trinket_m0/doc/index.rst index 4714f9d1aff..224f9aa4c6d 100644 --- a/boards/adafruit/trinket_m0/doc/index.rst +++ b/boards/adafruit/trinket_m0/doc/index.rst @@ -1,7 +1,4 @@ -.. _adafruit_trinket_m0: - -Adafruit Trinket M0 -################### +.. zephyr:board:: adafruit_trinket_m0 Overview ******** @@ -10,10 +7,6 @@ The Adafruit Trinket M0 is a tiny (27 mm x 15 mm) ARM development board with an onboard RGB LED, USB port, and range of I/O broken out onto 5 pins. -.. image:: img/adafruit_trinket_m0.jpg - :align: center - :alt: Adafruit Trinket M0 - Hardware ******** diff --git a/boards/adi/apard32690/apard32690_max32690_m4.dts b/boards/adi/apard32690/apard32690_max32690_m4.dts index 793a717442b..4de11b92848 100644 --- a/boards/adi/apard32690/apard32690_max32690_m4.dts +++ b/boards/adi/apard32690/apard32690_max32690_m4.dts @@ -53,6 +53,35 @@ led2 = &green_led; sw0 = &usr_btn; }; + + arduino_header: connector { + compatible = "arduino-header-r3"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpio3 0 0>, /* A0 */ + <1 0 &gpio3 1 0>, /* A1 */ + <2 0 &gpio3 2 0>, /* A2 */ + <3 0 &gpio3 3 0>, /* A3 */ + <4 0 &gpio3 4 0>, /* A4 */ + <5 0 &gpio3 5 0>, /* A5 */ + <6 0 &gpio2 14 0>, /* D0 */ + <7 0 &gpio2 16 0>, /* D1 */ + <8 0 &gpio2 13 0>, /* D2 */ + <9 0 &gpio2 15 0>, /* D3 */ + <10 0 &gpio0 8 0>, /* D4 */ + <11 0 &gpio0 7 0>, /* D5 */ + <12 0 &gpio1 24 0>, /* D6 */ + <13 0 &gpio1 25 0>, /* D7 */ + <14 0 &gpio1 31 0>, /* D8 */ + <15 0 &gpio1 30 0>, /* D9 */ + <16 0 &gpio1 23 0>, /* D10 */ + <17 0 &gpio1 29 0>, /* D11 */ + <18 0 &gpio1 28 0>, /* D12 */ + <19 0 &gpio1 26 0>, /* D13 */ + <20 0 &gpio2 17 0>, /* D14 */ + <21 0 &gpio2 18 0>; /* D15 */ + }; }; &clk_ipo { @@ -104,6 +133,22 @@ arduino_serial: &uart1 { current-speed = <115200>; }; +&spi1a_miso_p1_28 { + power-source = ; +}; + +&spi1a_mosi_p1_29 { + power-source = ; +}; + +&spi1a_sck_p1_26 { + power-source = ; +}; + +&spi1a_ss0_p1_23 { + power-source = ; +}; + arduino_spi: &spi1 { pinctrl-0 = <&spi1a_miso_p1_28 &spi1a_mosi_p1_29 &spi1a_sck_p1_26 &spi1a_ss0_p1_23>; @@ -177,3 +222,8 @@ pmod_spi: &spi4 { }; }; }; + +&w1 { + pinctrl-0 = <&owm_io_p0_8 &owm_pe_p0_7>; + pinctrl-names = "default"; +}; diff --git a/boards/adi/apard32690/apard32690_max32690_m4.yaml b/boards/adi/apard32690/apard32690_max32690_m4.yaml index f3f842b66b2..bc040f86855 100644 --- a/boards/adi/apard32690/apard32690_max32690_m4.yaml +++ b/boards/adi/apard32690/apard32690_max32690_m4.yaml @@ -8,6 +8,7 @@ toolchain: - gnuarmemb - xtools supported: + - arduino_gpio - arduino_serial - arduino_spi - pmod_spi @@ -16,5 +17,6 @@ supported: - spi - trng - counter + - w1 ram: 1024 flash: 3072 diff --git a/boards/adi/apard32690/doc/index.rst b/boards/adi/apard32690/doc/index.rst index 192f0bba814..8223f2b88e9 100644 --- a/boards/adi/apard32690/doc/index.rst +++ b/boards/adi/apard32690/doc/index.rst @@ -1,7 +1,4 @@ -.. _ad_apard32690_sl: - -AD-APARD32690-SL -################ +.. zephyr:board:: apard32690 Overview ******** @@ -19,10 +16,6 @@ the required power circuitry. The Zephyr port is running on the MAX32690 MCU. -.. image:: img/apard32690_img.webp - :align: center - :alt: AD-APARD32690-SL Front - Hardware ******** @@ -117,6 +110,8 @@ Below interfaces are supported by Zephyr on APARD32690. +-----------+------------+------------------------------------+ | Timer | on-chip | counter | +-----------+------------+------------------------------------+ +| W1 | on-chip | one wire master | ++-----------+------------+------------------------------------+ Connections and IOs diff --git a/boards/adi/eval_adin1110ebz/doc/index.rst b/boards/adi/eval_adin1110ebz/doc/index.rst index f39a04b7362..4f38e78faf0 100644 --- a/boards/adi/eval_adin1110ebz/doc/index.rst +++ b/boards/adi/eval_adin1110ebz/doc/index.rst @@ -1,7 +1,4 @@ -.. _adi_eval_adin1110ebz: - -ADI EVAL-ADIN1110EVB Evaluation board -##################################### +.. zephyr:board:: adi_eval_adin1110ebz Overview ******** @@ -23,12 +20,6 @@ The SPI interface provides configuration and data access to the ADIN1110. A small prototyping area and test points are provided for experimentation with alternative cable connection topologies including isolation transformers and/or power coupling inductors. -.. figure:: img/adi_eval_adin1110ebz.webp - :align: center - :alt: ADI EVAL-ADIN1110EBZ - - ADI EVAL-ADIN1110EBZ (Credit: Analog Devices, Inc.) - .. important:: S201 DIP switches are shipped in Open Alliance SPI mode. The current Zephyr diff --git a/boards/adi/eval_adin2111ebz/doc/index.rst b/boards/adi/eval_adin2111ebz/doc/index.rst index ea0ce92be2a..7579c85b0cd 100644 --- a/boards/adi/eval_adin2111ebz/doc/index.rst +++ b/boards/adi/eval_adin2111ebz/doc/index.rst @@ -1,7 +1,4 @@ -.. _adi_eval_adin2111ebz: - -ADI EVAL-ADIN2111EVB Evaluation board -##################################### +.. zephyr:board:: adi_eval_adin2111ebz Overview ******** @@ -38,12 +35,6 @@ the 2 PHYs configuration and data exchange between SPI host and ports. so the S1 DIP switches must be set as ``SPI_CFG0 OFF and SPI_CFG1 OFF``. An inconsistent S1 DIP switches configuration will halt the boot. -.. figure:: img/adi_eval_adin2111ebz.webp - :align: center - :alt: ADI EVAL-ADIN2111EBZ - - ADI EVAL-ADIN2111EBZ (Credit: Analog Devices, Inc.) - Hardware ******** diff --git a/boards/adi/max32655evkit/doc/index.rst b/boards/adi/max32655evkit/doc/index.rst index d052dba938a..649df3bde37 100644 --- a/boards/adi/max32655evkit/doc/index.rst +++ b/boards/adi/max32655evkit/doc/index.rst @@ -1,7 +1,4 @@ -.. _max32655_evkit: - -MAX32655EVKIT -############# +.. zephyr:board:: max32655evkit Overview ******** @@ -101,6 +98,12 @@ Below are the interfaces supported by Zephyr on MAX32655EVKIT. +-----------+------------+-------------------------------------+ | Timer | on-chip | counter | +-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| W1 | on-chip | one wire master | ++-----------+------------+-------------------------------------+ +| Flash | on-chip | flash | ++-----------+------------+-------------------------------------+ Connections and IOs =================== diff --git a/boards/adi/max32655evkit/max32655evkit_max32655_m4.dts b/boards/adi/max32655evkit/max32655evkit_max32655_m4.dts index eea6c9e6ab4..a14953606ea 100644 --- a/boards/adi/max32655evkit/max32655evkit_max32655_m4.dts +++ b/boards/adi/max32655evkit/max32655evkit_max32655_m4.dts @@ -78,6 +78,13 @@ status = "okay"; }; +/* + * ERTCO is required for counter RTC + */ +&clk_ertco { + status = "okay"; +}; + &gpio0 { status = "okay"; }; @@ -117,3 +124,12 @@ pinctrl-0 = <&spi0_mosi_p0_5 &spi0_miso_p0_6 &spi0_sck_p0_7 &spi0_ss0_p0_4>; pinctrl-names = "default"; }; + +&w1 { + pinctrl-0 = <&owm_io_p0_6 &owm_pe_p0_7>; + pinctrl-names = "default"; +}; + +&rtc_counter { + status = "okay"; +}; diff --git a/boards/adi/max32655evkit/max32655evkit_max32655_m4.yaml b/boards/adi/max32655evkit/max32655evkit_max32655_m4.yaml index 0a870489a22..f3a7fac43ba 100644 --- a/boards/adi/max32655evkit/max32655evkit_max32655_m4.yaml +++ b/boards/adi/max32655evkit/max32655evkit_max32655_m4.yaml @@ -17,5 +17,9 @@ supported: - spi - adc - counter + - rtc_counter + - pwm + - w1 + - flash ram: 128 flash: 512 diff --git a/boards/adi/max32655fthr/doc/index.rst b/boards/adi/max32655fthr/doc/index.rst index 3c9efcfb675..839365066cc 100644 --- a/boards/adi/max32655fthr/doc/index.rst +++ b/boards/adi/max32655fthr/doc/index.rst @@ -1,7 +1,4 @@ -.. _max32655_fthr: - -MAX32655FTHR -############ +.. zephyr:board:: max32655fthr Overview ******** @@ -114,6 +111,10 @@ Below are the interfaces supported by Zephyr on MAX32655FTHR. +-----------+------------+-------------------------------------+ | Timer | on-chip | counter | +-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| Flash | on-chip | flash | ++-----------+------------+-------------------------------------+ Push Buttons ************ diff --git a/boards/adi/max32655fthr/max32655fthr_max32655_m4.dts b/boards/adi/max32655fthr/max32655fthr_max32655_m4.dts index f5df5e5260a..2f82dc09022 100644 --- a/boards/adi/max32655fthr/max32655fthr_max32655_m4.dts +++ b/boards/adi/max32655fthr/max32655fthr_max32655_m4.dts @@ -112,6 +112,13 @@ status = "okay"; }; +/* + * ERTCO is required for counter RTC + */ +&clk_ertco { + status = "okay"; +}; + &gpio0 { status = "okay"; }; @@ -151,3 +158,7 @@ pinctrl-0 = <&spi1_mosi_p0_21 &spi1_miso_p0_22 &spi1_sck_p0_23 &spi1_ss0_p0_20>; pinctrl-names = "default"; }; + +&rtc_counter { + status = "okay"; +}; diff --git a/boards/adi/max32655fthr/max32655fthr_max32655_m4.yaml b/boards/adi/max32655fthr/max32655fthr_max32655_m4.yaml index e361e18e24f..37c8b01e02e 100644 --- a/boards/adi/max32655fthr/max32655fthr_max32655_m4.yaml +++ b/boards/adi/max32655fthr/max32655fthr_max32655_m4.yaml @@ -17,5 +17,8 @@ supported: - spi - adc - counter + - rtc_counter + - pwm + - flash ram: 128 flash: 512 diff --git a/boards/adi/max32662evkit/Kconfig.defconfig b/boards/adi/max32662evkit/Kconfig.defconfig new file mode 100644 index 00000000000..415360cc1eb --- /dev/null +++ b/boards/adi/max32662evkit/Kconfig.defconfig @@ -0,0 +1,29 @@ +# MAX32662EVKIT boards configuration + +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_MAX32662EVKIT + +if DISPLAY + +config MIPI_DBI_SPI_3WIRE + default y + +if LVGL + +config LV_Z_BITS_PER_PIXEL + default 16 + +choice LV_COLOR_DEPTH + default LV_COLOR_DEPTH_16 # 16 bit per pixel +endchoice + +configdefault LV_COLOR_16_SWAP + default y + +endif # LVGL + +endif # DISPLAY + +endif # BOARD_MAX32662EVKIT diff --git a/boards/adi/max32662evkit/doc/index.rst b/boards/adi/max32662evkit/doc/index.rst index 64718015706..b343fb6ed99 100644 --- a/boards/adi/max32662evkit/doc/index.rst +++ b/boards/adi/max32662evkit/doc/index.rst @@ -1,7 +1,4 @@ -.. _max32662_evkit: - -MAX32662EVKIT -############# +.. zephyr:board:: max32662evkit Overview ******** @@ -12,10 +9,6 @@ for battery-powered edge devices. The Zephyr port is running on the MAX32662 MCU. -.. image:: img/max32662evkit.webp - :align: center - :alt: MAX32662EVKIT - Hardware ******** @@ -111,6 +104,10 @@ Below interfaces are supported by Zephyr on MAX32662EVKIT. +-----------+------------+-------------------------------------+ | Timer | on-chip | counter | +-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| Flash | on-chip | flash | ++-----------+------------+-------------------------------------+ Connections and IOs =================== diff --git a/boards/adi/max32662evkit/max32662evkit.dts b/boards/adi/max32662evkit/max32662evkit.dts index e458a8d6904..5f204b91bef 100644 --- a/boards/adi/max32662evkit/max32662evkit.dts +++ b/boards/adi/max32662evkit/max32662evkit.dts @@ -11,6 +11,7 @@ #include #include #include +#include / { model = "Analog Devices MAX32662EVKIT"; @@ -21,6 +22,7 @@ zephyr,shell-uart = &uart0; zephyr,sram = &sram2; zephyr,flash = &flash0; + zephyr,display = &st7735; }; leds { @@ -47,6 +49,40 @@ sw0 = &pb1; watchdog0 = &wdt0; }; + + mipi_dbi { + compatible = "zephyr,mipi-dbi-spi"; + spi-dev = <&spi1>; + #address-cells = <1>; + #size-cells = <0>; + + status = "okay"; + + st7735: st7735@0 { + compatible = "sitronix,st7735r"; + mipi-max-frequency = ; + mipi-mode = "MIPI_DBI_MODE_SPI_3WIRE"; + + reg = <0>; + width = <130>; + height = <132>; + x-offset = <0>; + y-offset = <0>; + madctl = <0xc0>; + colmod = <0x05>; + vmctr1 = <0x51>; + pwctr1 = [02 02]; + pwctr2 = [c5]; + pwctr3 = [0d 00]; + pwctr4 = [8d 1a]; + pwctr5 = [8d ee]; + frmctr1 = [02 35 36]; + frmctr2 = [02 35 36]; + frmctr3 = [02 35 36 02 35 36]; + gamctrp1 = [0a 1c 0c 14 33 2b 24 28 27 25 2c 39 00 05 03 0d]; + gamctrn1 = [0a 1c 0c 14 33 2b 24 28 27 25 2d 3a 00 05 03 0d]; + }; + }; }; &uart0 { @@ -66,6 +102,13 @@ status = "okay"; }; +/* + * ERTCO is required for counter RTC + */ +&clk_ertco { + status = "okay"; +}; + &gpio0 { status = "okay"; }; @@ -84,8 +127,27 @@ status = "okay"; }; +&rtc_counter { + status = "okay"; +}; + &spi0 { status = "okay"; pinctrl-0 = <&spi0a_copi_p0_3 &spi0a_cito_p0_2 &spi0a_sck_p0_4 &spi0a_ts0_p0_5>; pinctrl-names = "default"; }; + +&spi1a_mosi_p0_8 { + power-source=; +}; + +&spi1a_sck_p0_17 { + power-source=; +}; + +&spi1 { + status = "okay"; + pinctrl-0 = <&spi1a_mosi_p0_8 &spi1a_sck_p0_17>; + pinctrl-names = "default"; + cs-gpios = <&gpio0 18 (GPIO_ACTIVE_LOW | MAX32_VSEL_VDDIOH)>; +}; diff --git a/boards/adi/max32662evkit/max32662evkit.yaml b/boards/adi/max32662evkit/max32662evkit.yaml index f4577c7bcab..eebab96b676 100644 --- a/boards/adi/max32662evkit/max32662evkit.yaml +++ b/boards/adi/max32662evkit/max32662evkit.yaml @@ -17,5 +17,8 @@ supported: - spi - adc - counter + - rtc_counter + - pwm + - flash ram: 80 flash: 256 diff --git a/boards/adi/max32666evkit/doc/index.rst b/boards/adi/max32666evkit/doc/index.rst index 528a8026ca1..f71b1a69bb6 100644 --- a/boards/adi/max32666evkit/doc/index.rst +++ b/boards/adi/max32666evkit/doc/index.rst @@ -1,21 +1,12 @@ -.. _max32666evkit: - -MAX32666EVKIT -############# +.. zephyr:board:: max32666evkit Overview ******** The MAX32666EVKIT provides a platform for evaluating the capabilities of the MAX32665 and MAX32666 high-efficiency Arm® microcontrollers and audio DSP for wearable and hearable device applications. - The Zephyr port is running on the MAX32666 MCU. -.. image:: img/max32666evkit.webp - :align: center - :alt: MAX32666EVKIT Front - - Hardware ******** @@ -122,6 +113,12 @@ Below interfaces are supported by Zephyr on MAX32666EVKIT. +-----------+------------+-------------------------------------+ | Timer | on-chip | counter | +-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| W1 | on-chip | one wire master | ++-----------+------------+-------------------------------------+ +| Flash | on-chip | flash | ++-----------+------------+-------------------------------------+ Connections and IOs diff --git a/boards/adi/max32666evkit/max32666evkit_max32666_cpu0.dts b/boards/adi/max32666evkit/max32666evkit_max32666_cpu0.dts index a87658da4e8..a04fcd6a4e8 100644 --- a/boards/adi/max32666evkit/max32666evkit_max32666_cpu0.dts +++ b/boards/adi/max32666evkit/max32666evkit_max32666_cpu0.dts @@ -105,3 +105,12 @@ &wdt0 { status = "okay"; }; + +&w1 { + pinctrl-0 = <&owm_io_p0_4 &owm_pe_p0_5>; + pinctrl-names = "default"; +}; + +&rtc_counter { + status = "okay"; +}; diff --git a/boards/adi/max32666evkit/max32666evkit_max32666_cpu0.yaml b/boards/adi/max32666evkit/max32666evkit_max32666_cpu0.yaml index 45320dd7307..7d5f8699970 100644 --- a/boards/adi/max32666evkit/max32666evkit_max32666_cpu0.yaml +++ b/boards/adi/max32666evkit/max32666evkit_max32666_cpu0.yaml @@ -16,5 +16,9 @@ supported: - watchdog - adc - counter + - rtc_counter + - pwm + - w1 + - flash ram: 560 flash: 1024 diff --git a/boards/adi/max32666fthr/doc/index.rst b/boards/adi/max32666fthr/doc/index.rst index df762d373f5..1cd8a999de1 100644 --- a/boards/adi/max32666fthr/doc/index.rst +++ b/boards/adi/max32666fthr/doc/index.rst @@ -1,7 +1,4 @@ -.. _max32666_fthr: - -MAX32666FTHR -############ +.. zephyr:board:: max32666fthr Overview ******** @@ -21,7 +18,7 @@ The Zephyr port is running on the MAX32666 MCU. :align: center :alt: MAX32666FTHR Front -.. image:: img/max32666fthr_img1.jpg +.. image:: img/max32666fthr_img2.jpg :align: center :alt: MAX32666FTHR Back @@ -123,6 +120,12 @@ Below interfaces are supported by Zephyr on MAX32666FTHR. +-----------+------------+-------------------------------------+ | Timer | on-chip | counter | +-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| W1 | on-chip | one wire master | ++-----------+------------+-------------------------------------+ +| Flash | on-chip | flash | ++-----------+------------+-------------------------------------+ Connections and IOs =================== diff --git a/boards/adi/max32666fthr/max32666fthr_max32666_cpu0.dts b/boards/adi/max32666fthr/max32666fthr_max32666_cpu0.dts index 95597c47266..02b45bda3db 100644 --- a/boards/adi/max32666fthr/max32666fthr_max32666_cpu0.dts +++ b/boards/adi/max32666fthr/max32666fthr_max32666_cpu0.dts @@ -120,8 +120,17 @@ status = "okay"; }; +&rtc_counter { + status = "okay"; +}; + &spi1 { status = "okay"; pinctrl-0 = <&spi1_mosi_p0_17 &spi1_miso_p0_18 &spi1_sck_p0_19 &spi1_ss0_p0_16>; pinctrl-names = "default"; }; + +&w1 { + pinctrl-0 = <&owm_io_p0_12>; + pinctrl-names = "default"; +}; diff --git a/boards/adi/max32666fthr/max32666fthr_max32666_cpu0.yaml b/boards/adi/max32666fthr/max32666fthr_max32666_cpu0.yaml index f70a32e68cf..c40294e0ae3 100644 --- a/boards/adi/max32666fthr/max32666fthr_max32666_cpu0.yaml +++ b/boards/adi/max32666fthr/max32666fthr_max32666_cpu0.yaml @@ -17,5 +17,9 @@ supported: - spi - adc - counter + - rtc_counter + - pwm + - w1 + - flash ram: 560 flash: 1024 diff --git a/boards/adi/max32670evkit/doc/index.rst b/boards/adi/max32670evkit/doc/index.rst index 3a03283975e..a5b10ef8d9e 100644 --- a/boards/adi/max32670evkit/doc/index.rst +++ b/boards/adi/max32670evkit/doc/index.rst @@ -1,7 +1,4 @@ -.. _max32670_evkit: - -MAX32670EVKIT -############# +.. zephyr:board:: max32670evkit Overview ******** @@ -15,10 +12,6 @@ from 8-bit or 16-bit microcontrollers. The Zephyr port is running on the MAX32670 MCU. -.. image:: img/max32670evkit.webp - :align: center - :alt: MAX32670 EVKIT - Hardware ******** @@ -118,6 +111,10 @@ Below interfaces are supported by Zephyr on MAX32670EVKIT. +-----------+------------+-------------------------------------+ | Timer | on-chip | counter | +-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| Flash | on-chip | flash | ++-----------+------------+-------------------------------------+ Connections and IOs =================== diff --git a/boards/adi/max32670evkit/max32670evkit.dts b/boards/adi/max32670evkit/max32670evkit.dts index 98c6076374b..ed8a3f47601 100644 --- a/boards/adi/max32670evkit/max32670evkit.dts +++ b/boards/adi/max32670evkit/max32670evkit.dts @@ -65,6 +65,13 @@ status = "okay"; }; +/* + * ERTCO is required for counter RTC + */ +&clk_ertco { + status = "okay"; +}; + &gpio0 { status = "okay"; }; @@ -96,3 +103,7 @@ pinctrl-0 = <&spi0_mosi_p0_3 &spi0_miso_p0_2 &spi0_sck_p0_4 &spi0_ss0_p0_5>; pinctrl-names = "default"; }; + +&rtc_counter { + status = "okay"; +}; diff --git a/boards/adi/max32670evkit/max32670evkit.yaml b/boards/adi/max32670evkit/max32670evkit.yaml index f4550186628..d040a09de49 100644 --- a/boards/adi/max32670evkit/max32670evkit.yaml +++ b/boards/adi/max32670evkit/max32670evkit.yaml @@ -16,5 +16,8 @@ supported: - watchdog - spi - counter + - rtc_counter + - pwm + - flash ram: 160 flash: 384 diff --git a/boards/adi/max32672evkit/Kconfig.defconfig b/boards/adi/max32672evkit/Kconfig.defconfig index cb74c0282e7..28ba2e3b964 100644 --- a/boards/adi/max32672evkit/Kconfig.defconfig +++ b/boards/adi/max32672evkit/Kconfig.defconfig @@ -19,7 +19,7 @@ choice LV_COLOR_DEPTH default LV_COLOR_DEPTH_16 # 16 bit per pixel endchoice -config LV_COLOR_16_SWAP +configdefault LV_COLOR_16_SWAP default y endif # LVGL diff --git a/boards/adi/max32672evkit/doc/index.rst b/boards/adi/max32672evkit/doc/index.rst index 2ad07382fc4..c706898a353 100644 --- a/boards/adi/max32672evkit/doc/index.rst +++ b/boards/adi/max32672evkit/doc/index.rst @@ -1,7 +1,4 @@ -.. _max32672_evkit: - -MAX32672EVKIT -############# +.. zephyr:board:: max32672evkit Overview ******** @@ -13,10 +10,6 @@ designs an easy, cost-optimal upgrade path from 8-bit or 16-bit microcontrollers The Zephyr port is running on the MAX32672 MCU. -.. image:: img/max32672evkit.webp - :align: center - :alt: MAX32672EVKIT - Hardware ******** @@ -113,6 +106,10 @@ Below interfaces are supported by Zephyr on MAX32672EVKIT. +-----------+------------+-------------------------------------+ | Timer | on-chip | counter | +-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| Flash | on-chip | flash | ++-----------+------------+-------------------------------------+ Connections and IOs diff --git a/boards/adi/max32672evkit/max32672evkit.dts b/boards/adi/max32672evkit/max32672evkit.dts index d1d97f78af2..581a9723c1d 100644 --- a/boards/adi/max32672evkit/max32672evkit.dts +++ b/boards/adi/max32672evkit/max32672evkit.dts @@ -66,7 +66,7 @@ st7735: st7735@0 { compatible = "sitronix,st7735r"; mipi-max-frequency = ; - mipi-mode = ; + mipi-mode = "MIPI_DBI_MODE_SPI_3WIRE"; reg = <0>; width = <130>; @@ -103,6 +103,13 @@ status = "okay"; }; +/* + * ERTCO is required for counter RTC + */ +&clk_ertco { + status = "okay"; +}; + &gpio0 { status = "okay"; }; @@ -149,3 +156,7 @@ pinctrl-names = "default"; cs-gpios = <&gpio0 5 (GPIO_ACTIVE_LOW | MAX32_VSEL_VDDIOH)>; }; + +&rtc_counter { + status = "okay"; +}; diff --git a/boards/adi/max32672evkit/max32672evkit.yaml b/boards/adi/max32672evkit/max32672evkit.yaml index 276acbe28f8..e6dae70435c 100644 --- a/boards/adi/max32672evkit/max32672evkit.yaml +++ b/boards/adi/max32672evkit/max32672evkit.yaml @@ -17,5 +17,8 @@ supported: - spi - adc - counter + - rtc_counter + - pwm + - flash ram: 200 flash: 1024 diff --git a/boards/adi/max32672fthr/doc/index.rst b/boards/adi/max32672fthr/doc/index.rst index d773c4ceb95..76033bf97ec 100644 --- a/boards/adi/max32672fthr/doc/index.rst +++ b/boards/adi/max32672fthr/doc/index.rst @@ -1,7 +1,4 @@ -.. _max32672_fthr: - -MAX32672FTHR -############ +.. zephyr:board:: max32672fthr Overview ******** @@ -115,6 +112,10 @@ Below interfaces are supported by Zephyr on MAX32672FTHR. +-----------+------------+-------------------------------------+ | Timer | on-chip | counter | +-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| Flash | on-chip | flash | ++-----------+------------+-------------------------------------+ Connections and IOs diff --git a/boards/adi/max32672fthr/max32672fthr.dts b/boards/adi/max32672fthr/max32672fthr.dts index b2287cf7708..7690d03424a 100644 --- a/boards/adi/max32672fthr/max32672fthr.dts +++ b/boards/adi/max32672fthr/max32672fthr.dts @@ -100,6 +100,13 @@ status = "okay"; }; +/* + * ERTCO is required for counter RTC + */ +&clk_ertco { + status = "okay"; +}; + &gpio0 { status = "okay"; }; @@ -148,3 +155,7 @@ pinctrl-0 = <&spi1a_mosi_p0_15 &spi1a_miso_p0_14 &spi1a_sck_p0_16 &spi1a_ss0_p0_17>; pinctrl-names = "default"; }; + +&rtc_counter { + status = "okay"; +}; diff --git a/boards/adi/max32672fthr/max32672fthr.yaml b/boards/adi/max32672fthr/max32672fthr.yaml index 68ba3c8b8a6..f98839246c8 100644 --- a/boards/adi/max32672fthr/max32672fthr.yaml +++ b/boards/adi/max32672fthr/max32672fthr.yaml @@ -17,5 +17,8 @@ supported: - spi - adc - counter + - rtc_counter + - pwm + - flash ram: 200 flash: 1024 diff --git a/boards/adi/max32675evkit/doc/index.rst b/boards/adi/max32675evkit/doc/index.rst index c4cb514d591..a9de574eb21 100644 --- a/boards/adi/max32675evkit/doc/index.rst +++ b/boards/adi/max32675evkit/doc/index.rst @@ -1,7 +1,4 @@ -.. _max32675_evkit: - -MAX32675EVKIT -############# +.. zephyr:board:: max32675evkit Overview ******** @@ -13,10 +10,6 @@ industrial sensors for configuration and diagnostics. The Zephyr port is running on the MAX32675 MCU. -.. image:: img/max32675evkit.webp - :align: center - :alt: MAX32675EVKIT - Hardware ******** @@ -98,6 +91,10 @@ Below interfaces are supported by Zephyr on MAX32675EVKIT. +-----------+------------+-------------------------------------+ | I2C | on-chip | i2c | +-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| Flash | on-chip | flash | ++-----------+------------+-------------------------------------+ Connections and IOs =================== diff --git a/boards/adi/max32675evkit/max32675evkit.yaml b/boards/adi/max32675evkit/max32675evkit.yaml index b16eefcba45..023a35465f3 100644 --- a/boards/adi/max32675evkit/max32675evkit.yaml +++ b/boards/adi/max32675evkit/max32675evkit.yaml @@ -14,5 +14,7 @@ supported: - serial - trng - spi + - pwm + - flash ram: 160 flash: 384 diff --git a/boards/adi/max32680evkit/Kconfig.defconfig b/boards/adi/max32680evkit/Kconfig.defconfig index 99702938eae..33ba842e291 100644 --- a/boards/adi/max32680evkit/Kconfig.defconfig +++ b/boards/adi/max32680evkit/Kconfig.defconfig @@ -19,7 +19,7 @@ choice LV_COLOR_DEPTH default LV_COLOR_DEPTH_16 # 16 bit per pixel endchoice -config LV_COLOR_16_SWAP +configdefault LV_COLOR_16_SWAP default y endif # LVGL diff --git a/boards/adi/max32680evkit/doc/index.rst b/boards/adi/max32680evkit/doc/index.rst index 4663894d58a..13c6d7d06b6 100644 --- a/boards/adi/max32680evkit/doc/index.rst +++ b/boards/adi/max32680evkit/doc/index.rst @@ -1,7 +1,4 @@ -.. _max32680_evkit: - -MAX32680EVKIT -############# +.. zephyr:board:: max32680evkit Overview ******** @@ -17,11 +14,6 @@ the latest generation Bluetooth® 5.2 Low Energy The Zephyr port is running on the MAX32680 MCU. -.. image:: img/max32680evkit_img1.jpg - :align: center - :alt: MAX32680 EVKIT - - Hardware ******** @@ -124,6 +116,10 @@ Below interfaces are supported by Zephyr on MAX32680EVKIT. +-----------+------------+-------------------------------------+ | Timer | on-chip | counter | +-----------+------------+-------------------------------------+ +| W1 | on-chip | one wire master | ++-----------+------------+-------------------------------------+ +| Flash | on-chip | flash | ++-----------+------------+-------------------------------------+ Connections and IOs =================== diff --git a/boards/adi/max32680evkit/max32680evkit_max32680_m4.dts b/boards/adi/max32680evkit/max32680evkit_max32680_m4.dts index 3e426960b0c..4547da3459d 100644 --- a/boards/adi/max32680evkit/max32680evkit_max32680_m4.dts +++ b/boards/adi/max32680evkit/max32680evkit_max32680_m4.dts @@ -72,7 +72,7 @@ st7735: st7735@0 { compatible = "sitronix,st7735r"; mipi-max-frequency = ; - mipi-mode = ; + mipi-mode = "MIPI_DBI_MODE_SPI_3WIRE"; reg = <0>; width = <130>; @@ -165,3 +165,8 @@ pinctrl-names = "default"; cs-gpios = <&gpio0 4 (GPIO_ACTIVE_LOW | MAX32_VSEL_VDDIOH)>; }; + +&w1 { + pinctrl-0 = <&owm_io_p0_6 &owm_pe_p0_7>; + pinctrl-names = "default"; +}; diff --git a/boards/adi/max32680evkit/max32680evkit_max32680_m4.yaml b/boards/adi/max32680evkit/max32680evkit_max32680_m4.yaml index 604d3935222..1fc90758f49 100644 --- a/boards/adi/max32680evkit/max32680evkit_max32680_m4.yaml +++ b/boards/adi/max32680evkit/max32680evkit_max32680_m4.yaml @@ -17,5 +17,7 @@ supported: - spi - adc - counter + - w1 + - flash ram: 128 flash: 512 diff --git a/boards/adi/max32690evkit/Kconfig.defconfig b/boards/adi/max32690evkit/Kconfig.defconfig index 342cc0ca513..2e5d60419c8 100644 --- a/boards/adi/max32690evkit/Kconfig.defconfig +++ b/boards/adi/max32690evkit/Kconfig.defconfig @@ -19,7 +19,7 @@ choice LV_COLOR_DEPTH default LV_COLOR_DEPTH_16 # 16 bit per pixel endchoice -config LV_COLOR_16_SWAP +configdefault LV_COLOR_16_SWAP default y endif # LVGL diff --git a/boards/adi/max32690evkit/doc/img/max32690evkit_img1.jpg b/boards/adi/max32690evkit/doc/img/max32690evkit.jpg similarity index 100% rename from boards/adi/max32690evkit/doc/img/max32690evkit_img1.jpg rename to boards/adi/max32690evkit/doc/img/max32690evkit.jpg diff --git a/boards/adi/max32690evkit/doc/index.rst b/boards/adi/max32690evkit/doc/index.rst index 5f4fe41e158..d976048dcb6 100644 --- a/boards/adi/max32690evkit/doc/index.rst +++ b/boards/adi/max32690evkit/doc/index.rst @@ -1,7 +1,4 @@ -.. _max32690_evkit: - -MAX32690EVKIT -############# +.. zephyr:board:: max32690evkit Overview ******** @@ -14,7 +11,7 @@ industrial sensors/networks, internet of things (IoT), and asset tracking. The Zephyr port is running on the MAX32690 MCU. -.. image:: img/max32690evkit_img1.jpg +.. image:: img/max32690evkit.jpg :align: center :alt: MAX32690 EVKIT Front @@ -110,7 +107,7 @@ Below interfaces are supported by Zephyr on MAX32690EVKIT. | UART | on-chip | serial | +-----------+------------+-------------------------------------+ | SPI | on-chip | spi | -+--------------------------------------------------------------+ ++-----------+------------+-------------------------------------+ | I2C | on-chip | i2c | +-----------+------------+-------------------------------------+ | TRNG | on-chip | entropy | @@ -123,6 +120,12 @@ Below interfaces are supported by Zephyr on MAX32690EVKIT. +-----------+------------+-------------------------------------+ | Timer | on-chip | counter | +-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| W1 | on-chip | one wire master | ++-----------+------------+-------------------------------------+ +| Flash | on-chip | flash | ++-----------+------------+-------------------------------------+ Connections and IOs diff --git a/boards/adi/max32690evkit/max32690evkit_max32690_m4.dts b/boards/adi/max32690evkit/max32690evkit_max32690_m4.dts index 85b9d251e07..d04a91852cd 100644 --- a/boards/adi/max32690evkit/max32690evkit_max32690_m4.dts +++ b/boards/adi/max32690evkit/max32690evkit_max32690_m4.dts @@ -63,7 +63,7 @@ st7735: st7735@0 { compatible = "sitronix,st7735r"; mipi-max-frequency = ; - mipi-mode = ; + mipi-mode = "MIPI_DBI_MODE_SPI_3WIRE"; reg = <0>; width = <130>; @@ -158,3 +158,12 @@ pinctrl-0 = <&spi0b_mosi_p2_28 &spi0b_miso_p2_27 &spi0b_sck_p2_29 &spi0b_ss1_p2_26>; pinctrl-names = "default"; }; + +&w1 { + pinctrl-0 = <&owm_io_p0_8 &owm_pe_p0_7>; + pinctrl-names = "default"; +}; + +&rtc_counter { + status = "okay"; +}; diff --git a/boards/adi/max32690evkit/max32690evkit_max32690_m4.yaml b/boards/adi/max32690evkit/max32690evkit_max32690_m4.yaml index bd7e017dd30..b6a5a9a5d7a 100644 --- a/boards/adi/max32690evkit/max32690evkit_max32690_m4.yaml +++ b/boards/adi/max32690evkit/max32690evkit_max32690_m4.yaml @@ -17,5 +17,9 @@ supported: - watchdog - adc - counter + - rtc_counter + - pwm + - w1 + - flash ram: 1024 flash: 3072 diff --git a/boards/adi/max32690fthr/doc/index.rst b/boards/adi/max32690fthr/doc/index.rst index edb480f3898..fdce08e32e8 100644 --- a/boards/adi/max32690fthr/doc/index.rst +++ b/boards/adi/max32690fthr/doc/index.rst @@ -1,7 +1,4 @@ -.. _max32690_fthr: - -MAX32690FTHR -############ +.. zephyr:board:: max32690fthr Overview ******** @@ -84,7 +81,9 @@ Below interfaces are supported by Zephyr on MAX32690FTHR. | I2C | on-chip | i2c | +-----------+------------+-------------------------------------+ | SPI | on-chip | spi | -+--------------------------------------------------------------+ ++-----------+------------+-------------------------------------+ +| Flash | on-chip | flash | ++-----------+------------+-------------------------------------+ Programming and Debugging ************************* diff --git a/boards/adi/max32690fthr/max32690fthr_max32690_m4.yaml b/boards/adi/max32690fthr/max32690fthr_max32690_m4.yaml index bbf1af6853f..d81738ee742 100644 --- a/boards/adi/max32690fthr/max32690fthr_max32690_m4.yaml +++ b/boards/adi/max32690fthr/max32690fthr_max32690_m4.yaml @@ -15,5 +15,6 @@ supported: - feather_serial - feather_i2c - feather_spi + - flash ram: 1024 flash: 3072 diff --git a/boards/adi/max78002evkit/Kconfig.max78002evkit b/boards/adi/max78002evkit/Kconfig.max78002evkit new file mode 100644 index 00000000000..a18aa6b97d9 --- /dev/null +++ b/boards/adi/max78002evkit/Kconfig.max78002evkit @@ -0,0 +1,7 @@ +# MAX78002EVKIT board configuration + +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MAX78002EVKIT + select SOC_MAX78002_M4 if BOARD_MAX78002EVKIT_MAX78002_M4 diff --git a/boards/adi/max78002evkit/board.cmake b/boards/adi/max78002evkit/board.cmake new file mode 100644 index 00000000000..b7d321b2f84 --- /dev/null +++ b/boards/adi/max78002evkit/board.cmake @@ -0,0 +1,7 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(openocd --cmd-pre-init "source [find interface/cmsis-dap.cfg]") +board_runner_args(openocd --cmd-pre-init "source [find target/max78002.cfg]") + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/adi/max78002evkit/board.yml b/boards/adi/max78002evkit/board.yml new file mode 100644 index 00000000000..f995c7199f0 --- /dev/null +++ b/boards/adi/max78002evkit/board.yml @@ -0,0 +1,9 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +board: + name: max78002evkit + full_name: MAX78002EVKIT + vendor: adi + socs: + - name: max78002 diff --git a/boards/adi/max78002evkit/doc/img/max78002evkit.webp b/boards/adi/max78002evkit/doc/img/max78002evkit.webp new file mode 100644 index 00000000000..f3452168a63 Binary files /dev/null and b/boards/adi/max78002evkit/doc/img/max78002evkit.webp differ diff --git a/boards/adi/max78002evkit/doc/img/max78002evkit_back.webp b/boards/adi/max78002evkit/doc/img/max78002evkit_back.webp new file mode 100644 index 00000000000..ae0c1b99ed6 Binary files /dev/null and b/boards/adi/max78002evkit/doc/img/max78002evkit_back.webp differ diff --git a/boards/adi/max78002evkit/doc/index.rst b/boards/adi/max78002evkit/doc/index.rst new file mode 100644 index 00000000000..a5bd4acf09b --- /dev/null +++ b/boards/adi/max78002evkit/doc/index.rst @@ -0,0 +1,295 @@ +.. zephyr:board:: max78002evkit + +Overview +******** +The MAX78002 evaluation kit (EV kit) provides a platform and tools for leveraging device capabilities to build new +generations of artificial intelligence (AI) products. + +The kit provides optimal versatility with a modular peripheral architecture, allowing a variety of input and output +devices to be remotely located. DVP and CSI cameras, I2S audio peripherals, digital microphones, and analog sensors +are supported, while a pair of industry-standard QWIIC connectors supports a large and growing array of aftermarket +development boards. An onboard stereo audio codec offers line-level audio input and output, and tactile input is +provided by a touch-enabled 2.4in TFT display. The MAX78002 energy consumption is tracked by a power accumulator, +with four channels of formatted results presented on a secondary TFT display. All device GPIOs are accessible on +0.1in pin headers. A standard coaxial power jack serves as power input, using the included 5V, 3A wall-mount +adapter. Two USB connectors provide serial access to the MAX78002, one directly and the other through a USB to UART +bridge. A third USB connector allows access to the MAX78002 energy consumption data. Rounding out the features, a +microSD connector provides the capability for inexpensive highdensity portable data storage. + +The Zephyr port is running on the MAX78002 MCU. + +.. image:: img/max78002evkit.webp + :align: center + :alt: MAX78002 EVKIT Front + +.. image:: img/max78002evkit_back.webp + :align: center + :alt: MAX78002 EVKIT Back + +Hardware +******** + +- MAX78002 MCU: + + - Dual-Core, Low-Power Microcontroller + + - Arm Cortex-M4 Processor with FPU up to 120MHz + - 2.5MB Flash, 64KB ROM, and 384KB SRAM + - Optimized Performance with 16KB Instruction Cache + - Optional Error Correction Code (ECC SEC-DED) for SRAM + - 32-Bit RISC-V Coprocessor up to 60MHz + - Up to 60 General-Purpose I/O Pins + - MIPI Camera Serial Interface 2 (MIPI CSI-2) Controller V2.1 + - Support for Two Data Lanes + - 12-Bit Parallel Camera Interface + - I 2S Controller/Target for Digital Audio Interface + - Secure Digital Interface Supports SD 3.0/SDIO 3.0/eMMC 4.51 + + - Convolutional Neural Network (CNN) Accelerator + + - Highly Optimized for Deep CNNs + - 2 Million 8-Bit Weight Capacity with 1-, 2-, 4-, and 8-bit Weights + - 1.3MB CNN Data Memory + - Programmable Input Image Size up to 2048 x 2048 Pixels + - Programmable Network Depth up to 128 Layers + - Programmable per Layer Network Channel Widths up to 1024 Channels + - 1- and 2-Dimensional Convolution Processing + - Capable of Processing VGA Images at 30fps + + - Power Management for Extending Battery Life + + - Integrated Single-Inductor Multiple-Output (SIMO) Switch-Mode Power Supply (SMPS) + - 2.85V to 3.6V Supply Voltage Range + - Support of Optional External Auxiliary CNN Power Supply + - Dynamic Voltage Scaling Minimizes Active Core Power Consumption + - 23.9μA/MHz While Loop Execution at 3.3V from Cache (CM4 only) + - Selectable SRAM Retention in Low-Power Modes with Real-Time Clock (RTC) Enabled + + - Security and Integrity + + - Available Secure Boot + - AES 128/192/256 Hardware Acceleration Engine + - True Random Number Generator (TRNG) Seed Generator + + - Ultra-Low-Power Wireless Microcontroller + + - Internal 100MHz Oscillator + - Flexible Low-Power Modes with 7.3728MHz System Clock Option + - 512KB Flash and 128KB SRAM (Optional ECC on One 32KB SRAM Bank) + - 16KB Instruction Cache + + - Bluetooth 5.2 LE Radio + + - Dedicated, Ultra-Low-Power, 32-Bit RISC-V Coprocessor to Offload Timing-Critical Bluetooth Processing + - Fully Open-Source Bluetooth 5.2 Stack Available + - Supports AoA, AoD, LE Audio, and Mesh + - High-Throughput (2Mbps) Mode + - Long-Range (125kbps and 500kbps) Modes + - Rx Sensitivity: -97.5dBm; Tx Power: +4.5dBm + - Single-Ended Antenna Connection (50Ω) + + - Power Management Maximizes Battery Life + + - 2.0V to 3.6V Supply Voltage Range + - Integrated SIMO Power Regulator + - Dynamic Voltage Scaling (DVS) + - 23.8μA/MHz Active Current at 3.0V + - 4.4μA at 3.0V Retention Current for 32KB + - Selectable SRAM Retention + RTC in Low-Power Modes + + - Multiple Peripherals for System Control + + - Up to Two High-Speed SPI Master/Slave + - Up to Three High-Speed I2C Master/Slave (3.4Mbps) + - Up to Four UART, One I2S Master/Slave + - Up to 8-Input, 10-Bit Sigma-Delta ADC 7.8ksps + - Up to Four Micro-Power Comparators + - Timers: Up to Two Four 32-Bit, Two LP, TwoWatchdog Timers + - 1-Wire® Master + - Up to Four Pulse Train (PWM) Engines + - RTC with Wake-Up Timer + - Up to 52 GPIOs + + - Security and Integrity​ + + - Available Secure Boot + - TRNG Seed Generator + - AES 128/192/256 Hardware Acceleration Engine + +- External devices connected to the MAX78002 EVKIT: + + - Color TFT Display + - Audio Stereo Codec Interface + - Digital Microphone + - A 8Mb QSPI ram + +Supported Features +================== + +The ``max78002evkit/max78002/m4`` board target supports the following interfaces: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | clock and reset control | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial | ++-----------+------------+-------------------------------------+ +| TRNG | on-chip | entropy | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| DMA | on-chip | dma controller | ++-----------+------------+-------------------------------------+ +| Watchdog | on-chip | watchdog | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| Timer | on-chip | counter | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| W1 | on-chip | one wire master | ++-----------+------------+-------------------------------------+ +| Flash | on-chip | flash | ++-----------+------------+-------------------------------------+ + +Connections and IOs +=================== + ++-----------+-------------------+----------------------------------------------------------------------------------+ +| Name | Signal | Usage | ++===========+===================+==================================================================================+ +| JP1 | 3V3 MON | Normal operation in conjunction with JP3 jumpered 1-2 | ++-----------+-------------------+----------------------------------------------------------------------------------+ +| JP2 | 3V3 SW PM BYPASS | Power monitor shunts for main 3.3 V system power are bypassed | ++-----------+-------------------+----------------------------------------------------------------------------------+ +| JP3 | CNN MON | Normal operation in conjunction with JP6 jumpered 1-2 | ++-----------+-------------------+----------------------------------------------------------------------------------+ +| JP4 | VCOREA PM BYPASS | Power monitor shunts for U4's share of VCOREA + CNN loads are bypassed | ++-----------+-------------------+----------------------------------------------------------------------------------+ +| JP5 | VCOREB PM BYPASS | Power monitor shunts for VCOREB are bypassed | ++-----------+-------------------+----------------------------------------------------------------------------------+ +| JP6 | VREGO_A PM BYPASS | Power monitor shunts for VREGO_A are bypassed | ++-----------+-------------------+----------------------------------------------------------------------------------+ +| JP7 | VBAT | Enable/Disable 3V3 VBAT power | ++-----------+-------------------+----------------------------------------------------------------------------------+ +| JP8 | VREGI | Enable/Disable 3V3 VREGI power | ++-----------+-------------------+----------------------------------------------------------------------------------+ +| JP9 | VREGI/VBAT | Onboard 3V3_PM / external source at TP10 supplies VREGI/VBAT | ++-----------+-------------------+----------------------------------------------------------------------------------+ +| JP10 | VDDIOH | Onboard 3V3_PM/3V3_SW supplies VDDIOH | ++-----------+-------------------+----------------------------------------------------------------------------------+ +| JP11 | VDDA | VREGO_A_PM powers VDDA | ++-----------+-------------------+----------------------------------------------------------------------------------+ +| JP12 | VDDIO | VREGO_A_PM powers VDDIO | ++-----------+-------------------+----------------------------------------------------------------------------------+ +| JP13 | VCOREB | VREGO_B powers VCOREB | ++-----------+-------------------+----------------------------------------------------------------------------------+ +| JP14 | VCOREA | VREGO_C ties to net VCOREA | ++-----------+-------------------+----------------------------------------------------------------------------------+ +| JP15 | VREF | DUT ADC VREF is supplied by precision external reference | ++-----------+-------------------+----------------------------------------------------------------------------------+ +| JP16 | I2C1 SDA | I2C1 DATA pull-up | ++-----------+-------------------+----------------------------------------------------------------------------------+ +| JP17 | I2C1 SCL | I2C1 CLOCK pull-up | ++-----------+-------------------+----------------------------------------------------------------------------------+ +| JP18 | TRIG1 | PWR accumulator trigger signal 1 ties to port 1.6 | ++-----------+-------------------+----------------------------------------------------------------------------------+ +| JP19 | TRIG2 | PWR accumulator trigger signal 2 ties to port 1.7 | ++-----------+-------------------+----------------------------------------------------------------------------------+ +| JP20 | UART0 EN | Connect/Disconnect USB-UART bridge to UART0 | ++-----------+-------------------+----------------------------------------------------------------------------------+ +| JP21 | I2C0_SDA | I2C0 DATA pull-up | ++-----------+-------------------+----------------------------------------------------------------------------------+ +| JP22 | I2C0_SCL | I2C0 CLOCK pull-up | ++-----------+-------------------+----------------------------------------------------------------------------------+ +| JP23 | UART1 EN | Connect/Disconnect USB-UART bridge to UART1 | ++-----------+-------------------+----------------------------------------------------------------------------------+ +| JP24 | EXT I2C0 EN | Enable/Disable QWIIC interface for I2C0 | ++-----------+-------------------+----------------------------------------------------------------------------------+ +| JP25 | PB1 PU | Enable/Disable 100kΩ pull-up for pushbutton mode, port 2.6 | ++-----------+-------------------+----------------------------------------------------------------------------------+ +| JP26 | PB2 PU | Enable/Disable 100kΩ pull-up for pushbutton mode, port 2.7 | ++-----------+-------------------+----------------------------------------------------------------------------------+ +| JP27 | I2C2 SDA | I2C2 DATA pull-up | ++-----------+-------------------+----------------------------------------------------------------------------------+ +| JP28 | I2C2 SCL | I2C2 CLOCK pull-up | ++-----------+-------------------+----------------------------------------------------------------------------------+ +| JP29 | VDDB | USB XCVR VDDB powered from VBUS / powered full time by system 3V3_PM | ++-----------+-------------------+----------------------------------------------------------------------------------+ +| JP30 | EXT I2C2 EN | Enable/Disable QWIIC interface for I2C2 | ++-----------+-------------------+----------------------------------------------------------------------------------+ +| JP31 | L/R SEL | Select MIC ON R/L CH, I2S microphone data stream | ++-----------+-------------------+----------------------------------------------------------------------------------+ +| JP32 | MIC-I2S I/O | External I2S/MIC data from I2S I/O / MIC header connected to I2S SDI | ++-----------+-------------------+----------------------------------------------------------------------------------+ +| JP33 | MIC-I2S/CODEC | Onboard CODEC data / external I2S data from header connects to I2S SDI | ++-----------+-------------------+----------------------------------------------------------------------------------+ +| JP34 | I2S VDD | Select 1.8V/3.3V for external MIC and DATA I2S interface | ++-----------+-------------------+----------------------------------------------------------------------------------+ +| JP35 | I2C1 SDA | I2C1 DATA pull-up | ++-----------+-------------------+----------------------------------------------------------------------------------+ +| JP36 | I2C1 SCL | I2C1 CLOCK pull-up | ++-----------+-------------------+----------------------------------------------------------------------------------+ +| JP37 | I2S CK SEL | Select SMA connector J6 / onboard crystal oscillator for I2S master clock source | ++-----------+-------------------+----------------------------------------------------------------------------------+ +| JP38 | DVP CAM PWR | Enable/Disable OVM7692 for DVP camera PWDN input | ++-----------+-------------------+----------------------------------------------------------------------------------+ +| JP39 | SW CAM PWUP | Camera reset and power up under port pin control | ++-----------+-------------------+----------------------------------------------------------------------------------+ +| JP40 | HW PWUP / SW PWUP | Camera will reset and power up as soon as 3.3V reaches a valid level | ++-----------+-------------------+----------------------------------------------------------------------------------+ +| JP41 | CSI CAM I2C EN | Connect/Disconnect I2C1 to CSI camera Digilent P5C I2C | ++-----------+-------------------+----------------------------------------------------------------------------------+ +| JP42 | TFT DC | TFT data/command select connects to port 2.2 | ++-----------+-------------------+----------------------------------------------------------------------------------+ +| JP43 | TFT CS | Select port 0.3 / port 1.7 to drive TFT CS | ++-----------+-------------------+----------------------------------------------------------------------------------+ +| JP44 | LED1 EN | Enable/Disable LED1 | ++-----------+-------------------+----------------------------------------------------------------------------------+ +| JP45 | LED2 EN | Enable/Disable LED2 | ++-----------+-------------------+----------------------------------------------------------------------------------+ + +Programming and Debugging +************************* + +Flashing +======== + +The MAX78002 MCU can be flashed by connecting an external debug probe to the +SWD port. SWD debug can be accessed through the Cortex 10-pin connector, JH8. +Logic levels are fixed to VDDIO (1.8V). + +Once the debug probe is connected to your host computer, then you can simply run the +``west flash`` command to write a firmware image into flash. + +.. note:: + + This board uses OpenOCD as the default debug interface. You can also use + a Segger J-Link with Segger's native tooling by overriding the runner, + appending ``--runner jlink`` to your ``west`` command(s). The J-Link should + be connected to the standard 2*5 pin debug connector (JH8) using an + appropriate adapter board and cable. + +Debugging +========= + +Please refer to the `Flashing`_ section and run the ``west debug`` command +instead of ``west flash``. + +References +********** + +- `MAX78002EVKIT web page`_ + +.. _MAX78002EVKIT web page: + https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max78002evkit.html diff --git a/boards/adi/max78002evkit/max78002evkit_max78002_m4.dts b/boards/adi/max78002evkit/max78002evkit_max78002_m4.dts new file mode 100644 index 00000000000..8b6df6c28c1 --- /dev/null +++ b/boards/adi/max78002evkit/max78002evkit_max78002_m4.dts @@ -0,0 +1,127 @@ +/* + * Copyright (c) 2024 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include +#include + +/ { + model = "Analog Devices MAX78002EVKIT"; + compatible = "adi,max78002evkit"; + + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,sram = &sram2; + zephyr,flash = &flash0; + }; + + leds { + compatible = "gpio-leds"; + led1: led_1 { + gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>; + label = "Green LED"; + }; + led2: led_2 { + gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; + label = "Red LED"; + }; + }; + + buttons { + compatible = "gpio-keys"; + pb1: pb1 { + gpios = <&gpio2 6 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "SW2"; + zephyr,code = ; + }; + pb2: pb2 { + gpios = <&gpio2 7 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "SW3"; + zephyr,code = ; + }; + pb_wakeup: pb_wakeup { + gpios = <&gpio3 1 (GPIO_PULL_UP | GPIO_ACTIVE_LOW + | MAX32_GPIO_VSEL_VDDIOH)>; + label = "Wakeup"; + zephyr,code = ; + }; + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + led0 = &led1; + led1 = &led2; + sw0 = &pb1; + sw1 = &pb2; + watchdog0 = &wdt0; + }; +}; + +&uart0 { + pinctrl-0 = <&uart0a_tx_p0_1 &uart0a_rx_p0_0>; + pinctrl-names = "default"; + current-speed = <115200>; + data-bits = <8>; + parity = "none"; + status = "okay"; +}; + +&clk_ipo { + status = "okay"; +}; + +&clk_ibro { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&gpio3 { + status = "okay"; +}; + +&trng { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + pinctrl-0 = <&i2c0_scl_p0_10 &i2c0_sda_p0_11>; + pinctrl-names = "default"; +}; + +&dma0 { + status = "okay"; +}; + +&wdt0 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + pinctrl-0 = <&spi0_mosi_p0_5 &spi0_miso_p0_6 &spi0_sck_p0_7 &spi0_ss0_p0_4>; + pinctrl-names = "default"; +}; + +&w1 { + pinctrl-0 = <&owm_io_p0_6 &owm_pe_p0_7>; + pinctrl-names = "default"; +}; diff --git a/boards/adi/max78002evkit/max78002evkit_max78002_m4.yaml b/boards/adi/max78002evkit/max78002evkit_max78002_m4.yaml new file mode 100644 index 00000000000..4631e4e276b --- /dev/null +++ b/boards/adi/max78002evkit/max78002evkit_max78002_m4.yaml @@ -0,0 +1,24 @@ +identifier: max78002evkit/max78002/m4 +name: max78002evkit m4 +vendor: adi +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - gpio + - serial + - trng + - i2c + - dma + - watchdog + - spi + - adc + - counter + - pwm + - w1 + - flash +ram: 384 +flash: 2560 diff --git a/boards/adi/max78002evkit/max78002evkit_max78002_m4_defconfig b/boards/adi/max78002evkit/max78002evkit_max78002_m4_defconfig new file mode 100644 index 00000000000..a048ab2608f --- /dev/null +++ b/boards/adi/max78002evkit/max78002evkit_max78002_m4_defconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +# Enable GPIO +CONFIG_GPIO=y + +# Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable UART +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/adi/sdp_k1/doc/index.rst b/boards/adi/sdp_k1/doc/index.rst index 0b23797da6b..680852f53dd 100644 --- a/boards/adi/sdp_k1/doc/index.rst +++ b/boards/adi/sdp_k1/doc/index.rst @@ -1,7 +1,4 @@ -.. _adi_sdp_k1: - -ADI SDP-K1 -########## +.. zephyr:board:: adi_sdp_k1 Overview ******** @@ -24,12 +21,6 @@ ADI components. - 16MB SDRAM - Arduino UNO and 120-pin SDP connectors -.. figure:: img/adi_sdp_k1.webp - :align: center - :alt: ADI SDP-K1 - - ADI SDP-K1 (Credit: Analog Devices, Inc.) - More information about the board can be found on the `ADI SDP-K1 website`_. Hardware diff --git a/boards/alientek/pandora_stm32l475/doc/index.rst b/boards/alientek/pandora_stm32l475/doc/index.rst index 082c814914a..d976ee7740f 100644 --- a/boards/alientek/pandora_stm32l475/doc/index.rst +++ b/boards/alientek/pandora_stm32l475/doc/index.rst @@ -1,7 +1,4 @@ -.. _pandora_stm32l475_board: - -Alientek STM32L475 Pandora -########################## +.. zephyr:board:: pandora_stm32l475 Overview ******** @@ -28,15 +25,12 @@ some highlights of the STM32L475 Pandora board: - MCU current ammeter with 4 ranges and auto-calibration - Connector for external board or RF-EEPROM - Four power supply options: + - ST-LINK/V2-1 - USB FS connector - External 5 V - CR2032 battery (not provided) -.. image:: img/pandora_stm32l475.jpg - :align: center - :alt: STM32L475 Pandora - More information about the board can be found at the `STM32L475 Pandora website`_. Hardware diff --git a/boards/alientek/pandora_stm32l475/pandora_stm32l475.dts b/boards/alientek/pandora_stm32l475/pandora_stm32l475.dts index 567e88a0152..7661de67198 100644 --- a/boards/alientek/pandora_stm32l475/pandora_stm32l475.dts +++ b/boards/alientek/pandora_stm32l475/pandora_stm32l475.dts @@ -83,6 +83,7 @@ qspi-max-frequency = <80000000>; jedec-id = [ef 40 18]; spi-bus-width = <4>; + writeoc = "PP_1_1_4"; status = "okay"; }; }; diff --git a/boards/altr/max10/doc/index.rst b/boards/altr/max10/doc/index.rst index 0ff861b4f83..0c16aa329e8 100644 --- a/boards/altr/max10/doc/index.rst +++ b/boards/altr/max10/doc/index.rst @@ -1,21 +1,11 @@ -.. _altera_max10: - -Altera MAX10 -############ +.. zephyr:board:: altera_max10 Overview ******** - The Zephyr kernel is supported on the Altera MAX10 Rev C development kit, using the Nios II Gen 2 soft CPU. -.. figure:: img/altera_max10.jpg - :align: center - :alt: Altera's MAX* 10 - - Altera's MAX* 10 (Credit: Altera) - Hardware ******** diff --git a/boards/ambiq/apollo3_evb/Kconfig.defconfig b/boards/ambiq/apollo3_evb/Kconfig.defconfig new file mode 100644 index 00000000000..bd2a5f91add --- /dev/null +++ b/boards/ambiq/apollo3_evb/Kconfig.defconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2024 Ambiq Micro Inc. + +if BOARD_APOLLO3_EVB + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 32768 if AMBIQ_STIMER_TIMER + +config LOG_BACKEND_SWO_FREQ_HZ + default 1000000 + depends on LOG_BACKEND_SWO + +endif # BOARD_APOLLO3_EVB diff --git a/boards/ambiq/apollo3_evb/apollo3_evb-pinctrl.dtsi b/boards/ambiq/apollo3_evb/apollo3_evb-pinctrl.dtsi index 7fbd368813b..26cf5e58063 100644 --- a/boards/ambiq/apollo3_evb/apollo3_evb-pinctrl.dtsi +++ b/boards/ambiq/apollo3_evb/apollo3_evb-pinctrl.dtsi @@ -17,6 +17,11 @@ input-enable; }; }; + itm_default: itm_default { + group1 { + pinmux = ; + }; + }; i2c0_default: i2c0_default { group1 { pinmux = , ; @@ -65,7 +70,11 @@ bias-pull-up; }; }; - + spid0_default: spid0_default { + group1 { + pinmux = , , , ; + }; + }; spi0_default: spi0_default { group1 { pinmux = , , ; diff --git a/boards/ambiq/apollo3_evb/apollo3_evb.dts b/boards/ambiq/apollo3_evb/apollo3_evb.dts index a47b97f1696..30828d729c5 100644 --- a/boards/ambiq/apollo3_evb/apollo3_evb.dts +++ b/boards/ambiq/apollo3_evb/apollo3_evb.dts @@ -2,6 +2,7 @@ #include #include "apollo3_evb-pinctrl.dtsi" +#include / { model = "Ambiq Apollo3 Blue evaluation board"; @@ -13,9 +14,11 @@ zephyr,flash = &flash0; zephyr,console = &uart0; zephyr,shell-uart = &uart0; + zephyr,uart-mcumgr = &uart0; zephyr,uart-pipe = &uart0; zephyr,flash-controller = &flash; zephyr,bt_hci = &bt_hci_apollo; + zephyr,code-partition = &slot0_partition; }; aliases { @@ -25,6 +28,9 @@ led2 = &led2; sw0 = &button0; sw1 = &button1; + bootloader-led0 = &led0; + mcuboot-led0 = &led0; + rtc = &rtc0; }; leds { @@ -56,14 +62,17 @@ button0: button_0 { gpios = <&gpio0_31 16 GPIO_ACTIVE_LOW>; label = "BTN0"; + zephyr,code = ; }; button1: button_1 { gpios = <&gpio0_31 18 GPIO_ACTIVE_LOW>; label = "BTN1"; + zephyr,code = ; }; button2: button_2 { gpios = <&gpio0_31 19 GPIO_ACTIVE_LOW>; label = "BTN2"; + zephyr,code = ; }; }; }; @@ -77,14 +86,36 @@ #address-cells = <1>; #size-cells = <1>; - /* Set 16KB of storage at the end of the 976KB of flash */ - storage_partition: partition@f0000 { + internal_boot_partition: partition@0 { + label = "internal_bootloader"; + reg = <0x00000000 0xc000>; + }; + + boot_partition: partition@c000 { + label = "mcuboot"; + reg = <0x0000c000 0xc000>; + }; + slot0_partition: partition@18000 { + label = "image-0"; + reg = <0x00018000 0x72000>; + }; + slot1_partition: partition@8a000 { + label = "image-1"; + reg = <0x0008a000 0x72000>; + }; + + /* Set 16KB of storage at the end of the 1024KB of flash */ + storage_partition: partition@fc000 { label = "storage"; - reg = <0x000f0000 0x4000>; + reg = <0x000fc000 0x4000>; }; }; }; +&stimer0 { + clk-source = <3>; +}; + &bleif { pinctrl-0 = <&bleif_default>; pinctrl-names = "default"; @@ -98,6 +129,12 @@ status = "okay"; }; +&itm { + pinctrl-0 = <&itm_default>; + pinctrl-names = "default"; + status = "okay"; +}; + &wdt0 { status = "okay"; }; @@ -116,6 +153,8 @@ pinctrl-0 = <&i2c3_default>; pinctrl-names = "default"; clock-frequency = ; + scl-gpios = <&gpio32_63 10 (GPIO_OPEN_DRAIN | GPIO_PULL_UP)>; + sda-gpios = <&gpio32_63 11 (GPIO_OPEN_DRAIN | GPIO_PULL_UP)>; status = "okay"; }; @@ -151,6 +190,11 @@ status = "okay"; }; +&rtc0 { + status = "okay"; + clock = "XTAL"; +}; + &adc0 { compatible = "ambiq,adc"; pinctrl-0 = <&adc0_default>; diff --git a/boards/ambiq/apollo3_evb/doc/index.rst b/boards/ambiq/apollo3_evb/doc/index.rst index 570e1d54d45..429d973d378 100644 --- a/boards/ambiq/apollo3_evb/doc/index.rst +++ b/boards/ambiq/apollo3_evb/doc/index.rst @@ -1,14 +1,7 @@ -.. _apollo3_evb: - -Ambiq Apollo3 Blue EVB -###################### +.. zephyr:board:: apollo3_evb Apollo3 Blue EVB is a board by Ambiq featuring their ultra-low power Apollo3 Blue SoC. -.. image:: ./apollo3-blue-soc-eval-board.jpg - :align: center - :alt: Apollo3 Blue EVB - Hardware ******** diff --git a/boards/ambiq/apollo3p_evb/Kconfig.defconfig b/boards/ambiq/apollo3p_evb/Kconfig.defconfig new file mode 100644 index 00000000000..5e677acf238 --- /dev/null +++ b/boards/ambiq/apollo3p_evb/Kconfig.defconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2024 Ambiq Micro Inc. + +if BOARD_APOLLO3P_EVB + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 32768 if AMBIQ_STIMER_TIMER + +config LOG_BACKEND_SWO_FREQ_HZ + default 1000000 + depends on LOG_BACKEND_SWO + +endif # BOARD_APOLLO3P_EVB diff --git a/boards/ambiq/apollo3p_evb/apollo3p_evb-pinctrl.dtsi b/boards/ambiq/apollo3p_evb/apollo3p_evb-pinctrl.dtsi index b026ba7722f..3eea582a372 100644 --- a/boards/ambiq/apollo3p_evb/apollo3p_evb-pinctrl.dtsi +++ b/boards/ambiq/apollo3p_evb/apollo3p_evb-pinctrl.dtsi @@ -17,6 +17,11 @@ input-enable; }; }; + itm_default: itm_default { + group1 { + pinmux = ; + }; + }; i2c0_default: i2c0_default { group1 { pinmux = , ; @@ -65,7 +70,11 @@ bias-pull-up; }; }; - + spid0_default: spid0_default { + group1 { + pinmux = , , , ; + }; + }; spi0_default: spi0_default { group1 { pinmux = , , ; diff --git a/boards/ambiq/apollo3p_evb/apollo3p_evb.dts b/boards/ambiq/apollo3p_evb/apollo3p_evb.dts index 75d61cbf2a3..88b3cefbb2f 100644 --- a/boards/ambiq/apollo3p_evb/apollo3p_evb.dts +++ b/boards/ambiq/apollo3p_evb/apollo3p_evb.dts @@ -2,6 +2,7 @@ #include #include "apollo3p_evb-pinctrl.dtsi" +#include / { model = "Ambiq Apollo3 Blue Plus evaluation board"; @@ -25,6 +26,7 @@ led2 = &led2; sw0 = &button0; sw1 = &button1; + rtc = &rtc0; }; leds { @@ -56,14 +58,17 @@ button0: button_0 { gpios = <&gpio0_31 16 GPIO_ACTIVE_LOW>; label = "BTN0"; + zephyr,code = ; }; button1: button_1 { gpios = <&gpio0_31 18 GPIO_ACTIVE_LOW>; label = "BTN1"; + zephyr,code = ; }; button2: button_2 { gpios = <&gpio0_31 19 GPIO_ACTIVE_LOW>; label = "BTN2"; + zephyr,code = ; }; }; }; @@ -85,6 +90,10 @@ }; }; +&stimer0 { + clk-source = <3>; +}; + &bleif { pinctrl-0 = <&bleif_default>; pinctrl-names = "default"; @@ -98,6 +107,12 @@ status = "okay"; }; +&itm { + pinctrl-0 = <&itm_default>; + pinctrl-names = "default"; + status = "okay"; +}; + &wdt0 { status = "okay"; }; @@ -116,6 +131,8 @@ pinctrl-0 = <&i2c3_default>; pinctrl-names = "default"; clock-frequency = ; + scl-gpios = <&gpio32_63 10 (GPIO_OPEN_DRAIN | GPIO_PULL_UP)>; + sda-gpios = <&gpio32_63 11 (GPIO_OPEN_DRAIN | GPIO_PULL_UP)>; status = "okay"; }; @@ -151,6 +168,11 @@ status = "okay"; }; +&rtc0 { + status = "okay"; + clock = "XTAL"; +}; + &adc0 { compatible = "ambiq,adc"; pinctrl-0 = <&adc0_default>; diff --git a/boards/ambiq/apollo3p_evb/doc/index.rst b/boards/ambiq/apollo3p_evb/doc/index.rst index c06f3b1e168..a5f848c4f2c 100644 --- a/boards/ambiq/apollo3p_evb/doc/index.rst +++ b/boards/ambiq/apollo3p_evb/doc/index.rst @@ -1,14 +1,7 @@ -.. _apollo3p_evb: - -Ambiq Apollo3 Blue Plus EVB -########################### +.. zephyr:board:: apollo3p_evb Apollo3 Blue Plus EVB is a board by Ambiq featuring their ultra-low power Apollo3 Blue Plus SoC. -.. image:: ./apollo3-blue-plus-soc-eval-board.jpg - :align: center - :alt: Apollo3 Blue Plus EVB - Hardware ******** diff --git a/boards/ambiq/apollo4p_blue_kxr_evb/Kconfig.defconfig b/boards/ambiq/apollo4p_blue_kxr_evb/Kconfig.defconfig index 5d16de3a1ca..63595ffddbd 100644 --- a/boards/ambiq/apollo4p_blue_kxr_evb/Kconfig.defconfig +++ b/boards/ambiq/apollo4p_blue_kxr_evb/Kconfig.defconfig @@ -4,6 +4,13 @@ if BOARD_APOLLO4P_BLUE_KXR_EVB +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 32768 if AMBIQ_STIMER_TIMER + +config LOG_BACKEND_SWO_FREQ_HZ + default 1000000 + depends on LOG_BACKEND_SWO + if BT config MAIN_STACK_SIZE diff --git a/boards/ambiq/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb-pinctrl.dtsi b/boards/ambiq/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb-pinctrl.dtsi index 1d64b010f60..f8c20b0fad9 100644 --- a/boards/ambiq/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb-pinctrl.dtsi +++ b/boards/ambiq/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb-pinctrl.dtsi @@ -16,6 +16,11 @@ input-enable; }; }; + itm_default: itm_default { + group1 { + pinmux = ; + }; + }; i2c0_default: i2c0_default { group1 { pinmux = , ; diff --git a/boards/ambiq/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb.dts b/boards/ambiq/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb.dts index 6a246a1f12e..cdcbcee689b 100644 --- a/boards/ambiq/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb.dts +++ b/boards/ambiq/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb.dts @@ -1,5 +1,6 @@ /dts-v1/; #include +#include #include "apollo4p_blue_kxr_evb-pinctrl.dtsi" @@ -25,6 +26,7 @@ led2 = &led2; sw0 = &button0; sw1 = &button1; + rtc = &rtc0; }; leds { @@ -45,13 +47,18 @@ buttons { compatible = "gpio-keys"; + polling-mode; button0: button_0 { gpios = <&gpio0_31 17 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; label = "BTN0"; + zephyr,code = ; + status = "okay"; }; button1: button_1 { gpios = <&gpio0_31 19 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; label = "BTN1"; + zephyr,code = ; + status = "okay"; }; }; }; @@ -63,10 +70,21 @@ status = "okay"; }; +&itm { + pinctrl-0 = <&itm_default>; + pinctrl-names = "default"; + status = "okay"; +}; + &counter0 { status = "okay"; }; +&rtc0 { + status = "okay"; + clock = "XTAL"; +}; + &wdt0 { status = "okay"; }; @@ -76,6 +94,8 @@ pinctrl-0 = <&i2c0_default>; pinctrl-names = "default"; clock-frequency = ; + scl-gpios = <&gpio0_31 5 (GPIO_OPEN_DRAIN | GPIO_PULL_UP)>; + sda-gpios = <&gpio0_31 6 (GPIO_OPEN_DRAIN | GPIO_PULL_UP)>; status = "okay"; }; @@ -117,6 +137,10 @@ }; }; +&stimer0 { + clk-source = <3>; +}; + &xo32m { pinctrl-0 = <&xo32m_default>; pinctrl-names = "default"; @@ -129,6 +153,12 @@ status = "okay"; }; +zephyr_udc0: &usb { + vddusb33-gpios = <&gpio0_31 13 (GPIO_PULL_UP)>; + vddusb0p9-gpios = <&gpio0_31 15 (GPIO_PULL_UP)>; + status = "okay"; +}; + &gpio0_31 { status = "okay"; }; diff --git a/boards/ambiq/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb.yaml b/boards/ambiq/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb.yaml index d9e9f244d86..a1e0378d592 100644 --- a/boards/ambiq/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb.yaml +++ b/boards/ambiq/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb.yaml @@ -16,6 +16,7 @@ supported: - i2c - clock_control - ble + - usbd testing: ignore_tags: - net diff --git a/boards/ambiq/apollo4p_blue_kxr_evb/doc/index.rst b/boards/ambiq/apollo4p_blue_kxr_evb/doc/index.rst index 3a1876297d2..81158fba6db 100644 --- a/boards/ambiq/apollo4p_blue_kxr_evb/doc/index.rst +++ b/boards/ambiq/apollo4p_blue_kxr_evb/doc/index.rst @@ -1,14 +1,7 @@ -.. _apollo4p_blue_kxr_evb: - -Ambiq Apollo4 Blue Plus KXR EVB -############################### +.. zephyr:board:: apollo4p_blue_kxr_evb Apollo4 Blue Plus KXR EVB is a board by Ambiq featuring their ultra-low power Apollo4 Blue Plus SoC. -.. image:: ./apollo4-blue-plus-kxr-soc-eval-board.jpg - :align: center - :alt: Apollo4 Blue Plus KXR EVB - Hardware ******** diff --git a/boards/ambiq/apollo4p_evb/Kconfig.defconfig b/boards/ambiq/apollo4p_evb/Kconfig.defconfig new file mode 100644 index 00000000000..782fec1cfb6 --- /dev/null +++ b/boards/ambiq/apollo4p_evb/Kconfig.defconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2024 Ambiq Micro Inc. + +if BOARD_APOLLO4P_EVB + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 32768 if AMBIQ_STIMER_TIMER + +config LOG_BACKEND_SWO_FREQ_HZ + default 1000000 + depends on LOG_BACKEND_SWO + +endif # BOARD_APOLLO4P_EVB diff --git a/boards/ambiq/apollo4p_evb/apollo4p_evb-pinctrl.dtsi b/boards/ambiq/apollo4p_evb/apollo4p_evb-pinctrl.dtsi index 125e1a7d238..dbbb233485e 100644 --- a/boards/ambiq/apollo4p_evb/apollo4p_evb-pinctrl.dtsi +++ b/boards/ambiq/apollo4p_evb/apollo4p_evb-pinctrl.dtsi @@ -17,6 +17,11 @@ input-enable; }; }; + itm_default: itm_default { + group1 { + pinmux = ; + }; + }; adc0_default: adc0_default{ group1 { pinmux = , ; diff --git a/boards/ambiq/apollo4p_evb/apollo4p_evb.dts b/boards/ambiq/apollo4p_evb/apollo4p_evb.dts index c678604f358..71ccc5399fd 100644 --- a/boards/ambiq/apollo4p_evb/apollo4p_evb.dts +++ b/boards/ambiq/apollo4p_evb/apollo4p_evb.dts @@ -1,5 +1,6 @@ /dts-v1/; #include +#include #include "apollo4p_evb-pinctrl.dtsi" @@ -45,13 +46,18 @@ buttons { compatible = "gpio-keys"; + polling-mode; button0: button_0 { gpios = <&gpio0_31 18 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; label = "BTN0"; + zephyr,code = ; + status = "okay"; }; button1: button_1 { gpios = <&gpio0_31 19 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; label = "BTN1"; + zephyr,code = ; + status = "okay"; }; }; }; @@ -63,8 +69,14 @@ status = "okay"; }; +&itm { + pinctrl-0 = <&itm_default>; + pinctrl-names = "default"; + status = "okay"; +}; + &adc0 { -compatible = "ambiq,adc"; + compatible = "ambiq,adc"; pinctrl-0 = <&adc0_default>; pinctrl-names = "default"; status = "okay"; @@ -88,6 +100,8 @@ compatible = "ambiq,adc"; pinctrl-0 = <&i2c0_default>; pinctrl-names = "default"; clock-frequency = ; + scl-gpios = <&gpio0_31 5 (GPIO_OPEN_DRAIN | GPIO_PULL_UP)>; + sda-gpios = <&gpio0_31 6 (GPIO_OPEN_DRAIN | GPIO_PULL_UP)>; status = "okay"; }; @@ -135,6 +149,16 @@ compatible = "ambiq,adc"; }; }; +&stimer0 { + clk-source = <3>; +}; + +zephyr_udc0: &usb { + vddusb33-gpios = <&gpio96_127 7 (GPIO_PULL_UP)>; + vddusb0p9-gpios = <&gpio96_127 5 (GPIO_PULL_UP)>; + status = "okay"; +}; + &gpio0_31 { status = "okay"; }; diff --git a/boards/ambiq/apollo4p_evb/apollo4p_evb.yaml b/boards/ambiq/apollo4p_evb/apollo4p_evb.yaml index 1b7b54a71e6..b54f5d4150c 100644 --- a/boards/ambiq/apollo4p_evb/apollo4p_evb.yaml +++ b/boards/ambiq/apollo4p_evb/apollo4p_evb.yaml @@ -17,6 +17,7 @@ supported: - rtc - adc - hwinfo + - usbd testing: ignore_tags: - net diff --git a/boards/ambiq/apollo4p_evb/doc/index.rst b/boards/ambiq/apollo4p_evb/doc/index.rst index fef698b0a1b..d2cc43e5bb4 100644 --- a/boards/ambiq/apollo4p_evb/doc/index.rst +++ b/boards/ambiq/apollo4p_evb/doc/index.rst @@ -1,14 +1,7 @@ -.. _apollo4p_evb: - -Ambiq Apollo4P EVB -################## +.. zephyr:board:: apollo4p_evb Apollo4P EVB is a board by Ambiq featuring their ultra-low power Apollo4 Plus SoC. -.. image:: ./apollo4-plus-soc-eval-board.jpg - :align: center - :alt: Apollo4P EVB - Hardware ******** diff --git a/boards/amd/acp_6_0_adsp/Kconfig.acp_6_0_adsp b/boards/amd/acp_6_0_adsp/Kconfig.acp_6_0_adsp new file mode 100644 index 00000000000..265e6dcf0c6 --- /dev/null +++ b/boards/amd/acp_6_0_adsp/Kconfig.acp_6_0_adsp @@ -0,0 +1,5 @@ +# Copyright (c) 2024 AMD +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ACP_6_0_ADSP +select SOC_ACP_6_0 diff --git a/boards/amd/acp_6_0_adsp/acp_6_0_acp_adsp.dts b/boards/amd/acp_6_0_adsp/acp_6_0_acp_adsp.dts new file mode 100644 index 00000000000..e54f613b9e2 --- /dev/null +++ b/boards/amd/acp_6_0_adsp/acp_6_0_acp_adsp.dts @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2024 AMD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include + +/ { + model = "AMD ACP_6_0 Audio DSP"; + compatible = "acp_6_0"; +}; diff --git a/boards/amd/acp_6_0_adsp/acp_6_0_adsp.yml b/boards/amd/acp_6_0_adsp/acp_6_0_adsp.yml new file mode 100644 index 00000000000..a93795d3c00 --- /dev/null +++ b/boards/amd/acp_6_0_adsp/acp_6_0_adsp.yml @@ -0,0 +1,14 @@ +# +# Copyright 2024 AMD +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: acp_6_0_adsp/acp_6_0 +name: AMD ACP6.0 Audio DSP +type: mcu +arch: xtensa +toolchain: + - zephyr + - xcc +vendor: amd diff --git a/boards/amd/acp_6_0_adsp/acp_6_0_adsp_defconfig b/boards/amd/acp_6_0_adsp/acp_6_0_adsp_defconfig new file mode 100644 index 00000000000..34c4fb56f28 --- /dev/null +++ b/boards/amd/acp_6_0_adsp/acp_6_0_adsp_defconfig @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_GEN_ISR_TABLES=y +CONFIG_GEN_IRQ_VECTOR_TABLE=y +CONFIG_XTENSA_RESET_VECTOR=y +CONFIG_OUTPUT_SYMBOLS=y +CONFIG_MULTI_LEVEL_INTERRUPTS=n +CONFIG_2ND_LEVEL_INTERRUPTS=n +CONFIG_DCACHE_LINE_SIZE_DETECT=n +CONFIG_DCACHE_LINE_SIZE=128 diff --git a/boards/amd/acp_6_0_adsp/board.cmake b/boards/amd/acp_6_0_adsp/board.cmake new file mode 100644 index 00000000000..7032982c617 --- /dev/null +++ b/boards/amd/acp_6_0_adsp/board.cmake @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 +board_set_flasher_ifnset(misc-flasher) +board_finalize_runner_args(misc-flasher) +board_set_rimage_target(rmb) diff --git a/boards/amd/acp_6_0_adsp/board.yml b/boards/amd/acp_6_0_adsp/board.yml new file mode 100644 index 00000000000..53ae8b3c871 --- /dev/null +++ b/boards/amd/acp_6_0_adsp/board.yml @@ -0,0 +1,6 @@ +board: + name: acp_6_0_adsp + full_name: ACP 6.0 Xtensa Audio DSP + vendor: amd + socs: + - name: acp_6_0 diff --git a/boards/amd/acp_6_0_adsp/doc/index.rst b/boards/amd/acp_6_0_adsp/doc/index.rst new file mode 100644 index 00000000000..fcc9221eafc --- /dev/null +++ b/boards/amd/acp_6_0_adsp/doc/index.rst @@ -0,0 +1,109 @@ +.. zephyr:board:: acp_6_0_adsp + +Overview +******** + +ACP 6.0 is Audio co-processor in AMD SoC based on HiFi5 DSP Xtensa Architecture, +Zephyr OS is ported to run various audio and speech use cases on +the SOF based framework. + +SOF can be built with either Zephyr or Cadence's proprietary +Xtensa OS (XTOS) and run on a ACP 6.0 AMD platforms. + +Hardware +******** + +- Board features: + + - RAM: 1.75MB HP SRAM & 512KB configurable IRAM/DRAM + - Audio Interfaces: + + - 1 x SP (I2S, PCM), + - 1 x BT (I2S, PCM), + - 1 x HS (I2S, PCM), + - DMIC + +Supported Features +================== + +The following hardware features are supported: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| I2S | on-chip | I2S controller | ++-----------+------------+-------------------------------------+ +| DMIC(PDM) | on-chip | PDM controller | ++-----------+------------+-------------------------------------+ + +System Clock +============ + +The ACP 6.0 SoC operates with an audio clock frequency ranging from 200 to 800 MHz. + +System requirements +******************* + +Xtensa Toolchain (optional) +=========================== + +The Zephyr SDK provides GCC-based toolchains necessary to build Zephyr for +the AMD ACP boards. For users looking for higher optimization levels, +building with the proprietary Xtensa toolchain from Cadence +might be preferable. + +The following instructions assume you have purchased and +installed the toolchain(s) and core(s) for your board following +instructions from Xtensa documentation. + +If you choose to build with the Xtensa toolchain instead of the Zephyr SDK, set +the following environment variables specific to the board in addition to the +Xtensa toolchain environment variable listed below. + +First, make sure, the necessary license is available from +Cadence and set the license variables as per the instruction from Cadence. +Next, set the following environment variables: + +The bottom three variables are specific to acp_6_0. + +.. code-block:: shell + + export XTENSA_TOOLCHAIN_PATH="tools installed path" + export XTENSA_BUILDS_DIR="user build directory path" + export ZEPHYR_TOOLCHAIN_VARIANT=xcc + export TOOLCHAIN_VER=RI-2019.1-linux + export XTENSA_CORE=LX7_HiFi5_PROD + +Programming and Debugging +************************* + +Building +======== + +Build as usual. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: acp_6_0_adsp/acp_6_0 + :goals: build + +Flashing +======== + +AMD supports only signed images flashing on ACP 6.0 platforms +through ACP Linux Driver. + +The following boot sequence messages can be observed in dmesg + + - booting DSP firmware + - ACP_DSP0_RUNSTALL : 0x0 + - ipc rx: 0x70000000 + - Firmware info: version 2:11:99-03a9d + - Firmware: ABI 3:29:1 Kernel ABI 3:23:0 + - mailbox upstream 0x0 - size 0x400 + - mailbox downstream 0x400 - size 0x400 + - stream region 0x1000 - size 0x400 + - debug region 0x800 - size 0x400 + - fw_state change: 3 -> 6 + - ipc rx done: 0x70000000 + - firmware boot complete diff --git a/boards/amd/kv260_r5/board.cmake b/boards/amd/kv260_r5/board.cmake index 029cda7417c..1b095406484 100644 --- a/boards/amd/kv260_r5/board.cmake +++ b/boards/amd/kv260_r5/board.cmake @@ -1,3 +1,4 @@ # Copyright (c) 2022 Linaro. # # SPDX-License-Identifier: Apache-2.0 +include(${ZEPHYR_BASE}/boards/common/xsdb.board.cmake) diff --git a/boards/amd/kv260_r5/doc/index.rst b/boards/amd/kv260_r5/doc/index.rst index ee1e04f2a7e..9383dbd9df6 100644 --- a/boards/amd/kv260_r5/doc/index.rst +++ b/boards/amd/kv260_r5/doc/index.rst @@ -1,7 +1,4 @@ -.. _kv260_r5: - -Xilinx KV260 Development Board RPU Cortex-R5 -############################################ +.. zephyr:board:: kv260_r5 Overview ******** @@ -17,10 +14,6 @@ This processing unit is based on an ARM Cortex-R5 CPU, it also enables the follo * Xilinx Zynq TTC (Cadence TTC) * Xilinx Zynq UART -.. figure:: kv260-starter-kit.jpg - :align: center - :alt: Xilinx KV260 Starter Kit - Hardware ******** Supported Features diff --git a/boards/amd/kv260_r5/support/xsdb.cfg b/boards/amd/kv260_r5/support/xsdb.cfg new file mode 100644 index 00000000000..2976c9e763f --- /dev/null +++ b/boards/amd/kv260_r5/support/xsdb.cfg @@ -0,0 +1,24 @@ +# Copyright (c) 2024 Advanced Micro Devices, Inc. +# +# SPDX-License-Identifier: Apache-2.0 + +proc load_image args { + set elf_file [lindex $args 0] + set fsblelf_file [lindex $args 1] + connect -url 127.0.0.1:3121 + after 2000 + targets -set -nocase -filter {name =~ "*R5*#0"} + rst -proc + dow $fsblelf_file + after 1000 + con + after 1000 + stop + targets -set -nocase -filter {name =~ "*R5*#0"} + after 2000 + dow $elf_file + con + exit +} + +load_image {*}$argv diff --git a/boards/andestech/adp_xc7k_ae350/adp_xc7k_ae350.dts b/boards/andestech/adp_xc7k_ae350/adp_xc7k_ae350.dts index 58c91613057..09763df9fff 100644 --- a/boards/andestech/adp_xc7k_ae350/adp_xc7k_ae350.dts +++ b/boards/andestech/adp_xc7k_ae350/adp_xc7k_ae350.dts @@ -215,3 +215,7 @@ &dma0 { status = "okay"; }; + +&mbox { + status = "okay"; +}; diff --git a/boards/arduino/due/doc/index.rst b/boards/arduino/due/doc/index.rst index dfc6e007801..e1eda346744 100644 --- a/boards/arduino/due/doc/index.rst +++ b/boards/arduino/due/doc/index.rst @@ -205,6 +205,8 @@ Now press the Reset button and you should see "Hello World! arduino_due" in your References ********** +.. target-notes:: + .. _Arduino Due website: https://www.arduino.cc/en/Main/ArduinoBoardDue .. _Atmel SAM3X8E Datasheet: http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-11057-32-bit-Cortex-M3-Microcontroller-SAM3X-SAM3A_Datasheet.pdf diff --git a/boards/arduino/mkrzero/arduino_mkrzero.dts b/boards/arduino/mkrzero/arduino_mkrzero.dts index b682e84aec8..a0f26d57fa0 100644 --- a/boards/arduino/mkrzero/arduino_mkrzero.dts +++ b/boards/arduino/mkrzero/arduino_mkrzero.dts @@ -89,6 +89,7 @@ spi-max-frequency = <1000000>; mmc { compatible = "zephyr,sdmmc-disk"; + disk-name = "SD"; status = "okay"; }; }; diff --git a/boards/arduino/nano_33_ble/Kconfig.defconfig b/boards/arduino/nano_33_ble/Kconfig.defconfig index 73bd7e9c32d..f7803f7718a 100644 --- a/boards/arduino/nano_33_ble/Kconfig.defconfig +++ b/boards/arduino/nano_33_ble/Kconfig.defconfig @@ -3,9 +3,6 @@ if BOARD_ARDUINO_NANO_33_BLE -config BT_CTLR - default BT - config REGULATOR default y if SENSOR diff --git a/boards/arduino/nano_33_iot/arduino_nano_33_iot.dts b/boards/arduino/nano_33_iot/arduino_nano_33_iot.dts index 6cce683f0a9..f5fc56c015f 100644 --- a/boards/arduino/nano_33_iot/arduino_nano_33_iot.dts +++ b/boards/arduino/nano_33_iot/arduino_nano_33_iot.dts @@ -114,7 +114,7 @@ reg = <0x6a>; }; - atecc608a@15 { + atecc608a@6a { compatible = "atmel,atecc608"; reg = <0x6a>; }; diff --git a/boards/arduino/nicla_sense_me/Kconfig.defconfig b/boards/arduino/nicla_sense_me/Kconfig.defconfig index b1e6a59d7d3..ff2238ca601 100644 --- a/boards/arduino/nicla_sense_me/Kconfig.defconfig +++ b/boards/arduino/nicla_sense_me/Kconfig.defconfig @@ -5,7 +5,4 @@ if BOARD_ARDUINO_NICLA_SENSE_ME -config BT_CTLR - default BT - endif # BOARD_ARDUINO_NICLA_SENSE_ME diff --git a/boards/arduino/nicla_sense_me/arduino_nicla_sense_me_defconfig b/boards/arduino/nicla_sense_me/arduino_nicla_sense_me_defconfig index f8691d1c1ce..8c35a59f63c 100644 --- a/boards/arduino/nicla_sense_me/arduino_nicla_sense_me_defconfig +++ b/boards/arduino/nicla_sense_me/arduino_nicla_sense_me_defconfig @@ -13,6 +13,3 @@ CONFIG_SERIAL=y # enable console CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/arduino/nicla_vision/CMakeLists.txt b/boards/arduino/nicla_vision/CMakeLists.txt new file mode 100644 index 00000000000..31b0b2ec593 --- /dev/null +++ b/boards/arduino/nicla_vision/CMakeLists.txt @@ -0,0 +1,4 @@ +# Copyright 2024 Felipe Neves +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources_ifdef(CONFIG_VIDEO camera_ext_clock.c) diff --git a/boards/arduino/nicla_vision/arduino_nicla_vision_stm32h747xx_m7.dts b/boards/arduino/nicla_vision/arduino_nicla_vision_stm32h747xx_m7.dts index ffd72fe9fb7..0028128f8e2 100644 --- a/boards/arduino/nicla_vision/arduino_nicla_vision_stm32h747xx_m7.dts +++ b/boards/arduino/nicla_vision/arduino_nicla_vision_stm32h747xx_m7.dts @@ -22,14 +22,7 @@ zephyr,sram = &sram0; zephyr,flash = &flash0; zephyr,code-partition = &slot0_partition; - }; - - sdram1: sdram@c0000000 { - compatible = "zephyr,memory-region", "mmio-sram"; - device_type = "memory"; - reg = <0xc0000000 DT_SIZE_M(8)>; - zephyr,memory-region = "SDRAM1"; - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>; + zephyr,camera = &dcmi; }; aliases { @@ -45,10 +38,12 @@ &clk_hse { status = "okay"; + hse-bypass; clock-frequency = ; }; &clk_lse { + lse-bypass; status = "okay"; }; @@ -122,13 +117,6 @@ }; }; -&i2c3 { - status = "okay"; - pinctrl-0 = <&i2c3_scl_pa8 &i2c3_sda_pc9>; - pinctrl-names = "default"; - clock-frequency = ; -}; - &spi4 { status = "okay"; pinctrl-0 = <&spi4_nss_pe11 &spi4_sck_pe12 @@ -170,6 +158,37 @@ }; }; +&quadspi { + pinctrl-0 = <&quadspi_clk_pf10 &quadspi_bk1_ncs_pg6 + &quadspi_bk1_io0_pd11 &quadspi_bk1_io1_pf9 + &quadspi_bk1_io2_pe2 &quadspi_bk1_io3_pd13>; + pinctrl-names = "default"; + status = "okay"; + + n25q128a1: qspi-nor-flash@90000000 { + compatible = "st,stm32-qspi-nor"; + reg = <0x90000000 DT_SIZE_M(16)>; /* 128 Mbits */ + qspi-max-frequency = <72000000>; + status = "okay"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + slot1_partition: partition@0 { + label = "image-1"; + reg = <0x00000000 DT_SIZE_M(1)>; + }; + + storage_partition: partition@100000 { + label = "storage"; + reg = <0x00100000 DT_SIZE_M(15)>; + }; + }; + }; +}; + &rng { status = "okay"; }; @@ -192,3 +211,81 @@ zephyr_udc0: &usbotg_hs { phys = <&otghs_ulpi_phy>; status = "okay"; }; + +&i2c3 { + status = "okay"; + pinctrl-0 = <&i2c3_scl_pa8 &i2c3_sda_pc9>; + pinctrl-names = "default"; + clock-frequency = ; + + gc2145: gc2145@3c { + compatible = "galaxycore,gc2145"; + reg = <0x3c>; + status = "okay"; + + port { + gc2145_ep_out: endpoint { + remote-endpoint = <&dcmi_ep_in>; + }; + }; + + }; +}; + +&dcmi { + pinctrl-0 = <&dcmi_d0_pc6 &dcmi_d1_pc7 &dcmi_d2_pe0 &dcmi_d3_pe1 + &dcmi_d4_pe4 &dcmi_d5_pd3 &dcmi_d6_pe5 &dcmi_d7_pe6 + &dcmi_pixclk_pa6 &dcmi_hsync_pa4 &dcmi_vsync_pg9>; + + pinctrl-names = "default"; + status = "okay"; + + sensor = <&gc2145>; + bus-width = <8>; + hsync-active = <0>; + vsync-active = <0>; + pixelclk-active = <0>; + capture-rate = <1>; + dmas = <&dma1 0 38 (STM32_DMA_PERIPH_TO_MEMORY | STM32_DMA_PERIPH_NO_INC | + STM32_DMA_MEM_INC | STM32_DMA_PERIPH_8BITS | STM32_DMA_MEM_32BITS | + STM32_DMA_PRIORITY_HIGH) STM32_DMA_FIFO_1_4>; + + port { + dcmi_ep_in: endpoint { + remote-endpoint = <&gc2145_ep_out>; + }; + }; +}; + +/* The Arduino nicla uses a PWM output to generate the clock for the + * GC2145 sensor, so we need to configure the PWM generator... + */ +&timers3 { + status = "okay"; + st,prescaler = <0>; + + cam_clock_pwm: pwm { + status = "okay"; + pinctrl-0 = <&tim3_ch2_pa7>; + pinctrl-names = "default"; + }; +}; + +&cam_clock_pwm { + /* ...then use the pwmclock node to start the clock generation */ + pwmclock: pwmclock { + status = "okay"; + compatible = "pwm-clock"; + clock-frequency = <0>; + #clock-cells = <1>; + pwms = <&cam_clock_pwm 2 PWM_HZ(10000000) PWM_POLARITY_NORMAL>; + }; +}; + +&dma1 { + status = "okay"; +}; + +&dmamux1 { + status = "okay"; +}; diff --git a/boards/arduino/opta/board_gpio_hse.c b/boards/arduino/nicla_vision/board_gpio_hse.c similarity index 92% rename from boards/arduino/opta/board_gpio_hse.c rename to boards/arduino/nicla_vision/board_gpio_hse.c index 2ee45f52dad..caeca006ad5 100644 --- a/boards/arduino/opta/board_gpio_hse.c +++ b/boards/arduino/nicla_vision/board_gpio_hse.c @@ -11,7 +11,7 @@ static int board_gpio_hse(void) { /* The external oscillator that drives the HSE clock should be enabled - * by setting the GPIOI1 pin. This function is registered at priority + * by setting the GPIOH1 pin. This function is registered at priority * RE_KERNEL_1 to be executed before the standard STM clock * setup code. */ diff --git a/boards/arduino/nicla_vision/camera_ext_clock.c b/boards/arduino/nicla_vision/camera_ext_clock.c new file mode 100644 index 00000000000..82b3695feb7 --- /dev/null +++ b/boards/arduino/nicla_vision/camera_ext_clock.c @@ -0,0 +1,42 @@ +/* + * Copyright 2024 Felipe Neves + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include + +LOG_MODULE_REGISTER(camera_ext_clock, CONFIG_CLOCK_CONTROL_LOG_LEVEL); + +int camera_ext_clock_enable(void) +{ + int ret; + uint32_t rate; + const struct device *cam_ext_clk_dev = DEVICE_DT_GET(DT_NODELABEL(pwmclock)); + + if (!device_is_ready(cam_ext_clk_dev)) { + LOG_ERR("Camera external clock source device is not ready!"); + return -ENODEV; + } + + ret = clock_control_on(cam_ext_clk_dev, (clock_control_subsys_t)0); + if (ret < 0) { + LOG_ERR("Failed to enable camera external clock error: (%d)", ret); + return ret; + } + + ret = clock_control_get_rate(cam_ext_clk_dev, (clock_control_subsys_t)0, &rate); + if (ret < 0) { + LOG_ERR("Failed to get camera external clock rate, error: (%d)", ret); + return ret; + } + + LOG_INF("Camera external clock rate: (%u) Hz", rate); + + return 0; +} + +SYS_INIT(camera_ext_clock_enable, POST_KERNEL, CONFIG_CLOCK_CONTROL_PWM_INIT_PRIORITY); diff --git a/boards/arduino/nicla_vision/doc/index.rst b/boards/arduino/nicla_vision/doc/index.rst index fac12f25fac..73b2d7cd733 100644 --- a/boards/arduino/nicla_vision/doc/index.rst +++ b/boards/arduino/nicla_vision/doc/index.rst @@ -61,6 +61,8 @@ following hardware features: +-----------+------------+-------------------------------------+ | SPI | on-chip | spi | +-----------+------------+-------------------------------------+ +| DCMI | on-chip | Parallel Camera interface | ++-----------+------------+-------------------------------------+ | IPM | on-chip | virtual mailbox based on HSEM | +-----------+------------+-------------------------------------+ | RADIO | Murata 1DX | WiFi and Bluetooth module | diff --git a/boards/arduino/opta/CMakeLists.txt b/boards/arduino/opta/CMakeLists.txt index c4483abeb70..07d2bfea9bc 100644 --- a/boards/arduino/opta/CMakeLists.txt +++ b/boards/arduino/opta/CMakeLists.txt @@ -1,4 +1,4 @@ # Copyright (c) 2021 STMicroelectronics # SPDX-License-Identifier: Apache-2.0 -zephyr_sources(board_gpio_hse.c) +zephyr_sources(board_gpio_init.c) diff --git a/boards/arduino/opta/Kconfig.defconfig b/boards/arduino/opta/Kconfig.defconfig index 1a89b70db5c..6199be7debe 100644 --- a/boards/arduino/opta/Kconfig.defconfig +++ b/boards/arduino/opta/Kconfig.defconfig @@ -11,34 +11,10 @@ config NET_L2_ETHERNET endif # NETWORKING -if USB_DEVICE_STACK +if BOARD_ARDUINO_OPTA_STM32H747XX_M7 -config USB_DEVICE_PRODUCT - default "Arduino Opta" +source "boards/common/usb/Kconfig.cdc_acm_serial.defconfig" -config USB_DEVICE_PID - default 0x0164 - -config USB_DEVICE_VID - default 0x35d1 - -config USB_DEVICE_INITIALIZE_AT_BOOT - default y - -if LOG - -# Logger cannot use itself to log -choice USB_CDC_ACM_LOG_LEVEL_CHOICE - default USB_CDC_ACM_LOG_LEVEL_OFF -endchoice - -# Set USB log level to error only -choice USB_DEVICE_LOG_LEVEL_CHOICE - default USB_DEVICE_LOG_LEVEL_ERR -endchoice - -endif # LOG - -endif # USB_DEVICE_STACK +endif # BOARD_ARDUINO_OPTA_STM32H747XX_M7 endif # BOARD_ARDUINO_OPTA diff --git a/boards/arduino/opta/arduino_opta-common.dtsi b/boards/arduino/opta/arduino_opta-common.dtsi index dcf957265c4..cf276172889 100644 --- a/boards/arduino/opta/arduino_opta-common.dtsi +++ b/boards/arduino/opta/arduino_opta-common.dtsi @@ -87,3 +87,117 @@ &mailbox { status = "okay"; }; + +&rng { + status = "okay"; +}; + +&usart3 { + pinctrl-0 = <&usart3_tx_pb10 &usart3_rx_pb11 &usart3_cts_pb13 &usart3_de_pb14>; + pinctrl-names = "default"; + current-speed = <115200>; + /* The RS485 is often used with the ModBus protocol. */ + modbus0 { + compatible = "zephyr,modbus-serial"; + de-gpios = <&gpiob 14 GPIO_ACTIVE_HIGH>; + re-gpios = <&gpiob 13 GPIO_ACTIVE_LOW>; + }; +}; + +&adc1 { + pinctrl-0 = <&adc1_inp0_pa0_c &adc1_inp6_pf12>; + pinctrl-names = "default"; + st,adc-clock-source = "SYNC"; + st,adc-prescaler = <4>; + vref-mv = <10000>; + + #address-cells = <1>; + #size-cells = <0>; + + a0: channel@0 { + reg = <0>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <16>; + }; + + a2: channel@6 { + reg = <6>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <16>; + }; + +}; + +&adc2 { + pinctrl-0 = <&adc2_inp9_pb0>; + pinctrl-names = "default"; + st,adc-clock-source = "SYNC"; + st,adc-prescaler = <4>; + vref-mv = <10000>; + + #address-cells = <1>; + #size-cells = <0>; + + a3: channel@9 { + reg = <9>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <16>; + }; +}; + +&adc3 { + pinctrl-0 = <&adc3_inp6_pf10 &adc3_inp7_pf8 &adc3_inp8_pf6 &adc3_inp9_pf4 &adc3_inp0_pc2_c>; + pinctrl-names = "default"; + st,adc-clock-source = "SYNC"; + st,adc-prescaler = <4>; + vref-mv = <10000>; + + #address-cells = <1>; + #size-cells = <0>; + + a1: channel@0 { + reg = <0>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <16>; + }; + + a4: channel@6 { + reg = <6>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <16>; + }; + + a5: channel@7 { + reg = <7>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <16>; + }; + + a6: channel@8 { + reg = <8>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <16>; + }; + + a7: channel@9 { + reg = <9>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <16>; + }; +}; diff --git a/boards/arduino/opta/arduino_opta_stm32h747xx_m4.dts b/boards/arduino/opta/arduino_opta_stm32h747xx_m4.dts index e2825752ddc..ea586872b63 100644 --- a/boards/arduino/opta/arduino_opta_stm32h747xx_m4.dts +++ b/boards/arduino/opta/arduino_opta_stm32h747xx_m4.dts @@ -18,7 +18,7 @@ chosen { zephyr,sram = &sram1; zephyr,flash = &flash1; - zephyr,code-partition = &slot0_partition; + zephyr,code-partition = &slot1_partition; }; }; @@ -28,7 +28,12 @@ #address-cells = <1>; #size-cells = <1>; - slot0_partition: partition@80000 { + slot0_partition: partition@0 { + label = "unused"; + reg = <0x00000000 DT_SIZE_K(512)>; + }; + + slot1_partition: partition@80000 { label = "image-0"; reg = <0x00080000 DT_SIZE_K(512)>; }; diff --git a/boards/arduino/opta/arduino_opta_stm32h747xx_m7.dts b/boards/arduino/opta/arduino_opta_stm32h747xx_m7.dts index e26a16c7858..d1b63e91e52 100644 --- a/boards/arduino/opta/arduino_opta_stm32h747xx_m7.dts +++ b/boards/arduino/opta/arduino_opta_stm32h747xx_m7.dts @@ -16,41 +16,20 @@ compatible = "arduino,opta-m7"; chosen { - zephyr,console = &cdc_acm_uart0; - zephyr,shell-uart = &cdc_acm_uart0; - zephyr,cdc-acm-uart0 = &cdc_acm_uart0; zephyr,sram = &sram0; zephyr,flash = &flash0; zephyr,code-partition = &slot0_partition; }; - - ethernet_phy_en: ethernet_phy_en { - compatible = "regulator-fixed"; - regulator-name = "ethernet-phy-reset-release"; - enable-gpios = <&gpioj 15 GPIO_ACTIVE_HIGH>; - regulator-boot-on; - status = "okay"; - }; - - sdram2: sdram@d0000000 { - compatible = "zephyr,memory-region", "mmio-sram"; - device_type = "memory"; - reg = <0xd0000000 DT_SIZE_M(32)>; - zephyr,memory-region = "SDRAM2"; - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>; - }; }; zephyr_udc0: &usbotg_fs { pinctrl-0 = <&usb_otg_fs_dm_pa11 &usb_otg_fs_dp_pa12>; pinctrl-names = "default"; status = "okay"; - - cdc_acm_uart0: cdc_acm_uart0 { - compatible = "zephyr,cdc-acm-uart"; - }; }; +#include <../boards/common/usb/cdc_acm_serial.dtsi> + &clk_hse { clock-frequency = ; hse-bypass; @@ -94,6 +73,12 @@ zephyr_udc0: &usbotg_fs { #address-cells = <1>; #size-cells = <1>; + boot_partition: partition@0 { + label = "mcu-boot"; + reg = <0x00000000 DT_SIZE_K(256)>; + read-only; + }; + slot0_partition: partition@40000 { label = "image-0"; reg = <0x00040000 DT_SIZE_K(768)>; @@ -101,6 +86,7 @@ zephyr_udc0: &usbotg_fs { }; }; +/* Assign USB to M7 by default */ &usbotg_fs { status = "okay"; }; @@ -109,10 +95,7 @@ zephyr_udc0: &usbotg_fs { status = "disabled"; }; -&cdc_acm_uart0 { - status = "okay"; -}; - +/* Assign ethernet to M7 by default */ &mac { pinctrl-0 = < ð_ref_clk_pa1 @@ -128,9 +111,9 @@ zephyr_udc0: &usbotg_fs { }; &mdio { - status = "okay"; pinctrl-0 = <ð_mdio_pa2 ð_mdc_pc1>; pinctrl-names = "default"; + status = "okay"; ethernet-phy@0 { compatible = "ethernet-phy"; @@ -138,7 +121,3 @@ zephyr_udc0: &usbotg_fs { status = "okay"; }; }; - -&rng { - status = "okay"; -}; diff --git a/boards/arduino/opta/arduino_opta_stm32h747xx_m7_defconfig b/boards/arduino/opta/arduino_opta_stm32h747xx_m7_defconfig index a0dd727422e..b57ac0d6f8e 100644 --- a/boards/arduino/opta/arduino_opta_stm32h747xx_m7_defconfig +++ b/boards/arduino/opta/arduino_opta_stm32h747xx_m7_defconfig @@ -27,11 +27,3 @@ CONFIG_STM32H7_BOOT_M4_AT_INIT=n CONFIG_SERIAL=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y -CONFIG_UART_LINE_CTRL=y - -# Enable USB Stack (needed for the console to work) -CONFIG_USB_DEVICE_STACK=y - -# Enable regulator (needed to enable eth) -CONFIG_REGULATOR=y -CONFIG_REGULATOR_FIXED=y diff --git a/boards/arduino/opta/board_gpio_init.c b/boards/arduino/opta/board_gpio_init.c new file mode 100644 index 00000000000..fcf8f6872a6 --- /dev/null +++ b/boards/arduino/opta/board_gpio_init.c @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2024 DNDG srl + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include + +static int board_gpio_init(void) +{ + /* The external oscillator that drives the HSE clock should be enabled + * by setting the GPIOI1 pin. This function is registered at priority + * RE_KERNEL_1 to be executed before the standard STM clock + * setup code. + * + * Note that the HSE should be turned on by the M7 only because M4 + * is not booted by default on Opta and cannot configure the clocks + * anyway. + */ +#ifdef CONFIG_BOARD_ARDUINO_OPTA_STM32H747XX_M7 + LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOH); + LL_GPIO_SetPinMode(GPIOH, LL_GPIO_PIN_1, LL_GPIO_MODE_OUTPUT); + LL_GPIO_SetPinSpeed(GPIOH, LL_GPIO_PIN_1, LL_GPIO_SPEED_FREQ_LOW); + LL_GPIO_SetPinOutputType(GPIOH, LL_GPIO_PIN_1, LL_GPIO_OUTPUT_PUSHPULL); + LL_GPIO_SetPinPull(GPIOH, LL_GPIO_PIN_1, LL_GPIO_PULL_UP); + LL_GPIO_SetOutputPin(GPIOH, LL_GPIO_PIN_1); +#endif + + /* The ethernet adapter is enabled by settig the GPIOJ15 pin to 1. + * This is done only if the network has been explicitly configured + */ +#ifdef CONFIG_NET_L2_ETHERNET + LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOJ); + LL_GPIO_SetPinMode(GPIOJ, LL_GPIO_PIN_15, LL_GPIO_MODE_OUTPUT); + LL_GPIO_SetPinSpeed(GPIOJ, LL_GPIO_PIN_15, LL_GPIO_SPEED_FREQ_LOW); + LL_GPIO_SetPinOutputType(GPIOJ, LL_GPIO_PIN_15, LL_GPIO_OUTPUT_PUSHPULL); + LL_GPIO_SetPinPull(GPIOJ, LL_GPIO_PIN_15, LL_GPIO_PULL_UP); + LL_GPIO_SetOutputPin(GPIOJ, LL_GPIO_PIN_15); +#endif + + return 0; +} + +SYS_INIT(board_gpio_init, PRE_KERNEL_1, 0); diff --git a/boards/arduino/opta/doc/index.rst b/boards/arduino/opta/doc/index.rst index 01badd338ff..8c6aa788487 100644 --- a/boards/arduino/opta/doc/index.rst +++ b/boards/arduino/opta/doc/index.rst @@ -67,6 +67,8 @@ supports the following hardware features: +-----------+------------+-------------------------------------+ | ETHERNET | on-board | eth | +-----------+------------+-------------------------------------+ +| RS485 | on-board | uart | ++-----------+------------+-------------------------------------+ The ``arduino_opta/stm32h747xx/m4`` board target supports the following hardware features: diff --git a/boards/arduino/portenta_h7/Kconfig.defconfig b/boards/arduino/portenta_h7/Kconfig.defconfig index 002ff75b5a5..b2a4abd35e7 100644 --- a/boards/arduino/portenta_h7/Kconfig.defconfig +++ b/boards/arduino/portenta_h7/Kconfig.defconfig @@ -10,34 +10,22 @@ config NET_L2_ETHERNET endif # NETWORKING -if USB_DEVICE_STACK +if BOARD_ARDUINO_PORTENTA_H7_STM32H747XX_M7 -config USB_DEVICE_PRODUCT - default "Arduino SA Portenta H7" +source "boards/common/usb/Kconfig.cdc_acm_serial.defconfig" -config USB_DEVICE_PID - default 0x035b +endif # BOARD_ARDUINO_PORTENTA_H7_STM32H747XX_M7 -config USB_DEVICE_VID - default 0x2341 - -config USB_DEVICE_INITIALIZE_AT_BOOT - default y +endif # BOARD_ARDUINO_PORTENTA_H7 -if LOG +if BT -# Logger cannot use itself to log -choice USB_CDC_ACM_LOG_LEVEL_CHOICE - default USB_CDC_ACM_LOG_LEVEL_OFF +choice AIROC_PART + default CYW4343W endchoice -# Set USB log level to error only -choice USB_DEVICE_LOG_LEVEL_CHOICE - default USB_DEVICE_LOG_LEVEL_ERR +choice CYW4343W_MODULE + default CYW4343W_MURATA_1DX endchoice -endif # LOG - -endif # USB_DEVICE_STACK - -endif # BOARD_ARDUINO_PORTENTA_H7 +endif # BT diff --git a/boards/arduino/portenta_h7/arduino_portenta_h7-common.dtsi b/boards/arduino/portenta_h7/arduino_portenta_h7-common.dtsi index e030d9d1cd0..7a61e830e52 100644 --- a/boards/arduino/portenta_h7/arduino_portenta_h7-common.dtsi +++ b/boards/arduino/portenta_h7/arduino_portenta_h7-common.dtsi @@ -243,7 +243,4 @@ zephyr_udc0: &usbotg_hs { <&rcc STM32_SRC_HSI48 USB_SEL(3)>; num-bidir-endpoints = < 4 >; status = "okay"; - cdc_acm_uart0: cdc_acm_uart0 { - compatible = "zephyr,cdc-acm-uart"; - }; }; diff --git a/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m4.dts b/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m4.dts index 12190a28715..3e135283481 100644 --- a/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m4.dts +++ b/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m4.dts @@ -28,5 +28,5 @@ }; &usart1 { - status = "disabled"; + status = "okay"; }; diff --git a/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m4_defconfig b/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m4_defconfig index 8a931846ae7..768c0b2c03d 100644 --- a/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m4_defconfig +++ b/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m4_defconfig @@ -10,9 +10,7 @@ CONFIG_ARM_MPU=y # Enable HW stack protection CONFIG_HW_STACK_PROTECTION=y -# Enable uart driver -# CONFIG_SERIAL=y - -# By default CONSOLE is assigned to m7 -# CONFIG_CONSOLE=y -# CONFIG_UART_CONSOLE=y +# On M4, USART1 is used as the UART console backend by default +CONFIG_SERIAL=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7.dts b/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7.dts index 4b43bb6cbd4..3a3745c5a7d 100644 --- a/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7.dts +++ b/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7.dts @@ -8,6 +8,7 @@ #include #include #include "arduino_portenta_h7-common.dtsi" +#include <../boards/common/usb/cdc_acm_serial.dtsi> / { model = "Arduino Portenta H7 board"; @@ -15,12 +16,10 @@ /* HW resources are split between CM7 and CM4 */ chosen { - zephyr,console = &cdc_acm_uart0; - zephyr,shell-uart = &cdc_acm_uart0; - zephyr,cdc-acm-uart0 = &cdc_acm_uart0; zephyr,sram = &sram0; zephyr,flash = &flash0; zephyr,code-partition = &slot0_partition; + zephyr,bt-hci = &bt_hci_uart; }; oscen: oscen { @@ -80,9 +79,9 @@ clock-frequency = ; }; - +/* USART1 is enabled on M4 by default */ &usart1 { - status = "okay"; + status = "disabled"; }; &i2c1 { @@ -98,10 +97,6 @@ status = "okay"; }; -&cdc_acm_uart0 { - status = "okay"; -}; - &flash0 { partitions { compatible = "fixed-partitions"; @@ -137,3 +132,24 @@ }; }; }; + +&uart7 { + pinctrl-0 = <&uart7_tx_pa15 &uart7_rx_pf6 + &uart7_cts_pf9 &uart7_rts_pf8>; + pinctrl-names = "default"; + current-speed = <115200>; + hw-flow-control; + status = "okay"; + + bt_hci_uart: bt_hci_uart { + compatible = "zephyr,bt-hci-uart"; + status = "okay"; + + murata-1dx { + compatible = "infineon,cyw43xxx-bt-hci"; + bt-reg-on-gpios = <&gpioj 12 GPIO_ACTIVE_HIGH>; + bt-host-wake-gpios = <&gpioj 13 GPIO_ACTIVE_HIGH>; + bt-dev-wake-gpios = <&gpioj 14 GPIO_ACTIVE_HIGH>; + }; + }; +}; diff --git a/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7_defconfig b/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7_defconfig index ff4b2954d02..acc978d70c9 100644 --- a/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7_defconfig +++ b/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7_defconfig @@ -16,12 +16,8 @@ CONFIG_HW_STACK_PROTECTION=y # Use zephyr,code-partition as flash offset CONFIG_USE_DT_CODE_PARTITION=y -# Disable following to assign serial ports to m4 core - -# Enable uart driver +# On M7, USB CDC ACM is used as the UART console backend by default CONFIG_SERIAL=y - -# Enable console CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_UART_LINE_CTRL=y @@ -29,6 +25,3 @@ CONFIG_UART_LINE_CTRL=y # Enable regulator CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED=y - -# Enable USB Stack -CONFIG_USB_DEVICE_STACK=y diff --git a/boards/arduino/portenta_h7/doc/index.rst b/boards/arduino/portenta_h7/doc/index.rst index 3ed69927f4f..2d1d167065e 100644 --- a/boards/arduino/portenta_h7/doc/index.rst +++ b/boards/arduino/portenta_h7/doc/index.rst @@ -65,6 +65,8 @@ The current Zephyr arduino_portenta_h7 board configuration supports the followin +-----------+------------+-------------------------------------+ | ETHERNET | on-board | eth | +-----------+------------+-------------------------------------+ +| RADIO | Murata 1DX | WiFi and Bluetooth module | ++-----------+------------+-------------------------------------+ Other hardware features are not yet supported on Zephyr porting. @@ -74,6 +76,22 @@ is used; to enable the use of the external oscillator, manually specify the hardware revision at build time (see :ref:`application_board_version` for information on how to build for specific revisions of the board). +Applications that intend to use BLE must specify hardware revision at build time. + +Currently only BLE is supported on this board, WiFi is not supported. + +Fetch Binary Blobs +****************** + +The board Bluetooth/WiFi module requires fetching some binary blob files, to do +that run the command: + +.. code-block:: console + + west blobs fetch hal_infineon + +.. note:: Only Bluetooth functionality is currently supported. + Resources sharing ================= diff --git a/boards/arduino/uno_r4/arduino_uno_r4_common.dtsi b/boards/arduino/uno_r4/arduino_uno_r4_common.dtsi index 6a81cec8b7d..f9fff37eaab 100644 --- a/boards/arduino/uno_r4/arduino_uno_r4_common.dtsi +++ b/boards/arduino/uno_r4/arduino_uno_r4_common.dtsi @@ -64,12 +64,30 @@ clock-frequency = <48000000>; }; -&cgc { - clock-source = <&hoco>; - iclk-div = <1>; - pclka-div = <1>; - pclkb-div = <2>; - pclkc-div = <1>; - pclkd-div = <1>; - fclk-div = <2>; +&pclkblock { + clocks = <&hoco>; +}; + +&iclk { + div = <1>; +}; + +&pclka { + div = <1>; +}; + +&pclkb { + div = <2>; +}; + +&pclkc { + div = <1>; +}; + +&pclkd { + div = <1>; +}; + +&fclk { + div = <2>; }; diff --git a/boards/arduino/uno_r4/arduino_uno_r4_minima-pinctrl.dtsi b/boards/arduino/uno_r4/arduino_uno_r4_minima-pinctrl.dtsi index c9538829a48..863d9e6030a 100644 --- a/boards/arduino/uno_r4/arduino_uno_r4_minima-pinctrl.dtsi +++ b/boards/arduino/uno_r4/arduino_uno_r4_minima-pinctrl.dtsi @@ -4,12 +4,18 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include &pinctrl { sci2_default: sci2_default { group1 { - pinmux = , ; + /* tx */ + psels = ; + drive-strength = "medium"; + }; + group2 { + /* rx */ + psels = ; }; }; }; diff --git a/boards/arduino/uno_r4/arduino_uno_r4_minima_defconfig b/boards/arduino/uno_r4/arduino_uno_r4_minima_defconfig index bcd05338d44..3c655ea376e 100644 --- a/boards/arduino/uno_r4/arduino_uno_r4_minima_defconfig +++ b/boards/arduino/uno_r4/arduino_uno_r4_minima_defconfig @@ -16,8 +16,6 @@ CONFIG_UART_CONSOLE=y # Enable GPIO CONFIG_GPIO=y -CONFIG_PINCTRL=y - CONFIG_CLOCK_CONTROL=y CONFIG_USE_DT_CODE_PARTITION=y diff --git a/boards/arduino/uno_r4/arduino_uno_r4_wifi-pinctrl.dtsi b/boards/arduino/uno_r4/arduino_uno_r4_wifi-pinctrl.dtsi index 093d4e4cdf9..9add47e4723 100644 --- a/boards/arduino/uno_r4/arduino_uno_r4_wifi-pinctrl.dtsi +++ b/boards/arduino/uno_r4/arduino_uno_r4_wifi-pinctrl.dtsi @@ -4,12 +4,18 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include &pinctrl { sci2_default: sci2_default { group1 { - pinmux = , ; + /* tx */ + psels = ; + drive-strength = "medium"; + }; + group2 { + /* rx */ + psels = ; }; }; }; diff --git a/boards/arduino/uno_r4/arduino_uno_r4_wifi_defconfig b/boards/arduino/uno_r4/arduino_uno_r4_wifi_defconfig index 76f5a5fb854..48137e86d7a 100644 --- a/boards/arduino/uno_r4/arduino_uno_r4_wifi_defconfig +++ b/boards/arduino/uno_r4/arduino_uno_r4_wifi_defconfig @@ -16,8 +16,6 @@ CONFIG_UART_CONSOLE=y # Enable GPIO CONFIG_GPIO=y -CONFIG_PINCTRL=y - CONFIG_CLOCK_CONTROL=y CONFIG_USE_DT_CODE_PARTITION=y diff --git a/boards/arm/fvp_base_revc_2xaemv8a/doc/index.rst b/boards/arm/fvp_base_revc_2xaemv8a/doc/index.rst index 81a098b3ae1..0954a2d90a1 100644 --- a/boards/arm/fvp_base_revc_2xaemv8a/doc/index.rst +++ b/boards/arm/fvp_base_revc_2xaemv8a/doc/index.rst @@ -117,6 +117,8 @@ Networking References ********** +.. target-notes:: + 1. (ID070919) Arm® Architecture Reference Manual - Armv8, for Armv8-A architecture profile 2. AArch64 Exception and Interrupt Handling 3. https://developer.arm.com/tools-and-software/simulation-models/fixed-virtual-platforms diff --git a/boards/arm/fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a.yaml b/boards/arm/fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a.yaml index ce4bdb8a5f1..02a956dc628 100644 --- a/boards/arm/fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a.yaml +++ b/boards/arm/fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a.yaml @@ -5,6 +5,9 @@ identifier: fvp_base_revc_2xaemv8a name: FVP Emulation FVP_Base_RevC-2xAEMvA arch: arm64 type: sim +simulation: + - name: armfvp + exec: FVP_Base_RevC-2xAEMvA toolchain: - zephyr - cross-compile diff --git a/boards/arm/fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a_fvp_base_revc_2xaemv8a_smp_ns.yaml b/boards/arm/fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a_fvp_base_revc_2xaemv8a_smp_ns.yaml index e64ed9f8e7c..fae3074e6d8 100644 --- a/boards/arm/fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a_fvp_base_revc_2xaemv8a_smp_ns.yaml +++ b/boards/arm/fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a_fvp_base_revc_2xaemv8a_smp_ns.yaml @@ -1,10 +1,13 @@ # Copyright (c) 2022 Arm Limited (or its affiliates). All rights reserved. # SPDX-License-Identifier: Apache-2.0 -identifier: fvp_base_revc_2xaemv8a//smp/ns +identifier: fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a/smp/ns name: FVP Emulation FVP_Base_RevC-2xAEMvA (SMP) arch: arm64 type: sim +simulation: + - name: armfvp + exec: FVP_Base_RevC-2xAEMvA toolchain: - zephyr - cross-compile diff --git a/boards/arm/fvp_baser_aemv8r/doc/aarch32.rst b/boards/arm/fvp_baser_aemv8r/doc/aarch32.rst index d1911002020..8fcc4d07b0e 100644 --- a/boards/arm/fvp_baser_aemv8r/doc/aarch32.rst +++ b/boards/arm/fvp_baser_aemv8r/doc/aarch32.rst @@ -96,6 +96,8 @@ Refer to the detailed overview about :ref:`application_debugging`. References ********** +.. target-notes:: + .. [1] https://developer.arm.com/tools-and-software/simulation-models/fixed-virtual-platforms/arm-ecosystem-models .. [2] Arm Architecture Reference Manual Supplement - Armv8, for Armv8-R AArch32 architecture profile https://developer.arm.com/documentation/ddi0568/latest diff --git a/boards/arm/fvp_baser_aemv8r/doc/aarch64.rst b/boards/arm/fvp_baser_aemv8r/doc/aarch64.rst index 3c45ce22840..724ee182cc9 100644 --- a/boards/arm/fvp_baser_aemv8r/doc/aarch64.rst +++ b/boards/arm/fvp_baser_aemv8r/doc/aarch64.rst @@ -106,6 +106,8 @@ See :ref:`debug_with_arm_ds` for how to debug with Arm Development Studio [5]_. References ********** +.. target-notes:: + .. [1] https://developer.arm.com/tools-and-software/simulation-models/fixed-virtual-platforms/arm-ecosystem-models .. [2] Arm Architecture Reference Manual Supplement - Armv8, for Armv8-R AArch64 architecture profile https://developer.arm.com/documentation/ddi0600/latest/ diff --git a/boards/arm/fvp_baser_aemv8r/doc/debug-with-arm-ds.rst b/boards/arm/fvp_baser_aemv8r/doc/debug-with-arm-ds.rst index 874cd70aa7e..79b48aca535 100644 --- a/boards/arm/fvp_baser_aemv8r/doc/debug-with-arm-ds.rst +++ b/boards/arm/fvp_baser_aemv8r/doc/debug-with-arm-ds.rst @@ -141,5 +141,7 @@ connected in ``Debug Control`` window. References ********** +.. target-notes:: + .. [1] https://developer.arm.com/tools-and-software/embedded/arm-development-studio .. [2] https://developer.arm.com/tools-and-software/simulation-models/fixed-virtual-platforms/arm-ecosystem-models diff --git a/boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch32.yaml b/boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch32.yaml index 0f7b38d648c..16cdd5264c8 100644 --- a/boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch32.yaml +++ b/boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch32.yaml @@ -6,6 +6,9 @@ identifier: fvp_baser_aemv8r/fvp_aemv8r_aarch32 name: FVP Emulation FVP_BaseR_AEMv8R AArch32 arch: arm type: sim +simulation: + - name: armfvp + exec: FVP_BaseR_AEMv8R toolchain: - zephyr - cross-compile diff --git a/boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch32_smp.yaml b/boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch32_smp.yaml index d056a315af6..e8eceff40e8 100644 --- a/boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch32_smp.yaml +++ b/boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch32_smp.yaml @@ -5,6 +5,9 @@ identifier: fvp_baser_aemv8r/fvp_aemv8r_aarch32/smp name: FVP Emulation FVP_BaseR_AEMv8R AArch32 (SMP) arch: arm type: sim +simulation: + - name: armfvp + exec: FVP_BaseR_AEMv8R toolchain: - zephyr - cross-compile diff --git a/boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch64.yaml b/boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch64.yaml index 501a6b89374..6f07158964b 100644 --- a/boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch64.yaml +++ b/boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch64.yaml @@ -5,6 +5,9 @@ identifier: fvp_baser_aemv8r/fvp_aemv8r_aarch64 name: FVP Emulation FVP_BaseR_AEMv8R arch: arm64 type: sim +simulation: + - name: armfvp + exec: FVP_BaseR_AEMv8R toolchain: - zephyr - cross-compile diff --git a/boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch64_smp.yaml b/boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch64_smp.yaml index fa1baf892d9..bd4807b0710 100644 --- a/boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch64_smp.yaml +++ b/boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch64_smp.yaml @@ -5,6 +5,9 @@ identifier: fvp_baser_aemv8r/fvp_aemv8r_aarch64/smp name: FVP Emulation FVP_BaseR_AEMv8R (SMP) arch: arm64 type: sim +simulation: + - name: armfvp + exec: FVP_BaseR_AEMv8R toolchain: - zephyr - cross-compile diff --git a/boards/arm/mps2/mps2_an385.yaml b/boards/arm/mps2/mps2_an385.yaml index 7bda3fc3dcc..bbd929892c5 100644 --- a/boards/arm/mps2/mps2_an385.yaml +++ b/boards/arm/mps2/mps2_an385.yaml @@ -2,7 +2,8 @@ identifier: mps2/an385 name: ARM V2M MPS2 type: mcu arch: arm -simulation: qemu +simulation: + - name: qemu toolchain: - zephyr - gnuarmemb diff --git a/boards/arm/mps2/mps2_an521_cpu0.yaml b/boards/arm/mps2/mps2_an521_cpu0.yaml index e5247a292e5..68210b954b4 100644 --- a/boards/arm/mps2/mps2_an521_cpu0.yaml +++ b/boards/arm/mps2/mps2_an521_cpu0.yaml @@ -4,7 +4,9 @@ type: mcu arch: arm ram: 4096 flash: 4096 -simulation: qemu +simulation: + - name: qemu + - name: armfvp toolchain: - gnuarmemb - zephyr diff --git a/boards/arm/mps2/mps2_an521_cpu0_ns.yaml b/boards/arm/mps2/mps2_an521_cpu0_ns.yaml index 6a24f388785..c4a589c9396 100644 --- a/boards/arm/mps2/mps2_an521_cpu0_ns.yaml +++ b/boards/arm/mps2/mps2_an521_cpu0_ns.yaml @@ -4,7 +4,9 @@ type: mcu arch: arm ram: 512 flash: 512 -simulation: qemu +simulation: + - name: qemu + - name: armfvp toolchain: - gnuarmemb - zephyr diff --git a/boards/arm/mps2/mps2_an521_cpu1.yaml b/boards/arm/mps2/mps2_an521_cpu1.yaml index 29bd722157b..3880d479d6e 100644 --- a/boards/arm/mps2/mps2_an521_cpu1.yaml +++ b/boards/arm/mps2/mps2_an521_cpu1.yaml @@ -4,7 +4,9 @@ type: mcu arch: arm ram: 512 flash: 468 -simulation: qemu +simulation: + - name: qemu + - name: armfvp toolchain: - gnuarmemb - zephyr diff --git a/boards/arm/mps3/Kconfig b/boards/arm/mps3/Kconfig index 019f22aae49..836143e8f31 100644 --- a/boards/arm/mps3/Kconfig +++ b/boards/arm/mps3/Kconfig @@ -1,5 +1,6 @@ # Copyright (c) 2021 Linaro Limited +# Copyright 2024 Arm Limited and/or its affiliates # SPDX-License-Identifier: Apache-2.0 config BOARD_MPS3 - select QEMU_TARGET + select QEMU_TARGET if BOARD_MPS3_CORSTONE300_AN547 || BOARD_MPS3_CORSTONE300_AN547_NS diff --git a/boards/arm/mps3/Kconfig.defconfig b/boards/arm/mps3/Kconfig.defconfig index 078012e46a7..4ce6cf0c910 100644 --- a/boards/arm/mps3/Kconfig.defconfig +++ b/boards/arm/mps3/Kconfig.defconfig @@ -1,7 +1,8 @@ # Copyright (c) 2018-2021 Linaro Limited +# Copyright 2024 Arm Limited and/or its affiliates # SPDX-License-Identifier: Apache-2.0 -if BOARD_MPS3_AN547 +if BOARD_MPS3_CORSTONE300_AN547 || BOARD_MPS3_CORSTONE300_AN552 || BOARD_MPS3_CORSTONE300_FVP || BOARD_MPS3_CORSTONE310_AN555 || BOARD_MPS3_CORSTONE310_FVP # MPU-based null-pointer dereferencing detection cannot # be applied as the (0x0 - 0x400) is unmapped but QEMU diff --git a/boards/arm/mps3/Kconfig.mps3 b/boards/arm/mps3/Kconfig.mps3 index 84dd3fff095..02d081f826a 100644 --- a/boards/arm/mps3/Kconfig.mps3 +++ b/boards/arm/mps3/Kconfig.mps3 @@ -1,7 +1,17 @@ # Copyright (c) 2023 Nordic Semiconductor +# Copyright 2024 Arm Limited and/or its affiliates # # SPDX-License-Identifier: Apache-2.0 config BOARD_MPS3 select SOC_SERIES_MPS3 - select SOC_MPS3_AN547 + select SOC_MPS3_CORSTONE300 if BOARD_MPS3_CORSTONE300_AN547 || \ + BOARD_MPS3_CORSTONE300_AN547_NS || \ + BOARD_MPS3_CORSTONE300_AN552 || \ + BOARD_MPS3_CORSTONE300_AN552_NS || \ + BOARD_MPS3_CORSTONE300_FVP || \ + BOARD_MPS3_CORSTONE300_FVP_NS + select SOC_MPS3_CORSTONE310 if BOARD_MPS3_CORSTONE310_AN555 || \ + BOARD_MPS3_CORSTONE310_AN555_NS || \ + BOARD_MPS3_CORSTONE310_FVP || \ + BOARD_MPS3_CORSTONE310_FVP_NS diff --git a/boards/arm/mps3/board.cmake b/boards/arm/mps3/board.cmake index b8035658dd2..ca090a832fc 100644 --- a/boards/arm/mps3/board.cmake +++ b/boards/arm/mps3/board.cmake @@ -1,24 +1,46 @@ # Copyright (c) 2021 Linaro +# Copyright 2024 Arm Limited and/or its affiliates # SPDX-License-Identifier: Apache-2.0 -# The AN547 FVP must be used to enable Ethos-U55 NPU support, but QEMU also +# The FVP variant must be used to enable Ethos-U55 NPU support, but QEMU also # supports the AN547 without the NPU. # -# For emulation, QEMU is used by default. To use AN547 FVP as an emulation -# use the 'run_armfvp' target, for example: +# Default emulation: +# QEMU is used by default for corstone300/an547 and +# FVP is used by default for corstone300/fvp. +# FVP is used by default for corstone310/fvp. # -# $ west build -b mps3_an547 samples/hello_world -t run_armfvp -set(SUPPORTED_EMU_PLATFORMS qemu armfvp) -# QEMU settings -set(QEMU_CPU_TYPE_${ARCH} cortex-m55) -set(QEMU_FLAGS_${ARCH} - -cpu ${QEMU_CPU_TYPE_${ARCH}} - -machine mps3-an547 - -nographic - -vga none - ) +if(CONFIG_BOARD_MPS3_CORSTONE300_AN547 OR CONFIG_BOARD_MPS3_CORSTONE300_AN547_NS) + set(SUPPORTED_EMU_PLATFORMS qemu) + + # QEMU settings + set(QEMU_CPU_TYPE_${ARCH} cortex-m55) + set(QEMU_FLAGS_${ARCH} + -cpu ${QEMU_CPU_TYPE_${ARCH}} + -machine mps3-an547 + -nographic + -vga none + ) +elseif(CONFIG_BOARD_MPS3_CORSTONE300_FVP OR CONFIG_BOARD_MPS3_CORSTONE300_FVP_NS) + set(SUPPORTED_EMU_PLATFORMS armfvp) + set(ARMFVP_BIN_NAME FVP_Corstone_SSE-300_Ethos-U55) +elseif(CONFIG_BOARD_MPS3_CORSTONE300) + string(REPLACE "mps3/corstone300;" "" board_targets "${board_targets}") + string(REPLACE ";" "\n" board_targets "${board_targets}") + message(FATAL_ERROR "Please use a target from the list below: \n${board_targets}\n") +elseif(CONFIG_BOARD_MPS3_CORSTONE310_FVP OR CONFIG_BOARD_MPS3_CORSTONE310_FVP_NS) + set(SUPPORTED_EMU_PLATFORMS armfvp) + set(ARMFVP_BIN_NAME FVP_Corstone_SSE-310) + if(CONFIG_BOARD_MPS3_CORSTONE310_FVP) + set(ARMFVP_FLAGS + # default is '0x11000000' but should match cpu.INITSVTOR which is 0. + -C mps3_board.sse300.iotss3_systemcontrol.INITSVTOR_RST=0 + ) + endif() +endif() + board_set_debugger_ifnset(qemu) if (CONFIG_BUILD_WITH_TFM) @@ -28,14 +50,11 @@ if (CONFIG_BUILD_WITH_TFM) set(QEMU_KERNEL_OPTION "-device;loader,file=${CMAKE_BINARY_DIR}/zephyr/tfm_merged.hex") endif() -# FVP settings -set(ARMFVP_BIN_NAME FVP_Corstone_SSE-300_Ethos-U55) - # FVP Parameters # -C indicate a config option in the form of: # instance.parameter=value # Run the FVP with --list-params to list all options -set(ARMFVP_FLAGS +set(ARMFVP_FLAGS ${ARMFVP_FLAGS} -C mps3_board.uart0.out_file=- -C mps3_board.uart0.unbuffered_output=1 -C mps3_board.uart1.out_file=- @@ -43,4 +62,7 @@ set(ARMFVP_FLAGS -C mps3_board.uart2.out_file=- -C mps3_board.uart2.unbuffered_output=1 -C mps3_board.visualisation.disable-visualisation=1 + -C mps3_board.telnetterminal0.start_telnet=0 + -C mps3_board.telnetterminal1.start_telnet=0 + -C mps3_board.telnetterminal2.start_telnet=0 ) diff --git a/boards/arm/mps3/board.yml b/boards/arm/mps3/board.yml index 9eea26dc244..0257cd3a9d1 100644 --- a/boards/arm/mps3/board.yml +++ b/boards/arm/mps3/board.yml @@ -3,6 +3,22 @@ board: full_name: MPS3 AN547 vendor: arm socs: - - name: 'an547' + - name: 'corstone300' variants: - - name: 'ns' + - name: 'an547' + variants: + - name: 'ns' + - name: 'an552' + variants: + - name: 'ns' + - name: 'fvp' + variants: + - name: 'ns' + - name: 'corstone310' + variants: + - name: 'an555' + variants: + - name: 'ns' + - name: 'fvp' + variants: + - name: 'ns' diff --git a/boards/arm/mps3/doc/img/mps3_an547.jpg b/boards/arm/mps3/doc/img/mps3.jpg similarity index 100% rename from boards/arm/mps3/doc/img/mps3_an547.jpg rename to boards/arm/mps3/doc/img/mps3.jpg diff --git a/boards/arm/mps3/doc/index.rst b/boards/arm/mps3/doc/index.rst index e618b9a714c..82089408ec0 100644 --- a/boards/arm/mps3/doc/index.rst +++ b/boards/arm/mps3/doc/index.rst @@ -1,61 +1,196 @@ -.. _mps3_an547_board: +.. _mps3_board: -ARM MPS3 AN547 +ARM MPS3 ############### Overview ******** -The mps3_an547 board configuration is used by Zephyr applications that run -on the MPS3 AN547 board. It provides support for the MPS3 AN547 ARM Cortex-M55 -CPU and the following devices: +The mps3 board configuration is used by Zephyr applications that run +on the MPS3 board. It provides support for the following devices: - Nested Vectored Interrupt Controller (NVIC) - System Tick System Clock (SYSTICK) - Cortex-M System Design Kit GPIO - Cortex-M System Design Kit UART - Ethos-U55 NPU +- AN547 and AN552 support Arm Cortex-M55 CPU +- AN555 support Arm Cortex-M85 CPU -.. image:: img/mps3_an547.jpg +.. image:: img/mps3.jpg :align: center - :alt: ARM MPS3 AN547 + :alt: ARM MPS3 -This board configuration also supports using the `Corstone-300 FVP`_ to emulate -a MPS3 AN547 hardware platform. +`Corstone-300 FVP`_/`Corstone-310 FVP`_ (Fixed Virtual Platforms) is a complete +simulations of the Arm system, including processor, memory and peripherals. +They are available free of charge for Linux and Windows systems. +The FVPs have been selected for simulation since they provide access to the +Ethos-U55 NPU, which is unavailable in QEMU or other simulation platforms. -The Corstone-300 FVP (Fixed Virtual Platform) is a complete simulation of the -Arm system, including processor, memory and peripherals. It is a available free -of charge for Linux and Windows systems. The FVP has been selected for -simulation since it provides access to the Ethos-U55 NPU, which is unavailable -in QEMU or other simulation platforms. - -To run the Fixed Virtual Platform simulation tool you must download "FVP model -for the Corstone-300 MPS3" from Arm and install it on your host PC. This board -has been tested with version 11.12.57 (Nov 2 2020). Zephyr board options ==================== -The MPS3+ AN547 is an SoC with Cortex-M55 architecture. Zephyr provides support -for building for both Secure and Non-Secure firmware. +.. tabs:: + + .. tab:: MPS3 Corstone-300 (AN547) + + The MPS3+ AN547 is an SoC with Cortex-M55 architecture. Zephyr provides support + for building for both Secure and Non-Secure firmware. + + The BOARD options are summarized below: + + +-------------------------------+-----------------------------------------------+ + | BOARD | Description | + +===============================+===============================================+ + | ``mps3/corstone300/an547`` | For building Secure (or Secure-only) firmware | + +-------------------------------+-----------------------------------------------+ + | ``mps3/corstone300/an547/ns`` | For building Non-Secure firmware | + +-------------------------------+-----------------------------------------------+ + + FPGA Usage: + - Follow `Programming and Debugging`_ for build and flash instructions. + + FVP Usage: + - FVP is not supported for this variant. + + QEMU Usage: + - To run with QEMU instead of the default FVP, override the emulator selection at build time via: + + .. code-block:: bash + + $ west build -b mps3_an547 samples/hello_world -DEMU_PLATFORM=qemu -t run + + .. tab:: MPS3 Corstone-300 (AN552) + + The MPS3+ AN552 is an SoC with Cortex-M55 architecture. Zephyr provides support + for building for both Secure and Non-Secure firmware. + + The BOARD options are summarized below: + + +-------------------------------+-----------------------------------------------+ + | BOARD | Description | + +===============================+===============================================+ + | ``mps3/corstone300/an552`` | For building Secure (or Secure-only) firmware | + +-------------------------------+-----------------------------------------------+ + | ``mps3/corstone300/an552/ns`` | For building Non-Secure firmware | + +-------------------------------+-----------------------------------------------+ + + FPGA Usage: + - Follow `Programming and Debugging`_ for build and flash instructions. + + FVP Usage: + - FVP not supported for this variant. + + QEMU Usage: + - QEMU not supported for this variant of board. + + .. tab:: MPS3 Corstone-300 (FVP) + + The MPS3+ FVP is an SoC with Cortex-M55 architecture. Zephyr provides support + for building for both Secure and Non-Secure firmware. + + The BOARD options are summarized below: + + +-------------------------------+-----------------------------------------------+ + | BOARD | Description | + +===============================+===============================================+ + | ``mps3/corstone300/fvp`` | For building Secure (or Secure-only) firmware | + +-------------------------------+-----------------------------------------------+ + | ``mps3/corstone300/fvp/ns`` | For building Non-Secure firmware | + +-------------------------------+-----------------------------------------------+ + + FPGA Usage: + - N/A. + + FVP Usage: + - To run with the FVP, first set environment variable ``ARMFVP_BIN_PATH`` before using it. Then you can run it with ``west build -t run``. + + .. code-block:: bash + + export ARMFVP_BIN_PATH=/path/to/fvp/directory + west build -b {BOARD qualifier from table above} samples/hello_world -t run + + To run the Fixed Virtual Platform simulation tool you must download "FVP model + for the Corstone-300 MPS3" from Arm and install it on your host PC. This board + has been tested with version 11.24.13 (Jan 4 2024). + + QEMU Usage: + - N/A. + + .. tab:: MPS3 Corstone-310 (AN555) + + The MPS3+ AN555 is an SoC with Cortex-M85 architecture. Zephyr provides support + for building for both Secure and Non-Secure firmware. + + The BOARD options are summarized below: + + +-------------------------------+-----------------------------------------------+ + | BOARD | Description | + +===============================+===============================================+ + | ``mps3/corstone310/an555`` | For building Secure (or Secure-only) firmware | + +-------------------------------+-----------------------------------------------+ + | ``mps3/corstone310/an555/ns`` | For building Non-Secure firmware | + +-------------------------------+-----------------------------------------------+ + + FPGA Usage: + - Follow `Programming and Debugging`_ for build and flash instructions. -The BOARD options are summarized below: + FVP Usage: + - FVP not supported for this variant. -+----------------------+-----------------------------------------------+ -| BOARD | Description | -+======================+===============================================+ -| ``mps3/an547`` | For building Secure (or Secure-only) firmware | -+----------------------+-----------------------------------------------+ -| ``mps3/an547/ns`` | For building Non-Secure firmware | -+----------------------+-----------------------------------------------+ + QEMU Usage: + - QEMU not supported for this variant of board. + + .. tab:: MPS3 Corstone-310 (FVP) + + The MPS3+ FVP is an SoC with Cortex-M85 architecture. Zephyr provides support + for building for both Secure and Non-Secure firmware. + + The BOARD options are summarized below: + + +-------------------------------+-----------------------------------------------+ + | BOARD | Description | + +===============================+===============================================+ + | ``mps3/corstone310/fvp`` | For building Secure (or Secure-only) firmware | + +-------------------------------+-----------------------------------------------+ + | ``mps3/corstone310/fvp/ns`` | For building Non-Secure firmware | + +-------------------------------+-----------------------------------------------+ + + FPGA Usage: + - N/A. + + FVP Usage: + - To run with the FVP, first set environment variable ``ARMFVP_BIN_PATH`` before using it. Then you can run it with ``west build -t run``. + + .. code-block:: bash + + export ARMFVP_BIN_PATH=/path/to/fvp/directory + west build -b {BOARD qualifier from table above} samples/hello_world -t run + + To run the Fixed Virtual Platform simulation tool you must download "FVP model + for the Corstone-310 MPS3" from Arm and install it on your host PC. This board + has been tested with version 11.24.13 (Jan 4 2024). + + QEMU Usage: + - N/A. + + .. note:: + Board qualifier must include the board name as mentioned above. + ``mps3/corstone300`` or ``mps3/corstone310`` without the board name is not a valid qualifier. Hardware ******** -ARM MPS3 AN547 provides the following hardware components: +ARM MPS3 provides the following hardware components: + +- CPU + + - AN547 and AN552 support Arm Cortex-M55 CPU and + Soft Macro Model (SMM) implementation of SSE-300 subsystem + - AN555 support Arm Cortex-M85 CPU and + Soft Macro Model (SMM) implementation of SSE-310 subsystem -- ARM Cortex-M55 -- Soft Macro Model (SMM) implementation of SSE-300 subsystem - Memory - 8MB BRAM @@ -89,7 +224,7 @@ ARM MPS3 AN547 provides the following hardware components: Supported Features =================== -The ``mps3/an547`` board configuration supports the following hardware features: +The ``MPS3`` board configuration supports the following hardware features: +-----------+------------+-------------------------------------+ | Interface | Controller | Driver/Component | @@ -109,14 +244,16 @@ See the `MPS3 FPGA Website`_ for a complete list of MPS3 AN547 board hardware features. The default configuration can be found in -:zephyr_file:`boards/arm/mps3/mps3_an547_defconfig`. + - For AN547: :zephyr_file:`boards/arm/mps3/mps3_corstone300_an547_defconfig`. + - For AN552: :zephyr_file:`boards/arm/mps3/mps3_corstone300_an552_defconfig`. + - For FVP : :zephyr_file:`boards/arm/mps3/mps3_corstone300_fvp_defconfig`. + - For AN555: :zephyr_file:`boards/arm/mps3/mps3_corstone310_an555_defconfig`. -For more details refer to `MPS3 AN547 Technical Reference Manual (TRM)`_. Serial Port =========== -The MPS3 AN547 has six UARTs. The Zephyr console output by default, uses +The MPS3 has six UARTs. The Zephyr console output by default, uses UART0, which is exposed over the Debug USB interface (J8). Serial port 0 on the Debug USB interface is the MCC board control console. @@ -127,26 +264,28 @@ Serial port 2 on the Debug USB interface is connected to UART 1. Serial port 3 on the Debug USB interface is connected to UART 2. +.. Programming and Debugging: + Programming and Debugging ************************* Flashing ======== -MPS3 AN547 provides: +MPS3 provides: - A USB connection to the host computer, which exposes Mass Storage and CMSIS-DAP, and serial ports. -Building an application ------------------------ +Building an application with AN547 +---------------------------------- You can build applications in the usual way. Here is an example for -the :zephyr:code-sample:`hello_world` application. +the :zephyr:code-sample:`hello_world` application with AN547. .. zephyr-app-commands:: :zephyr-app: samples/hello_world - :board: mps3/an547 + :board: mps3/corstone300/an547 :goals: build Open a serial terminal (minicom, putty, etc.) with the following settings: @@ -178,7 +317,7 @@ The update requires 3 steps: 1. Copy application files to ``/SOFTWARE/``. 2. Open ``/MB/HBI0309C/AN547/images.txt``. -3. Update the ``AN547/images.txt`` file as follows: +3. Update the ``images.txt`` file as follows: .. code-block:: bash @@ -200,46 +339,45 @@ serial port: Hello World! mps3 -FVP Usage -========= - -To run with the FVP, first set environment variable ``ARMFVP_BIN_PATH`` before -using it. Then you can run it with ``west build -t run``. - -.. code-block:: bash - - export ARMFVP_BIN_PATH=/path/to/fvp/directory - west build -t run - - -QEMU Usage -========== - -To run with QEMU instead of the default FVP, override the emulator selection -at build time via: - -.. code-block:: bash - - $ west build -b mps3_an547 samples/hello_world -DEMU_PLATFORM=qemu -t run - - -Note, however, that the Ethos-U55 NPU is not available in QEMU. If you require -the use of the NPU, please use the default FVP for device emulation. +For more details refer to: + - `MPS3 AN547 Technical Reference Manual (TRM)`_ + - `MPS3 AN552 Technical Reference Manual (TRM)`_ + - `MPS3 AN555 Technical Reference Manual (TRM)`_ + - `MPS3 FPGA Prototyping Board Technical Reference Manual (TRM)`_ + - `Cortex M55 Generic User Guide`_ + - `Cortex M85 Generic User Guide`_ + - `Corelink SSE-300 Example Subsystem`_ + - `Corelink SSE-310 Example Subsystem`_ .. _Corstone-300 FVP: https://developer.arm.com/tools-and-software/open-source-software/arm-platforms-software/arm-ecosystem-fvps +.. _Corstone-310 FVP: + https://developer.arm.com/tools-and-software/open-source-software/arm-platforms-software/arm-ecosystem-fvps + .. _MPS3 FPGA Website: https://developer.arm.com/tools-and-software/development-boards/fpga-prototyping-boards/mps3 .. _MPS3 AN547 Technical Reference Manual (TRM): https://developer.arm.com/-/media/Arm%20Developer%20Community/PDF/DAI0547B_SSE300_PLUS_U55_FPGA_for_mps3.pdf +.. _MPS3 AN552 Technical Reference Manual (TRM): + https://developer.arm.com/documentation/dai0552/latest + +.. _MPS3 AN555 Technical Reference Manual (TRM): + https://developer.arm.com/documentation/107642/latest + .. _MPS3 FPGA Prototyping Board Technical Reference Manual (TRM): https://developer.arm.com/documentation/100765/latest .. _Cortex M55 Generic User Guide: https://developer.arm.com/documentation/101051/latest +.. _Cortex M85 Generic User Guide: + https://developer.arm.com/documentation/101924/latest + .. _Corelink SSE-300 Example Subsystem: https://developer.arm.com/documentation/101772/latest + +.. _Corelink SSE-310 Example Subsystem: + https://developer.arm.com/documentation/102778/latest diff --git a/boards/arm/mps3/mps3_an547-common.dtsi b/boards/arm/mps3/mps3_an547-common.dtsi deleted file mode 100644 index 96147b0bd29..00000000000 --- a/boards/arm/mps3/mps3_an547-common.dtsi +++ /dev/null @@ -1,173 +0,0 @@ -/* - * Copyright (c) 2019-2021 Linaro Limited - * - * SPDX-License-Identifier: Apache-2.0 - */ - -sysclk: system-clock { - compatible = "fixed-clock"; - clock-frequency = <25000000>; - #clock-cells = <0>; -}; - -gpio0: gpio@1100000 { - compatible = "arm,cmsdk-gpio"; - reg = <0x1100000 0x1000>; - interrupts = <69 3>; - gpio-controller; - #gpio-cells = <2>; -}; - -gpio1: gpio@1101000 { - compatible = "arm,cmsdk-gpio"; - reg = <0x1101000 0x1000>; - interrupts = <70 3>; - gpio-controller; - #gpio-cells = <2>; -}; - -gpio2: gpio@1102000 { - compatible = "arm,cmsdk-gpio"; - reg = <0x1102000 0x1000>; - interrupts = <71 3>; - gpio-controller; - #gpio-cells = <2>; -}; - -gpio3: gpio@1103000 { - compatible = "arm,cmsdk-gpio"; - reg = <0x1103000 0x1000>; - interrupts = <72 3>; - gpio-controller; - #gpio-cells = <2>; -}; - -eth0: eth@1400000 { - /* Linux has "smsc,lan9115" */ - compatible = "smsc,lan9220"; - /* Actual reg range is ~0x200 */ - reg = <0x1400000 0x100000>; - interrupts = <49 3>; -}; - -i2c_touch: i2c@9200000 { - compatible = "arm,versatile-i2c"; - clock-frequency = ; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x9200000 0x1000>; -}; - -i2c_audio_conf: i2c@9201000 { - compatible = "arm,versatile-i2c"; - clock-frequency = ; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x9201000 0x1000>; -}; - -i2c_shield0: i2c@9203000 { - compatible = "arm,versatile-i2c"; - clock-frequency = ; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x9203000 0x1000>; -}; - -i2c_shield1: i2c@9204000 { - compatible = "arm,versatile-i2c"; - clock-frequency = ; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x9204000 0x1000>; -}; - -i2c_ddr4_eeprom: i2c@9208000 { - compatible = "arm,versatile-i2c"; - clock-frequency = ; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x9208000 0x1000>; -}; - -gpio_led0: mps3_fpgaio@9302000 { - compatible = "arm,mps3-fpgaio-gpio"; - - reg = <0x9302000 0x4>; - gpio-controller; - #gpio-cells = <1>; - ngpios = <8>; -}; - -gpio_button: mps3_fpgaio@9302008 { - compatible = "arm,mps3-fpgaio-gpio"; - - reg = <0x9302008 0x4>; - gpio-controller; - #gpio-cells = <1>; - ngpios = <2>; -}; - -gpio_misc: mps3_fpgaio@930204c { - compatible = "arm,mps3-fpgaio-gpio"; - - reg = <0x930204c 0x4>; - gpio-controller; - #gpio-cells = <1>; - ngpios = <3>; -}; - -uart0: uart@9303000 { - compatible = "arm,cmsdk-uart"; - reg = <0x9303000 0x1000>; - interrupts = <34 3 33 3>; - interrupt-names = "tx", "rx"; - clocks = <&sysclk>; - current-speed = <115200>; -}; - -uart1: uart@9304000 { - compatible = "arm,cmsdk-uart"; - reg = <0x9304000 0x1000>; - interrupts = <36 3 35 3>; - interrupt-names = "tx", "rx"; - clocks = <&sysclk>; - current-speed = <115200>; -}; - -uart2: uart@9305000 { - compatible = "arm,cmsdk-uart"; - reg = <0x9305000 0x1000>; - interrupts = <38 3 37 3>; - interrupt-names = "tx", "rx"; - clocks = <&sysclk>; - current-speed = <115200>; -}; - -uart3: uart@9306000 { - compatible = "arm,cmsdk-uart"; - reg = <0x9306000 0x1000>; - interrupts = <40 3 39 3>; - interrupt-names = "tx", "rx"; - clocks = <&sysclk>; - current-speed = <115200>; -}; - -uart4: uart@9307000 { - compatible = "arm,cmsdk-uart"; - reg = <0x9307000 0x1000>; - interrupts = <42 3 41 3>; - interrupt-names = "tx", "rx"; - clocks = <&sysclk>; - current-speed = <115200>; -}; - -uart5: uart@9308000 { - compatible = "arm,cmsdk-uart"; - status = "disabled"; - reg = <0x9308000 0x1000>; - interrupt-names = "tx", "rx"; - interrupts = <126 3 125 3>; - clocks = <&sysclk>; - current-speed = <115200>; -}; diff --git a/boards/arm/mps3/mps3_an547.dts b/boards/arm/mps3/mps3_an547.dts deleted file mode 100644 index 8b6585a13e2..00000000000 --- a/boards/arm/mps3/mps3_an547.dts +++ /dev/null @@ -1,180 +0,0 @@ -/* - * Copyright (c) 2018-2021 Linaro Limited - * Copyright 2022 Arm Limited and/or its affiliates - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include -#include -#include -#include - -/ { - compatible = "arm,mps3-an547"; - #address-cells = <1>; - #size-cells = <1>; - - aliases { - led0 = &led_0; - led1 = &led_1; - sw0 = &user_button_0; - sw1 = &user_button_1; - }; - - chosen { - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - zephyr,sram = &dtcm; - zephyr,flash = &itcm; - }; - - leds { - compatible = "gpio-leds"; - led_0: led_0 { - gpios = <&gpio_led0 0>; - label = "USERLED0"; - }; - led_1: led_1 { - gpios = <&gpio_led0 1>; - label = "USERLED1"; - }; - led_2: led_2 { - gpios = <&gpio_led0 2>; - label = "USERLED2"; - }; - led_3: led_3 { - gpios = <&gpio_led0 3>; - label = "USERLED3"; - }; - led_4: led_4 { - gpios = <&gpio_led0 4>; - label = "USERLED4"; - }; - led_5: led_5 { - gpios = <&gpio_led0 5>; - label = "USERLED5"; - }; - led_6: led_6 { - gpios = <&gpio_led0 6>; - label = "USERLED6"; - }; - led_7: led_7 { - gpios = <&gpio_led0 7>; - label = "USERLED7"; - }; - led_8: led_8 { - gpios = <&gpio_led0 8>; - label = "PB1LED"; - }; - led_9: led_9 { - gpios = <&gpio_led0 9>; - label = "PB2LED"; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - user_button_0: button_0 { - label = "USERPB0"; - gpios = <&gpio_button 0>; - zephyr,code = ; - }; - user_button_1: button_1 { - label = "USERPB1"; - gpios = <&gpio_button 1>; - zephyr,code = ; - }; - }; - - ethosu { - #address-cells = <1>; - #size-cells = <0>; - interrupt-parent = <&nvic>; - - ethosu0: ethosu@48102000 { - compatible = "arm,ethos-u"; - reg = <0x48102000>; - interrupts = <56 3>; - secure-enable; - privilege-enable; - status = "okay"; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-m55"; - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - - mpu: mpu@e000ed90 { - compatible = "arm,armv8.1m-mpu"; - reg = <0xe000ed90 0x40>; - }; - }; - }; - - /* We utilize the secure addresses, if you subtract 0x10000000 - * you'll get the non-secure alias - */ - itcm: itcm@10000000 { /* alias @ 0x0 */ - compatible = "zephyr,memory-region"; - reg = <0x10000000 DT_SIZE_K(512)>; - zephyr,memory-region = "ITCM"; - }; - - sram: sram@11000000 { /* alias @ 0x01000000 */ - compatible = "zephyr,memory-region", "mmio-sram"; - reg = <0x11000000 DT_SIZE_M(2)>; - zephyr,memory-region = "SRAM"; - }; - - dtcm: dtcm@30000000 { /* alias @ 0x20000000 */ - compatible = "zephyr,memory-region"; - reg = <0x30000000 DT_SIZE_K(512)>; - zephyr,memory-region = "DTCM"; - }; - - isram: sram@31000000 {/* alias @ 0x21000000 */ - compatible = "zephyr,memory-region", "mmio-sram"; - reg = <0x31000000 DT_SIZE_M(4)>; - zephyr,memory-region = "ISRAM"; - }; - - /* DDR4 - 2G, alternates non-secure/secure every 256M */ - ddr4: memory@60000000 { - device_type = "memory"; - compatible = "zephyr,memory-region"; - reg = <0x60000000 DT_SIZE_M(256) - 0x70000000 DT_SIZE_M(256) - 0x80000000 DT_SIZE_M(256) - 0x90000000 DT_SIZE_M(256) - 0xa0000000 DT_SIZE_M(256) - 0xb0000000 DT_SIZE_M(256) - 0xc0000000 DT_SIZE_M(256) - 0xd0000000 DT_SIZE_M(256)>; - zephyr,memory-region = "DDR4"; - }; - - soc { - peripheral@50000000 { - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x50000000 0x10000000>; - - #include "mps3_an547-common.dtsi" - }; - }; -}; - -&nvic { - arm,num-irq-priority-bits = <3>; -}; diff --git a/boards/arm/mps3/mps3_an547.yaml b/boards/arm/mps3/mps3_an547.yaml deleted file mode 100644 index 538fa24db67..00000000000 --- a/boards/arm/mps3/mps3_an547.yaml +++ /dev/null @@ -1,26 +0,0 @@ -# -# Copyright (c) 2019-2021 Linaro Limited -# -# SPDX-License-Identifier: Apache-2.0 -# - -identifier: mps3/an547 -name: Arm MPS3-AN547 -type: mcu -arch: arm -ram: 512 -flash: 512 -simulation: qemu -toolchain: - - gnuarmemb - - zephyr - - xtools -supported: - - gpio -testing: - ignore_tags: - - drivers - - bluetooth - - net - - timer -vendor: arm diff --git a/boards/arm/mps3/mps3_an547_defconfig b/boards/arm/mps3/mps3_an547_defconfig deleted file mode 100644 index 90c9b6a9f8e..00000000000 --- a/boards/arm/mps3/mps3_an547_defconfig +++ /dev/null @@ -1,21 +0,0 @@ -# -# Copyright (c) 2018-2021 Linaro Limited -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_RUNTIME_NMI=y -CONFIG_ARM_TRUSTZONE_M=y -CONFIG_ARM_MPU=y -CONFIG_QEMU_ICOUNT_SHIFT=7 - -# GPIOs -CONFIG_GPIO=y - -# Serial -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y - -# Build a Secure firmware image -CONFIG_TRUSTED_EXECUTION_SECURE=y diff --git a/boards/arm/mps3/mps3_an547_ns.dts b/boards/arm/mps3/mps3_an547_ns.dts deleted file mode 100644 index 1c6a0fc2605..00000000000 --- a/boards/arm/mps3/mps3_an547_ns.dts +++ /dev/null @@ -1,152 +0,0 @@ -/* - * Copyright (c) 2018-2021 Linaro Limited - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include -#include -#include -#include - -/ { - compatible = "arm,mps3-an547"; - #address-cells = <1>; - #size-cells = <1>; - - aliases { - led0 = &led_0; - led1 = &led_1; - sw0 = &user_button_0; - sw1 = &user_button_1; - }; - - chosen { - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - zephyr,sram = &ram; - zephyr,flash = &code; - }; - - leds { - compatible = "gpio-leds"; - led_0: led_0 { - gpios = <&gpio_led0 0>; - label = "USERLED0"; - }; - led_1: led_1 { - gpios = <&gpio_led0 1>; - label = "USERLED1"; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - user_button_0: button_0 { - label = "USERPB0"; - gpios = <&gpio_button 0>; - zephyr,code = ; - }; - user_button_1: button_1 { - label = "USERPB1"; - gpios = <&gpio_button 1>; - zephyr,code = ; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-m55"; - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - - mpu: mpu@e000ed90 { - compatible = "arm,armv8.1m-mpu"; - reg = <0xe000ed90 0x40>; - }; - }; - }; - - /* We utilize the secure addresses, if you subtract 0x10000000 - * you'll get the non-secure alias - */ - itcm: itcm@0 { - compatible = "zephyr,memory-region"; - reg = <0x0 DT_SIZE_K(512)>; - zephyr,memory-region = "ITCM"; - }; - - sram: sram@1000000 { - compatible = "zephyr,memory-region", "mmio-sram"; - reg = <0x1000000 DT_SIZE_M(2)>; - zephyr,memory-region = "SRAM"; - }; - - dtcm: dtcm@20000000 { - compatible = "zephyr,memory-region"; - reg = <0x20000000 DT_SIZE_K(512)>; - zephyr,memory-region = "DTCM"; - }; - - isram: sram@21000000 { - compatible = "zephyr,memory-region", "mmio-sram"; - reg = <0x21000000 DT_SIZE_M(4)>; - zephyr,memory-region = "ISRAM"; - }; - - /* DDR4 - 2G, alternates non-secure/secure every 256M */ - ddr4: memory@60000000 { - device_type = "memory"; - compatible = "zephyr,memory-region"; - reg = <0x60000000 DT_SIZE_M(256) - 0x70000000 DT_SIZE_M(256) - 0x80000000 DT_SIZE_M(256) - 0x90000000 DT_SIZE_M(256) - 0xa0000000 DT_SIZE_M(256) - 0xb0000000 DT_SIZE_M(256) - 0xc0000000 DT_SIZE_M(256) - 0xd0000000 DT_SIZE_M(256)>; - zephyr,memory-region = "DDR4"; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - /* The memory regions defined below must match what the TF-M - * project has defined for that board - a single image boot is - * assumed. Please see the memory layout in: - * https://git.trustedfirmware.org/TF-M/trusted-firmware-m.git/tree/platform/ext/target/mps3/an547/partition/flash_layout.h - */ - - code: memory@01060000 { - reg = <0x01060000 DT_SIZE_K(384)>; - }; - - ram: memory@21000000 { - reg = <0x21000000 DT_SIZE_M(2)>; - }; - }; - - soc { - peripheral@40000000 { - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x40000000 0x10000000>; - - #include "mps3_an547-common.dtsi" - }; - }; -}; - -&nvic { - arm,num-irq-priority-bits = <3>; -}; diff --git a/boards/arm/mps3/mps3_an547_ns.yaml b/boards/arm/mps3/mps3_an547_ns.yaml deleted file mode 100644 index e58f636b555..00000000000 --- a/boards/arm/mps3/mps3_an547_ns.yaml +++ /dev/null @@ -1,21 +0,0 @@ -# -# Copyright (c) 2019-2021 Linaro Limited -# -# SPDX-License-Identifier: Apache-2.0 -# - -identifier: mps3/an547/ns -name: Arm MPS3-AN547_ns -type: mcu -arch: arm -ram: 2048 -flash: 384 -simulation: qemu -toolchain: - - gnuarmemb - - zephyr - - xtools -testing: - default: true - only_tags: - - trusted-firmware-m diff --git a/boards/arm/mps3/mps3_an547_ns_defconfig b/boards/arm/mps3/mps3_an547_ns_defconfig deleted file mode 100644 index ccc25c35019..00000000000 --- a/boards/arm/mps3/mps3_an547_ns_defconfig +++ /dev/null @@ -1,22 +0,0 @@ -# -# Copyright (c) 2018-2021 Linaro Limited -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_ARM_TRUSTZONE_M=y -CONFIG_RUNTIME_NMI=y -CONFIG_ARM_MPU=y -CONFIG_QEMU_ICOUNT_SHIFT=6 - -# GPIOs -CONFIG_GPIO=y - -# Serial -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y - -# Build a Non-secure firmware image -CONFIG_TRUSTED_EXECUTION_SECURE=n -CONFIG_TRUSTED_EXECUTION_NONSECURE=y diff --git a/boards/arm/mps3/mps3_common.dtsi b/boards/arm/mps3/mps3_common.dtsi new file mode 100644 index 00000000000..798af263310 --- /dev/null +++ b/boards/arm/mps3/mps3_common.dtsi @@ -0,0 +1,106 @@ +/* + * Copyright 2024 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* /dts-v1/; */ + +#include +#include +#include +#include +#include + +/ { + aliases { + led0 = &led_0; + led1 = &led_1; + sw0 = &user_button_0; + sw1 = &user_button_1; + }; + + leds { + compatible = "gpio-leds"; + led_0: led_0 { + gpios = <&gpio_led0 0>; + label = "USERLED0"; + }; + led_1: led_1 { + gpios = <&gpio_led0 1>; + label = "USERLED1"; + }; + led_2: led_2 { + gpios = <&gpio_led0 2>; + label = "USERLED2"; + }; + led_3: led_3 { + gpios = <&gpio_led0 3>; + label = "USERLED3"; + }; + led_4: led_4 { + gpios = <&gpio_led0 4>; + label = "USERLED4"; + }; + led_5: led_5 { + gpios = <&gpio_led0 5>; + label = "USERLED5"; + }; + led_6: led_6 { + gpios = <&gpio_led0 6>; + label = "USERLED6"; + }; + led_7: led_7 { + gpios = <&gpio_led0 7>; + label = "USERLED7"; + }; + led_8: led_8 { + gpios = <&gpio_led0 8>; + label = "PB1LED"; + }; + led_9: led_9 { + gpios = <&gpio_led0 9>; + label = "PB2LED"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + user_button_0: button_0 { + label = "USERPB0"; + gpios = <&gpio_button 0>; + zephyr,code = ; + }; + user_button_1: button_1 { + label = "USERPB1"; + gpios = <&gpio_button 1>; + zephyr,code = ; + }; + }; + + null_ptr_detect: null_ptr_detect@0 { + compatible = "zephyr,memory-region"; + /* 0 - CONFIG_CORTEX_M_NULL_POINTER_EXCEPTION_PAGE_SIZE> */ + reg = <0x0 0x400>; + zephyr,memory-region = "NULL_PTR_DETECT"; + zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_FLASH) )>; + }; + /* DDR4 - 2G, alternates non-secure/secure every 256M */ + ddr4: memory@60000000 { + device_type = "memory"; + compatible = "zephyr,memory-region"; + reg = <0x60000000 DT_SIZE_M(256) + 0x70000000 DT_SIZE_M(256) + 0x80000000 DT_SIZE_M(256) + 0x90000000 DT_SIZE_M(256) + 0xa0000000 DT_SIZE_M(256) + 0xb0000000 DT_SIZE_M(256) + 0xc0000000 DT_SIZE_M(256) + 0xd0000000 DT_SIZE_M(256)>; + zephyr,memory-region = "DDR4"; + }; +}; + +&nvic { + arm,num-irq-priority-bits = <3>; +}; diff --git a/boards/arm/mps3/mps3_common_soc_peripheral.dtsi b/boards/arm/mps3/mps3_common_soc_peripheral.dtsi new file mode 100644 index 00000000000..6fd5c7acd40 --- /dev/null +++ b/boards/arm/mps3/mps3_common_soc_peripheral.dtsi @@ -0,0 +1,204 @@ +/* + * Copyright (c) 2019-2021 Linaro Limited + * Copyright 2024 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + */ + +sysclk: system-clock { + compatible = "fixed-clock"; + clock-frequency = <25000000>; + #clock-cells = <0>; +}; + +gpio0: gpio@1100000 { + compatible = "arm,cmsdk-gpio"; + reg = <0x1100000 0x1000>; + interrupts = <69 3>; + gpio-controller; + #gpio-cells = <2>; +}; + +gpio1: gpio@1101000 { + compatible = "arm,cmsdk-gpio"; + reg = <0x1101000 0x1000>; + interrupts = <70 3>; + gpio-controller; + #gpio-cells = <2>; +}; + +gpio2: gpio@1102000 { + compatible = "arm,cmsdk-gpio"; + reg = <0x1102000 0x1000>; + interrupts = <71 3>; + gpio-controller; + #gpio-cells = <2>; +}; + +gpio3: gpio@1103000 { + compatible = "arm,cmsdk-gpio"; + reg = <0x1103000 0x1000>; + interrupts = <72 3>; + gpio-controller; + #gpio-cells = <2>; +}; + +eth0: eth@1400000 { + /* Linux has "smsc,lan9115" */ + compatible = "smsc,lan9220"; + /* Actual reg range is ~0x200 */ + reg = <0x1400000 0x100000>; + interrupts = <49 3>; +}; + +i2c_touch: i2c@9200000 { + compatible = "arm,versatile-i2c"; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x9200000 0x1000>; +}; + +i2c_audio_conf: i2c@9201000 { + compatible = "arm,versatile-i2c"; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x9201000 0x1000>; +}; + +spi_adc: spi@9202000 { + compatible = "arm,pl022"; + reg = <0x9202000 DT_SIZE_K(4)>; + interrupts = <53 3>; + interrupt-names = "shield_adc"; + clocks = <&sysclk>; + #address-cells = <1>; + #size-cells = <0>; +}; + +spi_shield0: spi@9203000 { + compatible = "arm,pl022"; + reg = <0x9203000 DT_SIZE_K(4)>; + interrupts = <54 3>; + interrupt-names = "shield0_spi"; + clocks = <&sysclk>; + #address-cells = <1>; + #size-cells = <0>; +}; + +spi_shield1: spi@9204000 { + compatible = "arm,pl022"; + reg = <0x9204000 DT_SIZE_K(4)>; + interrupts = <55 3>; + interrupt-names = "shield1_spi"; + clocks = <&sysclk>; + #address-cells = <1>; + #size-cells = <0>; +}; + +i2c_shield0: i2c@9205000 { + compatible = "arm,versatile-i2c"; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x9205000 0x1000>; +}; + +i2c_shield1: i2c@9206000 { + compatible = "arm,versatile-i2c"; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x9206000 0x1000>; +}; + +i2c_ddr4_eeprom: i2c@9208000 { + compatible = "arm,versatile-i2c"; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x9208000 0x1000>; +}; + +gpio_led0: mps3_fpgaio@9302000 { + compatible = "arm,mps3-fpgaio-gpio"; + + reg = <0x9302000 0x4>; + gpio-controller; + #gpio-cells = <1>; + ngpios = <8>; +}; + +gpio_button: mps3_fpgaio@9302008 { + compatible = "arm,mps3-fpgaio-gpio"; + + reg = <0x9302008 0x4>; + gpio-controller; + #gpio-cells = <1>; + ngpios = <2>; +}; + +gpio_misc: mps3_fpgaio@930204c { + compatible = "arm,mps3-fpgaio-gpio"; + + reg = <0x930204c 0x4>; + gpio-controller; + #gpio-cells = <1>; + ngpios = <3>; +}; + +uart0: uart@9303000 { + compatible = "arm,cmsdk-uart"; + reg = <0x9303000 0x1000>; + interrupts = <34 3 33 3>; + interrupt-names = "tx", "rx"; + clocks = <&sysclk>; + current-speed = <115200>; +}; + +uart1: uart@9304000 { + compatible = "arm,cmsdk-uart"; + reg = <0x9304000 0x1000>; + interrupts = <36 3 35 3>; + interrupt-names = "tx", "rx"; + clocks = <&sysclk>; + current-speed = <115200>; +}; + +uart2: uart@9305000 { + compatible = "arm,cmsdk-uart"; + reg = <0x9305000 0x1000>; + interrupts = <38 3 37 3>; + interrupt-names = "tx", "rx"; + clocks = <&sysclk>; + current-speed = <115200>; +}; + +uart3: uart@9306000 { + compatible = "arm,cmsdk-uart"; + reg = <0x9306000 0x1000>; + interrupts = <40 3 39 3>; + interrupt-names = "tx", "rx"; + clocks = <&sysclk>; + current-speed = <115200>; +}; + +uart4: uart@9307000 { + compatible = "arm,cmsdk-uart"; + reg = <0x9307000 0x1000>; + interrupts = <42 3 41 3>; + interrupt-names = "tx", "rx"; + clocks = <&sysclk>; + current-speed = <115200>; +}; + +uart5: uart@9308000 { + compatible = "arm,cmsdk-uart"; + status = "disabled"; + reg = <0x9308000 0x1000>; + interrupt-names = "tx", "rx"; + interrupts = <126 3 125 3>; + clocks = <&sysclk>; + current-speed = <115200>; +}; diff --git a/boards/arm/mps3/mps3_corstone300_an547.dts b/boards/arm/mps3/mps3_corstone300_an547.dts new file mode 100644 index 00000000000..ae71ddf7282 --- /dev/null +++ b/boards/arm/mps3/mps3_corstone300_an547.dts @@ -0,0 +1,97 @@ +/* + * Copyright (c) 2018-2021 Linaro Limited + * Copyright 2024 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include +#include +#include "mps3_common.dtsi" + +/ { + compatible = "arm,mps3-an547"; + #address-cells = <1>; + #size-cells = <1>; + + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,sram = &dtcm; + zephyr,flash = &itcm; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-m55"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + + mpu: mpu@e000ed90 { + compatible = "arm,armv8.1m-mpu"; + reg = <0xe000ed90 0x40>; + }; + }; + }; + + ethosu { + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&nvic>; + + ethosu0: ethosu@48102000 { + compatible = "arm,ethos-u"; + reg = <0x48102000>; + interrupts = <56 3>; + secure-enable; + privilege-enable; + status = "okay"; + }; + }; + + /* We utilize the secure addresses, if you subtract 0x10000000 + * you'll get the non-secure alias + */ + itcm: itcm@10000000 { /* alias @ 0x0 */ + compatible = "zephyr,memory-region"; + reg = <0x10000000 DT_SIZE_K(512)>; + zephyr,memory-region = "ITCM"; + }; + + sram: sram@11000000 { /* alias @ 0x01000000 */ + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0x11000000 DT_SIZE_M(2)>; + zephyr,memory-region = "SRAM"; + }; + + dtcm: dtcm@30000000 { /* alias @ 0x20000000 */ + compatible = "zephyr,memory-region"; + reg = <0x30000000 DT_SIZE_K(512)>; + zephyr,memory-region = "DTCM"; + }; + + isram: sram@31000000 {/* alias @ 0x21000000 */ + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0x31000000 DT_SIZE_M(4)>; + zephyr,memory-region = "ISRAM"; + }; + + soc { + peripheral@50000000 { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x50000000 0x10000000>; + + #include "mps3_common_soc_peripheral.dtsi" + }; + }; +}; diff --git a/boards/arm/mps3/mps3_corstone300_an547.yaml b/boards/arm/mps3/mps3_corstone300_an547.yaml new file mode 100644 index 00000000000..87a7100ed37 --- /dev/null +++ b/boards/arm/mps3/mps3_corstone300_an547.yaml @@ -0,0 +1,29 @@ +# +# Copyright (c) 2019-2021 Linaro Limited +# Copyright 2024 Arm Limited and/or its affiliates +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: mps3/corstone300/an547 +name: Arm MPS3-Corstone300-AN547 +type: mcu +arch: arm +ram: 512 +flash: 512 +simulation: + - name: qemu + - name: armfvp +toolchain: + - gnuarmemb + - zephyr + - xtools +supported: + - gpio +testing: + ignore_tags: + - drivers + - bluetooth + - net + - timer +vendor: arm diff --git a/boards/arm/mps3/mps3_corstone300_an547_defconfig b/boards/arm/mps3/mps3_corstone300_an547_defconfig new file mode 100644 index 00000000000..2d4a9af56ae --- /dev/null +++ b/boards/arm/mps3/mps3_corstone300_an547_defconfig @@ -0,0 +1,22 @@ +# +# Copyright (c) 2018-2021 Linaro Limited +# Copyright 2024 Arm Limited and/or its affiliates +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_RUNTIME_NMI=y +CONFIG_ARM_TRUSTZONE_M=y +CONFIG_ARM_MPU=y +CONFIG_QEMU_ICOUNT_SHIFT=7 + +# GPIOs +CONFIG_GPIO=y + +# Serial +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y + +# Build a Secure firmware image +CONFIG_TRUSTED_EXECUTION_SECURE=y diff --git a/boards/arm/mps3/mps3_corstone300_an547_ns.dts b/boards/arm/mps3/mps3_corstone300_an547_ns.dts new file mode 100644 index 00000000000..5a4e0031946 --- /dev/null +++ b/boards/arm/mps3/mps3_corstone300_an547_ns.dts @@ -0,0 +1,102 @@ +/* + * Copyright (c) 2018-2021 Linaro Limited + * Copyright 2024 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include +#include +#include "mps3_common.dtsi" + +/ { + compatible = "arm,mps3-an547"; + #address-cells = <1>; + #size-cells = <1>; + + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,sram = &ram; + zephyr,flash = &code; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-m55"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + + mpu: mpu@e000ed90 { + compatible = "arm,armv8.1m-mpu"; + reg = <0xe000ed90 0x40>; + }; + }; + }; + + /* We utilize the secure addresses, if you subtract 0x10000000 + * you'll get the non-secure alias + */ + itcm: itcm@0 { + compatible = "zephyr,memory-region"; + reg = <0x0 DT_SIZE_K(512)>; + zephyr,memory-region = "ITCM"; + }; + + sram: sram@1000000 { + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0x1000000 DT_SIZE_M(2)>; + zephyr,memory-region = "SRAM"; + }; + + dtcm: dtcm@20000000 { + compatible = "zephyr,memory-region"; + reg = <0x20000000 DT_SIZE_K(512)>; + zephyr,memory-region = "DTCM"; + }; + + isram: sram@21000000 { + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0x21000000 DT_SIZE_M(4)>; + zephyr,memory-region = "ISRAM"; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* The memory regions defined below must match what the TF-M + * project has defined for that board - a single image boot is + * assumed. Please see the memory layout in: + * https://git.trustedfirmware.org/TF-M/trusted-firmware-m.git/tree/platform/ext/target/mps3/corstone300/common/partition/flash_layout.h + */ + + code: memory@28080000 { + reg = <0x28080000 DT_SIZE_K(512)>; + }; + + ram: memory@21020000 { + reg = <0x21020000 DT_SIZE_M(2)>; + }; + }; + + soc { + peripheral@40000000 { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x40000000 0x10000000>; + + #include "mps3_common_soc_peripheral.dtsi" + }; + }; +}; diff --git a/boards/arm/mps3/mps3_corstone300_an547_ns.yaml b/boards/arm/mps3/mps3_corstone300_an547_ns.yaml new file mode 100644 index 00000000000..3efa3da5de6 --- /dev/null +++ b/boards/arm/mps3/mps3_corstone300_an547_ns.yaml @@ -0,0 +1,23 @@ +# +# Copyright (c) 2019-2021 Linaro Limited +# Copyright 2024 Arm Limited and/or its affiliates +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: mps3/corstone300/an547/ns +name: Arm MPS3-Corstone300-AN547_ns +type: mcu +arch: arm +ram: 2048 +flash: 512 +simulation: + - name: qemu +toolchain: + - gnuarmemb + - zephyr + - xtools +testing: + default: true + only_tags: + - trusted-firmware-m diff --git a/boards/arm/mps3/mps3_corstone300_an547_ns_defconfig b/boards/arm/mps3/mps3_corstone300_an547_ns_defconfig new file mode 100644 index 00000000000..37a0b3827f0 --- /dev/null +++ b/boards/arm/mps3/mps3_corstone300_an547_ns_defconfig @@ -0,0 +1,23 @@ +# +# Copyright (c) 2018-2021 Linaro Limited +# Copyright 2024 Arm Limited and/or its affiliates +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_ARM_TRUSTZONE_M=y +CONFIG_RUNTIME_NMI=y +CONFIG_ARM_MPU=y +CONFIG_QEMU_ICOUNT_SHIFT=6 + +# GPIOs +CONFIG_GPIO=y + +# Serial +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y + +# Build a Non-secure firmware image +CONFIG_TRUSTED_EXECUTION_SECURE=n +CONFIG_TRUSTED_EXECUTION_NONSECURE=y diff --git a/boards/arm/mps3/mps3_corstone300_an552.dts b/boards/arm/mps3/mps3_corstone300_an552.dts new file mode 100644 index 00000000000..7c7ec8d02a5 --- /dev/null +++ b/boards/arm/mps3/mps3_corstone300_an552.dts @@ -0,0 +1,96 @@ +/* + * Copyright 2024 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include +#include +#include "mps3_common.dtsi" + +/ { + compatible = "arm,mps3-an552"; + #address-cells = <1>; + #size-cells = <1>; + + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,sram = &dtcm; + zephyr,flash = &itcm; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-m55"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + + mpu: mpu@e000ed90 { + compatible = "arm,armv8.1m-mpu"; + reg = <0xe000ed90 0x40>; + }; + }; + }; + + ethosu { + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&nvic>; + + ethosu0: ethosu@48102000 { + compatible = "arm,ethos-u"; + reg = <0x48102000>; + interrupts = <56 3>; + secure-enable; + privilege-enable; + status = "okay"; + }; + }; + + /* We utilize the secure addresses, if you subtract 0x10000000 + * you'll get the non-secure alias + */ + itcm: itcm@10000000 { /* alias @ 0x0 */ + compatible = "zephyr,memory-region"; + reg = <0x10000000 DT_SIZE_K(512)>; + zephyr,memory-region = "ITCM"; + }; + + sram: sram@11000000 { /* alias @ 0x01000000 */ + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0x11000000 DT_SIZE_M(1)>; + zephyr,memory-region = "SRAM"; + }; + + dtcm: dtcm@30000000 { /* alias @ 0x20000000 */ + compatible = "zephyr,memory-region"; + reg = <0x30000000 DT_SIZE_K(512)>; + zephyr,memory-region = "DTCM"; + }; + + isram: sram@31000000 {/* alias @ 0x21000000 */ + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0x31000000 DT_SIZE_M(2)>; + zephyr,memory-region = "ISRAM"; + }; + + soc { + peripheral@50000000 { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x50000000 0x10000000>; + + #include "mps3_common_soc_peripheral.dtsi" + }; + }; +}; diff --git a/boards/arm/mps3/mps3_corstone300_an552.yaml b/boards/arm/mps3/mps3_corstone300_an552.yaml new file mode 100644 index 00000000000..ecabe715085 --- /dev/null +++ b/boards/arm/mps3/mps3_corstone300_an552.yaml @@ -0,0 +1,22 @@ +# Copyright 2024 Arm Limited and/or its affiliates +# SPDX-License-Identifier: Apache-2.0 + +identifier: mps3/corstone300/an552 +name: Arm MPS3-Corstone300-AN552 +type: mcu +arch: arm +ram: 512 +flash: 512 +toolchain: + - gnuarmemb + - zephyr + - xtools +supported: + - gpio +testing: + ignore_tags: + - drivers + - bluetooth + - net + - timer +vendor: arm diff --git a/boards/arm/mps3/mps3_corstone300_an552_defconfig b/boards/arm/mps3/mps3_corstone300_an552_defconfig new file mode 100644 index 00000000000..f5607f3da4c --- /dev/null +++ b/boards/arm/mps3/mps3_corstone300_an552_defconfig @@ -0,0 +1,17 @@ +# Copyright 2024 Arm Limited and/or its affiliates +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_RUNTIME_NMI=y +CONFIG_ARM_TRUSTZONE_M=y +CONFIG_ARM_MPU=y + +# GPIOs +CONFIG_GPIO=y + +# Serial +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y + +# Build a Secure firmware image +CONFIG_TRUSTED_EXECUTION_SECURE=y diff --git a/boards/arm/mps3/mps3_corstone300_an552_ns.dts b/boards/arm/mps3/mps3_corstone300_an552_ns.dts new file mode 100644 index 00000000000..17e9d259bca --- /dev/null +++ b/boards/arm/mps3/mps3_corstone300_an552_ns.dts @@ -0,0 +1,101 @@ +/* + * Copyright 2024 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include +#include +#include "mps3_common.dtsi" + +/ { + compatible = "arm,mps3-an552"; + #address-cells = <1>; + #size-cells = <1>; + + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,sram = &ram; + zephyr,flash = &code; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-m55"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + + mpu: mpu@e000ed90 { + compatible = "arm,armv8.1m-mpu"; + reg = <0xe000ed90 0x40>; + }; + }; + }; + + /* We utilize the secure addresses, if you subtract 0x10000000 + * you'll get the non-secure alias + */ + itcm: itcm@0 { + compatible = "zephyr,memory-region"; + reg = <0x0 DT_SIZE_K(512)>; + zephyr,memory-region = "ITCM"; + }; + + sram: sram@1000000 { + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0x1000000 DT_SIZE_M(1)>; + zephyr,memory-region = "SRAM"; + }; + + dtcm: dtcm@20000000 { + compatible = "zephyr,memory-region"; + reg = <0x20000000 DT_SIZE_K(512)>; + zephyr,memory-region = "DTCM"; + }; + + isram: sram@21000000 { + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0x21000000 DT_SIZE_M(2)>; + zephyr,memory-region = "ISRAM"; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* The memory regions defined below must match what the TF-M + * project has defined for that board - a single image boot is + * assumed. Please see the memory layout in: + * https://git.trustedfirmware.org/TF-M/trusted-firmware-m.git/tree/platform/ext/target/mps3/corstone300/common/partition/flash_layout.h + */ + + code: memory@28080000 { + reg = <0x28080000 DT_SIZE_K(512)>; + }; + + ram: memory@21020000 { + reg = <0x21020000 DT_SIZE_M(1)>; + }; + }; + + soc { + peripheral@40000000 { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x40000000 0x10000000>; + + #include "mps3_common_soc_peripheral.dtsi" + }; + }; +}; diff --git a/boards/arm/mps3/mps3_corstone300_an552_ns.yaml b/boards/arm/mps3/mps3_corstone300_an552_ns.yaml new file mode 100644 index 00000000000..b8a914a5725 --- /dev/null +++ b/boards/arm/mps3/mps3_corstone300_an552_ns.yaml @@ -0,0 +1,17 @@ +# Copyright 2024 Arm Limited and/or its affiliates +# SPDX-License-Identifier: Apache-2.0 + +identifier: mps3/corstone300/an552/ns +name: Arm MPS3-Corstone300-AN552_ns +type: mcu +arch: arm +ram: 2048 +flash: 512 +toolchain: + - gnuarmemb + - zephyr + - xtools +testing: + default: true + only_tags: + - trusted-firmware-m diff --git a/boards/arm/mps3/mps3_corstone300_an552_ns_defconfig b/boards/arm/mps3/mps3_corstone300_an552_ns_defconfig new file mode 100644 index 00000000000..c9cfdd8950b --- /dev/null +++ b/boards/arm/mps3/mps3_corstone300_an552_ns_defconfig @@ -0,0 +1,18 @@ +# Copyright 2024 Arm Limited and/or its affiliates +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_RUNTIME_NMI=y +CONFIG_ARM_TRUSTZONE_M=y +CONFIG_ARM_MPU=y + +# GPIOs +CONFIG_GPIO=y + +# Serial +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y + +# Build a Non-secure firmware image +CONFIG_TRUSTED_EXECUTION_SECURE=n +CONFIG_TRUSTED_EXECUTION_NONSECURE=y diff --git a/boards/arm/mps3/mps3_corstone300_fvp.dts b/boards/arm/mps3/mps3_corstone300_fvp.dts new file mode 100644 index 00000000000..eff11378c61 --- /dev/null +++ b/boards/arm/mps3/mps3_corstone300_fvp.dts @@ -0,0 +1,96 @@ +/* + * Copyright 2024 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include +#include +#include "mps3_common.dtsi" + +/ { + compatible = "arm,mps3-fvp"; + #address-cells = <1>; + #size-cells = <1>; + + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,sram = &dtcm; + zephyr,flash = &itcm; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-m55"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + + mpu: mpu@e000ed90 { + compatible = "arm,armv8.1m-mpu"; + reg = <0xe000ed90 0x40>; + }; + }; + }; + + ethosu { + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&nvic>; + + ethosu0: ethosu@48102000 { + compatible = "arm,ethos-u"; + reg = <0x48102000>; + interrupts = <56 3>; + secure-enable; + privilege-enable; + status = "okay"; + }; + }; + + /* We utilize the secure addresses, if you subtract 0x10000000 + * you'll get the non-secure alias + */ + itcm: itcm@10000000 { /* alias @ 0x0 */ + compatible = "zephyr,memory-region"; + reg = <0x10000000 DT_SIZE_K(512)>; + zephyr,memory-region = "ITCM"; + }; + + sram: sram@11000000 { /* alias @ 0x01000000 */ + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0x11000000 DT_SIZE_M(1)>; + zephyr,memory-region = "SRAM"; + }; + + dtcm: dtcm@30000000 { /* alias @ 0x20000000 */ + compatible = "zephyr,memory-region"; + reg = <0x30000000 DT_SIZE_K(512)>; + zephyr,memory-region = "DTCM"; + }; + + isram: sram@31000000 {/* alias @ 0x21000000 */ + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0x31000000 DT_SIZE_M(2)>; + zephyr,memory-region = "ISRAM"; + }; + + soc { + peripheral@50000000 { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x50000000 0x10000000>; + + #include "mps3_common_soc_peripheral.dtsi" + }; + }; +}; diff --git a/boards/arm/mps3/mps3_corstone300_fvp.yaml b/boards/arm/mps3/mps3_corstone300_fvp.yaml new file mode 100644 index 00000000000..3d850b7f4ea --- /dev/null +++ b/boards/arm/mps3/mps3_corstone300_fvp.yaml @@ -0,0 +1,25 @@ +# Copyright 2024 Arm Limited and/or its affiliates +# SPDX-License-Identifier: Apache-2.0 + +identifier: mps3/corstone300/fvp +name: Arm MPS3-Corstone300-FVP +type: mcu +arch: arm +ram: 512 +flash: 512 +simulation: + - name: armfvp + exec: FVP_Corstone_SSE-300_Ethos-U55 +toolchain: + - gnuarmemb + - zephyr + - xtools +supported: + - gpio +testing: + ignore_tags: + - drivers + - bluetooth + - net + - timer +vendor: arm diff --git a/boards/arm/mps3/mps3_corstone300_fvp_defconfig b/boards/arm/mps3/mps3_corstone300_fvp_defconfig new file mode 100644 index 00000000000..f5607f3da4c --- /dev/null +++ b/boards/arm/mps3/mps3_corstone300_fvp_defconfig @@ -0,0 +1,17 @@ +# Copyright 2024 Arm Limited and/or its affiliates +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_RUNTIME_NMI=y +CONFIG_ARM_TRUSTZONE_M=y +CONFIG_ARM_MPU=y + +# GPIOs +CONFIG_GPIO=y + +# Serial +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y + +# Build a Secure firmware image +CONFIG_TRUSTED_EXECUTION_SECURE=y diff --git a/boards/arm/mps3/mps3_corstone300_fvp_ns.dts b/boards/arm/mps3/mps3_corstone300_fvp_ns.dts new file mode 100644 index 00000000000..8a9704cae3a --- /dev/null +++ b/boards/arm/mps3/mps3_corstone300_fvp_ns.dts @@ -0,0 +1,101 @@ +/* + * Copyright 2024 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include +#include +#include "mps3_common.dtsi" + +/ { + compatible = "arm,mps3-fvp"; + #address-cells = <1>; + #size-cells = <1>; + + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,sram = &ram; + zephyr,flash = &code; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-m55"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + + mpu: mpu@e000ed90 { + compatible = "arm,armv8.1m-mpu"; + reg = <0xe000ed90 0x40>; + }; + }; + }; + + /* We utilize the secure addresses, if you subtract 0x10000000 + * you'll get the non-secure alias + */ + itcm: itcm@0 { + compatible = "zephyr,memory-region"; + reg = <0x0 DT_SIZE_K(512)>; + zephyr,memory-region = "ITCM"; + }; + + sram: sram@1000000 { + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0x1000000 DT_SIZE_M(1)>; + zephyr,memory-region = "SRAM"; + }; + + dtcm: dtcm@20000000 { + compatible = "zephyr,memory-region"; + reg = <0x20000000 DT_SIZE_K(512)>; + zephyr,memory-region = "DTCM"; + }; + + isram: sram@21000000 { + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0x21000000 DT_SIZE_M(2)>; + zephyr,memory-region = "ISRAM"; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* The memory regions defined below must match what the TF-M + * project has defined for that board - a single image boot is + * assumed. Please see the memory layout in: + * https://git.trustedfirmware.org/TF-M/trusted-firmware-m.git/tree/platform/ext/target/mps3/corstone300/common/partition/flash_layout.h + */ + + code: memory@28080000 { + reg = <0x28080000 DT_SIZE_K(512)>; + }; + + ram: memory@21020000 { + reg = <0x21020000 DT_SIZE_M(1)>; + }; + }; + + soc { + peripheral@40000000 { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x40000000 0x10000000>; + + #include "mps3_common_soc_peripheral.dtsi" + }; + }; +}; diff --git a/boards/arm/mps3/mps3_corstone300_fvp_ns.yaml b/boards/arm/mps3/mps3_corstone300_fvp_ns.yaml new file mode 100644 index 00000000000..0802a129434 --- /dev/null +++ b/boards/arm/mps3/mps3_corstone300_fvp_ns.yaml @@ -0,0 +1,19 @@ +# Copyright 2024 Arm Limited and/or its affiliates +# SPDX-License-Identifier: Apache-2.0 + +identifier: mps3/corstone300/fvp/ns +name: Arm MPS3-Corstone300-FVP_ns +type: mcu +arch: arm +ram: 2048 +flash: 512 +# Related issue #81656 +twister: false +toolchain: + - gnuarmemb + - zephyr + - xtools +testing: + default: true + only_tags: + - trusted-firmware-m diff --git a/boards/arm/mps3/mps3_corstone300_fvp_ns_defconfig b/boards/arm/mps3/mps3_corstone300_fvp_ns_defconfig new file mode 100644 index 00000000000..1aca4a4abc4 --- /dev/null +++ b/boards/arm/mps3/mps3_corstone300_fvp_ns_defconfig @@ -0,0 +1,20 @@ +# Copyright 2024 Arm Limited and/or its affiliates +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_RUNTIME_NMI=y +CONFIG_ARM_TRUSTZONE_M=y +CONFIG_ARM_MPU=y + +# GPIOs +CONFIG_GPIO=y + +# Serial +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y + +# Build a Non-secure firmware image +CONFIG_TRUSTED_EXECUTION_SECURE=n +CONFIG_TRUSTED_EXECUTION_NONSECURE=y + +CONFIG_BUILD_WITH_TFM=y diff --git a/boards/arm/mps3/mps3_corstone310_an555.dts b/boards/arm/mps3/mps3_corstone310_an555.dts new file mode 100644 index 00000000000..f16aff58eae --- /dev/null +++ b/boards/arm/mps3/mps3_corstone310_an555.dts @@ -0,0 +1,96 @@ +/* + * Copyright 2024 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include +#include +#include "mps3_common.dtsi" + +/ { + compatible = "arm,mps3-an555"; + #address-cells = <1>; + #size-cells = <1>; + + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,sram = &dtcm; + zephyr,flash = &itcm; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-m85"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + + mpu: mpu@e000ed90 { + compatible = "arm,armv8.1m-mpu"; + reg = <0xe000ed90 0x40>; + }; + }; + }; + + ethosu { + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&nvic>; + + ethosu0: ethosu@50004000 { + compatible = "arm,ethos-u"; + reg = <0x50004000>; + interrupts = <16 3>; + secure-enable; + privilege-enable; + status = "okay"; + }; + }; + + /* We utilize the secure addresses, if you subtract 0x10000000 + * you'll get the non-secure alias + */ + itcm: itcm@10000000 { /* alias @ 0x0 */ + compatible = "zephyr,memory-region"; + reg = <0x10000000 DT_SIZE_K(32)>; + zephyr,memory-region = "ITCM"; + }; + + sram: sram@11000000 { /* alias @ 0x01000000 */ + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0x11000000 DT_SIZE_M(2)>; + zephyr,memory-region = "SRAM"; + }; + + dtcm: dtcm@30000000 { /* alias @ 0x20000000 */ + compatible = "zephyr,memory-region"; + reg = <0x30000000 DT_SIZE_K(32)>; + zephyr,memory-region = "DTCM"; + }; + + isram: sram@31000000 {/* alias @ 0x21000000 */ + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0x31000000 DT_SIZE_M(4)>; + zephyr,memory-region = "ISRAM"; + }; + + soc { + peripheral@50000000 { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x50000000 0x10000000>; + + #include "mps3_common_soc_peripheral.dtsi" + }; + }; +}; diff --git a/boards/arm/mps3/mps3_corstone310_an555.yaml b/boards/arm/mps3/mps3_corstone310_an555.yaml new file mode 100644 index 00000000000..5bcd0fb1925 --- /dev/null +++ b/boards/arm/mps3/mps3_corstone310_an555.yaml @@ -0,0 +1,22 @@ +# Copyright 2024 Arm Limited and/or its affiliates +# SPDX-License-Identifier: Apache-2.0 + +identifier: mps3/corstone310/an555 +name: Arm MPS3-Corstone310-AN555 +type: mcu +arch: arm +ram: 32 +flash: 32 +toolchain: + - gnuarmemb + - zephyr + - xtools +supported: + - gpio +testing: + ignore_tags: + - drivers + - bluetooth + - net + - timer +vendor: arm diff --git a/boards/arm/mps3/mps3_corstone310_an555_defconfig b/boards/arm/mps3/mps3_corstone310_an555_defconfig new file mode 100644 index 00000000000..f5607f3da4c --- /dev/null +++ b/boards/arm/mps3/mps3_corstone310_an555_defconfig @@ -0,0 +1,17 @@ +# Copyright 2024 Arm Limited and/or its affiliates +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_RUNTIME_NMI=y +CONFIG_ARM_TRUSTZONE_M=y +CONFIG_ARM_MPU=y + +# GPIOs +CONFIG_GPIO=y + +# Serial +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y + +# Build a Secure firmware image +CONFIG_TRUSTED_EXECUTION_SECURE=y diff --git a/boards/arm/mps3/mps3_corstone310_an555_ns.dts b/boards/arm/mps3/mps3_corstone310_an555_ns.dts new file mode 100644 index 00000000000..786ca6d9eb1 --- /dev/null +++ b/boards/arm/mps3/mps3_corstone310_an555_ns.dts @@ -0,0 +1,101 @@ +/* + * Copyright 2024 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include +#include +#include "mps3_common.dtsi" + +/ { + compatible = "arm,mps3-an555"; + #address-cells = <1>; + #size-cells = <1>; + + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,sram = &ram; + zephyr,flash = &code; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-m85"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + + mpu: mpu@e000ed90 { + compatible = "arm,armv8.1m-mpu"; + reg = <0xe000ed90 0x40>; + }; + }; + }; + + /* We utilize the secure addresses, if you subtract 0x10000000 + * you'll get the non-secure alias + */ + itcm: itcm@0 { + compatible = "zephyr,memory-region"; + reg = <0x0 DT_SIZE_K(32)>; + zephyr,memory-region = "ITCM"; + }; + + sram: sram@1000000 { + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0x1000000 DT_SIZE_M(2)>; + zephyr,memory-region = "SRAM"; + }; + + dtcm: dtcm@20000000 { + compatible = "zephyr,memory-region"; + reg = <0x20000000 DT_SIZE_K(512)>; + zephyr,memory-region = "DTCM"; + }; + + isram: sram@21000000 { + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0x21000000 DT_SIZE_M(4)>; + zephyr,memory-region = "ISRAM"; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* The memory regions defined below must match what the TF-M + * project has defined for that board - a single image boot is + * assumed. Please see the memory layout in: + * https://git.trustedfirmware.org/TF-M/trusted-firmware-m.git/tree/platform/ext/target/mps3/corstone310/common/partition/flash_layout.h + */ + + code: memory@1000000 { + reg = <0x01000000 DT_SIZE_M(2)>; + }; + + ram: memory@21000000 { + reg = <0x21000000 DT_SIZE_M(4)>; + }; + }; + + soc { + peripheral@40000000 { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x40000000 0x10000000>; + + #include "mps3_common_soc_peripheral.dtsi" + }; + }; +}; diff --git a/boards/arm/mps3/mps3_corstone310_an555_ns.yaml b/boards/arm/mps3/mps3_corstone310_an555_ns.yaml new file mode 100644 index 00000000000..f6a1f444f39 --- /dev/null +++ b/boards/arm/mps3/mps3_corstone310_an555_ns.yaml @@ -0,0 +1,17 @@ +# Copyright 2024 Arm Limited and/or its affiliates +# SPDX-License-Identifier: Apache-2.0 + +identifier: mps3/corstone310/an555/ns +name: Arm MPS3-Corstone310-AN555_ns +type: mcu +arch: arm +ram: 32 +flash: 32 +toolchain: + - gnuarmemb + - zephyr + - xtools +testing: + default: true + only_tags: + - trusted-firmware-m diff --git a/boards/arm/mps3/mps3_corstone310_an555_ns_defconfig b/boards/arm/mps3/mps3_corstone310_an555_ns_defconfig new file mode 100644 index 00000000000..51224f49ad8 --- /dev/null +++ b/boards/arm/mps3/mps3_corstone310_an555_ns_defconfig @@ -0,0 +1,18 @@ +# Copyright 2024 Arm Limited and/or its affiliates +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARM_TRUSTZONE_M=y +CONFIG_RUNTIME_NMI=y +CONFIG_ARM_MPU=y + +# GPIOs +CONFIG_GPIO=y + +# Serial +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y + +# Build a Non-secure firmware image +CONFIG_TRUSTED_EXECUTION_SECURE=n +CONFIG_TRUSTED_EXECUTION_NONSECURE=y diff --git a/boards/arm/mps3/mps3_corstone310_fvp.dts b/boards/arm/mps3/mps3_corstone310_fvp.dts new file mode 100644 index 00000000000..6ad45b5f973 --- /dev/null +++ b/boards/arm/mps3/mps3_corstone310_fvp.dts @@ -0,0 +1,96 @@ +/* + * Copyright 2024 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include +#include +#include "mps3_common.dtsi" + +/ { + compatible = "arm,mps3-fvp"; + #address-cells = <1>; + #size-cells = <1>; + + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,sram = &dtcm; + zephyr,flash = &itcm; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-m85"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + + mpu: mpu@e000ed90 { + compatible = "arm,armv8.1m-mpu"; + reg = <0xe000ed90 0x40>; + }; + }; + }; + + ethosu { + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&nvic>; + + ethosu0: ethosu@50004000 { + compatible = "arm,ethos-u"; + reg = <0x50004000>; + interrupts = <16 3>; + secure-enable; + privilege-enable; + status = "okay"; + }; + }; + + /* We utilize the secure addresses, if you subtract 0x10000000 + * you'll get the non-secure alias + */ + itcm: itcm@10000000 { /* alias @ 0x0 */ + compatible = "zephyr,memory-region"; + reg = <0x10000000 DT_SIZE_K(32)>; + zephyr,memory-region = "ITCM"; + }; + + sram: sram@11000000 { /* alias @ 0x01000000 */ + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0x11000000 DT_SIZE_M(2)>; + zephyr,memory-region = "SRAM"; + }; + + dtcm: dtcm@30000000 { /* alias @ 0x20000000 */ + compatible = "zephyr,memory-region"; + reg = <0x30000000 DT_SIZE_K(32)>; + zephyr,memory-region = "DTCM"; + }; + + isram: sram@31000000 {/* alias @ 0x21000000 */ + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0x31000000 DT_SIZE_M(4)>; + zephyr,memory-region = "ISRAM"; + }; + + soc { + peripheral@50000000 { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x50000000 0x10000000>; + + #include "mps3_common_soc_peripheral.dtsi" + }; + }; +}; diff --git a/boards/arm/mps3/mps3_corstone310_fvp.yaml b/boards/arm/mps3/mps3_corstone310_fvp.yaml new file mode 100644 index 00000000000..ab6c8d7e561 --- /dev/null +++ b/boards/arm/mps3/mps3_corstone310_fvp.yaml @@ -0,0 +1,25 @@ +# Copyright 2024 Arm Limited and/or its affiliates +# SPDX-License-Identifier: Apache-2.0 + +identifier: mps3/corstone310/fvp +name: Arm MPS3-Corstone310-FVP +type: mcu +arch: arm +ram: 32 +flash: 32 +simulation: + - name: armfvp + exec: FVP_Corstone_SSE-310 +toolchain: + - gnuarmemb + - zephyr + - xtools +supported: + - gpio +testing: + ignore_tags: + - drivers + - bluetooth + - net + - timer +vendor: arm diff --git a/boards/arm/mps3/mps3_corstone310_fvp_defconfig b/boards/arm/mps3/mps3_corstone310_fvp_defconfig new file mode 100644 index 00000000000..f5607f3da4c --- /dev/null +++ b/boards/arm/mps3/mps3_corstone310_fvp_defconfig @@ -0,0 +1,17 @@ +# Copyright 2024 Arm Limited and/or its affiliates +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_RUNTIME_NMI=y +CONFIG_ARM_TRUSTZONE_M=y +CONFIG_ARM_MPU=y + +# GPIOs +CONFIG_GPIO=y + +# Serial +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y + +# Build a Secure firmware image +CONFIG_TRUSTED_EXECUTION_SECURE=y diff --git a/boards/arm/mps3/mps3_corstone310_fvp_ns.dts b/boards/arm/mps3/mps3_corstone310_fvp_ns.dts new file mode 100644 index 00000000000..acc9b5fb737 --- /dev/null +++ b/boards/arm/mps3/mps3_corstone310_fvp_ns.dts @@ -0,0 +1,101 @@ +/* + * Copyright 2024 Arm Limited and/or its affiliates + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include +#include +#include "mps3_common.dtsi" + +/ { + compatible = "arm,mps3-fvp"; + #address-cells = <1>; + #size-cells = <1>; + + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,sram = &ram; + zephyr,flash = &code; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-m85"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + + mpu: mpu@e000ed90 { + compatible = "arm,armv8.1m-mpu"; + reg = <0xe000ed90 0x40>; + }; + }; + }; + + /* We utilize the secure addresses, if you subtract 0x10000000 + * you'll get the non-secure alias + */ + itcm: itcm@0 { + compatible = "zephyr,memory-region"; + reg = <0x0 DT_SIZE_K(32)>; + zephyr,memory-region = "ITCM"; + }; + + sram: sram@1000000 { + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0x1000000 DT_SIZE_M(2)>; + zephyr,memory-region = "SRAM"; + }; + + dtcm: dtcm@20000000 { + compatible = "zephyr,memory-region"; + reg = <0x20000000 DT_SIZE_K(512)>; + zephyr,memory-region = "DTCM"; + }; + + isram: sram@21000000 { + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0x21000000 DT_SIZE_M(4)>; + zephyr,memory-region = "ISRAM"; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* The memory regions defined below must match what the TF-M + * project has defined for that board - a single image boot is + * assumed. Please see the memory layout in: + * https://git.trustedfirmware.org/TF-M/trusted-firmware-m.git/tree/platform/ext/target/mps3/corstone310/common/partition/flash_layout.h + */ + + code: memory@28080000 { + reg = <0x28080000 DT_SIZE_K(512)>; + }; + + ram: memory@21020000 { + reg = <0x21020000 DT_SIZE_M(1)>; + }; + }; + + soc { + peripheral@40000000 { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x40000000 0x10000000>; + + #include "mps3_common_soc_peripheral.dtsi" + }; + }; +}; diff --git a/boards/arm/mps3/mps3_corstone310_fvp_ns.yaml b/boards/arm/mps3/mps3_corstone310_fvp_ns.yaml new file mode 100644 index 00000000000..6a70eff7fb0 --- /dev/null +++ b/boards/arm/mps3/mps3_corstone310_fvp_ns.yaml @@ -0,0 +1,17 @@ +# Copyright 2024 Arm Limited and/or its affiliates +# SPDX-License-Identifier: Apache-2.0 + +identifier: mps3/corstone310/fvp/ns +name: Arm MPS3-Corstone310-FVP_ns +type: mcu +arch: arm +ram: 32 +flash: 32 +toolchain: + - gnuarmemb + - zephyr + - xtools +testing: + default: true + only_tags: + - trusted-firmware-m diff --git a/boards/arm/mps3/mps3_corstone310_fvp_ns_defconfig b/boards/arm/mps3/mps3_corstone310_fvp_ns_defconfig new file mode 100644 index 00000000000..4eec22103ff --- /dev/null +++ b/boards/arm/mps3/mps3_corstone310_fvp_ns_defconfig @@ -0,0 +1,19 @@ +# Copyright 2024 Arm Limited and/or its affiliates +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARM_TRUSTZONE_M=y +CONFIG_RUNTIME_NMI=y +CONFIG_ARM_MPU=y + +# GPIOs +CONFIG_GPIO=y + +# Serial +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y + +# Build a Non-secure firmware image +CONFIG_TRUSTED_EXECUTION_SECURE=n +CONFIG_TRUSTED_EXECUTION_NONSECURE=y +CONFIG_BUILD_WITH_TFM=y diff --git a/boards/arm/v2m_musca_s1/v2m_musca_s1_musca_s1_ns.dts b/boards/arm/v2m_musca_s1/v2m_musca_s1_musca_s1_ns.dts index 5ea0bde7748..0607b2bbc00 100644 --- a/boards/arm/v2m_musca_s1/v2m_musca_s1_musca_s1_ns.dts +++ b/boards/arm/v2m_musca_s1/v2m_musca_s1_musca_s1_ns.dts @@ -41,7 +41,7 @@ }; }; - mram0: mram@a080400 { + mram0: mram@a080000 { /* Internal code eMRAM */ reg = <0x0a080000 0x80000>; }; diff --git a/boards/aspeed/ast1030_evb/doc/index.rst b/boards/aspeed/ast1030_evb/doc/index.rst index fb7d83d074b..1c23d7d2644 100644 --- a/boards/aspeed/ast1030_evb/doc/index.rst +++ b/boards/aspeed/ast1030_evb/doc/index.rst @@ -1,7 +1,4 @@ -.. _ast1030_evb: - -AST1030_EVB -################### +.. zephyr:board:: ast1030_evb Overview ******** @@ -10,10 +7,6 @@ The AST1030_EVB kit is a development platform to evaluate the Aspeed AST10x0 series SOCs. This board needs to be mated with part number AST1030. -.. image:: ast1030_evb.jpg - :align: center - :alt: AST1030 Evaluation Board - Hardware ******** diff --git a/boards/atmarktechno/degu_evk/Kconfig.defconfig b/boards/atmarktechno/degu_evk/Kconfig.defconfig index 286008a36ab..12c29c90ee0 100644 --- a/boards/atmarktechno/degu_evk/Kconfig.defconfig +++ b/boards/atmarktechno/degu_evk/Kconfig.defconfig @@ -5,29 +5,6 @@ if BOARD_DEGU_EVK -if USB_DEVICE_STACK - -config USB_DEVICE_PRODUCT - default "Degu Evaluation Kit" - -config UART_INTERRUPT_DRIVEN - default y - -config UART_LINE_CTRL - default y - -endif # USB_DEVICE_STACK - -if LOG - -# Logger cannot use itself to log -config USB_CDC_ACM_LOG_LEVEL - default 0 - -# Set USB log level to error only -config USB_DEVICE_LOG_LEVEL - default 1 - -endif # LOG +source "boards/common/usb/Kconfig.cdc_acm_serial.defconfig" endif # BOARD_DEGU_EVK diff --git a/boards/atmarktechno/degu_evk/degu_evk.dts b/boards/atmarktechno/degu_evk/degu_evk.dts index e9d579bd367..82c7b75ba7f 100644 --- a/boards/atmarktechno/degu_evk/degu_evk.dts +++ b/boards/atmarktechno/degu_evk/degu_evk.dts @@ -16,8 +16,6 @@ chosen { zephyr,sram = &sram0; zephyr,flash = &flash0; - zephyr,console = °u_cdc_acm_uart; - zephyr,shell-uart = °u_cdc_acm_uart; zephyr,code-partition = &slot0_partition; zephyr,ieee802154 = &ieee802154; }; @@ -173,8 +171,6 @@ zephyr_udc0: &usbd { compatible = "nordic,nrf-usbd"; status = "okay"; - - degu_cdc_acm_uart: degu_cdc_acm_uart { - compatible = "zephyr,cdc-acm-uart"; - }; }; + +#include <../boards/common/usb/cdc_acm_serial.dtsi> diff --git a/boards/atmarktechno/degu_evk/degu_evk_defconfig b/boards/atmarktechno/degu_evk/degu_evk_defconfig index ceed266a402..bd22e1dbfde 100644 --- a/boards/atmarktechno/degu_evk/degu_evk_defconfig +++ b/boards/atmarktechno/degu_evk/degu_evk_defconfig @@ -10,9 +10,6 @@ CONFIG_SERIAL=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y -# Enable USB (for CDC ACM console) -CONFIG_USB_DEVICE_STACK=y - # Additional board options CONFIG_GPIO=y diff --git a/boards/atmarktechno/degu_evk/doc/index.rst b/boards/atmarktechno/degu_evk/doc/index.rst index a252c4273e8..a41ff1238e3 100644 --- a/boards/atmarktechno/degu_evk/doc/index.rst +++ b/boards/atmarktechno/degu_evk/doc/index.rst @@ -1,7 +1,4 @@ -.. _degu_evk: - -Degu Evaluation Kit -#################### +.. zephyr:board:: degu_evk The Degu Evaluation Kit is an IoT device for sensors and actuators and can connect to an OpenThread mesh network. The Kit has a @@ -9,6 +6,4 @@ Nordic nRF52840 SoC and NXP A71CH Secure Element, and can connect some Seeed Grove sensors via GPIO, ADC, I2C, and UART. -.. figure:: img/degu_evk.jpg - For more information, see the `Degu Project website `__. diff --git a/boards/atmel/sam/sam4e_xpro/doc/index.rst b/boards/atmel/sam/sam4e_xpro/doc/index.rst index b01e60cd56d..1069727aa6c 100644 --- a/boards/atmel/sam/sam4e_xpro/doc/index.rst +++ b/boards/atmel/sam/sam4e_xpro/doc/index.rst @@ -1,7 +1,4 @@ -.. _sam4e_xpro: - -SAM4E Xplained Pro -################### +.. zephyr:board:: sam4e_xpro Overview ******** @@ -9,10 +6,6 @@ Overview The SAM4E Xplained Pro evaluation kit is a development platform to evaluate the Atmel SAM4E series microcontrollers. -.. image:: img/sam4e_xpro.jpg - :align: center - :alt: SAM4E Xplained Pro - Hardware ******** diff --git a/boards/atmel/sam/sam4e_xpro/sam4e_xpro.dts b/boards/atmel/sam/sam4e_xpro/sam4e_xpro.dts index ddd73d0faef..253d5ba48d1 100644 --- a/boards/atmel/sam/sam4e_xpro/sam4e_xpro.dts +++ b/boards/atmel/sam/sam4e_xpro/sam4e_xpro.dts @@ -219,6 +219,7 @@ pinctrl-names = "default"; mmc { compatible = "zephyr,sdmmc-disk"; + disk-name = "SD"; status = "okay"; }; }; diff --git a/boards/atmel/sam/sam4l_ek/doc/index.rst b/boards/atmel/sam/sam4l_ek/doc/index.rst index f3e4e27d376..f958a540515 100644 --- a/boards/atmel/sam/sam4l_ek/doc/index.rst +++ b/boards/atmel/sam/sam4l_ek/doc/index.rst @@ -1,7 +1,4 @@ -.. _sam4l_ek: - -SAM4L-EK -######## +.. zephyr:board:: sam4l_ek Overview ******** @@ -22,10 +19,6 @@ The kit is equipped with a rich set of peripherals that make the ATSAM4L-EK a perfect evaluation platform. Download the `SAM4L-EK Online User Guide`_ for more details. -.. image:: img/atmel-sam4l-ek-callouts.jpg - :align: center - :alt: SAM4L-EK - Hardware ******** diff --git a/boards/atmel/sam/sam4l_ek/sam4l_ek.yaml b/boards/atmel/sam/sam4l_ek/sam4l_ek.yaml index f33959c7805..3a8193e5515 100644 --- a/boards/atmel/sam/sam4l_ek/sam4l_ek.yaml +++ b/boards/atmel/sam/sam4l_ek/sam4l_ek.yaml @@ -16,6 +16,5 @@ supported: - i2c - spi - uart - - usb - usb_device vendor: atmel diff --git a/boards/atmel/sam/sam4s_xplained/doc/index.rst b/boards/atmel/sam/sam4s_xplained/doc/index.rst index a5276bd6716..480411323bd 100644 --- a/boards/atmel/sam/sam4s_xplained/doc/index.rst +++ b/boards/atmel/sam/sam4s_xplained/doc/index.rst @@ -1,7 +1,4 @@ -.. _sam4s_xplained: - -SAM4S Xplained -############## +.. zephyr:board:: sam4s_xplained Overview ******** @@ -9,10 +6,6 @@ Overview The SAM4S Xplained evaluation kit is a development platform to evaluate the Atmel SAM4S series microcontrollers. -.. image:: img/sam4s_xplained.jpg - :align: center - :alt: SAM4S Xplained - Hardware ******** diff --git a/boards/atmel/sam/sam_e70_xplained/doc/index.rst b/boards/atmel/sam/sam_e70_xplained/doc/index.rst index 67b90d42c59..6c816439176 100644 --- a/boards/atmel/sam/sam_e70_xplained/doc/index.rst +++ b/boards/atmel/sam/sam_e70_xplained/doc/index.rst @@ -1,7 +1,4 @@ -.. _sam_e70_xplained: - -SAM E70(B) Xplained -################### +.. zephyr:board:: sam_e70_xplained Overview ******** @@ -10,10 +7,6 @@ The SAM E70 Xplained evaluation kit is a development platform to evaluate the Atmel SAM E70 series microcontrollers. The current version allows to use both IC variations ATSAME70Q21A(B). -.. image:: img/sam_e70_xplained.jpg - :align: center - :alt: SAM E70 Xplained - Hardware ******** diff --git a/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained_same70q21.dts b/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained_same70q21.dts index d96e5083d5b..9ca18e32927 100644 --- a/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained_same70q21.dts +++ b/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained_same70q21.dts @@ -8,7 +8,7 @@ /dts-v1/; -#include +#include #include "sam_e70_xplained-common.dtsi" / { diff --git a/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained_same70q21.yaml b/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained_same70q21.yaml index e6da0170989..a9fb5a4704f 100644 --- a/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained_same70q21.yaml +++ b/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained_same70q21.yaml @@ -20,7 +20,6 @@ supported: - pwm - netif:eth - spi - - usb - usb_device - watchdog vendor: atmel diff --git a/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained_same70q21b.dts b/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained_same70q21b.dts index e65d9da3325..50bd89a5ed3 100644 --- a/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained_same70q21b.dts +++ b/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained_same70q21b.dts @@ -7,7 +7,7 @@ /dts-v1/; -#include +#include #include "sam_e70_xplained-common.dtsi" / { diff --git a/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained_same70q21b.yaml b/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained_same70q21b.yaml index 8d15c3ae088..4adc2dc6dd3 100644 --- a/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained_same70q21b.yaml +++ b/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained_same70q21b.yaml @@ -20,7 +20,6 @@ supported: - pwm - netif:eth - spi - - usb - usb_device - watchdog vendor: atmel diff --git a/boards/atmel/sam/sam_v71_xult/doc/index.rst b/boards/atmel/sam/sam_v71_xult/doc/index.rst index 7ce56d58a70..cb7ecbfda43 100644 --- a/boards/atmel/sam/sam_v71_xult/doc/index.rst +++ b/boards/atmel/sam/sam_v71_xult/doc/index.rst @@ -1,7 +1,4 @@ -.. _sam_v71_xplained_ultra: - -SAM V71(B) Xplained Ultra -######################### +.. zephyr:board:: sam_v71_xult Overview ******** @@ -10,10 +7,6 @@ The SAM V71 Xplained Ultra evaluation kit is a development platform to evaluate the Atmel SAM V71 series microcontrollers. The current version allows to use both IC variations ATSAMV71Q21A(B). -.. image:: img/sam_v71_xult.jpg - :align: center - :alt: SAM V71 Xplained Ultra - Hardware ******** diff --git a/boards/atmel/sam/sam_v71_xult/sam_v71_xult-common.dtsi b/boards/atmel/sam/sam_v71_xult/sam_v71_xult-common.dtsi index f6981455b51..d5500da2bfc 100644 --- a/boards/atmel/sam/sam_v71_xult/sam_v71_xult-common.dtsi +++ b/boards/atmel/sam/sam_v71_xult/sam_v71_xult-common.dtsi @@ -2,7 +2,7 @@ * Copyright (c) 2017 Piotr Mienkowski * Copyright (c) 2017 Justin Watson * Copyright (c) 2020 Stephanos Ioannidis - * Copyright (c) 2019-2022 Gerson Fernando Budke + * Copyright (c) 2019-2024 Gerson Fernando Budke * * SPDX-License-Identifier: Apache-2.0 */ @@ -17,6 +17,7 @@ led0 = &yellow_led1; pwm-led0 = &pwm_led0; pwm-0 = &pwm0; + rtc = &rtc; sw0 = &sw0_user_button; sw1 = &sw1_user_button; watchdog0 = &wdt; @@ -336,6 +337,10 @@ zephyr_udc0: &usbhs { }; }; +&rtc { + status = "okay"; +}; + ext1_spi: &spi0 { }; diff --git a/boards/atmel/sam/sam_v71_xult/sam_v71_xult_samv71q21.dts b/boards/atmel/sam/sam_v71_xult/sam_v71_xult_samv71q21.dts index 9bdcadc7946..ed06c0752b0 100644 --- a/boards/atmel/sam/sam_v71_xult/sam_v71_xult_samv71q21.dts +++ b/boards/atmel/sam/sam_v71_xult/sam_v71_xult_samv71q21.dts @@ -8,7 +8,7 @@ /dts-v1/; -#include +#include #include "sam_v71_xult-common.dtsi" / { diff --git a/boards/atmel/sam/sam_v71_xult/sam_v71_xult_samv71q21.yaml b/boards/atmel/sam/sam_v71_xult/sam_v71_xult_samv71q21.yaml index e8b433685d0..271565dac24 100644 --- a/boards/atmel/sam/sam_v71_xult/sam_v71_xult_samv71q21.yaml +++ b/boards/atmel/sam/sam_v71_xult/sam_v71_xult_samv71q21.yaml @@ -22,8 +22,8 @@ supported: - i2s - pwm - netif:eth + - rtc - spi - - usb - usb_device - watchdog - xpro_gpio diff --git a/boards/atmel/sam/sam_v71_xult/sam_v71_xult_samv71q21b.dts b/boards/atmel/sam/sam_v71_xult/sam_v71_xult_samv71q21b.dts index f6f7f5a03eb..313093defd8 100644 --- a/boards/atmel/sam/sam_v71_xult/sam_v71_xult_samv71q21b.dts +++ b/boards/atmel/sam/sam_v71_xult/sam_v71_xult_samv71q21b.dts @@ -7,7 +7,7 @@ /dts-v1/; -#include +#include #include "sam_v71_xult-common.dtsi" / { diff --git a/boards/atmel/sam/sam_v71_xult/sam_v71_xult_samv71q21b.yaml b/boards/atmel/sam/sam_v71_xult/sam_v71_xult_samv71q21b.yaml index 578359edbbe..732d1de39e6 100644 --- a/boards/atmel/sam/sam_v71_xult/sam_v71_xult_samv71q21b.yaml +++ b/boards/atmel/sam/sam_v71_xult/sam_v71_xult_samv71q21b.yaml @@ -22,8 +22,8 @@ supported: - i2s - pwm - netif:eth + - rtc - spi - - usb - usb_device - watchdog - xpro_gpio diff --git a/boards/atmel/sam0/samc21n_xpro/doc/index.rst b/boards/atmel/sam0/samc21n_xpro/doc/index.rst index 600163a00c9..678e3afa453 100644 --- a/boards/atmel/sam0/samc21n_xpro/doc/index.rst +++ b/boards/atmel/sam0/samc21n_xpro/doc/index.rst @@ -1,7 +1,4 @@ -.. _samc21n_xpro: - -SAM C21N Xplained Pro Evaluation Kit -#################################### +.. zephyr:board:: samc21n_xpro Overview ******** @@ -12,10 +9,6 @@ microcontrollers. The kit includes Atmel’s Embedded Debugger (EDBG), which provides a full debug interface without the need for additional hardware. -.. image:: img/atsamc21n_xpro.jpg - :align: center - :alt: SAMC21N-XPRO - Hardware ******** diff --git a/boards/atmel/sam0/samd20_xpro/doc/index.rst b/boards/atmel/sam0/samd20_xpro/doc/index.rst index 7b788cbbf73..6127a37aff6 100644 --- a/boards/atmel/sam0/samd20_xpro/doc/index.rst +++ b/boards/atmel/sam0/samd20_xpro/doc/index.rst @@ -1,7 +1,4 @@ -.. _samd20_xpro: - -SAM D20 Xplained Pro Evaluation Kit -################################### +.. zephyr:board:: samd20_xpro Overview ******** @@ -12,13 +9,6 @@ microcontrollers. The kit includes Atmel’s Embedded Debugger (EDBG), which provides a full debug interface without the need for additional hardware. -.. figure:: img/atsamd20_xpro.jpg - :width: 500px - :align: center - :alt: SAMD20-XPRO - - SAMD20-XPRO (Credit: `Microchip Technology`_) - Hardware ******** diff --git a/boards/atmel/sam0/samd20_xpro/samd20_xpro.yaml b/boards/atmel/sam0/samd20_xpro/samd20_xpro.yaml index 548bd6c462a..1db726120e1 100644 --- a/boards/atmel/sam0/samd20_xpro/samd20_xpro.yaml +++ b/boards/atmel/sam0/samd20_xpro/samd20_xpro.yaml @@ -1,3 +1,6 @@ +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + identifier: samd20_xpro name: SAM D20 Xplained Pro type: mcu @@ -9,7 +12,6 @@ toolchain: flash: 256 ram: 32 supported: - - adc - flash - gpio - i2c diff --git a/boards/atmel/sam0/samd21_xpro/doc/index.rst b/boards/atmel/sam0/samd21_xpro/doc/index.rst index f4f5bd3391d..057d6d80b8d 100644 --- a/boards/atmel/sam0/samd21_xpro/doc/index.rst +++ b/boards/atmel/sam0/samd21_xpro/doc/index.rst @@ -1,7 +1,4 @@ -.. _samd21_xpro: - -SAM D21 Xplained Pro Evaluation Kit -################################### +.. zephyr:board:: samd21_xpro Overview ******** @@ -12,13 +9,6 @@ microcontrollers. The kit includes Atmel's Embedded Debugger (EDBG), which provides a full debug interface without the need for additional hardware. -.. figure:: img/atsamd21_xpro.jpg - :width: 500px - :align: center - :alt: SAMD21-XPRO - - SAMD21-XPRO (Credit: `Microchip Technology`_) - Hardware ******** diff --git a/boards/atmel/sam0/samd21_xpro/samd21_xpro.yaml b/boards/atmel/sam0/samd21_xpro/samd21_xpro.yaml index c41c9443285..e1e8e08bdbb 100644 --- a/boards/atmel/sam0/samd21_xpro/samd21_xpro.yaml +++ b/boards/atmel/sam0/samd21_xpro/samd21_xpro.yaml @@ -1,6 +1,7 @@ # Copyright (c) 2018 Bryan O'Donoghue # Copyright (c) 2024 Gerson Fernando Budke # SPDX-License-Identifier: Apache-2.0 + identifier: samd21_xpro name: SAM D21 Xplained Pro type: mcu @@ -12,7 +13,6 @@ toolchain: flash: 256 ram: 32 supported: - - adc - counter - dma - gpio diff --git a/boards/atmel/sam0/same54_xpro/doc/index.rst b/boards/atmel/sam0/same54_xpro/doc/index.rst index 5fa1eb49e37..61b127d7a1b 100644 --- a/boards/atmel/sam0/same54_xpro/doc/index.rst +++ b/boards/atmel/sam0/same54_xpro/doc/index.rst @@ -1,7 +1,4 @@ -.. _same54_xpro: - -SAM E54 Xplained Pro Evaluation Kit -################################### +.. zephyr:board:: same54_xpro Overview ******** @@ -12,10 +9,6 @@ microcontrollers. The kit includes Atmel’s Embedded Debugger (EDBG), which provides a full debug interface without the need for additional hardware. -.. image:: img/atsame54_xpro.jpg - :align: center - :alt: SAME54-XPRO - Hardware ******** diff --git a/boards/atmel/sam0/saml21_xpro/doc/index.rst b/boards/atmel/sam0/saml21_xpro/doc/index.rst index 172fa1f0826..b92e1bf09a7 100644 --- a/boards/atmel/sam0/saml21_xpro/doc/index.rst +++ b/boards/atmel/sam0/saml21_xpro/doc/index.rst @@ -1,7 +1,4 @@ - .. _saml21_xpro: - -SAM L21 Xplained Pro Evaluation Kit -################################### +.. zephyr:board:: saml21_xpro Overview ******** @@ -12,10 +9,6 @@ microcontrollers. The kit includes Atmel’s Embedded Debugger (EDBG), which provides a full debug interface without the need for additional hardware. -.. image:: img/atsaml21-xpro.jpg - :align: center - :alt: SAML21-XPRO - Hardware ******** diff --git a/boards/atmel/sam0/samr21_xpro/doc/index.rst b/boards/atmel/sam0/samr21_xpro/doc/index.rst index 91a47615b9a..e04b4d7a711 100644 --- a/boards/atmel/sam0/samr21_xpro/doc/index.rst +++ b/boards/atmel/sam0/samr21_xpro/doc/index.rst @@ -1,7 +1,4 @@ -.. _samr21_xpro: - -SAM R21 Xplained Pro Evaluation Kit -################################### +.. zephyr:board:: samr21_xpro Overview ******** @@ -12,10 +9,6 @@ bundled with Atmel's AT86RF233, a 2.4GHz IEEE802.15.4 compatible radio. The kit includes Atmel’s Embedded Debugger (EDBG), which provides a full debug interface without the need for additional hardware. -.. image:: img/atsamr21_xpro.jpg - :align: center - :alt: SAMR21-XPRO - Hardware ******** diff --git a/boards/atmel/sam0/samr21_xpro/samr21_xpro-pinctrl.dtsi b/boards/atmel/sam0/samr21_xpro/samr21_xpro-pinctrl.dtsi index de5b64f0f8c..81f7bce508a 100644 --- a/boards/atmel/sam0/samr21_xpro/samr21_xpro-pinctrl.dtsi +++ b/boards/atmel/sam0/samr21_xpro/samr21_xpro-pinctrl.dtsi @@ -1,11 +1,17 @@ /* - * Copyright (c) 2022, Gerson Fernando Budke + * Copyright (c) 2022-2024, Gerson Fernando Budke * SPDX-License-Identifier: Apache-2.0 */ #include &pinctrl { + adc_default: adc_default { + group1 { + pinmux = ; + }; + }; + pwm_default: pwm_default { group1 { pinmux = ; diff --git a/boards/atmel/sam0/samr21_xpro/samr21_xpro.dts b/boards/atmel/sam0/samr21_xpro/samr21_xpro.dts index 01ed0e8826c..e53fdc80f55 100644 --- a/boards/atmel/sam0/samr21_xpro/samr21_xpro.dts +++ b/boards/atmel/sam0/samr21_xpro/samr21_xpro.dts @@ -106,6 +106,12 @@ clock-frequency = <48000000>; }; +&adc { + status = "okay"; + pinctrl-0 = <&adc_default>; + pinctrl-names = "default"; +}; + &tcc0 { status = "okay"; compatible = "atmel,sam0-tcc-pwm"; diff --git a/boards/atmel/sam0/samr21_xpro/samr21_xpro.yaml b/boards/atmel/sam0/samr21_xpro/samr21_xpro.yaml index 25ce756d667..b61a8209edb 100644 --- a/boards/atmel/sam0/samr21_xpro/samr21_xpro.yaml +++ b/boards/atmel/sam0/samr21_xpro/samr21_xpro.yaml @@ -1,6 +1,7 @@ # Copyright (c) 2019 Benjamin Valentin -# Copyright (c) 2019-2024 Gerson Fernando Budke +# Copyright (c) 2019-2024 Gerson Fernando Budke # SPDX-License-Identifier: Apache-2.0 + identifier: samr21_xpro name: SAM R21 Xplained Pro type: mcu diff --git a/boards/atmel/sam0/samr34_xpro/doc/index.rst b/boards/atmel/sam0/samr34_xpro/doc/index.rst index aa8849d2cb3..4a38544be35 100644 --- a/boards/atmel/sam0/samr34_xpro/doc/index.rst +++ b/boards/atmel/sam0/samr34_xpro/doc/index.rst @@ -1,7 +1,4 @@ - .. _samr34_xpro: - -SAM R34 Xplained Pro Evaluation Kit -################################### +.. zephyr:board:: samr34_xpro Overview ******** @@ -17,10 +14,6 @@ including both a SAML21 die, and a Semtech SX1276 LoRa radio die. This board is also referred to as DM320111. -.. image:: img/atsamr34-xpro.jpg - :align: center - :alt: SAMR34-XPRO - Hardware ******** diff --git a/boards/bbc/microbit/Kconfig.defconfig b/boards/bbc/microbit/Kconfig.defconfig index 1f8bf5b8bc7..41fec971508 100644 --- a/boards/bbc/microbit/Kconfig.defconfig +++ b/boards/bbc/microbit/Kconfig.defconfig @@ -5,9 +5,6 @@ if BOARD_BBC_MICROBIT -config BT_CTLR - default BT - if FXOS8700 choice FXOS8700_MODE diff --git a/boards/bbc/microbit/doc/index.rst b/boards/bbc/microbit/doc/index.rst index c4d11f7a671..1d829d89a89 100644 --- a/boards/bbc/microbit/doc/index.rst +++ b/boards/bbc/microbit/doc/index.rst @@ -1,7 +1,4 @@ -.. _bbc_microbit: - -BBC MicroBit -############## +.. zephyr:board:: bbc_microbit Overview ******** @@ -23,12 +20,6 @@ connectors that are part of the 23-pin edge connector. * FLASH * RADIO (Bluetooth Low Energy) -.. figure:: img/bbc_microbit.jpg - :align: center - :alt: BBC Micro Bit - - BBC Micro Bit (Credit: http://microbit.org/) - More information about the board can be found at the `microbit website`_. Hardware diff --git a/boards/bbc/microbit_v2/Kconfig.defconfig b/boards/bbc/microbit_v2/Kconfig.defconfig index 3139f2f24c5..c00278c3ced 100644 --- a/boards/bbc/microbit_v2/Kconfig.defconfig +++ b/boards/bbc/microbit_v2/Kconfig.defconfig @@ -5,7 +5,4 @@ if BOARD_BBC_MICROBIT_V2 -config BT_CTLR - default BT - endif # BOARD_BBC_MICROBIT_V2 diff --git a/boards/bbc/microbit_v2/doc/index.rst b/boards/bbc/microbit_v2/doc/index.rst index d906f13660b..62c3cee2252 100644 --- a/boards/bbc/microbit_v2/doc/index.rst +++ b/boards/bbc/microbit_v2/doc/index.rst @@ -1,7 +1,4 @@ -.. _bbc_microbit_v2: - -BBC MicroBit V2 -################# +.. zephyr:board:: bbc_microbit_v2 Overview ******** @@ -16,12 +13,6 @@ magnetometer sensors, Bluetooth and USB connectivity, a display consisting of USB or an external battery pack. The device inputs and outputs are through five ring connectors that are part of the 23-pin edge connector. -.. figure:: img/bbc_microbit2.jpg - :align: center - :alt: BBC Micro Bit V2 - - BBC Micro Bit V2 (Credit: http://microbit.org/) - More information about the board can be found at the `microbit website`_. Hardware diff --git a/boards/bcdevices/plt_demo_v2/Kconfig.defconfig b/boards/bcdevices/plt_demo_v2/Kconfig.defconfig index ce7c0c3891f..1ee0f255fcf 100644 --- a/boards/bcdevices/plt_demo_v2/Kconfig.defconfig +++ b/boards/bcdevices/plt_demo_v2/Kconfig.defconfig @@ -5,9 +5,6 @@ if BOARD_BLUECLOVER_PLT_DEMO_V2_NRF52832 -config BT_CTLR - default BT - config I2C default SENSOR diff --git a/boards/bcdevices/plt_demo_v2/doc/index.rst b/boards/bcdevices/plt_demo_v2/doc/index.rst index cf4df2dcb87..646e5c92025 100644 --- a/boards/bcdevices/plt_demo_v2/doc/index.rst +++ b/boards/bcdevices/plt_demo_v2/doc/index.rst @@ -1,7 +1,4 @@ -.. _blueclover_plt_demo_v2_nrf52832: - -Blue Clover PLT Demo V2 nRF52832 -################################ +.. zephyr:board:: blueclover_plt_demo_v2 Overview ******** @@ -27,10 +24,6 @@ The Nordic Semiconductor nRF52832 ARM Cortex-M4F MCU features the following: * :abbr:`UART (Universal asynchronous receiver-transmitter)` * :abbr:`WDT (Watchdog Timer)` -.. figure:: img/blueclover_plt_demo_v2.jpg - :align: center - :alt: Blue Clover PLT Demo V2 nRF52832 - Hardware ******** diff --git a/boards/beagle/beaglebone_ai64/Kconfig.beaglebone_ai64 b/boards/beagle/beaglebone_ai64/Kconfig.beaglebone_ai64 new file mode 100644 index 00000000000..08b2561528d --- /dev/null +++ b/boards/beagle/beaglebone_ai64/Kconfig.beaglebone_ai64 @@ -0,0 +1,7 @@ +# Copyright (C) 2023 BeagleBoard.org Foundation +# Copyright (C) 2023 S Prashanth +# +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_BEAGLEBONE_AI64 + select SOC_J721E_MAIN_R5F0_0 if BOARD_BEAGLEBONE_AI64_J721E_MAIN_R5F0_0 diff --git a/boards/beagle/beaglebone_ai64/beaglebone_ai64_j721e_main_r5f0_0-pinctrl.dtsi b/boards/beagle/beaglebone_ai64/beaglebone_ai64_j721e_main_r5f0_0-pinctrl.dtsi new file mode 100644 index 00000000000..dfc744b72e4 --- /dev/null +++ b/boards/beagle/beaglebone_ai64/beaglebone_ai64_j721e_main_r5f0_0-pinctrl.dtsi @@ -0,0 +1,21 @@ +/* Copyright (C) 2023 BeagleBoard.org Foundation + * Copyright (C) 2023 S Prashanth + * Copyright (c) 2024 Texas Instruments Incorporated + * Andrew Davis + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + uart2_tx_default: uart2_tx_default { + /* 0x1c is address of padconfig register of p8.34 and 14 is mux mode */ + pinmux = ; + }; + + uart2_rx_default: uart2_rx_default { + /* 0x14 is address of padconfig register of p8.22 and 14 is mux mode */ + pinmux = ; + }; +}; diff --git a/boards/beagle/beaglebone_ai64/beaglebone_ai64_j721e_main_r5f0_0.dts b/boards/beagle/beaglebone_ai64/beaglebone_ai64_j721e_main_r5f0_0.dts new file mode 100644 index 00000000000..8c4c8f0e8e4 --- /dev/null +++ b/boards/beagle/beaglebone_ai64/beaglebone_ai64_j721e_main_r5f0_0.dts @@ -0,0 +1,57 @@ +/* Copyright (C) 2023 BeagleBoard.org Foundation + * Copyright (C) 2023 S Prashanth + * Copyright (c) 2024 Texas Instruments Incorporated + * Andrew Davis + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "beaglebone_ai64_j721e_main_r5f0_0-pinctrl.dtsi" +#include + +/ { + model = "BeagleBoard.org BeagleBone AI-64"; + compatible = "beagle,beaglebone-ai64"; + + chosen { + zephyr,sram = &atcm; + zephyr,console = &uart2; + }; + + cpus { + cpu@0 { + status = "okay"; + }; + }; + + ddr0: memory@a2000000 { + compatible = "mmio-sram"; + reg = <0xa2000000 DT_SIZE_M(1)>; + }; + + rsc_table: memory@a2100000 { + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0xa2100000 DT_SIZE_M(1)>; + zephyr,memory-region = "RSC_TABLE"; + }; + + ddr1: memory@a2200000 { + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0xa2200000 DT_SIZE_M(14)>; + zephyr,memory-region = "DRAM"; + }; +}; + +&uart2 { + status = "okay"; + pinctrl-0 = <&uart2_tx_default &uart2_rx_default>; + pinctrl-names = "default"; + current-speed = <115200>; +}; + +&systick_timer { + status = "okay"; +}; diff --git a/boards/beagle/beaglebone_ai64/beaglebone_ai64_j721e_main_r5f0_0.yaml b/boards/beagle/beaglebone_ai64/beaglebone_ai64_j721e_main_r5f0_0.yaml new file mode 100644 index 00000000000..0adaeddf82f --- /dev/null +++ b/boards/beagle/beaglebone_ai64/beaglebone_ai64_j721e_main_r5f0_0.yaml @@ -0,0 +1,17 @@ +# Copyright (C) 2023 BeagleBoard.org Foundation +# Copyright (C) 2023 S Prashanth +# +# SPDX-License-Identifier: Apache-2.0 + +identifier: beaglebone_ai64/j721e/main_r5f0_0 +name: BeagleBone-AI64 R5 +type: mcu +arch: arm +ram: 32 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - uart +vendor: beagle diff --git a/boards/beagle/beaglebone_ai64/beaglebone_ai64_j721e_main_r5f0_0_defconfig b/boards/beagle/beaglebone_ai64/beaglebone_ai64_j721e_main_r5f0_0_defconfig new file mode 100644 index 00000000000..244755fe3c9 --- /dev/null +++ b/boards/beagle/beaglebone_ai64/beaglebone_ai64_j721e_main_r5f0_0_defconfig @@ -0,0 +1,15 @@ +# Copyright (C) 2023 BeagleBoard.org Foundation +# Copyright (C) 2023 S Prashanth +# +# SPDX-License-Identifier: Apache-2.0 + +# Zephyr Kernel Configuration +CONFIG_XIP=n + +# Serial Driver +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +# Enable Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/beagle/beaglebone_ai64/board.yml b/boards/beagle/beaglebone_ai64/board.yml new file mode 100644 index 00000000000..e81db526dd5 --- /dev/null +++ b/boards/beagle/beaglebone_ai64/board.yml @@ -0,0 +1,6 @@ +board: + name: beaglebone_ai64 + full_name: BeagleBone AI-64 + vendor: beagle + socs: + - name: j721e diff --git a/boards/beagle/beaglebone_ai64/doc/assets/beaglebone_ai_64.webp b/boards/beagle/beaglebone_ai64/doc/assets/beaglebone_ai_64.webp new file mode 100644 index 00000000000..f513626e0e2 Binary files /dev/null and b/boards/beagle/beaglebone_ai64/doc/assets/beaglebone_ai_64.webp differ diff --git a/boards/beagle/beaglebone_ai64/doc/index.rst b/boards/beagle/beaglebone_ai64/doc/index.rst new file mode 100644 index 00000000000..d54775011db --- /dev/null +++ b/boards/beagle/beaglebone_ai64/doc/index.rst @@ -0,0 +1,121 @@ +.. zephyr:board:: beaglebone_ai64 + +Overview +******** + +BeagleBone AI-64 is a computational platform powered by TI J721E SoC, which is +targeted for automotive applications. + +Hardware +******** + +BeagleBone AI-64 is powered by TI J721E SoC, which has three domains (MAIN, +MCU, WKUP). This document gives overview of Zephyr running on Cortex R5's +in the MAIN domain. + +L1 Memory System +---------------- + +* 16 KB instruction cache. +* 16 KB data cache. +* 64 KB TCM. + +Region Address Translation +-------------------------- + +The RAT module performs a region based address translation. It translates a +32-bit input address into a 48-bit output address. Any input transaction that +starts inside of a programmed region will have its address translated, if the +region is enabled. + +VIM Interrupt Controller +------------------------ + +The VIM aggregates device interrupts and sends them to the R5F CPU(s). The VIM +module supports 512 interrupt inputs per R5F core. Each interrupt can be either +a level or a pulse (both active-high). The VIM has two interrupt outputs per core +IRQ and FIQ. + +Supported Features +****************** + +The board configuration supports, + ++-----------+------------+-----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=======================+ +| UART | on-chip | serial port-polling | +| | | serial port-interrupt | ++-----------+------------+-----------------------+ + +Other hardwares features are currently not supported. + +Running Zephyr +************** + +The J721E does not have a separate flash for the R5 cores. Because of this +the A72 core has to load the program for the R5 cores to the right memory +address, set the PC and start the processor. +This can be done from Linux on the A72 core via remoteproc. + +By default the R5's Memory Protection Unit (MPU) only allows for execution of +instructions in the ATCM/BTCM. There is also a couple regions of DRAM memory +carved out for each R5 by Linux. These can be used for IPC (DDR0) and for +data (DDR1). DDR1 can also be used for executable regions after programming +the MPU. + +This is the memory mapping from A72 to the memory usable by the R5. Note that +the R5 cores always see their local ATCM at address 0x00000000 and their BTCM +at address 0x41010000. The ATCM/BTCM locations are fixed in hardware, but the +DDR regions are by convention. If you would like to use different DRAM +locations or sizes, you must also update for the same on the A72 software. +(For Linux as the A72 host, this would be changed in Device Tree). + ++------------+--------------+--------------+--------------+--------------+--------+ +| Region | R5FSS0 Core0 | R5FSS0 Core1 | R5FSS1 Core0 | R5FSS1 Core1 | Size | ++============+==============+==============+==============+==============+========+ +| ATCM | 0x05c00000 | 0x05d00000 | 0x05e00000 | 0x05f00000 | 32KB | ++------------+--------------+--------------+--------------+--------------+--------+ +| BTCM | 0x05c10000 | 0x05d10000 | 0x05e10000 | 0x05f00000 | 32KB | ++------------+--------------+--------------+--------------+--------------+--------+ +| DDR0 | 0xA2000000 | 0xA3000000 | 0xA4000000 | 0xA5000000 | 1MB | ++------------+--------------+--------------+--------------+--------------+--------+ +| DDR1 | 0xA2100000 | 0xA3000000 | 0xA4100000 | 0xA5000000 | 15MB | ++------------+--------------+--------------+--------------+--------------+--------+ + +Steps to build and run an image +------------------------------- + +Here is an example for the :zephyr:code-sample:`hello_world` application +targeting one of the Cortex R5F on BeagleBone AI-64: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: beaglebone_ai64/j721e/main_r5f0_0 + :goals: build + +To load the image: + +| Copy Zephyr image to the /lib/firmware/ directory. +| ``cp build/zephyr/zephyr.elf /lib/firmware/`` +| +| Ensure the core is not running. +| ``echo stop > /dev/remoteproc/j7-main-r5f0_0/state`` +| +| Configuring the image name to the remoteproc module. +| ``echo zephyr.elf > /dev/remoteproc/j7-main-r5f0_0/firmware`` +| +| Once the image name is configured, send the start command. +| ``echo start > /dev/remoteproc/j7-main-r5f0_0/state`` + +Console +------- + +Zephyr on BeagleBone AI-64 J721E Cortex R5 uses UART 2 (Rx p8.22, Tx p8.34) +as console. + +References +********** + +* `BeagleBone AI-64 Homepage `_ +* `J721E TRM `_ diff --git a/boards/beagle/beagleconnect_freedom/beagleconnect_freedom-pinctrl.dtsi b/boards/beagle/beagleconnect_freedom/beagleconnect_freedom-pinctrl.dtsi index cf662d67a2e..c630d9b865f 100644 --- a/boards/beagle/beagleconnect_freedom/beagleconnect_freedom-pinctrl.dtsi +++ b/boards/beagle/beagleconnect_freedom/beagleconnect_freedom-pinctrl.dtsi @@ -95,4 +95,18 @@ pinmux = <30 IOC_PORT_RFC_GPO0>; bias-disable; }; + + /* MB1 PWM */ + pwm0_default: pwm0_default { + pinmux = <17 IOC_PORT_MCU_PORT_EVENT1>; + bias-disable; + drive-strength = <2>; + }; + + /* MB2 PWM */ + pwm1_default: pwm1_default { + pinmux = <19 IOC_PORT_MCU_PORT_EVENT3>; + bias-disable; + drive-strength = <2>; + }; }; diff --git a/boards/beagle/beagleconnect_freedom/beagleconnect_freedom.dts b/boards/beagle/beagleconnect_freedom/beagleconnect_freedom.dts index f94737a9e37..3191eccb625 100644 --- a/boards/beagle/beagleconnect_freedom/beagleconnect_freedom.dts +++ b/boards/beagle/beagleconnect_freedom/beagleconnect_freedom.dts @@ -201,10 +201,87 @@ }; }; -&ieee802154 { +&ieee802154g { status = "okay"; }; -&ieee802154g { +&gpt0 { + status = "okay"; +}; + +&gpt1 { + status = "okay"; +}; + +&pwm0 { status = "okay"; + pinctrl-0 = <&pwm0_default>; + pinctrl-names = "default"; +}; + +&pwm1 { + status = "okay"; + pinctrl-0 = <&pwm1_default>; + pinctrl-names = "default"; +}; + +&adc0 { + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + /* MB1 AN */ + channel@9 { + reg = <9>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + }; + + /* MB2 AN */ + channel@a { + reg = <10>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + }; + + /* MB1/2 SCL */ + channel@b { + reg = <11>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + }; + + /* MB1/2 SDA */ + channel@c { + reg = <12>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + }; + + /* MB2 CS */ + channel@d { + reg = <13>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + }; + + /* MB1 CS */ + channel@e { + reg = <14>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + }; }; diff --git a/boards/beagle/beagleconnect_freedom/beagleconnect_freedom.yaml b/boards/beagle/beagleconnect_freedom/beagleconnect_freedom.yaml index 46cfaf5de3f..cbe7f154814 100644 --- a/boards/beagle/beagleconnect_freedom/beagleconnect_freedom.yaml +++ b/boards/beagle/beagleconnect_freedom/beagleconnect_freedom.yaml @@ -14,4 +14,6 @@ supported: - spi - uart - hwinfo + - adc + - pwm vendor: beagle diff --git a/boards/beagle/beagleconnect_freedom/beagleconnect_freedom_defconfig b/boards/beagle/beagleconnect_freedom/beagleconnect_freedom_defconfig index 024c0463996..194d0cf76a5 100644 --- a/boards/beagle/beagleconnect_freedom/beagleconnect_freedom_defconfig +++ b/boards/beagle/beagleconnect_freedom/beagleconnect_freedom_defconfig @@ -6,7 +6,6 @@ # CONFIG_GPIO=y -CONFIG_PINCTRL=y CONFIG_BUILD_OUTPUT_HEX=y # custom callback for the antenna switch diff --git a/boards/beagle/beagleconnect_freedom/doc/index.rst b/boards/beagle/beagleconnect_freedom/doc/index.rst index 43a237d0317..8bf3bf4e6e6 100644 --- a/boards/beagle/beagleconnect_freedom/doc/index.rst +++ b/boards/beagle/beagleconnect_freedom/doc/index.rst @@ -1,7 +1,4 @@ -.. _beagleconnect_freedom: - -BeagleConnect Freedom -##################### +.. zephyr:board:: beagleconnect_freedom Overview ******** @@ -9,14 +6,6 @@ Overview BeagleBoard.org BeagleConnect Freedom is a wireless Internet of Things board based on the SimpleLink multi-Standard CC1352P7 wireless MCU. - -.. figure:: img/beagleconnect_freedom.webp - :align: center - :width: 500px - :alt: BeagleBoard.org BeagleConnect Freedom - - BeagleBoard.org BeagleConnect Freedom - Hardware ******** BeagleBoard.org BeagleConnect Freedom board features the TI CC1352P7 wireless microcontroller. @@ -62,6 +51,14 @@ The board configuration supports the following hardware features: +-----------+------------+----------------------+ | I2C | off-chip | BCF_BRIDGE_MCU | +-----------+------------+----------------------+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| RADIO | on-chip | ieee802154 | ++-----------+------------+----------------------+ Connections and IOs =================== diff --git a/boards/beagle/beagleplay/beagleplay_cc1352p7.dts b/boards/beagle/beagleplay/beagleplay_cc1352p7.dts index 858ca21d162..43dd64f9c1c 100644 --- a/boards/beagle/beagleplay/beagleplay_cc1352p7.dts +++ b/boards/beagle/beagleplay/beagleplay_cc1352p7.dts @@ -87,7 +87,7 @@ }; &ieee802154 { - status = "okay"; + status = "disabled"; }; &ieee802154g { diff --git a/boards/beagle/beagleplay/beagleplay_cc1352p7_defconfig b/boards/beagle/beagleplay/beagleplay_cc1352p7_defconfig index b56ce4d3e8d..f722a3a6fd2 100644 --- a/boards/beagle/beagleplay/beagleplay_cc1352p7_defconfig +++ b/boards/beagle/beagleplay/beagleplay_cc1352p7_defconfig @@ -18,3 +18,8 @@ CONFIG_HW_STACK_PROTECTION=y # Adjust for oscillator capacitors CONFIG_CC13X2_CC26X2_XOSC_CAPARRAY_DELTA=0x02 + +# Enable default uart console +CONFIG_SERIAL=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/beagle/beagleplay/doc/beagleplay_cc1352p7.rst b/boards/beagle/beagleplay/doc/beagleplay_cc1352p7.rst index fc36f0ce430..24665eafce1 100644 --- a/boards/beagle/beagleplay/doc/beagleplay_cc1352p7.rst +++ b/boards/beagle/beagleplay/doc/beagleplay_cc1352p7.rst @@ -1,7 +1,4 @@ -.. _beagleplay_cc1352p7: - -BeaglePlay (CC1352) -################### +.. zephyr:board:: beagleplay Overview ******** @@ -10,14 +7,6 @@ BeagleBoard.org BeaglePlay is an open hardware single board computer based on a quad-core ARM Cortex-A53 SoC with an external TI SimpleLink multi-standard CC1352P7 wireless MCU providing long-range, low-power connectivity. - -.. figure:: img/beagle_play.webp - :align: center - :width: 500px - :alt: BeagleBoard.org BeaglePlay - - BeagleBoard.org BeaglePlay - Hardware ******** diff --git a/boards/beagle/beaglev_fire/beaglev_fire_common.dtsi b/boards/beagle/beaglev_fire/beaglev_fire_common.dtsi index 24b1958a9d9..086dabbed84 100644 --- a/boards/beagle/beaglev_fire/beaglev_fire_common.dtsi +++ b/boards/beagle/beaglev_fire/beaglev_fire_common.dtsi @@ -14,6 +14,28 @@ compatible = "beagle,beaglev-fire", "microchip,mpfs"; aliases { }; + + beaglev { + #address-cells = <2>; + #size-cells = <1>; + + ddr_cached_high: memory@1000000000 { + compatible = "mmio-sram"; + reg = <0x10 0x00000000 0x80000000>; /* 2GB */ + }; + }; + + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,sram = &ddr_cached_high; + }; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + clock-frequency = <150000000>; }; &gpio2 { diff --git a/boards/beagle/beaglev_fire/beaglev_fire_polarfire_e51.dts b/boards/beagle/beaglev_fire/beaglev_fire_polarfire_e51.dts index 5a8537124d4..e1556c09528 100644 --- a/boards/beagle/beaglev_fire/beaglev_fire_polarfire_e51.dts +++ b/boards/beagle/beaglev_fire/beaglev_fire_polarfire_e51.dts @@ -21,16 +21,4 @@ status = "disabled"; }; }; - - chosen { - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - zephyr,sram = &sram1; - }; -}; - -&uart0 { - status = "okay"; - current-speed = <115200>; - clock-frequency = <150000000>; }; diff --git a/boards/beagle/beaglev_fire/beaglev_fire_polarfire_e51.yaml b/boards/beagle/beaglev_fire/beaglev_fire_polarfire_e51.yaml index bc5ee3de628..745c033310b 100644 --- a/boards/beagle/beaglev_fire/beaglev_fire_polarfire_e51.yaml +++ b/boards/beagle/beaglev_fire/beaglev_fire_polarfire_e51.yaml @@ -4,7 +4,7 @@ type: mcu arch: riscv toolchain: - zephyr -ram: 3840 +ram: 2048000 testing: ignore_tags: - net diff --git a/boards/beagle/beaglev_fire/beaglev_fire_polarfire_u54.dts b/boards/beagle/beaglev_fire/beaglev_fire_polarfire_u54.dts index 7c4fba300fd..36513a8f651 100644 --- a/boards/beagle/beaglev_fire/beaglev_fire_polarfire_u54.dts +++ b/boards/beagle/beaglev_fire/beaglev_fire_polarfire_u54.dts @@ -5,21 +5,9 @@ model = "beagle,beaglev-fire"; compatible = "beagle,beaglev-fire", "microchip,mpfs"; - chosen { - zephyr,console = &uart1; - zephyr,shell-uart = &uart1; - zephyr,sram = &sram1; - }; - cpus { cpu@0 { status = "disabled"; }; }; }; - -&uart1 { - status = "okay"; - current-speed = <115200>; - clock-frequency = <150000000>; -}; diff --git a/boards/beagle/beaglev_fire/beaglev_fire_polarfire_u54.yaml b/boards/beagle/beaglev_fire/beaglev_fire_polarfire_u54.yaml index 9204225a766..e99022d4a14 100644 --- a/boards/beagle/beaglev_fire/beaglev_fire_polarfire_u54.yaml +++ b/boards/beagle/beaglev_fire/beaglev_fire_polarfire_u54.yaml @@ -4,7 +4,7 @@ type: mcu arch: riscv toolchain: - zephyr -ram: 3840 +ram: 2048000 testing: ignore_tags: - net diff --git a/boards/beagle/beaglev_fire/beaglev_fire_polarfire_u54_smp.dts b/boards/beagle/beaglev_fire/beaglev_fire_polarfire_u54_smp.dts index cf9ed20aa3e..9d81bf66e06 100644 --- a/boards/beagle/beaglev_fire/beaglev_fire_polarfire_u54_smp.dts +++ b/boards/beagle/beaglev_fire/beaglev_fire_polarfire_u54_smp.dts @@ -4,16 +4,4 @@ / { model = "beagle,beaglev-fire"; compatible = "beagle,beaglev-fire", "microchip,mpfs"; - - chosen { - zephyr,console = &uart1; - zephyr,shell-uart = &uart1; - zephyr,sram = &sram1; - }; -}; - -&uart1 { - status = "okay"; - current-speed = <115200>; - clock-frequency = <150000000>; }; diff --git a/boards/beagle/beaglev_fire/beaglev_fire_polarfire_u54_smp.yaml b/boards/beagle/beaglev_fire/beaglev_fire_polarfire_u54_smp.yaml index e8f31601438..809d7fd2c3e 100644 --- a/boards/beagle/beaglev_fire/beaglev_fire_polarfire_u54_smp.yaml +++ b/boards/beagle/beaglev_fire/beaglev_fire_polarfire_u54_smp.yaml @@ -4,7 +4,7 @@ type: mcu arch: riscv toolchain: - zephyr -ram: 3840 +ram: 2048000 testing: ignore_tags: - net diff --git a/boards/beagle/beaglev_fire/doc/index.rst b/boards/beagle/beaglev_fire/doc/index.rst index 23d63f4db7a..4cc146f10a2 100644 --- a/boards/beagle/beaglev_fire/doc/index.rst +++ b/boards/beagle/beaglev_fire/doc/index.rst @@ -1,7 +1,4 @@ -.. _beaglev_fire: - -BeagleV®-Fire -############# +.. zephyr:board:: beaglev_fire Overview ******** @@ -15,18 +12,20 @@ Built around the powerful and energy-efficient RISC-V instruction set architectu its versatile FPGA fabric, BeagleV®-Fire SBC offers unparalleled opportunities for developers, hobbyists, and researchers to explore and experiment with RISC-V technology. -.. image:: img/BeagleV-Fire-Front-Annotated-768x432.webp - :align: center - :alt: beaglev_fire - Building ======== +There are three board configurations provided for the BeagleV-Fire: + +* ``beaglev_fire/polarfire/e51``: Uses only the E51 core +* ``beaglev_fire/polarfire/u54``: Uses the U54 cores +* ``beaglev_fire/polarfire/u54/smp``: Uses the U54 cores with CONFIG_SMP=y + Applications for the ``beaglev_fire`` board configuration can be built as usual: .. zephyr-app-commands:: :zephyr-app: samples/hello_world - :board: beaglev_fire + :board: beaglev_fire/polarfire/u54 :goals: build Debugging @@ -83,3 +82,49 @@ and load the binary: load break main continue + +Flashing +======== +When using the PolarFire `Hart Software Services `_ along with Zephyr, you need to use the `hss-payload-generator `_ tool to generate an image that HSS can boot. + +.. code-block:: yaml + + set-name: 'ZephyrImage' + + # Define the entry point address for each hart (U54 cores) + hart-entry-points: + u54_1: '0x1000000000' + + # Define the payloads (ELF binaries or raw blobs) + payloads: + : + exec-addr: '0x1000000000' # Where Zephyr should be loaded + owner-hart: u54_1 # Primary hart that runs Zephyr + priv-mode: prv_m # Start in Machine mode + skip-opensbi: true # Boot directly without OpenSBI + +After generating the image, you can flash it to the board by restarting a board that's connected over USB and UART, interrupting the HSS boot process with a key press, and then running the ``mmc`` and ``usbdmsc`` commands: + +.. code-block:: bash + + Press a key to enter CLI, ESC to skip + Timeout in 1 second + .[6.304162] Character 100 pressed + [6.308415] Type HELP for list of commands + [6.313276] >> mmc + [10.450867] Selecting SDCARD/MMC (fallback) as boot source ... + [10.457550] Attempting to select eMMC ... Passed + [10.712708] >> usbdmsc + [14.732841] initialize MMC + [14.736400] Attempting to select eMMC ... Passed + [15.168707] MMC - 512 byte pages, 512 byte blocks, 30621696 pages + Waiting for USB Host to connect... (CTRL-C to quit) + . 0 bytes written, 0 bytes read + USB Host connected. Waiting for disconnect... (CTRL-C to quit) + / 0 bytes written, 219136 bytes read + +This will cause the board to appear as a USB mass storage device. You can then then flash the image with ``dd`` or other tools like `BalenaEtcher `_: + +.. code-block:: bash + + dd if= of=/dev/sdXD bs=4M status=progress oflag=sync diff --git a/boards/blues/swan_r5/Kconfig.defconfig b/boards/blues/swan_r5/Kconfig.defconfig index a9d7a1e00b1..44ddb9268d1 100644 --- a/boards/blues/swan_r5/Kconfig.defconfig +++ b/boards/blues/swan_r5/Kconfig.defconfig @@ -9,14 +9,4 @@ config SPI_STM32_INTERRUPT default y depends on SPI -if NETWORKING - -config USB_DEVICE_STACK - default y - -config USB_DEVICE_NETWORK_EEM - default y - -endif # NETWORKING - endif # BOARD_SWAN_R5 diff --git a/boards/blues/swan_r5/doc/index.rst b/boards/blues/swan_r5/doc/index.rst index 6ee06251f30..51212bd4c64 100644 --- a/boards/blues/swan_r5/doc/index.rst +++ b/boards/blues/swan_r5/doc/index.rst @@ -1,7 +1,4 @@ -.. _swan_r5_board: - -Blues Wireless Swan -################### +.. zephyr:board:: swan_r5 Overview ******** @@ -53,10 +50,6 @@ some highlights of the board: - 12-bit ADC, 2 x 12-bit DAC - low-power RTC, and CRC calculation peripherals -.. image:: img/swan.jpg - :align: center - :alt: Blues Wireless Swan - More information about the board can be found at the `Swan Product Page`_. Hardware @@ -222,6 +215,8 @@ You should see the following message on the console: References ********** +.. target-notes:: + .. _Swan Product Page: https://blues.io/products/swan diff --git a/boards/blues/swan_r5/swan_r5.dts b/boards/blues/swan_r5/swan_r5.dts index 221ca274fde..42fb3202217 100644 --- a/boards/blues/swan_r5/swan_r5.dts +++ b/boards/blues/swan_r5/swan_r5.dts @@ -195,7 +195,7 @@ zephyr_udc0: &usbotg_fs { &adc1 { pinctrl-0 = <&adc1_in6_pa1>; pinctrl-names = "default"; - st,adc-clock-source = ; + st,adc-clock-source = "SYNC"; st,adc-prescaler = <4>; status = "okay"; }; diff --git a/boards/bytesatwork/bytesensi_l/Kconfig.defconfig b/boards/bytesatwork/bytesensi_l/Kconfig.defconfig index 52c2d397af8..45628d07f25 100644 --- a/boards/bytesatwork/bytesensi_l/Kconfig.defconfig +++ b/boards/bytesatwork/bytesensi_l/Kconfig.defconfig @@ -3,7 +3,4 @@ if BOARD_BYTESENSI_L -config BT_CTLR - default BT - endif # BOARD_BYTESENSI_L diff --git a/boards/bytesatwork/bytesensi_l/doc/index.rst b/boards/bytesatwork/bytesensi_l/doc/index.rst index 9d16e74d21b..d1b220a778b 100644 --- a/boards/bytesatwork/bytesensi_l/doc/index.rst +++ b/boards/bytesatwork/bytesensi_l/doc/index.rst @@ -1,7 +1,4 @@ -.. _bytesensi_l: - -bytesatwork byteSENSI-L -####################### +.. zephyr:board:: bytesensi_l Overview ******** @@ -9,11 +6,6 @@ Overview The byteSENSI-L is a fun LoRa device based on nRF52 MCU that integrates many sensors. -.. image:: img/byteSENSI-L.jpg - :width: 800px - :align: center - :alt: byteSENSI-L - Hardware ******** diff --git a/boards/cdns/xt-sim/doc/index.rst b/boards/cdns/xt-sim/doc/index.rst index 5f97e597250..f904ae34572 100644 --- a/boards/cdns/xt-sim/doc/index.rst +++ b/boards/cdns/xt-sim/doc/index.rst @@ -1,7 +1,4 @@ -.. _xt-sim: - -Xtensa simulator -################ +.. zephyr:board:: xt-sim Overview ******** @@ -13,12 +10,6 @@ addition to a base ISA to tailor the processor for a particular application. For more information, see https://ip.cadence.com/ipportfolio/tensilica-ip/xtensa-customizable -.. figure:: img/xt-sim.jpg - :align: center - :alt: Xtensa Xplorer (Eclipse base frontend for xt-sim) - - Xtensa Xplorer - Hardware ******** @@ -177,4 +168,6 @@ Build and run as follows: References ********** +.. target-notes:: + .. _Xtensa tools: https://ip.cadence.com/support/sdk-evaluation-request diff --git a/boards/common/ecpprog.board.cmake b/boards/common/ecpprog.board.cmake new file mode 100644 index 00000000000..25aa5914f08 --- /dev/null +++ b/boards/common/ecpprog.board.cmake @@ -0,0 +1,5 @@ +# Copyright (c) 2024 tinyVision.ai Inc. +# SPDX-License-Identifier: Apache-2.0 + +board_set_flasher_ifnset(ecpprog) +board_finalize_runner_args(ecpprog) diff --git a/boards/common/esp32.board.cmake b/boards/common/esp32.board.cmake index ee5bb0d6c39..cfe7b7683fc 100644 --- a/boards/common/esp32.board.cmake +++ b/boards/common/esp32.board.cmake @@ -6,7 +6,7 @@ board_set_debugger_ifnset(openocd) board_runner_args(openocd --no-init --no-halt --no-targets --no-load) board_runner_args(openocd --gdb-init "set remote hardware-watchpoint-limit 2") -board_runner_args(openocd --gdb-init "flushregs") +board_runner_args(openocd --gdb-init "maintenance flush register-cache") board_runner_args(openocd --gdb-init "mon reset halt") board_runner_args(openocd --gdb-init "thb main") diff --git a/boards/common/minichlink.board.cmake b/boards/common/minichlink.board.cmake new file mode 100644 index 00000000000..99f79da0ca0 --- /dev/null +++ b/boards/common/minichlink.board.cmake @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Dhiru Kholia +# SPDX-License-Identifier: Apache-2.0 + +board_set_flasher_ifnset(minichlink) +board_finalize_runner_args(minichlink) diff --git a/boards/common/simics.board.cmake b/boards/common/simics.board.cmake index 792197a54cc..49fe1bfb7cd 100644 --- a/boards/common/simics.board.cmake +++ b/boards/common/simics.board.cmake @@ -1,5 +1,7 @@ -# Copyright (c) 2023 Intel Corporation +# Copyright (c) 2023-2024 Intel Corporation # # SPDX-License-Identifier: Apache-2.0 +set(SUPPORTED_EMU_PLATFORMS simics) + board_finalize_emu_args(simics) diff --git a/boards/common/usb/Kconfig.cdc_acm_serial.defconfig b/boards/common/usb/Kconfig.cdc_acm_serial.defconfig new file mode 100644 index 00000000000..3a5661a98f4 --- /dev/null +++ b/boards/common/usb/Kconfig.cdc_acm_serial.defconfig @@ -0,0 +1,51 @@ +# Copyright (c) 2023-2024 Nordic Semiconductor ASA +# +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_REQUIRES_SERIAL_BACKEND_CDC_ACM + default y + +if BOARD_SERIAL_BACKEND_CDC_ACM + +config SERIAL + default y + +config CONSOLE + default y + +config UART_CONSOLE + default CONSOLE + +config SHELL_BACKEND_SERIAL_CHECK_DTR + default SHELL + depends on UART_LINE_CTRL + +config UART_LINE_CTRL + default SHELL + +config USB_DEVICE_STACK + default y + +config USB_DEVICE_INITIALIZE_AT_BOOT + default y if !MCUBOOT + +config USB_DEVICE_REMOTE_WAKEUP + default n + +if LOG + +choice USB_CDC_ACM_LOG_LEVEL_CHOICE + default USB_CDC_ACM_LOG_LEVEL_OFF +endchoice + +choice USB_DEVICE_LOG_LEVEL_CHOICE + default USB_DEVICE_LOG_LEVEL_OFF +endchoice + +# Wait 4000ms at startup for logging +config LOG_PROCESS_THREAD_STARTUP_DELAY_MS + default 4000 + +endif # LOG + +endif # BOARD_SERIAL_BACKEND_CDC_ACM diff --git a/boards/common/usb/cdc_acm_serial.dtsi b/boards/common/usb/cdc_acm_serial.dtsi new file mode 100644 index 00000000000..14e702fa525 --- /dev/null +++ b/boards/common/usb/cdc_acm_serial.dtsi @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + chosen { + zephyr,console = &board_cdc_acm_uart; + zephyr,shell-uart = &board_cdc_acm_uart; + zephyr,uart-mcumgr = &board_cdc_acm_uart; + zephyr,bt-mon-uart = &board_cdc_acm_uart; + zephyr,bt-c2h-uart = &board_cdc_acm_uart; + }; +}; + +&zephyr_udc0 { + board_cdc_acm_uart: board_cdc_acm_uart { + compatible = "zephyr,cdc-acm-uart"; + }; +}; diff --git a/boards/common/xsdb.board.cmake b/boards/common/xsdb.board.cmake new file mode 100644 index 00000000000..2d95922a9c6 --- /dev/null +++ b/boards/common/xsdb.board.cmake @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Advanced Micro Devices, Inc. +# +# SPDX-License-Identifier: Apache-2.0 +board_set_debugger_ifnset(xsdb) +board_set_flasher_ifnset(xsdb) +board_finalize_runner_args(xsdb) diff --git a/boards/contextualelectronics/abc/Kconfig.defconfig b/boards/contextualelectronics/abc/Kconfig.defconfig index 8568f02c34b..76745cd7b1f 100644 --- a/boards/contextualelectronics/abc/Kconfig.defconfig +++ b/boards/contextualelectronics/abc/Kconfig.defconfig @@ -5,7 +5,4 @@ if BOARD_CONTEXTUALELECTRONICS_ABC -config BT_CTLR - default BT - endif # BOARD_CONTEXTUALELECTRONICS_ABC diff --git a/boards/contextualelectronics/abc/doc/index.rst b/boards/contextualelectronics/abc/doc/index.rst index dd8aa8acfb0..d7f12bc4738 100644 --- a/boards/contextualelectronics/abc/doc/index.rst +++ b/boards/contextualelectronics/abc/doc/index.rst @@ -1,7 +1,4 @@ -.. _contextualelectronics_abc: - -Contextual Electronics Advanced BLE Cell -######################################## +.. zephyr:board:: contextualelectronics_abc Overview ******** @@ -21,12 +18,6 @@ Nordic Semiconductor nRF52840 ARM Cortex-M4F CPU and the following devices: * :abbr:`UART (Universal asynchronous receiver-transmitter)` * Quectel BG95 Modem -.. figure:: img/contextualelectronics_abc.jpg - :align: center - :alt: Contextual Electronics Advanced BLE Cell - - Contextual Electronics Advanced BLE Cell (Credit: Chris Gamell) - More information about the board can be found at the `ABC Board website`_. The `Nordic Semiconductor Infocenter`_ contains the processor's information and the datasheet. diff --git a/boards/croxel/croxel_cx1825/Kconfig.defconfig b/boards/croxel/croxel_cx1825/Kconfig.defconfig index c96e14fea06..b6f6c5ef704 100644 --- a/boards/croxel/croxel_cx1825/Kconfig.defconfig +++ b/boards/croxel/croxel_cx1825/Kconfig.defconfig @@ -3,16 +3,6 @@ if BOARD_CROXEL_CX1825 -config BT_CTLR - default BT - -if LOG - -# Logger cannot use itself to log -choice USB_CDC_ACM_LOG_LEVEL_CHOICE - default USB_CDC_ACM_LOG_LEVEL_OFF -endchoice - -endif # LOG +source "boards/common/usb/Kconfig.cdc_acm_serial.defconfig" endif # BOARD_CROXEL_CX1825 diff --git a/boards/croxel/croxel_cx1825/croxel_cx1825_nrf52840.dts b/boards/croxel/croxel_cx1825/croxel_cx1825_nrf52840.dts index 0aaa70158f8..0dd4d908fa7 100644 --- a/boards/croxel/croxel_cx1825/croxel_cx1825_nrf52840.dts +++ b/boards/croxel/croxel_cx1825/croxel_cx1825_nrf52840.dts @@ -17,8 +17,6 @@ zephyr,sram = &sram0; zephyr,flash = &flash0; zephyr,code-partition = &slot0_partition; - zephyr,console = &cdc_acm_0; - zephyr,shell-uart = &cdc_acm_0; }; leds { @@ -130,12 +128,10 @@ zephyr_udc0: &usbd { compatible = "nordic,nrf-usbd"; status = "okay"; - - cdc_acm_0: cdc_acm_0 { - compatible = "zephyr,cdc-acm-uart"; - }; }; +#include <../boards/common/usb/cdc_acm_serial.dtsi> + &flash0 { partitions { diff --git a/boards/croxel/croxel_cx1825/croxel_cx1825_nrf52840_defconfig b/boards/croxel/croxel_cx1825/croxel_cx1825_nrf52840_defconfig index 8694d118b00..6a76f262ed3 100644 --- a/boards/croxel/croxel_cx1825/croxel_cx1825_nrf52840_defconfig +++ b/boards/croxel/croxel_cx1825/croxel_cx1825_nrf52840_defconfig @@ -10,11 +10,6 @@ CONFIG_HW_STACK_PROTECTION=y # enable GPIO CONFIG_GPIO=y -# Assume we start console by default -CONFIG_USB_DEVICE_INITIALIZE_AT_BOOT=y - -# Console over USB CDC-ACM -CONFIG_USB_DEVICE_STACK=y CONFIG_SERIAL=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y diff --git a/boards/croxel/croxel_cx1825/doc/index.rst b/boards/croxel/croxel_cx1825/doc/index.rst index c2dc41220b7..ab88c4dd432 100644 --- a/boards/croxel/croxel_cx1825/doc/index.rst +++ b/boards/croxel/croxel_cx1825/doc/index.rst @@ -1,7 +1,4 @@ -.. _croxel_cx1825_nrf52840: - -CX1825 nRF52840 -############### +.. zephyr:board:: croxel_cx1825 Overview ******** @@ -24,12 +21,6 @@ Semiconductor nRF52840 ARM Cortex-M4F CPU and the following devices: * :abbr:`USB (Universal Serial Bus)` * :abbr:`WDT (Watchdog Timer)` -.. figure:: img/cx1825_nrf52840.jpg - :align: center - :alt: CX1825 - - Croxel's CX1825 Bluetooth Prototyping board (Credit: Croxel) - Hardware ******** diff --git a/boards/ct/ctcc/Kconfig b/boards/ct/ctcc/Kconfig deleted file mode 100644 index 3a7ec750888..00000000000 --- a/boards/ct/ctcc/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -# CTHINGS.CO Connectivity Card board configuration - -# Copyright (c) 2024 CTHINGS.CO -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_SERIAL_BACKEND_CDC_ACM - bool "USB CDC" - default y - depends on BOARD_CTCC_NRF52840 diff --git a/boards/ct/ctcc/Kconfig.ctcc b/boards/ct/ctcc/Kconfig.ctcc index bdda03b4c0a..7434347751d 100644 --- a/boards/ct/ctcc/Kconfig.ctcc +++ b/boards/ct/ctcc/Kconfig.ctcc @@ -5,3 +5,4 @@ config BOARD_CTCC select SOC_NRF52840_QIAA if BOARD_CTCC_NRF52840 + select SOC_NRF9161_LACA if BOARD_CTCC_NRF9161 || BOARD_CTCC_NRF9161_NS diff --git a/boards/ct/ctcc/Kconfig.defconfig b/boards/ct/ctcc/Kconfig.defconfig index fb74f895a03..298f3d2fe21 100644 --- a/boards/ct/ctcc/Kconfig.defconfig +++ b/boards/ct/ctcc/Kconfig.defconfig @@ -5,54 +5,27 @@ if BOARD_CTCC_NRF52840 -if BOARD_SERIAL_BACKEND_CDC_ACM +source "boards/common/usb/Kconfig.cdc_acm_serial.defconfig" -config USB_DEVICE_STACK - default y - -config USB_CDC_ACM - default SERIAL - -config CONSOLE - default y - -config UART_CONSOLE - default CONSOLE - -config USB_DEVICE_INITIALIZE_AT_BOOT - default y if !MCUBOOT && CONSOLE - -config USB_DEVICE_REMOTE_WAKEUP - default n - -if LOG - -# Turn off logging for USB CDC ACM -choice USB_CDC_ACM_LOG_LEVEL_CHOICE - default USB_CDC_ACM_LOG_LEVEL_OFF -endchoice - -# Turn off logging for USB Device -choice USB_DEVICE_LOG_LEVEL_CHOICE - default USB_DEVICE_LOG_LEVEL_OFF -endchoice - -# Wait 5s at startup for logging -config LOG_PROCESS_THREAD_STARTUP_DELAY_MS - default 5000 +endif # BOARD_CTCC_NRF52840 -endif # LOG +if BOARD_CTCC_NRF9161 || BOARD_CTCC_NRF9161_NS -if USB_DEVICE_STACK +# Workaround for not being able to have commas in macro arguments. +# For explanation please see: boards/nordic/nrf9161dk/Kconfig.defconfig +DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition -config SERIAL - default y +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + depends on BOARD_CTCC_NRF9161 && TRUSTED_EXECUTION_SECURE -endif # USB_DEVICE_STACK +if BOARD_CTCC_NRF9161_NS -endif # BOARD_SERIAL_BACKEND_CDC_ACM +config FLASH_LOAD_OFFSET + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) -config BT_CTLR - default BT +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) -endif # BOARD_CTCC_NRF52840 +endif # BOARD_CTCC_NRF9161_NS +endif # BOARD_CTCC_NRF9161 || BOARD_CTCC_NRF9161_NS diff --git a/boards/ct/ctcc/board.cmake b/boards/ct/ctcc/board.cmake index 3a315c29fbe..11d0511404b 100644 --- a/boards/ct/ctcc/board.cmake +++ b/boards/ct/ctcc/board.cmake @@ -1,6 +1,19 @@ # SPDX-License-Identifier: Apache-2.0 -board_runner_args(nrfjprog "--softreset") -board_runner_args(pyocd "--target=nrf52840" "--frequency=4000000") -include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) -include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) +if(CONFIG_BOARD_CTCC_NRF52840) + board_runner_args(nrfjprog "--softreset") + board_runner_args(pyocd "--target=nrf52840" "--frequency=4000000") + include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) + include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) +elseif(CONFIG_BOARD_CTCC_NRF9161 OR CONFIG_BOARD_CTCC_NRF9161_NS) + if(CONFIG_BOARD_CTCC_NRF9161_NS) + set(TFM_PUBLIC_KEY_FORMAT "full") + endif() + if(CONFIG_TFM_FLASH_MERGED_BINARY) + set_property(TARGET runners_yaml_props_target PROPERTY hex_file tfm_merged.hex) + endif() + board_runner_args(nrfjprog "--softreset") + board_runner_args(pyocd "--target=nrf9161" "--frequency=4000000") + include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) + include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) +endif() diff --git a/boards/ct/ctcc/board.yml b/boards/ct/ctcc/board.yml index b6212047d79..826b1846af5 100644 --- a/boards/ct/ctcc/board.yml +++ b/boards/ct/ctcc/board.yml @@ -1,5 +1,8 @@ board: name: ctcc - full_name: Connectivity Card nRF52840 + full_name: CTHINGS.CO Connectivity Card socs: - name: nrf52840 + - name: nrf9161 + variants: + - name: 'ns' diff --git a/boards/ct/ctcc/ctcc_nrf52840.dts b/boards/ct/ctcc/ctcc_nrf52840.dts index 0e026d1a828..f99cc540e9c 100644 --- a/boards/ct/ctcc/ctcc_nrf52840.dts +++ b/boards/ct/ctcc/ctcc_nrf52840.dts @@ -12,11 +12,6 @@ compatible = "ct,ctcc-nrf52840"; chosen { - zephyr,console = &cdc_acm_uart; - zephyr,shell-uart = &cdc_acm_uart; - zephyr,uart-mcumgr = &cdc_acm_uart; - zephyr,bt-mon-uart = &cdc_acm_uart; - zephyr,bt-c2h-uart = &cdc_acm_uart; zephyr,sram = &sram0; zephyr,flash = &flash0; zephyr,code-partition = &slot0_partition; @@ -58,7 +53,7 @@ label = "image-0"; reg = <0x00012000 0x00076000>; }; - slot1_partition: partition@87000 { + slot1_partition: partition@88000 { label = "image-1"; reg = <0x00088000 0x00074000>; }; @@ -69,6 +64,10 @@ }; }; +®0 { + status = "okay"; +}; + ®1 { regulator-initial-mode = ; }; @@ -88,8 +87,6 @@ zephyr_udc0: &usbd { compatible = "nordic,nrf-usbd"; status = "okay"; - - cdc_acm_uart: cdc_acm_uart { - compatible = "zephyr,cdc-acm-uart"; - }; }; + +#include <../boards/common/usb/cdc_acm_serial.dtsi> diff --git a/boards/ct/ctcc/ctcc_nrf52840.yaml b/boards/ct/ctcc/ctcc_nrf52840.yaml index 06f83148bbf..3f4099b5b87 100644 --- a/boards/ct/ctcc/ctcc_nrf52840.yaml +++ b/boards/ct/ctcc/ctcc_nrf52840.yaml @@ -9,7 +9,7 @@ toolchain: supported: - ble - gpio - - usb_cdc - usb_device - watchdog + - counter vendor: ct diff --git a/boards/ct/ctcc/ctcc_nrf9161-pinctrl.dtsi b/boards/ct/ctcc/ctcc_nrf9161-pinctrl.dtsi new file mode 100644 index 00000000000..c48b2987b85 --- /dev/null +++ b/boards/ct/ctcc/ctcc_nrf9161-pinctrl.dtsi @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2024 CTHINGS.CO + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + uart0_default: uart0_default { + group1 { + psels = , + ; + }; + group2 { + psels = , + ; + }; + }; + + uart0_sleep: uart0_sleep { + group1 { + psels = , + , + , + ; + low-power-enable; + }; + }; + + uart1_default: uart1_default { + group1 { + psels = , + ; + }; + group2 { + psels = , + ; + bias-pull-up; + }; + }; + + uart1_sleep: uart1_sleep { + group1 { + psels = , + , + , + ; + low-power-enable; + }; + }; + + spi3_default: spi3_default { + group1 { + psels = , + , + ; + nordic,drive-mode = ; + }; + }; + + spi3_sleep: spi3_sleep { + group1 { + psels = , + , + ; + low-power-enable; + }; + }; +}; diff --git a/boards/ct/ctcc/ctcc_nrf9161.dts b/boards/ct/ctcc/ctcc_nrf9161.dts new file mode 100644 index 00000000000..6f3d9af92c6 --- /dev/null +++ b/boards/ct/ctcc/ctcc_nrf9161.dts @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2024 CTHINGS.CO + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "ctcc_nrf9161_common.dtsi" + +/ { + chosen { + zephyr,sram = &sram0_s; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + zephyr,sram-secure-partition = &sram0_s; + zephyr,sram-non-secure-partition = &sram0_ns; + }; +}; diff --git a/boards/ct/ctcc/ctcc_nrf9161.yaml b/boards/ct/ctcc/ctcc_nrf9161.yaml new file mode 100644 index 00000000000..8cc32c4068a --- /dev/null +++ b/boards/ct/ctcc/ctcc_nrf9161.yaml @@ -0,0 +1,15 @@ +identifier: ctcc/nrf9161 +name: CTHINGS.CO Connectivity Card nRF9161 +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 88 +flash: 1024 +supported: + - gpio + - watchdog + - counter +vendor: ct diff --git a/boards/ct/ctcc/ctcc_nrf9161_common.dtsi b/boards/ct/ctcc/ctcc_nrf9161_common.dtsi new file mode 100644 index 00000000000..92a2a757c55 --- /dev/null +++ b/boards/ct/ctcc/ctcc_nrf9161_common.dtsi @@ -0,0 +1,91 @@ +/* + * Copyright (c) 2024 CTHINGS.CO + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "ctcc_nrf9161-pinctrl.dtsi" +#include + +/ { + model = "CTHINGS.CO Connectivity Card nRF9161"; + compatible = "ct,ctcc-nrf9161"; + + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,uart-mcumgr = &uart0; + }; + + leds { + compatible = "gpio-leds"; + led1: led_1 { + gpios = <&gpio0 11 GPIO_ACTIVE_LOW>; + label = "LED 1"; + }; + led2: led_2 { + gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; + label = "LED 2"; + }; + }; + + aliases { + led0 = &led1; + led1 = &led2; + mcuboot-led0 = &led1; + bootloader-led0 = &led1; + watchdog0 = &wdt0; + spi-flash0 = &mx25r6435; + }; +}; + +&adc { + status = "okay"; +}; + +&gpiote { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-1 = <&uart0_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&uart1 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart1_default>; + pinctrl-1 = <&uart1_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&spi3 { + compatible = "nordic,nrf-spim"; + status = "okay"; + cs-gpios = <&gpio0 16 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&spi3_default>; + pinctrl-1 = <&spi3_sleep>; + pinctrl-names = "default", "sleep"; + + mx25r6435: mx25r6435fm2il0@0 { + compatible = "jedec,spi-nor"; + status = "disabled"; + reg = <0>; + spi-max-frequency = <10000000>; + size = ; + has-dpd; + dpd-wakeup-sequence = <30000>, <20>, <30000>; + jedec-id = [c2 25 38]; + }; +}; + +/* Include default memory partition configuration file */ +#include diff --git a/boards/ct/ctcc/ctcc_nrf9161_defconfig b/boards/ct/ctcc/ctcc_nrf9161_defconfig new file mode 100644 index 00000000000..c486d832382 --- /dev/null +++ b/boards/ct/ctcc/ctcc_nrf9161_defconfig @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable TrustZone-M +CONFIG_ARM_TRUSTZONE_M=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/ct/ctcc/ctcc_nrf9161_ns.dts b/boards/ct/ctcc/ctcc_nrf9161_ns.dts new file mode 100644 index 00000000000..1c23b0b8410 --- /dev/null +++ b/boards/ct/ctcc/ctcc_nrf9161_ns.dts @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2024 CTHINGS.CO + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "ctcc_nrf9161_common.dtsi" + +/ { + chosen { + zephyr,flash = &flash0; + zephyr,sram = &sram0_ns; + zephyr,code-partition = &slot0_ns_partition; + }; +}; + +/* Disable UART1, because it is used by default in TF-M */ +&uart1 { + status = "disabled"; +}; diff --git a/boards/ct/ctcc/ctcc_nrf9161_ns.yaml b/boards/ct/ctcc/ctcc_nrf9161_ns.yaml new file mode 100644 index 00000000000..67a17c77209 --- /dev/null +++ b/boards/ct/ctcc/ctcc_nrf9161_ns.yaml @@ -0,0 +1,14 @@ +identifier: ctcc/nrf9161/ns +name: CTHINGS.CO Connectivity Card nRF9161 Non Secure +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 128 +flash: 192 +supported: + - gpio + - watchdog +vendor: ct diff --git a/boards/ct/ctcc/ctcc_nrf9161_ns_defconfig b/boards/ct/ctcc/ctcc_nrf9161_ns_defconfig new file mode 100644 index 00000000000..2a74dd56f41 --- /dev/null +++ b/boards/ct/ctcc/ctcc_nrf9161_ns_defconfig @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable TrustZone-M +CONFIG_ARM_TRUSTZONE_M=y + +# This board implies building Non-Secure firmware +CONFIG_TRUSTED_EXECUTION_NONSECURE=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/ct/ctcc/doc/img/ctcc_nrf9161_mpcie.webp b/boards/ct/ctcc/doc/img/ctcc_nrf9161_mpcie.webp new file mode 100644 index 00000000000..20785314c3d Binary files /dev/null and b/boards/ct/ctcc/doc/img/ctcc_nrf9161_mpcie.webp differ diff --git a/boards/ct/ctcc/doc/index.rst b/boards/ct/ctcc/doc/index.rst index 914df63b3aa..97780246a74 100644 --- a/boards/ct/ctcc/doc/index.rst +++ b/boards/ct/ctcc/doc/index.rst @@ -1,24 +1,29 @@ -.. _ctcc_nrf52840: - -CTHINGS.CO Connectivity Card nRF52840 -##################################### +.. zephyr:board:: ctcc Overview ******** -The Connectivity Card nRF52840 enables BLE and IEEE 802.15.4 connectivity -over mPCIe or M.2 using USB port with on-board nRF52840 SoC. +Connectivity Cards come with either M.2 or mPCIe form factor with various SoCs, enabling different +radio interfaces. + +* The Connectivity Card nRF52840 enables BLE and IEEE 802.15.4 over mPCIe or M.2 + using USB device with on-board nRF52840 SoC + +* The Connectivity Card nRF9161 enables LTE-M/NB-IoT and DECT NR+ over mPCIe or M.2 + using on-board USB-UART converter -This board has following features: +Connectivity Card has following features: * CLOCK * FLASH * :abbr:`GPIO (General Purpose Input Output)` * :abbr:`MPU (Memory Protection Unit)` * :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* RADIO (Bluetooth Low Energy and 802.15.4) +* RADIO (Bluetooth Low Energy and 802.15.4) (only nRF52840) +* RADIO (LTE-M/NB-IoT and DECT NR+) (only nRF9161) * :abbr:`RTC (nRF RTC System Clock)` -* :abbr:`USB (Universal Serial Bus)` +* :abbr:`USB (Universal Serial Bus)` (only nRF52840) +* :abbr:`UARTE (Universal asynchronous receiver-transmitter with EasyDMA)` (only nRF9161) * :abbr:`WDT (Watchdog Timer)` .. figure:: img/ctcc_nrf52840_mpcie.webp @@ -33,13 +38,21 @@ This board has following features: ctcc/nrf52840 M.2 board +.. figure:: img/ctcc_nrf9161_mpcie.webp + :align: center + :alt: CTCC nRF9161 mPCIe + + ctcc/nrf9161 mPCIe board + More information about the board can be found at the -`ctcc_nrf52840 Website`_ and for SoC information: `Nordic Semiconductor Infocenter`_. +`Connectivity Cards Website`_ and for SoC information: `Nordic Semiconductor Infocenter`_. Hardware ******** -The ``ctcc/nrf52840`` board target has one external oscillator of the 32.768 kHz. +* The ``ctcc/nrf52840`` board target has one external oscillator of the 32.768 kHz. +* The ``ctcc/nrf9161`` board target has one external SPI NOR 64Mbit memory and one on-board USB-UART + converter (CP210X). Supported Features ================== @@ -70,22 +83,61 @@ hardware features: | WDT | on-chip | watchdog | +-----------+------------+----------------------+ +The ``ctcc/nrf9161`` board target supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| FLASH | external | spi | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| RADIO | on-chip | LTE-M/NB-IoT, | +| | | DECT NR\+ | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| SPU | on-chip | system protection | ++-----------+------------+----------------------+ +| UARTE | on-chip | serial | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + Connections and IOs =================== LED --- -Note that board does not have on-board LEDs, however it exposes +Note that boards do not have on-board LEDs, however they expose LED signals on mPCIe/M.2 pins. +nRF52840: + * LED1 = P0.23 * LED2 = P0.22 +nRF9161: + +* LED1 = P0.11 +* LED2 = P0.12 + Programming and Debugging ************************* -Applications for the ``ctcc/nrf52840`` board target can be +Applications for ``ctcc`` boards can be built in the usual way (see :ref:`build_an_application` for more details). Flashing @@ -94,7 +146,10 @@ Flashing The board supports the following programming options: 1. Using an external :ref:`debug probe ` -2. Using MCUboot with DFU support +2. Using `MCUboot`_ with MCUmgr support + +Below instructions are provided for ``ctcc/nrf52840``, to use ``nrf9161`` target, the USB device configs have +to be replaced with UART configurations. Option 1: Using an External Debug Probe --------------------------------------- @@ -117,58 +172,65 @@ logs on emulated USB port. :board: ctcc/nrf52840 :goals: build flash -Debugging -========= +Option 2: Using MCUboot with MCUmgr support +------------------------------------------- -The ``ctcc/nrf52840`` board target does not have an on-board J-Link debug IC, however -instructions from the :ref:`nordic_segger` page also apply to this board, -with the additional step of connecting an external debugger. +It is also possible to use the MCUboot bootloader with :ref:`mcu_mgr` support to flash +Zephyr applications. + +Install a MCUmgr-compatible tool from :ref:`supported list ` +and make sure MCUboot's ``imgtool`` is available for signing your binary +for MCUboot as described on :ref:`west-sign`. -Option 2: Using MCUboot with DFU support ----------------------------------------- +#. Compile MCUboot as a Zephyr application with ``MCUmgr`` support. -It is also possible to use the MCUboot bootloader with DFU support to flash -Zephyr applications. You need to flash MCUboot with DFU support and fill in slot0 with -some application one-time using Option 1. Then you can re-flash an application using DFU utility -by loading images to slot1. Note, it's not possible to have only MCUboot and load directly -software to slot0 due to DFU implementation in Zephyr, which for present slot0 and slot1 in flash -map, it assumes only slot1 partition as writeable. + .. tabs:: -Install ``dfu-util`` first and make sure MCUboot's ``imgtool`` is -available for signing your binary for MCUboot as described on :ref:`west-sign`. + .. group-tab:: nRF52840 -Next, do the **one-time setup** to flash MCUboot with DFU support. -We'll assume you've cloned the `MCUboot`_ as a submodule when initializing -Zephyr repositories using :ref:`west` tool. + To build the MCUboot: -#. Compile MCUboot as a Zephyr application with DFU support. + .. zephyr-app-commands:: + :app: mcuboot/boot/zephyr + :board: ctcc/nrf52840 + :build-dir: mcuboot + :goals: build - .. zephyr-app-commands:: - :app: mcuboot/boot/zephyr - :board: ctcc/nrf52840 - :build-dir: mcuboot - :goals: build - :gen-args: -DCONFIG_BOOT_USB_DFU_WAIT=y + .. group-tab:: nRF9161 + + To build the MCUboot: + + .. zephyr-app-commands:: + :app: mcuboot/boot/zephyr + :board: ctcc/nrf9161 + :build-dir: mcuboot + :goals: build #. Flash it onto the board as described in Option 1. -#. Flash other Zephyr application to fill in slot0 e.g: +#. Flash other Zephyr application over USB using :ref:`MCUmgr-compatible tool ` and reset target to boot into the image. + + .. tabs:: - .. zephyr-app-commands:: - :zephyr-app: samples/subsys/usb/dfu - :board: ctcc/nrf52840 - :build-dir: dfu - :goals: build - :gen-args: -DCONFIG_BOOTLOADER_MCUBOOT=y -DCONFIG_MCUBOOT_SIGNATURE_KEY_FILE=\"path/to/mcuboot/boot/root-rsa-2048.pem\" + .. group-tab:: nRF52840 -You can now flash a Zephyr application to the board using DFU util. -As an example we'll use the :zephyr:code-sample:`usb-cdc-acm-console` sample. + Build the blinky example with MCUboot support: - .. zephyr-app-commands:: - :zephyr-app: samples/subsys/usb/console - :board: ctcc/nrf52840 - :goals: build flash - :gen-args: -DCONFIG_BOOTLOADER_MCUBOOT=y -DCONFIG_MCUBOOT_SIGNATURE_KEY_FILE=\"path/to/mcuboot/boot/root-rsa-2048.pem\" + .. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: ctcc/nrf52840 + :goals: build + :gen-args: -DCONFIG_BOOTLOADER_MCUBOOT=y -DCONFIG_MCUBOOT_SIGNATURE_KEY_FILE=\"path/to/mcuboot/boot/root-rsa-2048.pem\" + + .. group-tab:: nRF9161 + + Build the blinky example with MCUboot support: + + .. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: ctcc/nrf9161 + :goals: build + :gen-args: -DCONFIG_BOOTLOADER_MCUBOOT=y -DCONFIG_MCUBOOT_SIGNATURE_KEY_FILE=\"path/to/mcuboot/boot/root-rsa-2048.pem\" .. note:: @@ -176,25 +238,26 @@ As an example we'll use the :zephyr:code-sample:`usb-cdc-acm-console` sample. directory. Providing certificate in build args produces signed binary automatically. Do not use this certificate in your production firmware! -#. Plug in ``ctcc/nrf52840`` card to mPCIe/M.2 slot or use mPCIe/M.2 adapter to USB - and plug such adapter to USB port. +Debugging +========= - You should see ``NordicSemiconductor MCUBOOT`` or ``NordicSemiconductor Zephyr DFU sample`` - (if you flashed ``dfu`` sample to slot0) device once plugging it into host - USB port. You can check that on Linux system by entering ``lsusb`` command. +These boards do not have an on-board J-Link debug IC, however +instructions from the :ref:`nordic_segger` page also apply to them, +with the additional step of connecting an external debugger. - To check if DFU device is visible you can enter ``sudo dfu-util -l`` command. Once the - device is visible you can flash Zephyr image using DFU util: ``sudo dfu-util --alt 1 --download build/zephyr/zephyr.signed.bin`` +To test flashed software, plug in ``ctcc`` card to mPCIe/M.2 slot or use mPCIe/M.2 adapter to USB and plug such adapter to USB port. + * For ``ctcc/nrf52840`` check on Linux system by entering ``lsusb`` command if the following device appears: ``NordicSemiconductor MCUBOOT`` or ``NordicSemiconductor USB-DEV`` (when booted into blinky example). + * For ``ctcc/nrf9161`` it's not possible to see a change in ``lsusb`` due to the on-board USB-UART converter. Intead, connect to the UART console using a terminal emulation program of your choice. References ********** .. target-notes:: -.. _ctcc_nrf52840 Website: +.. _Connectivity Cards Website: https://cthings.co/products/connectivity-cards .. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com .. _MCUboot: - https://github.com/JuulLabs-OSS/mcuboot + https://github.com/zephyrproject-rtos/mcuboot diff --git a/boards/cypress/cy8ckit_062_ble/Kconfig.cy8ckit_062_ble b/boards/cypress/cy8ckit_062_ble/Kconfig.cy8ckit_062_ble index 450f6530657..5720120d8de 100644 --- a/boards/cypress/cy8ckit_062_ble/Kconfig.cy8ckit_062_ble +++ b/boards/cypress/cy8ckit_062_ble/Kconfig.cy8ckit_062_ble @@ -1,4 +1,4 @@ -# PSoC6 BLE Pioneer Kit configuration +# PSOC 6 BLE Pioneer Kit configuration # Copyright (c) 2018 Cypress # Copyright (c) 2020 ATL Electronics diff --git a/boards/cypress/cy8ckit_062_ble/board.yml b/boards/cypress/cy8ckit_062_ble/board.yml index 8640f1e7d98..d737b33762e 100644 --- a/boards/cypress/cy8ckit_062_ble/board.yml +++ b/boards/cypress/cy8ckit_062_ble/board.yml @@ -1,6 +1,6 @@ board: name: cy8ckit_062_ble - full_name: PSoC63 BLE Pioneer Kit + full_name: PSOC 63 BLE Pioneer Kit vendor: cypress revision: format: "major.minor.patch" diff --git a/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0.dts b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0.dts index 0fae593a879..b4394a6a910 100644 --- a/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0.dts +++ b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0.dts @@ -11,7 +11,7 @@ #include "cy8ckit_062_ble_common.dtsi" / { - model = "Cypress PSoC6 BLE Pioneer Kit"; + model = "Cypress PSOC 6 BLE Pioneer Kit"; compatible = "cypress,cy8c6xx7_cm0p", "cypress,psoc6"; chosen { diff --git a/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0_0_0_0.yaml b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0_0_0_0.yaml index a8e935bd50a..0ef2e8ae823 100644 --- a/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0_0_0_0.yaml +++ b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0_0_0_0.yaml @@ -6,7 +6,7 @@ # identifier: cy8ckit_062_ble@0.0.0/cy8c6347/m0 -name: Cypress PSoC6 BLE Pioneer Kit (M0, rev. 0.0.0) +name: Cypress PSOC 6 BLE Pioneer Kit (M0, rev. 0.0.0) type: mcu arch: arm ram: 288 diff --git a/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0_1_0_0.yaml b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0_1_0_0.yaml index 27b02fa4bed..032fc65cdf3 100644 --- a/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0_1_0_0.yaml +++ b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0_1_0_0.yaml @@ -6,7 +6,7 @@ # identifier: cy8ckit_062_ble@1.0.0/cy8c6347/m0 -name: Cypress PSoC6 BLE Pioneer Kit (M0, rev. 1.0.0) +name: Cypress PSOC 6 BLE Pioneer Kit (M0, rev. 1.0.0) type: mcu arch: arm ram: 288 diff --git a/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4.dts b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4.dts index e232445e811..81cd184bb1f 100644 --- a/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4.dts +++ b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4.dts @@ -9,13 +9,28 @@ #include #include "cy8ckit_062_ble_common.dtsi" +#include "cy8ckit_062_ble_cy8c6347-pinctrl.dtsi" / { - model = "Cypress PSoC6 BLE Pioneer Kit"; + model = "Cypress PSOC 6 BLE Pioneer Kit"; compatible = "cypress,cy8c6xx7_cm4", "cypress,psoc6"; + aliases { + uart-6 = &uart6; + }; + chosen { zephyr,sram = &sram2; zephyr,flash = &flash1; + zephyr,console = &uart6; + zephyr,shell-uart = &uart6; }; }; + +&uart6 { + status = "okay"; + current-speed = <115200>; + + pinctrl-0 = <&p13_0_scb6_uart_rx &p13_1_scb6_uart_tx>; + pinctrl-names = "default"; +}; diff --git a/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4_0_0_0.overlay b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4_0_0_0.overlay deleted file mode 100644 index 26f422a9b4d..00000000000 --- a/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4_0_0_0.overlay +++ /dev/null @@ -1,26 +0,0 @@ -/* - * Copyright (c) 2021, ATL Electronics - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "cy8ckit_062_ble_cy8c6347-pinctrl.dtsi" - -/ { - aliases { - uart-6 = &uart6; - }; - - chosen { - zephyr,console = &uart6; - zephyr,shell-uart = &uart6; - }; -}; - -&uart6 { - status = "okay"; - current-speed = <115200>; - - pinctrl-0 = <&p13_0_scb6_uart_rx &p13_1_scb6_uart_tx>; - pinctrl-names = "default"; -}; diff --git a/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4_0_0_0.yaml b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4_0_0_0.yaml index 30708da7fa4..1ca0aaa3a11 100644 --- a/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4_0_0_0.yaml +++ b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4_0_0_0.yaml @@ -6,7 +6,7 @@ # identifier: cy8ckit_062_ble@0.0.0/cy8c6347/m4 -name: Cypress PSoC6 BLE Pioneer Kit (M4, rev. 0.0.0) +name: Cypress PSOC 6 BLE Pioneer Kit (M4, rev. 0.0.0) type: mcu arch: arm ram: 288 diff --git a/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4_1_0_0.yaml b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4_1_0_0.yaml index c7572470978..cdfb09a6942 100644 --- a/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4_1_0_0.yaml +++ b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4_1_0_0.yaml @@ -6,7 +6,7 @@ # identifier: cy8ckit_062_ble@1.0.0/cy8c6347/m4 -name: Cypress PSoC6 BLE Pioneer Kit (M4, rev. 1.0.0) +name: Cypress PSOC 6 BLE Pioneer Kit (M4, rev. 1.0.0) type: mcu arch: arm ram: 288 diff --git a/boards/cypress/cy8ckit_062_ble/doc/index.rst b/boards/cypress/cy8ckit_062_ble/doc/index.rst index 46940f0691a..01ad4696ea2 100644 --- a/boards/cypress/cy8ckit_062_ble/doc/index.rst +++ b/boards/cypress/cy8ckit_062_ble/doc/index.rst @@ -1,21 +1,21 @@ .. _cy8ckit_062_ble: -INFINEON PSoC63 BLE Pioneer Kit -############################### +INFINEON PSOC 63 BLE Pioneer Kit +################################ Overview ******** -The PSoC 6 BLE Pioneer Kit (CY8CKIT-062-BLE) is a hardware platform that -enables design and debug of the Cypress PSoC 63 BLE MCU. +The PSOC 6 BLE Pioneer Kit (CY8CKIT-062-BLE) is a hardware platform that +enables design and debug of the Cypress PSOC 63 BLE MCU. -The PSoC 6 BLE Pioneer Kit features the PSoC 63 MCU: a dual-core MCU, with a +The PSOC 6 BLE Pioneer Kit features the PSOC 63 MCU: a dual-core MCU, with a 150-MHz Arm Cortex-M4 as the primary application processor and a 100-MHz Arm Cortex-M0+ that supports low-power operations, 1MB of Flash, 288KB of SRAM, an integrated BLE 4.2 radio, 78 GPIO, 7 programmable analog blocks, 12 programmable digital blocks, and capacitive-sensing with CapSense. -The PSoC 6 BLE Pioneer board offers compatibility with Arduino shields, a +The PSOC 6 BLE Pioneer board offers compatibility with Arduino shields, a 512-Mb NOR flash, onboard programmer/debugger (KitProg2), USB Type-C power delivery system (EZ-PD™ CCG3), 5-segment CapSense slider, two CapSense buttons, one CapSense proximity sensing header, an RGB LED, two user LEDs, @@ -42,45 +42,45 @@ enables the CM4 core. 6. KitProg2 I/O header (J6)1 7. KitProg2 programming/custom application header (J7)1 8. External power supply connector (J9) -9. PSoC 6 BLE user button (SW2) +9. PSOC 6 BLE user button (SW2) 10. KitProg2 application selection button (SW4) 11. Digilent® Pmod™ compatible I/O header (J14)1 12. Power LED (LED4) 13. KitProg2 status LEDs (LED1, LED2, and LED3) -14. PSoC 6 reset button (SW1) -15. PSoC 6 I/O header (J18, J19 and J20) +14. PSOC 6 reset button (SW1) +15. PSOC 6 I/O header (J18, J19 and J20) 16. Arduino™ Uno R3 compatible power header (J1) -17. PSoC 6 debug and trace header (J12) -18. Arduino Uno R3 compatible PSoC 6 I/O header (J2, J3 and J4) -19. PSoC 6 program and debug header (J11) +17. PSOC 6 debug and trace header (J12) +18. Arduino Uno R3 compatible PSOC 6 I/O header (J2, J3 and J4) +19. PSOC 6 program and debug header (J11) 20. KitProg2 programming target selection switch (SW6) 21. CapSense slider and buttons 22. CapSense proximity header (J13) -23. PSoC 6 BLE VDD selection switch (SW5) -24. PSoC 6 BLE power monitoring jumper (J8)2 +23. PSOC 6 BLE VDD selection switch (SW5) +24. PSOC 6 BLE power monitoring jumper (J8)2 25. Arduino Uno R3 compatible ICSP header (J5)1 -26. PSoC 6 user LEDs (LED8 and LED9) +26. PSOC 6 user LEDs (LED8 and LED9) 27. RGB LED (LED5) 28. Cypress 512-Mbit serial NOR Flash memory (S25FL512S, U4) 29. Cypress serial Ferroelectric RAM (U5)1 30. VBACKUP and PMIC control selection switch (SW7)2 -31. Cypress PSoC 6 BLE (CY8C6347BZI-BLD53, U1) +31. Cypress PSOC 6 BLE (CY8C6347BZI-BLD53, U1) 32. BLE Antenna 33. U.FL connector for external antenna (J17)1 34. Cypress main voltage regulator (MB39C022G, U6) -35. KitProg2 (PSoC 5LP) programmer and debugger(CY8C5868LTI-LP039, U2) +35. KitProg2 (PSOC 5LP) programmer and debugger(CY8C5868LTI-LP039, U2) 36. Battery connector (J15)1,2 37. USB PD output voltage (9V/12V) connector (J16) Hardware ******** -For more information about the PSoC 63 BLE MCU SoC and CY8CKIT-062-BLE board: +For more information about the PSOC 63 BLE MCU SoC and CY8CKIT-062-BLE board: -- `PSoC 63 BLE MCU SoC Website`_ -- `PSoC 63 BLE MCU Datasheet`_ -- `PSoC 63 BLE MCU Architecture Reference Manual`_ -- `PSoC 63 BLE MCU Register Reference Manual`_ +- `PSOC 63 BLE MCU SoC Website`_ +- `PSOC 63 BLE MCU Datasheet`_ +- `PSOC 63 BLE MCU Architecture Reference Manual`_ +- `PSOC 63 BLE MCU Register Reference Manual`_ - `CY8CKIT-062-BLE Website`_ - `CY8CKIT-062-BLE User Guide`_ - `CY8CKIT-062-BLE Schematics`_ @@ -118,18 +118,18 @@ Cortex-M4 System Clock ============ -The PSoC 63 BLE MCU SoC is configured to use the internal IMO+FLL as a source for +The PSOC 63 BLE MCU SoC is configured to use the internal IMO+FLL as a source for the system clock. CM0+ works at 50MHz, CM4 - at 100MHz. Other sources for the system clock are provided in the SOC, depending on your system requirements. Serial Port =========== -The PSoC 63 BLE MCU SoC has 8 SCB blocks and each one can be configured as +The PSOC 63 BLE MCU SoC has 8 SCB blocks and each one can be configured as UART/SPI/I2C interfaces for serial communication. At the moment UART5 on SCB5 and UART6 on SCB6 are configured. SCB5 is connected to the onboard KitProg2's USB-UART Bridge working as a serial console interface. SCB6 to P13_0, P13_1 -pins on the J3 of the Arduino Uno R3 compatible PSoC6 I/O header for general +pins on the J3 of the Arduino Uno R3 compatible PSOC 6 I/O header for general purposes. OpenOCD Installation @@ -149,7 +149,7 @@ Programming and Debugging The CY8CKIT-062-BLE includes an onboard programmer/debugger (KitProg2) with mass storage programming to provide debugging, flash programming, and serial -communication over USB. There are also PSoC 6 program and debug headers J11 +communication over USB. There are also PSOC 6 program and debug headers J11 and J12 that can be used with Segger J-Link [default]. A watchdog timer is enabled by default. To disable it call Cy_WDT_Unlock() and Cy_WDT_Disable(). @@ -283,16 +283,18 @@ UART_RTS with UART_CTS from KitProg2. References ********** -.. _PSoC 63 BLE MCU SoC Website: +.. target-notes:: + +.. _PSOC 63 BLE MCU SoC Website: https://www.cypress.com/products/32-bit-arm-cortex-m4-cortex-m0-psoc-63-connectivity-line -.. _PSoC 63 BLE MCU Datasheet: +.. _PSOC 63 BLE MCU Datasheet: https://www.cypress.com/documentation/datasheets/psoc-6-mcu-psoc-63-ble-datasheet-programmable-system-chip-psoc -.. _PSoC 63 BLE MCU Architecture Reference Manual: +.. _PSOC 63 BLE MCU Architecture Reference Manual: https://www.cypress.com/documentation/technical-reference-manuals/psoc-6-mcu-psoc-63-ble-architecture-technical-reference -.. _PSoC 63 BLE MCU Register Reference Manual: +.. _PSOC 63 BLE MCU Register Reference Manual: https://www.cypress.com/documentation/technical-reference-manuals/psoc-6-mcu-cy8c63x6-cy8c63x7-cy8c63x6-cy8c63x7-registers .. _CY8CKIT-062-BLE Website: diff --git a/boards/cypress/cy8ckit_062_wifi_bt/Kconfig.cy8ckit_062_wifi_bt b/boards/cypress/cy8ckit_062_wifi_bt/Kconfig.cy8ckit_062_wifi_bt index e77e648b62a..8f25a09652b 100644 --- a/boards/cypress/cy8ckit_062_wifi_bt/Kconfig.cy8ckit_062_wifi_bt +++ b/boards/cypress/cy8ckit_062_wifi_bt/Kconfig.cy8ckit_062_wifi_bt @@ -1,4 +1,4 @@ -# PSoC6 WiFi-BT Pioneer Kit configuration +# PSOC 6 WiFi-BT Pioneer Kit configuration # Copyright (c) 2018 Cypress # Copyright (c) 2020 ATL Electronics diff --git a/boards/cypress/cy8ckit_062_wifi_bt/board.yml b/boards/cypress/cy8ckit_062_wifi_bt/board.yml index f070d6f3960..c1dd112325a 100644 --- a/boards/cypress/cy8ckit_062_wifi_bt/board.yml +++ b/boards/cypress/cy8ckit_062_wifi_bt/board.yml @@ -1,6 +1,6 @@ board: name: cy8ckit_062_wifi_bt - full_name: PSoC6 WiFi-BT Pioneer Kit + full_name: PSOC 6 WiFi-BT Pioneer Kit vendor: cypress socs: - name: cy8c6247 diff --git a/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m0.dts b/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m0.dts index 73766b76c10..a4cd4709c61 100644 --- a/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m0.dts +++ b/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m0.dts @@ -12,8 +12,8 @@ #include "cy8ckit_062_wifi_bt_cy8c6247-pinctrl.dtsi" / { - model = "cy8ckit_062_wifi_bt_m0 with a Cypress PSoC6 SoC"; - compatible = "cypress,cy8ckit_062_wifi_bt_m0", "cypress,PSoC6"; + model = "cy8ckit_062_wifi_bt_m0 with a Cypress PSOC 6 SoC"; + compatible = "cypress,cy8ckit_062_wifi_bt_m0", "cypress,PSOC6"; aliases { sw0 = &user_bt; diff --git a/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m0.yaml b/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m0.yaml index 3b2372a04dc..4135437c52a 100644 --- a/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m0.yaml +++ b/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m0.yaml @@ -5,7 +5,7 @@ # identifier: cy8ckit_062_wifi_bt/cy8c6247/m0 -name: Cypress PSoC6 WiFi-BT Pioneer Kit (M0) +name: Cypress PSOC 6 WiFi-BT Pioneer Kit (M0) type: mcu arch: arm ram: 288 diff --git a/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m4.dts b/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m4.dts index 29ea4b85134..04bbfa1fb96 100644 --- a/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m4.dts +++ b/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m4.dts @@ -10,8 +10,8 @@ #include "cy8ckit_062_wifi_bt_cy8c6247-pinctrl.dtsi" / { - model = "cy8ckit_062_wifi_bt_m4 with a Cypress PSoC6 SoC"; - compatible = "cypress,cy8ckit_062_wifi_bt_m4", "cypress,PSoC6"; + model = "cy8ckit_062_wifi_bt_m4 with a Cypress PSOC 6 SoC"; + compatible = "cypress,cy8ckit_062_wifi_bt_m4", "cypress,PSOC6"; aliases { uart-5 = &uart5; diff --git a/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m4.yaml b/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m4.yaml index df5c8c0b53b..e861d197140 100644 --- a/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m4.yaml +++ b/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m4.yaml @@ -5,7 +5,7 @@ # identifier: cy8ckit_062_wifi_bt/cy8c6247/m4 -name: Cypress PSoC6 WiFi-BT Pioneer Kit (M4) +name: Cypress PSOC 6 WiFi-BT Pioneer Kit (M4) type: mcu arch: arm ram: 288 diff --git a/boards/cypress/cy8ckit_062_wifi_bt/doc/index.rst b/boards/cypress/cy8ckit_062_wifi_bt/doc/index.rst index d7e20c9bcb0..a0ad601ad63 100644 --- a/boards/cypress/cy8ckit_062_wifi_bt/doc/index.rst +++ b/boards/cypress/cy8ckit_062_wifi_bt/doc/index.rst @@ -1,16 +1,16 @@ .. _cy8ckit_062_wifi_bt: -INFINEON PSoC6 WiFi-BT Pioneer Kit -################################## +INFINEON PSOC 6 WiFi-BT Pioneer Kit +################################### Overview ******** -The PSoC 6 WiFi-BT Pioneer Kit (CY8CKIT-062-WiFi-BT) is a low-cost hardware -platform that enables design and debug of the PSoC 62 MCU and the Murata +The PSOC 6 WiFi-BT Pioneer Kit (CY8CKIT-062-WiFi-BT) is a low-cost hardware +platform that enables design and debug of the PSOC 62 MCU and the Murata LBEE5KL1DX Module (CYW4343W WiFi + Bluetooth Combo Chip). -The PSoC 6 WiFi-BT Pioneer Kit features the PSoC 62 MCU: a +The PSOC 6 WiFi-BT Pioneer Kit features the PSOC 62 MCU: a dual-core MCU, with a 150-MHz Arm Cortex-M4 as the primary application processor and a 100-MHz Arm Cortex-M0+ that supports low-power operations, 1MB of Flash, 288KB of SRAM, 104 GPIO, 7 programmable analog blocks, @@ -18,7 +18,7 @@ processor and a 100-MHz Arm Cortex-M0+ that supports low-power operations, a PDM-PCM digital microphone interface, and industry-leading capacitive-sensing with CapSense. -The PSoC 6 WiFi-BT Pioneer board offers compatibility with Arduino shields. +The PSOC 6 WiFi-BT Pioneer board offers compatibility with Arduino shields. The Cortex-M0+ is a primary core on the board's SoC. It starts first and enables the CM4 core. @@ -35,45 +35,45 @@ enables the CM4 core. 6. KitProg2 I/O header (J6)1 7. KitProg2 programming/custom application header (J7)1 8. External power supply connector (J9) -9. PSoC 6 user button (SW2) +9. PSOC 6 user button (SW2) 10. KitProg2 application selection button (SW4) 11. Digilent® Pmod™ compatible I/O header (J14)1 12. Power LED (LED4) 13. KitProg2 status LEDs (LED1, LED2, and LED3) -14. PSoC 6 reset button (SW1) -15. PSoC 6 I/O header (J18, J19 and J20) +14. PSOC 6 reset button (SW1) +15. PSOC 6 I/O header (J18, J19 and J20) 16. Arduino™ Uno R3 compatible power header (J1) -17. PSoC 6 debug and trace header (J12) -18. Arduino Uno R3 compatible PSoC 6 I/O header (J2, J3 and J4) -19. PSoC 6 program and debug header (J11) +17. PSOC 6 debug and trace header (J12) +18. Arduino Uno R3 compatible PSOC 6 I/O header (J2, J3 and J4) +19. PSOC 6 program and debug header (J11) 20. CapSense proximity header (J13) 21. CapSense slider and buttons -22. PSoC 6 VDD selection switch (SW5) +22. PSOC 6 VDD selection switch (SW5) 23. Cypress 512-Mbit serial NOR Flash memory (S25-FL512S, U4) -24. PSoC 6 user LEDs (LED8 and LED9) +24. PSOC 6 user LEDs (LED8 and LED9) 25. RGB LED (LED5) 26. WiFi/BT module (LBEE5KL 1DX, U6) 27. Cypress serial Ferroelectric RAM (U5)1 28. WiFi-BT Antenna 29. VBACKUP and PMIC control selection switch (SW7)2 -30. PSoC 6 USB device Type-C connector (J28) -31. Cypress PSoC 6 (CY8C6247BZI-D54, U1) -32. PSoC 6 USB Host Type-A connector (J27) +30. PSOC 6 USB device Type-C connector (J28) +31. Cypress PSOC 6 (CY8C6247BZI-D54, U1) +32. PSOC 6 USB Host Type-A connector (J27) 33. Arduino Uno R3 compatible ICSP header (J5)1 -34. PSoC 6 power monitoring jumper (J8)2 -35. KitProg2 (PSoC 5LP) programmer and debugger(CY8C5868LTI-LP039, U2) +34. PSOC 6 power monitoring jumper (J8)2 +35. KitProg2 (PSOC 5LP) programmer and debugger(CY8C5868LTI-LP039, U2) 36. Battery connector (J15)1,2 37. USB PD output voltage (9V/12V) connector (J16) Hardware ******** -For more information about the PSoC 62 MCU SoC and CY8CKIT-062-WiFi-BT board: +For more information about the PSOC 62 MCU SoC and CY8CKIT-062-WiFi-BT board: -- `PSoC 62 MCU SoC Website`_ -- `PSoC 62 MCU Datasheet`_ -- `PSoC 62 MCU Architecture Reference Manual`_ -- `PSoC 62 MCU Register Reference Manual`_ +- `PSOC 62 MCU SoC Website`_ +- `PSOC 62 MCU Datasheet`_ +- `PSOC 62 MCU Architecture Reference Manual`_ +- `PSOC 62 MCU Register Reference Manual`_ - `CY8CKIT-062-WiFi-BT Website`_ - `CY8CKIT-062-WiFi-BT User Guide`_ - `CY8CKIT-062-WiFi-BT Schematics`_ @@ -105,18 +105,18 @@ The default configuration can be found in the Kconfig System Clock ============ -The PSoC 62 MCU SoC is configured to use the internal IMO+FLL as a source for +The PSOC 62 MCU SoC is configured to use the internal IMO+FLL as a source for the system clock. CM0+ works at 50MHz, CM4 - at 100MHz. Other sources for the system clock are provided in the SOC, depending on your system requirements. Serial Port =========== -The PSoC 62 MCU SoC has 9 SCB blocks 8 of each can be configured as UART +The PSOC 62 MCU SoC has 9 SCB blocks 8 of each can be configured as UART interfaces for serial communication. At the moment UART5 on SCB5 and UART6 on SCB6 are configured. SCB5 is connected to the onboard KitProg2's USB-UART Bridge, SCB6 to P12_0, P12_1 pins on the J3 of the Arduino Uno R3 compatible -PSoC6 I/O header. +PSOC 6 I/O header. OpenOCD Installation ==================== @@ -136,7 +136,7 @@ Programming and Debugging The CY8CKIT-062-WiFi-BT includes an onboard programmer/debugger (KitProg2) with mass storage programming to provide debugging, flash programming, and serial -communication over USB. There are also PSoC 6 program and debug headers J11 +communication over USB. There are also PSOC 6 program and debug headers J11 and J12 that can be used with Segger J-Link. A watchdog timer is enabled by default. To disable it call Cy_WDT_Unlock() and Cy_WDT_Disable(). @@ -146,7 +146,7 @@ CM4 core working FW for both cores should be written into Flash. CM0+ FW should starts the CM4 core at one point using Cy_SysEnableCM4(CM4_START_ADDRESS); call. CM4_START_ADDRESS is 0x10060000 in the current configuration. The CM0+/CM4 Flash/SRAM areas are defined in -:zephyr_file:`dts/arm/cypress/psoc6.dtsi`. +:zephyr_file:`dts/arm/infineon/cat1a/legacy/psoc6.dtsi`. Build the project for CM0+ @@ -186,16 +186,18 @@ serial port: References ********** -.. _PSoC 62 MCU SoC Website: +.. target-notes:: + +.. _PSOC 62 MCU SoC Website: https://www.cypress.com/products/32-bit-arm-cortex-m4-psoc-6 -.. _PSoC 62 MCU Datasheet: +.. _PSOC 62 MCU Datasheet: https://www.cypress.com/documentation/datasheets/psoc-6-mcu-psoc-62-datasheet-programmable-system-chip-psoc-preliminary -.. _PSoC 62 MCU Architecture Reference Manual: +.. _PSOC 62 MCU Architecture Reference Manual: https://www.cypress.com/documentation/technical-reference-manuals/psoc-6-mcu-psoc-62-architecture-technical-reference-manual -.. _PSoC 62 MCU Register Reference Manual: +.. _PSOC 62 MCU Register Reference Manual: https://www.cypress.com/documentation/technical-reference-manuals/psoc-6-mcu-psoc-62-register-technical-reference-manual-trm .. _CY8CKIT-062-WiFi-BT Website: diff --git a/boards/deprecated.cmake b/boards/deprecated.cmake index c2b49e34fef..78a960ec2e4 100644 --- a/boards/deprecated.cmake +++ b/boards/deprecated.cmake @@ -13,897 +13,27 @@ # https://docs.zephyrproject.org/latest/develop/api/api_lifecycle.html#deprecated, # so these aliases are eventually removed -set(96b_carbon_DEPRECATED - 96b_carbon/stm32f401xe -) -set(96b_carbon_nrf51_DEPRECATED - 96b_carbon/nrf51822 -) -set(96b_meerkat96_DEPRECATED - 96b_meerkat96/mcimx7d/m4 -) -set(actinius_icarus_bee_ns_DEPRECATED - actinius_icarus_bee/nrf9160/ns -) -set(actinius_icarus_ns_DEPRECATED - actinius_icarus/nrf9160/ns -) -set(actinius_icarus_som_dk_ns_DEPRECATED - actinius_icarus_som_dk/nrf9160/ns -) -set(actinius_icarus_som_ns_DEPRECATED - actinius_icarus_som/nrf9160/ns -) set(adafruit_feather_DEPRECATED adafruit_feather_nrf52840/nrf52840 ) -set(adafruit_feather_nrf52840_DEPRECATED - adafruit_feather_nrf52840/nrf52840 -) -set(adafruit_itsybitsy_nrf52840_DEPRECATED - adafruit_itsybitsy -) -set(adp_xc7k_ae350_DEPRECATED - adp_xc7k -) -set(am62x_m4_phyboard_lyra_DEPRECATED - phyboard_lyra/am6234/m4 -) -set(am62x_m4_sk_DEPRECATED - sk_am62/am6234/m4 -) -set(arduino_giga_r1_m4_DEPRECATED - arduino_giga_r1/stm32h747xx/m4 -) -set(arduino_giga_r1_m7_DEPRECATED - arduino_giga_r1/stm32h747xx/m7 -) -set(arduino_nano_33_ble_sense_DEPRECATED - arduino_nano_33_ble/nrf52840/sense -) -set(arduino_opta_m4_DEPRECATED - arduino_opta/stm32h747xx/m4 -) -set(arduino_portenta_h7_m4_DEPRECATED - arduino_portenta_h7/stm32h747xx/m4 -) -set(arduino_portenta_h7_m7_DEPRECATED - arduino_portenta_h7/stm32h747xx/m7 -) -set(arty_a7_arm_designstart_m1_DEPRECATED - arty_a7/designstart_fpga_cortex_m1 -) -set(arty_a7_arm_designstart_m3_DEPRECATED - arty_a7/designstart_fpga_cortex_m3 -) -set(atsamc21n_xpro_DEPRECATED - samc21n_xpro -) -set(atsamd20_xpro_DEPRECATED - samd20_xpro -) -set(atsamd21_xpro_DEPRECATED - samd21_xpro -) -set(atsame54_xpro_DEPRECATED - same54_xpro -) -set(atsaml21_xpro_DEPRECATED - saml21_xpro -) -set(atsamr21_xpro_DEPRECATED - samr21_xpro -) -set(atsamr34_xpro_DEPRECATED - samr34_xpro -) -set(b_u585i_iot02a_ns_DEPRECATED - b_u585i_iot02a/stm32u585xx/ns -) -set(bcm958402m2_a72_DEPRECATED - bcm958402m2/bcm58402/a72 -) -set(bcm958402m2_m7_DEPRECATED - bcm958402m2/bcm58402/m7 -) -set(bl5340_dvk_cpuapp_DEPRECATED - bl5340_dvk/nrf5340/cpuapp -) -set(bl5340_dvk_cpuapp_ns_DEPRECATED - bl5340_dvk/nrf5340/cpuapp/ns -) -set(bl5340_dvk_cpunet_DEPRECATED - bl5340_dvk/nrf5340/cpunet -) -set(blueclover_plt_demo_v2_nrf52832_DEPRECATED - blueclover_plt_demo_v2 -) -set(circuitdojo_feather_nrf9160_DEPRECATED - circuitdojo_feather -) -set(circuitdojo_feather_nrf9160_ns_DEPRECATED - circuitdojo_feather/nrf9160/ns -) -set(colibri_imx7d_m4_DEPRECATED - colibri_imx7d/mcimx7d/m4 -) -set(cy8ckit_062_ble_m0_DEPRECATED - cy8ckit_062_ble/cy8c6347/m0 -) -set(cy8ckit_062_ble_m4_DEPRECATED - cy8ckit_062_ble/cy8c6347/m4 -) -set(cy8ckit_062_wifi_bt_m0_DEPRECATED - cy8ckit_062_wifi_bt/cy8c6247/m0 -) -set(cy8ckit_062_wifi_bt_m4_DEPRECATED - cy8ckit_062_wifi_bt/cy8c6247/m4 -) -set(cy8ckit_062s4_m4_DEPRECATED - cy8ckit_062s4 -) -set(ebyte_e73_tbb_nrf52832_DEPRECATED - ebyte_e73_tbb -) -set(efm32pg_stk3402a_DEPRECATED - slstk3402a/efm32pg12b500f1024gl125 -) -set(efm32pg_stk3402a_jg_DEPRECATED - slstk3402a/efm32jg12b500f1024gl125 -) -set(efm32hg_slstk3400a_DEPRECATED - slstk3400a -) -set(efm32pg_stk3401a_DEPRECATED - slstk3401a -) -set(efm32gg_stk3701a_DEPRECATED - slstk3701a -) -set(efm32gg_slwstk6121a_DEPRECATED - slwrb4321a -) -set(efr32_radio_brd4104a_DEPRECATED - slwrb4104a -) -set(efr32_radio_brd4161a_DEPRECATED - slwrb4161a -) -set(efr32_radio_brd4170a_DEPRECATED - slwrb4170a -) -set(efr32_radio_brd4180a_DEPRECATED - slwrb4180a -) -set(efr32_radio_brd4187c_DEPRECATED - xg24_rb4187c -) -set(efr32_radio_brd4250b_DEPRECATED - slwrb4250b -) -set(efr32_radio_brd4255a_DEPRECATED - slwrb4255a -) -set(efm32gg_sltb009a_DEPRECATED - sltb009a -) -set(efr32mg_sltb004a_DEPRECATED - sltb004a -) -set(efr32bg22_brd4184a_DEPRECATED - sltb010a@0 -) -set(efr32bg22_brd4184b_DEPRECATED - sltb010a@2 -) -set(efr32xg24_dk2601b_DEPRECATED - xg24_dk2601b -) -set(efr32bg27_brd2602a_DEPRECATED - xg27_dk2602a -) -set(em_starterkit_DEPRECATED - em_starterkit/emsk_em9d -) -set(em_starterkit_em11d_DEPRECATED - em_starterkit@2.3/emsk_em11d -) -set(em_starterkit_em7d_DEPRECATED - em_starterkit@2.3/emsk_em7d -) -set(em_starterkit_em7d_v22_DEPRECATED - em_starterkit@2.2/emsk_em7d -) -set(emsdp_DEPRECATED - emsdp/emsdp_em11d -) -set(emsdp_em4_DEPRECATED - emsdp/emsdp_em4 -) -set(emsdp_em5d_DEPRECATED - emsdp/emsdp_em5d -) -set(emsdp_em6_DEPRECATED - emsdp/emsdp_em6 -) -set(emsdp_em7d_DEPRECATED - emsdp/emsdp_em7d -) -set(emsdp_em7d_esp_DEPRECATED - emsdp/emsdp_em7d_esp -) -set(emsdp_em9d_DEPRECATED - emsdp/emsdp_em9d -) -set(esp32_DEPRECATED - esp32_devkitc_wrover/esp32/procpu -) -set(esp32_devkitc_wroom_DEPRECATED - esp32_devkitc_wroom/esp32/procpu -) -set(esp32_devkitc_wroom_appcpu_DEPRECATED - esp32_devkitc_wroom/esp32/appcpu -) -set(esp32_devkitc_wrover_DEPRECATED - esp32_devkitc_wrover/esp32/procpu -) -set(esp32_devkitc_wrover_appcpu_DEPRECATED - esp32_devkitc_wrover/esp32/appcpu -) -set(esp32_ethernet_kit_DEPRECATED - esp32_ethernet_kit/esp32/procpu -) -set(esp32c3_luatos_core_usb_DEPRECATED - esp32c3_luatos_core/esp32c3/usb -) -set(esp32s3_devkitm_DEPRECATED - esp32s3_devkitm/esp32s3/procpu -) -set(esp32s3_devkitm_appcpu_DEPRECATED - esp32s3_devkitm/esp32s3/appcpu -) -set(esp32s3_luatos_core_DEPRECATED - esp32s3_luatos_core/esp32s3/procpu -) -set(esp32s3_luatos_core_usb_DEPRECATED - esp32s3_luatos_core/esp32s3/procpu/usb -) -set(esp_wrover_kit_DEPRECATED - esp_wrover_kit/esp32/procpu -) -set(fvp_base_revc_2xaemv8a_smp_ns_DEPRECATED - fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a/smp/ns -) -set(fvp_baser_aemv8r_DEPRECATED - fvp_baser_aemv8r/fvp_aemv8r_aarch64 -) -set(fvp_baser_aemv8r_aarch32_DEPRECATED - fvp_baser_aemv8r/fvp_aemv8r_aarch32 -) -set(fvp_baser_aemv8r_aarch32_smp_DEPRECATED - fvp_baser_aemv8r/fvp_aemv8r_aarch32/smp -) -set(fvp_baser_aemv8r_smp_DEPRECATED - fvp_baser_aemv8r/fvp_aemv8r_aarch64/smp -) -set(heltec_wifi_lora32_v2_DEPRECATED - heltec_wifi_lora32_v2/esp32/procpu -) -set(heltec_wireless_stick_lite_v3_DEPRECATED - heltec_wireless_stick_lite_v3/esp32s3/procpu -) -set(hexiwear_k64_DEPRECATED - hexiwear/mk64f12 -) -set(hexiwear_kw40z_DEPRECATED - hexiwear/mkw40z4 -) -set(hifive1_revb_DEPRECATED - hifive1@B -) -set(hsdk_2cores_DEPRECATED - hsdk/arc_hsdk/2cores -) -set(intel_adsp_ace15_mtpm_DEPRECATED - intel_adsp/ace15_mtpm -) -set(intel_adsp_ace20_lnl_DEPRECATED - intel_adsp/ace20_lnl -) -set(intel_adsp_cavs25_DEPRECATED - intel_adsp/cavs25 -) -set(intel_adsp_cavs25_tgph_DEPRECATED - intel_adsp/cavs25/tgph -) -set(intel_ehl_crb_sbl_DEPRECATED - intel_ehl_crb/elkhart_lake/sbl -) -set(kincony_kc868_a32_DEPRECATED - kincony_kc868_a32/esp32/procpu -) -set(longan_nano_lite_DEPRECATED - longan_nano/gd32vf103/lite -) -set(lpcxpresso54114_m0_DEPRECATED - lpcxpresso54114/lpc54114/m0 -) -set(lpcxpresso54114_m4_DEPRECATED - lpcxpresso54114/lpc54114/m4 -) -set(lpcxpresso55s69_cpu0_DEPRECATED - lpcxpresso55s69/lpc55s69/cpu0 -) -set(lpcxpresso55s69_cpu1_DEPRECATED - lpcxpresso55s69/lpc55s69/cpu1 -) -set(lpcxpresso55s69_ns_DEPRECATED - lpcxpresso55s69/lpc55s69/cpu0/ns -) -set(m5stack_atoms3_DEPRECATED - m5stack_atoms3/esp32s3/procpu -) -set(m5stack_atoms3_lite_DEPRECATED - m5stack_atoms3_lite/esp32s3/procpu -) -set(m5stack_core2_DEPRECATED - m5stack_core2/esp32/procpu -) -set(m5stack_stamps3_DEPRECATED - m5stack_stamps3/esp32s3/procpu -) -set(m5stickc_plus_DEPRECATED - m5stickc_plus/esp32/procpu -) -set(mimx8mm_evk_DEPRECATED - imx8mm_evk/mimx8mm6/m4 -) -set(mimx8mm_evk_a53_DEPRECATED - imx8mm_evk/mimx8mm6/a53 -) -set(mimx8mm_evk_a53_smp_DEPRECATED - imx8mm_evk/mimx8mm6/a53/smp -) -set(mimx8mm_phyboard_polis_DEPRECATED - mimx8mm_phyboard_polis/mimx8mm6/m4 -) -set(mimx8mn_evk_a53_DEPRECATED - imx8mn_evk/mimx8mn6/a53 -) -set(mimx8mn_evk_a53_smp_DEPRECATED - imx8mn_evk/mimx8mn6/a53/smp -) -set(mimx8mp_evk_a53_DEPRECATED - imx8mp_evk/mimx8ml8/a53 -) -set(mimx8mp_evk_a53_smp_DEPRECATED - imx8mp_evk/mimx8ml8/a53/smp -) -set(mimx8mp_evk_ddr_DEPRECATED - imx8mp_evk/mimx8ml8/m7/ddr -) -set(mimx8mp_evk_itcm_DEPRECATED - imx8mp_evk/mimx8ml8/m7 -) -set(mimx8mp_phyboard_pollux_DEPRECATED - mimx8mp_phyboard_pollux/mimx8ml8/m7 -) -set(mimx8mq_evk_cm4_DEPRECATED - imx8mq_evk/mimx8mq6/m4 -) -set(mimx93_evk_a55_DEPRECATED - imx93_evk/mimx9352/a55 -) -set(mimxrt1050_evk_qspi_DEPRECATED - mimxrt1050_evk@qspi -) -set(mimxrt1060_evk_hyperflash_DEPRECATED - mimxrt1060_evk@hyperflash -) -set(mimxrt1160_evk_cm4_DEPRECATED - mimxrt1160_evk/mimxrt1166/cm4 -) -set(mimxrt1160_evk_cm7_DEPRECATED - mimxrt1160_evk/mimxrt1166/cm7 -) -set(mimxrt1170_evk_cm4_DEPRECATED - mimxrt1170_evk@A/mimxrt1176/cm4 -) -set(mimxrt1170_evk_cm7_DEPRECATED - mimxrt1170_evk@A/mimxrt1176/cm7 -) -set(mimxrt1170_evkb_cm4_DEPRECATED - mimxrt1170_evk@B/mimxrt1176/cm4 -) -set(mimxrt1170_evkb_cm7_DEPRECATED - mimxrt1170_evk@B/mimxrt1176/cm7 -) -set(mimxrt595_evk_cm33_DEPRECATED - mimxrt595_evk/mimxrt595s/cm33 -) -set(mimxrt685_evk_cm33_DEPRECATED - mimxrt685_evk/mimxrt685s/cm33 -) -set(mps2_an385_DEPRECATED - mps2/an385 -) -set(mps2_an521_DEPRECATED - mps2/an521/cpu0 -) -set(mps2_an521_ns_DEPRECATED - mps2/an521/cpu0/ns -) -set(mps2_an521_remote_DEPRECATED - mps2/an521/cpu1 -) -set(mps3_an547_DEPRECATED - mps3 -) -set(mps3_an547_ns_DEPRECATED - mps3/an547/ns -) - -set(native_posix_64_DEPRECATED - native_posix/native/64 -) - -set(native_sim_64_DEPRECATED - native_sim/native/64 -) - -set(nrf21540dk_nrf52840_DEPRECATED - nrf21540dk -) -set(nrf51dk_nrf51422_DEPRECATED - nrf51dk -) -set(nrf51dongle_nrf51422_DEPRECATED - nrf51dongle -) -set(nrf52833dk_nrf52820_DEPRECATED - nrf52833dk/nrf52820 -) -set(nrf52833dk_nrf52833_DEPRECATED - nrf52833dk/nrf52833 -) -set(nrf52840dk_nrf52811_DEPRECATED - nrf52840dk/nrf52811 -) -set(nrf52840dk_nrf52840_DEPRECATED - nrf52840dk/nrf52840 -) -set(nrf52840dongle_nrf52840_DEPRECATED - nrf52840dongle -) -set(nrf52dk_nrf52805_DEPRECATED - nrf52dk/nrf52805 -) -set(nrf52dk_nrf52810_DEPRECATED - nrf52dk/nrf52810 -) -set(nrf52dk_nrf52832_DEPRECATED - nrf52dk/nrf52832 -) -set(nrf5340_audio_dk_nrf5340_cpuapp_DEPRECATED - nrf5340_audio_dk/nrf5340/cpuapp -) -set(nrf5340_audio_dk_nrf5340_cpuapp_ns_DEPRECATED - nrf5340_audio_dk/nrf5340/cpuapp/ns -) -set(nrf5340_audio_dk_nrf5340_cpunet_DEPRECATED - nrf5340_audio_dk/nrf5340/cpunet -) -set(nrf5340bsim_nrf5340_cpuapp_DEPRECATED - nrf5340bsim/nrf5340/cpuapp -) -set(nrf5340bsim_nrf5340_cpunet_DEPRECATED - nrf5340bsim/nrf5340/cpunet -) -set(nrf5340dk_nrf5340_cpuapp_DEPRECATED - nrf5340dk/nrf5340/cpuapp -) -set(nrf5340dk_nrf5340_cpuapp_ns_DEPRECATED - nrf5340dk/nrf5340/cpuapp/ns -) -set(nrf5340dk_nrf5340_cpunet_DEPRECATED - nrf5340dk/nrf5340/cpunet -) -set(nrf9131ek_nrf9131_DEPRECATED - nrf9131ek -) -set(nrf9131ek_nrf9131_ns_DEPRECATED - nrf9131ek/nrf9131/ns -) -set(nrf9151dk_nrf9151_DEPRECATED - nrf9151dk -) -set(nrf9151dk_nrf9151_ns_DEPRECATED - nrf9151dk/nrf9151/ns -) -set(nrf9160_innblue21_DEPRECATED - innblue21 -) -set(nrf9160_innblue21_ns_DEPRECATED - innblue21/nrf9160/ns -) -set(nrf9160_innblue22_DEPRECATED - innblue22 -) -set(nrf9160_innblue22_ns_DEPRECATED - innblue22/nrf9160/ns -) -set(nrf9160dk_nrf52840_DEPRECATED - nrf9160dk/nrf52840 -) -set(nrf9160dk_nrf9160_DEPRECATED - nrf9160dk/nrf9160 -) -set(nrf9160dk_nrf9160_ns_DEPRECATED - nrf9160dk/nrf9160/ns -) -set(nrf9161dk_nrf9161_DEPRECATED - nrf9161dk -) -set(nrf9161dk_nrf9161_ns_DEPRECATED - nrf9161dk/nrf9161/ns -) -set(nsim_em_DEPRECATED - nsim/nsim_em -) -set(nsim_em11d_DEPRECATED - nsim/nsim_em11d -) -set(nsim_em7d_v22_DEPRECATED - nsim/nsim_em7d_v22 -) -set(nsim_hs_DEPRECATED - nsim/nsim_hs -) -set(nsim_hs3x_hostlink_DEPRECATED - nsim/nsim_hs/hostlink -) -set(nsim_hs5x_DEPRECATED - nsim/nsim_hs5x -) -set(nsim_hs5x_smp_DEPRECATED - nsim/nsim_hs5x/smp -) -set(nsim_hs5x_smp_12cores_DEPRECATED - nsim/nsim_hs5x/smp/12cores -) -set(nsim_hs6x_DEPRECATED - nsim/nsim_hs6x -) -set(nsim_hs6x_smp_DEPRECATED - nsim/nsim_hs6x/smp -) -set(nsim_hs6x_smp_12cores_DEPRECATED - nsim/nsim_hs6x/smp/12cores -) -set(nsim_hs_flash_xip_DEPRECATED - nsim/nsim_hs/flash_xip -) -set(nsim_hs_mpuv6_DEPRECATED - nsim/nsim_hs/mpuv6 -) -set(nsim_hs_smp_DEPRECATED - nsim/nsim_hs/smp -) -set(nsim_hs_sram_DEPRECATED - nsim/nsim_hs/sram -) -set(nsim_sem_DEPRECATED - nsim/nsim_sem -) -set(nsim_sem_mpu_stack_guard_DEPRECATED - nsim/nsim_sem/mpu_stack_guard -) -set(nsim_vpx5_DEPRECATED - nsim/nsim_vpx5 -) -set(nucleo_h745zi_q_m4_DEPRECATED - nucleo_h745zi_q/stm32h745xx/m4 -) -set(nucleo_h745zi_q_m7_DEPRECATED - nucleo_h745zi_q/stm32h745xx/m7 -) -set(nucleo_l452re_p_DEPRECATED - nucleo_l452re/stm32l452xx/p -) -set(nucleo_l552ze_q_ns_DEPRECATED - nucleo_l552ze_q/stm32l552xx/ns -) -set(nuvoton_pfm_m487_DEPRECATED - numaker_pfm_m487 -) -set(nxp_adsp_imx8_DEPRECATED - imx8qm_mek/mimx8qm6/adsp -) -set(nxp_adsp_imx8m_DEPRECATED - imx8mp_evk/mimx8ml8/adsp -) -set(nxp_adsp_imx8ulp_DEPRECATED - imx8ulp_evk/mimx8ud7/adsp -) -set(nxp_adsp_imx8x_DEPRECATED - imx8qxp_mek/mimx8qx6/adsp -) -set(nxp_adsp_rt595_DEPRECATED - mimxrt595_evk/mimxrt595s/f1 -) -set(nxp_ls1046ardb_DEPRECATED - ls1046ardb -) -set(nxp_ls1046ardb_smp_2cores_DEPRECATED - ls1046ardb/ls1046a/smp -) -set(nxp_ls1046ardb_smp_4cores_DEPRECATED - ls1046ardb/ls1046a/smp/4cores -) -set(odroid_go_DEPRECATED - odroid_go/esp32/procpu -) -set(olimex_esp32_evb_DEPRECATED - olimex_esp32_evb/esp32/procpu -) -set(pan1783_evb_cpuapp_DEPRECATED - pan1783_evb/nrf5340/cpuapp -) -set(pan1783_evb_cpunet_DEPRECATED - pan1783_evb/nrf5340/cpunet -) -set(pan1783a_evb_cpuapp_DEPRECATED - pan1783a_evb/nrf5340/cpuapp -) -set(pan1783a_evb_cpunet_DEPRECATED - pan1783a_evb/nrf5340/cpunet -) -set(pan1783a_pa_evb_cpuapp_DEPRECATED - pan1783a_pa_evb/nrf5340/cpuapp -) -set(pan1783a_pa_evb_cpunet_DEPRECATED - pan1783a_pa_evb/nrf5340/cpunet -) -set(phycore_am62x_a53_DEPRECATED - phyboard_lyra/am6234/a53 -) -set(pico_pi_m4_DEPRECATED - pico_pi/mcimx7d/m4 -) -set(qemu_arc_em_DEPRECATED - qemu_arc/qemu_arc_em -) -set(qemu_arc_hs_DEPRECATED - qemu_arc/qemu_arc_hs -) -set(qemu_arc_hs5x_DEPRECATED - qemu_arc/qemu_arc_hs5x -) -set(qemu_arc_hs6x_DEPRECATED - qemu_arc/qemu_arc_hs6x -) -set(qemu_arc_hs_xip_DEPRECATED - qemu_arc/qemu_arc_hs/xip -) -set(qemu_cortex_a53_smp_DEPRECATED - qemu_cortex_a53/qemu_cortex_a53/smp -) -set(qemu_cortex_a53_xip_DEPRECATED - qemu_cortex_a53/qemu_cortex_a53/xip -) -set(qemu_malta_be_DEPRECATED - qemu_malta/qemu_malta/be -) -set(qemu_riscv32_smp_DEPRECATED - qemu_riscv32/qemu_virt_riscv32/smp -) -set(qemu_riscv64_smp_DEPRECATED - qemu_riscv64/qemu_virt_riscv64/smp -) -set(qemu_x86_64_nokpti_DEPRECATED - qemu_x86_64/atom/nokpti -) -set(qemu_x86_nokpti_DEPRECATED - qemu_x86/atom/nokpti -) -set(qemu_x86_nommu_DEPRECATED - qemu_x86/atom/nommu -) -set(qemu_x86_nopae_DEPRECATED - qemu_x86/atom/nopae -) -set(qemu_x86_virt_DEPRECATED - qemu_x86/atom/virt -) -set(qemu_x86_xip_DEPRECATED - qemu_x86/atom/xip -) -set(qemu_xtensa_mmu_DEPRECATED - qemu_xtensa/dc233c/mmu -) -set(rak4631_nrf52840_DEPRECATED - rak4631 -) -set(rak5010_nrf52840_DEPRECATED - rak5010 -) -set(raytac_mdbt50q_db_33_nrf52833_DEPRECATED - raytac_mdbt50q_db_33 -) -set(raytac_mdbt50q_db_40_nrf52840_DEPRECATED - raytac_mdbt50q_db_40 -) -set(raytac_mdbt53_db_40_nrf5340_cpuapp_DEPRECATED - raytac_mdbt53_db_40/nrf5340/cpuapp -) -set(raytac_mdbt53_db_40_nrf5340_cpuapp_ns_DEPRECATED - raytac_mdbt53_db_40/nrf5340/cpuapp/ns -) -set(raytac_mdbt53_db_40_nrf5340_cpunet_DEPRECATED - raytac_mdbt53_db_40/nrf5340/cpunet -) -set(raytac_mdbt53v_db_40_nrf5340_cpuapp_DEPRECATED - raytac_mdbt53v_db_40/nrf5340/cpuapp -) -set(raytac_mdbt53v_db_40_nrf5340_cpuapp_ns_DEPRECATED - raytac_mdbt53v_db_40/nrf5340/cpuapp/ns -) -set(raytac_mdbt53v_db_40_nrf5340_cpunet_DEPRECATED - raytac_mdbt53v_db_40/nrf5340/cpunet -) -set(rcar_h3_salvatorx_cr7_DEPRECATED - rcar_salvator_x/r8a77951/r7 -) -set(rcar_h3ulcb_ca57_DEPRECATED - rcar_h3ulcb/r8a77951/a57 -) -set(rcar_h3ulcb_cr7_DEPRECATED - rcar_h3ulcb/r8a77951/r7 -) -set(rcar_salvator_xs_m3_DEPRECATED - rcar_salvator_xs -) -set(rcar_spider_cr52_DEPRECATED - rcar_spider_s4 -) -set(reel_board_v2_DEPRECATED - reel_board@2 -) -set(roc_rk3568_pc_smp_DEPRECATED - roc_rk3568_pc/rk3568/smp -) -set(rpi_pico_w_DEPRECATED - rpi_pico/rp2040/w -) -set(rv32m1_vega_ri5cy_DEPRECATED - rv32m1_vega/openisa_rv32m1/ri5cy -) -set(rv32m1_vega_zero_riscy_DEPRECATED - rv32m1_vega/openisa_rv32m1/zero_riscy -) -set(s32z270dc2_rtu0_r52_DEPRECATED - s32z2xxdc2/s32z270/rtu0 -) -set(s32z270dc2_rtu1_r52_DEPRECATED - s32z2xxdc2/s32z270/rtu1 -) -set(sam_e70_xplained_DEPRECATED - sam_e70_xplained/same70q21 -) -set(sam_e70b_xplained_DEPRECATED - sam_e70_xplained/same70q21b -) -set(sam_v71_xult_DEPRECATED - sam_v71_xult/samv71q21 -) -set(sam_v71b_xult_DEPRECATED - sam_v71_xult/samv71q21b -) -set(sparkfun_thing_plus_nrf9160_DEPRECATED - sparkfun_thing_plus -) -set(sparkfun_thing_plus_nrf9160_ns_DEPRECATED - sparkfun_thing_plus/nrf9160/ns -) -set(stm32_min_dev_black_DEPRECATED - stm32_min_dev@black -) -set(stm32_min_dev_blue_DEPRECATED - stm32_min_dev@blue -) -set(stm32h747i_disco_m4_DEPRECATED - stm32h747i_disco/stm32h747xx/m4 -) -set(stm32h747i_disco_m7_DEPRECATED - stm32h747i_disco/stm32h747xx/m7 -) -set(stm32l562e_dk_ns_DEPRECATED - stm32l562e_dk/stm32l562xx/ns -) -set(tdk_robokit1_DEPRECATED - robokit1 -) -set(thingy52_nrf52832_DEPRECATED - thingy52 -) -set(thingy53_nrf5340_cpuapp_DEPRECATED - thingy53/nrf5340/cpuapp -) -set(thingy53_nrf5340_cpuapp_ns_DEPRECATED - thingy53/nrf5340/cpuapp/ns -) -set(thingy53_nrf5340_cpunet_DEPRECATED - thingy53/nrf5340/cpunet -) -set(ubx_bmd300eval_nrf52832_DEPRECATED - ubx_bmd300eval -) -set(ubx_bmd330eval_nrf52810_DEPRECATED - ubx_bmd330eval -) -set(ubx_bmd340eval_nrf52840_DEPRECATED - ubx_bmd340eval -) -set(ubx_bmd345eval_nrf52840_DEPRECATED - ubx_bmd345eval -) -set(ubx_bmd360eval_nrf52811_DEPRECATED - ubx_bmd360eval -) -set(ubx_bmd380eval_nrf52840_DEPRECATED - ubx_bmd380eval -) -set(ubx_evkannab1_nrf52832_DEPRECATED - ubx_evkannab1 -) -set(ubx_evkninab1_nrf52832_DEPRECATED - ubx_evkninab1 -) -set(ubx_evkninab3_nrf52840_DEPRECATED - ubx_evkninab3 -) -set(ubx_evkninab4_nrf52833_DEPRECATED - ubx_evkninab4 -) -set(udoo_neo_full_m4_DEPRECATED - udoo_neo_full/mcimx6x/m4 -) -set(v2m_musca_b1_ns_DEPRECATED - v2m_musca_b1/musca_b1/ns -) -set(v2m_musca_s1_ns_DEPRECATED - v2m_musca_s1/musca_s1/ns -) -set(verdin_imx8mp_m7_ddr_DEPRECATED - verdin_imx8mp/mimx8ml8/m7/ddr -) -set(verdin_imx8mp_m7_itcm_DEPRECATED - verdin_imx8mp/mimx8ml8/m7 -) -set(vmu_rt1170_DEPRECATED - vmu_rt1170/mimxrt1176/cm7 -) -set(warp7_m4_DEPRECATED - warp7/mcimx7d/m4 -) -set(we_ophelia1ev_nrf52805_DEPRECATED - we_ophelia1ev +set(qemu_xtensa_DEPRECATED + qemu_xtensa/dc233c ) -set(we_proteus2ev_nrf52832_DEPRECATED - we_proteus2ev +set(mimx8mp_phyboard_pollux/mimx8ml8/m7_DEPRECATED + phyboard_pollux/mimx8ml8/m7 ) -set(we_proteus3ev_nrf52840_DEPRECATED - we_proteus3ev +set(mimx8mm_phyboard_polis/mimx8mm6/m4_DEPRECATED + phyboard_polis/mimx8mm6/m4 ) -set(xenvm_gicv3_DEPRECATED - xenvm/xenvm/gicv3 +set(mimxrt1050_evk_DEPRECATED + mimxrt1050_evk/mimxrt1052/hyperflash ) -set(xiao_ble_sense_DEPRECATED - xiao_ble/nrf52840/sense +set(mimxrt1060_evk_DEPRECATED + mimxrt1060_evk/mimxrt1064/hyperflash ) -set(xiao_esp32s3_DEPRECATED - xiao_esp32s3/esp32s3/procpu +set(mimxrt1060_evk_DEPRECATED + mimxrt1060_evk/mimxrt1062/qspi ) -set(yd_esp32_DEPRECATED - yd_esp32/esp32/procpu +set(mimxrt1060_evkb_DEPRECATED + mimxrt1060_evk@B/mimxrt1062/qspi ) diff --git a/boards/digilent/zybo/Kconfig b/boards/digilent/zybo/Kconfig new file mode 100644 index 00000000000..ae4a701f37f --- /dev/null +++ b/boards/digilent/zybo/Kconfig @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config UART_XLNX_PS + select PINCTRL if BOARD_ZYBO diff --git a/boards/digilent/zybo/zybo_defconfig b/boards/digilent/zybo/zybo_defconfig index bf2bc2777e6..34a1e3204b4 100644 --- a/boards/digilent/zybo/zybo_defconfig +++ b/boards/digilent/zybo/zybo_defconfig @@ -4,7 +4,6 @@ CONFIG_ARM_ARCH_TIMER=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=325000000 -CONFIG_PINCTRL=y CONFIG_SERIAL=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y diff --git a/boards/dptechnics/walter/Kconfig b/boards/dptechnics/walter/Kconfig new file mode 100644 index 00000000000..37d9291d13f --- /dev/null +++ b/boards/dptechnics/walter/Kconfig @@ -0,0 +1,7 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 4096 if BOARD_WALTER_ESP32S3_PROCPU + default 256 if BOARD_WALTER_ESP32S3_APPCPU diff --git a/boards/dptechnics/walter/Kconfig.defconfig b/boards/dptechnics/walter/Kconfig.defconfig deleted file mode 100644 index 642988e72fe..00000000000 --- a/boards/dptechnics/walter/Kconfig.defconfig +++ /dev/null @@ -1,20 +0,0 @@ -# Copyright (c) 2024 DPTechnics bv -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_WALTER_ESP32S3_PROCPU - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 65535 if WIFI && BT - default 51200 if WIFI - default 40960 if BT - default 4096 - -endif # BOARD_WALTER_ESP32S3_PROCPU - -if BOARD_WALTER_ESP32S3_APPCPU - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - default 256 - -endif # BOARD_WALTER_ESP32S3_APPCPU diff --git a/boards/dptechnics/walter/doc/index.rst b/boards/dptechnics/walter/doc/index.rst index bb8d9eecbf5..c77e266f52b 100644 --- a/boards/dptechnics/walter/doc/index.rst +++ b/boards/dptechnics/walter/doc/index.rst @@ -1,7 +1,4 @@ -.. _walter: - -DPTechnics Walter -################# +.. zephyr:board:: walter Overview ******** @@ -11,12 +8,6 @@ with a Sequans Monarch 2 GM02SP LTE-M/NB-IoT/GNSS modem. More information about Walter can be found on the `QuickSpot Website`_ and on the `QuickSpot GitHub page`_. -.. figure:: img/walter.webp - :align: center - :alt: DPTechnics Walter board - - DPTechnics Walter board (Credit: DPTechnics bv) - Hardware ******** diff --git a/boards/dptechnics/walter/walter_esp32s3_appcpu.dts b/boards/dptechnics/walter/walter_esp32s3_appcpu.dts index a2ef2198559..e7e6ff46a86 100644 --- a/boards/dptechnics/walter/walter_esp32s3_appcpu.dts +++ b/boards/dptechnics/walter/walter_esp32s3_appcpu.dts @@ -5,7 +5,7 @@ */ /dts-v1/; -#include +#include "espressif/esp32s3/esp32s3_wroom_n16r2.dtsi" #include / { @@ -13,9 +13,11 @@ compatible = "espressif,esp32s3"; chosen { - zephyr,sram = &sram0; + zephyr,sram = &sram1; zephyr,ipc_shm = &shm0; zephyr,ipc = &ipm0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_appcpu_partition; }; }; diff --git a/boards/dptechnics/walter/walter_esp32s3_procpu.dts b/boards/dptechnics/walter/walter_esp32s3_procpu.dts index 310fa5d59df..8d864885e0f 100644 --- a/boards/dptechnics/walter/walter_esp32s3_procpu.dts +++ b/boards/dptechnics/walter/walter_esp32s3_procpu.dts @@ -22,7 +22,7 @@ }; chosen { - zephyr,sram = &sram0; + zephyr,sram = &sram1; zephyr,console = &usb_serial; zephyr,shell-uart = &usb_serial; zephyr,flash = &flash0; diff --git a/boards/dptechnics/walter/walter_esp32s3_procpu.yaml b/boards/dptechnics/walter/walter_esp32s3_procpu.yaml index 839c29069a7..a26fa60e26b 100644 --- a/boards/dptechnics/walter/walter_esp32s3_procpu.yaml +++ b/boards/dptechnics/walter/walter_esp32s3_procpu.yaml @@ -16,8 +16,4 @@ supported: - pwm - dma - input -testing: - ignore_tags: - - net - - bluetooth vendor: dptechnics diff --git a/boards/dragino/lsn50/doc/index.rst b/boards/dragino/lsn50/doc/index.rst index 4a29c56af1d..999c809a90f 100644 --- a/boards/dragino/lsn50/doc/index.rst +++ b/boards/dragino/lsn50/doc/index.rst @@ -1,7 +1,4 @@ -.. _dragino_lsn50_board: - -Dragino LSN50 LoRA Sensor Node -############################## +.. zephyr:board:: dragino_lsn50 Overview ******** @@ -23,10 +20,6 @@ This kit provides: - GPIOs exposed via screw terminals on the carrier board - Housing -.. image:: img/dragino_lsn50.jpg - :align: center - :alt: Dragino LSN50 - More information about the board can be found at the `Dragino LSN50 website`_. Hardware diff --git a/boards/dragino/nbsn95/doc/index.rst b/boards/dragino/nbsn95/doc/index.rst index 27e32b7d06f..c18bb7eee40 100644 --- a/boards/dragino/nbsn95/doc/index.rst +++ b/boards/dragino/nbsn95/doc/index.rst @@ -1,7 +1,4 @@ -.. _dragino_nbsn95_board: - -Dragino NBSN95 NB-IoT Sensor Node -################################# +.. zephyr:board:: dragino_nbsn95 Overview ******** @@ -22,10 +19,6 @@ This kit provides: - GPIOs exposed via screw terminals on the carrier board - Housing -.. image:: img/dragino_nbsn95.jpg - :align: center - :alt: Dragino NBSN95 - More information about the board can be found at the `Dragino NBSN95 website`_. Hardware diff --git a/boards/ebyte/e73_tbb/Kconfig.defconfig b/boards/ebyte/e73_tbb/Kconfig.defconfig index d3434e975a2..57d28a3f08c 100644 --- a/boards/ebyte/e73_tbb/Kconfig.defconfig +++ b/boards/ebyte/e73_tbb/Kconfig.defconfig @@ -6,7 +6,4 @@ if BOARD_EBYTE_E73_TBB_NRF52832 -config BT_CTLR - default BT - endif # BOARD_EBYTE_E73_TBB_NRF52832 diff --git a/boards/ebyte/e73_tbb/doc/index.rst b/boards/ebyte/e73_tbb/doc/index.rst index 7f18da86159..5d1327e322c 100644 --- a/boards/ebyte/e73_tbb/doc/index.rst +++ b/boards/ebyte/e73_tbb/doc/index.rst @@ -1,7 +1,4 @@ -.. _ebyte_e73_tbb_nrf52832: - -EBYTE E73-TBB -############# +.. zephyr:board:: ebyte_e73_tbb Overview ******** @@ -25,12 +22,6 @@ the following devices: * :abbr:`UART (Universal asynchronous receiver-transmitter)` * :abbr:`WDT (Watchdog Timer)` -.. figure:: img/ebyte_e73_tbb_nrf52832.jpg - :align: center - :alt: EBYTE E73-TBB - - EBYTE E73-TBB (Credit: EBYTE) - More information about the board can be found at the `E73-TBB website`_. The `Nordic Semiconductor Infocenter`_ contains the processor's information and the datasheet. diff --git a/boards/efinix/titanium_ti60_f225/doc/img/ti60f225-board-top.jpg b/boards/efinix/titanium_ti60_f225/doc/img/titanium_ti60_f225.jpg similarity index 100% rename from boards/efinix/titanium_ti60_f225/doc/img/ti60f225-board-top.jpg rename to boards/efinix/titanium_ti60_f225/doc/img/titanium_ti60_f225.jpg diff --git a/boards/efinix/titanium_ti60_f225/doc/index.rst b/boards/efinix/titanium_ti60_f225/doc/index.rst index 1b6430e9309..ec193126434 100644 --- a/boards/efinix/titanium_ti60_f225/doc/index.rst +++ b/boards/efinix/titanium_ti60_f225/doc/index.rst @@ -1,7 +1,4 @@ -.. _titanium_ti60_f225: - -Efinix Titanium Ti60 F225 -######################### +.. zephyr:board:: titanium_ti60_f225 Overview ******** @@ -11,12 +8,6 @@ high performance with the lowest possible power on a small physical size. In add which is a user-configurable RISC-V SoC based on the VexRiscv core with configurable feature set and extension. Using the Efinity IP Manager, you can configure the SoC to include only the peripherals that you require. -.. figure:: img/ti60f225-board-top.jpg - :align: center - :alt: titanium_ti60_f225_board - -Figure is the development board - Board block diagram ******************* diff --git a/boards/electronut/nrf52840_blip/Kconfig.defconfig b/boards/electronut/nrf52840_blip/Kconfig.defconfig index 91ff6042e0c..3d09e0f48e8 100644 --- a/boards/electronut/nrf52840_blip/Kconfig.defconfig +++ b/boards/electronut/nrf52840_blip/Kconfig.defconfig @@ -5,7 +5,4 @@ if BOARD_NRF52840_BLIP -config BT_CTLR - default BT - endif # BOARD_NRF52840_BLIP diff --git a/boards/electronut/nrf52840_blip/doc/index.rst b/boards/electronut/nrf52840_blip/doc/index.rst index 67a736bcd06..03dfff0bf56 100644 --- a/boards/electronut/nrf52840_blip/doc/index.rst +++ b/boards/electronut/nrf52840_blip/doc/index.rst @@ -1,7 +1,4 @@ -.. _nrf52840_blip: - -Electronut Labs Blip -#################### +.. zephyr:board:: nrf52840_blip Overview ******** @@ -25,12 +22,6 @@ nRF52840 ARM Cortex-M4F CPU and the following devices: * :abbr:`USB (Universal Serial Bus)` * :abbr:`WDT (Watchdog Timer)` -.. figure:: img/nrf52840_blip.jpg - :align: center - :alt: Electronut Labs Blip - - Electronut Labs Blip (Credit: Electronut Labs) - More information about the board is available at https://github.com/electronut/ElectronutLabs-blip. Hardware diff --git a/boards/electronut/nrf52840_papyr/Kconfig.defconfig b/boards/electronut/nrf52840_papyr/Kconfig.defconfig index 94d55d43358..d61070ea97b 100644 --- a/boards/electronut/nrf52840_papyr/Kconfig.defconfig +++ b/boards/electronut/nrf52840_papyr/Kconfig.defconfig @@ -5,7 +5,4 @@ if BOARD_NRF52840_PAPYR -config BT_CTLR - default BT - endif # BOARD_NRF52840_PAPYR diff --git a/boards/electronut/nrf52840_papyr/doc/nrf52840_papyr.rst b/boards/electronut/nrf52840_papyr/doc/nrf52840_papyr.rst index 814ef881360..391175eebc2 100644 --- a/boards/electronut/nrf52840_papyr/doc/nrf52840_papyr.rst +++ b/boards/electronut/nrf52840_papyr/doc/nrf52840_papyr.rst @@ -1,7 +1,4 @@ -.. _nrf52840_papyr: - -Electronut Labs Papyr -##################### +.. zephyr:board:: nrf52840_papyr Overview ******** @@ -27,12 +24,6 @@ the following devices: * :abbr:`WDT (Watchdog Timer)` * COUNTER -.. figure:: img/nrf52840_papyr.jpg - :align: center - :alt: Electronut Labs Papyr - - Electronut Labs Papyr (Credit: Electronut Labs) - More information about the board is available at https://gitlab.com/electronutlabs-public/papyr. Hardware diff --git a/boards/element14/warp7/doc/index.rst b/boards/element14/warp7/doc/index.rst index e55de8a80e3..d0940f5271a 100644 --- a/boards/element14/warp7/doc/index.rst +++ b/boards/element14/warp7/doc/index.rst @@ -1,7 +1,4 @@ -.. _warp7: - -WaRP7 - Next Generation IoT and Wearable Development Platform -############################################################# +.. zephyr:board:: warp7 Overview ******** @@ -11,11 +8,6 @@ core and Single Cortex M4 core. Zephyr was ported to run on the M4 core. In a later release, it will also communicate with the A7 core (running Linux) via RPmsg. - -.. image:: warp7.jpg - :align: center - :alt: WaRP7-iMX7S - Hardware ******** diff --git a/boards/element14/warp7/warp7_mcimx7d_m4_defconfig b/boards/element14/warp7/warp7_mcimx7d_m4_defconfig index b62210da43e..90df69ee07b 100644 --- a/boards/element14/warp7/warp7_mcimx7d_m4_defconfig +++ b/boards/element14/warp7/warp7_mcimx7d_m4_defconfig @@ -9,4 +9,3 @@ CONFIG_SERIAL=y CONFIG_UART_INTERRUPT_DRIVEN=y CONFIG_CONSOLE=y CONFIG_XIP=y -CONFIG_PINCTRL=y diff --git a/boards/enclustra/mercury_xu/CMakeLists.txt b/boards/enclustra/mercury_xu/CMakeLists.txt deleted file mode 100644 index f1877356e3b..00000000000 --- a/boards/enclustra/mercury_xu/CMakeLists.txt +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2020, Antmicro -# SPDX-License-Identifier: Apache-2.0 - -zephyr_library() -zephyr_library_sources(board.c) diff --git a/boards/enclustra/mercury_xu/Kconfig b/boards/enclustra/mercury_xu/Kconfig new file mode 100644 index 00000000000..3c03770248c --- /dev/null +++ b/boards/enclustra/mercury_xu/Kconfig @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config UART_XLNX_PS + select PINCTRL if BOARD_MERCURY_XU diff --git a/boards/enclustra/mercury_xu/board.c b/boards/enclustra/mercury_xu/board.c deleted file mode 100644 index db436299a9c..00000000000 --- a/boards/enclustra/mercury_xu/board.c +++ /dev/null @@ -1,16 +0,0 @@ -/* - * Copyright (c) 2020, Antmicro - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include - -static int mercury_xu_init(void) -{ - return 0; -} - -SYS_INIT(mercury_xu_init, PRE_KERNEL_2, - CONFIG_KERNEL_INIT_PRIORITY_DEFAULT); diff --git a/boards/enclustra/mercury_xu/mercury_xu_defconfig b/boards/enclustra/mercury_xu/mercury_xu_defconfig index 10ed71b13c9..d39f536ec21 100644 --- a/boards/enclustra/mercury_xu/mercury_xu_defconfig +++ b/boards/enclustra/mercury_xu/mercury_xu_defconfig @@ -9,5 +9,3 @@ CONFIG_UART_CONSOLE=y # Enable timer CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 - -CONFIG_PINCTRL=y diff --git a/boards/espressif/esp32_devkitc_wroom/Kconfig b/boards/espressif/esp32_devkitc_wroom/Kconfig new file mode 100644 index 00000000000..39114996412 --- /dev/null +++ b/boards/espressif/esp32_devkitc_wroom/Kconfig @@ -0,0 +1,7 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 4096 if BOARD_ESP32_DEVKITC_WROOM_ESP32_PROCPU + default 256 if BOARD_ESP32_DEVKITC_WROOM_ESP32_APPCPU diff --git a/boards/espressif/esp32_devkitc_wroom/Kconfig.defconfig b/boards/espressif/esp32_devkitc_wroom/Kconfig.defconfig deleted file mode 100644 index 374b423b548..00000000000 --- a/boards/espressif/esp32_devkitc_wroom/Kconfig.defconfig +++ /dev/null @@ -1,22 +0,0 @@ -# ESP32 board configuration - -# Copyright (c) 2017 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_ESP32_DEVKITC_WROOM_ESP32_PROCPU - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 65535 if WIFI && BT - default 51200 if WIFI - default 40960 if BT - default 4096 - -endif # BOARD_ESP32_DEVKITC_WROOM_ESP32_PROCPU - -if BOARD_ESP32_DEVKITC_WROOM_ESP32_APPCPU - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - default 4096 - -endif # BOARD_ESP32_DEVKITC_WROOM_ESP32_APPCPU diff --git a/boards/espressif/esp32_devkitc_wroom/doc/index.rst b/boards/espressif/esp32_devkitc_wroom/doc/index.rst index 4107dbf6cfe..228660a603a 100644 --- a/boards/espressif/esp32_devkitc_wroom/doc/index.rst +++ b/boards/espressif/esp32_devkitc_wroom/doc/index.rst @@ -1,7 +1,4 @@ -.. _esp32_devkitc_wroom: - -ESP32-DevKitC-WROOM -################### +.. zephyr:board:: esp32_devkitc_wroom Overview ******** @@ -41,12 +38,6 @@ The features include the following: - Cryptographic hardware acceleration (RNG, ECC, RSA, SHA-2, AES) - 5uA deep sleep current -.. figure:: img/esp32_devkitc_wroom.jpg - :align: center - :alt: ESP32-DevKitC-WROOM - - ESP32-DevKitC-WROOM-32D DK - For more information, check the datasheet at `ESP32 Datasheet`_ or the technical reference manual at `ESP32 Technical Reference Manual`_. @@ -292,6 +283,8 @@ GDB stub is enabled on ESP32. References ********** +.. target-notes:: + .. _`ESP32-DevKitC-WROOM`: https://docs.espressif.com/projects/esp-idf/en/stable/esp32/hw-reference/esp32/get-started-devkitc.html# .. _`ESP32 Datasheet`: https://www.espressif.com/sites/default/files/documentation/esp32_datasheet_en.pdf .. _`ESP32 Technical Reference Manual`: https://espressif.com/sites/default/files/documentation/esp32_technical_reference_manual_en.pdf diff --git a/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_appcpu.dts b/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_appcpu.dts index e86ffdb90bf..c88ae757867 100644 --- a/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_appcpu.dts +++ b/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_appcpu.dts @@ -13,9 +13,11 @@ compatible = "espressif,esp32"; chosen { - zephyr,sram = &sram0; + zephyr,sram = &sram1; zephyr,ipc_shm = &shm0; zephyr,ipc = &ipm0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_appcpu_partition; }; }; diff --git a/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_procpu.dts b/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_procpu.dts index fb3075c028e..783a8f2a7f7 100644 --- a/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_procpu.dts +++ b/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_procpu.dts @@ -32,7 +32,7 @@ }; chosen { - zephyr,sram = &sram0; + zephyr,sram = &sram1; zephyr,console = &uart0; zephyr,shell-uart = &uart0; zephyr,flash = &flash0; diff --git a/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_procpu.yaml b/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_procpu.yaml index 88e22e7b170..7bc3c8feb55 100644 --- a/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_procpu.yaml +++ b/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_procpu.yaml @@ -18,8 +18,4 @@ supported: - counter - entropy - input -testing: - ignore_tags: - - net - - bluetooth vendor: espressif diff --git a/boards/espressif/esp32_devkitc_wrover/Kconfig b/boards/espressif/esp32_devkitc_wrover/Kconfig new file mode 100644 index 00000000000..6442ca47279 --- /dev/null +++ b/boards/espressif/esp32_devkitc_wrover/Kconfig @@ -0,0 +1,7 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 4096 if BOARD_ESP32_DEVKITC_WROVER_ESP32_PROCPU + default 256 if BOARD_ESP32_DEVKITC_WROVER_ESP32_APPCPU diff --git a/boards/espressif/esp32_devkitc_wrover/Kconfig.defconfig b/boards/espressif/esp32_devkitc_wrover/Kconfig.defconfig deleted file mode 100644 index c56c404a40e..00000000000 --- a/boards/espressif/esp32_devkitc_wrover/Kconfig.defconfig +++ /dev/null @@ -1,20 +0,0 @@ -# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_ESP32_DEVKITC_WROVER_ESP32_PROCPU - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 65535 if WIFI && BT - default 51200 if WIFI - default 40960 if BT - default 4096 - -endif # BOARD_ESP32_DEVKITC_WROVER_ESP32_PROCPU - -if BOARD_ESP32_DEVKITC_WROVER_ESP32_APPCPU - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - default 4096 - -endif # BOARD_ESP32_DEVKITC_WROVER_ESP32_APPCPU diff --git a/boards/espressif/esp32_devkitc_wrover/doc/index.rst b/boards/espressif/esp32_devkitc_wrover/doc/index.rst index 79bb94f6b1a..cf1fb64f32f 100644 --- a/boards/espressif/esp32_devkitc_wrover/doc/index.rst +++ b/boards/espressif/esp32_devkitc_wrover/doc/index.rst @@ -1,7 +1,4 @@ -.. _esp32_devkitc_wrover: - -ESP32-DevKitC-WROVER -#################### +.. zephyr:board:: esp32_devkitc_wrover Overview ******** @@ -41,12 +38,6 @@ The features include the following: - Cryptographic hardware acceleration (RNG, ECC, RSA, SHA-2, AES) - 5uA deep sleep current -.. figure:: img/esp32_devkitc_wrover.jpg - :align: center - :alt: ESP32-DevKitC-WROVER - - ESP32-DevKitC-WROVER-IE - For more information, check the datasheet at `ESP32 Datasheet`_ or the technical reference manual at `ESP32 Technical Reference Manual`_. @@ -292,6 +283,8 @@ GDB stub is enabled on ESP32. References ********** +.. target-notes:: + .. _`ESP32-DevKitC-WROVER`: https://docs.espressif.com/projects/esp-idf/en/stable/esp32/hw-reference/esp32/get-started-devkitc.html# .. _`ESP32 Datasheet`: https://www.espressif.com/sites/default/files/documentation/esp32_datasheet_en.pdf .. _`ESP32 Technical Reference Manual`: https://espressif.com/sites/default/files/documentation/esp32_technical_reference_manual_en.pdf diff --git a/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_appcpu.dts b/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_appcpu.dts index 81078114c97..f6fb39576f2 100644 --- a/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_appcpu.dts +++ b/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_appcpu.dts @@ -13,9 +13,11 @@ compatible = "espressif,esp32"; chosen { - zephyr,sram = &sram0; + zephyr,sram = &sram1; zephyr,ipc_shm = &shm0; zephyr,ipc = &ipm0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_appcpu_partition; }; }; diff --git a/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_procpu.dts b/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_procpu.dts index df8e3c019fc..33f0f3f134b 100644 --- a/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_procpu.dts +++ b/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_procpu.dts @@ -9,7 +9,7 @@ #include "esp32_devkitc_wrover-pinctrl.dtsi" #include #include -#include +#include / { model = "Espressif ESP32-DevkitC WROVER-E PROCPU"; @@ -32,7 +32,7 @@ }; chosen { - zephyr,sram = &sram0; + zephyr,sram = &sram1; zephyr,console = &uart0; zephyr,shell-uart = &uart0; zephyr,flash = &flash0; diff --git a/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_procpu.yaml b/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_procpu.yaml index a2089253a3c..62e40f71e93 100644 --- a/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_procpu.yaml +++ b/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_procpu.yaml @@ -18,8 +18,4 @@ supported: - counter - entropy - input -testing: - ignore_tags: - - net - - bluetooth vendor: espressif diff --git a/boards/espressif/esp32_ethernet_kit/Kconfig b/boards/espressif/esp32_ethernet_kit/Kconfig new file mode 100644 index 00000000000..a6297194caf --- /dev/null +++ b/boards/espressif/esp32_ethernet_kit/Kconfig @@ -0,0 +1,7 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 4096 if BOARD_ESP32_ETHERNET_KIT_ESP32_PROCPU + default 256 if BOARD_ESP32_ETHERNET_KIT_ESP32_APPCPU diff --git a/boards/espressif/esp32_ethernet_kit/Kconfig.defconfig b/boards/espressif/esp32_ethernet_kit/Kconfig.defconfig index 75b0cc9f631..5a36768659d 100644 --- a/boards/espressif/esp32_ethernet_kit/Kconfig.defconfig +++ b/boards/espressif/esp32_ethernet_kit/Kconfig.defconfig @@ -12,18 +12,4 @@ choice SPIRAM_TYPE default SPIRAM_TYPE_ESPPSRAM64 endchoice -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 65535 if WIFI && BT - default 51200 if WIFI - default 40960 if BT - default 4096 - endif # BOARD_ESP32_ETHERNET_KIT_ESP32_PROCPU - -if BOARD_ESP32_ETHERNET_KIT_ESP32_APPCPU - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - default 4096 - -endif # BOARD_ESP32_ETHERNET_KIT_ESP32_APPCPU diff --git a/boards/espressif/esp32_ethernet_kit/doc/img/esp32-ethernet-kit-v1.2-overview.jpg b/boards/espressif/esp32_ethernet_kit/doc/img/esp32_ethernet_kit.jpg similarity index 100% rename from boards/espressif/esp32_ethernet_kit/doc/img/esp32-ethernet-kit-v1.2-overview.jpg rename to boards/espressif/esp32_ethernet_kit/doc/img/esp32_ethernet_kit.jpg diff --git a/boards/espressif/esp32_ethernet_kit/doc/index.rst b/boards/espressif/esp32_ethernet_kit/doc/index.rst index 4437e479bdf..7233284d314 100644 --- a/boards/espressif/esp32_ethernet_kit/doc/index.rst +++ b/boards/espressif/esp32_ethernet_kit/doc/index.rst @@ -1,7 +1,4 @@ -.. _esp32_ethernet_kit: - -ESP32-Ethernet-Kit -################## +.. zephyr:board:: esp32_ethernet_kit Overview ******** @@ -13,13 +10,6 @@ over Ethernet (PoE). .. _get-started-esp32-ethernet-kit-v1.2-overview: -.. figure:: img/esp32-ethernet-kit-v1.2-overview.jpg - :align: center - :alt: ESP32-Ethernet-Kit V1.2 - :figclass: align-center - - ESP32-Ethernet-Kit V1.2 Overview - ESP32-Ethernet-Kit is an ESP32-WROVER-E based development. For more information, check the datasheet at `ESP32-WROVER-E Datasheet`_. @@ -615,6 +605,8 @@ during board initialization (board_init.c) References ********** +.. target-notes:: + .. _`ESP32-Ethernet-Kit V1.2 Ethernet Board (A) Schematic`: https://dl.espressif.com/dl/schematics/SCH_ESP32-Ethernet-Kit_A_V1.2_20200528.pdf .. _`ESP32-WROVER-E Datasheet`: https://www.espressif.com/sites/default/files/documentation/esp32-wrover-e_esp32-wrover-ie_datasheet_en.pdf .. _`OpenOCD ESP32`: https://github.com/espressif/openocd-esp32/releases diff --git a/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_appcpu.dts b/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_appcpu.dts index 24b4fd8271f..c4a99a62ef9 100644 --- a/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_appcpu.dts +++ b/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_appcpu.dts @@ -13,9 +13,11 @@ compatible = "espressif,esp32"; chosen { - zephyr,sram = &sram0; + zephyr,sram = &sram1; zephyr,ipc_shm = &shm0; zephyr,ipc = &ipm0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_appcpu_partition; }; }; diff --git a/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_procpu.dts b/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_procpu.dts index 61838ea748a..91446897fc4 100644 --- a/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_procpu.dts +++ b/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_procpu.dts @@ -19,7 +19,7 @@ }; chosen { - zephyr,sram = &sram0; + zephyr,sram = &sram1; zephyr,console = &uart0; zephyr,shell-uart = &uart0; zephyr,flash = &flash0; diff --git a/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_procpu.yaml b/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_procpu.yaml index ca098c1ef77..fb3c3cdd704 100644 --- a/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_procpu.yaml +++ b/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_procpu.yaml @@ -10,8 +10,4 @@ supported: - uart - nvs - pwm -testing: - ignore_tags: - - net - - bluetooth vendor: espressif diff --git a/boards/espressif/esp32c3_devkitc/Kconfig b/boards/espressif/esp32c3_devkitc/Kconfig new file mode 100644 index 00000000000..c6a99b1032d --- /dev/null +++ b/boards/espressif/esp32c3_devkitc/Kconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 4096 diff --git a/boards/espressif/esp32c3_devkitc/Kconfig.defconfig b/boards/espressif/esp32c3_devkitc/Kconfig.defconfig deleted file mode 100644 index 2e71f23c2d7..00000000000 --- a/boards/espressif/esp32c3_devkitc/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# ESP32C3 devkitc board configuration - -# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 65535 if WIFI && BT - default 51200 if WIFI - default 40960 if BT - default 4096 diff --git a/boards/espressif/esp32c3_devkitc/doc/img/esp32c3_devkitc.webp b/boards/espressif/esp32c3_devkitc/doc/img/esp32c3_devkitc.webp new file mode 100644 index 00000000000..5f2dc9e6c3d Binary files /dev/null and b/boards/espressif/esp32c3_devkitc/doc/img/esp32c3_devkitc.webp differ diff --git a/boards/espressif/esp32c3_devkitc/doc/index.rst b/boards/espressif/esp32c3_devkitc/doc/index.rst index 97ce7f181b5..a57d0be2623 100644 --- a/boards/espressif/esp32c3_devkitc/doc/index.rst +++ b/boards/espressif/esp32c3_devkitc/doc/index.rst @@ -1,7 +1,4 @@ -.. _esp32c3_devkitc: - -ESP32-C3-DevKitC -################ +.. zephyr:board:: esp32c3_devkitc Overview ******** @@ -246,6 +243,8 @@ You can debug an application in the usual way. Here is an example for the :zephy References ********** +.. target-notes:: + .. _`ESP32-C3-DevKitC`: https://docs.espressif.com/projects/esp-dev-kits/en/latest/esp32c3/esp32-c3-devkitc-02/index.html .. _`ESP32-C3 Datasheet`: https://www.espressif.com/sites/default/files/documentation/esp32-c3_datasheet_en.pdf .. _`ESP32-C3 Technical Reference Manual`: https://espressif.com/sites/default/files/documentation/esp32-c3_technical_reference_manual_en.pdf diff --git a/boards/espressif/esp32c3_devkitc/esp32c3_devkitc.dts b/boards/espressif/esp32c3_devkitc/esp32c3_devkitc.dts index c009ccb0d0a..86326fcc077 100644 --- a/boards/espressif/esp32c3_devkitc/esp32c3_devkitc.dts +++ b/boards/espressif/esp32c3_devkitc/esp32c3_devkitc.dts @@ -16,7 +16,7 @@ compatible = "espressif,esp32c3"; chosen { - zephyr,sram = &sram0; + zephyr,sram = &sram1; zephyr,console = &uart0; zephyr,shell-uart = &uart0; zephyr,flash = &flash0; diff --git a/boards/espressif/esp32c3_devkitc/esp32c3_devkitc.yaml b/boards/espressif/esp32c3_devkitc/esp32c3_devkitc.yaml index 876ee788553..f2b98e3e4ed 100644 --- a/boards/espressif/esp32c3_devkitc/esp32c3_devkitc.yaml +++ b/boards/espressif/esp32c3_devkitc/esp32c3_devkitc.yaml @@ -15,8 +15,4 @@ supported: - spi - counter - entropy -testing: - ignore_tags: - - net - - bluetooth vendor: espressif diff --git a/boards/espressif/esp32c3_devkitm/Kconfig b/boards/espressif/esp32c3_devkitm/Kconfig new file mode 100644 index 00000000000..c6a99b1032d --- /dev/null +++ b/boards/espressif/esp32c3_devkitm/Kconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 4096 diff --git a/boards/espressif/esp32c3_devkitm/Kconfig.defconfig b/boards/espressif/esp32c3_devkitm/Kconfig.defconfig deleted file mode 100644 index cf5aeac8382..00000000000 --- a/boards/espressif/esp32c3_devkitm/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# ESP32C3 devkitm board configuration - -# Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 65535 if WIFI && BT - default 51200 if WIFI - default 40960 if BT - default 4096 diff --git a/boards/espressif/esp32c3_devkitm/doc/img/esp32c3_devkitm.webp b/boards/espressif/esp32c3_devkitm/doc/img/esp32c3_devkitm.webp new file mode 100644 index 00000000000..d28264253d7 Binary files /dev/null and b/boards/espressif/esp32c3_devkitm/doc/img/esp32c3_devkitm.webp differ diff --git a/boards/espressif/esp32c3_devkitm/doc/index.rst b/boards/espressif/esp32c3_devkitm/doc/index.rst index aed67104255..24eb23bc7b8 100644 --- a/boards/espressif/esp32c3_devkitm/doc/index.rst +++ b/boards/espressif/esp32c3_devkitm/doc/index.rst @@ -1,7 +1,4 @@ -.. _esp32c3_devkitm: - -ESP32-C3-DevKitM -################ +.. zephyr:board:: esp32c3_devkitm Overview ******** @@ -246,6 +243,8 @@ You can debug an application in the usual way. Here is an example for the :zephy References ********** +.. target-notes:: + .. _`ESP32-C3-DevKitM`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32c3/hw-reference/esp32c3/user-guide-devkitm-1.html .. _`ESP32-C3 Datasheet`: https://www.espressif.com/sites/default/files/documentation/esp32-c3_datasheet_en.pdf .. _`ESP32-C3 Technical Reference Manual`: https://espressif.com/sites/default/files/documentation/esp32-c3_technical_reference_manual_en.pdf diff --git a/boards/espressif/esp32c3_devkitm/esp32c3_devkitm.dts b/boards/espressif/esp32c3_devkitm/esp32c3_devkitm.dts index 3cc7c5218de..25bd583daee 100644 --- a/boards/espressif/esp32c3_devkitm/esp32c3_devkitm.dts +++ b/boards/espressif/esp32c3_devkitm/esp32c3_devkitm.dts @@ -16,7 +16,7 @@ compatible = "espressif,esp32c3"; chosen { - zephyr,sram = &sram0; + zephyr,sram = &sram1; zephyr,console = &uart0; zephyr,shell-uart = &uart0; zephyr,flash = &flash0; diff --git a/boards/espressif/esp32c3_devkitm/esp32c3_devkitm.yaml b/boards/espressif/esp32c3_devkitm/esp32c3_devkitm.yaml index 49ba690a563..38153891381 100644 --- a/boards/espressif/esp32c3_devkitm/esp32c3_devkitm.yaml +++ b/boards/espressif/esp32c3_devkitm/esp32c3_devkitm.yaml @@ -16,8 +16,4 @@ supported: - spi - counter - entropy -testing: - ignore_tags: - - net - - bluetooth vendor: espressif diff --git a/boards/espressif/esp32c3_rust/Kconfig b/boards/espressif/esp32c3_rust/Kconfig new file mode 100644 index 00000000000..c6a99b1032d --- /dev/null +++ b/boards/espressif/esp32c3_rust/Kconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 4096 diff --git a/boards/espressif/esp32c3_rust/Kconfig.defconfig b/boards/espressif/esp32c3_rust/Kconfig.defconfig deleted file mode 100644 index 77418527f48..00000000000 --- a/boards/espressif/esp32c3_rust/Kconfig.defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 65535 if WIFI && BT - default 51200 if WIFI - default 40960 if BT - default 4096 diff --git a/boards/espressif/esp32c3_rust/doc/img/esp32c3_rust.webp b/boards/espressif/esp32c3_rust/doc/img/esp32c3_rust.webp new file mode 100644 index 00000000000..aba51b8fe69 Binary files /dev/null and b/boards/espressif/esp32c3_rust/doc/img/esp32c3_rust.webp differ diff --git a/boards/espressif/esp32c3_rust/doc/index.rst b/boards/espressif/esp32c3_rust/doc/index.rst index 7b80d30ee5f..a6f41a01866 100644 --- a/boards/espressif/esp32c3_rust/doc/index.rst +++ b/boards/espressif/esp32c3_rust/doc/index.rst @@ -1,7 +1,4 @@ -.. _esp32c3_rust: - -ESP32-C3-DevKit-RUST -#################### +.. zephyr:board:: esp32c3_rust Overview ******** @@ -291,6 +288,8 @@ You can debug an application in the usual way. Here is an example for the :zephy References ********** +.. target-notes:: + .. _`ESP32-C3-DevKit-RUST`: https://github.com/esp-rs/esp-rust-board/tree/v1.2 .. _`ESP32-C3 Datasheet`: https://www.espressif.com/sites/default/files/documentation/esp32-c3_datasheet_en.pdf .. _`ESP32-C3 Technical Reference Manual`: https://espressif.com/sites/default/files/documentation/esp32-c3_technical_reference_manual_en.pdf diff --git a/boards/espressif/esp32c3_rust/esp32c3_rust.dts b/boards/espressif/esp32c3_rust/esp32c3_rust.dts index 5d397f3e1c9..867fa84adcf 100644 --- a/boards/espressif/esp32c3_rust/esp32c3_rust.dts +++ b/boards/espressif/esp32c3_rust/esp32c3_rust.dts @@ -17,7 +17,7 @@ compatible = "espressif,esp32c3_rust"; chosen { - zephyr,sram = &sram0; + zephyr,sram = &sram1; zephyr,console = &usb_serial; zephyr,shell-uart = &usb_serial; zephyr,flash = &flash0; diff --git a/boards/espressif/esp32c3_rust/esp32c3_rust.yaml b/boards/espressif/esp32c3_rust/esp32c3_rust.yaml index fedd0178f45..a82552337b4 100644 --- a/boards/espressif/esp32c3_rust/esp32c3_rust.yaml +++ b/boards/espressif/esp32c3_rust/esp32c3_rust.yaml @@ -18,8 +18,4 @@ supported: - spi - counter - entropy -testing: - ignore_tags: - - net - - bluetooth vendor: espressif diff --git a/boards/espressif/esp32c6_devkitc/Kconfig b/boards/espressif/esp32c6_devkitc/Kconfig new file mode 100644 index 00000000000..c6a99b1032d --- /dev/null +++ b/boards/espressif/esp32c6_devkitc/Kconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 4096 diff --git a/boards/espressif/esp32c6_devkitc/Kconfig.defconfig b/boards/espressif/esp32c6_devkitc/Kconfig.defconfig deleted file mode 100644 index fccfb36845b..00000000000 --- a/boards/espressif/esp32c6_devkitc/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# ESP32C6 devkitc board configuration - -# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 65535 if WIFI && BT - default 51200 if WIFI - default 40960 if BT - default 4096 diff --git a/boards/espressif/esp32c6_devkitc/doc/img/esp32c6_devkitc.webp b/boards/espressif/esp32c6_devkitc/doc/img/esp32c6_devkitc.webp new file mode 100644 index 00000000000..3b16025a0a8 Binary files /dev/null and b/boards/espressif/esp32c6_devkitc/doc/img/esp32c6_devkitc.webp differ diff --git a/boards/espressif/esp32c6_devkitc/doc/index.rst b/boards/espressif/esp32c6_devkitc/doc/index.rst index 7b856912a9a..ecbc4573360 100644 --- a/boards/espressif/esp32c6_devkitc/doc/index.rst +++ b/boards/espressif/esp32c6_devkitc/doc/index.rst @@ -1,7 +1,4 @@ -.. _esp32c6_devkitc: - -ESP32-C6-DevKitC -################ +.. zephyr:board:: esp32c6_devkitc Overview ******** @@ -102,10 +99,16 @@ Current Zephyr's ESP32-C6-DevKitC board supports the following features: +------------+------------+-------------------------------------+ | SPI Master | on-chip | spi | +------------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++------------+------------+-------------------------------------+ +| Timers | on-chip | counter | ++------------+------------+-------------------------------------+ | Watchdog | on-chip | watchdog | +------------+------------+-------------------------------------+ | LEDC | on-chip | pwm | +------------+------------+-------------------------------------+ +| MCPWM | on-chip | pwm | ++------------+------------+-------------------------------------+ | SPI DMA | on-chip | spi | +------------+------------+-------------------------------------+ | GDMA | on-chip | dma | @@ -114,6 +117,8 @@ Current Zephyr's ESP32-C6-DevKitC board supports the following features: +------------+------------+-------------------------------------+ | USB-CDC | on-chip | serial | +------------+------------+-------------------------------------+ +| Wi-Fi | on-chip | | ++------------+------------+-------------------------------------+ System requirements ******************* @@ -281,6 +286,8 @@ You can debug an application in the usual way. Here is an example for the :zephy References ********** +.. target-notes:: + .. _`ESP32-C6-DevKitC`: https://docs.espressif.com/projects/esp-dev-kits/en/latest/esp32c6/esp32-c6-devkitc-1/user_guide.html .. _`ESP32-C6 Datasheet`: https://www.espressif.com/sites/default/files/documentation/esp32-c6_datasheet_en.pdf .. _`ESP32-C6 Technical Reference Manual`: https://espressif.com/sites/default/files/documentation/esp32-c6_technical_reference_manual_en.pdf diff --git a/boards/espressif/esp32c6_devkitc/esp32c6_devkitc-pinctrl.dtsi b/boards/espressif/esp32c6_devkitc/esp32c6_devkitc-pinctrl.dtsi index a9cda93d22a..5265d5ef972 100644 --- a/boards/espressif/esp32c6_devkitc/esp32c6_devkitc-pinctrl.dtsi +++ b/boards/espressif/esp32c6_devkitc/esp32c6_devkitc-pinctrl.dtsi @@ -32,4 +32,14 @@ output-low; }; }; + + i2c0_default: i2c0_default { + group1 { + pinmux = , + ; + bias-pull-up; + drive-open-drain; + output-high; + }; + }; }; diff --git a/boards/espressif/esp32c6_devkitc/esp32c6_devkitc.dts b/boards/espressif/esp32c6_devkitc/esp32c6_devkitc.dts index a00de99e2b5..896ae30530c 100644 --- a/boards/espressif/esp32c6_devkitc/esp32c6_devkitc.dts +++ b/boards/espressif/esp32c6_devkitc/esp32c6_devkitc.dts @@ -16,7 +16,7 @@ compatible = "espressif,esp32c6"; chosen { - zephyr,sram = &sram0; + zephyr,sram = &sramhp; zephyr,console = &uart0; zephyr,shell-uart = &uart0; zephyr,flash = &flash0; @@ -49,6 +49,13 @@ status = "okay"; }; +&i2c0 { + status = "okay"; + clock-frequency = ; + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; +}; + &spi2 { #address-cells = <1>; #size-cells = <0>; diff --git a/boards/espressif/esp32c6_devkitc/esp32c6_devkitc.yaml b/boards/espressif/esp32c6_devkitc/esp32c6_devkitc.yaml index e72471a02ed..f36685e8367 100644 --- a/boards/espressif/esp32c6_devkitc/esp32c6_devkitc.yaml +++ b/boards/espressif/esp32c6_devkitc/esp32c6_devkitc.yaml @@ -10,10 +10,8 @@ supported: - watchdog - uart - dma + - pwm - spi + - counter - entropy -testing: - ignore_tags: - - net - - bluetooth - - tracing + - i2c diff --git a/boards/espressif/esp32s2_devkitc/Kconfig b/boards/espressif/esp32s2_devkitc/Kconfig new file mode 100644 index 00000000000..c6a99b1032d --- /dev/null +++ b/boards/espressif/esp32s2_devkitc/Kconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 4096 diff --git a/boards/espressif/esp32s2_devkitc/Kconfig.defconfig b/boards/espressif/esp32s2_devkitc/Kconfig.defconfig deleted file mode 100644 index 03bfd65b195..00000000000 --- a/boards/espressif/esp32s2_devkitc/Kconfig.defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# ESP32S2 DevKitC board configuration - -# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -config ENTROPY_GENERATOR - default y - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 32768 if WIFI - default 4096 diff --git a/boards/espressif/esp32s2_devkitc/doc/img/esp32s2_devkitc.webp b/boards/espressif/esp32s2_devkitc/doc/img/esp32s2_devkitc.webp new file mode 100644 index 00000000000..07f8b7ee41e Binary files /dev/null and b/boards/espressif/esp32s2_devkitc/doc/img/esp32s2_devkitc.webp differ diff --git a/boards/espressif/esp32s2_devkitc/doc/index.rst b/boards/espressif/esp32s2_devkitc/doc/index.rst index 9e1bb15fd10..e5cb0ff6191 100644 --- a/boards/espressif/esp32s2_devkitc/doc/index.rst +++ b/boards/espressif/esp32s2_devkitc/doc/index.rst @@ -1,7 +1,4 @@ -.. _esp32s2_devkitc: - -ESP32-S2-DevKitC -################ +.. zephyr:board:: esp32s2_devkitc Overview ******** @@ -252,7 +249,9 @@ You can debug an application in the usual way. Here is an example for the :zephy References ********** -.. _`ESP32-S3-DevKitC`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32s2/hw-reference/esp32s2/user-guide-saola-1-v1.2.html +.. target-notes:: + +.. _`ESP32-S2-DevKitC`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32s2/hw-reference/esp32s2/user-guide-saola-1-v1.2.html .. _`ESP32-S2 Datasheet`: https://www.espressif.com/sites/default/files/documentation/esp32-s2_datasheet_en.pdf .. _`ESP32-S2 Technical Reference Manual`: https://espressif.com/sites/default/files/documentation/esp32-s2_technical_reference_manual_en.pdf .. _`JTAG debugging for ESP32-S2`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32s2/api-guides/jtag-debugging/index.html diff --git a/boards/espressif/esp32s2_devkitc/esp32s2_devkitc.yaml b/boards/espressif/esp32s2_devkitc/esp32s2_devkitc.yaml index 482d8ad5ec2..44a6f971e3b 100644 --- a/boards/espressif/esp32s2_devkitc/esp32s2_devkitc.yaml +++ b/boards/espressif/esp32s2_devkitc/esp32s2_devkitc.yaml @@ -19,8 +19,4 @@ supported: - input - can - dma -testing: - ignore_tags: - - net - - bluetooth vendor: espressif diff --git a/boards/espressif/esp32s2_devkitc/esp32s2_devkitc_defconfig b/boards/espressif/esp32s2_devkitc/esp32s2_devkitc_defconfig index 5476839e2ba..f029cac9e9e 100644 --- a/boards/espressif/esp32s2_devkitc/esp32s2_devkitc_defconfig +++ b/boards/espressif/esp32s2_devkitc/esp32s2_devkitc_defconfig @@ -1,6 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 - CONFIG_MAIN_STACK_SIZE=2048 CONFIG_CONSOLE=y diff --git a/boards/espressif/esp32s2_saola/Kconfig b/boards/espressif/esp32s2_saola/Kconfig new file mode 100644 index 00000000000..c6a99b1032d --- /dev/null +++ b/boards/espressif/esp32s2_saola/Kconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 4096 diff --git a/boards/espressif/esp32s2_saola/Kconfig.defconfig b/boards/espressif/esp32s2_saola/Kconfig.defconfig deleted file mode 100644 index 5beaa3e15b1..00000000000 --- a/boards/espressif/esp32s2_saola/Kconfig.defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# ESP32S2 Saola board configuration - -# Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -config ENTROPY_GENERATOR - default y - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 32768 if WIFI - default 4096 diff --git a/boards/espressif/esp32s2_saola/doc/img/esp32s2_saola.webp b/boards/espressif/esp32s2_saola/doc/img/esp32s2_saola.webp new file mode 100644 index 00000000000..833147b884c Binary files /dev/null and b/boards/espressif/esp32s2_saola/doc/img/esp32s2_saola.webp differ diff --git a/boards/espressif/esp32s2_saola/doc/index.rst b/boards/espressif/esp32s2_saola/doc/index.rst index dba54f93cae..a2ad776acfe 100644 --- a/boards/espressif/esp32s2_saola/doc/index.rst +++ b/boards/espressif/esp32s2_saola/doc/index.rst @@ -1,7 +1,4 @@ -.. _esp32s2_saola: - -ESP32-S2-Saola -############## +.. zephyr:board:: esp32s2_saola Overview ******** @@ -252,6 +249,8 @@ You can debug an application in the usual way. Here is an example for the :zephy References ********** +.. target-notes:: + .. _`ESP32-S3-DevKitC`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32s2/hw-reference/esp32s2/user-guide-saola-1-v1.2.html .. _`ESP32-S2 Datasheet`: https://www.espressif.com/sites/default/files/documentation/esp32-s2_datasheet_en.pdf .. _`ESP32-S2 Technical Reference Manual`: https://espressif.com/sites/default/files/documentation/esp32-s2_technical_reference_manual_en.pdf diff --git a/boards/espressif/esp32s2_saola/esp32s2_saola.yaml b/boards/espressif/esp32s2_saola/esp32s2_saola.yaml index 1e1e391bb0e..bebe2a293a8 100644 --- a/boards/espressif/esp32s2_saola/esp32s2_saola.yaml +++ b/boards/espressif/esp32s2_saola/esp32s2_saola.yaml @@ -17,8 +17,4 @@ supported: - counter - entropy - input -testing: - ignore_tags: - - net - - bluetooth vendor: espressif diff --git a/boards/espressif/esp32s3_devkitc/Kconfig b/boards/espressif/esp32s3_devkitc/Kconfig new file mode 100644 index 00000000000..308628a4273 --- /dev/null +++ b/boards/espressif/esp32s3_devkitc/Kconfig @@ -0,0 +1,7 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 4096 if BOARD_ESP32S3_DEVKITC_ESP32S3_PROCPU + default 256 if BOARD_ESP32S3_DEVKITC_ESP32S3_APPCPU diff --git a/boards/espressif/esp32s3_devkitc/Kconfig.defconfig b/boards/espressif/esp32s3_devkitc/Kconfig.defconfig deleted file mode 100644 index d539cd66523..00000000000 --- a/boards/espressif/esp32s3_devkitc/Kconfig.defconfig +++ /dev/null @@ -1,22 +0,0 @@ -# ESP32S3 DevKitC board configuration - -# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_ESP32S3_DEVKITC_ESP32S3_PROCPU - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 65535 if WIFI && BT - default 51200 if WIFI - default 40960 if BT - default 4096 - -endif # BOARD_ESP32S3_DEVKITC_ESP32S3_PROCPU - -if BOARD_ESP32S3_DEVKITC_ESP32S3_APPCPU - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - default 256 - -endif # BOARD_ESP32S3_DEVKITC_ESP32S3_APPCPU diff --git a/boards/espressif/esp32s3_devkitc/doc/img/esp32s3_devkitc.webp b/boards/espressif/esp32s3_devkitc/doc/img/esp32s3_devkitc.webp new file mode 100644 index 00000000000..f838c1b77c8 Binary files /dev/null and b/boards/espressif/esp32s3_devkitc/doc/img/esp32s3_devkitc.webp differ diff --git a/boards/espressif/esp32s3_devkitc/doc/index.rst b/boards/espressif/esp32s3_devkitc/doc/index.rst index cd49316dacd..008b64fecae 100644 --- a/boards/espressif/esp32s3_devkitc/doc/index.rst +++ b/boards/espressif/esp32s3_devkitc/doc/index.rst @@ -1,7 +1,4 @@ -.. _esp32s3_devkitc: - -ESP32-S3-DevKitC -################ +.. zephyr:board:: esp32s3_devkitc Overview ******** @@ -279,6 +276,8 @@ You can debug an application in the usual way. Here is an example for the :zephy References ********** +.. target-notes:: + .. _`ESP32-S3-DevKitC`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32s3/hw-reference/esp32s3/user-guide-devkitc-1.html .. _`ESP32-S3 Datasheet`: https://www.espressif.com/sites/default/files/documentation/esp32-s3-wroom-1_wroom-1u_datasheet_en.pdf .. _`ESP32-S3 Technical Reference Manual`: https://www.espressif.com/sites/default/files/documentation/esp32-s3_technical_reference_manual_en.pdf diff --git a/boards/espressif/esp32s3_devkitc/esp32s3_devkitc-pinctrl.dtsi b/boards/espressif/esp32s3_devkitc/esp32s3_devkitc-pinctrl.dtsi index 2967cce447d..0eef5f1add7 100644 --- a/boards/espressif/esp32s3_devkitc/esp32s3_devkitc-pinctrl.dtsi +++ b/boards/espressif/esp32s3_devkitc/esp32s3_devkitc-pinctrl.dtsi @@ -20,6 +20,17 @@ }; }; + uart1_default: uart1_default { + group1 { + pinmux = ; + output-high; + }; + group2 { + pinmux = ; + bias-pull-up; + }; + }; + i2c0_default: i2c0_default { group1 { pinmux = , diff --git a/boards/espressif/esp32s3_devkitc/esp32s3_devkitc_appcpu.dts b/boards/espressif/esp32s3_devkitc/esp32s3_devkitc_appcpu.dts index cddc827b4e3..bac7de229b3 100644 --- a/boards/espressif/esp32s3_devkitc/esp32s3_devkitc_appcpu.dts +++ b/boards/espressif/esp32s3_devkitc/esp32s3_devkitc_appcpu.dts @@ -5,17 +5,20 @@ */ /dts-v1/; -#include +#include #include +#include "esp32s3_devkitc-pinctrl.dtsi" / { model = "Espressif ESP32S3-DevkitC APPCPU"; compatible = "espressif,esp32s3"; chosen { - zephyr,sram = &sram0; + zephyr,sram = &sram1; zephyr,ipc_shm = &shm0; zephyr,ipc = &ipm0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_appcpu_partition; }; }; diff --git a/boards/espressif/esp32s3_devkitc/esp32s3_devkitc_procpu.dts b/boards/espressif/esp32s3_devkitc/esp32s3_devkitc_procpu.dts index cae78713f81..48806ab5a4c 100644 --- a/boards/espressif/esp32s3_devkitc/esp32s3_devkitc_procpu.dts +++ b/boards/espressif/esp32s3_devkitc/esp32s3_devkitc_procpu.dts @@ -5,11 +5,11 @@ */ /dts-v1/; -#include "espressif/esp32s3/esp32s3_wroom_n8.dtsi" -#include "esp32s3_devkitc-pinctrl.dtsi" +#include #include #include #include +#include "esp32s3_devkitc-pinctrl.dtsi" / { model = "Espressif ESP32S3-DevkitC PROCPU"; @@ -21,7 +21,7 @@ }; chosen { - zephyr,sram = &sram0; + zephyr,sram = &sram1; zephyr,console = &uart0; zephyr,shell-uart = &uart0; zephyr,flash = &flash0; diff --git a/boards/espressif/esp32s3_devkitc/esp32s3_devkitc_procpu.yaml b/boards/espressif/esp32s3_devkitc/esp32s3_devkitc_procpu.yaml index 2a5e48d464f..ae1de5034e7 100644 --- a/boards/espressif/esp32s3_devkitc/esp32s3_devkitc_procpu.yaml +++ b/boards/espressif/esp32s3_devkitc/esp32s3_devkitc_procpu.yaml @@ -17,8 +17,4 @@ supported: - pwm - dma - input -testing: - ignore_tags: - - net - - bluetooth vendor: espressif diff --git a/boards/espressif/esp32s3_devkitm/Kconfig b/boards/espressif/esp32s3_devkitm/Kconfig new file mode 100644 index 00000000000..84e633e5af2 --- /dev/null +++ b/boards/espressif/esp32s3_devkitm/Kconfig @@ -0,0 +1,7 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 4096 if BOARD_ESP32S3_DEVKITM_ESP32S3_PROCPU + default 256 if BOARD_ESP32S3_DEVKITM_ESP32S3_APPCPU diff --git a/boards/espressif/esp32s3_devkitm/Kconfig.defconfig b/boards/espressif/esp32s3_devkitm/Kconfig.defconfig deleted file mode 100644 index 26339590ee3..00000000000 --- a/boards/espressif/esp32s3_devkitm/Kconfig.defconfig +++ /dev/null @@ -1,22 +0,0 @@ -# ESP32S3 DevKitM board configuration - -# Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_ESP32S3_DEVKITM_ESP32S3_PROCPU - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 65535 if WIFI && BT - default 51200 if WIFI - default 40960 if BT - default 4096 - -endif # BOARD_ESP32S3_DEVKITM_ESP32S3_PROCPU - -if BOARD_ESP32S3_DEVKITM_ESP32S3_APPCPU - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - default 256 - -endif # BOARD_ESP32S3_DEVKITM_ESP32S3_APPCPU diff --git a/boards/espressif/esp32s3_devkitm/doc/img/esp32s3_devkitm.webp b/boards/espressif/esp32s3_devkitm/doc/img/esp32s3_devkitm.webp new file mode 100644 index 00000000000..9a2c127a4fa Binary files /dev/null and b/boards/espressif/esp32s3_devkitm/doc/img/esp32s3_devkitm.webp differ diff --git a/boards/espressif/esp32s3_devkitm/doc/index.rst b/boards/espressif/esp32s3_devkitm/doc/index.rst index 04a3997abba..ada774ec2a1 100644 --- a/boards/espressif/esp32s3_devkitm/doc/index.rst +++ b/boards/espressif/esp32s3_devkitm/doc/index.rst @@ -1,7 +1,4 @@ -.. _esp32s3_devkitm: - -ESP32-S3-DevKitM -################ +.. zephyr:board:: esp32s3_devkitm Overview ******** @@ -279,6 +276,8 @@ You can debug an application in the usual way. Here is an example for the :zephy References ********** +.. target-notes:: + .. _`ESP32-S3-DevKitM User Guide`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32s3/hw-reference/esp32s3/user-guide-devkitm-1.html .. _`ESP32-S3 Datasheet`: https://www.espressif.com/sites/default/files/documentation/esp32-s3-mini-1_mini-1u_datasheet_en.pdf .. _`ESP32-S3 Technical Reference Manual`: https://www.espressif.com/sites/default/files/documentation/esp32-s3_technical_reference_manual_en.pdf diff --git a/boards/espressif/esp32s3_devkitm/esp32s3_devkitm-pinctrl.dtsi b/boards/espressif/esp32s3_devkitm/esp32s3_devkitm-pinctrl.dtsi index aa048eb4b7f..adbe936cb2a 100644 --- a/boards/espressif/esp32s3_devkitm/esp32s3_devkitm-pinctrl.dtsi +++ b/boards/espressif/esp32s3_devkitm/esp32s3_devkitm-pinctrl.dtsi @@ -20,6 +20,17 @@ }; }; + uart1_default: uart1_default { + group1 { + pinmux = ; + output-high; + }; + group2 { + pinmux = ; + bias-pull-up; + }; + }; + i2c0_default: i2c0_default { group1 { pinmux = , diff --git a/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_appcpu.dts b/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_appcpu.dts index 0a758507c3f..08a9e005be3 100644 --- a/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_appcpu.dts +++ b/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_appcpu.dts @@ -5,17 +5,20 @@ */ /dts-v1/; -#include +#include #include +#include "esp32s3_devkitm-pinctrl.dtsi" / { model = "Espressif ESP32S3-DevkitM APPCPU"; compatible = "espressif,esp32s3"; chosen { - zephyr,sram = &sram0; + zephyr,sram = &sram1; zephyr,ipc_shm = &shm0; zephyr,ipc = &ipm0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_appcpu_partition; }; }; diff --git a/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_appcpu_defconfig b/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_appcpu_defconfig index 9abf2ff0430..1ac2b1c55c9 100644 --- a/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_appcpu_defconfig +++ b/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_appcpu_defconfig @@ -1,4 +1,3 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_MAIN_STACK_SIZE=2048 -CONFIG_CLOCK_CONTROL=y +CONFIG_MAIN_STACK_SIZE=4096 diff --git a/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_procpu.dts b/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_procpu.dts index d168e97fe60..89c5b8c1641 100644 --- a/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_procpu.dts +++ b/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_procpu.dts @@ -6,10 +6,10 @@ /dts-v1/; #include -#include "esp32s3_devkitm-pinctrl.dtsi" #include #include #include +#include "esp32s3_devkitm-pinctrl.dtsi" / { model = "Espressif ESP32S3-DevkitM PROCPU"; @@ -21,7 +21,7 @@ }; chosen { - zephyr,sram = &sram0; + zephyr,sram = &sram1; zephyr,console = &uart0; zephyr,shell-uart = &uart0; zephyr,flash = &flash0; diff --git a/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_procpu.yaml b/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_procpu.yaml index 084f6f7539e..e153c2e9f81 100644 --- a/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_procpu.yaml +++ b/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_procpu.yaml @@ -18,8 +18,4 @@ supported: - dma - input - video -testing: - ignore_tags: - - net - - bluetooth vendor: espressif diff --git a/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_procpu_defconfig b/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_procpu_defconfig index d789bab1824..92308aa841b 100644 --- a/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_procpu_defconfig +++ b/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_procpu_defconfig @@ -1,6 +1,6 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_MAIN_STACK_SIZE=2048 +CONFIG_MAIN_STACK_SIZE=4096 CONFIG_CONSOLE=y CONFIG_SERIAL=y diff --git a/boards/espressif/esp32s3_eye/Kconfig b/boards/espressif/esp32s3_eye/Kconfig new file mode 100644 index 00000000000..25042fa0ce1 --- /dev/null +++ b/boards/espressif/esp32s3_eye/Kconfig @@ -0,0 +1,7 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 4096 if BOARD_ESP32S3_EYE_ESP32S3_PROCPU + default 256 if BOARD_ESP32S3_EYE_ESP32S3_APPCPU diff --git a/boards/espressif/esp32s3_eye/Kconfig.defconfig b/boards/espressif/esp32s3_eye/Kconfig.defconfig index 71c7374e095..66745cfd2be 100644 --- a/boards/espressif/esp32s3_eye/Kconfig.defconfig +++ b/boards/espressif/esp32s3_eye/Kconfig.defconfig @@ -5,21 +5,7 @@ if BOARD_ESP32S3_EYE_ESP32S3_PROCPU -config LV_COLOR_16_SWAP +configdefault LV_COLOR_16_SWAP default y -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 65535 if WIFI && BT - default 51200 if WIFI - default 40960 if BT - default 4096 - endif # BOARD_ESP32S3_EYE_ESP32S3_PROCPU - -if BOARD_ESP32S3_EYE_ESP32S3_APPCPU - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - default 256 - -endif # BOARD_ESP32S3_EYE_ESP32S3_APPCPU diff --git a/boards/espressif/esp32s3_eye/doc/img/ESP32-S3-EYE-isometric.webp b/boards/espressif/esp32s3_eye/doc/img/esp32s3_eye.webp similarity index 100% rename from boards/espressif/esp32s3_eye/doc/img/ESP32-S3-EYE-isometric.webp rename to boards/espressif/esp32s3_eye/doc/img/esp32s3_eye.webp diff --git a/boards/espressif/esp32s3_eye/doc/index.rst b/boards/espressif/esp32s3_eye/doc/index.rst index bbe95728e94..662c4e51998 100644 --- a/boards/espressif/esp32s3_eye/doc/index.rst +++ b/boards/espressif/esp32s3_eye/doc/index.rst @@ -1,7 +1,4 @@ -.. _esp32s3_eye: - -ESP32-S3-EYE -############ +.. zephyr:board:: esp32s3_eye Overview ******** @@ -20,10 +17,6 @@ ESP32-S3-WROOM-1 module, camera, SD card slot, digital microphone, USB port, and and the sub board (ESP32-S3-EYE-SUB) that contains an LCD display. The main board and sub board are connected through pin headers. -.. figure:: img/ESP32-S3-EYE-isometric.webp - :align: center - :alt: ESP32-S3-EYE - Block Diagram ------------- diff --git a/boards/espressif/esp32s3_eye/esp32s3_eye_appcpu.dts b/boards/espressif/esp32s3_eye/esp32s3_eye_appcpu.dts index 4b5d6240185..8e323c4e463 100644 --- a/boards/espressif/esp32s3_eye/esp32s3_eye_appcpu.dts +++ b/boards/espressif/esp32s3_eye/esp32s3_eye_appcpu.dts @@ -6,60 +6,29 @@ /dts-v1/; #include +#include + / { model = "Espressif ESP32S3-EYE APPCPU"; compatible = "espressif,esp32s3"; chosen { - zephyr,sram = &sram0; + zephyr,sram = &sram1; zephyr,ipc_shm = &shm0; zephyr,ipc = &ipm0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_appcpu_partition; }; }; -&trng0 { - status = "okay"; +&flash0 { + reg = <0x0 DT_SIZE_M(4)>; }; -&ipm0 { +&trng0 { status = "okay"; }; -&flash0 { +&ipm0 { status = "okay"; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Reserve 64kB for the bootloader */ - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x00010000>; - read-only; - }; - - /* Reserve 1024kB for the application in slot 0 */ - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 0x00100000>; - }; - - /* Reserve 1024kB for the application in slot 1 */ - slot1_partition: partition@110000 { - label = "image-1"; - reg = <0x00110000 0x00100000>; - }; - - /* Reserve 256kB for the scratch partition */ - scratch_partition: partition@210000 { - label = "image-scratch"; - reg = <0x00210000 0x00040000>; - }; - - storage_partition: partition@250000 { - label = "storage"; - reg = <0x00250000 0x00006000>; - }; - }; }; diff --git a/boards/espressif/esp32s3_eye/esp32s3_eye_procpu.dts b/boards/espressif/esp32s3_eye/esp32s3_eye_procpu.dts index fab93cbcf6d..1b2afa8b83a 100644 --- a/boards/espressif/esp32s3_eye/esp32s3_eye_procpu.dts +++ b/boards/espressif/esp32s3_eye/esp32s3_eye_procpu.dts @@ -10,6 +10,7 @@ #include #include #include +#include / { model = "Espressif ESP32S3-EYE PROCPU"; @@ -23,7 +24,7 @@ }; chosen { - zephyr,sram = &sram0; + zephyr,sram = &sram1; zephyr,console = &usb_serial; zephyr,shell-uart = &usb_serial; zephyr,flash = &flash0; @@ -108,7 +109,7 @@ nvgam-param = [D0 04 0C 11 13 2C 3F 44 51 2F 1F 1F 20 23]; ram-param = [00 F0]; rgb-param = [CD 08 14]; - mipi-mode = ; + mipi-mode = "MIPI_DBI_MODE_SPI_4WIRE"; }; }; }; @@ -200,45 +201,6 @@ status = "okay"; }; -&flash0 { - status = "okay"; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Reserve 64kB for the bootloader */ - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x00010000>; - read-only; - }; - - /* Reserve 1024kB for the application in slot 0 */ - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 0x00100000>; - }; - - /* Reserve 1024kB for the application in slot 1 */ - slot1_partition: partition@110000 { - label = "image-1"; - reg = <0x00110000 0x00100000>; - }; - - /* Reserve 256kB for the scratch partition */ - scratch_partition: partition@210000 { - label = "image-scratch"; - reg = <0x00210000 0x00040000>; - }; - - storage_partition: partition@250000 { - label = "storage"; - reg = <0x00250000 0x00006000>; - }; - }; -}; - &esp32_bt_hci { status = "okay"; }; diff --git a/boards/espressif/esp32s3_eye/esp32s3_eye_procpu.yaml b/boards/espressif/esp32s3_eye/esp32s3_eye_procpu.yaml index adddce2e59e..1159b63942b 100644 --- a/boards/espressif/esp32s3_eye/esp32s3_eye_procpu.yaml +++ b/boards/espressif/esp32s3_eye/esp32s3_eye_procpu.yaml @@ -16,8 +16,5 @@ supported: - pwm - dma - input -testing: - ignore_tags: - - net - - bluetooth + - video vendor: espressif diff --git a/boards/espressif/esp8684_devkitm/Kconfig b/boards/espressif/esp8684_devkitm/Kconfig new file mode 100644 index 00000000000..c6a99b1032d --- /dev/null +++ b/boards/espressif/esp8684_devkitm/Kconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 4096 diff --git a/boards/espressif/esp8684_devkitm/Kconfig.defconfig b/boards/espressif/esp8684_devkitm/Kconfig.defconfig deleted file mode 100644 index 60266dd5fd8..00000000000 --- a/boards/espressif/esp8684_devkitm/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# ESP8684 devkitm board configuration - -# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 65535 if WIFI && BT - default 51200 if WIFI - default 40960 if BT - default 4096 diff --git a/boards/espressif/esp8684_devkitm/doc/img/esp8684_devkitm.webp b/boards/espressif/esp8684_devkitm/doc/img/esp8684_devkitm.webp new file mode 100644 index 00000000000..519a0668caf Binary files /dev/null and b/boards/espressif/esp8684_devkitm/doc/img/esp8684_devkitm.webp differ diff --git a/boards/espressif/esp8684_devkitm/doc/index.rst b/boards/espressif/esp8684_devkitm/doc/index.rst index fe2ba1e60bf..1b20435c586 100644 --- a/boards/espressif/esp8684_devkitm/doc/index.rst +++ b/boards/espressif/esp8684_devkitm/doc/index.rst @@ -1,7 +1,4 @@ -.. _esp8684_devkitm: - -ESP8684-DevKitM -############### +.. zephyr:board:: esp8684_devkitm Overview ******** @@ -242,6 +239,8 @@ You can debug an application in the usual way. Here is an example for the :zephy References ********** +.. target-notes:: + .. _`ESP8684-DevKitM User Guide`: https://docs.espressif.com/projects/esp-dev-kits/en/latest/esp8684/esp8684-devkitm-1/user_guide.html .. _`ESP8684 Datasheet`: https://www.espressif.com/sites/default/files/documentation/esp8684_datasheet_en.pdf .. _`ESP8684 Technical Reference Manual`: https://www.espressif.com/sites/default/files/documentation/esp8684_technical_reference_manual_en.pdf diff --git a/boards/espressif/esp8684_devkitm/esp8684_devkitm.dts b/boards/espressif/esp8684_devkitm/esp8684_devkitm.dts index 0b52a3d2b86..a6a76ac4756 100644 --- a/boards/espressif/esp8684_devkitm/esp8684_devkitm.dts +++ b/boards/espressif/esp8684_devkitm/esp8684_devkitm.dts @@ -16,7 +16,7 @@ compatible = "espressif,esp32c2"; chosen { - zephyr,sram = &sram0; + zephyr,sram = &sram1; zephyr,console = &uart0; zephyr,shell-uart = &uart0; zephyr,flash = &flash0; diff --git a/boards/espressif/esp8684_devkitm/esp8684_devkitm.yaml b/boards/espressif/esp8684_devkitm/esp8684_devkitm.yaml index e689bbfe6c1..3344e8d5e2c 100644 --- a/boards/espressif/esp8684_devkitm/esp8684_devkitm.yaml +++ b/boards/espressif/esp8684_devkitm/esp8684_devkitm.yaml @@ -12,8 +12,4 @@ supported: - entropy - pwm - spi -testing: - ignore_tags: - - net - - bluetooth vendor: espressif diff --git a/boards/espressif/esp_wrover_kit/Kconfig b/boards/espressif/esp_wrover_kit/Kconfig new file mode 100644 index 00000000000..64997988d51 --- /dev/null +++ b/boards/espressif/esp_wrover_kit/Kconfig @@ -0,0 +1,7 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 4096 if BOARD_ESP_WROVER_KIT_ESP32_PROCPU + default 256 if BOARD_ESP_WROVER_KIT_ESP32_APPCPU diff --git a/boards/espressif/esp_wrover_kit/Kconfig.defconfig b/boards/espressif/esp_wrover_kit/Kconfig.defconfig index adf8cd7e398..3fed00825a3 100644 --- a/boards/espressif/esp_wrover_kit/Kconfig.defconfig +++ b/boards/espressif/esp_wrover_kit/Kconfig.defconfig @@ -5,21 +5,7 @@ if BOARD_ESP_WROVER_KIT_ESP32_PROCPU -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 65535 if WIFI && BT - default 51200 if WIFI - default 40960 if BT - default 4096 - config DISK_DRIVER_SDMMC default y endif # BOARD_ESP_WROVER_KIT_ESP32_PROCPU - -if BOARD_ESP_WROVER_KIT_ESP32_APPCPU - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - default 4096 - -endif # BOARD_ESP_WROVER_KIT_ESP32_APPCPU diff --git a/boards/espressif/esp_wrover_kit/doc/img/esp-wrover-kit-v4.1-layout-front.jpg b/boards/espressif/esp_wrover_kit/doc/img/esp_wrover_kit.jpg similarity index 100% rename from boards/espressif/esp_wrover_kit/doc/img/esp-wrover-kit-v4.1-layout-front.jpg rename to boards/espressif/esp_wrover_kit/doc/img/esp_wrover_kit.jpg diff --git a/boards/espressif/esp_wrover_kit/doc/index.rst b/boards/espressif/esp_wrover_kit/doc/index.rst index 0bef9a9ce4d..96f1c0570c2 100644 --- a/boards/espressif/esp_wrover_kit/doc/index.rst +++ b/boards/espressif/esp_wrover_kit/doc/index.rst @@ -1,7 +1,4 @@ -.. _esp_wrover_kit: - -ESP-WROVER-KIT -############## +.. zephyr:board:: esp_wrover_kit Overview ******** @@ -43,7 +40,7 @@ Functional Description The following two figures and the table below describe the key components, interfaces, and controls of the ESP-WROVER-KIT board. -.. figure:: img/esp-wrover-kit-v4.1-layout-front.jpg +.. figure:: img/esp_wrover_kit.jpg :align: center :alt: esp wrover front @@ -652,6 +649,8 @@ You can debug an application in the usual way. Here is an example for the :zephy References ********** +.. target-notes:: + .. _`ESP32 Datasheet`: https://www.espressif.com/sites/default/files/documentation/esp32_datasheet_en.pdf (PDF) .. _`ESP32-WROVER-E Datasheet`: https://www.espressif.com/sites/default/files/documentation/esp32-wrover-e_esp32-wrover-ie_datasheet_en.pdf (PDF) .. _`OpenOCD ESP32`: https://github.com/espressif/openocd-esp32/releases diff --git a/boards/espressif/esp_wrover_kit/esp_wrover_kit-pinctrl.dtsi b/boards/espressif/esp_wrover_kit/esp_wrover_kit-pinctrl.dtsi index aee93f0eb67..62fb834954c 100644 --- a/boards/espressif/esp_wrover_kit/esp_wrover_kit-pinctrl.dtsi +++ b/boards/espressif/esp_wrover_kit/esp_wrover_kit-pinctrl.dtsi @@ -21,6 +21,17 @@ }; }; + uart1_default: uart1_default { + group1 { + pinmux = ; + output-high; + }; + group2 { + pinmux = ; + bias-pull-up; + }; + }; + spim2_default: spim2_default { group1 { pinmux = , diff --git a/boards/espressif/esp_wrover_kit/esp_wrover_kit_appcpu.dts b/boards/espressif/esp_wrover_kit/esp_wrover_kit_appcpu.dts index 154857f15e9..903f48f308e 100644 --- a/boards/espressif/esp_wrover_kit/esp_wrover_kit_appcpu.dts +++ b/boards/espressif/esp_wrover_kit/esp_wrover_kit_appcpu.dts @@ -13,9 +13,11 @@ compatible = "espressif,esp32"; chosen { - zephyr,sram = &sram0; + zephyr,sram = &sram1; zephyr,ipc_shm = &shm0; zephyr,ipc = &ipm0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_appcpu_partition; }; }; diff --git a/boards/espressif/esp_wrover_kit/esp_wrover_kit_procpu.dts b/boards/espressif/esp_wrover_kit/esp_wrover_kit_procpu.dts index a19aa040a46..614bd1ec54f 100644 --- a/boards/espressif/esp_wrover_kit/esp_wrover_kit_procpu.dts +++ b/boards/espressif/esp_wrover_kit/esp_wrover_kit_procpu.dts @@ -7,7 +7,7 @@ #include #include "esp_wrover_kit-pinctrl.dtsi" -#include +#include / { model = "Espressif ESP32-Wrover-Kit PROCPU"; @@ -30,7 +30,7 @@ }; chosen { - zephyr,sram = &sram0; + zephyr,sram = &sram1; zephyr,console = &uart0; zephyr,shell-uart = &uart0; zephyr,flash = &flash0; @@ -103,6 +103,13 @@ pinctrl-names = "default"; }; +&uart1 { + status = "disabled"; + current-speed = <115200>; + pinctrl-0 = <&uart1_default>; + pinctrl-names = "default"; +}; + &gpio0 { status = "okay"; @@ -202,6 +209,7 @@ mmc { compatible = "zephyr,sdmmc-disk"; + disk-name = "SD"; status = "okay"; }; }; diff --git a/boards/espressif/esp_wrover_kit/esp_wrover_kit_procpu.yaml b/boards/espressif/esp_wrover_kit/esp_wrover_kit_procpu.yaml index d316dd1b8d0..88bcdc3289b 100644 --- a/boards/espressif/esp_wrover_kit/esp_wrover_kit_procpu.yaml +++ b/boards/espressif/esp_wrover_kit/esp_wrover_kit_procpu.yaml @@ -17,8 +17,4 @@ supported: - spi - counter - entropy -testing: - ignore_tags: - - net - - bluetooth vendor: espressif diff --git a/boards/ezurio/bl5340_dvk/Kconfig.defconfig b/boards/ezurio/bl5340_dvk/Kconfig.defconfig index d90d05152fa..b71b51265b9 100644 --- a/boards/ezurio/bl5340_dvk/Kconfig.defconfig +++ b/boards/ezurio/bl5340_dvk/Kconfig.defconfig @@ -87,7 +87,7 @@ choice LV_COLOR_DEPTH default LV_COLOR_DEPTH_16 endchoice -config LV_COLOR_16_SWAP +configdefault LV_COLOR_16_SWAP default y config INPUT @@ -101,11 +101,6 @@ endif # BOARD_BL5340_DVK_NRF5340_CPUAPP || BOARD_BL5340_DVK_NRF5340_CPUAPP_NS if BOARD_BL5340_DVK_NRF5340_CPUNET -# BT_CTLR depends on BT. When BT is enabled we should default to also -# enabling the controller. -config BT_CTLR - default y if BT - config BT_ECC default y if BT diff --git a/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_common.dtsi b/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_common.dtsi index af4f1cddeae..c6986c7c878 100644 --- a/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_common.dtsi +++ b/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_common.dtsi @@ -16,6 +16,7 @@ zephyr,bt-c2h-uart = &uart0; zephyr,display = &ili9340; zephyr,bt-hci = &bt_hci_ipc0; + zephyr,touch = &ft5336; }; /* Main LEDs and buttons are on an I2C TCA9538 GPIO port expander */ @@ -139,6 +140,16 @@ status = "okay"; }; +&lfxo { + load-capacitors = "internal"; + load-capacitance-picofarad = <7>; +}; + +&hfxo { + load-capacitors = "internal"; + load-capacitance-femtofarad = <13500>; +}; + &adc { status = "okay"; }; @@ -241,6 +252,7 @@ spi-max-frequency = <8000000>; mmc { compatible = "zephyr,sdmmc-disk"; + disk-name = "SD"; status = "okay"; }; }; diff --git a/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_defconfig b/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_defconfig index b60faf810bb..115c1ec2952 100644 --- a/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_defconfig +++ b/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_defconfig @@ -21,6 +21,3 @@ CONFIG_UART_CONSOLE=y # Setup clocks CONFIG_CLOCK_CONTROL_NRF_K32SRC_250PPM=y -CONFIG_SOC_LFXO_CAP_INT_7PF=y -CONFIG_SOC_HFXO_CAP_INTERNAL=y -CONFIG_SOC_HFXO_CAP_INT_VALUE_X2=27 diff --git a/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_partition_conf.dtsi b/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_partition_conf.dtsi index b85e3d03dc2..2fc651230f4 100644 --- a/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_partition_conf.dtsi +++ b/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_partition_conf.dtsi @@ -57,5 +57,5 @@ reg = <0x20040000 0x30000>; }; -/* Include shared RAM configuration file */ -#include "bl5340_dvk_nrf5340_shared_sram_planning_conf.dtsi" +/* Include default shared RAM configuration file */ +#include diff --git a/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpunet_common.dtsi b/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpunet_common.dtsi index ce2e145d587..1f5fc0bb340 100644 --- a/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpunet_common.dtsi +++ b/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpunet_common.dtsi @@ -63,5 +63,5 @@ }; }; -/* Include shared RAM configuration file */ -#include "bl5340_dvk_nrf5340_shared_sram_planning_conf.dtsi" +/* Include default shared RAM configuration file */ +#include diff --git a/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_shared_sram_planning_conf.dtsi b/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_shared_sram_planning_conf.dtsi deleted file mode 100644 index fbb059494c3..00000000000 --- a/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_shared_sram_planning_conf.dtsi +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Copyright (c) 2019 Nordic Semiconductor ASA - * Copyright (c) 2021 Laird Connectivity - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/* Default shared SRAM planning when building for BL5340 DVK. - * This file is included by both nRF5340 CPUAPP (Application MCU) - * and nRF5340 CPUNET (Network MCU). - * - 64 kB SRAM allocated as Shared memory (sram0_shared) - * - Region defined after the image SRAM of Application MCU - */ - -/ { - chosen { - /* shared memory reserved for the inter-processor communication */ - zephyr,ipc_shm = &sram0_shared; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sram0_shared: memory@20070000 { - /* SRAM allocated to shared memory */ - reg = <0x20070000 0x10000>; - }; - }; -}; diff --git a/boards/ezurio/bl5340_dvk/doc/index.rst b/boards/ezurio/bl5340_dvk/doc/index.rst index 62a7de87f93..b19a0516c30 100644 --- a/boards/ezurio/bl5340_dvk/doc/index.rst +++ b/boards/ezurio/bl5340_dvk/doc/index.rst @@ -1,7 +1,4 @@ -.. _bl5340_dvk: - -Ezurio BL5340 DVK -################# +.. zephyr:board:: bl5340_dvk Overview ******** @@ -43,12 +40,6 @@ This development kit has the following features: * :abbr:`USB (Universal Serial Bus)` * :abbr:`WDT (Watchdog Timer)` -.. figure:: img/bl5340_dvk_top.jpg - :align: center - :alt: BL5340 DVK - - BL5340 DVK (Credit: Ezurio) - More information about the module can be found on the `BL5340 homepage`_. diff --git a/boards/ezurio/bl652_dvk/Kconfig.defconfig b/boards/ezurio/bl652_dvk/Kconfig.defconfig index 62fac3e6c21..e7e6afee009 100644 --- a/boards/ezurio/bl652_dvk/Kconfig.defconfig +++ b/boards/ezurio/bl652_dvk/Kconfig.defconfig @@ -5,9 +5,6 @@ if BOARD_BL652_DVK -config BT_CTLR - default BT - if DAC config I2C diff --git a/boards/ezurio/bl652_dvk/doc/bl652_dvk.rst b/boards/ezurio/bl652_dvk/doc/bl652_dvk.rst index aaae4b9071b..27ec3f92928 100644 --- a/boards/ezurio/bl652_dvk/doc/bl652_dvk.rst +++ b/boards/ezurio/bl652_dvk/doc/bl652_dvk.rst @@ -1,7 +1,4 @@ -.. _bl652_dvk: - -Ezurio BL652 DVK -################ +.. zephyr:board:: bl652_dvk Overview ******** @@ -31,12 +28,6 @@ Available BL652 DVK part numbers: * DVK-BL652-SA * DVK-BL652-SC -.. figure:: img/bl652_dvk.jpg - :align: center - :alt: BL652 DVK - - BL652 DVK Board - .. figure:: img/BL652-SA_DVK_BoxContents.jpg :align: center :alt: BL652-SA DVK Box Contents diff --git a/boards/ezurio/bl653_dvk/Kconfig.defconfig b/boards/ezurio/bl653_dvk/Kconfig.defconfig index 43f19f65a6d..b2a37d4a6e3 100644 --- a/boards/ezurio/bl653_dvk/Kconfig.defconfig +++ b/boards/ezurio/bl653_dvk/Kconfig.defconfig @@ -5,9 +5,6 @@ if BOARD_BL653_DVK -config BT_CTLR - default BT - if DAC config I2C diff --git a/boards/ezurio/bl653_dvk/doc/bl653_dvk.rst b/boards/ezurio/bl653_dvk/doc/bl653_dvk.rst index 48c252b5ff9..e4de59757e8 100644 --- a/boards/ezurio/bl653_dvk/doc/bl653_dvk.rst +++ b/boards/ezurio/bl653_dvk/doc/bl653_dvk.rst @@ -1,7 +1,4 @@ -.. _bl653_dvk: - -Ezurio BL653 DVK -################ +.. zephyr:board:: bl653_dvk Overview ******** @@ -27,12 +24,6 @@ This development kit has the following features: * :abbr:`USB (Universal Serial Bus)` * :abbr:`WDT (Watchdog Timer)` -.. figure:: img/bl653_dvk.jpg - :align: center - :alt: BL653 Development Kit - - BL653 Development Kit Board - More information about the board can be found at the `BL653 website`_. diff --git a/boards/ezurio/bl654_dvk/Kconfig.defconfig b/boards/ezurio/bl654_dvk/Kconfig.defconfig index dbd4fb812f0..c4b8594f891 100644 --- a/boards/ezurio/bl654_dvk/Kconfig.defconfig +++ b/boards/ezurio/bl654_dvk/Kconfig.defconfig @@ -5,9 +5,6 @@ if BOARD_BL654_DVK -config BT_CTLR - default BT - if DAC config I2C diff --git a/boards/ezurio/bl654_dvk/doc/bl654_dvk.rst b/boards/ezurio/bl654_dvk/doc/bl654_dvk.rst index d262a9a5146..5a59932df25 100644 --- a/boards/ezurio/bl654_dvk/doc/bl654_dvk.rst +++ b/boards/ezurio/bl654_dvk/doc/bl654_dvk.rst @@ -1,7 +1,4 @@ -.. _bl654_dvk: - -Ezurio BL654 DVK -################ +.. zephyr:board:: bl654_dvk Overview ******** @@ -32,12 +29,6 @@ This development kit has the following features: * :abbr:`USB (Universal Serial Bus)` * :abbr:`WDT (Watchdog Timer)` -.. figure:: img/bl654_dvk.jpg - :align: center - :alt: BL654 Development Kit - - BL654 Development Kit Board - .. figure:: img/455-00001_BoxContents.jpg :align: center :alt: 455-00001 Box Contents diff --git a/boards/ezurio/bl654_sensor_board/Kconfig.defconfig b/boards/ezurio/bl654_sensor_board/Kconfig.defconfig index 3ac458bcec9..ecdc77a2cdd 100644 --- a/boards/ezurio/bl654_sensor_board/Kconfig.defconfig +++ b/boards/ezurio/bl654_sensor_board/Kconfig.defconfig @@ -5,7 +5,4 @@ if BOARD_BL654_SENSOR_BOARD -config BT_CTLR - default BT - endif # BOARD_BL654_SENSOR_BOARD diff --git a/boards/ezurio/bl654_sensor_board/doc/bl654_sensor_board.rst b/boards/ezurio/bl654_sensor_board/doc/bl654_sensor_board.rst index 32036e38ada..373e9bf1bdc 100644 --- a/boards/ezurio/bl654_sensor_board/doc/bl654_sensor_board.rst +++ b/boards/ezurio/bl654_sensor_board/doc/bl654_sensor_board.rst @@ -1,7 +1,4 @@ -.. _bl654_sensor_board: - -Ezurio BL654 Sensor Board -######################### +.. zephyr:board:: bl654_sensor_board Overview ******** @@ -27,12 +24,6 @@ This sensor board has the following features: * :abbr:`UART (Universal asynchronous receiver-transmitter)` * :abbr:`WDT (Watchdog Timer)` -.. figure:: img/bl654_sensor_board.jpg - :align: center - :alt: BL654 Sensor Board front and back - - BL654 Sensor Board front and back - .. figure:: img/bl654_sensor_board_usb_swd_programmer.jpg :align: center :alt: BL654 Sensor Board connected to USB-SWD Programmer (UART and SWD access) diff --git a/boards/ezurio/bl654_usb/Kconfig b/boards/ezurio/bl654_usb/Kconfig deleted file mode 100644 index c9779a44da9..00000000000 --- a/boards/ezurio/bl654_usb/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -# BL654 USB adapter board configuration - -# Copyright (c) 2021 Laird Connectivity -# SPDX-License-Identifier: Apache-2.0 - -config BL654_USB_SERIAL_BACKEND_CDCACM - bool "Use CDC ACM UART as backend for BL654 USB adapter" - default y if !USB_DEVICE_BLUETOOTH - help - Use CDC ACM UART as backend for console or shell. diff --git a/boards/ezurio/bl654_usb/Kconfig.defconfig b/boards/ezurio/bl654_usb/Kconfig.defconfig index baf624a0c5a..7b1a6770950 100644 --- a/boards/ezurio/bl654_usb/Kconfig.defconfig +++ b/boards/ezurio/bl654_usb/Kconfig.defconfig @@ -25,35 +25,6 @@ config FLASH_LOAD_SIZE default 0xdf000 depends on !USE_DT_CODE_PARTITION -config USB_CDC_ACM - default n if USB_DEVICE_BLUETOOTH - -if BL654_USB_SERIAL_BACKEND_CDCACM - -config UART_CONSOLE - default CONSOLE - -config USB_DEVICE_INITIALIZE_AT_BOOT - default y if !MCUBOOT - -config SHELL_BACKEND_SERIAL_CHECK_DTR - default SHELL - depends on UART_LINE_CTRL - -config UART_LINE_CTRL - default SHELL - -# Logger cannot use itself to log -config USB_CDC_ACM_LOG_LEVEL - default 0 - -# Set USB log level to error only -config USB_DEVICE_LOG_LEVEL - default 1 - -endif #BL654_USB_SERIAL_BACKEND_CDCACM - -config BT_CTLR - default BT +source "boards/common/usb/Kconfig.cdc_acm_serial.defconfig" endif # BOARD_BL654_USB diff --git a/boards/ezurio/bl654_usb/bl654_usb.dts b/boards/ezurio/bl654_usb/bl654_usb.dts index a6f81f64e61..6ce352bda6d 100644 --- a/boards/ezurio/bl654_usb/bl654_usb.dts +++ b/boards/ezurio/bl654_usb/bl654_usb.dts @@ -16,9 +16,6 @@ chosen { zephyr,sram = &sram0; zephyr,flash = &flash0; - zephyr,console = &bl654_cdc_acm_uart; - zephyr,shell-uart = &bl654_cdc_acm_uart; - zephyr,bt-c2h-uart = &bl654_cdc_acm_uart; zephyr,code-partition = &slot0_partition; zephyr,ieee802154 = &ieee802154; }; @@ -118,8 +115,6 @@ zephyr_udc0: &usbd { compatible = "nordic,nrf-usbd"; status = "okay"; - - bl654_cdc_acm_uart: bl654_cdc_acm_uart { - compatible = "zephyr,cdc-acm-uart"; - }; }; + +#include <../boards/common/usb/cdc_acm_serial.dtsi> diff --git a/boards/ezurio/bl654_usb/bl654_usb_defconfig b/boards/ezurio/bl654_usb/bl654_usb_defconfig index ba7d61d55be..053eb9dafdb 100644 --- a/boards/ezurio/bl654_usb/bl654_usb_defconfig +++ b/boards/ezurio/bl654_usb/bl654_usb_defconfig @@ -13,9 +13,6 @@ CONFIG_CONSOLE=y # Enable GPIO CONFIG_GPIO=y -# Enable USB -CONFIG_USB_DEVICE_STACK=y - # 32KHz clock source CONFIG_CLOCK_CONTROL_NRF_K32SRC_XTAL=y CONFIG_CLOCK_CONTROL_NRF_K32SRC_150PPM=y diff --git a/boards/ezurio/bl654_usb/doc/bl654_usb.rst b/boards/ezurio/bl654_usb/doc/bl654_usb.rst index c2ba1a23698..345331890ec 100644 --- a/boards/ezurio/bl654_usb/doc/bl654_usb.rst +++ b/boards/ezurio/bl654_usb/doc/bl654_usb.rst @@ -1,7 +1,4 @@ -.. _bl654_usb: - -Ezurio BL654 USB (451-00004) -############################ +.. zephyr:board:: bl654_usb Overview ******** @@ -23,12 +20,6 @@ This USB adapter has the following features: * :abbr:`WDT (Watchdog Timer)` * :abbr:`RTC (nRF RTC System Clock)` -.. figure:: img/bl654_usb.jpg - :align: center - :alt: BL654 USB adapter - - BL654 USB Adapter - .. figure:: img/bl654_usb_pcb.jpg :align: center :alt: 451-00004 Box Contents @@ -104,7 +95,7 @@ Programming and Debugging Applications for the ``bl654_usb`` board configuration can be built in the usual way (see :ref:`build_an_application` for more details). The ``bl654_usb`` board cannot be used for debugging. The compatible BL654 DVK -board can be used for development. Documentation can be found at the :ref:`bl654_dvk` +board can be used for development. Documentation can be found at the :zephyr:board:`bl654_dvk` site and :zephyr_file:`boards/ezurio/bl654_dvk/doc/bl654_dvk.rst` Flashing diff --git a/boards/ezurio/bt510/Kconfig.defconfig b/boards/ezurio/bt510/Kconfig.defconfig index 70cb87fa1f7..42cd1488a22 100644 --- a/boards/ezurio/bt510/Kconfig.defconfig +++ b/boards/ezurio/bt510/Kconfig.defconfig @@ -5,9 +5,6 @@ if BOARD_BT510 -config BT_CTLR - default BT - config I2C default SENSOR diff --git a/boards/ezurio/bt510/doc/bt510.rst b/boards/ezurio/bt510/doc/bt510.rst index bcdaf272265..fdfd9312ffe 100644 --- a/boards/ezurio/bt510/doc/bt510.rst +++ b/boards/ezurio/bt510/doc/bt510.rst @@ -1,7 +1,4 @@ -.. _bt510: - -Ezurio Sentrius BT510 Sensor -############################ +.. zephyr:board:: bt510 Overview ******** @@ -24,12 +21,6 @@ The sensor has the following features: * :abbr:`UART (Universal Asynchronous Receiver-Transmitter)` * :abbr:`WDT (Watchdog Timer)` -.. figure:: img/bt510.jpg - :align: center - :alt: Sentrius BT510 Sensor, front view - - Sentrius BT510 Sensor, front view - .. figure:: img/bt510_back.jpg :align: center :alt: Sentrius BT510 Sensor, rear view diff --git a/boards/ezurio/bt610/Kconfig.defconfig b/boards/ezurio/bt610/Kconfig.defconfig index 9a82770655e..04963261957 100644 --- a/boards/ezurio/bt610/Kconfig.defconfig +++ b/boards/ezurio/bt610/Kconfig.defconfig @@ -5,9 +5,6 @@ if BOARD_BT610 -config BT_CTLR - default BT - config I2C default $(dt_compat_on_bus,$(DT_COMPAT_TI_TCA9538),i2c) diff --git a/boards/ezurio/bt610/doc/bt610.rst b/boards/ezurio/bt610/doc/bt610.rst index 528186ec880..0ae62035a48 100644 --- a/boards/ezurio/bt610/doc/bt610.rst +++ b/boards/ezurio/bt610/doc/bt610.rst @@ -1,7 +1,4 @@ -.. _bt610: - -Ezurio Sentrius BT610 Sensor -############################ +.. zephyr:board:: bt610 Overview ******** @@ -28,12 +25,6 @@ The sensor has the following features: * :abbr:`UART (Universal Asynchronous Receiver-Transmitter)` * :abbr:`WDT (Watchdog Timer)` -.. figure:: img/bt610_front.jpg - :align: center - :alt: Sentrius BT610 Sensor, front view - - Sentrius BT610 Sensor, front view - .. figure:: img/bt610_back.jpg :align: center :alt: Sentrius BT610 Sensor, rear view diff --git a/boards/ezurio/bt610/doc/img/bt610_front.jpg b/boards/ezurio/bt610/doc/img/bt610.jpg similarity index 100% rename from boards/ezurio/bt610/doc/img/bt610_front.jpg rename to boards/ezurio/bt610/doc/img/bt610.jpg diff --git a/boards/ezurio/mg100/Kconfig.defconfig b/boards/ezurio/mg100/Kconfig.defconfig index 0db2eee8478..ff0ba3feee1 100644 --- a/boards/ezurio/mg100/Kconfig.defconfig +++ b/boards/ezurio/mg100/Kconfig.defconfig @@ -15,7 +15,4 @@ config NORDIC_QSPI_NOR_FLASH_LAYOUT_PAGE_SIZE config REGULATOR default DISK_DRIVER_SDMMC -config BT_CTLR - default BT - endif # BOARD_MG100 diff --git a/boards/ezurio/mg100/doc/index.rst b/boards/ezurio/mg100/doc/index.rst index 86b92c52abf..5f66c65e147 100644 --- a/boards/ezurio/mg100/doc/index.rst +++ b/boards/ezurio/mg100/doc/index.rst @@ -1,7 +1,4 @@ -.. _mg100: - -Ezurio Sentrius™ MG100 Gateway -############################## +.. zephyr:board:: mg100 Overview ******** @@ -46,12 +43,6 @@ and the following devices: * :abbr:`HL7800 (Sierra Wireless HL7800 LTE-M1/NB-IoT modem)` * :abbr:`SD Card` -.. figure:: img/mg100.jpg - :align: center - :alt: MG100 - - MG100 (450-00054-K1) - Hardware ******** diff --git a/boards/ezurio/mg100/mg100.dts b/boards/ezurio/mg100/mg100.dts index de091a3ab66..18826ed8956 100644 --- a/boards/ezurio/mg100/mg100.dts +++ b/boards/ezurio/mg100/mg100.dts @@ -154,6 +154,7 @@ spi-max-frequency = <8000000>; mmc { compatible = "zephyr,sdmmc-disk"; + disk-name = "SD"; status = "okay"; }; }; diff --git a/boards/ezurio/pinnacle_100_dvk/Kconfig.defconfig b/boards/ezurio/pinnacle_100_dvk/Kconfig.defconfig index c53ec05d15a..299754eda5a 100644 --- a/boards/ezurio/pinnacle_100_dvk/Kconfig.defconfig +++ b/boards/ezurio/pinnacle_100_dvk/Kconfig.defconfig @@ -14,7 +14,4 @@ config MODEM_HL7800 config NORDIC_QSPI_NOR_FLASH_LAYOUT_PAGE_SIZE default 4096 -config BT_CTLR - default BT - endif # BOARD_PINNACLE_100_DVK diff --git a/boards/ezurio/pinnacle_100_dvk/doc/index.rst b/boards/ezurio/pinnacle_100_dvk/doc/index.rst index 7b63ada033b..71511d8dfc8 100644 --- a/boards/ezurio/pinnacle_100_dvk/doc/index.rst +++ b/boards/ezurio/pinnacle_100_dvk/doc/index.rst @@ -1,7 +1,4 @@ -.. _pinnacle_100_dvk: - -Ezurio Pinnacle 100 DVK -####################### +.. zephyr:board:: pinnacle_100_dvk Overview ******** @@ -49,12 +46,6 @@ and the following devices: * :abbr:`BME680 (Bosch Sensortec BME680 environmental sensor)` * :abbr:`HL7800 (Sierra Wireless HL7800 LTE-M1/NB-IoT modem)` -.. figure:: img/pinnacle_100_dvk.jpg - :align: center - :alt: Pinnacle 100 DVK - - Pinnacle 100 DVK (453-00010-K1) - Hardware ******** diff --git a/boards/ezurio/rm1xx_dvk/Kconfig.defconfig b/boards/ezurio/rm1xx_dvk/Kconfig.defconfig index 01cbc05ee78..27d934196f1 100644 --- a/boards/ezurio/rm1xx_dvk/Kconfig.defconfig +++ b/boards/ezurio/rm1xx_dvk/Kconfig.defconfig @@ -5,7 +5,4 @@ if BOARD_RM1XX_DVK -config BT_CTLR - default BT - endif # BOARD_RM1XX_DVK diff --git a/boards/ezurio/rm1xx_dvk/doc/img/RM186-DVK.jpg b/boards/ezurio/rm1xx_dvk/doc/img/rm1xx_dvk.jpg similarity index 100% rename from boards/ezurio/rm1xx_dvk/doc/img/RM186-DVK.jpg rename to boards/ezurio/rm1xx_dvk/doc/img/rm1xx_dvk.jpg diff --git a/boards/ezurio/rm1xx_dvk/doc/index.rst b/boards/ezurio/rm1xx_dvk/doc/index.rst index bd57e8f400d..8462f92c1b2 100644 --- a/boards/ezurio/rm1xx_dvk/doc/index.rst +++ b/boards/ezurio/rm1xx_dvk/doc/index.rst @@ -1,7 +1,4 @@ -.. _rm1xx_dvk: - -Ezurio RM1xx DVK -################ +.. zephyr:board:: rm1xx_dvk Overview ******** @@ -28,12 +25,6 @@ This development kit has the following features: * :abbr:`UART (Universal asynchronous receiver-transmitter)` * :abbr:`WDT (Watchdog Timer)` -.. figure:: img/RM186-DVK.jpg - :align: center - :alt: RM1xx development kit (DVK) - - RM1xx development kit (DVK) (Credit: Ezurio) - .. figure:: img/RM186-SM.jpg :align: center :alt: RM1xx module diff --git a/boards/ezurio/rm1xx_dvk/rm1xx_dvk_defconfig b/boards/ezurio/rm1xx_dvk/rm1xx_dvk_defconfig index 46dc69d74cd..1289685e1e8 100644 --- a/boards/ezurio/rm1xx_dvk/rm1xx_dvk_defconfig +++ b/boards/ezurio/rm1xx_dvk/rm1xx_dvk_defconfig @@ -9,5 +9,3 @@ CONFIG_SERIAL=y # enable console CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y - -CONFIG_PINCTRL=y diff --git a/boards/fanke/fk750m1_vbt6/Kconfig.fk750m1_vbt6 b/boards/fanke/fk750m1_vbt6/Kconfig.fk750m1_vbt6 new file mode 100644 index 00000000000..7c73267ab61 --- /dev/null +++ b/boards/fanke/fk750m1_vbt6/Kconfig.fk750m1_vbt6 @@ -0,0 +1,5 @@ +# Copyright (c) 2024 zack jiang <1125934312@qq.com> +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_FK750M1_VBT6 + select SOC_STM32H750XX diff --git a/boards/fanke/fk750m1_vbt6/board.cmake b/boards/fanke/fk750m1_vbt6/board.cmake new file mode 100644 index 00000000000..3932958fd1d --- /dev/null +++ b/boards/fanke/fk750m1_vbt6/board.cmake @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(openocd --target-handle=_CHIPNAME.cpu0) +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") +board_runner_args(jlink "--device=STM32H750VB" "--speed=4000") + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/fanke/fk750m1_vbt6/board.yml b/boards/fanke/fk750m1_vbt6/board.yml new file mode 100644 index 00000000000..2aae1f00b73 --- /dev/null +++ b/boards/fanke/fk750m1_vbt6/board.yml @@ -0,0 +1,6 @@ +board: + name: fk750m1_vbt6 + full_name: FK750M1-VBT6 + vendor: fanke + socs: + - name: stm32h750xx diff --git a/boards/fanke/fk750m1_vbt6/doc/img/fk750m1_vbt6.webp b/boards/fanke/fk750m1_vbt6/doc/img/fk750m1_vbt6.webp new file mode 100644 index 00000000000..cc86302e95a Binary files /dev/null and b/boards/fanke/fk750m1_vbt6/doc/img/fk750m1_vbt6.webp differ diff --git a/boards/fanke/fk750m1_vbt6/doc/index.rst b/boards/fanke/fk750m1_vbt6/doc/index.rst new file mode 100644 index 00000000000..6a558bddc08 --- /dev/null +++ b/boards/fanke/fk750m1_vbt6/doc/index.rst @@ -0,0 +1,157 @@ +.. zephyr:board:: fk750m1_vbt6 + +Overview +******** + +The FK750M1-VBT6 core board by FANKE Technology Co., Ltd. is an advanced microcontroller +platform based on the STMicroelectronics Arm® Cortex®-M7 core STM32H750VBT6 microcontroller. +This board is an ideal solution for developers looking to create high-performance +applications, leveraging its robust capabilities and support for sophisticated display +and image processing technologies. + +The FK750M1-VBT6 is designed as a reference design for user application development before +transitioning to the final product, significantly simplifying the development process. +Its wide range of hardware features, including advanced display and image processing capabilities, +allowing for comprehensive evaluation and testing of peripherals and functionalities. + +Hardware +******** + +FK750M1-VBT6 provides the following hardware components: + +- STM32H750VB in LQFP100 package +- ARM 32-bit Cortex-M7 CPU with FPU +- 480 MHz max CPU frequency +- 128 KB Flash +- 1 MB SRAM: 192 Kbytes TCM RAM (64 Kbytes ITCM RAM + 128 Kbytes DTCM RAM), 864 Kbytes user SRAM, and 4 Kbytes SRAM in Backup domain +- Main clock: External 25MHz crystal oscillator. +- RTC: 32.768kHz crystal oscillator. +- high-resolution timers(2.1 ns max resolution, 1) +- 32-bit timers(2) +- 16-bit timers(17) +- 1 reset button, and 1 BOOT button +- 1 user LED +- External 64-Mbit QSPI (W25Q64) NOR Flash memory. +- USB OTG Full Speed and High Speed(1) +- 1 micro SD card +- 1 DCMI camera interface +- 1 SPI LCD interface +- SWD and serial port accessibility through a pin header +- Bring out 73 IO ports + +More information about STM32H750VB can be found here: + +- `STM32H750VB on www.st.com`_ + +Supported Features +================== + +The Zephyr ``fk750m1_vbt6`` board target supports the following hardware +features: + ++-------------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++=============+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-------------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-------------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++-------------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-------------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-------------+------------+-------------------------------------+ +| RNG | on-chip | True Random number generator | ++-------------+------------+-------------------------------------+ +| Backup SRAM | on-chip | Backup SRAM | ++-------------+------------+-------------------------------------+ +| SPI | on-chip | spi bus | ++-------------+------------+-------------------------------------+ +| QUADSPI | on-chip | quadspi | ++-------------+------------+-------------------------------------+ + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration per core can be found in +:zephyr_file:`boards/fanke/fk750m1_vbt6/fk750m1_vbt6_defconfig` + +Pin Mapping +=========== + +FK750M1-VBT6 board has 5 GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +The FK750M1-VBT6 board is configured as follows + +- UART_1 TX/RX : PA9/PA10 (available on the header pins) +- User LED (blue) : PC13 +- SPI4 NCS/CLK/MOSI : PE11/PE12/PE14 (SPI LCD) +- QuadSPI NCS/CLK/IO0/IO1/IO2/IO3 : PB6/PB2/PD11/PD12/PE2/PD13 (NOR Flash) +- USB DM/DP : PA11/PA12 + +System Clock +============ + +The FK750M1-VBT6 System Clock could be driven by an internal or external oscillator, +as well as by the main PLL clock. By default the system clock is driven by the PLL clock at 480MHz, +driven by an 25MHz external crystal oscillator. + +Serial Port +=========== + +The Zephyr console output is assigned to UART1. The default communication settings are 115200 8N1. + +Programming and Debugging +************************* + +Applications for the ``fk750m1_vbt6`` board target can be built and flashed in the usual +way (see :ref:`build_an_application` and :ref:`application_run` for more details). + +Flashing +======== + +The FK750M1-VBT6 board does not include an on-board debugger. As a result, it requires +an external debugger, such as ST-Link, for programming and debugging purposes. + +The board provides header pins for the Serial Wire Debug (SWD) interface. + +Flashing an application to FK750M1-VBT6 +--------------------------------------- + +To begin, connect the ST-Link Debug Programmer to the FK750M1-VBT6 board using the SWD +interface. Next, connect the ST-Link to your host computer via a USB port. +Once this setup is complete, you can proceed to build and flash your application to the board + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: fk750m1_vbt6 + :goals: build flash + +Run a serial host program to connect with your board: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 -b 115200 + +Then, press the RESET button, you should see the following message: + +.. code-block:: console + + Hello World! fk750m1_vbt6 + +Debugging +========= + +This current Zephyr port does not support debugging. + +References +********** + +.. target-notes:: +.. _STM32H750VB on www.st.com: https://www.st.com/en/microcontrollers/stm32h750vb.html diff --git a/boards/fanke/fk750m1_vbt6/fk750m1_vbt6.dts b/boards/fanke/fk750m1_vbt6/fk750m1_vbt6.dts new file mode 100644 index 00000000000..a3351b7e864 --- /dev/null +++ b/boards/fanke/fk750m1_vbt6/fk750m1_vbt6.dts @@ -0,0 +1,171 @@ +/* + * Copyright (c) 2024 zack jiang <1125934312@qq.com> + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include +#include +#include + +/ { + model = "FANKE FK750M1-VBT6 board"; + compatible = "fanke,fk750m1-vbt6"; + + chosen { + zephyr,console = &usart1; + zephyr,shell-uart = &usart1; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,display = &st7789v_240x240; + }; + + leds { + compatible = "gpio-leds"; + user_led: led_0 { + gpios = <&gpioc 13 GPIO_ACTIVE_LOW>; + label = "User LED"; + }; + }; + + aliases { + led0 = &user_led; + }; + + mipi_dbi_st7789v_240x240 { + compatible = "zephyr,mipi-dbi-spi"; + spi-dev = <&spi4>; + dc-gpios = <&gpioe 15 GPIO_ACTIVE_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + + st7789v_240x240: st7789v@0 { + compatible = "sitronix,st7789v"; + mipi-max-frequency = <20000000>; + reg = <0>; + width = <240>; + height = <240>; + x-offset = <0>; + y-offset = <0>; + vcom = <0x19>; + gctrl = <0x35>; + vrhs = <0x12>; + vdvs = <0x20>; + mdac = <0x00>; + gamma = <0x01>; + colmod = <0x05>; + lcm = <0x2c>; + porch-param = [0c 0c 00 33 33]; + cmd2en-param = [5a 69 02 01]; + pwctrl1-param = [a4 a1]; + pvgam-param = [D0 04 0D 11 13 2B 3F 54 4C 18 0D 0B 1F 23]; + nvgam-param = [D0 04 0C 11 13 2C 3F 44 51 2F 1F 1F 20 23]; + ram-param = [00 F0]; + rgb-param = [CD 08 14]; + mipi-mode = "MIPI_DBI_MODE_SPI_4WIRE"; + }; + }; +}; + +&clk_hsi48 { + status = "okay"; +}; + +&clk_hse { + clock-frequency = ; + status = "okay"; +}; + +&pll { + div-m = <5>; + mul-n = <192>; + div-p = <2>; + div-q = <4>; + div-r = <4>; + clocks = <&clk_hse>; + status = "okay"; +}; + +&pll3 { + div-m = <5>; + mul-n = <192>; + div-p = <2>; + div-q = <20>; + div-r = <99>; + clocks = <&clk_hse>; + status = "okay"; +}; + +&rcc { + clocks = <&pll>; + clock-frequency = ; + d1cpre = <1>; + hpre = <2>; + d1ppre = <2>; + d2ppre1 = <2>; + d2ppre2 = <2>; + d3ppre = <2>; +}; + +&quadspi { + pinctrl-0 = <&quadspi_bk1_io0_pd11 &quadspi_bk1_io1_pd12 + &quadspi_bk1_io2_pe2 &quadspi_bk1_io3_pd13 + &quadspi_clk_pb2 &quadspi_bk1_ncs_pb6>; + pinctrl-names = "default"; + status = "okay"; + + /* Winbond external flash */ + w25q64_qspi: qspi-nor-flash@90000000 { + compatible = "st,stm32-qspi-nor"; + reg = <0x90000000 DT_SIZE_M(64)>; /* 64 Mbits */ + qspi-max-frequency = <40000000>; + status = "okay"; + spi-bus-width = <4>; + writeoc = "PP_1_1_4"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + storage_partition: partition@0 { + label = "storage"; + reg = <0x00000000 DT_SIZE_M(64)>; + }; + }; + }; +}; + +&spi4 { + pinctrl-0 = <&spi4_sck_pe12 &spi4_mosi_pe14>; + cs-gpios = <&gpioe 11 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + status = "okay"; +}; + +&gpiod { + status = "okay"; + + lcd_led { + gpio-hog; + gpios = <15 GPIO_ACTIVE_HIGH>; + output-high; + }; +}; + +&usart1 { + pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>; + pinctrl-names = "default"; + current-speed = <115200>; + status = "okay"; +}; + +&backup_sram { + status = "okay"; +}; + +&rng { + status = "okay"; +}; diff --git a/boards/fanke/fk750m1_vbt6/fk750m1_vbt6.yaml b/boards/fanke/fk750m1_vbt6/fk750m1_vbt6.yaml new file mode 100644 index 00000000000..ffb5170ae82 --- /dev/null +++ b/boards/fanke/fk750m1_vbt6/fk750m1_vbt6.yaml @@ -0,0 +1,14 @@ +identifier: fk750m1_vbt6 +name: FANKE FK750M1-VBT6 +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 1024 +flash: 128 +supported: + - uart + - gpio +vendor: fanke diff --git a/boards/fanke/fk750m1_vbt6/fk750m1_vbt6_defconfig b/boards/fanke/fk750m1_vbt6/fk750m1_vbt6_defconfig new file mode 100644 index 00000000000..527b26b55e6 --- /dev/null +++ b/boards/fanke/fk750m1_vbt6/fk750m1_vbt6_defconfig @@ -0,0 +1,18 @@ +# Copyright (c) zack jiang <1125934312@qq.com> +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable HW stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable UART +CONFIG_SERIAL=y + +# Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable GPIO +CONFIG_GPIO=y diff --git a/boards/fanke/fk750m1_vbt6/support/openocd.cfg b/boards/fanke/fk750m1_vbt6/support/openocd.cfg new file mode 100644 index 00000000000..1db2475768a --- /dev/null +++ b/boards/fanke/fk750m1_vbt6/support/openocd.cfg @@ -0,0 +1,25 @@ +# Copyright (c) zack jiang <1125934312@qq.com> +# SPDX-License-Identifier: Apache-2.0 + +source [find interface/stlink-dap.cfg] +transport select "dapdirect_swd" + +set WORKAREASIZE 0x8000 + +set CHIPNAME STM32H750VB +set BOARDNAME FK750M1-VBT6 + +source [find target/stm32h7x.cfg] + +# Enable debug when in low power modes +set ENABLE_LOW_POWER 1 + +# Stop Watchdog counters when halt +set STOP_WATCHDOG 1 + +# Reset configuration +# use hardware reset, connect under reset +# connect_assert_srst needed if low power mode application running (WFI...) +reset_config srst_only srst_nogate connect_assert_srst +set CONNECT_UNDER_RESET 1 +set CORE_RESET 0 diff --git a/boards/fanke/fk7b0m1_vbt6/fk7b0m1_vbt6.yaml b/boards/fanke/fk7b0m1_vbt6/fk7b0m1_vbt6.yaml index f847d49f450..e50692f318a 100644 --- a/boards/fanke/fk7b0m1_vbt6/fk7b0m1_vbt6.yaml +++ b/boards/fanke/fk7b0m1_vbt6/fk7b0m1_vbt6.yaml @@ -1,5 +1,5 @@ identifier: fk7b0m1_vbt6 -name: FANKE FK7B0M1-VBT6 board +name: FANKE FK7B0M1-VBT6 type: mcu arch: arm toolchain: diff --git a/boards/firefly/roc_rk3568_pc/doc/index.rst b/boards/firefly/roc_rk3568_pc/doc/index.rst index 4da6df1023a..bd55e747c51 100644 --- a/boards/firefly/roc_rk3568_pc/doc/index.rst +++ b/boards/firefly/roc_rk3568_pc/doc/index.rst @@ -1,7 +1,4 @@ -.. _roc_rk3568_pc: - -Firefly ROC-RK3568-PC (Quad-core Cortex-A55) -############################################ +.. zephyr:board:: roc_rk3568_pc Overview ******** diff --git a/boards/franzininho/esp32s2_franzininho/Kconfig b/boards/franzininho/esp32s2_franzininho/Kconfig new file mode 100644 index 00000000000..c6a99b1032d --- /dev/null +++ b/boards/franzininho/esp32s2_franzininho/Kconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 4096 diff --git a/boards/franzininho/esp32s2_franzininho/Kconfig.defconfig b/boards/franzininho/esp32s2_franzininho/Kconfig.defconfig deleted file mode 100644 index 7bf6f84463b..00000000000 --- a/boards/franzininho/esp32s2_franzininho/Kconfig.defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# ESP32S2 Franzininho board configuration - -# Copyright (c) 2022 Felipe Neves -# SPDX-License-Identifier: Apache-2.0 - -config ENTROPY_GENERATOR - default y - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 32768 if WIFI - default 4096 diff --git a/boards/franzininho/esp32s2_franzininho/doc/index.rst b/boards/franzininho/esp32s2_franzininho/doc/index.rst index efa47c90719..47f223b83ca 100644 --- a/boards/franzininho/esp32s2_franzininho/doc/index.rst +++ b/boards/franzininho/esp32s2_franzininho/doc/index.rst @@ -1,7 +1,4 @@ -.. _esp32s2_franzininho: - -ESP32-S2 Franzininho -#################### +.. zephyr:board:: esp32s2_franzininho Overview ******** @@ -30,10 +27,6 @@ The features include the following: - DAC - LED PWM with up to 8 channels -.. figure:: img/esp32_s2_franzininho.jpg - :align: center - :alt: ESP32-S2 FRANZININHO - System requirements =================== @@ -173,6 +166,8 @@ message in the monitor: References ********** +.. target-notes:: + .. [1] https://www.espressif.com/en/products/socs/esp32-s2 .. _`ESP32S2 Technical Reference Manual`: https://espressif.com/sites/default/files/documentation/esp32-s2_technical_reference_manual_en.pdf .. _`ESP32S2 Datasheet`: https://www.espressif.com/sites/default/files/documentation/esp32-s2_datasheet_en.pdf diff --git a/boards/franzininho/esp32s2_franzininho/esp32s2_franzininho.dts b/boards/franzininho/esp32s2_franzininho/esp32s2_franzininho.dts index 74d5f7610a9..beee6810d62 100644 --- a/boards/franzininho/esp32s2_franzininho/esp32s2_franzininho.dts +++ b/boards/franzininho/esp32s2_franzininho/esp32s2_franzininho.dts @@ -8,6 +8,7 @@ #include #include "esp32s2_franzininho-pinctrl.dtsi" +#include / { model = "ESP32S2 Franzininho"; @@ -107,45 +108,6 @@ pinctrl-names = "default"; }; -&flash0 { - status = "okay"; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Reserve 60kB for the bootloader */ - boot_partition: partition@1000 { - label = "mcuboot"; - reg = <0x00001000 0x0000F000>; - read-only; - }; - - /* Reserve 1024kB for the application in slot 0 */ - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 0x00100000>; - }; - - /* Reserve 1024kB for the application in slot 1 */ - slot1_partition: partition@110000 { - label = "image-1"; - reg = <0x00110000 0x00100000>; - }; - - /* Reserve 256kB for the scratch partition */ - scratch_partition: partition@210000 { - label = "image-scratch"; - reg = <0x00210000 0x00040000>; - }; - - storage_partition: partition@250000 { - label = "storage"; - reg = <0x00250000 0x00006000>; - }; - }; -}; - &wdt0 { status = "okay"; }; diff --git a/boards/franzininho/esp32s2_franzininho/esp32s2_franzininho.yaml b/boards/franzininho/esp32s2_franzininho/esp32s2_franzininho.yaml index 0a227dc6021..da3da1bdc3a 100644 --- a/boards/franzininho/esp32s2_franzininho/esp32s2_franzininho.yaml +++ b/boards/franzininho/esp32s2_franzininho/esp32s2_franzininho.yaml @@ -14,6 +14,4 @@ supported: testing: ignore_tags: - heap - - net - - bluetooth vendor: franzininho diff --git a/boards/fysetc/index.rst b/boards/fysetc/index.rst new file mode 100644 index 00000000000..546023ba7b0 --- /dev/null +++ b/boards/fysetc/index.rst @@ -0,0 +1,10 @@ +.. _boards-fysetc: + +FYSETC +###### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/fysetc/ucan/Kconfig.ucan b/boards/fysetc/ucan/Kconfig.ucan new file mode 100644 index 00000000000..c88f895ea01 --- /dev/null +++ b/boards/fysetc/ucan/Kconfig.ucan @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Henrik Brix Andersen +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_UCAN + select SOC_STM32F072XB diff --git a/boards/fysetc/ucan/board.cmake b/boards/fysetc/ucan/board.cmake new file mode 100644 index 00000000000..c383530f74c --- /dev/null +++ b/boards/fysetc/ucan/board.cmake @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Henrik Brix Andersen +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(dfu-util "--pid=0483:df11" "--alt=0" "--dfuse") +board_runner_args(jlink "--device=STM32F072CB") + +include(${ZEPHYR_BASE}/boards/common/dfu-util.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/fysetc/ucan/board.yml b/boards/fysetc/ucan/board.yml new file mode 100644 index 00000000000..3e9b1d3b092 --- /dev/null +++ b/boards/fysetc/ucan/board.yml @@ -0,0 +1,6 @@ +board: + name: ucan + full_name: UCAN + vendor: fysetc + socs: + - name: stm32f072xb diff --git a/boards/fysetc/ucan/doc/index.rst b/boards/fysetc/ucan/doc/index.rst new file mode 100644 index 00000000000..f9b4b53809f --- /dev/null +++ b/boards/fysetc/ucan/doc/index.rst @@ -0,0 +1,71 @@ +.. zephyr:board:: ucan + +Overview +******** + +The FYSETC UCAN is an open-source USB to CAN 2.0B adapter board. More information can be found on +the `UCAN website`_ and in the `UCAN wiki`_. + +Hardware +******** + +The UCAN board is equipped with a STM32F072CB microcontroller and features an USB-C connector, a +terminal block for connecting to the CAN bus, and two user LEDs. Schematics and component placement +drawings are available in the `UCAN GitHub repository`_. + +Supported Features +================== + +The ``ucan`` board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| USB | on-chip | USB | ++-----------+------------+-------------------------------------+ +| CAN1 | on-chip | CAN controller | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/fysetc/ucan/ucan_defconfig`. + +Other hardware features are not currently supported by the port. + +System Clock +============ + +The STM32F072CB PLL is driven by an external crystal oscillator (HSE) running at 8 MHz and +configured to provide a system clock of 48 MHz. + +Programming and Debugging +************************* + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +If flashing via USB DFU, short pins ``B0`` and ``3V3`` when applying power to the UCAN board in +order to enter the built-in DFU mode. + +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: ucan + :goals: flash + +.. _UCAN website: + https://www.fysetc.com/products/fysetc-ucan-board + +.. _UCAN wiki: + https://wiki.fysetc.com/UCAN/ + +.. _UCAN GitHub repository: + https://github.com/FYSETC/UCAN/ diff --git a/boards/fysetc/ucan/doc/ucan.webp b/boards/fysetc/ucan/doc/ucan.webp new file mode 100644 index 00000000000..427747f4296 Binary files /dev/null and b/boards/fysetc/ucan/doc/ucan.webp differ diff --git a/boards/fysetc/ucan/ucan.dts b/boards/fysetc/ucan/ucan.dts new file mode 100644 index 00000000000..a0f47da9256 --- /dev/null +++ b/boards/fysetc/ucan/ucan.dts @@ -0,0 +1,96 @@ +/* + * Copyright (c) 2024 Henrik Brix Andersen + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include + +/ { + model = "FYSETC UCAN board"; + compatible = "fysetc,ucan"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + zephyr,canbus = &can1; + }; + + aliases { + led0 = &led_rx; + led1 = &led_tx; + }; + + leds { + compatible = "gpio-leds"; + led_rx: led_rx { + gpios = <&gpioa 0 GPIO_ACTIVE_HIGH>; + label = "LED RX"; + }; + led_tx: led_tx { + gpios = <&gpioa 1 GPIO_ACTIVE_HIGH>; + label = "LED TX"; + }; + }; + + transceiver0: can-phy0 { + compatible = "can-transceiver-gpio"; + enable-gpios = <&gpioc 13 GPIO_ACTIVE_LOW>; + max-bitrate = <1000000>; + #phy-cells = <0>; + }; +}; + +&clk_hse { + status = "okay"; + clock-frequency = ; +}; + +&pll { + prediv = <1>; + mul = <6>; + clocks = <&clk_hse>; + status = "okay"; +}; + +&rcc { + clocks = <&pll>; + clock-frequency = ; + ahb-prescaler = <1>; + apb1-prescaler = <1>; +}; + +zephyr_udc0: &usb { + pinctrl-0 = <&usb_dm_pa11 &usb_dp_pa12>; + pinctrl-names = "default"; + status = "okay"; +}; + +&can1 { + pinctrl-0 = <&can_rx_pb8 &can_tx_pb9>; + pinctrl-names = "default"; + phys = <&transceiver0>; + status = "okay"; +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 DT_SIZE_K(48)>; + read-only; + }; + slot0_partition: partition@c000 { + label = "image-0"; + reg = <0x0000c000 DT_SIZE_K(80)>; + }; + }; +}; diff --git a/boards/fysetc/ucan/ucan.yaml b/boards/fysetc/ucan/ucan.yaml new file mode 100644 index 00000000000..cd65a21e1fd --- /dev/null +++ b/boards/fysetc/ucan/ucan.yaml @@ -0,0 +1,15 @@ +identifier: ucan +name: FYSETC UCAN +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb +ram: 16 +flash: 128 +supported: + - can + - gpio + - usb_device + - usbd +vendor: fysetc diff --git a/boards/fysetc/ucan/ucan_defconfig b/boards/fysetc/ucan/ucan_defconfig new file mode 100644 index 00000000000..91c3c15b37d --- /dev/null +++ b/boards/fysetc/ucan/ucan_defconfig @@ -0,0 +1 @@ +CONFIG_GPIO=y diff --git a/boards/gaisler/generic_leon3/doc/index.rst b/boards/gaisler/generic_leon3/doc/index.rst index 9ab9c897ce8..9f7781f3e21 100644 --- a/boards/gaisler/generic_leon3/doc/index.rst +++ b/boards/gaisler/generic_leon3/doc/index.rst @@ -1,7 +1,4 @@ -.. _generic_leon3: - -Generic LEON3 -############# +.. zephyr:board:: generic_leon3 Overview ******** diff --git a/boards/gaisler/generic_leon3/generic_leon3.yaml b/boards/gaisler/generic_leon3/generic_leon3.yaml index 3aecda82e0e..62130690461 100644 --- a/boards/gaisler/generic_leon3/generic_leon3.yaml +++ b/boards/gaisler/generic_leon3/generic_leon3.yaml @@ -1,8 +1,9 @@ identifier: generic_leon3 name: Generic LEON3 system type: mcu -simulation: tsim -simulation_exec: tsim-leon3 +simulation: + - name: tsim + exec: tsim-leon3 arch: sparc ram: 4096 flash: 2048 diff --git a/boards/gaisler/gr716a_mini/doc/index.rst b/boards/gaisler/gr716a_mini/doc/index.rst index c09374996e7..0f723306105 100644 --- a/boards/gaisler/gr716a_mini/doc/index.rst +++ b/boards/gaisler/gr716a_mini/doc/index.rst @@ -1,7 +1,4 @@ -.. _gr716a_mini: - -GR716-MINI Development Board -############################ +.. zephyr:board:: gr716a_mini Overview ******** @@ -16,12 +13,6 @@ The GR716-MINI development board provides: * 4x MMCX connectors (2 ADC, 2 DAC) * Miniature 80 pin mezzanine connector (bottom side) -.. figure:: gr716a_mini.jpg - :align: center - :alt: GR716-MINI Development Board - - GR716-MINI Development Board (Credit: Cobham Gaisler AB) - Hardware ******** diff --git a/boards/gaisler/gr716a_mini/gr716a_mini.yaml b/boards/gaisler/gr716a_mini/gr716a_mini.yaml index 7898925121e..4d2743602c6 100644 --- a/boards/gaisler/gr716a_mini/gr716a_mini.yaml +++ b/boards/gaisler/gr716a_mini/gr716a_mini.yaml @@ -1,8 +1,9 @@ identifier: gr716a_mini name: GR716-MINI Development Board type: mcu -simulation: tsim -simulation_exec: tsim-leon3 +simulation: + - name: tsim + exec: tsim-leon3 arch: sparc toolchain: - zephyr diff --git a/boards/gardena/index.rst b/boards/gardena/index.rst new file mode 100644 index 00000000000..48aa599c7b6 --- /dev/null +++ b/boards/gardena/index.rst @@ -0,0 +1,10 @@ +.. _boards-gardena: + +GARDENA GmbH +############ + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/gardena/sgrm/Kconfig.sgrm b/boards/gardena/sgrm/Kconfig.sgrm new file mode 100644 index 00000000000..3a758c2eaf7 --- /dev/null +++ b/boards/gardena/sgrm/Kconfig.sgrm @@ -0,0 +1,6 @@ +# Copyright (c) 2024 GARDENA GmbH +# +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_SGRM + select SOC_PART_NUMBER_SIM3U167BGM diff --git a/boards/gardena/sgrm/board.cmake b/boards/gardena/sgrm/board.cmake new file mode 100644 index 00000000000..60f466d5539 --- /dev/null +++ b/boards/gardena/sgrm/board.cmake @@ -0,0 +1,8 @@ +# Copyright (c) 2024 GARDENA GmbH +# +# SPDX-License-Identifier: Apache-2.0 + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) + +board_runner_args(jlink "--device=SiM3U167") +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/gardena/sgrm/board.yml b/boards/gardena/sgrm/board.yml new file mode 100644 index 00000000000..1d1c1dcc843 --- /dev/null +++ b/boards/gardena/sgrm/board.yml @@ -0,0 +1,10 @@ +# Copyright (c) 2024 GARDENA GmbH +# +# SPDX-License-Identifier: Apache-2.0 + +board: + name: sgrm + full_name: Smart Garden Radio Module + vendor: gardena + socs: + - name: sim3u167 diff --git a/boards/gardena/sgrm/doc/index.rst b/boards/gardena/sgrm/doc/index.rst new file mode 100644 index 00000000000..40d05a9f4f3 --- /dev/null +++ b/boards/gardena/sgrm/doc/index.rst @@ -0,0 +1,105 @@ +.. zephyr:board:: sgrm + +Overview +******** + +This is a SoM that is used as a radio module by the GARDENA smart gateway (manual_, `FOSS parts`_). + +.. _manual: https://content.tdr.dss.husqvarnagroup.net/pub000094159/doc000240276 +.. _FOSS parts: https://github.com/husqvarnagroup/smart-garden-gateway-public + +Hardware +******** + +- Silicon Labs SiM3U167-B-GM_ SoC +- Silicon Labs Si4467_ transceiver (via SPI) +- Controls an RGB LED via high drive pins. It's expected to mirror the state of 3 low-drive pins + coming from the Linux SoC. +- UART is connected to the Linux SoC. Usually it's used for PPP, but it can also be used for + debugging when PPP is not active. + +.. _SiM3U167-B-GM: https://www.silabs.com/mcu/32-bit-microcontrollers/precision32-sim3u1xx/device.SiM3U167-B-GQ?tab=specs +.. _Si4467: https://www.silabs.com/wireless/proprietary/ezradiopro-sub-ghz-ics/device.si4467?tab=specs + +Supported Features +================== + +The ``sgrm`` board target supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| DMA | on-chip | dma | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ + +Connections and IOs +=================== + ++--------+--------------------------+----------------------------------------------------+ +| Pin | Name | Note | ++========+==========================+====================================================+ +| PB0.0 | TX (O) | Serial connection to the Linux SoM | ++--------+--------------------------+ | +| PB0.1 | RX (I) | | ++--------+--------------------------+ | +| PB0.2 | RTS (O) | | ++--------+--------------------------+ | +| PB0.3 | CTS (I) | | ++--------+--------------------------+----------------------------------------------------+ +| PB0.4 | LED red (I) | Controlled by the Linux SoM | ++--------+--------------------------+ | +| PB0.5 | LED green (I) | | ++--------+--------------------------+ | +| PB0.6 | LED blue (I) | | ++--------+--------------------------+----------------------------------------------------+ +| PB0.13 | TX (O) | UART1 for debugging (no connection to Linux SoM) | ++--------+--------------------------+ | +| PB0.14 | RX (I) | | ++--------+--------------------------+----------------------------------------------------+ +| PB4.0 | LED red (O) | Mirrors PB0.4 | ++--------+--------------------------+----------------------------------------------------+ +| PB4.1 | LED green (O) | Mirrors PB0.5 | ++--------+--------------------------+----------------------------------------------------+ +| PB4.2 | LED blue (O) | Mirrors PB0.6 | ++--------+--------------------------+----------------------------------------------------+ + +Programming and Debugging +************************* + +Flashing +======== + +The easiest way is to do this via SSH from the Linux SoM that's connected to the SiM3U SoM. + +On your building machine: + +.. code-block:: shell + + scp -O build/zephyr/zephyr.hex root@IP:/tmp/ + +On the gateway: + +.. code-block:: shell + + openocd -f board/gardena_radio.cfg -c 'program /tmp/zephyr.hex verify exit' + reset-rm + +Debugging +========= + +The easiest way is to do this via SSH from the Linux gateway as well: + +.. code-block:: shell + + openocd -f board/gardena_radio.cfg -c init diff --git a/boards/gardena/sgrm/doc/sgrm.webp b/boards/gardena/sgrm/doc/sgrm.webp new file mode 100644 index 00000000000..5b62da13807 Binary files /dev/null and b/boards/gardena/sgrm/doc/sgrm.webp differ diff --git a/boards/gardena/sgrm/sgrm-pinctrl.dtsi b/boards/gardena/sgrm/sgrm-pinctrl.dtsi new file mode 100644 index 00000000000..61111630813 --- /dev/null +++ b/boards/gardena/sgrm/sgrm-pinctrl.dtsi @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2024 GARDENA GmbH + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + usart0_default: usart0_default { + group1 { + pinmux = , + ; + output-enable; + }; + group2 { + pinmux = , + ; + input-enable; + }; + }; + + usart1_default: usart1_default { + group1 { + pinmux = ; + output-enable; + }; + group2 { + pinmux = ; + input-enable; + }; + }; +}; diff --git a/boards/gardena/sgrm/sgrm.dts b/boards/gardena/sgrm/sgrm.dts new file mode 100644 index 00000000000..58a9e90e97e --- /dev/null +++ b/boards/gardena/sgrm/sgrm.dts @@ -0,0 +1,92 @@ +/* + * Copyright (c) 2024 GARDENA GmbH + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "sgrm-pinctrl.dtsi" + +/ { + model = "GARDENA Smart Garden Radio Module"; + compatible = "gardena,sgrm-sim3u167", "silabs,sim3u167","silabs,sim3u"; + + chosen { + zephyr,console = &usart1; + zephyr,flash = &flash0; + zephyr,shell-uart = &usart1; + zephyr,sram = &sram0; + zephyr,ppp-uart = &usart0; + }; +}; + +&cpu0 { + clock-frequency = <76953600>; +}; + +&pll0 { + status = "okay"; +}; + +&clk_ahb { + clocks = <&pll0>; + status = "okay"; +}; + +&clk_apb { + divider = <2>; + status = "okay"; +}; + +&usart0 { + current-speed = <500000>; + pinctrl-0 = <&usart0_default>; + pinctrl-names = "default"; + hw-flow-control; + status = "okay"; +}; + +&usart1 { + current-speed = <115200>; + pinctrl-0 = <&usart1_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + disable-pullups; + status = "okay"; +}; + +&gpio3 { + status = "okay"; +}; + +&flash0 { + status = "okay"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + slot0_partition: partition@0 { + label = "image-0"; + reg = <0x00000000 DT_SIZE_K(192)>; + }; + + storage_partition: partition@30000 { + label = "storage"; + reg = <0x00030000 DT_SIZE_K(64)>; + }; + }; +}; diff --git a/boards/gardena/sgrm/sgrm.yaml b/boards/gardena/sgrm/sgrm.yaml new file mode 100644 index 00000000000..fe14fefec88 --- /dev/null +++ b/boards/gardena/sgrm/sgrm.yaml @@ -0,0 +1,21 @@ +# Copyright (c) 2024 GARDENA GmbH +# +# SPDX-License-Identifier: Apache-2.0 + +identifier: sgrm +name: GARDENA Smart Garden Radio Module +type: mcu +arch: arm +ram: 32 +flash: 256 +toolchain: + - gnuarmemb + - xtools + - zephyr +supported: + - dma + - flash + - gpio + - nvs + - uart +vendor: gardena diff --git a/boards/gardena/sgrm/sgrm_defconfig b/boards/gardena/sgrm/sgrm_defconfig new file mode 100644 index 00000000000..e7d47535289 --- /dev/null +++ b/boards/gardena/sgrm/sgrm_defconfig @@ -0,0 +1,9 @@ +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable GPIO +CONFIG_GPIO=y diff --git a/boards/gardena/sgrm/support/openocd.cfg b/boards/gardena/sgrm/support/openocd.cfg new file mode 100644 index 00000000000..87aca7aab60 --- /dev/null +++ b/boards/gardena/sgrm/support/openocd.cfg @@ -0,0 +1,24 @@ +# Copyright (c) 2024 GARDENA GmbH +# +# SPDX-License-Identifier: Apache-2.0 + +source [find interface/ftdi/olimex-arm-usb-ocd-h.cfg] +source [find interface/ftdi/olimex-arm-jtag-swd.cfg] + +source [find target/sim3x.cfg] + +# On SiM3U1xx, doing a chip reset also takes down the debug port. For this reason, we disable the +# chip reset and instead only reset the Cortex M via the AIRCR SYSRESETREQ bit, as suggested in the +# chip's errata: https://www.silabs.com/documents/public/errata/SiM3U1xx-SiM3C1xxErrata.pdf +cortex_m reset_config sysresetreq + +$_TARGETNAME configure -event gdb-attach { + echo "Debugger attaching: halting execution" + reset halt + gdb_breakpoint_override hard +} + +$_TARGETNAME configure -event gdb-detach { + echo "Debugger detaching: resuming execution" + resume +} diff --git a/boards/gd/gd32a503v_eval/doc/index.rst b/boards/gd/gd32a503v_eval/doc/index.rst index bd9170b16c4..8fcec05bdc3 100644 --- a/boards/gd/gd32a503v_eval/doc/index.rst +++ b/boards/gd/gd32a503v_eval/doc/index.rst @@ -1,8 +1,4 @@ -.. _gd32a503v_eval: - -GigaDevice GD32A503V-EVAL -######################### - +.. zephyr:board:: gd32a503v_eval Overview ******** @@ -14,11 +10,6 @@ The GD32A503VD features a single-core ARM Cortex-M4F MCU which can run up to 120-MHz with flash accesses zero wait states, 384kiB of Flash, 48kiB of SRAM and 88 GPIOs. -.. image:: img/gd32a503v_eval.jpg - :align: center - :alt: gd32a503v_eval - - Hardware ******** diff --git a/boards/gd/gd32e103v_eval/doc/index.rst b/boards/gd/gd32e103v_eval/doc/index.rst index f53d0b173d3..382bed8c7de 100644 --- a/boards/gd/gd32e103v_eval/doc/index.rst +++ b/boards/gd/gd32e103v_eval/doc/index.rst @@ -1,8 +1,4 @@ -.. _gd32e103v_eval: - -GigaDevice GD32E103V-EVAL -######################### - +.. zephyr:board:: gd32e103v_eval Overview ******** @@ -14,11 +10,6 @@ The GD32E103VB features a single-core ARM Cortex-M4F MCU which can run up to 120-MHz with flash accesses zero wait states, 128kiB of Flash, 32kiB of SRAM and 80 GPIOs. -.. image:: img/gd32e103v_eval.jpg - :align: center - :alt: gd32e103v_eval - - Hardware ******** diff --git a/boards/gd/gd32e507v_start/doc/index.rst b/boards/gd/gd32e507v_start/doc/index.rst index 902b4a20766..a8b8f7a9469 100644 --- a/boards/gd/gd32e507v_start/doc/index.rst +++ b/boards/gd/gd32e507v_start/doc/index.rst @@ -1,7 +1,4 @@ -.. _gd32e507v_start: - -GigaDevice GD32E507V-START -########################## +.. zephyr:board:: gd32e507v_start Overview ******** @@ -13,10 +10,6 @@ The GD32E507VE features a single-core ARM Cortex-M33 MCU which can run up to 180 MHz with flash accesses zero wait states, 512kiB of Flash, 128kiB of SRAM and 80 GPIOs. -.. image:: img/gd32e507v_start.jpg - :align: center - :alt: gd32e507v_start - Hardware ******** diff --git a/boards/gd/gd32e507z_eval/doc/index.rst b/boards/gd/gd32e507z_eval/doc/index.rst index edaac634410..610562b3eae 100644 --- a/boards/gd/gd32e507z_eval/doc/index.rst +++ b/boards/gd/gd32e507z_eval/doc/index.rst @@ -1,7 +1,4 @@ -.. _gd32e507z_eval: - -GigaDevice GD32E507Z-EVAL -######################### +.. zephyr:board:: gd32e507z_eval Overview ******** @@ -13,10 +10,6 @@ The GD32E507ZE features a single-core ARM Cortex-M33 MCU which can run up to 180 MHz with flash accesses zero wait states, 512kiB of Flash, 128kiB of SRAM and 112 GPIOs. -.. image:: img/gd32e507z_eval.webp - :align: center - :alt: gd32e507z_eval - Hardware ******** diff --git a/boards/gd/gd32f350r_eval/doc/index.rst b/boards/gd/gd32f350r_eval/doc/index.rst index d5dc24f46c9..2c7ad726352 100644 --- a/boards/gd/gd32f350r_eval/doc/index.rst +++ b/boards/gd/gd32f350r_eval/doc/index.rst @@ -1,7 +1,4 @@ -.. _gd32f350r_eval: - -GigaDevice GD32F350R-EVAL -######################### +.. zephyr:board:: gd32f350r_eval Overview ******** @@ -13,10 +10,6 @@ The GD32F350RBT6 features a single-core ARM Cortex-M4F MCU which can run up to 108-MHz with flash accesses zero wait states, 128kB of Flash, 16kB of SRAM and 55 GPIOs. -.. image:: img/gd32f350r_eval.webp - :align: center - :alt: gd32f350r_eval - Hardware ******** diff --git a/boards/gd/gd32f403z_eval/doc/index.rst b/boards/gd/gd32f403z_eval/doc/index.rst index c5c97fd727c..d304094a3e7 100644 --- a/boards/gd/gd32f403z_eval/doc/index.rst +++ b/boards/gd/gd32f403z_eval/doc/index.rst @@ -1,8 +1,4 @@ -.. _gd32f403z_eval: - -GigaDevice GD32F403Z-EVAL -######################### - +.. zephyr:board:: gd32f403z_eval Overview ******** @@ -14,11 +10,6 @@ The GD32F403ZE features a single-core ARM Cortex-M4F MCU which can run up to 168-MHz with flash accesses zero wait states, 512kiB of Flash, 96kiB of SRAM and 112 GPIOs. -.. image:: img/gd32f403z_eval.jpg - :align: center - :alt: gd32f403z_eval - - Hardware ******** diff --git a/boards/gd/gd32f407v_start/doc/index.rst b/boards/gd/gd32f407v_start/doc/index.rst index a59243db498..68332eb51b8 100644 --- a/boards/gd/gd32f407v_start/doc/index.rst +++ b/boards/gd/gd32f407v_start/doc/index.rst @@ -1,7 +1,4 @@ -.. _gd32f407v_start: - -GigaDevice GD32F407V-START -########################## +.. zephyr:board:: gd32f407v_start Overview ******** @@ -13,10 +10,6 @@ The GD32F407VE features a single-core ARM Cortex-M4 MCU which can run up to 168 MHz with flash accesses zero wait states, 3072kiB of Flash, 192kiB of SRAM and 82 GPIOs. -.. image:: img/gd32f407v_start.webp - :align: center - :alt: gd32f407v_start - Hardware ******** diff --git a/boards/gd/gd32f450i_eval/doc/index.rst b/boards/gd/gd32f450i_eval/doc/index.rst index e01c3957652..d342cc9774d 100644 --- a/boards/gd/gd32f450i_eval/doc/index.rst +++ b/boards/gd/gd32f450i_eval/doc/index.rst @@ -1,7 +1,4 @@ -.. _gd32f450i_eval: - -GigaDevice GD32F450I-EVAL -######################### +.. zephyr:board:: gd32f450i_eval Overview ******** @@ -13,11 +10,6 @@ The GD32F450IK features a single-core ARM Cortex-M4F MCU which can run up to 200 MHz with flash accesses zero wait states, 3072kiB of Flash, 256kiB of SRAM and 140 GPIOs. -.. image:: img/gd32f450i_eval.webp - :align: center - :alt: gd32f450i_eval - - Hardware ******** diff --git a/boards/gd/gd32f450v_start/doc/index.rst b/boards/gd/gd32f450v_start/doc/index.rst index 0b1a781758b..36870e0c667 100644 --- a/boards/gd/gd32f450v_start/doc/index.rst +++ b/boards/gd/gd32f450v_start/doc/index.rst @@ -1,7 +1,4 @@ -.. _gd32f450v_start: - -GigaDevice GD32F450V-START -########################## +.. zephyr:board:: gd32f450v_start Overview ******** @@ -13,10 +10,6 @@ The GD32F450VK features a single-core ARM Cortex-M4F MCU which can run up to 200 MHz with flash accesses zero wait states, 3072kiB of Flash, 256kiB of SRAM and 82 GPIOs. -.. image:: img/gd32f450v_start.webp - :align: center - :alt: gd32f450v_start - Hardware ******** diff --git a/boards/gd/gd32f450z_eval/doc/index.rst b/boards/gd/gd32f450z_eval/doc/index.rst index cdc4f8f42a7..5a8d8b74763 100644 --- a/boards/gd/gd32f450z_eval/doc/index.rst +++ b/boards/gd/gd32f450z_eval/doc/index.rst @@ -1,7 +1,4 @@ -.. _gd32f450z_eval: - -GigaDevice GD32F450Z-EVAL -######################### +.. zephyr:board:: gd32f450z_eval Overview ******** @@ -13,11 +10,6 @@ The GD32F450ZK features a single-core ARM Cortex-M4F MCU which can run up to 200 MHz with flash accesses zero wait states, 3072kiB of Flash, 256kiB of SRAM and 114 GPIOs. -.. image:: img/gd32f450z_eval.webp - :align: center - :alt: gd32f450z_eval - - Hardware ******** diff --git a/boards/gd/gd32f470i_eval/doc/index.rst b/boards/gd/gd32f470i_eval/doc/index.rst index 75e33eaed2a..1a8865f4d06 100644 --- a/boards/gd/gd32f470i_eval/doc/index.rst +++ b/boards/gd/gd32f470i_eval/doc/index.rst @@ -1,7 +1,4 @@ -.. _gd32f470i_eval: - -GigaDevice GD32F470I-EVAL -######################### +.. zephyr:board:: gd32f470i_eval Overview ******** @@ -13,11 +10,6 @@ The GD32F470IK features a single-core ARM Cortex-M4F MCU which can run up to 240 MHz with flash accesses zero wait states, 3072kiB of Flash, 256kiB of SRAM and 140 GPIOs. -.. image:: img/gd32f470i_eval.jpg - :align: center - :alt: gd32f470i_eval - - Hardware ******** diff --git a/boards/gd/gd32l233r_eval/doc/index.rst b/boards/gd/gd32l233r_eval/doc/index.rst index 884978fd021..d6770856256 100644 --- a/boards/gd/gd32l233r_eval/doc/index.rst +++ b/boards/gd/gd32l233r_eval/doc/index.rst @@ -1,7 +1,4 @@ -.. _gd32l233r_eval: - -GigaDevice GD32L233R-EVA -######################### +.. zephyr:board:: gd32l233r_eval Overview ******** @@ -13,10 +10,6 @@ The GD32RCT6 features a single-core ARM Cortex-M4F MCU which can run up to 64-MHz with flash accesses zero wait states, 256kB of Flash, 32kB of SRAM and 59 GPIOs. -.. image:: img/gd32l233r_eval.jpg - :align: center - :alt: gd32l233r_eval - Hardware ******** diff --git a/boards/gd/gd32vf103c_starter/doc/index.rst b/boards/gd/gd32vf103c_starter/doc/index.rst index 29a428c6c98..40b22fa18c5 100644 --- a/boards/gd/gd32vf103c_starter/doc/index.rst +++ b/boards/gd/gd32vf103c_starter/doc/index.rst @@ -1,7 +1,4 @@ -.. _gd32vf103c_starter: - -GigaDevice GD32VF103C-STARTER -############################# +.. zephyr:board:: gd32vf103c_starter Overview ******** @@ -13,10 +10,6 @@ The GD32VF103CB features a single-core RISC-V 32-bit MCU which can run up to 108 MHz with flash accesses zero wait states, 128 KiB of Flash, 32 KiB of SRAM and 37 GPIOs. -.. image:: img/gd32vf103c_starter.jpg - :align: center - :alt: gd32vf103c_starter - Hardware ******** diff --git a/boards/gd/gd32vf103v_eval/doc/index.rst b/boards/gd/gd32vf103v_eval/doc/index.rst index 5aa8e8327bd..773262c8eab 100644 --- a/boards/gd/gd32vf103v_eval/doc/index.rst +++ b/boards/gd/gd32vf103v_eval/doc/index.rst @@ -1,7 +1,4 @@ -.. _gd32vf103v_eval: - -GigaDevice GD32VF103V-EVAL -########################## +.. zephyr:board:: gd32vf103v_eval Overview ******** @@ -13,10 +10,6 @@ The GD32VF103VB features a single-core RISC-V 32-bit MCU which can run up to 108 MHz with flash accesses zero wait states, 128 KiB of Flash, 32 KiB of SRAM and 80 GPIOs. -.. image:: img/gd32vf103v_eval.jpg - :align: center - :alt: gd32vf103v_eval - Hardware ******** diff --git a/boards/google/dragonclaw/doc/index.rst b/boards/google/dragonclaw/doc/index.rst index ff4fc5253bb..3f717a84341 100644 --- a/boards/google/dragonclaw/doc/index.rst +++ b/boards/google/dragonclaw/doc/index.rst @@ -1,7 +1,4 @@ -.. _google_dragonclaw_board: - -Google Dragonclaw Development Board -################################### +.. zephyr:board:: google_dragonclaw Overview ******** diff --git a/boards/google/icetower/Kconfig.google_icetower b/boards/google/icetower/Kconfig.google_icetower new file mode 100644 index 00000000000..b6f143710cb --- /dev/null +++ b/boards/google/icetower/Kconfig.google_icetower @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Google LLC +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_GOOGLE_ICETOWER + select SOC_STM32H743XX diff --git a/boards/google/icetower/board.cmake b/boards/google/icetower/board.cmake new file mode 100644 index 00000000000..51e47b13107 --- /dev/null +++ b/boards/google/icetower/board.cmake @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: Apache-2.0 + +# keep first +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") +board_runner_args(jlink "--device=STM32H743VI" "--speed=4000") +board_runner_args(openocd --target-handle=_CHIPNAME.cpu0) + +# keep first +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/google/icetower/board.yml b/boards/google/icetower/board.yml new file mode 100644 index 00000000000..beaafd5d4e1 --- /dev/null +++ b/boards/google/icetower/board.yml @@ -0,0 +1,6 @@ +board: + name: google_icetower + full_name: Icetower Development Board + vendor: google + socs: + - name: stm32h743xx diff --git a/boards/google/icetower/doc/index.rst b/boards/google/icetower/doc/index.rst new file mode 100644 index 00000000000..45ecb81be2d --- /dev/null +++ b/boards/google/icetower/doc/index.rst @@ -0,0 +1,47 @@ +.. zephyr:board:: google_icetower + +Overview +******** + +Google Icetower Development Board is a board created by Google for +fingerprint-related functionality development. + +Board has connectors for fingerprint sensors. Console is exposed over `μServo`_ +connector. MCU can be flashed using μServo or SWD. + +Hardware +******** + +- STM32H7A3VIT6 LQFP100 package + +Pin Mapping +=========== + +Default Zephyr Peripheral Mapping: +---------------------------------- +- USART_1 TX/RX : PA9/PA10 +- SPI_1 CS/CLK/MISO/MOSI : PA4/PA5/PA6/PA7 +- SPI_4 CS/CLK/MISO/MOSI : PE11/PE12/PE13/PE14 + +Programming and Debugging +************************* + +Build application as usual for the ``google_icetower`` board, and flash +using μServo or an external J-Link connected to J4. If μServo is used, please +follow the `Chromium EC Flashing Documentation`_. + +Debugging +========= + +Use SWD with a J-Link or ST-Link. Remember that SW2 must be set to CORESIGHT. + +References +********** + +.. target-notes:: + +.. _Chromium EC Flashing Documentation: + https://chromium.googlesource.com/chromiumos/platform/ec#Flashing-via-the-servo-debug-board + +.. _μServo: + https://chromium.googlesource.com/chromiumos/third_party/hdctools/+/master/docs/servo_micro.md diff --git a/boards/google/icetower/google_icetower.dts b/boards/google/icetower/google_icetower.dts new file mode 100644 index 00000000000..fa549c7bbe0 --- /dev/null +++ b/boards/google/icetower/google_icetower.dts @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2024 Google LLC + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include + +/ { + model = "Google Icetower development board"; + compatible = "google,icetower-fpmcu"; + + chosen { + zephyr,console = &usart1; + zephyr,shell-uart = &usart1; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + }; +}; + +&clk_lsi { + /* LSI clock frequency is 32kHz */ + status = "okay"; +}; + +&clk_hsi { + status = "okay"; + hsi-div = <1>; + clock-frequency = ; +}; + +&rcc { + clocks = <&clk_hsi>; + clock-frequency = ; + d1cpre = <1>; + hpre = <1>; + d1ppre = <1>; + d2ppre1 = <1>; + d2ppre2 = <1>; + d3ppre = <1>; +}; + +/* USART1: Servo UART (console) */ +&usart1 { + pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>; + pinctrl-names = "default"; + current-speed = <115200>; + status = "okay"; +}; + +/* SPI1: communication with the AP */ +&spi1 { + pinctrl-0 = <&spi1_nss_pa4 &spi1_sck_pa5 + &spi1_miso_pa6 &spi1_mosi_pa7>; + pinctrl-names = "default"; + status = "okay"; +}; + +/* SPI4: communication with the fingerprint sensor */ +&spi4 { + pinctrl-0 = <&spi4_nss_pe11 &spi4_sck_pe12 + &spi4_miso_pe13 &spi4_mosi_pe14>; + pinctrl-names = "default"; + status = "okay"; +}; + +&rtc { + clocks = <&rcc STM32_CLOCK_BUS_APB4 0x00010000>, + <&rcc STM32_SRC_LSI RTC_SEL(2)>; + status = "okay"; + + backup_regs { + status = "okay"; + }; +}; diff --git a/boards/google/icetower/google_icetower.yaml b/boards/google/icetower/google_icetower.yaml new file mode 100644 index 00000000000..c0b2473c100 --- /dev/null +++ b/boards/google/icetower/google_icetower.yaml @@ -0,0 +1,19 @@ +identifier: google_icetower +name: Google Icetower Development Board +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 1024 +flash: 2048 +vendor: google +supported: + - counter + - dma + - gpio + - i2c + - spi + - pwm + - rtc diff --git a/boards/google/icetower/google_icetower_defconfig b/boards/google/icetower/google_icetower_defconfig new file mode 100644 index 00000000000..705c23fe4b9 --- /dev/null +++ b/boards/google/icetower/google_icetower_defconfig @@ -0,0 +1,17 @@ +# Copyright (c) 2024 Google Inc +# SPDX-License-Identifier: Apache-2.0 + +# Serial Drivers +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +# Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# GPIO Controller +CONFIG_GPIO=y + +# Enable MPU and HW stack protection +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y diff --git a/boards/google/twinkie_v2/doc/index.rst b/boards/google/twinkie_v2/doc/index.rst index 42be6aa2958..3ba2f42e267 100644 --- a/boards/google/twinkie_v2/doc/index.rst +++ b/boards/google/twinkie_v2/doc/index.rst @@ -1,7 +1,4 @@ -.. _google_twinkie_v2_board: - -Google Twinkie V2 -################# +.. zephyr:board:: google_twinkie_v2 Overview ******** diff --git a/boards/google/twinkie_v2/google_twinkie_v2.dts b/boards/google/twinkie_v2/google_twinkie_v2.dts index 7eafd8e3612..eaffe70edf4 100644 --- a/boards/google/twinkie_v2/google_twinkie_v2.dts +++ b/boards/google/twinkie_v2/google_twinkie_v2.dts @@ -65,14 +65,14 @@ csa_vbus: vbusc { compatible = "current-sense-amplifier"; io-channels = <&adc1 17>; - sense-resistor-micro-ohms = <3000>; + sense-resistor-milli-ohms = <3>; sense-gain-mult = <100>; }; csa_cc2: vconc { compatible = "current-sense-amplifier"; io-channels = <&adc1 18>; - sense-resistor-micro-ohms = <10000>; + sense-resistor-milli-ohms = <10>; sense-gain-mult = <25>; }; @@ -101,7 +101,7 @@ &adc1_in18_pc5 /* CSA_CC2 */ >; pinctrl-names = "default"; - st,adc-clock-source = ; + st,adc-clock-source = "SYNC"; st,adc-prescaler = <4>; status = "okay"; diff --git a/boards/hardkernel/odroid_go/Kconfig b/boards/hardkernel/odroid_go/Kconfig new file mode 100644 index 00000000000..6327490e226 --- /dev/null +++ b/boards/hardkernel/odroid_go/Kconfig @@ -0,0 +1,7 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 4096 if BOARD_ODROID_GO_ESP32_PROCPU + default 256 if BOARD_ODROID_GO_ESP32_APPCPU diff --git a/boards/hardkernel/odroid_go/Kconfig.defconfig b/boards/hardkernel/odroid_go/Kconfig.defconfig index 121f6e69397..cbc16ebc788 100644 --- a/boards/hardkernel/odroid_go/Kconfig.defconfig +++ b/boards/hardkernel/odroid_go/Kconfig.defconfig @@ -18,18 +18,4 @@ choice SPIRAM_TYPE default SPIRAM_TYPE_ESPPSRAM32 endchoice -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 65535 if WIFI && BT - default 51200 if WIFI - default 40960 if BT - default 4096 - endif # BOARD_ODROID_GO_ESP32_PROCPU - -if BOARD_ODROID_GO_ESP32_APPCPU - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - default 4096 - -endif # BOARD_ODROID_GO_ESP32_APPCPU diff --git a/boards/hardkernel/odroid_go/doc/index.rst b/boards/hardkernel/odroid_go/doc/index.rst index 62f38d4799d..0963435fa3d 100644 --- a/boards/hardkernel/odroid_go/doc/index.rst +++ b/boards/hardkernel/odroid_go/doc/index.rst @@ -1,7 +1,4 @@ -.. _odroid_go: - -ODROID-GO -######### +.. zephyr:board:: odroid_go Overview ******** @@ -24,12 +21,6 @@ The features include the following: - Expansion port (I2C, GPIO, SPI) - Cryptographic hardware acceleration (RNG, ECC, RSA, SHA-2, AES) -.. figure:: img/odroid_go.jpg - :align: center - :alt: ODROID-GO - - ODROID-Go Game Kit - External Connector ================== diff --git a/boards/hardkernel/odroid_go/odroid_go-flash_partition_table.dtsi b/boards/hardkernel/odroid_go/odroid_go-flash_partition_table.dtsi deleted file mode 100644 index bd0a69298c8..00000000000 --- a/boards/hardkernel/odroid_go/odroid_go-flash_partition_table.dtsi +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright (c) 2024 Yannis Damigos - * - * SPDX-License-Identifier: Apache-2.0 - */ - -&flash0 { - status = "okay"; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Reserve 60kB for the bootloader */ - boot_partition: partition@1000 { - label = "mcuboot"; - reg = <0x00001000 0x0000F000>; - read-only; - }; - - /* Reserve 2048kB for the application in slot 0 */ - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 0x00200000>; - }; - - /* Reserve 2048kB for the application in slot 1 */ - slot1_partition: partition@210000 { - label = "image-1"; - reg = <0x00210000 0x00200000>; - }; - - /* Reserve the remaining 12224kB for the storage partition */ - storage_partition: partition@410000 { - label = "storage"; - reg = <0x00410000 0x00BF0000>; - }; - }; -}; diff --git a/boards/hardkernel/odroid_go/odroid_go_appcpu.dts b/boards/hardkernel/odroid_go/odroid_go_appcpu.dts index 656272a24e8..3fe5151c7ce 100644 --- a/boards/hardkernel/odroid_go/odroid_go_appcpu.dts +++ b/boards/hardkernel/odroid_go/odroid_go_appcpu.dts @@ -6,16 +6,18 @@ /dts-v1/; #include -#include "odroid_go-flash_partition_table.dtsi" +#include / { model = "ODROID-GO Game Kit APPCPU"; compatible = "hardkernel,odroid_go", "espressif,esp32"; chosen { - zephyr,sram = &sram0; + zephyr,sram = &sram1; zephyr,ipc_shm = &shm0; zephyr,ipc = &ipm0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_appcpu_partition; }; }; diff --git a/boards/hardkernel/odroid_go/odroid_go_procpu.dts b/boards/hardkernel/odroid_go/odroid_go_procpu.dts index 108e503cec4..386627ff358 100644 --- a/boards/hardkernel/odroid_go/odroid_go_procpu.dts +++ b/boards/hardkernel/odroid_go/odroid_go_procpu.dts @@ -7,7 +7,7 @@ #include #include "odroid_go-pinctrl.dtsi" -#include "odroid_go-flash_partition_table.dtsi" +#include #include / { @@ -15,7 +15,7 @@ compatible = "hardkernel,odroid_go", "espressif,esp32"; chosen { - zephyr,sram = &sram0; + zephyr,sram = &sram1; zephyr,console = &uart0; zephyr,shell-uart = &uart0; zephyr,flash = &flash0; @@ -144,6 +144,7 @@ status = "okay"; mmc { compatible = "zephyr,sdmmc-disk"; + disk-name = "SD"; status = "okay"; }; spi-max-frequency = <20000000>; diff --git a/boards/hardkernel/odroid_go/odroid_go_procpu.yaml b/boards/hardkernel/odroid_go/odroid_go_procpu.yaml index f2eafb52676..0f9df7d05e5 100644 --- a/boards/hardkernel/odroid_go/odroid_go_procpu.yaml +++ b/boards/hardkernel/odroid_go/odroid_go_procpu.yaml @@ -11,8 +11,4 @@ supported: - watchdog - uart - nvs -testing: - ignore_tags: - - net - - bluetooth vendor: hardkernel diff --git a/boards/heltec/heltec_wifi_lora32_v2/Kconfig b/boards/heltec/heltec_wifi_lora32_v2/Kconfig new file mode 100644 index 00000000000..dccd74430a5 --- /dev/null +++ b/boards/heltec/heltec_wifi_lora32_v2/Kconfig @@ -0,0 +1,7 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 4096 if BOARD_HELTEC_WIFI_LORA32_V2_ESP32_PROCPU + default 256 if BOARD_HELTEC_WIFI_LORA32_V2_ESP32_APPCPU diff --git a/boards/heltec/heltec_wifi_lora32_v2/Kconfig.defconfig b/boards/heltec/heltec_wifi_lora32_v2/Kconfig.defconfig deleted file mode 100644 index a2979499b65..00000000000 --- a/boards/heltec/heltec_wifi_lora32_v2/Kconfig.defconfig +++ /dev/null @@ -1,22 +0,0 @@ -# HELTEC board configuration - -# Copyright (c) 2021 Instituto de Pesquisas Eldorado (eldorado.org.br) -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_HELTEC_WIFI_LORA32_V2_ESP32_PROCPU - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 65535 if WIFI && BT - default 51200 if WIFI - default 40960 if BT - default 4096 - -endif # BOARD_HELTEC_WIFI_LORA32_V2_ESP32_PROCPU - -if BOARD_HELTEC_WIFI_LORA32_V2_ESP32_APPCPU - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - default 256 - -endif # BOARD_HELTEC_WIFI_LORA_V2_ESP32_APPCPU diff --git a/boards/heltec/heltec_wifi_lora32_v2/doc/index.rst b/boards/heltec/heltec_wifi_lora32_v2/doc/index.rst index ee595e0a847..c4987a76b8f 100644 --- a/boards/heltec/heltec_wifi_lora32_v2/doc/index.rst +++ b/boards/heltec/heltec_wifi_lora32_v2/doc/index.rst @@ -1,7 +1,4 @@ -.. _heltec_wifi_lora32_v2: - -Heltec WiFi LoRa 32 (V2) -######################## +.. zephyr:board:: heltec_wifi_lora32_v2 Overview ******** diff --git a/boards/heltec/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_appcpu.dts b/boards/heltec/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_appcpu.dts index 1b9f7dff700..0363d711293 100644 --- a/boards/heltec/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_appcpu.dts +++ b/boards/heltec/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_appcpu.dts @@ -6,15 +6,18 @@ /dts-v1/; #include +#include / { model = "Heltec Wi-Fi Lora32 V2 APPCPU"; compatible = "espressif,esp32"; chosen { - zephyr,sram = &sram0; + zephyr,sram = &sram1; zephyr,ipc_shm = &shm0; zephyr,ipc = &ipm0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_appcpu_partition; }; }; @@ -25,42 +28,3 @@ &trng0 { status = "okay"; }; - -&flash0 { - status = "okay"; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Reserve 60kB for the bootloader */ - boot_partition: partition@1000 { - label = "mcuboot"; - reg = <0x00001000 0x0000F000>; - read-only; - }; - - /* Reserve 1024kB for the application in slot 0 */ - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 0x00100000>; - }; - - /* Reserve 1024kB for the application in slot 1 */ - slot1_partition: partition@110000 { - label = "image-1"; - reg = <0x00110000 0x00100000>; - }; - - /* Reserve 256kB for the scratch partition */ - scratch_partition: partition@210000 { - label = "image-scratch"; - reg = <0x00210000 0x00040000>; - }; - - storage_partition: partition@250000 { - label = "storage"; - reg = <0x00250000 0x00006000>; - }; - }; -}; diff --git a/boards/heltec/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_procpu.dts b/boards/heltec/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_procpu.dts index 4c7cedf82b5..c641e773e07 100644 --- a/boards/heltec/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_procpu.dts +++ b/boards/heltec/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_procpu.dts @@ -8,6 +8,7 @@ #include #include "heltec_wifi_lora32_v2-pinctrl.dtsi" #include +#include / { model = "Heltec Wi-Fi Lora32 V2 PROCPU"; @@ -50,7 +51,7 @@ }; chosen { - zephyr,sram = &sram0; + zephyr,sram = &sram1; zephyr,console = &uart0; zephyr,shell-uart = &uart0; zephyr,flash = &flash0; @@ -59,6 +60,10 @@ }; }; +&flash0 { + reg = <0x0 DT_SIZE_M(4)>; +}; + &uart0 { status = "okay"; current-speed = <115200>; @@ -106,50 +111,6 @@ }; }; -&flash0 { - /* the board is using plain d0wd SoC part without the flash - * so any additional flash size should be defined at the board level - */ - reg = <0x0 DT_SIZE_M(8)>; - - status = "okay"; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Reserve 60kB for the bootloader */ - boot_partition: partition@1000 { - label = "mcuboot"; - reg = <0x00001000 0x0000F000>; - read-only; - }; - - /* Reserve 1024kB for the application in slot 0 */ - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 0x00100000>; - }; - - /* Reserve 1024kB for the application in slot 1 */ - slot1_partition: partition@110000 { - label = "image-1"; - reg = <0x00110000 0x00100000>; - }; - - /* Reserve 256kB for the scratch partition */ - scratch_partition: partition@210000 { - label = "image-scratch"; - reg = <0x00210000 0x00040000>; - }; - - storage_partition: partition@250000 { - label = "storage"; - reg = <0x00250000 0x00006000>; - }; - }; -}; - &esp32_bt_hci { status = "okay"; }; diff --git a/boards/heltec/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_procpu.yaml b/boards/heltec/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_procpu.yaml index d516f1e1c5c..67ff09aa3d5 100644 --- a/boards/heltec/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_procpu.yaml +++ b/boards/heltec/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_procpu.yaml @@ -10,8 +10,4 @@ supported: - watchdog - uart - nvs -testing: - ignore_tags: - - net - - bluetooth vendor: espressif diff --git a/boards/heltec/heltec_wireless_stick_lite_v3/Kconfig b/boards/heltec/heltec_wireless_stick_lite_v3/Kconfig new file mode 100644 index 00000000000..02f8c7bdbd3 --- /dev/null +++ b/boards/heltec/heltec_wireless_stick_lite_v3/Kconfig @@ -0,0 +1,7 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 4096 if BOARD_HELTEC_WIRELESS_STICK_LITE_V3_ESP32S3_PROCPU + default 256 if BOARD_HELTEC_WIRELESS_STICK_LITE_V3_ESP32S3_APPCPU diff --git a/boards/heltec/heltec_wireless_stick_lite_v3/Kconfig.defconfig b/boards/heltec/heltec_wireless_stick_lite_v3/Kconfig.defconfig deleted file mode 100644 index c1aa6f030c7..00000000000 --- a/boards/heltec/heltec_wireless_stick_lite_v3/Kconfig.defconfig +++ /dev/null @@ -1,23 +0,0 @@ -# Heltec Wireless Stick Lite (V3) board configuration - -# Copyright (c) 2021 Instituto de Pesquisas Eldorado (eldorado.org.br) -# Copyright (c) 2023 The Zephyr Project Contributors -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_HELTEC_WIRELESS_STICK_LITE_V3_ESP32S3_PROCPU - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 65535 if WIFI && BT - default 51200 if WIFI - default 40960 if BT - default 4096 - -endif # BOARD_HELTEC_WIRELESS_STICK_LITE_V3_ESP32S3_PROCPU - -if BOARD_HELTEC_WIRELESS_STICK_LITE_V3_ESP32S3_APPCPU - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - default 256 - -endif # BOARD_HELTEC_WIRELESS_STICK_LITE_V3_ESP32S3_APPCPU diff --git a/boards/heltec/heltec_wireless_stick_lite_v3/doc/index.rst b/boards/heltec/heltec_wireless_stick_lite_v3/doc/index.rst index 352d158fbac..4f6430965e5 100644 --- a/boards/heltec/heltec_wireless_stick_lite_v3/doc/index.rst +++ b/boards/heltec/heltec_wireless_stick_lite_v3/doc/index.rst @@ -1,20 +1,10 @@ -.. heltec_wireless_stick_lite_v3: - -HelTec Wireless Stick Lite (V3) -############################### +.. zephyr:board:: heltec_wireless_stick_lite_v3 Overview ******** HelTec Wireless Stick Lite (V3) is a development board with Wi-Fi, Bluetooth and LoRa support. It is designed and produced by HelTec Automation(TM). [1]_ -.. figure:: heltec_wireless_stick_lite_v3.webp - :width: 400px - :align: center - :alt: HelTec Wireless Stick Lite (V3) - - HelTec Wireless Stick Lite (V3) (Credit: Chengdu HelTec Automation Technology Co., Ltd.) - Hardware ******** diff --git a/boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_appcpu.dts b/boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_appcpu.dts index 92bde107bc3..6a8ca48d962 100644 --- a/boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_appcpu.dts +++ b/boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_appcpu.dts @@ -6,60 +6,29 @@ /dts-v1/; #include +#include + / { model = "Heltec Wireless Stick Lite V3 APPCPU"; compatible = "espressif,esp32s3"; chosen { - zephyr,sram = &sram0; + zephyr,sram = &sram1; zephyr,ipc_shm = &shm0; zephyr,ipc = &ipm0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_appcpu_partition; }; }; -&trng0 { - status = "okay"; +&flash0 { + reg = <0x0 DT_SIZE_M(4)>; }; -&ipm0 { +&trng0 { status = "okay"; }; -&flash0 { +&ipm0 { status = "okay"; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Reserve 64kB for the bootloader */ - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x00010000>; - read-only; - }; - - /* Reserve 1024kB for the application in slot 0 */ - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 0x00100000>; - }; - - /* Reserve 1024kB for the application in slot 1 */ - slot1_partition: partition@110000 { - label = "image-1"; - reg = <0x00110000 0x00100000>; - }; - - /* Reserve 256kB for the scratch partition */ - scratch_partition: partition@210000 { - label = "image-scratch"; - reg = <0x00210000 0x00040000>; - }; - - storage_partition: partition@250000 { - label = "storage"; - reg = <0x00250000 0x00006000>; - }; - }; }; diff --git a/boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_procpu.dts b/boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_procpu.dts index d4b2f2b17e8..9e02e3db483 100644 --- a/boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_procpu.dts +++ b/boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_procpu.dts @@ -12,6 +12,7 @@ #include #include #include +#include / { model = "Heltec Wireless Stick Lite V3 PROCPU"; @@ -67,7 +68,7 @@ }; chosen { - zephyr,sram = &sram0; + zephyr,sram = &sram1; zephyr,console = &uart0; zephyr,shell-uart = &uart0; zephyr,flash = &flash0; @@ -76,6 +77,10 @@ }; }; +&flash0 { + reg = <0x0 DT_SIZE_M(4)>; +}; + &adc1 { status ="okay"; }; @@ -168,45 +173,6 @@ pinctrl-names = "default"; }; -&flash0 { - status = "okay"; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Reserve 64kB for the bootloader */ - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x00010000>; - read-only; - }; - - /* Reserve 1024kB for the application in slot 0 */ - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 0x00100000>; - }; - - /* Reserve 1024kB for the application in slot 1 */ - slot1_partition: partition@110000 { - label = "image-1"; - reg = <0x00110000 0x00100000>; - }; - - /* Reserve 256kB for the scratch partition */ - scratch_partition: partition@210000 { - label = "image-scratch"; - reg = <0x00210000 0x00040000>; - }; - - storage_partition: partition@250000 { - label = "storage"; - reg = <0x00250000 0x00006000>; - }; - }; -}; - &esp32_bt_hci { status = "okay"; }; diff --git a/boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_procpu.yaml b/boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_procpu.yaml index 91221f8616b..0ed96e577a1 100644 --- a/boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_procpu.yaml +++ b/boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_procpu.yaml @@ -16,8 +16,4 @@ supported: - pwm - dma - lora -testing: - ignore_tags: - - net - - bluetooth vendor: heltec diff --git a/boards/holyiot/yj16019/Kconfig.defconfig b/boards/holyiot/yj16019/Kconfig.defconfig index c4298c49d6e..4fa098bd482 100644 --- a/boards/holyiot/yj16019/Kconfig.defconfig +++ b/boards/holyiot/yj16019/Kconfig.defconfig @@ -5,7 +5,4 @@ if BOARD_HOLYIOT_YJ16019 -config BT_CTLR - default BT - endif # BOARD_HOLYIOT_YJ16019 diff --git a/boards/holyiot/yj16019/doc/index.rst b/boards/holyiot/yj16019/doc/index.rst index 7ecbf5b0931..86575a0838b 100644 --- a/boards/holyiot/yj16019/doc/index.rst +++ b/boards/holyiot/yj16019/doc/index.rst @@ -1,7 +1,4 @@ -.. _holyiot_yj16019: - -Holyiot YJ-16019 -################ +.. zephyr:board:: holyiot_yj16019 Overview ******** @@ -20,12 +17,6 @@ Semiconductor nRF52832 ARM Cortex-M4 CPU and the following devices: * Segger RTT (RTT Console) * :abbr:`WDT (Watchdog Timer)` -.. figure:: img/holyiot_yj16019_front.jpg - :align: center - :alt: Holyiot YJ-16019 - - Holyiot YJ-16019 (Credit: Holyiot) - The board is equipped with one LED, one push button, and is powered by a CR2032 coin cell. The `Nordic Semiconductor Infocenter`_ contains the processor's information and the datasheet. diff --git a/boards/index.rst b/boards/index.rst index 77814350d9e..0643a355e59 100644 --- a/boards/index.rst +++ b/boards/index.rst @@ -1,24 +1,42 @@ .. _boards: -Supported Boards -################ - -Zephyr project developers are continually adding board-specific support as -documented below. +Supported Boards and Shields +############################ If you are looking to add Zephyr support for a new board, please start with the :ref:`board_porting_guide`. -When adding support documentation for each board, remember to use the template +When adding support documentation for a board, remember to use the template available under :zephyr_file:`doc/templates/board.tmpl`. +Shields are hardware add-ons that can be stacked on top of a board to add extra +functionality. They are listed separately from boards, towards :ref:`the end of +this page `. + +.. admonition:: Search Tips + :class: dropdown + + * Use the form below to filter the list of supported boards. If a field is left empty, it will + not be used in the filtering process. + + * A board must meet **all** criteria selected across different fields. For example, if you select + both a vendor and an architecture, only boards that match both will be displayed. Within a + single field, selecting multiple options (such as two architectures) will show boards matching + **either** option. + + * Can't find your exact board? Don't worry! If a similar board with the same or a closely related + MCU exists, you can use it as a :ref:`starting point ` for adding + support for your own board. .. toctree:: :maxdepth: 2 :glob: + :hidden: */index +.. zephyr:board-catalog:: + .. _boards-shields: Shields diff --git a/boards/infineon/cy8ckit_062s2_ai/Kconfig.cy8ckit_062s2_ai b/boards/infineon/cy8ckit_062s2_ai/Kconfig.cy8ckit_062s2_ai new file mode 100644 index 00000000000..a063f196cec --- /dev/null +++ b/boards/infineon/cy8ckit_062s2_ai/Kconfig.cy8ckit_062s2_ai @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Arrow Electronics. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_CY8CKIT_062S2_AI + select SOC_CY8C624ABZI_S2D44 diff --git a/boards/infineon/cy8ckit_062s2_ai/board.cmake b/boards/infineon/cy8ckit_062s2_ai/board.cmake new file mode 100644 index 00000000000..48e33964ca5 --- /dev/null +++ b/boards/infineon/cy8ckit_062s2_ai/board.cmake @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +# During gdb session, by default connect to CM4 core. +board_runner_args(openocd "--gdb-init=disconnect") +board_runner_args(openocd "--gdb-init=target extended-remote :3334") +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) + +board_runner_args(pyocd "--target=cy8c6xxa") +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/infineon/cy8ckit_062s2_ai/board.yml b/boards/infineon/cy8ckit_062s2_ai/board.yml new file mode 100644 index 00000000000..1bd554cd550 --- /dev/null +++ b/boards/infineon/cy8ckit_062s2_ai/board.yml @@ -0,0 +1,9 @@ +# Copyright (c) 2024 Arrow Electronics. +# SPDX-License-Identifier: Apache-2.0 + +board: + name: cy8ckit_062s2_ai + full_name: PSOC 6 AI Evaluation Kit + vendor: infineon + socs: + - name: cy8c624abzi_s2d44 diff --git a/boards/infineon/cy8ckit_062s2_ai/cy8ckit_062s2_ai.dts b/boards/infineon/cy8ckit_062s2_ai/cy8ckit_062s2_ai.dts new file mode 100644 index 00000000000..c3c5b1ee840 --- /dev/null +++ b/boards/infineon/cy8ckit_062s2_ai/cy8ckit_062s2_ai.dts @@ -0,0 +1,125 @@ +/* + * Copyright (c) 2024 Arrow Electronics. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include + +/ { + model = "CY8CKIT-062S2-AI PSOC 6 AI Evaluation Kit"; + compatible = "infineon,cy8ckit_062s2_ai", "cypress,PSOC6"; + + chosen { + zephyr,console = &uart5; + zephyr,shell-uart = &uart5; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + }; + + aliases { + led0 = &user_led0; + sw0 = &user_bt; + watchdog0 = &watchdog0; + }; + + leds { + compatible = "gpio-leds"; + user_led0: led_0 { + label = "LED_0"; + gpios = <&gpio_prt5 3 GPIO_ACTIVE_HIGH>; + }; + user_led1: led_1 { + label = "LED_1"; + gpios = <&gpio_prt5 4 GPIO_ACTIVE_HIGH>; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + user_bt: button_0 { + label = "SW_0"; + gpios = <&gpio_prt5 2 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + zephyr,code = ; + }; + }; +}; + +&fll0 { + status = "okay"; + clock-frequency = <100000000>; +}; + +&clk_hf0 { + clock-div = <1>; + clocks = <&fll0>; +}; + +/* CM4 core clock = 100MHz + * &fll clock-frequency / &clk_hf0 clock-div / &clk_fast clock-div = 100MHz / 1 / 1 = 100MHz + */ +&clk_fast { + clock-div = <1>; +}; + +/* CM0+ core clock = 50MHz + * &fll clock-frequency / &clk_hf0 clock-div / &clk_slow clock-div = 100MHz / 1 / 2 = 50MHz + */ +&clk_slow { + clock-div = <2>; +}; + +/* PERI core clock = 100MHz + * &fll clock-frequency / &clk_hf0 clock-div / &clk_peri clock-div = 100MHz / 1 / 1 = 100MHz + */ +&clk_peri { + clock-div = <1>; +}; + +&gpio_prt5 { + status = "okay"; +}; + +&gpio_prt10 { + status = "okay"; +}; + +/* UART connected to KitProg3 */ +uart5: &scb5 { + compatible = "infineon,cat1-uart"; + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&p5_1_scb5_uart_tx &p5_0_scb5_uart_rx>; + pinctrl-names = "default"; +}; + +uart1: &scb1 { + compatible = "infineon,cat1-uart"; + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&p10_0_scb1_uart_rx &p10_1_scb1_uart_tx>; + pinctrl-names = "default"; +}; + +&p5_1_scb5_uart_tx { + drive-push-pull; +}; + +&p5_0_scb5_uart_rx { + input-enable; +}; + +&p10_1_scb1_uart_tx { + drive-push-pull; +}; + +&p10_0_scb1_uart_rx { + input-enable; +}; + +&watchdog0 { + status = "okay"; +}; diff --git a/boards/infineon/cy8ckit_062s2_ai/cy8ckit_062s2_ai.yaml b/boards/infineon/cy8ckit_062s2_ai/cy8ckit_062s2_ai.yaml new file mode 100644 index 00000000000..eef9a3a2388 --- /dev/null +++ b/boards/infineon/cy8ckit_062s2_ai/cy8ckit_062s2_ai.yaml @@ -0,0 +1,13 @@ +identifier: cy8ckit_062s2_ai +name: CY8CKIT-062S2-AI PSOC 6 AI Evaluation Kit +type: mcu +arch: arm +ram: 1024 +flash: 2048 +toolchain: + - zephyr +supported: + - gpio + - uart + - watchdog +vendor: infineon diff --git a/boards/infineon/cy8ckit_062s2_ai/cy8ckit_062s2_ai_defconfig b/boards/infineon/cy8ckit_062s2_ai/cy8ckit_062s2_ai_defconfig new file mode 100644 index 00000000000..105fb484e28 --- /dev/null +++ b/boards/infineon/cy8ckit_062s2_ai/cy8ckit_062s2_ai_defconfig @@ -0,0 +1,24 @@ +# Copyright (c) 2024 Arrow Electronics. +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable HW stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable GPIO driver +CONFIG_GPIO=y + +# Enable clock controller +CONFIG_CLOCK_CONTROL=y + +# Add catcm0p sleep images for CM0 Devices +CONFIG_SOC_PSOC6_CM0P_IMAGE_SLEEP=y diff --git a/boards/infineon/cy8ckit_062s2_ai/doc/img/cy8ckit_062s2_ai.webp b/boards/infineon/cy8ckit_062s2_ai/doc/img/cy8ckit_062s2_ai.webp new file mode 100644 index 00000000000..56075d2e884 Binary files /dev/null and b/boards/infineon/cy8ckit_062s2_ai/doc/img/cy8ckit_062s2_ai.webp differ diff --git a/boards/infineon/cy8ckit_062s2_ai/doc/index.rst b/boards/infineon/cy8ckit_062s2_ai/doc/index.rst new file mode 100644 index 00000000000..8395bcd98ce --- /dev/null +++ b/boards/infineon/cy8ckit_062s2_ai/doc/index.rst @@ -0,0 +1,182 @@ +.. zephyr:board:: cy8ckit_062s2_ai + +Overview +******** + +The PSOC 6 AI Evaluation Kit (CY8CKIT-062S2-AI) is a cost effective and small development kit that +enables design and debug of PSOC 6 MCUs. +It includes a CY8C624ABZI-S2D44 MCU which is based on a 150-MHz Arm |reg| Cortex |reg|-M4 and +a 100-MHz Arm |reg| Cortex |reg|-M0+, with 2048 KB of on-chip Flash, 1024 KB of SRAM, +a Quad-SPI external memory interface, built-in hardware and software security features, +rich analog, digital, and communication peripherals. + +The board features an AIROC |reg| CYW43439 Wi-Fi & Bluetooth |reg| combo device, +a 512 MB NOR flash, an onboard programmer/debugger (KitProg3), USB host and device features, +two user LEDs, and one push button. + +Hardware +******** + +For more information about the CY8C624ABZI-S2D44 MCU SoC and CY8CKIT-062S2-AI board: + +- `CY8C624ABZI-S2D44 MCU SoC Website`_ +- `CY8C624ABZI-S2D44 MCU Datasheet`_ +- `CY8CKIT-062S2-AI Website`_ +- `CY8CKIT-062S2-AI User Guide`_ +- `CY8CKIT-062S2-AI Schematics`_ + +Supported Features +================== + +The ``cy8ckit_062s2_ai/cy8c624abzi_s2d44`` board target supports the following hardware features: + ++-----------+------------+-----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=======================+ +| NVIC | on-chip | nested vectored | +| | | interrupt controller | ++-----------+------------+-----------------------+ +| SYSTICK | on-chip | system clock | ++-----------+------------+-----------------------+ +| GPIO | on-chip | GPIO | ++-----------+------------+-----------------------+ +| PINCTRL | on-chip | pin control | ++-----------+------------+-----------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-----------------------+ +| WATCHDOG | on-chip | watchdog | ++-----------+------------+-----------------------+ + + +The default configuration can be found in the defconfig and dts files: + + - :zephyr_file:`boards/infineon/cy8ckit_062s2_ai/cy8ckit_062s2_ai_defconfig` + - :zephyr_file:`boards/infineon/cy8ckit_062s2_ai/cy8ckit_062s2_ai.dts` + +System Clock +============ + +The PCY8C624ABZI-S2D44 MCU SoC is configured to use the internal IMO+FLL as a source for +the system clock. CM0+ works at 50MHz, CM4 - at 100MHz. Other sources for the +system clock are provided in the SoC, depending on your system requirements. + + +Fetch Binary Blobs +****************** + +The CY8CKIT-062S2-AI board requires fetch binary files (e.g CM0+ prebuilt images). + +To fetch Binary Blobs: + +.. code-block:: console + + west blobs fetch hal_infineon + + +Build blinking led sample +************************* + +Here is an example for building the :zephyr:code-sample:`blinky` sample application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: cy8ckit_062s2_ai/cy8c624abzi_s2d44 + :goals: build + +Programming and Debugging +************************* + +The CY8CKIT-062S2-AI board includes an onboard programmer/debugger (`KitProg3`_) +to provide debugging, flash programming, and serial communication over USB. +Flash and debug commands use OpenOCD and require a custom Infineon OpenOCD version, +that supports KitProg3, to be installed. + + +Infineon OpenOCD Installation +============================= + +Both the full `ModusToolbox`_ and the `ModusToolbox Programming Tools`_ packages include Infineon OpenOCD. +Installing either of these packages will also install Infineon OpenOCD. +If neither package is installed, a minimal installation can be done by downloading the `Infineon OpenOCD`_ release +for your system and manually extract the files to a location of your choice. + +.. note:: + + Linux requires device access rights to be set up for KitProg3. + This is handled automatically by the ModusToolbox and ModusToolbox Programming Tools installations. + When doing a minimal installation, this can be done manually by executing the script + ``openocd/udev_rules/install_rules.sh``. + +West Commands +============= + +The path to the installed Infineon OpenOCD executable must be available to the ``west`` tool commands. +There are multiple ways of doing this. +The example below uses a permanent CMake argument to set the CMake variable ``OPENOCD``. + + .. tabs:: + .. group-tab:: Windows + + .. code-block:: shell + + # Run west config once to set permanent CMake argument + west config build.cmake-args -- -DOPENOCD=path/to/infineon/openocd/bin/openocd.exe + + # Do a pristine build once after setting CMake argument + west build -b cy8ckit_062s2_ai/cy8c624abzi_s2d44 -p always samples/basic/blinky + + west flash + west debug + + .. group-tab:: Linux + + .. code-block:: shell + + # Run west config once to set permanent CMake argument + west config build.cmake-args -- -DOPENOCD=path/to/infineon/openocd/bin/openocd + + # Do a pristine build once after setting CMake argument + west build -b cy8ckit_062s2_ai/cy8c624abzi_s2d44 -p always samples/basic/blinky + + west flash + west debug + +Alternatively, pyOCD can also be used to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner pyocd + +References +********** + +.. target-notes:: + +.. _CY8C624ABZI-S2D44 MCU SoC Website: + https://www.infineon.com/cms/en/product/microcontroller/32-bit-psoc-arm-cortex-microcontroller/psoc-6-32-bit-arm-cortex-m4-mcu/psoc-62/psoc-62x8-62xa/cy8c624abzi-s2d44/ + +.. _CY8C624ABZI-S2D44 MCU Datasheet: + https://www.infineon.com/dgdl/Infineon-PSOC_6_MCU_CY8C62X8_CY8C62XA-DataSheet-v16_00-EN.pdf?fileId=8ac78c8c7d0d8da4017d0ee7d03a70b1 + +.. _CY8CKIT-062S2-AI Website: + https://www.infineon.com/cms/en/product/evaluation-boards/cy8ckit-062s2-ai/?redirId=273839 + +.. _CY8CKIT-062S2-AI User Guide: + https://www.infineon.com/dgdl/Infineon-CY8CKIT_062S2_AI_KIT_GUIDE-UserManual-v01_00-EN.pdf?fileId=8ac78c8c90530b3a01906d4608842668 + +.. _CY8CKIT-062S2-AI Schematics: + https://www.infineon.com/dgdl/Infineon-CY8CKIT-062S2-AI_PSoC_6_AI_Evaluation_Board_Schematic-PCBDesignData-v01_00-EN.pdf?fileId=8ac78c8c8eeb092c018f0af9e109106f + +.. _ModusToolbox: + https://softwaretools.infineon.com/tools/com.ifx.tb.tool.modustoolbox + +.. _ModusToolbox Programming Tools: + https://softwaretools.infineon.com/tools/com.ifx.tb.tool.modustoolboxprogtools + +.. _Infineon OpenOCD: + https://github.com/Infineon/openocd/releases/latest + +.. _KitProg3: + https://github.com/Infineon/KitProg3 diff --git a/boards/infineon/cy8ckit_062s2_ai/support/openocd.cfg b/boards/infineon/cy8ckit_062s2_ai/support/openocd.cfg new file mode 100644 index 00000000000..5b123bd203f --- /dev/null +++ b/boards/infineon/cy8ckit_062s2_ai/support/openocd.cfg @@ -0,0 +1,12 @@ +if {[info exists env(OPENOCD_INTERFACE)]} { + set INTERFACE $env(OPENOCD_INTERFACE) +} else { + # By default connect over Debug USB port + set INTERFACE "cmsis-dap" +} + +source [find interface/$INTERFACE.cfg] + +transport select swd + +source [find target/psoc6_2m.cfg] diff --git a/boards/infineon/cy8ckit_062s4/cy8ckit_062s4.dts b/boards/infineon/cy8ckit_062s4/cy8ckit_062s4.dts index 9328a0cf60d..4ba5a5b9fda 100644 --- a/boards/infineon/cy8ckit_062s4/cy8ckit_062s4.dts +++ b/boards/infineon/cy8ckit_062s4/cy8ckit_062s4.dts @@ -7,7 +7,7 @@ #include / { - model = "Infineon PSoC 62S4 Pioneer Kit"; + model = "Infineon PSOC 62S4 Pioneer Kit"; compatible ="cypress,psoc6"; chosen { zephyr,sram = &sram0; diff --git a/boards/infineon/cy8ckit_062s4/cy8ckit_062s4.yaml b/boards/infineon/cy8ckit_062s4/cy8ckit_062s4.yaml index 4ab5c7580ec..0965da54b3a 100644 --- a/boards/infineon/cy8ckit_062s4/cy8ckit_062s4.yaml +++ b/boards/infineon/cy8ckit_062s4/cy8ckit_062s4.yaml @@ -2,7 +2,7 @@ # Copyright (c) 2023 David Ullmann identifier: cy8ckit_062s4 -name: CY8CKIT-062S4 PSoC 62S4 +name: CY8CKIT-062S4 PSOC 62S4 type: mcu arch: arm ram: 128 diff --git a/boards/infineon/cy8ckit_062s4/cy8ckit_062s4_defconfig b/boards/infineon/cy8ckit_062s4/cy8ckit_062s4_defconfig index 04b8a04dda6..d0909391c45 100644 --- a/boards/infineon/cy8ckit_062s4/cy8ckit_062s4_defconfig +++ b/boards/infineon/cy8ckit_062s4/cy8ckit_062s4_defconfig @@ -5,8 +5,6 @@ CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y -CONFIG_PINCTRL=y - CONFIG_BUILD_OUTPUT_HEX=y CONFIG_CORTEX_M_SYSTICK=y CONFIG_XIP=y diff --git a/boards/infineon/cy8ckit_062s4/doc/index.rst b/boards/infineon/cy8ckit_062s4/doc/index.rst index 1dfdb93bd30..b5e3e39cc1d 100644 --- a/boards/infineon/cy8ckit_062s4/doc/index.rst +++ b/boards/infineon/cy8ckit_062s4/doc/index.rst @@ -1,11 +1,8 @@ -.. _cy8ckit_062s4: - -[INFINEON PSoC 62S4 Pioneer Kit] -################################ +.. zephyr:board:: cy8ckit_062s4 Overview ******** -The PSOC 62S4 Pioneer kit has a CY8C62x4 MCU, which is an ultra-low-power PSoC device specifically designed for battery-operated analog +The PSOC 62S4 Pioneer kit has a CY8C62x4 MCU, which is an ultra-low-power PSOC device specifically designed for battery-operated analog sensing applications. It includes a 150-MHz Arm® Cortex®-M4 CPU as the primary application processor, a 100-MHz Arm® Cortex®-M0+ CPU that supports low-power operations, up to 256 KB Flash and 128 KB SRAM, programmable analog sensing, CapSense™ touch-sensing, and programmable digital peripherals. @@ -15,21 +12,14 @@ programmer/debugger (KitProg3), a 512-Mbit Quad SPI NOR flash, a micro-B connect interface, a thermistor, an ambient light sensor, a 5-segment CapSense™ slider, two CapSense™ buttons, two user LEDs, and a push button. The board supports operating voltages from 1.8 V to 3.3 V for PSoC™ 6 MCU. -.. figure::img/cy8ckit_062s4.png - :width: 800px - :align: center - :alt: Board Name - - Board Name (Credit: ) - Hardware ******** -`CY8CKIT 062S4 Pioneer Kit Website`_ -`CY8CKIT 062S4 Pioneer Kit Guide`_ -`CY8CKIT 062S4 Pioneer Kit Schematic`_ -`CY8CKIT 062S4 Pioneer Kit Technical Reference Manual`_ -`CY8CKIT 062S4 Pioneer Kit Datasheet`_ +* `CY8CKIT 062S4 Pioneer Kit Website`_ +* `CY8CKIT 062S4 Pioneer Kit Guide`_ +* `CY8CKIT 062S4 Pioneer Kit Schematic`_ +* `CY8CKIT 062S4 Pioneer Kit Technical Reference Manual`_ +* `CY8CKIT 062S4 Pioneer Kit Datasheet`_ Supported Features ================== @@ -49,8 +39,10 @@ The board configuration supports the following hardware features: | UART | on-chip | serial port-polling; | +-----------+------------+-----------------------+ + The default configuration can be found in the Kconfig -:zephyr_file:`boards/infineon/cy8ckit_062s4/cy8ckit_062s4_defconfig`. + +:zephyr_file:`boards/infineon/cy8ckit_062s4/cy8ckit_062s4_defconfig` Clock Configuration =================== @@ -66,50 +58,96 @@ Clock Configuration +-----------+------------+-----------------------+ Fetch Binary Blobs -================== +****************** .. code-block:: console west blobs fetch hal_infineon +Build blinking led sample +************************* -Build and flash hello world sample -********************************** +Here is an example for building the :zephyr:code-sample:`blinky` sample application. +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: cy8ckit_062s4 + :goals: build -.. code-block:: console +Programming and Debugging +************************* + +The CY8CKIT-062S4 includes an onboard programmer/debugger (`KitProg3`_) to provide debugging, flash programming, and serial communication over USB. Flash and debug commands use OpenOCD and require a custom Infineon OpenOCD version, that supports KitProg3, to be installed. + +Infineon OpenOCD Installation +============================= + +Both the full `ModusToolbox`_ and the `ModusToolbox Programming Tools`_ packages include Infineon OpenOCD. Installing either of these packages will also install Infineon OpenOCD. If neither package is installed, a minimal installation can be done by downloading the `Infineon OpenOCD`_ release for your system and manually extract the files to a location of your choice. + +.. note:: Linux requires device access rights to be set up for KitProg3. This is handled automatically by the ModusToolbox and ModusToolbox Programming Tools installations. When doing a minimal installation, this can be done manually by executing the script ``openocd/udev_rules/install_rules.sh``. + +West Commands +============= + +The path to the installed Infineon OpenOCD executable must be available to the ``west`` tool commands. There are multiple ways of doing this. The example below uses a permanent CMake argument to set the CMake variable ``OPENOCD``. - cd zephyr/samples/hello_world - west build -p auto -b cy8ckit_062s4 --pristine - west flash - picocom /dev/ttyACM0 -b 115200 + .. tabs:: + .. group-tab:: Windows -OpenOCD Installation -==================== + .. code-block:: shell -To get the OpenOCD package, it is required that you + # Run west config once to set permanent CMake argument + west config build.cmake-args -- -DOPENOCD=path/to/infineon/openocd/bin/openocd.exe -1. Download the software ModusToolbox 3.1. https://softwaretools.infineon.com/tools/com.ifx.tb.tool.modustoolbox -2. Once downloaded add the path to access the Scripts folder provided by ModusToolbox - export PATH=$PATH:/path/to/ModusToolbox/tools_3.1/openocd/scripts -3. Add the OpenOCD executable file's path to west flash/debug. -4. Flash using: west flash --openocd path/to/infineon/openocd/bin/openocd -5. Debug using: west debug --openocd path/to/infineon/openocd/bin/openocd + # Do a pristine build once after setting CMake argument + west build -b cy8ckit_062s4 -p always samples/basic/blinky + + west flash + west debug + + .. group-tab:: Linux + + .. code-block:: shell + + # Run west config once to set permanent CMake argument + west config build.cmake-args -- -DOPENOCD=path/to/infineon/openocd/bin/openocd + + # Do a pristine build once after setting CMake argument + west build -b cy8ckit_062s4 -p always samples/basic/blinky + + west flash + west debug + +Once the gdb console starts after executing the west debug command, you may now set breakpoints and perform other standard GDB debugging on the PSOC 6 CM4 core. References ********** +.. target-notes:: + .. _CY8CKIT 062S4 Pioneer Kit Guide: - https://www.infineon.com/dgdl/Infineon-CY8CKIT_062S4_PSoC62S4_pioneer_kit_guide-UserManual-v01_00-EN.pdf?fileId=8ac78c8c7e7124d1017e962f98992207 + https://www.infineon.com/dgdl/Infineon-CY8CKIT_062S4_PSOC62S4_pioneer_kit_guide-UserManual-v01_00-EN.pdf?fileId=8ac78c8c7e7124d1017e962f98992207 .. _CY8CKIT 062S4 Pioneer Kit Website: https://www.infineon.com/cms/en/product/evaluation-boards/cy8ckit-062s4/?redirId=VL1508&utm_medium=referral&utm_source=cypress&utm_campaign=202110_globe_en_all_integration-dev_kit .. _CY8CKIT 062S4 Pioneer Kit Schematic: - https://www.infineon.com/dgdl/Infineon-CY8CKIT-062S4_PSoC_62S4_Pioneer_Kit_Schematic-PCBDesignData-v01_00-EN.pdf?fileId=8ac78c8c7d710014017d7153484d2081 + https://www.infineon.com/dgdl/Infineon-CY8CKIT-062S4_PSOC_62S4_Pioneer_Kit_Schematic-PCBDesignData-v01_00-EN.pdf?fileId=8ac78c8c7d710014017d7153484d2081 .. _CY8CKIT 062S4 Pioneer Kit Technical Reference Manual: https://www.infineon.com/dgdl/Infineon-PSOC_6_MCU_CY8C61X4CY8C62X4_REGISTERS_TECHNICAL_REFERENCE_MANUAL_(TRM)_PSOC_61_PSOC_62_MCU-AdditionalTechnicalInformation-v03_00-EN.pdf?fileId=8ac78c8c7d0d8da4017d0fb34f0627a7 .. _CY8CKIT 062S4 Pioneer Kit Datasheet: - https://www.infineon.com/dgdl/Infineon-PSoC_6_MCU_CY8C62X4-DataSheet-v12_00-EN.pdf?fileId=8ac78c8c7ddc01d7017ddd026d585901 + https://www.infineon.com/dgdl/Infineon-PSOC_6_MCU_CY8C62X4-DataSheet-v12_00-EN.pdf?fileId=8ac78c8c7ddc01d7017ddd026d585901 + +.. _ModusToolbox: + https://softwaretools.infineon.com/tools/com.ifx.tb.tool.modustoolbox + +.. _ModusToolbox Programming Tools: + https://softwaretools.infineon.com/tools/com.ifx.tb.tool.modustoolboxprogtools + +.. _Infineon OpenOCD: + https://github.com/Infineon/openocd/releases/latest + +.. _KitProg3: + https://github.com/Infineon/KitProg3 diff --git a/boards/infineon/cy8cproto_062_4343w/Kconfig.cy8cproto_062_4343w b/boards/infineon/cy8cproto_062_4343w/Kconfig.cy8cproto_062_4343w index 6af485a6bed..63d5185839b 100644 --- a/boards/infineon/cy8cproto_062_4343w/Kconfig.cy8cproto_062_4343w +++ b/boards/infineon/cy8cproto_062_4343w/Kconfig.cy8cproto_062_4343w @@ -1,4 +1,4 @@ -# CY8CPROTO-062-4343W PSoC™ 6 Wi-Fi BT Prototyping Kit +# CY8CPROTO-062-4343W PSOC™ 6 Wi-Fi BT Prototyping Kit # Copyright (c) 2021 Cypress Semiconductor Corporation. # SPDX-License-Identifier: Apache-2.0 diff --git a/boards/infineon/cy8cproto_062_4343w/Kconfig.defconfig b/boards/infineon/cy8cproto_062_4343w/Kconfig.defconfig index 5573b7f0417..d26e3293d2e 100644 --- a/boards/infineon/cy8cproto_062_4343w/Kconfig.defconfig +++ b/boards/infineon/cy8cproto_062_4343w/Kconfig.defconfig @@ -1,4 +1,4 @@ -# CY8CPROTO-062-4343W PSoC™ 6 Wi-Fi BT Prototyping Kit configuration +# CY8CPROTO-062-4343W PSOC™ 6 Wi-Fi BT Prototyping Kit configuration # Copyright (c) 2021 Cypress Semiconductor Corporation. # SPDX-License-Identifier: Apache-2.0 diff --git a/boards/infineon/cy8cproto_062_4343w/cy8cproto_062_4343w.dts b/boards/infineon/cy8cproto_062_4343w/cy8cproto_062_4343w.dts index b9e74ac685d..38980638022 100644 --- a/boards/infineon/cy8cproto_062_4343w/cy8cproto_062_4343w.dts +++ b/boards/infineon/cy8cproto_062_4343w/cy8cproto_062_4343w.dts @@ -10,8 +10,8 @@ #include "cy8cproto_062_4343w-pinctrl.dtsi" / { - model = "cy8cproto_062_4343w with an Cypress PSoC™ 6 SoC"; - compatible = "cypress,cy8cproto_062_4343w", "cypress,PSoC6"; + model = "cy8cproto_062_4343w with an Cypress PSOC™ 6 SoC"; + compatible = "cypress,cy8cproto_062_4343w", "cypress,PSOC6"; aliases { uart-5 = &uart5; diff --git a/boards/infineon/cy8cproto_062_4343w/cy8cproto_062_4343w.yaml b/boards/infineon/cy8cproto_062_4343w/cy8cproto_062_4343w.yaml index 113c686db03..5eb55d4de6d 100644 --- a/boards/infineon/cy8cproto_062_4343w/cy8cproto_062_4343w.yaml +++ b/boards/infineon/cy8cproto_062_4343w/cy8cproto_062_4343w.yaml @@ -4,7 +4,7 @@ # identifier: cy8cproto_062_4343w -name: CY8CPROTO-062-4343W PSoC 6 Wi-Fi BT Prototyping Kit +name: CY8CPROTO-062-4343W PSOC 6 Wi-Fi BT Prototyping Kit type: mcu arch: arm ram: 1024 diff --git a/boards/infineon/cy8cproto_062_4343w/cy8cproto_062_4343w_defconfig b/boards/infineon/cy8cproto_062_4343w/cy8cproto_062_4343w_defconfig index 19975610f60..221643eca27 100644 --- a/boards/infineon/cy8cproto_062_4343w/cy8cproto_062_4343w_defconfig +++ b/boards/infineon/cy8cproto_062_4343w/cy8cproto_062_4343w_defconfig @@ -17,9 +17,6 @@ CONFIG_UART_CONSOLE=y # Enable UART driver CONFIG_SERIAL=y -# Enable pin controller -CONFIG_PINCTRL=y - # Enable GPIO driver CONFIG_GPIO=y diff --git a/boards/infineon/cy8cproto_062_4343w/doc/index.rst b/boards/infineon/cy8cproto_062_4343w/doc/index.rst index a5934089f0b..f04c28e5d00 100644 --- a/boards/infineon/cy8cproto_062_4343w/doc/index.rst +++ b/boards/infineon/cy8cproto_062_4343w/doc/index.rst @@ -1,13 +1,10 @@ -.. _cy8cproto_062_4343w: - -INFINEON CY8CPROTO-062-4343W -############################ +.. zephyr:board:: cy8cproto_062_4343w Overview ******** -The CY8CPROTO-062-4343W PSoC 6 Wi-Fi BT Prototyping Kit is a low-cost hardware -platform that enables design and debug of PSoC 6 MCUs. It comes with a Murata +The CY8CPROTO-062-4343W PSOC 6 Wi-Fi BT Prototyping Kit is a low-cost hardware +platform that enables design and debug of PSOC 6 MCUs. It comes with a Murata LBEE5KL1DX module, based on the CYW4343W combo device, industry-leading CAPSENSE for touch buttons and slider, on-board debugger/programmer with KitProg3, microSD card interface, 512-Mb Quad-SPI NOR flash, PDM-PCM microphone, and a thermistor. @@ -16,22 +13,18 @@ This kit is designed with a snap-away form-factor, allowing the user to separate the different components and features that come with this kit and use independently. In addition, support for Digilent's Pmod interface is also provided with this kit. -.. image:: img/board.jpg - :align: center - :alt: CY8CPROTO-062-4343W - Hardware ******** -For more information about the PSoC 62 MCU SoC and CY8CPROTO-062-4343W board: +For more information about the PSOC 62 MCU SoC and CY8CPROTO-062-4343W board: -- `PSoC 62 MCU SoC Website`_ -- `PSoC 62 MCU Datasheet`_ -- `PSoC 62 MCU Architecture Reference Manual`_ -- `PSoC 62 MCU Register Reference Manual`_ -- `CY8CPROTO-062-4343W PSoC 6 Wi-Fi BT Website`_ -- `CY8CPROTO-062-4343W PSoC 6 Wi-Fi BT User Guide`_ -- `CY8CPROTO-062-4343W PSoC 6 Wi-Fi BT Schematics`_ +- `PSOC 62 MCU SoC Website`_ +- `PSOC 62 MCU Datasheet`_ +- `PSOC 62 MCU Architecture Reference Manual`_ +- `PSOC 62 MCU Register Reference Manual`_ +- `CY8CPROTO-062-4343W PSOC 6 Wi-Fi BT Website`_ +- `CY8CPROTO-062-4343W PSOC 6 Wi-Fi BT User Guide`_ +- `CY8CPROTO-062-4343W PSOC 6 Wi-Fi BT Schematics`_ Kit Features: ============= @@ -48,9 +41,10 @@ Kit Features: Kit Contents: ============= -- PSoC 6 Wi-Fi BT Prototyping Board +- PSOC 6 Wi-Fi BT Prototyping Board - USB Type-A to Micro-B cable -- Quick Start Guide +- Quick start guide + Supported Features ================== @@ -80,7 +74,7 @@ The default configuration can be found in the Kconfig System Clock ============ -The PSoC 62 MCU SoC is configured to use the internal IMO+FLL as a source for +The PSOC 62 MCU SoC is configured to use the internal IMO+FLL as a source for the system clock. CM0+ works at 50MHz, CM4 - at 100MHz. Other sources for the system clock are provided in the SOC, depending on your system requirements. @@ -101,50 +95,58 @@ To fetch Binary Blobs: Build blinking led sample ************************* -Here is an example for the :zephyr:code-sample:`blinky` application. +Here is an example for building the :zephyr:code-sample:`blinky` sample application. -.. code-block:: console +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: cy8cproto_062_4343w + :goals: build - cd zephyr - west build -p auto -b cy8cproto_062_4343w samples/basic/blink +Programming and Debugging +************************* -OpenOCD Installation -==================== +The CY8CPROTO-062-4343W includes an onboard programmer/debugger (`KitProg3`_) to provide debugging, flash programming, and serial communication over USB. Flash and debug commands use OpenOCD and require a custom Infineon OpenOCD version, that supports KitProg3, to be installed. -To get the OpenOCD package, it is required that you +Infineon OpenOCD Installation +============================= -1. Download the software ModusToolbox 3.1. https://softwaretools.infineon.com/tools/com.ifx.tb.tool.modustoolbox -2. Once downloaded add the path to access the Scripts folder provided by ModusToolbox - export PATH=$PATH:/path/to/ModusToolbox/tools_3.1/openocd/scripts -3. Add the OpenOCD executable file's path to west flash/debug. -4. Flash using: west flash --openocd path/to/infineon/openocd/bin/openocd -5. Debug using: west debug --openocd path/to/infineon/openocd/bin/openocd +Both the full `ModusToolbox`_ and the `ModusToolbox Programming Tools`_ packages include Infineon OpenOCD. Installing either of these packages will also install Infineon OpenOCD. If neither package is installed, a minimal installation can be done by downloading the `Infineon OpenOCD`_ release for your system and manually extract the files to a location of your choice. +.. note:: Linux requires device access rights to be set up for KitProg3. This is handled automatically by the ModusToolbox and ModusToolbox Programming Tools installations. When doing a minimal installation, this can be done manually by executing the script ``openocd/udev_rules/install_rules.sh``. -Programming and Debugging -************************* +West Commands +============= -The CY8CPROTO-062-4343W includes an onboard programmer/debugger (KitProg2) with -mass storage programming to provide debugging, flash programming, and serial -communication over USB. Flash and debug commands must be pointed to the Cypress -OpenOCD you downloaded above. +The path to the installed Infineon OpenOCD executable must be available to the ``west`` tool commands. There are multiple ways of doing this. The example below uses a permanent CMake argument to set the CMake variable ``OPENOCD``. -On Windows: + .. tabs:: + .. group-tab:: Windows -.. code-block:: console + .. code-block:: shell - west flash --openocd path/to/infineon/openocd/bin/openocd.exe - west debug --openocd path/to/infineon/openocd/bin/openocd.exe + # Run west config once to set permanent CMake argument + west config build.cmake-args -- -DOPENOCD=path/to/infineon/openocd/bin/openocd.exe -On Linux: + # Do a pristine build once after setting CMake argument + west build -b cy8cproto_062_4343w -p always samples/basic/blinky -.. code-block:: console + west flash + west debug + + .. group-tab:: Linux + + .. code-block:: shell + + # Run west config once to set permanent CMake argument + west config build.cmake-args -- -DOPENOCD=path/to/infineon/openocd/bin/openocd - west flash --openocd path/to/infineon/openocd/bin/openocd - west debug --openocd path/to/infineon/openocd/bin/openocd + # Do a pristine build once after setting CMake argument + west build -b cy8cproto_062_4343w -p always samples/basic/blinky -Once the gdb console starts after executing the west debug command, you may -now set breakpoints and perform other standard GDB debugging on the PSoC 6 CM4 core. + west flash + west debug + +Once the gdb console starts after executing the west debug command, you may now set breakpoints and perform other standard GDB debugging on the PSOC 6 CM4 core. Errata ====== @@ -159,26 +161,35 @@ Errata | a server instance started by west debugserver. | | +------------------------------------------------+----------------------------------------+ -.. _PSoC 62 MCU SoC Website: +.. _PSOC 62 MCU SoC Website: https://www.cypress.com/products/32-bit-arm-cortex-m4-psoc-6 -.. _PSoC 62 MCU Datasheet: +.. _PSOC 62 MCU Datasheet: https://www.cypress.com/documentation/datasheets/psoc-6-mcu-psoc-62-datasheet-programmable-system-chip-psoc-preliminary -.. _PSoC 62 MCU Architecture Reference Manual: +.. _PSOC 62 MCU Architecture Reference Manual: https://www.cypress.com/documentation/technical-reference-manuals/psoc-6-mcu-psoc-62-architecture-technical-reference-manual -.. _PSoC 62 MCU Register Reference Manual: +.. _PSOC 62 MCU Register Reference Manual: https://www.cypress.com/documentation/technical-reference-manuals/psoc-6-mcu-psoc-62-register-technical-reference-manual-trm -.. _CY8CPROTO-062-4343W PSoC 6 Wi-Fi BT Website: +.. _CY8CPROTO-062-4343W PSOC 6 Wi-Fi BT Website: https://www.infineon.com/cms/en/product/evaluation-boards/cy8cproto-062-4343w/ -.. _CY8CPROTO-062-4343W PSoC 6 Wi-Fi BT User Guide: +.. _CY8CPROTO-062-4343W PSOC 6 Wi-Fi BT User Guide: https://www.infineon.com/cms/en/product/evaluation-boards/cy8cproto-062-4343w/#!?fileId=8ac78c8c7d0d8da4017d0f0118571844 -.. _CY8CPROTO-062-4343W PSoC 6 Wi-Fi BT Schematics: +.. _CY8CPROTO-062-4343W PSOC 6 Wi-Fi BT Schematics: https://www.infineon.com/cms/en/product/evaluation-boards/cy8cproto-062-4343w/#!?fileId=8ac78c8c7d0d8da4017d0f01126b183f +.. _ModusToolbox: + https://softwaretools.infineon.com/tools/com.ifx.tb.tool.modustoolbox + +.. _ModusToolbox Programming Tools: + https://softwaretools.infineon.com/tools/com.ifx.tb.tool.modustoolboxprogtools + .. _Infineon OpenOCD: - https://github.com/infineon/openocd/releases/tag/release-v4.3.0 + https://github.com/Infineon/openocd/releases/latest + +.. _KitProg3: + https://github.com/Infineon/KitProg3 diff --git a/boards/infineon/cy8cproto_063_ble/Kconfig.cy8cproto_063_ble b/boards/infineon/cy8cproto_063_ble/Kconfig.cy8cproto_063_ble index 23763f500c3..bc269a7fcfe 100644 --- a/boards/infineon/cy8cproto_063_ble/Kconfig.cy8cproto_063_ble +++ b/boards/infineon/cy8cproto_063_ble/Kconfig.cy8cproto_063_ble @@ -1,4 +1,4 @@ -# CY8CPROTO-063-BLE PSoC™ 6 BLE Prototyping Kit +# CY8CPROTO-063-BLE PSOC™ 6 BLE Prototyping Kit # # Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon company) or # an affiliate of Cypress Semiconductor Corporation diff --git a/boards/infineon/cy8cproto_063_ble/Kconfig.defconfig b/boards/infineon/cy8cproto_063_ble/Kconfig.defconfig index 4123455e9f9..0c805b26b80 100644 --- a/boards/infineon/cy8cproto_063_ble/Kconfig.defconfig +++ b/boards/infineon/cy8cproto_063_ble/Kconfig.defconfig @@ -1,4 +1,4 @@ -# CY8CPROTO-063-BLE PSoC™ 6 BLE Prototyping Kit +# CY8CPROTO-063-BLE PSOC™ 6 BLE Prototyping Kit # Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon company) or # an affiliate of Cypress Semiconductor Corporation diff --git a/boards/infineon/cy8cproto_063_ble/cy8cproto_063_ble.dts b/boards/infineon/cy8cproto_063_ble/cy8cproto_063_ble.dts index 5516895fddd..3cb9253a806 100644 --- a/boards/infineon/cy8cproto_063_ble/cy8cproto_063_ble.dts +++ b/boards/infineon/cy8cproto_063_ble/cy8cproto_063_ble.dts @@ -12,8 +12,8 @@ #include / { - model = "CY8CPROTO-063-BLE PSoC™ 6 BLE Prototyping Kit"; - compatible = "cypress,cy8cproto_063_ble", "cypress,PSoC6"; + model = "CY8CPROTO-063-BLE PSOC™ 6 BLE Prototyping Kit"; + compatible = "cypress,cy8cproto_063_ble", "cypress,PSOC6"; aliases { uart-5 = &uart5; diff --git a/boards/infineon/cy8cproto_063_ble/cy8cproto_063_ble.yaml b/boards/infineon/cy8cproto_063_ble/cy8cproto_063_ble.yaml index db4f1ec95b0..9fdb92c305e 100644 --- a/boards/infineon/cy8cproto_063_ble/cy8cproto_063_ble.yaml +++ b/boards/infineon/cy8cproto_063_ble/cy8cproto_063_ble.yaml @@ -4,7 +4,7 @@ # identifier: cy8cproto_063_ble -name: CY8CPROTO-063-BLE PSoC™ 6 BLE Prototyping Kit +name: CY8CPROTO-063-BLE PSOC™ 6 BLE Prototyping Kit type: mcu arch: arm ram: 288 diff --git a/boards/infineon/cy8cproto_063_ble/cy8cproto_063_ble_defconfig b/boards/infineon/cy8cproto_063_ble/cy8cproto_063_ble_defconfig index 17d512d195d..7d0d29ea39c 100644 --- a/boards/infineon/cy8cproto_063_ble/cy8cproto_063_ble_defconfig +++ b/boards/infineon/cy8cproto_063_ble/cy8cproto_063_ble_defconfig @@ -18,9 +18,6 @@ CONFIG_UART_CONSOLE=y # Enable UART driver CONFIG_SERIAL=y -# Enable pin controller -CONFIG_PINCTRL=y - # Enable GPIO CONFIG_GPIO=y diff --git a/boards/infineon/cy8cproto_063_ble/doc/index.rst b/boards/infineon/cy8cproto_063_ble/doc/index.rst index 86cc9cd5c15..90623b80382 100644 --- a/boards/infineon/cy8cproto_063_ble/doc/index.rst +++ b/boards/infineon/cy8cproto_063_ble/doc/index.rst @@ -1,27 +1,20 @@ -.. _cy8cproto_063_ble: - -INFINEON CY8CPROTO-063-BLE -########################### +.. zephyr:board:: cy8cproto_063_ble Overview ******** -The PSoC 6 BLE Proto Kit (CY8CPROTO-063-BLE) is a hardware platform that -enables design and debug of the Cypress PSoC 63 BLE MCU. - -.. image:: img/cy8cproto-063-ble.jpg - :align: center - :alt: CY8CPROTO-063-BLE +The PSOC 6 BLE Proto Kit (CY8CPROTO-063-BLE) is a hardware platform that +enables design and debug of the Cypress PSOC 63 BLE MCU. Hardware ******** -For more information about the PSoC 63 BLE MCU SoC and CY8CPROTO-063-BLE board: +For more information about the PSOC 63 BLE MCU SoC and CY8CPROTO-063-BLE board: -- `PSoC 63 BLE MCU SoC Website`_ -- `PSoC 63 BLE MCU Datasheet`_ -- `PSoC 63 BLE MCU Architecture Reference Manual`_ -- `PSoC 63 BLE MCU Register Reference Manual`_ +- `PSOC 63 BLE MCU SoC Website`_ +- `PSOC 63 BLE MCU Datasheet`_ +- `PSOC 63 BLE MCU Architecture Reference Manual`_ +- `PSOC 63 BLE MCU Register Reference Manual`_ - `CY8CPROTO-063-BLE Website`_ - `CY8CPROTO-063-BLE User Guide`_ - `CY8CPROTO-063-BLE Schematics`_ @@ -39,11 +32,11 @@ The board configuration supports the following hardware features: +-----------+------------+-----------------------+ | SYSTICK | on-chip | system clock | +-----------+------------+-----------------------+ -| GPIO | on-chip | gpio | +| GPIO | on-chip | GPIO | +-----------+------------+-----------------------+ | PINCTRL | on-chip | pin control | +-----------+------------+-----------------------+ -| SPI | on-chip | spi | +| SPI | on-chip | SPI | +-----------+------------+-----------------------+ | UART | on-chip | serial port-polling; | | | | serial port-interrupt | @@ -58,30 +51,18 @@ The board configuration supports the following hardware features: +-----------+------------+-----------------------+ -The default configurations can be found in +The default configuration can be found in the Kconfig + :zephyr_file:`boards/infineon/cy8cproto_063_ble/cy8cproto_063_ble_defconfig` System Clock ============ -The PSoC 63 BLE MCU SoC is configured to use the internal IMO+FLL as a source for +The PSOC 63 BLE MCU SoC is configured to use the internal IMO+FLL as a source for the system clock. CM0+ works at 50MHz, CM4 - at 100MHz. Other sources for the system clock are provided in the SOC, depending on your system requirements. -OpenOCD Installation -==================== - -To get the OpenOCD package, it is required that you - -1. Download the software ModusToolbox 3.1. https://softwaretools.infineon.com/tools/com.ifx.tb.tool.modustoolbox -2. Once downloaded add the path to access the Scripts folder provided by ModusToolbox - export PATH=$PATH:/path/to/ModusToolbox/tools_3.1/openocd/scripts -3. Add the OpenOCD executable file's path to west flash/debug. -4. Flash using: west flash --openocd path/to/infineon/openocd/bin/openocd -5. Debug using: west debug --openocd path/to/infineon/openocd/bin/openocd - - Fetch Binary Blobs ****************** @@ -94,41 +75,77 @@ To fetch Binary Blobs: west blobs fetch hal_infineon + +Build blinking led sample +************************* + +Here is an example for building the :zephyr:code-sample:`blinky` sample application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: cy8cproto_063_ble + :goals: build + Programming and Debugging ************************* -The CY8CPROTO-063-BLE includes an onboard programmer/debugger (KitProg3) with -mass storage programming to provide debugging, flash programming, and serial -communication over USB. Flash and debug commands must be pointed to the Cypress -OpenOCD you downloaded above. +The CY8CPROTO-063-BLE includes an onboard programmer/debugger (`KitProg3`_) to provide debugging, flash programming, and serial communication over USB. Flash and debug commands use OpenOCD and require a custom Infineon OpenOCD version, that supports KitProg3, to be installed. -On Windows: +Infineon OpenOCD Installation +============================= -.. code-block:: console +Both the full `ModusToolbox`_ and the `ModusToolbox Programming Tools`_ packages include Infineon OpenOCD. Installing either of these packages will also install Infineon OpenOCD. If neither package is installed, a minimal installation can be done by downloading the `Infineon OpenOCD`_ release for your system and manually extract the files to a location of your choice. - west flash --openocd path/to/infineon/openocd/bin/openocd.exe - west debug --openocd path/to/infineon/openocd/bin/openocd.exe +.. note:: Linux requires device access rights to be set up for KitProg3. This is handled automatically by the ModusToolbox and ModusToolbox Programming Tools installations. When doing a minimal installation, this can be done manually by executing the script ``openocd/udev_rules/install_rules.sh``. -On Linux: +West Commands +============= -.. code-block:: console +The path to the installed Infineon OpenOCD executable must be available to the ``west`` tool commands. There are multiple ways of doing this. The example below uses a permanent CMake argument to set the CMake variable ``OPENOCD``. + + .. tabs:: + .. group-tab:: Windows + + .. code-block:: shell + + # Run west config once to set permanent CMake argument + west config build.cmake-args -- -DOPENOCD=path/to/infineon/openocd/bin/openocd.exe + + # Do a pristine build once after setting CMake argument + west build -b cy8cproto_063_ble -p always samples/basic/blinky + + west flash + west debug + + .. group-tab:: Linux + + .. code-block:: shell + + # Run west config once to set permanent CMake argument + west config build.cmake-args -- -DOPENOCD=path/to/infineon/openocd/bin/openocd + + # Do a pristine build once after setting CMake argument + west build -b cy8cproto_063_ble -p always samples/basic/blinky + + west flash + west debug - west flash --openocd path/to/infineon/openocd/bin/openocd - west debug --openocd path/to/infineon/openocd/bin/openocd References ********** -.. _PSoC 63 BLE MCU SoC Website: +.. target-notes:: + +.. _PSOC 63 BLE MCU SoC Website: https://www.cypress.com/products/32-bit-arm-cortex-m4-psoc-6 -.. _PSoC 63 BLE MCU Datasheet: - https://www.infineon.com/dgdl/Infineon-PSoC_6_MCU_PSoC_63_with_BLE_Datasheet_Programmable_System-on-Chip_(PSoC)-DataSheet-v16_00-EN.pdf?fileId=8ac78c8c7d0d8da4017d0ee4efe46c37&utm_source=cypress&utm_medium=referral&utm_campaign=202110_globe_en_all_integration-files +.. _PSOC 63 BLE MCU Datasheet: + https://www.infineon.com/dgdl/Infineon-PSOC_6_MCU_PSOC_63_with_BLE_Datasheet_Programmable_System-on-Chip_(PSOC)-DataSheet-v16_00-EN.pdf?fileId=8ac78c8c7d0d8da4017d0ee4efe46c37&utm_source=cypress&utm_medium=referral&utm_campaign=202110_globe_en_all_integration-files -.. _PSoC 63 BLE MCU Architecture Reference Manual: +.. _PSOC 63 BLE MCU Architecture Reference Manual: https://documentation.infineon.com/html/psoc6/zrs1651212645947.html -.. _PSoC 63 BLE MCU Register Reference Manual: +.. _PSOC 63 BLE MCU Register Reference Manual: https://documentation.infineon.com/html/psoc6/bnm1651211483724.html .. _CY8CPROTO-063-BLE Website: @@ -140,5 +157,14 @@ References .. _CY8CPROTO-063-BLE Schematics: https://www.infineon.com/cms/en/product/evaluation-boards/cy8cproto-063-ble/#!?fileId=8ac78c8c7d0d8da4017d0f00ea3c1821 +.. _ModusToolbox: + https://softwaretools.infineon.com/tools/com.ifx.tb.tool.modustoolbox + +.. _ModusToolbox Programming Tools: + https://softwaretools.infineon.com/tools/com.ifx.tb.tool.modustoolboxprogtools + .. _Infineon OpenOCD: - https://github.com/infineon/openocd/releases/tag/release-v4.3.0 + https://github.com/Infineon/openocd/releases/latest + +.. _KitProg3: + https://github.com/Infineon/KitProg3 diff --git a/boards/infineon/cyw920829m2evk_02/board.cmake b/boards/infineon/cyw920829m2evk_02/board.cmake index 9fa085b7448..be95fa715a3 100644 --- a/boards/infineon/cyw920829m2evk_02/board.cmake +++ b/boards/infineon/cyw920829m2evk_02/board.cmake @@ -1,4 +1,7 @@ # Copyright (c) 2024 Cypress Semiconductor Corporation. # SPDX-License-Identifier: Apache-2.0 +board_runner_args(openocd "--target-handle=TARGET.cm33") include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +board_runner_args(jlink "--device=CYW20829_tm") +include (${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02.dts b/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02.dts index 83825dd8693..927b1f865f4 100644 --- a/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02.dts +++ b/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02.dts @@ -81,6 +81,10 @@ uart2: &scb2 { status = "okay"; }; +&mcwdt0 { + status = "okay"; +}; + &bluetooth { status = "okay"; }; diff --git a/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02.yaml b/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02.yaml index a02da7d1937..9d83de725c0 100644 --- a/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02.yaml +++ b/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02.yaml @@ -20,5 +20,8 @@ supported: - watchdog - spi - i2c + - rtc + - dma + - pwm vendor: infineon diff --git a/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02_defconfig b/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02_defconfig index fea80ce0119..e50b5462bab 100644 --- a/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02_defconfig +++ b/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02_defconfig @@ -4,7 +4,6 @@ # # General configuration -CONFIG_CORTEX_M_SYSTICK=y CONFIG_BUILD_OUTPUT_HEX=y CONFIG_BUILD_OUTPUT_BIN=y @@ -18,9 +17,6 @@ CONFIG_UART_CONSOLE=y # Enable UART driver CONFIG_SERIAL=y -# Enable pin controller -CONFIG_PINCTRL=y - # Enable GPIO driver CONFIG_GPIO=y diff --git a/boards/infineon/cyw920829m2evk_02/doc/index.rst b/boards/infineon/cyw920829m2evk_02/doc/index.rst index cac878c01a5..d4c5193c382 100644 --- a/boards/infineon/cyw920829m2evk_02/doc/index.rst +++ b/boards/infineon/cyw920829m2evk_02/doc/index.rst @@ -1,7 +1,4 @@ -.. _cyw920829m2evk_02: - -INFINEON CYW920829M2EVK-02 -############################ +.. zephyr:board:: cyw920829m2evk_02 Overview ******** @@ -10,10 +7,6 @@ The AIROC™ CYW20829 Bluetooth® LE MCU Evaluation Kit (CYW920829M2EVK-02) with The system features Dual Arm® Cortex® - M33s for powering the MCU and Bluetooth subsystem with programmable and reconfigurable analog and digital blocks. In addition, on the kit, there is a suite of on-board peripherals including six-axis inertial measurement unit (IMU), thermistor, analog mic, user programmable buttons (2), LEDs (2), and RGB LED. There is also extensive GPIO support with extended headers and Arduino Uno R3 compatibility for third-party shields. -.. image:: img/cyw920829m2evk_02.webp - :align: center - :alt: CYW920829M2EVK_02 - Hardware ******** @@ -97,6 +90,11 @@ Programming and Debugging The CYW920829M2EVK-02 includes an onboard programmer/debugger (`KitProg3`_) to provide debugging, flash programming, and serial communication over USB. Flash and debug commands use OpenOCD and require a custom Infineon OpenOCD version, that supports KitProg3, to be installed. +The CYW920829M2EVK-02 supports RTT via a SEGGER JLink device, under the target name cyw20829_tm. This can be enabled for an application by building with the rtt-console snippet or setting the following config values: CONFIG_UART_CONSOLE=n, CONFIG_RTT_CONSOLE=y, and CONFIG_USE_SEGGER_RTT=y. +e.g. west build -p always -b cyw920829m2evk_02 samples/basic/blinky -S rtt-console + +As an additional note there is currently a discrepancy in RAM address between SEGGER and the CYW920829M2EVK-02 device. So, for RTT control block, do not use "Auto Detection". Instead, set the search range to something reflecting: RAM RangeStart at 0x20000000 and RAM RangeSize of 0x3d000. + Infineon OpenOCD Installation ============================= diff --git a/boards/infineon/xmc45_relax_kit/doc/index.rst b/boards/infineon/xmc45_relax_kit/doc/index.rst index 621fc1cc83e..bfad619aedc 100644 --- a/boards/infineon/xmc45_relax_kit/doc/index.rst +++ b/boards/infineon/xmc45_relax_kit/doc/index.rst @@ -1,7 +1,4 @@ -.. _xmc45_relax_kit: - -INFINEON XMC45-RELAX-KIT -######################## +.. zephyr:board:: xmc45_relax_kit Overview ******** @@ -10,10 +7,6 @@ The XMC4500 Relax Kit is designed to evaluate the capabilities of the XMC4500 Microcontroller. It is based on High performance ARM Cortex-M4F which can run up to 120MHz. -.. image:: xmc45_relax_kit.jpg - :align: center - :alt: XMC45-RELAX-KIT - Features: ========= @@ -67,35 +60,56 @@ The Relax Kit development board configuration supports the following hardware fe +-----------+------------+-----------------------+ More details about the supported peripherals are available in `XMC4500 TRM`_ -Other hardware features are not currently supported by the Zephyr kernel. -Building and Flashing -********************* -Flashing -======== +The default configuration can be found in the Kconfig -Here is an example for the :zephyr:code-sample:`hello_world` application. +:zephyr_file:`boards/infineon/xmc45_relax_kit/xmc45_relax_kit_defconfig` + +Other hardware features are not currently supported by the Zephyr kernel. + +Build hello world sample +************************ +Here is an example for building the :zephyr:code-sample:`hello_world` sample application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world :board: xmc45_relax_kit - :goals: flash - -Debugging -========= + :goals: build +Programming and Debugging +************************* +West Commands +============= Here is an example for the :zephyr:code-sample:`hello_world` application. -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: xmc45_relax_kit - :goals: debug + .. tabs:: + .. group-tab:: Windows + + .. code-block:: shell + + # Do a pristine build + west build -b xmc45_relax_kit -p always samples/hello_world + + west flash + west debug -Step through the application in your debugger. + .. group-tab:: Linux + + .. code-block:: shell + + # Do a pristine build + west build -b xmc45_relax_kit -p always samples/hello_world + + west flash + west debug + +Once the gdb console starts after executing the west debug command, you may now set breakpoints and perform other standard GDB debugging. References ********** +.. target-notes:: + .. _Relax Kit User Manual: https://www.infineon.com/dgdl/Board_Users_Manual_XMC4500_Relax_Kit-V1_R1.2_released.pdf?fileId=db3a30433acf32c9013adf6b97b112f9 diff --git a/boards/infineon/xmc47_relax_kit/doc/index.rst b/boards/infineon/xmc47_relax_kit/doc/index.rst index 57eb28efaed..d5796afd7ea 100644 --- a/boards/infineon/xmc47_relax_kit/doc/index.rst +++ b/boards/infineon/xmc47_relax_kit/doc/index.rst @@ -1,7 +1,4 @@ -.. _xmc47_relax_kit: - -INFINEON XMC47-RELAX-KIT -######################## +.. zephyr:board:: xmc47_relax_kit Overview ******** @@ -10,10 +7,6 @@ The XMC4700 Relax Kit is designed to evaluate the capabilities of the XMC4700 Microcontroller. It is based on High performance ARM Cortex-M4F which can run up to 144MHz. -.. image:: xmc47_relax_kit.jpg - :align: center - :alt: XMC47-RELAX-KIT - Features: ========= @@ -72,33 +65,53 @@ The Relax Kit development board configuration supports the following hardware fe More details about the supported peripherals are available in `XMC4700 TRM`_ Other hardware features are not currently supported by the Zephyr kernel. -Building and Flashing -********************* -Flashing -======== +The default configuration can be found in the Kconfig -Here is an example for the :zephyr:code-sample:`hello_world` application. +:zephyr_file:`boards/infineon/xmc47_relax_kit/xmc47_relax_kit_defconfig` + +Build hello world sample +************************ +Here is an example for building the :zephyr:code-sample:`hello_world` sample application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world :board: xmc47_relax_kit - :goals: flash - -Debugging -========= + :goals: build +Programming and Debugging +************************* +West Commands +============= Here is an example for the :zephyr:code-sample:`hello_world` application. -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: xmc47_relax_kit - :goals: debug + .. tabs:: + .. group-tab:: Windows -Step through the application in your debugger. + .. code-block:: shell + + # Do a pristine build + west build -b xmc47_relax_kit -p always samples/hello_world + + west flash + west debug + + .. group-tab:: Linux + + .. code-block:: shell + + # Do a pristine build + west build -b xmc47_relax_kit -p always samples/hello_world + + west flash + west debug + +Once the gdb console starts after executing the west debug command, you may now set breakpoints and perform other standard GDB debugging. References ********** +.. target-notes:: + .. _Relax Kit User Manual: https://www.infineon.com/dgdl/Infineon-Board_User_Manual_XMC4700_XMC4800_Relax_Kit_Series-UserManual-v01_04-EN.pdf?fileId=5546d46250cc1fdf01513f8e052d07fc diff --git a/boards/innblue/innblue21/doc/index.rst b/boards/innblue/innblue21/doc/index.rst index 0990c395c62..bafb7d9911a 100644 --- a/boards/innblue/innblue21/doc/index.rst +++ b/boards/innblue/innblue21/doc/index.rst @@ -1,7 +1,4 @@ -.. _nrf9160_innblue21: - -nRF9160 INNBLUE21 -################# +.. zephyr:board:: innblue21 Overview ******** @@ -9,12 +6,6 @@ Overview The nRF9160 innblue21 is a cellular IoT sensor development board, which is based on the nRF9160 SiP, and features NB-IoT and LTE-M connectivity. -.. figure:: img/nrf9160_innblue21.jpg - :align: center - :alt: nRF9160 innblue21 - - nRF9160 innblue21 (Credit: innblue) - Hardware ******** diff --git a/boards/innblue/innblue22/doc/index.rst b/boards/innblue/innblue22/doc/index.rst index 3485ad4de77..9e84c4691df 100644 --- a/boards/innblue/innblue22/doc/index.rst +++ b/boards/innblue/innblue22/doc/index.rst @@ -1,7 +1,4 @@ -.. _nrf9160_innblue22: - -nRF9160 INNBLUE22 -################# +.. zephyr:board:: innblue22 Overview ******** @@ -9,12 +6,6 @@ Overview The nRF9160 innblue22 is a cellular IoT sensor development board, which is based on the nRF9160 SiP, and features NB-IoT and LTE-M connectivity. -.. figure:: img/nrf9160_innblue22.jpg - :align: center - :alt: nRF9160 innblue22 - - nRF9160 innblue22 (Credit: innblue) - Hardware ******** diff --git a/boards/intel/adl/intel_adl.dts b/boards/intel/adl/intel_adl.dts index 16dfb20a556..10b37802aeb 100644 --- a/boards/intel/adl/intel_adl.dts +++ b/boards/intel/adl/intel_adl.dts @@ -22,3 +22,7 @@ sdhc0 = &emmc; }; }; + +&cpu { + compatible = "intel,x86_64"; +}; diff --git a/boards/intel/adl/intel_adl_crb_defconfig b/boards/intel/adl/intel_adl_crb_defconfig index fb9be2a4994..7fad00df636 100644 --- a/boards/intel/adl/intel_adl_crb_defconfig +++ b/boards/intel/adl/intel_adl_crb_defconfig @@ -9,4 +9,3 @@ CONFIG_UART_CONSOLE=y CONFIG_X2APIC=y CONFIG_SMP=y CONFIG_BUILD_OUTPUT_EFI=y -CONFIG_BUILD_NO_GAP_FILL=y diff --git a/boards/intel/adl/intel_adl_rvp_defconfig b/boards/intel/adl/intel_adl_rvp_defconfig index fb9be2a4994..7fad00df636 100644 --- a/boards/intel/adl/intel_adl_rvp_defconfig +++ b/boards/intel/adl/intel_adl_rvp_defconfig @@ -9,4 +9,3 @@ CONFIG_UART_CONSOLE=y CONFIG_X2APIC=y CONFIG_SMP=y CONFIG_BUILD_OUTPUT_EFI=y -CONFIG_BUILD_NO_GAP_FILL=y diff --git a/boards/intel/adsp/intel_adsp_ace15_mtpm.yaml b/boards/intel/adsp/intel_adsp_ace15_mtpm.yaml deleted file mode 100644 index 3449cda35f7..00000000000 --- a/boards/intel/adsp/intel_adsp_ace15_mtpm.yaml +++ /dev/null @@ -1,15 +0,0 @@ -identifier: intel_adsp/ace15_mtpm -name: ACE 1.5 MTL M Audio DSP -type: mcu -arch: xtensa -toolchain: - - zephyr - - xcc - - xt-clang -supported: - - dma -testing: - ignore_tags: - - net - - bluetooth -vendor: intel diff --git a/boards/intel/adsp/intel_adsp_ace15_mtpm_sim.yaml b/boards/intel/adsp/intel_adsp_ace15_mtpm_sim.yaml deleted file mode 100644 index 418849ec8a4..00000000000 --- a/boards/intel/adsp/intel_adsp_ace15_mtpm_sim.yaml +++ /dev/null @@ -1,14 +0,0 @@ -identifier: intel_adsp/ace15_mtpm/sim -name: ACE 1.5 Meteor Lake M Audio DSP -type: sim -simulation: custom -arch: xtensa -toolchain: - - xcc - - zephyr - - xt-clang -testing: - timeout_multiplier: 4 - ignore_tags: - - net - - bluetooth diff --git a/boards/intel/adsp/intel_adsp_ace20_lnl.yaml b/boards/intel/adsp/intel_adsp_ace20_lnl.yaml deleted file mode 100644 index 47a02563654..00000000000 --- a/boards/intel/adsp/intel_adsp_ace20_lnl.yaml +++ /dev/null @@ -1,16 +0,0 @@ -identifier: intel_adsp/ace20_lnl -name: ACE 2.0 LNL Audio DSP -type: mcu -arch: xtensa -toolchain: - - xcc - - xt-clang - - zephyr -supported: - - dma -testing: - ignore_tags: - - net - - bluetooth - - mcumgr -vendor: intel diff --git a/boards/intel/adsp/intel_adsp_ace20_lnl_sim.yaml b/boards/intel/adsp/intel_adsp_ace20_lnl_sim.yaml deleted file mode 100644 index cde563043da..00000000000 --- a/boards/intel/adsp/intel_adsp_ace20_lnl_sim.yaml +++ /dev/null @@ -1,13 +0,0 @@ -identifier: intel_adsp/ace20_lnl/sim -name: ACE 2.0 Lunar Lake Audio DSP -type: sim -simulation: custom -arch: xtensa -toolchain: - - xcc - - xt-clang -testing: - timeout_multiplier: 6 - ignore_tags: - - net - - bluetooth diff --git a/boards/intel/adsp/intel_adsp_ace30_ptl.yaml b/boards/intel/adsp/intel_adsp_ace30_ptl.yaml deleted file mode 100644 index 061ac9cd742..00000000000 --- a/boards/intel/adsp/intel_adsp_ace30_ptl.yaml +++ /dev/null @@ -1,10 +0,0 @@ -identifier: intel_adsp/ace30/ptl -name: ACE 3.0 Panther Lake Audio DSP -type: mcu -arch: xtensa -toolchain: - - xt-clang -testing: - ignore_tags: - - net - - bluetooth diff --git a/boards/intel/adsp/intel_adsp_ace30_ptl_sim.yaml b/boards/intel/adsp/intel_adsp_ace30_ptl_sim.yaml deleted file mode 100644 index 42b07e49ee3..00000000000 --- a/boards/intel/adsp/intel_adsp_ace30_ptl_sim.yaml +++ /dev/null @@ -1,12 +0,0 @@ -identifier: intel_adsp/ace30/ptl/sim -name: ACE 3.0 Panther Lake Audio DSP -type: sim -simulation: custom -arch: xtensa -toolchain: - - xt-clang -testing: - timeout_multiplier: 8 - ignore_tags: - - net - - bluetooth diff --git a/boards/intel/adsp/intel_adsp_cavs25.yaml b/boards/intel/adsp/intel_adsp_cavs25.yaml deleted file mode 100644 index 79982b426e7..00000000000 --- a/boards/intel/adsp/intel_adsp_cavs25.yaml +++ /dev/null @@ -1,15 +0,0 @@ -identifier: intel_adsp/cavs25 -name: cAVS 2.5 Audio DSP (converged Audio Voice and Speech) -type: mcu -arch: xtensa -toolchain: - - xcc - - zephyr -supported: - - dma - - dai -testing: - ignore_tags: - - net - - bluetooth -vendor: intel diff --git a/boards/intel/adsp/intel_adsp_cavs25_tgph.yaml b/boards/intel/adsp/intel_adsp_cavs25_tgph.yaml deleted file mode 100644 index db3d32fad8f..00000000000 --- a/boards/intel/adsp/intel_adsp_cavs25_tgph.yaml +++ /dev/null @@ -1,14 +0,0 @@ -identifier: intel_adsp/cavs25/tgph -name: cAVS 2.5 Audio DSP for Tiger Lake H PCH (Converged Audio Voice and Speech) -type: mcu -arch: xtensa -toolchain: - - xcc - - zephyr -supported: - - dma -testing: - ignore_tags: - - net - - bluetooth -vendor: intel diff --git a/boards/intel/adsp/twister.yaml b/boards/intel/adsp/twister.yaml new file mode 100644 index 00000000000..866f8ff7a90 --- /dev/null +++ b/boards/intel/adsp/twister.yaml @@ -0,0 +1,58 @@ +type: mcu +arch: xtensa +toolchain: + - zephyr + - xcc + - xt-clang +supported: + - dma +testing: + ignore_tags: + - net + - bluetooth + - mcumgr +variants: + intel_adsp/ace30/ptl: + toolchain: + - xt-clang + - zephyr + intel_adsp/ace30: + twister: false + intel_adsp/ace20_lnl/sim: + type: sim + simulation: + - name: custom + exec: acesim + testing: + timeout_multiplier: 4 + intel_adsp/ace15_mtpm/sim: + type: sim + simulation: + - name: custom + exec: acesim + testing: + timeout_multiplier: 4 + intel_adsp/ace30/ptl/sim: + type: sim + simulation: + - name: custom + exec: acesim + toolchain: + - xt-clang + - zephyr + testing: + timeout_multiplier: 8 + intel_adsp/cavs25: + toolchain: + - xcc + - zephyr + supported: + - dma + - dai + intel_adsp/cavs25/tgph: + toolchain: + - xcc + - zephyr + supported: + - dma + - dai diff --git a/boards/intel/ehl/intel_ehl_crb_defconfig b/boards/intel/ehl/intel_ehl_crb_defconfig index ba1c681c4cf..734eca74bc2 100644 --- a/boards/intel/ehl/intel_ehl_crb_defconfig +++ b/boards/intel/ehl/intel_ehl_crb_defconfig @@ -8,5 +8,4 @@ CONFIG_UART_CONSOLE=y CONFIG_X2APIC=y CONFIG_SMP=y CONFIG_BUILD_OUTPUT_EFI=y -CONFIG_BUILD_NO_GAP_FILL=y CONFIG_PCIE_PRT=n diff --git a/boards/intel/ish/board.cmake b/boards/intel/ish/board.cmake index aa4b8ad48ae..a6329d38566 100644 --- a/boards/intel/ish/board.cmake +++ b/boards/intel/ish/board.cmake @@ -1,9 +1,8 @@ +# Copyright (c) 2023-2024 Intel Corporation +# # SPDX-License-Identifier: Apache-2.0 -set(SUPPORTED_EMU_PLATFORMS simics) - if(CONFIG_BOARD_INTEL_ISH_5_8_0) - board_emu_args(simics "project=$ENV{SIMICS_PROJECT}") board_emu_args(simics "zephyr_elf=${APPLICATION_BINARY_DIR}/zephyr/${KERNEL_ELF_NAME}") board_emu_args(simics "zephyr_start_address=${CONFIG_SRAM_BASE_ADDRESS}") include(${ZEPHYR_BASE}/boards/common/simics.board.cmake) diff --git a/boards/intel/ish/intel_ish_5_8_0.yaml b/boards/intel/ish/intel_ish_5_8_0.yaml index 566e7f21c13..34037b77449 100644 --- a/boards/intel/ish/intel_ish_5_8_0.yaml +++ b/boards/intel/ish/intel_ish_5_8_0.yaml @@ -5,11 +5,13 @@ arch: x86 toolchain: - zephyr ram: 640 -simulation: simics -simulation_exec: simics +simulation: + - name: simics + exec: simics supported: - serial testing: + timeout_multiplier: 2 ignore_tags: - net - bluetooth diff --git a/boards/intel/rpl/intel_rpl_p_crb_defconfig b/boards/intel/rpl/intel_rpl_p_crb_defconfig index c94efc744f6..853850deb12 100644 --- a/boards/intel/rpl/intel_rpl_p_crb_defconfig +++ b/boards/intel/rpl/intel_rpl_p_crb_defconfig @@ -10,4 +10,3 @@ CONFIG_UART_CONSOLE=y CONFIG_X2APIC=y CONFIG_SMP=y CONFIG_BUILD_OUTPUT_EFI=y -CONFIG_BUILD_NO_GAP_FILL=y diff --git a/boards/intel/rpl/intel_rpl_s_crb_defconfig b/boards/intel/rpl/intel_rpl_s_crb_defconfig index c94efc744f6..853850deb12 100644 --- a/boards/intel/rpl/intel_rpl_s_crb_defconfig +++ b/boards/intel/rpl/intel_rpl_s_crb_defconfig @@ -10,4 +10,3 @@ CONFIG_UART_CONSOLE=y CONFIG_X2APIC=y CONFIG_SMP=y CONFIG_BUILD_OUTPUT_EFI=y -CONFIG_BUILD_NO_GAP_FILL=y diff --git a/boards/intel/socfpga/agilex5_socdk/intel_socfpga_agilex5_socdk.dts b/boards/intel/socfpga/agilex5_socdk/intel_socfpga_agilex5_socdk.dts index d2f6c4370a3..6b185154fa6 100644 --- a/boards/intel/socfpga/agilex5_socdk/intel_socfpga_agilex5_socdk.dts +++ b/boards/intel/socfpga/agilex5_socdk/intel_socfpga_agilex5_socdk.dts @@ -26,6 +26,7 @@ mmc { /*SD Disk Access */ compatible = "zephyr,sdmmc-disk"; + disk-name = "SD"; status = "okay"; }; }; diff --git a/boards/intel/socfpga_std/cyclonev_socdk/doc/img/cv_soc_board.jpg b/boards/intel/socfpga_std/cyclonev_socdk/doc/img/cyclonev_socdk.jpg similarity index 100% rename from boards/intel/socfpga_std/cyclonev_socdk/doc/img/cv_soc_board.jpg rename to boards/intel/socfpga_std/cyclonev_socdk/doc/img/cyclonev_socdk.jpg diff --git a/boards/intel/socfpga_std/cyclonev_socdk/doc/index.rst b/boards/intel/socfpga_std/cyclonev_socdk/doc/index.rst index 6183491690c..7e6a426238a 100644 --- a/boards/intel/socfpga_std/cyclonev_socdk/doc/index.rst +++ b/boards/intel/socfpga_std/cyclonev_socdk/doc/index.rst @@ -10,7 +10,7 @@ Overview The Zephyr kernel is supported on the Intel® Cyclone® V SoC Development Kit, using its Hard Processor System (HPS) CPU. -.. figure:: img/cv_soc_board.jpg +.. figure:: img/cyclonev_socdk.jpg :align: center :alt: Intel's Cyclone® V SoC FPGA DevKit diff --git a/boards/khadas/edgev/doc/index.rst b/boards/khadas/edgev/doc/index.rst index c6c3e44826a..82294c07e99 100644 --- a/boards/khadas/edgev/doc/index.rst +++ b/boards/khadas/edgev/doc/index.rst @@ -1,7 +1,4 @@ -.. _khadas_edgev: - -Khadas Edge-V -################################# +.. zephyr:board:: khadas_edgev Overview ******** diff --git a/boards/kincony/kincony_kc868_a32/Kconfig b/boards/kincony/kincony_kc868_a32/Kconfig new file mode 100644 index 00000000000..19cad2072fe --- /dev/null +++ b/boards/kincony/kincony_kc868_a32/Kconfig @@ -0,0 +1,7 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 4096 if BOARD_KINCONY_KC868_A32_ESP32_PROCPU + default 256 if BOARD_KINCONY_KC868_A32_ESP32_APPCPU diff --git a/boards/kincony/kincony_kc868_a32/Kconfig.defconfig b/boards/kincony/kincony_kc868_a32/Kconfig.defconfig deleted file mode 100644 index 4d4613b36ad..00000000000 --- a/boards/kincony/kincony_kc868_a32/Kconfig.defconfig +++ /dev/null @@ -1,20 +0,0 @@ -# Copyright (c) 2023 Bartosz Bilas -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_KINCONY_KC868_A32_ESP32_PROCPU - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 65535 if WIFI && BT - default 51200 if WIFI - default 40960 if BT - default 4096 - -endif # BOARD_KINCONY_KC868_A32_ESP32_PROCPU - -if BOARD_KINCONY_KC868_A32_ESP32_APPCPU - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - default 256 - -endif # BOARD_KINCONY_KC868_A32_ESP32_APPCPU diff --git a/boards/kincony/kincony_kc868_a32/doc/index.rst b/boards/kincony/kincony_kc868_a32/doc/index.rst index ccc8676f512..d88eec584c6 100644 --- a/boards/kincony/kincony_kc868_a32/doc/index.rst +++ b/boards/kincony/kincony_kc868_a32/doc/index.rst @@ -1,7 +1,4 @@ -.. _kincony_kc868_a32: - -KINCONY KC868-A32 -################# +.. zephyr:board:: kincony_kc868_a32 Overview ******** @@ -23,12 +20,6 @@ The features include the following: - RESET and DOWNLOAD buttons - Powered by 12V DC -.. figure:: img/kincony_kc868_a32.jpg - :align: center - :alt: KINCONCY-KC868-A32 - - KINCONCY-KC868-A32 - System requirements =================== @@ -94,4 +85,6 @@ Enable Ethernet in KConfig: References ********** +.. target-notes:: + .. _KINCONY KC868-A32 User Guide: https://www.kincony.com/arduino-esp32-32-channel-relay-module-kc868-a32.html diff --git a/boards/kincony/kincony_kc868_a32/kincony_kc868_a32_appcpu.dts b/boards/kincony/kincony_kc868_a32/kincony_kc868_a32_appcpu.dts index 4717ca7fa62..d9747997ed0 100644 --- a/boards/kincony/kincony_kc868_a32/kincony_kc868_a32_appcpu.dts +++ b/boards/kincony/kincony_kc868_a32/kincony_kc868_a32_appcpu.dts @@ -6,15 +6,18 @@ /dts-v1/; #include +#include / { model = "Kincony KC868_A32 APPCPU"; compatible = "espressif,esp32"; chosen { - zephyr,sram = &sram0; + zephyr,sram = &sram1; zephyr,ipc_shm = &shm0; zephyr,ipc = &ipm0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_appcpu_partition; }; }; @@ -25,42 +28,3 @@ &trng0 { status = "okay"; }; - -&flash0 { - status = "okay"; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Reserve 60kB for the bootloader */ - boot_partition: partition@1000 { - label = "mcuboot"; - reg = <0x00001000 0x0000F000>; - read-only; - }; - - /* Reserve 1024kB for the application in slot 0 */ - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 0x00100000>; - }; - - /* Reserve 1024kB for the application in slot 1 */ - slot1_partition: partition@110000 { - label = "image-1"; - reg = <0x00110000 0x00100000>; - }; - - /* Reserve 256kB for the scratch partition */ - scratch_partition: partition@210000 { - label = "image-scratch"; - reg = <0x00210000 0x00040000>; - }; - - storage_partition: partition@250000 { - label = "storage"; - reg = <0x00250000 0x00006000>; - }; - }; -}; diff --git a/boards/kincony/kincony_kc868_a32/kincony_kc868_a32_procpu.dts b/boards/kincony/kincony_kc868_a32/kincony_kc868_a32_procpu.dts index be7da2765ef..5e7e337e7d8 100644 --- a/boards/kincony/kincony_kc868_a32/kincony_kc868_a32_procpu.dts +++ b/boards/kincony/kincony_kc868_a32/kincony_kc868_a32_procpu.dts @@ -18,7 +18,7 @@ }; chosen { - zephyr,sram = &sram0; + zephyr,sram = &sram1; zephyr,console = &uart0; zephyr,shell-uart = &uart0; zephyr,flash = &flash0; diff --git a/boards/kincony/kincony_kc868_a32/kincony_kc868_a32_procpu.yaml b/boards/kincony/kincony_kc868_a32/kincony_kc868_a32_procpu.yaml index 325c3794c29..89cfbb2e3fc 100644 --- a/boards/kincony/kincony_kc868_a32/kincony_kc868_a32_procpu.yaml +++ b/boards/kincony/kincony_kc868_a32/kincony_kc868_a32_procpu.yaml @@ -12,8 +12,4 @@ supported: - nvs - counter - entropy -testing: - ignore_tags: - - net - - bluetooth vendor: kincony diff --git a/boards/lilygo/ttgo_lora32/Kconfig b/boards/lilygo/ttgo_lora32/Kconfig new file mode 100644 index 00000000000..2b26ea33689 --- /dev/null +++ b/boards/lilygo/ttgo_lora32/Kconfig @@ -0,0 +1,7 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 4096 if BOARD_TTGO_LORA32_ESP32_PROCPU + default 256 if BOARD_TTGO_LORA32_ESP32_APPCPU diff --git a/boards/lilygo/ttgo_lora32/Kconfig.defconfig b/boards/lilygo/ttgo_lora32/Kconfig.defconfig deleted file mode 100644 index d77a95c89b0..00000000000 --- a/boards/lilygo/ttgo_lora32/Kconfig.defconfig +++ /dev/null @@ -1,25 +0,0 @@ -# Lilygo ttgo LoRa32 board configuration - -# Copyright (c) 2024 Lothar Felten -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_TTGO_LORA32_ESP32_PROCPU - -config ENTROPY_GENERATOR - default y - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 65535 if WIFI && BT - default 51200 if WIFI - default 40960 if BT - default 4096 - -endif # BOARD_TTGO_LORA32_ESP32_PROCPU - -if BOARD_TTGO_LORA32_ESP32_APPCPU - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - default 256 - -endif # BOARD_TTGO_LORA32_ESP32_APPCPU diff --git a/boards/lilygo/ttgo_lora32/doc/index.rst b/boards/lilygo/ttgo_lora32/doc/index.rst index c7a04423e90..fa6613d7414 100644 --- a/boards/lilygo/ttgo_lora32/doc/index.rst +++ b/boards/lilygo/ttgo_lora32/doc/index.rst @@ -1,12 +1,9 @@ -.. _ttgo_lora32: - -Lilygo TTGO LoRa32 -################## +.. zephyr:board:: ttgo_lora32 Overview ******** -The Lilygo TTGO LoRa32 is a development board for LoRa applications baesed on the ESP32-PICO-D4. +The Lilygo TTGO LoRa32 is a development board for LoRa applications based on the ESP32-PICO-D4. It's available in two versions supporting two different frequency ranges and features the following integrated components: @@ -18,13 +15,6 @@ It's available in two versions supporting two different frequency ranges and fea Some of the ESP32 I/O pins are accessible on the board's pin headers. -.. figure:: img/ttgo_lora32.webp - :align: center - :alt: Lilygo TTGO LoRa32 module - :width: 400 px - - Lilygo TTGO LoRa32 module - Functional Description ********************** @@ -49,13 +39,13 @@ of the Lilygo TTGO LoRa32 board. +------------------+-------------------------------------------------------------------------+ | Power Switch | Sliding power switch. | +------------------+-------------------------------------------------------------------------+ -| LCD screen | Built-in OLED display \(`SSD1306`_, 0.96", 128x64 px\) controlled | +| OLED display | Built-in OLED display \(`SSD1306`_, 0.96", 128x64 px\) controlled | | | by I2C interface | +------------------+-------------------------------------------------------------------------+ | SX1276/SX1278 | LoRa radio frontend chip, connected via SPI. | | | Use SX1276 for 433MHz and SX1276 for 868/915/923MHz. | +------------------+-------------------------------------------------------------------------+ -| TF card slot | TF card slot wired to the SD interface of the MCU. | +| TF card slot | TF card slot wired to the SDHC interface of the MCU. | +------------------+-------------------------------------------------------------------------+ @@ -178,8 +168,8 @@ Build and flash applications as usual (see :ref:`build_an_application` and :board: ttgo_lora32/esp32/procpu :goals: build -The usual ``flash`` target will work with the ``ttgo_lora32`` board -configuration. Here is an example for the :zephyr:code-sample:`hello_world` +The usual ``flash`` target will work with the ``ttgo_lora32`` board target. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: @@ -205,30 +195,15 @@ message in the monitor: ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** Hello World! ttgo_lora32 -LoRa samples +Code samples ============ -There are two LoRa samples that will work out of the box with this board. - -To build the LoRa transmit sample application using sysbuild use the command: - -.. zephyr-app-commands:: - :tool: west - :zephyr-app: samples/drivers/lora/send - :board: ttgo_lora32/esp32/procpu - :goals: build - :west-args: --sysbuild - :compact: - -To build the LoRa receive sample application using sysbuild use the command: +The following sample applications will work out of the box with this board: -.. zephyr-app-commands:: - :tool: west - :zephyr-app: samples/drivers/lora/receive - :board: ttgo_lora32/esp32/procpu - :goals: build - :west-args: --sysbuild - :compact: +* :zephyr:code-sample:`lora-send` +* :zephyr:code-sample:`lora-receive` +* :zephyr:code-sample:`fs` +* :zephyr:code-sample:`character-frame-buffer` Debugging ********* diff --git a/boards/lilygo/ttgo_lora32/ttgo_lora32-pinctrl.dtsi b/boards/lilygo/ttgo_lora32/ttgo_lora32-pinctrl.dtsi index 5f043ddb945..b8140e4451a 100644 --- a/boards/lilygo/ttgo_lora32/ttgo_lora32-pinctrl.dtsi +++ b/boards/lilygo/ttgo_lora32/ttgo_lora32-pinctrl.dtsi @@ -42,4 +42,11 @@ }; }; + sdhc0_default: sdhc0_default { + group1 { + pinmux = ; + bias-pull-up; + output-high; + }; + }; }; diff --git a/boards/lilygo/ttgo_lora32/ttgo_lora32_esp32_appcpu.dts b/boards/lilygo/ttgo_lora32/ttgo_lora32_esp32_appcpu.dts index c5eb19c240f..a4c5d93acfb 100644 --- a/boards/lilygo/ttgo_lora32/ttgo_lora32_esp32_appcpu.dts +++ b/boards/lilygo/ttgo_lora32/ttgo_lora32_esp32_appcpu.dts @@ -6,15 +6,18 @@ /dts-v1/; #include +#include / { model = "ttgo LoRa32 APPCPU"; compatible = "espressif,esp32"; chosen { - zephyr,sram = &sram0; + zephyr,sram = &sram1; zephyr,ipc_shm = &shm0; zephyr,ipc = &ipm0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_appcpu_partition; }; }; @@ -25,42 +28,3 @@ &trng0 { status = "okay"; }; - -&flash0 { - status = "okay"; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Reserve 60kB for the bootloader */ - boot_partition: partition@1000 { - label = "mcuboot"; - reg = <0x00001000 0x0000F000>; - read-only; - }; - - /* Reserve 1024kB for the application in slot 0 */ - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 0x00100000>; - }; - - /* Reserve 1024kB for the application in slot 1 */ - slot1_partition: partition@110000 { - label = "image-1"; - reg = <0x00110000 0x00100000>; - }; - - /* Reserve 256kB for the scratch partition */ - scratch_partition: partition@210000 { - label = "image-scratch"; - reg = <0x00210000 0x00040000>; - }; - - storage_partition: partition@250000 { - label = "storage"; - reg = <0x00250000 0x00006000>; - }; - }; -}; diff --git a/boards/lilygo/ttgo_lora32/ttgo_lora32_esp32_appcpu.yaml b/boards/lilygo/ttgo_lora32/ttgo_lora32_esp32_appcpu.yaml index f0485667260..0ab1a0e6182 100644 --- a/boards/lilygo/ttgo_lora32/ttgo_lora32_esp32_appcpu.yaml +++ b/boards/lilygo/ttgo_lora32/ttgo_lora32_esp32_appcpu.yaml @@ -24,4 +24,5 @@ testing: - cmsis_rtos - jwt - zdsp + - sdhc vendor: lilygo diff --git a/boards/lilygo/ttgo_lora32/ttgo_lora32_esp32_appcpu_defconfig b/boards/lilygo/ttgo_lora32/ttgo_lora32_esp32_appcpu_defconfig index 100bb882567..9abf2ff0430 100644 --- a/boards/lilygo/ttgo_lora32/ttgo_lora32_esp32_appcpu_defconfig +++ b/boards/lilygo/ttgo_lora32/ttgo_lora32_esp32_appcpu_defconfig @@ -2,4 +2,3 @@ CONFIG_MAIN_STACK_SIZE=2048 CONFIG_CLOCK_CONTROL=y -CONFIG_MINIMAL_LIBC=y diff --git a/boards/lilygo/ttgo_lora32/ttgo_lora32_esp32_procpu.dts b/boards/lilygo/ttgo_lora32/ttgo_lora32_esp32_procpu.dts index d8dfad087e3..6ae0dbeb015 100644 --- a/boards/lilygo/ttgo_lora32/ttgo_lora32_esp32_procpu.dts +++ b/boards/lilygo/ttgo_lora32/ttgo_lora32_esp32_procpu.dts @@ -8,6 +8,7 @@ #include #include "ttgo_lora32-pinctrl.dtsi" #include +#include / { model = "ttgo LoRa32 PROCPU"; @@ -18,16 +19,18 @@ uart-0 = &uart0; i2c-0 = &i2c0; watchdog0 = &wdt0; + sdhc0 = &sdhc1; lora0 = &lora0; }; chosen { - zephyr,sram = &sram0; + zephyr,sram = &sram1; zephyr,console = &uart0; zephyr,shell-uart = &uart0; zephyr,flash = &flash0; zephyr,code-partition = &slot0_partition; zephyr,display = &ssd1306_128x64; + zephyr,sdhc = &sdhc1; }; leds { @@ -121,41 +124,27 @@ status = "okay"; }; -&flash0 { - status = "okay"; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Reserve 60kB for the bootloader */ - boot_partition: partition@1000 { - label = "mcuboot"; - reg = <0x00001000 0x0000F000>; - read-only; - }; - - /* Reserve 1024kB for the application in slot 0 */ - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 0x00100000>; - }; - - /* Reserve 1024kB for the application in slot 1 */ - slot1_partition: partition@110000 { - label = "image-1"; - reg = <0x00110000 0x00100000>; - }; - - /* Reserve 256kB for the scratch partition */ - scratch_partition: partition@210000 { - label = "image-scratch"; - reg = <0x00210000 0x00040000>; - }; - - storage_partition: partition@250000 { - label = "storage"; - reg = <0x00250000 0x00006000>; +&sdhc { + sdhc1: sdhc@1 { + status = "okay"; + + pinctrl-0 = <&sdhc0_default>; + pinctrl-names = "default"; + power-delay-ms = <100>; + max-bus-freq = <52000000>; + bus-width = <4>; + + clk-pin = <14>; + cmd-pin = <15>; + d0-pin = <2>; + d1-pin = <4>; + d2-pin = <12>; + d3-pin = <13>; + + mmc { + compatible = "zephyr,sdmmc-disk"; + disk-name = "SD"; + status = "okay"; }; }; }; diff --git a/boards/lilygo/ttgo_lora32/ttgo_lora32_esp32_procpu.yaml b/boards/lilygo/ttgo_lora32/ttgo_lora32_esp32_procpu.yaml index f4d0e25cc59..e59818cc3dc 100644 --- a/boards/lilygo/ttgo_lora32/ttgo_lora32_esp32_procpu.yaml +++ b/boards/lilygo/ttgo_lora32/ttgo_lora32_esp32_procpu.yaml @@ -14,8 +14,5 @@ supported: - display - lora - nvs -testing: - ignore_tags: - - net - - bluetooth + - sdhc vendor: lilygo diff --git a/boards/lilygo/ttgo_lora32/ttgo_lora32_esp32_procpu_defconfig b/boards/lilygo/ttgo_lora32/ttgo_lora32_esp32_procpu_defconfig index ee9920cda68..e18641b5d44 100644 --- a/boards/lilygo/ttgo_lora32/ttgo_lora32_esp32_procpu_defconfig +++ b/boards/lilygo/ttgo_lora32/ttgo_lora32_esp32_procpu_defconfig @@ -8,3 +8,6 @@ CONFIG_UART_CONSOLE=y CONFIG_GPIO=y CONFIG_I2C=y + +# the following config is required to support chips of revision 1 +CONFIG_ESP32_USE_UNSUPPORTED_REVISION=y diff --git a/boards/lilygo/ttgo_t7v1_5/Kconfig b/boards/lilygo/ttgo_t7v1_5/Kconfig new file mode 100644 index 00000000000..05e38e3f85c --- /dev/null +++ b/boards/lilygo/ttgo_t7v1_5/Kconfig @@ -0,0 +1,7 @@ +# Copyright 2024 Tobias Kässer +# SPDX-License-Identifier: Apache-2.0 + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 4096 if BOARD_TTGO_T7V1_5_ESP32_PROCPU + default 256 if BOARD_TTGO_T7V1_5_ESP32_APPCPU diff --git a/boards/lilygo/ttgo_t7v1_5/Kconfig.sysbuild b/boards/lilygo/ttgo_t7v1_5/Kconfig.sysbuild new file mode 100644 index 00000000000..3a2d17ac5cf --- /dev/null +++ b/boards/lilygo/ttgo_t7v1_5/Kconfig.sysbuild @@ -0,0 +1,10 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +choice BOOTLOADER + default BOOTLOADER_MCUBOOT +endchoice + +choice BOOT_SIGNATURE_TYPE + default BOOT_SIGNATURE_TYPE_NONE +endchoice diff --git a/boards/lilygo/ttgo_t7v1_5/Kconfig.ttgo_t7v1_5 b/boards/lilygo/ttgo_t7v1_5/Kconfig.ttgo_t7v1_5 new file mode 100644 index 00000000000..e612323a066 --- /dev/null +++ b/boards/lilygo/ttgo_t7v1_5/Kconfig.ttgo_t7v1_5 @@ -0,0 +1,7 @@ +# Copyright 2024 Tobias Kässer +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_TTGO_T7V1_5 + select SOC_ESP32 + select SOC_ESP32_PROCPU if BOARD_TTGO_T7V1_5_ESP32_PROCPU + select SOC_ESP32_APPCPU if BOARD_TTGO_T7V1_5_ESP32_APPCPU diff --git a/boards/lilygo/ttgo_t7v1_5/board.cmake b/boards/lilygo/ttgo_t7v1_5/board.cmake new file mode 100644 index 00000000000..2f04d1fe886 --- /dev/null +++ b/boards/lilygo/ttgo_t7v1_5/board.cmake @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +if(NOT "${OPENOCD}" MATCHES "^${ESPRESSIF_TOOLCHAIN_PATH}/.*") + set(OPENOCD OPENOCD-NOTFOUND) +endif() +find_program(OPENOCD openocd PATHS ${ESPRESSIF_TOOLCHAIN_PATH}/openocd-esp32/bin NO_DEFAULT_PATH) + +include(${ZEPHYR_BASE}/boards/common/esp32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/lilygo/ttgo_t7v1_5/board.yml b/boards/lilygo/ttgo_t7v1_5/board.yml new file mode 100644 index 00000000000..0a3f7198646 --- /dev/null +++ b/boards/lilygo/ttgo_t7v1_5/board.yml @@ -0,0 +1,5 @@ +board: + name: ttgo_t7v1_5 + vendor: lilygo + socs: + - name: esp32 diff --git a/boards/lilygo/ttgo_t7v1_5/doc/img/ttgo_t7v1_5.webp b/boards/lilygo/ttgo_t7v1_5/doc/img/ttgo_t7v1_5.webp new file mode 100644 index 00000000000..605a4fb7cc8 Binary files /dev/null and b/boards/lilygo/ttgo_t7v1_5/doc/img/ttgo_t7v1_5.webp differ diff --git a/boards/lilygo/ttgo_t7v1_5/doc/index.rst b/boards/lilygo/ttgo_t7v1_5/doc/index.rst new file mode 100644 index 00000000000..13f5107cd80 --- /dev/null +++ b/boards/lilygo/ttgo_t7v1_5/doc/index.rst @@ -0,0 +1,216 @@ +.. zephyr:board:: ttgo_t7v1_5 + +Overview +******** + +LILYGO® TTGO T7 Mini32 V1.5 ia an IoT mini development board +based on the Espressif ESP32-WROVER-E module. + +It features the following integrated components: +- ESP32 chip (240MHz dual core, 520KB SRAM, Wi-Fi, Bluetooth) +- on board antenna +- Micro-USB connector for power and communication +- JST GH 2-pin battery connector +- LED + +Functional Description +********************** +This board is based on the ESP32-WROVER-E module with 4MB of flash (there +are models 16MB as well), WiFi and BLE support. It has a Micro-USB port for +programming and debugging, integrated battery charging and an on-board antenna. + +Connections and IOs +=================== + +The ``ttgo_t7v1_5/esp32/procpu`` board target supports the following hardware features: + ++-----------+------------+------------------+ +| Interface | Controller | Driver/Component | ++===========+============+==================+ +| CPU | ESP32 | arch/xtensa | ++-----------+------------+------------------+ +| GPIO | on-chip | gpio_esp32 | ++-----------+------------+------------------+ +| UART | on-chip | uart_esp32 | ++-----------+------------+------------------+ +| I2C | on-chip | i2c_esp32 | ++-----------+------------+------------------+ +| SPI | on-chip | spi_esp32_spim | ++-----------+------------+------------------+ +| LoRa | SX1276 | lora_sx127x | ++-----------+------------+------------------+ +| WiFi | on-chip | wifi_esp32 | ++-----------+------------+------------------+ +| BLE | on-chip | bluetooth_esp32 | ++-----------+------------+------------------+ +| Flash | on-chip | flash_esp32 | ++-----------+------------+------------------+ + +System requirements +******************* + +Prerequisites +============= + +Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command +below to retrieve those files. + +.. code-block:: console + + west blobs fetch hal_espressif + +.. note:: + + It is recommended running the command above after :file:`west update`. + +Building & Flashing +******************* + +Simple boot +=========== + +The board could be loaded using the single binary image, without 2nd stage bootloader. +It is the default option when building the application without additional configuration. + +.. note:: + + Simple boot does not provide any security features nor OTA updates. + +MCUboot bootloader +================== + +User may choose to use MCUboot bootloader instead. In that case the bootloader +must be build (and flash) at least once. + +There are two options to be used when building an application: + +1. Sysbuild +2. Manual build + +.. note:: + + User can select the MCUboot bootloader by adding the following line + to the board default configuration file. + + .. code:: cfg + + CONFIG_BOOTLOADER_MCUBOOT=y + +Sysbuild +======== + +The sysbuild makes possible to build and flash all necessary images needed to +bootstrap the board with the ESP32 SoC. + +To build the sample application using sysbuild use the command: + +.. zephyr-app-commands:: + :tool: west + :app: samples/hello_world + :board: ttgo_t7v1_5/esp32/procpu + :goals: build + :west-args: --sysbuild + :compact: + +By default, the ESP32 sysbuild creates bootloader (MCUboot) and application +images. But it can be configured to create other kind of images. + +Build directory structure created by sysbuild is different from traditional +Zephyr build. Output is structured by the domain subdirectories: + +.. code-block:: + + build/ + ├── hello_world + │   └── zephyr + │   ├── zephyr.elf + │   └── zephyr.bin + ├── mcuboot + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + └── domains.yaml + +.. note:: + + With ``--sysbuild`` option the bootloader will be re-build and re-flash + every time the pristine build is used. + +For more information about the system build please read the :ref:`sysbuild` documentation. + +Manual build +============ + +During the development cycle, it is intended to build & flash as quickly possible. +For that reason, images can be build one at a time using traditional build. + +The instructions following are relevant for both manual build and sysbuild. +The only difference is the structure of the build directory. + +.. note:: + + Remember that bootloader (MCUboot) needs to be flash at least once. + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: ttgo_t7v1_5/esp32/procpu + :goals: build + +The usual ``flash`` target will work with the ``ttgo_t7v1_5`` board +configuration. Here is an example for the :zephyr:code-sample:`hello_world` +application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: ttgo_t7v1_5/esp32/procpu + :goals: flash + +The default baud rate for the Lilygo TTGO T7 V1.5 is set to 1500000bps. If experiencing issues when flashing, +try using different values by using ``--esp-baud-rate `` option during +``west flash`` (e.g. ``west flash --esp-baud-rate 115200``). + +You can also open the serial monitor using the following command: + +.. code-block:: shell + + west espressif monitor + +After the board has automatically reset and booted, you should see the following +message in the monitor: + +.. code-block:: console + + ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** + Hello World! ttgo_t7v1_5 + +Sample applications +=================== + +The following samples will run out of the box on the TTGO T7 V1.5 board. + +To build the blinky sample: + +.. zephyr-app-commands:: + :tool: west + :app: samples/basic/blinky + :board: ttgo_t7v1_5/esp32/procpu + :goals: build + +To build the bluetooth beacon sample: + +.. zephyr-app-commands:: + :tool: west + :app: samples/bluetooth/beacon + :board: ttgo_t7v1_5/esp32/procpu + :goals: build + + +Related Documents +***************** +.. _`Lilygo TTGO T7-V1.5 schematic`: https://github.com/LilyGO/TTGO-T7-Demo/blob/master/t7_v1.5.pdf +.. _`Lilygo github repo`: https://github.com/LilyGO/TTGO-T7-Demo/tree/master +.. _`Espressif ESP32-WROVER-E datasheet`: https://www.espressif.com/sites/default/files/documentation/esp32-wrover-e_esp32-wrover-ie_datasheet_en.pdf +.. _`OpenOCD ESP32`: https://github.com/espressif/openocd-esp32/releases diff --git a/boards/lilygo/ttgo_t7v1_5/support/openocd.cfg b/boards/lilygo/ttgo_t7v1_5/support/openocd.cfg new file mode 100644 index 00000000000..756e960dd20 --- /dev/null +++ b/boards/lilygo/ttgo_t7v1_5/support/openocd.cfg @@ -0,0 +1,6 @@ +set ESP_RTOS none + +source [find interface/esp_usb_jtag.cfg] + +source [find target/esp32.cfg] +adapter_khz 5000 diff --git a/boards/lilygo/ttgo_t7v1_5/ttgo_t7v1_5-pinctrl.dtsi b/boards/lilygo/ttgo_t7v1_5/ttgo_t7v1_5-pinctrl.dtsi new file mode 100644 index 00000000000..13daa9b7ce9 --- /dev/null +++ b/boards/lilygo/ttgo_t7v1_5/ttgo_t7v1_5-pinctrl.dtsi @@ -0,0 +1,44 @@ +/* + * Copyright 2024 Tobias Kässer + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +&pinctrl { + uart0_default: uart0_default { + group1 { + pinmux = ; + output-high; + }; + group2 { + pinmux = ; + bias-pull-up; + }; + }; + + spim3_default: spim3_default { + group1 { + pinmux = , + ; + }; + /* GPIO5 is CS */ + group2 { + pinmux = ; + output-low; + }; + }; + + i2c0_default: i2c0_default { + group1 { + pinmux = , + ; + bias-pull-up; + drive-open-drain; + output-high; + }; + }; +}; diff --git a/boards/lilygo/ttgo_t7v1_5/ttgo_t7v1_5_esp32_appcpu.dts b/boards/lilygo/ttgo_t7v1_5/ttgo_t7v1_5_esp32_appcpu.dts new file mode 100644 index 00000000000..baca8424861 --- /dev/null +++ b/boards/lilygo/ttgo_t7v1_5/ttgo_t7v1_5_esp32_appcpu.dts @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include +#include + +/ { + model = "ttgo t7 v1.5 APPCPU"; + compatible = "espressif,esp32"; + + chosen { + zephyr,sram = &sram0; + zephyr,ipc_shm = &shm0; + zephyr,ipc = &ipm0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_appcpu_partition; + }; +}; + +&ipm0 { + status = "okay"; +}; + +&trng0 { + status = "okay"; +}; diff --git a/boards/lilygo/ttgo_t7v1_5/ttgo_t7v1_5_esp32_appcpu.yaml b/boards/lilygo/ttgo_t7v1_5/ttgo_t7v1_5_esp32_appcpu.yaml new file mode 100644 index 00000000000..b7efb73d9ae --- /dev/null +++ b/boards/lilygo/ttgo_t7v1_5/ttgo_t7v1_5_esp32_appcpu.yaml @@ -0,0 +1,27 @@ +identifier: ttgo_t7v1_5/esp32/appcpu +name: TTGO T7 V1.5 APPCPU +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - uart +testing: + ignore_tags: + - net + - bluetooth + - flash + - cpp + - posix + - watchdog + - logging + - kernel + - pm + - gpio + - crypto + - eeprom + - heap + - cmsis_rtos + - jwt + - zdsp +vendor: lilygo diff --git a/boards/lilygo/ttgo_t7v1_5/ttgo_t7v1_5_esp32_appcpu_defconfig b/boards/lilygo/ttgo_t7v1_5/ttgo_t7v1_5_esp32_appcpu_defconfig new file mode 100644 index 00000000000..9abf2ff0430 --- /dev/null +++ b/boards/lilygo/ttgo_t7v1_5/ttgo_t7v1_5_esp32_appcpu_defconfig @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 +CONFIG_CLOCK_CONTROL=y diff --git a/boards/lilygo/ttgo_t7v1_5/ttgo_t7v1_5_esp32_procpu.dts b/boards/lilygo/ttgo_t7v1_5/ttgo_t7v1_5_esp32_procpu.dts new file mode 100644 index 00000000000..4fab0e2ae72 --- /dev/null +++ b/boards/lilygo/ttgo_t7v1_5/ttgo_t7v1_5_esp32_procpu.dts @@ -0,0 +1,98 @@ +/* + * Copyright 2024 Tobias Kässer + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include +#include +#include "ttgo_t7v1_5-pinctrl.dtsi" +#include + +/ { + model = "ttgo T7 V1.5 PROCPU"; + compatible = "lilygo,ttgo-t7v1_5"; + + aliases { + led0 = &green_led; + uart-0 = &uart0; + i2c-0 = &i2c0; + watchdog0 = &wdt0; + }; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + }; + + leds { + compatible = "gpio-leds"; + + green_led: led_0 { + gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>; + label = "Green - LED0"; + }; + }; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +/* OLED display */ +&i2c0 { + status = "okay"; + clock-frequency = ; + sda-gpios = <&gpio0 21 GPIO_OPEN_DRAIN>; + scl-gpios = <&gpio0 22 GPIO_OPEN_DRAIN>; + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; +}; + +&spi3 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim3_default>; + pinctrl-names = "default"; + cs-gpios = <&gpio0 27 GPIO_ACTIVE_LOW>; +}; + +&timer0 { + status = "okay"; +}; + +&timer1 { + status = "okay"; +}; + +&timer2 { + status = "okay"; +}; + +&timer3 { + status = "okay"; +}; + +&trng0 { + status = "okay"; +}; + +&wifi { + status = "okay"; +}; diff --git a/boards/lilygo/ttgo_t7v1_5/ttgo_t7v1_5_esp32_procpu.yaml b/boards/lilygo/ttgo_t7v1_5/ttgo_t7v1_5_esp32_procpu.yaml new file mode 100644 index 00000000000..25d43a61502 --- /dev/null +++ b/boards/lilygo/ttgo_t7v1_5/ttgo_t7v1_5_esp32_procpu.yaml @@ -0,0 +1,16 @@ +identifier: ttgo_t7v1_5/esp32/procpu +name: TTGO T7 V1.5 PROCPU +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - gpio + - i2c + - spi + - watchdog + - uart + - pinmux + - display + - nvs +vendor: lilygo diff --git a/boards/lilygo/ttgo_t7v1_5/ttgo_t7v1_5_esp32_procpu_defconfig b/boards/lilygo/ttgo_t7v1_5/ttgo_t7v1_5_esp32_procpu_defconfig new file mode 100644 index 00000000000..f029cac9e9e --- /dev/null +++ b/boards/lilygo/ttgo_t7v1_5/ttgo_t7v1_5_esp32_procpu_defconfig @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y + +CONFIG_GPIO=y diff --git a/boards/lilygo/ttgo_t8c3/Kconfig b/boards/lilygo/ttgo_t8c3/Kconfig new file mode 100644 index 00000000000..c6a99b1032d --- /dev/null +++ b/boards/lilygo/ttgo_t8c3/Kconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 4096 diff --git a/boards/lilygo/ttgo_t8c3/Kconfig.defconfig b/boards/lilygo/ttgo_t8c3/Kconfig.defconfig deleted file mode 100644 index eb2f107cd0d..00000000000 --- a/boards/lilygo/ttgo_t8c3/Kconfig.defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2024 Lothar Felten -# SPDX-License-Identifier: Apache-2.0 - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 65535 if WIFI && BT - default 51200 if WIFI - default 40960 if BT - default 4096 diff --git a/boards/lilygo/ttgo_t8c3/Kconfig.ttgo_t8c3 b/boards/lilygo/ttgo_t8c3/Kconfig.ttgo_t8c3 index 60cd233a9b4..d65bd257bef 100644 --- a/boards/lilygo/ttgo_t8c3/Kconfig.ttgo_t8c3 +++ b/boards/lilygo/ttgo_t8c3/Kconfig.ttgo_t8c3 @@ -2,4 +2,4 @@ # SPDX-License-Identifier: Apache-2.0 config BOARD_TTGO_T8C3 - select SOC_ESP32C3_FX4 + select SOC_ESP32C3_FN4 diff --git a/boards/lilygo/ttgo_t8c3/doc/index.rst b/boards/lilygo/ttgo_t8c3/doc/index.rst index 2b11dd90a0a..4179528b6af 100644 --- a/boards/lilygo/ttgo_t8c3/doc/index.rst +++ b/boards/lilygo/ttgo_t8c3/doc/index.rst @@ -1,7 +1,4 @@ -.. _ttgo_t8c3: - -Lilygo TTGO T8-C3 -################# +.. zephyr:board:: ttgo_t8c3 Overview ******** @@ -17,12 +14,6 @@ It features the following integrated components: - JST GH 2-pin battery connector - LED -.. figure:: img/ttgo_t8c3.webp - :align: center - :alt: TTGO T8-C3 - - Lilygo TTGO T8-C3 - Functional Description ********************** This board is based on the ESP32-C3 with 4MB of flash, WiFi and BLE support. It @@ -33,7 +24,7 @@ enabled by moving a 0-ohm resistor. Connections and IOs =================== -The TTGO T8-C3 board configuration supports the following hardware features: +The ``ttgo_t8c3`` board target supports the following hardware features: +-----------+------------+------------------+ | Interface | Controller | Driver/Component | @@ -176,9 +167,8 @@ Build and flash applications as usual (see :ref:`build_an_application` and :board: ttgo_t8c3 :goals: build -The usual ``flash`` target will work with the ``ttgo_t8c3`` board -configuration. Here is an example for the :zephyr:code-sample:`hello_world` -application. +The usual ``flash`` target will work with the ``ttgo_t8c3`` board target. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/lilygo/ttgo_t8c3/ttgo_t8c3.dts b/boards/lilygo/ttgo_t8c3/ttgo_t8c3.dts index a38f5777762..896fdfc3bbf 100644 --- a/boards/lilygo/ttgo_t8c3/ttgo_t8c3.dts +++ b/boards/lilygo/ttgo_t8c3/ttgo_t8c3.dts @@ -8,6 +8,7 @@ #include #include "ttgo_t8c3-pinctrl.dtsi" +#include / { model = "Lilygo TTGO T8-C3"; @@ -20,7 +21,7 @@ }; chosen { - zephyr,sram = &sram0; + zephyr,sram = &sram1; zephyr,console = &usb_serial; zephyr,shell-uart = &usb_serial; zephyr,flash = &flash0; @@ -38,6 +39,10 @@ }; }; +&flash0 { + reg = <0x0 DT_SIZE_M(4)>; +}; + &uart0 { status = "okay"; current-speed = <115200>; @@ -97,37 +102,3 @@ &esp32_bt_hci{ status = "okay"; }; - -&flash0 { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x0000F000>; - read-only; - }; - - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 0x00100000>; - }; - - slot1_partition: partition@110000 { - label = "image-1"; - reg = <0x00110000 0x00100000>; - }; - - scratch_partition: partition@210000 { - label = "image-scratch"; - reg = <0x00210000 0x00040000>; - }; - - storage_partition: partition@250000 { - label = "storage"; - reg = <0x00250000 0x00006000>; - }; - }; -}; diff --git a/boards/lilygo/ttgo_t8c3/ttgo_t8c3.yaml b/boards/lilygo/ttgo_t8c3/ttgo_t8c3.yaml index e2fc320098a..e0d0ce24a3d 100644 --- a/boards/lilygo/ttgo_t8c3/ttgo_t8c3.yaml +++ b/boards/lilygo/ttgo_t8c3/ttgo_t8c3.yaml @@ -11,8 +11,4 @@ supported: - uart - watchdog - can -testing: - ignore_tags: - - net - - bluetooth vendor: lilygo diff --git a/boards/lilygo/ttgo_t8s3/Kconfig b/boards/lilygo/ttgo_t8s3/Kconfig new file mode 100644 index 00000000000..e0797e974b8 --- /dev/null +++ b/boards/lilygo/ttgo_t8s3/Kconfig @@ -0,0 +1,7 @@ +# Copyright (c) 2024 Lothar Felten +# SPDX-License-Identifier: Apache-2.0 + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 4096 if BOARD_TTGO_T8S3_ESP32S3_PROCPU + default 256 if BOARD_TTGO_T8S3_ESP32S3_APPCPU diff --git a/boards/lilygo/ttgo_t8s3/Kconfig.sysbuild b/boards/lilygo/ttgo_t8s3/Kconfig.sysbuild new file mode 100644 index 00000000000..3a2d17ac5cf --- /dev/null +++ b/boards/lilygo/ttgo_t8s3/Kconfig.sysbuild @@ -0,0 +1,10 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +choice BOOTLOADER + default BOOTLOADER_MCUBOOT +endchoice + +choice BOOT_SIGNATURE_TYPE + default BOOT_SIGNATURE_TYPE_NONE +endchoice diff --git a/boards/lilygo/ttgo_t8s3/Kconfig.ttgo_t8s3 b/boards/lilygo/ttgo_t8s3/Kconfig.ttgo_t8s3 new file mode 100644 index 00000000000..d119b68f6cb --- /dev/null +++ b/boards/lilygo/ttgo_t8s3/Kconfig.ttgo_t8s3 @@ -0,0 +1,7 @@ +# Copyright 2024 Lothar Felten +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_TTGO_T8S3 + select SOC_ESP32S3_WROOM_N16R8 + select SOC_ESP32S3_PROCPU if BOARD_TTGO_T8S3_ESP32S3_PROCPU + select SOC_ESP32S3_APPCPU if BOARD_TTGO_T8S3_ESP32S3_APPCPU diff --git a/boards/lilygo/ttgo_t8s3/board.cmake b/boards/lilygo/ttgo_t8s3/board.cmake new file mode 100644 index 00000000000..2f04d1fe886 --- /dev/null +++ b/boards/lilygo/ttgo_t8s3/board.cmake @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +if(NOT "${OPENOCD}" MATCHES "^${ESPRESSIF_TOOLCHAIN_PATH}/.*") + set(OPENOCD OPENOCD-NOTFOUND) +endif() +find_program(OPENOCD openocd PATHS ${ESPRESSIF_TOOLCHAIN_PATH}/openocd-esp32/bin NO_DEFAULT_PATH) + +include(${ZEPHYR_BASE}/boards/common/esp32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/lilygo/ttgo_t8s3/board.yml b/boards/lilygo/ttgo_t8s3/board.yml new file mode 100644 index 00000000000..a6bed2be915 --- /dev/null +++ b/boards/lilygo/ttgo_t8s3/board.yml @@ -0,0 +1,6 @@ +board: + name: ttgo_t8s3 + full_name: TTGO T8-S3 + vendor: lilygo + socs: + - name: esp32s3 diff --git a/boards/lilygo/ttgo_t8s3/doc/img/ttgo_t8s3.webp b/boards/lilygo/ttgo_t8s3/doc/img/ttgo_t8s3.webp new file mode 100644 index 00000000000..1ebfce3627c Binary files /dev/null and b/boards/lilygo/ttgo_t8s3/doc/img/ttgo_t8s3.webp differ diff --git a/boards/lilygo/ttgo_t8s3/doc/index.rst b/boards/lilygo/ttgo_t8s3/doc/index.rst new file mode 100644 index 00000000000..09455ed19a6 --- /dev/null +++ b/boards/lilygo/ttgo_t8s3/doc/index.rst @@ -0,0 +1,229 @@ +.. zephyr:board:: ttgo_t8s3 + +Overview +******** + +Lilygo TTGO T8-S3 is an IoT mini development board based on the +Espressif ESP32-S3 WiFi/Bluetooth dual-mode chip. + +It features the following integrated components: + +- ESP32-S3 chip (240MHz dual core, Bluetooth LE, Wi-Fi) +- on board antenna and IPEX connector +- USB-C connector for power and communication +- MX 1.25mm 2-pin battery connector +- JST SH 1.0mm 4-pin UART connector +- SD card slot + +Functional Description +********************** +This board is based on the ESP32-S3 with 16MB of flash, WiFi and BLE support. It +has an USB-C port for programming and debugging, integrated battery charging +and an on-board antenna. The fitted U.FL external antenna connector can be +enabled by moving a 0-ohm resistor. + +Connections and IOs +=================== + +The ``ttgo_t8s3`` board target supports the following hardware features: + ++------------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++============+============+=====================================+ +| UART | on-chip | serial port | ++------------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++------------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++------------+------------+-------------------------------------+ +| USB-JTAG | on-chip | hardware interface | ++------------+------------+-------------------------------------+ +| SPI Master | on-chip | spi, sdmmc | ++------------+------------+-------------------------------------+ +| TWAI/CAN | on-chip | can | ++------------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++------------+------------+-------------------------------------+ +| Timers | on-chip | counter | ++------------+------------+-------------------------------------+ +| Watchdog | on-chip | watchdog | ++------------+------------+-------------------------------------+ +| TRNG | on-chip | entropy | ++------------+------------+-------------------------------------+ +| LEDC | on-chip | pwm | ++------------+------------+-------------------------------------+ +| MCPWM | on-chip | pwm | ++------------+------------+-------------------------------------+ +| PCNT | on-chip | qdec | ++------------+------------+-------------------------------------+ +| GDMA | on-chip | dma | ++------------+------------+-------------------------------------+ +| USB-CDC | on-chip | serial | ++------------+------------+-------------------------------------+ + +Start Application Development +***************************** + +Before powering up your Lilygo TTGO T8-S3, please make sure that the board is in good +condition with no obvious signs of damage. + +System requirements +******************* + +Prerequisites +============= + +Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command +below to retrieve those files. + +.. code-block:: console + + west blobs fetch hal_espressif + +.. note:: + + It is recommended running the command above after :file:`west update`. + +Building & Flashing +******************* + +Simple boot +=========== + +The board could be loaded using the single binary image, without 2nd stage bootloader. +It is the default option when building the application without additional configuration. + +.. note:: + + Simple boot does not provide any security features nor OTA updates. + +MCUboot bootloader +================== + +User may choose to use MCUboot bootloader instead. In that case the bootloader +must be built (and flashed) at least once. + +There are two options to be used when building an application: + +1. Sysbuild +2. Manual build + +.. note:: + + User can select the MCUboot bootloader by adding the following line + to the board default configuration file. + + .. code-block:: cfg + + CONFIG_BOOTLOADER_MCUBOOT=y + +Sysbuild +======== + +The sysbuild makes possible to build and flash all necessary images needed to +bootstrap the board with the ESP32 SoC. + +To build the sample application using sysbuild use the command: + +.. zephyr-app-commands:: + :tool: west + :zephyr-app: samples/hello_world + :board: ttgo_t8s3/esp32s3/procpu + :goals: build + :west-args: --sysbuild + :compact: + +By default, the ESP32 sysbuild creates bootloader (MCUboot) and application +images. But it can be configured to create other kind of images. + +Build directory structure created by sysbuild is different from traditional +Zephyr build. Output is structured by the domain subdirectories: + +.. code-block:: + + build/ + ├── hello_world + │   └── zephyr + │   ├── zephyr.elf + │   └── zephyr.bin + ├── mcuboot + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + └── domains.yaml + +.. note:: + + With ``--sysbuild`` option the bootloader will be re-build and re-flash + every time the pristine build is used. + +For more information about the system build please read the :ref:`sysbuild` documentation. + +Manual build +============ + +During the development cycle, it is intended to build & flash as quickly possible. +For that reason, images can be built one at a time using traditional build. + +The instructions following are relevant for both manual build and sysbuild. +The only difference is the structure of the build directory. + +.. note:: + + Remember that bootloader (MCUboot) needs to be flash at least once. + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: ttgo_t8s3/esp32s3/procpu + :goals: build + +The usual ``flash`` target will work with the ``ttgo_t8s3`` board target +configuration. Here is an example for the :zephyr:code-sample:`hello_world` +application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: ttgo_t8s3/esp32s3/procpu + :goals: flash + +The default baud rate for the Lilygo TTGO T8-S3 is set to 1500000bps. If experiencing issues when flashing, +try using different values by using ``--esp-baud-rate `` option during +``west flash`` (e.g. ``west flash --esp-baud-rate 115200``). + +You can also open the serial monitor using the following command: + +.. code-block:: shell + + west espressif monitor + +After the board has automatically reset and booted, you should see the following +message in the monitor: + +.. code-block:: console + + ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** + Hello World! ttgo_t8s3 + +Code samples +============ + +The following code samples will run out of the box on the TTGO T8-S3 board: + +* :zephyr:code-sample:`wifi-shell` +* :zephyr:code-sample:`fs` + + +References +********** + +.. target-notes:: + +.. _`Lilygo TTGO T8-S3 schematic`: https://github.com/Xinyuan-LilyGO/T8-S3/blob/main/schematic/T8_S3_V1.0.pdf +.. _`Lilygo github repo`: https://github.com/Xinyuan-LilyGo +.. _`ESP32-S3 Datasheet`: https://www.espressif.com/sites/default/files/documentation/esp32-s3-mini-1_mini-1u_datasheet_en.pdf +.. _`ESP32-S3 Technical Reference Manual`: https://www.espressif.com/sites/default/files/documentation/esp32-s3_technical_reference_manual_en.pdf +.. _`OpenOCD ESP32`: https://github.com/espressif/openocd-esp32/releases +.. _`JTAG debugging for ESP32-S3`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32s3/api-guides/jtag-debugging/ diff --git a/boards/lilygo/ttgo_t8s3/support/openocd.cfg b/boards/lilygo/ttgo_t8s3/support/openocd.cfg new file mode 100644 index 00000000000..0b2c4909fe0 --- /dev/null +++ b/boards/lilygo/ttgo_t8s3/support/openocd.cfg @@ -0,0 +1,7 @@ +set ESP_RTOS none +set ESP32_ONLYCPU 1 + +source [find interface/esp_usb_jtag.cfg] + +source [find target/esp32s3.cfg] +adapter_khz 5000 diff --git a/boards/lilygo/ttgo_t8s3/ttgo_t8s3-pinctrl.dtsi b/boards/lilygo/ttgo_t8s3/ttgo_t8s3-pinctrl.dtsi new file mode 100644 index 00000000000..7b6d46e474c --- /dev/null +++ b/boards/lilygo/ttgo_t8s3/ttgo_t8s3-pinctrl.dtsi @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2024 Lothar Felten + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +&pinctrl { + uart0_default: uart0_default { + group1 { + pinmux = ; + output-high; + }; + group2 { + pinmux = ; + bias-pull-up; + }; + }; + + i2c0_default: i2c0_default { + group1 { + pinmux = , + ; + bias-pull-up; + drive-open-drain; + output-high; + }; + }; + + spim2_default: spim2_default { + group1 { + pinmux = , + , + ; + }; + group2 { + pinmux = ; + output-low; + }; + }; + + spim3_default: spim3_default { + group1 { + pinmux = , + , + ; + }; + group2 { + pinmux = ; + output-low; + }; + }; + + twai_default: twai_default { + group1 { + pinmux = , + ; + }; + }; +}; diff --git a/boards/lilygo/ttgo_t8s3/ttgo_t8s3_appcpu.dts b/boards/lilygo/ttgo_t8s3/ttgo_t8s3_appcpu.dts new file mode 100644 index 00000000000..fe07757f5cf --- /dev/null +++ b/boards/lilygo/ttgo_t8s3/ttgo_t8s3_appcpu.dts @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include +#include + +/ { + model = "TTGO T8S3 APPCPU"; + compatible = "espressif,esp32s3"; + + chosen { + zephyr,sram = &sram0; + zephyr,ipc_shm = &shm0; + zephyr,ipc = &ipm0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_appcpu_partition; + }; +}; + +&trng0 { + status = "okay"; +}; + +&ipm0 { + status = "okay"; +}; diff --git a/boards/lilygo/ttgo_t8s3/ttgo_t8s3_appcpu.yaml b/boards/lilygo/ttgo_t8s3/ttgo_t8s3_appcpu.yaml new file mode 100644 index 00000000000..c64689ec4f7 --- /dev/null +++ b/boards/lilygo/ttgo_t8s3/ttgo_t8s3_appcpu.yaml @@ -0,0 +1,27 @@ +identifier: ttgo_t8s3/esp32s3/appcpu +name: TTGO T8S3 APPCPU +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - uart +testing: + ignore_tags: + - net + - bluetooth + - flash + - cpp + - posix + - watchdog + - logging + - kernel + - pm + - gpio + - crypto + - eeprom + - heap + - cmsis_rtos + - jwt + - zdsp +vendor: lilygo diff --git a/boards/lilygo/ttgo_t8s3/ttgo_t8s3_appcpu_defconfig b/boards/lilygo/ttgo_t8s3/ttgo_t8s3_appcpu_defconfig new file mode 100644 index 00000000000..9abf2ff0430 --- /dev/null +++ b/boards/lilygo/ttgo_t8s3/ttgo_t8s3_appcpu_defconfig @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 +CONFIG_CLOCK_CONTROL=y diff --git a/boards/lilygo/ttgo_t8s3/ttgo_t8s3_procpu.dts b/boards/lilygo/ttgo_t8s3/ttgo_t8s3_procpu.dts new file mode 100644 index 00000000000..a034a9cb49a --- /dev/null +++ b/boards/lilygo/ttgo_t8s3/ttgo_t8s3_procpu.dts @@ -0,0 +1,146 @@ +/* + * Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include +#include "ttgo_t8s3-pinctrl.dtsi" +#include +#include +#include + +/ { + model = "TTGO T8S3 PROCPU"; + compatible = "espressif,esp32s3"; + + aliases { + i2c-0 = &i2c0; + watchdog0 = &wdt0; + sdhc0 = &sd0; + uart-0 = &uart0; + sw0 = &button0; + }; + + chosen { + zephyr,sram = &sram0; + /* console can be UART or USB CDC */ + /* zephyr,console = &uart0; */ + /* zephyr,shell-uart = &uart0; */ + zephyr,console = &usb_serial; + zephyr,shell-uart = &usb_serial; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + zephyr,bt-hci = &esp32_bt_hci; + }; + + buttons { + compatible = "gpio-keys"; + button0: button_0 { + gpios = <&gpio0 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "BOOT Button"; + zephyr,code = ; + }; + }; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&touch { + debounce-interval-ms = <30>; + href-microvolt = <2700000>; + lref-microvolt = <500000>; + href-atten-microvolt = <1000000>; + filter-mode = ; + filter-debounce-cnt = <1>; + filter-noise-thr = ; + filter-jitter-step = <4>; + filter-smooth-level = ; +}; + +&i2c0 { + clock-frequency = ; + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; +}; + +&spi2 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim2_default>; + pinctrl-names = "default"; + /* dma-enabled; TODO */ + clock-frequency = <20000000>; + cs-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; + sd0: sd@0 { + compatible = "zephyr,sdhc-spi-slot"; + reg = <0>; + status = "okay"; + spi-max-frequency = <20000000>; + mmc { + compatible = "zephyr,sdmmc-disk"; + disk-name = "SD"; + status = "okay"; + }; + }; +}; + +&spi3 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim3_default>; + pinctrl-names = "default"; +}; + +&twai { + pinctrl-0 = <&twai_default>; + pinctrl-names = "default"; +}; + +&usb_serial { + status = "okay"; +}; + +&timer0 { + status = "okay"; +}; + +&timer1 { + status = "okay"; +}; + +&timer2 { + status = "okay"; +}; + +&timer3 { + status = "okay"; +}; + +&wdt0 { + status = "okay"; +}; + +&trng0 { + status = "okay"; +}; + +&esp32_bt_hci { + status = "okay"; +}; diff --git a/boards/lilygo/ttgo_t8s3/ttgo_t8s3_procpu.yaml b/boards/lilygo/ttgo_t8s3/ttgo_t8s3_procpu.yaml new file mode 100644 index 00000000000..cc1b652145a --- /dev/null +++ b/boards/lilygo/ttgo_t8s3/ttgo_t8s3_procpu.yaml @@ -0,0 +1,21 @@ +identifier: ttgo_t8s3/esp32s3/procpu +name: TTGO T8S3 PROCPU +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - gpio + - uart + - i2c + - i2s + - spi + - can + - counter + - watchdog + - entropy + - pwm + - dma + - input + - video +vendor: lilygo diff --git a/boards/lilygo/ttgo_t8s3/ttgo_t8s3_procpu_defconfig b/boards/lilygo/ttgo_t8s3/ttgo_t8s3_procpu_defconfig new file mode 100644 index 00000000000..723de34c471 --- /dev/null +++ b/boards/lilygo/ttgo_t8s3/ttgo_t8s3_procpu_defconfig @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_GPIO=y +CONFIG_CLOCK_CONTROL=y diff --git a/boards/luatos/esp32c3_luatos_core/Kconfig b/boards/luatos/esp32c3_luatos_core/Kconfig new file mode 100644 index 00000000000..c6a99b1032d --- /dev/null +++ b/boards/luatos/esp32c3_luatos_core/Kconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 4096 diff --git a/boards/luatos/esp32c3_luatos_core/Kconfig.defconfig b/boards/luatos/esp32c3_luatos_core/Kconfig.defconfig deleted file mode 100644 index f6ad1adaa1c..00000000000 --- a/boards/luatos/esp32c3_luatos_core/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# ESP32C3 core board configuration - -# Copyright (c) 2023 YuLong Yao -# SPDX-License-Identifier: Apache-2.0 - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 65535 if WIFI && BT - default 51200 if WIFI - default 40960 if BT - default 4096 diff --git a/boards/luatos/esp32c3_luatos_core/doc/index.rst b/boards/luatos/esp32c3_luatos_core/doc/index.rst index 2e0d5ed56b2..02df6687cb3 100644 --- a/boards/luatos/esp32c3_luatos_core/doc/index.rst +++ b/boards/luatos/esp32c3_luatos_core/doc/index.rst @@ -256,6 +256,8 @@ You can debug an application in the usual way. Here is an example for the :zephy References ********** +.. target-notes:: + .. [1] https://www.espressif.com/en/products/socs/esp32-c3 .. _ESP32C3 Core Website: https://wiki.luatos.com/chips/esp32c3/board.html .. _ESP32C3 Technical Reference Manual: https://espressif.com/sites/default/files/documentation/esp32-c3_technical_reference_manual_en.pdf diff --git a/boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core.dts b/boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core.dts index cfdfd771d13..5f6aadc9ce1 100644 --- a/boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core.dts +++ b/boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core.dts @@ -10,7 +10,7 @@ / { chosen { - zephyr,sram = &sram0; + zephyr,sram = &sram1; zephyr,console = &uart0; zephyr,shell-uart = &uart0; zephyr,flash = &flash0; diff --git a/boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core.dtsi b/boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core.dtsi index c7b5b627547..f000b61f316 100644 --- a/boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core.dtsi +++ b/boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core.dtsi @@ -7,6 +7,7 @@ #include #include "esp32c3_luatos_core-pinctrl.dtsi" #include +#include / { model = "ESP32C3 Luatos Core"; @@ -92,45 +93,6 @@ pinctrl-names = "default"; }; -&flash0 { - status = "okay"; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Reserve 60kB for the bootloader */ - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x0000F000>; - read-only; - }; - - /* Reserve 1024kB for the application in slot 0 */ - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 0x00100000>; - }; - - /* Reserve 1024kB for the application in slot 1 */ - slot1_partition: partition@110000 { - label = "image-1"; - reg = <0x00110000 0x00100000>; - }; - - /* Reserve 256kB for the scratch partition */ - scratch_partition: partition@210000 { - label = "image-scratch"; - reg = <0x00210000 0x00040000>; - }; - - storage_partition: partition@250000 { - label = "storage"; - reg = <0x00250000 0x00006000>; - }; - }; -}; - &esp32_bt_hci { status = "okay"; }; diff --git a/boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core.yaml b/boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core.yaml index 5baefb918a2..5ba64d712dd 100644 --- a/boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core.yaml +++ b/boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core.yaml @@ -15,8 +15,4 @@ supported: - spi - counter - entropy -testing: - ignore_tags: - - net - - bluetooth vendor: luatos diff --git a/boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core_esp32c3_usb.dts b/boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core_esp32c3_usb.dts index f7e99f9b776..b029ef42ed4 100644 --- a/boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core_esp32c3_usb.dts +++ b/boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core_esp32c3_usb.dts @@ -10,7 +10,7 @@ / { chosen { - zephyr,sram = &sram0; + zephyr,sram = &sram1; zephyr,console = &usb_serial; zephyr,shell-uart = &usb_serial; zephyr,flash = &flash0; diff --git a/boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core_esp32c3_usb.yaml b/boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core_esp32c3_usb.yaml index 7910c6ac8ee..ca0982c4111 100644 --- a/boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core_esp32c3_usb.yaml +++ b/boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core_esp32c3_usb.yaml @@ -15,8 +15,4 @@ supported: - spi - counter - entropy -testing: - ignore_tags: - - net - - bluetooth vendor: luatos diff --git a/boards/luatos/esp32s3_luatos_core/Kconfig b/boards/luatos/esp32s3_luatos_core/Kconfig new file mode 100644 index 00000000000..a4565c096ca --- /dev/null +++ b/boards/luatos/esp32s3_luatos_core/Kconfig @@ -0,0 +1,7 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 4096 if BOARD_ESP32S3_LUATOS_CORE_ESP32S3_PROCPU || BOARD_ESP32S3_LUATOS_CORE_ESP32S3_PROCPU_USB + default 256 if BOARD_ESP32S3_LUATOS_CORE_ESP32S3_APPCPU || BOARD_ESP32S3_LUATOS_CORE_ESP32S3_APPCPU_USB diff --git a/boards/luatos/esp32s3_luatos_core/Kconfig.defconfig b/boards/luatos/esp32s3_luatos_core/Kconfig.defconfig deleted file mode 100644 index a14482e325d..00000000000 --- a/boards/luatos/esp32s3_luatos_core/Kconfig.defconfig +++ /dev/null @@ -1,22 +0,0 @@ -# ESP32S3 Core board configuration - -# Copyright (c) 2023 YuLong Yao -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_ESP32S3_LUATOS_CORE_ESP32S3_PROCPU || BOARD_ESP32S3_LUATOS_CORE_ESP32S3_PROCPU_USB - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 65535 if WIFI && BT - default 51200 if WIFI - default 40960 if BT - default 4096 - -endif # BOARD_ESP32S3_LUATOS_CORE_ESP32S3_PROCPU || BOARD_ESP32S3_LUATOS_CORE_ESP32S3_PROCPU_USB - -if BOARD_ESP32S3_LUATOS_CORE_ESP32S3_APPCPU || BOARD_ESP32S3_LUATOS_CORE_ESP32S3_APPCPU_USB - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - default 256 - -endif # BOARD_ESP32S3_LUATOS_CORE_ESP32S3_APPCPU || BOARD_ESP32S3_LUATOS_CORE_ESP32S3_APPCPU_USB diff --git a/boards/luatos/esp32s3_luatos_core/doc/index.rst b/boards/luatos/esp32s3_luatos_core/doc/index.rst index 7aa43102069..c8e3f74375f 100644 --- a/boards/luatos/esp32s3_luatos_core/doc/index.rst +++ b/boards/luatos/esp32s3_luatos_core/doc/index.rst @@ -286,6 +286,8 @@ You can debug an application in the usual way. Here is an example for the :zephy References ********** +.. target-notes:: + .. _`ESP32S3-Luatos-Core`: https://wiki.luatos.com/chips/esp32s3/board.html .. _`ESP32-S3 Datasheet`: https://www.espressif.com/sites/default/files/documentation/esp32-s3-mini-1_mini-1u_datasheet_en.pdf .. _`ESP32-S3 Technical Reference Manual`: https://www.espressif.com/sites/default/files/documentation/esp32-s3_technical_reference_manual_en.pdf diff --git a/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core.dtsi b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core.dtsi index 60365fdcd65..43ee4b45264 100644 --- a/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core.dtsi +++ b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core.dtsi @@ -7,6 +7,7 @@ #include #include "esp32s3_luatos_core-pinctrl.dtsi" #include +#include / { leds { @@ -103,45 +104,6 @@ status = "okay"; }; -&flash0 { - status = "okay"; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Reserve 64kB for the bootloader */ - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x00010000>; - read-only; - }; - - /* Reserve 1024kB for the application in slot 0 */ - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 0x00100000>; - }; - - /* Reserve 1024kB for the application in slot 1 */ - slot1_partition: partition@110000 { - label = "image-1"; - reg = <0x00110000 0x00100000>; - }; - - /* Reserve 256kB for the scratch partition */ - scratch_partition: partition@210000 { - label = "image-scratch"; - reg = <0x00210000 0x00040000>; - }; - - storage_partition: partition@250000 { - label = "storage"; - reg = <0x00250000 0x00006000>; - }; - }; -}; - &esp32_bt_hci { status = "okay"; }; diff --git a/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_appcpu.dts b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_appcpu.dts index 510e587925e..e302416886a 100644 --- a/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_appcpu.dts +++ b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_appcpu.dts @@ -5,15 +5,19 @@ */ /dts-v1/; -#include +#include +#include + / { model = "ESP32S3 Luatos Core APPCPU"; compatible = "espressif,esp32s3"; chosen { - zephyr,sram = &sram0; + zephyr,sram = &sram1; zephyr,ipc_shm = &shm0; zephyr,ipc = &ipm0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_appcpu_partition; }; }; @@ -24,42 +28,3 @@ &ipm0 { status = "okay"; }; - -&flash0 { - status = "okay"; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Reserve 64kB for the bootloader */ - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x00010000>; - read-only; - }; - - /* Reserve 1024kB for the application in slot 0 */ - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 0x00100000>; - }; - - /* Reserve 1024kB for the application in slot 1 */ - slot1_partition: partition@110000 { - label = "image-1"; - reg = <0x00110000 0x00100000>; - }; - - /* Reserve 256kB for the scratch partition */ - scratch_partition: partition@210000 { - label = "image-scratch"; - reg = <0x00210000 0x00040000>; - }; - - storage_partition: partition@250000 { - label = "storage"; - reg = <0x00250000 0x00006000>; - }; - }; -}; diff --git a/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_appcpu_usb.dts b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_appcpu_usb.dts index b36963af013..eee5d310b69 100644 --- a/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_appcpu_usb.dts +++ b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_appcpu_usb.dts @@ -5,15 +5,19 @@ */ /dts-v1/; -#include +#include +#include + / { model = "ESP32S3 Luatos Core USB APPCPU"; compatible = "espressif,esp32s3"; chosen { - zephyr,sram = &sram0; + zephyr,sram = &sram1; zephyr,ipc_shm = &shm0; zephyr,ipc = &ipm0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_appcpu_partition; }; }; @@ -24,42 +28,3 @@ &ipm0 { status = "okay"; }; - -&flash0 { - status = "okay"; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Reserve 64kB for the bootloader */ - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x00010000>; - read-only; - }; - - /* Reserve 1024kB for the application in slot 0 */ - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 0x00100000>; - }; - - /* Reserve 1024kB for the application in slot 1 */ - slot1_partition: partition@110000 { - label = "image-1"; - reg = <0x00110000 0x00100000>; - }; - - /* Reserve 256kB for the scratch partition */ - scratch_partition: partition@210000 { - label = "image-scratch"; - reg = <0x00210000 0x00040000>; - }; - - storage_partition: partition@250000 { - label = "storage"; - reg = <0x00250000 0x00006000>; - }; - }; -}; diff --git a/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_procpu.dts b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_procpu.dts index 2a04d568066..0b7973b8810 100644 --- a/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_procpu.dts +++ b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_procpu.dts @@ -21,7 +21,7 @@ }; chosen { - zephyr,sram = &sram0; + zephyr,sram = &sram1; zephyr,console = &uart0; zephyr,shell-uart = &uart0; zephyr,flash = &flash0; diff --git a/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_procpu.yaml b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_procpu.yaml index 6d564843a1c..369a2fc7b63 100644 --- a/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_procpu.yaml +++ b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_procpu.yaml @@ -15,8 +15,4 @@ supported: - entropy - pwm - dma -testing: - ignore_tags: - - net - - bluetooth vendor: luatos diff --git a/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_procpu_usb.dts b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_procpu_usb.dts index a4182a4ba80..0d7d8c6ae8a 100644 --- a/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_procpu_usb.dts +++ b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_procpu_usb.dts @@ -21,7 +21,7 @@ }; chosen { - zephyr,sram = &sram0; + zephyr,sram = &sram1; zephyr,console = &usb_serial; zephyr,shell-uart = &usb_serial; zephyr,flash = &flash0; diff --git a/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_procpu_usb.yaml b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_procpu_usb.yaml index 7e160d68117..fe4e1ad61dd 100644 --- a/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_procpu_usb.yaml +++ b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_procpu_usb.yaml @@ -15,8 +15,4 @@ supported: - entropy - pwm - dma -testing: - ignore_tags: - - net - - bluetooth vendor: luatos diff --git a/boards/m5stack/m5stack_atom_lite/Kconfig b/boards/m5stack/m5stack_atom_lite/Kconfig new file mode 100644 index 00000000000..5afa40f9dd4 --- /dev/null +++ b/boards/m5stack/m5stack_atom_lite/Kconfig @@ -0,0 +1,7 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 4096 if BOARD_M5STACK_ATOM_LITE_ESP32_PROCPU + default 256 if BOARD_M5STACK_ATOM_LITE_ESP32_APPCPU diff --git a/boards/m5stack/m5stack_atom_lite/Kconfig.defconfig b/boards/m5stack/m5stack_atom_lite/Kconfig.defconfig deleted file mode 100644 index 2b223f5409b..00000000000 --- a/boards/m5stack/m5stack_atom_lite/Kconfig.defconfig +++ /dev/null @@ -1,22 +0,0 @@ -# M5Stack ATOM Lite board configuration -# Copyright (c) 2023 Benjamin Cabé -# Copyright (c) 2022 AVSystem Sławomir Wolf Sp.j. (AVSystem) -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_M5STACK_ATOM_LITE_ESP32_PROCPU - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 65535 if WIFI && BT - default 51200 if WIFI - default 40960 if BT - default 4096 - -endif # BOARD_M5STACK_ATOM_LITE_ESP32_PROCPU - -if BOARD_M5STACK_ATOM_LITE_ESP32_APPCPU - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - default 256 - -endif # BOARD_M5STACK_ATOM_LITE_ESP32_APPCPU diff --git a/boards/m5stack/m5stack_atom_lite/doc/index.rst b/boards/m5stack/m5stack_atom_lite/doc/index.rst index 6a47c4a7f32..87e56a23677 100644 --- a/boards/m5stack/m5stack_atom_lite/doc/index.rst +++ b/boards/m5stack/m5stack_atom_lite/doc/index.rst @@ -1,7 +1,4 @@ -.. _m5stack_atom_lite: - -M5Stack ATOM Lite -################# +.. zephyr:board:: m5stack_atom_lite Overview ******** @@ -16,14 +13,6 @@ It features the following integrated components: - Infrared LED - 1x Grove extension port - -.. figure:: img/m5stack_atom_lite.webp - :align: center - :alt: M5Stack ATOM Lite - - M5Stack ATOM Lite - - Supported Features ================== diff --git a/boards/m5stack/m5stack_atom_lite/m5stack_atom_lite_appcpu.dts b/boards/m5stack/m5stack_atom_lite/m5stack_atom_lite_appcpu.dts index f5db6e76116..3262496f254 100644 --- a/boards/m5stack/m5stack_atom_lite/m5stack_atom_lite_appcpu.dts +++ b/boards/m5stack/m5stack_atom_lite/m5stack_atom_lite_appcpu.dts @@ -6,15 +6,18 @@ /dts-v1/; #include +#include / { model = "M5Stack Atom Lite APPCPU"; compatible = "espressif,esp32"; chosen { - zephyr,sram = &sram0; + zephyr,sram = &sram1; zephyr,ipc_shm = &shm0; zephyr,ipc = &ipm0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_appcpu_partition; }; }; @@ -25,42 +28,3 @@ &trng0 { status = "okay"; }; - -&flash0 { - status = "okay"; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Reserve 60kB for the bootloader */ - boot_partition: partition@1000 { - label = "mcuboot"; - reg = <0x00001000 0x0000F000>; - read-only; - }; - - /* Reserve 1024kB for the application in slot 0 */ - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 0x00100000>; - }; - - /* Reserve 1024kB for the application in slot 1 */ - slot1_partition: partition@110000 { - label = "image-1"; - reg = <0x00110000 0x00100000>; - }; - - /* Reserve 256kB for the scratch partition */ - scratch_partition: partition@210000 { - label = "image-scratch"; - reg = <0x00210000 0x00040000>; - }; - - storage_partition: partition@250000 { - label = "storage"; - reg = <0x00250000 0x00006000>; - }; - }; -}; diff --git a/boards/m5stack/m5stack_atom_lite/m5stack_atom_lite_procpu.dts b/boards/m5stack/m5stack_atom_lite/m5stack_atom_lite_procpu.dts index 3a8557f6794..012c2b1f8fe 100644 --- a/boards/m5stack/m5stack_atom_lite/m5stack_atom_lite_procpu.dts +++ b/boards/m5stack/m5stack_atom_lite/m5stack_atom_lite_procpu.dts @@ -13,13 +13,14 @@ #include #include #include +#include / { model = "M5Stack ATOM Lite PROCPU"; compatible = "m5stack,m5stack-atom-lite"; chosen { - zephyr,sram = &sram0; + zephyr,sram = &sram1; zephyr,console = &uart0; zephyr,shell-uart = &uart0; zephyr,flash = &flash0; @@ -143,45 +144,6 @@ status = "okay"; }; -&flash0 { - status = "okay"; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Reserve 60kB for the bootloader */ - boot_partition: partition@1000 { - label = "mcuboot"; - reg = <0x00001000 0x0000F000>; - read-only; - }; - - /* Reserve 1024kB for the application in slot 0 */ - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 0x00100000>; - }; - - /* Reserve 1024kB for the application in slot 1 */ - slot1_partition: partition@110000 { - label = "image-1"; - reg = <0x00110000 0x00100000>; - }; - - /* Reserve 256kB for the scratch partition */ - scratch_partition: partition@210000 { - label = "image-scratch"; - reg = <0x00210000 0x00040000>; - }; - - storage_partition: partition@250000 { - label = "storage"; - reg = <0x00250000 0x00006000>; - }; - }; -}; - &esp32_bt_hci { status = "okay"; }; diff --git a/boards/m5stack/m5stack_atom_lite/m5stack_atom_lite_procpu.yaml b/boards/m5stack/m5stack_atom_lite/m5stack_atom_lite_procpu.yaml index 14462ac58f8..04b3ef18716 100644 --- a/boards/m5stack/m5stack_atom_lite/m5stack_atom_lite_procpu.yaml +++ b/boards/m5stack/m5stack_atom_lite/m5stack_atom_lite_procpu.yaml @@ -12,8 +12,4 @@ supported: - uart - pinmux - nvs -testing: - ignore_tags: - - net - - bluetooth vendor: m5stack diff --git a/boards/m5stack/m5stack_atoms3/Kconfig b/boards/m5stack/m5stack_atoms3/Kconfig new file mode 100644 index 00000000000..e52b7a65c6d --- /dev/null +++ b/boards/m5stack/m5stack_atoms3/Kconfig @@ -0,0 +1,7 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 4096 if BOARD_M5STACK_ATOMS3_ESP32S3_PROCPU + default 256 if BOARD_M5STACK_ATOMS3_ESP32S3_APPCPU diff --git a/boards/m5stack/m5stack_atoms3/Kconfig.defconfig b/boards/m5stack/m5stack_atoms3/Kconfig.defconfig index f3b59178417..dcb601b638f 100644 --- a/boards/m5stack/m5stack_atoms3/Kconfig.defconfig +++ b/boards/m5stack/m5stack_atoms3/Kconfig.defconfig @@ -4,21 +4,7 @@ if BOARD_M5STACK_ATOMS3_ESP32S3_PROCPU -config LV_COLOR_16_SWAP +configdefault LV_COLOR_16_SWAP default y if LVGL -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 65535 if WIFI && BT - default 51200 if WIFI - default 40960 if BT - default 4096 - endif # BOARD_M5STACK_ATOMS3_ESP32S3_PROCPU - -if BOARD_M5STACK_ATOMS3_ESP32S3_APPCPU - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - default 256 - -endif # BOARD_M5STACK_ATOMS3_ESP32S3_APPCPU diff --git a/boards/m5stack/m5stack_atoms3/doc/index.rst b/boards/m5stack/m5stack_atoms3/doc/index.rst index 69bff1ee0cf..1b863cb08be 100644 --- a/boards/m5stack/m5stack_atoms3/doc/index.rst +++ b/boards/m5stack/m5stack_atoms3/doc/index.rst @@ -1,7 +1,4 @@ -.. _m5stack_atoms3: - -M5Stack AtomS3 -############## +.. zephyr:board:: m5stack_atoms3 Overview ******** @@ -18,14 +15,6 @@ It features the following integrated components: - 6-axis IMU MPU6886 - Infrared emitter - -.. figure:: img/m5stack_atoms3.webp - :align: center - :alt: M5Stack AtomS3 - - M5Stack AtomS3 - - Supported Features ================== diff --git a/boards/m5stack/m5stack_atoms3/m5stack_atoms3_appcpu.dts b/boards/m5stack/m5stack_atoms3/m5stack_atoms3_appcpu.dts index a117ee02922..2bc18ec2048 100644 --- a/boards/m5stack/m5stack_atoms3/m5stack_atoms3_appcpu.dts +++ b/boards/m5stack/m5stack_atoms3/m5stack_atoms3_appcpu.dts @@ -5,15 +5,19 @@ */ /dts-v1/; -#include +#include +#include + / { model = "M5Stack AtomS3 APPCPU"; compatible = "espressif,esp32s3"; chosen { - zephyr,sram = &sram0; + zephyr,sram = &sram1; zephyr,ipc_shm = &shm0; zephyr,ipc = &ipm0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_appcpu_partition; }; }; @@ -24,42 +28,3 @@ &ipm0 { status = "okay"; }; - -&flash0 { - status = "okay"; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Reserve 64kB for the bootloader */ - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x00010000>; - read-only; - }; - - /* Reserve 1024kB for the application in slot 0 */ - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 0x00100000>; - }; - - /* Reserve 1024kB for the application in slot 1 */ - slot1_partition: partition@110000 { - label = "image-1"; - reg = <0x00110000 0x00100000>; - }; - - /* Reserve 256kB for the scratch partition */ - scratch_partition: partition@210000 { - label = "image-scratch"; - reg = <0x00210000 0x00040000>; - }; - - storage_partition: partition@250000 { - label = "storage"; - reg = <0x00250000 0x00006000>; - }; - }; -}; diff --git a/boards/m5stack/m5stack_atoms3/m5stack_atoms3_procpu.dts b/boards/m5stack/m5stack_atoms3/m5stack_atoms3_procpu.dts index dd20fb00a8d..ed963407407 100644 --- a/boards/m5stack/m5stack_atoms3/m5stack_atoms3_procpu.dts +++ b/boards/m5stack/m5stack_atoms3/m5stack_atoms3_procpu.dts @@ -10,13 +10,14 @@ #include "grove_connectors.dtsi" #include #include +#include / { model = "M5Stack AtomS3 PROCPU"; compatible = "m5stack,atoms3"; chosen { - zephyr,sram = &sram0; + zephyr,sram = &sram1; zephyr,console = &usb_serial; zephyr,shell-uart = &usb_serial; zephyr,flash = &flash0; @@ -84,7 +85,7 @@ nvgam-param = [d0 00 02 07 0a 28 31 54 47 0e 1c 17 1b 1e]; ram-param = [00 E0]; rgb-param = [40 02 14]; - mipi-mode = ; + mipi-mode = "MIPI_DBI_MODE_SPI_4WIRE"; }; }; @@ -154,41 +155,6 @@ status = "okay"; }; -&flash0 { - status = "okay"; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x0000F000>; - read-only; - }; - - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 0x00100000>; - }; - - slot1_partition: partition@110000 { - label = "image-1"; - reg = <0x00110000 0x00100000>; - }; - - scratch_partition: partition@210000 { - label = "image-scratch"; - reg = <0x00210000 0x00040000>; - }; - - storage_partition: partition@250000 { - label = "storage"; - reg = <0x00250000 0x00006000>; - }; - }; -}; - &esp32_bt_hci { status = "okay"; }; diff --git a/boards/m5stack/m5stack_atoms3/m5stack_atoms3_procpu.yaml b/boards/m5stack/m5stack_atoms3/m5stack_atoms3_procpu.yaml index 082aa4e5699..8fe5983e19c 100644 --- a/boards/m5stack/m5stack_atoms3/m5stack_atoms3_procpu.yaml +++ b/boards/m5stack/m5stack_atoms3/m5stack_atoms3_procpu.yaml @@ -14,8 +14,4 @@ supported: - pinmux - nvs - display -testing: - ignore_tags: - - net - - bluetooth vendor: m5stack diff --git a/boards/m5stack/m5stack_atoms3_lite/Kconfig b/boards/m5stack/m5stack_atoms3_lite/Kconfig new file mode 100644 index 00000000000..acb26cf799c --- /dev/null +++ b/boards/m5stack/m5stack_atoms3_lite/Kconfig @@ -0,0 +1,7 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 4096 if BOARD_M5STACK_ATOMS3_LITE_ESP32S3_PROCPU + default 256 if BOARD_M5STACK_ATOMS3_LITE_ESP32S3_APPCPU diff --git a/boards/m5stack/m5stack_atoms3_lite/Kconfig.defconfig b/boards/m5stack/m5stack_atoms3_lite/Kconfig.defconfig index f0f262cd1f3..6934b4e9a4e 100644 --- a/boards/m5stack/m5stack_atoms3_lite/Kconfig.defconfig +++ b/boards/m5stack/m5stack_atoms3_lite/Kconfig.defconfig @@ -4,21 +4,7 @@ if BOARD_M5STACK_ATOMS3_LITE_ESP32S3_PROCPU -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 65535 if WIFI && BT - default 51200 if WIFI - default 40960 if BT - default 4096 - config KERNEL_MEM_POOL default y endif # BOARD_M5STACK_ATOMS3_LITE_ESP32S3_PROCPU - -if BOARD_M5STACK_ATOMS3_LITE_ESP32S3_APPCPU - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - default 256 - -endif # BOARD_M5STACK_ATOMS3_LITE_ESP32S3_APPCPU diff --git a/boards/m5stack/m5stack_atoms3_lite/doc/index.rst b/boards/m5stack/m5stack_atoms3_lite/doc/index.rst index ffbe8f1cb05..23af62d96e6 100644 --- a/boards/m5stack/m5stack_atoms3_lite/doc/index.rst +++ b/boards/m5stack/m5stack_atoms3_lite/doc/index.rst @@ -1,7 +1,4 @@ -.. _m5stack_atoms3_lite: - -M5Stack AtomS3 Lite -################### +.. zephyr:board:: m5stack_atoms3_lite Overview ******** @@ -16,14 +13,6 @@ It features the following integrated components: - 8MB of Flash - RGB Status-LED - -.. figure:: img/m5stack_atoms3_lite.webp - :align: center - :alt: M5Stack AtomS3 Lite - - M5Stack AtomS3 Lite - - Supported Features ================== diff --git a/boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_appcpu.dts b/boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_appcpu.dts index 2323548e7fc..0385c9e39a3 100644 --- a/boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_appcpu.dts +++ b/boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_appcpu.dts @@ -5,15 +5,19 @@ */ /dts-v1/; -#include +#include +#include + / { model = "M5Stack AtomS3 Lite APPCPU"; compatible = "espressif,esp32s3"; chosen { - zephyr,sram = &sram0; + zephyr,sram = &sram1; zephyr,ipc_shm = &shm0; zephyr,ipc = &ipm0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_appcpu_partition; }; }; @@ -24,42 +28,3 @@ &ipm0 { status = "okay"; }; - -&flash0 { - status = "okay"; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Reserve 64kB for the bootloader */ - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x00010000>; - read-only; - }; - - /* Reserve 1024kB for the application in slot 0 */ - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 0x00100000>; - }; - - /* Reserve 1024kB for the application in slot 1 */ - slot1_partition: partition@110000 { - label = "image-1"; - reg = <0x00110000 0x00100000>; - }; - - /* Reserve 256kB for the scratch partition */ - scratch_partition: partition@210000 { - label = "image-scratch"; - reg = <0x00210000 0x00040000>; - }; - - storage_partition: partition@250000 { - label = "storage"; - reg = <0x00250000 0x00006000>; - }; - }; -}; diff --git a/boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_procpu.dts b/boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_procpu.dts index 166ee2014ca..c5884a846a1 100644 --- a/boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_procpu.dts +++ b/boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_procpu.dts @@ -11,13 +11,14 @@ #include #include #include +#include / { model = "M5Stack AtomS3 Lite PROCPU"; compatible = "m5stack,atoms3_lite"; chosen { - zephyr,sram = &sram0; + zephyr,sram = &sram1; zephyr,console = &usb_serial; zephyr,shell-uart = &usb_serial; zephyr,flash = &flash0; @@ -46,6 +47,7 @@ &usb_serial { status = "okay"; }; + &uart0 { status = "okay"; current-speed = <115200>; @@ -112,41 +114,6 @@ status = "okay"; }; -&flash0 { - status = "okay"; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x0000F000>; - read-only; - }; - - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 0x00100000>; - }; - - slot1_partition: partition@110000 { - label = "image-1"; - reg = <0x00110000 0x00100000>; - }; - - scratch_partition: partition@210000 { - label = "image-scratch"; - reg = <0x00210000 0x00040000>; - }; - - storage_partition: partition@250000 { - label = "storage"; - reg = <0x00250000 0x00006000>; - }; - }; -}; - &esp32_bt_hci { status = "okay"; }; diff --git a/boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_procpu.yaml b/boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_procpu.yaml index 996732bc3dd..34420d21d60 100644 --- a/boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_procpu.yaml +++ b/boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_procpu.yaml @@ -16,8 +16,4 @@ supported: - pinmux - nvs - dma -testing: - ignore_tags: - - net - - bluetooth vendor: m5stack diff --git a/boards/m5stack/m5stack_core2/Kconfig b/boards/m5stack/m5stack_core2/Kconfig new file mode 100644 index 00000000000..30f3630e07f --- /dev/null +++ b/boards/m5stack/m5stack_core2/Kconfig @@ -0,0 +1,7 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 4096 if BOARD_M5STACK_CORE2_ESP32_PROCPU + default 256 if BOARD_M5STACK_CORE2_ESP32_APPCPU diff --git a/boards/m5stack/m5stack_core2/Kconfig.defconfig b/boards/m5stack/m5stack_core2/Kconfig.defconfig index fd9614d6cbb..155a3c1d39c 100644 --- a/boards/m5stack/m5stack_core2/Kconfig.defconfig +++ b/boards/m5stack/m5stack_core2/Kconfig.defconfig @@ -5,13 +5,6 @@ if BOARD_M5STACK_CORE2_ESP32_PROCPU -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 65535 if WIFI && BT - default 51200 if WIFI - default 65536 if BT - default 4096 - config KERNEL_MEM_POOL default y @@ -36,7 +29,7 @@ config INPUT_FT5336_INTERRUPT config INPUT default y -config LV_COLOR_16_SWAP +configdefault LV_COLOR_16_SWAP default y if LVGL # Increase initialization priority of MIPI DBI device, so that it initializes @@ -49,10 +42,3 @@ config MIPI_DBI_INIT_PRIORITY endif # MIPI_DBI endif # BOARD_M5STACK_CORE2_ESP32_PROCPU - -if BOARD_M5STACK_CORE2_ESP32_APPCPU - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - default 256 - -endif # BOARD_M5STACK_CORE2_ESP32_APPCPU diff --git a/boards/m5stack/m5stack_core2/doc/index.rst b/boards/m5stack/m5stack_core2/doc/index.rst index 02ba5fa7249..9855ef1de59 100644 --- a/boards/m5stack/m5stack_core2/doc/index.rst +++ b/boards/m5stack/m5stack_core2/doc/index.rst @@ -1,7 +1,4 @@ -.. _m5stack_core2: - -M5Stack Core2 -############# +.. zephyr:board:: m5stack_core2 Overview ******** @@ -26,13 +23,6 @@ M5Stack Core2 features the following integrated components: - MIC SPM1423 - Battery 390mAh 3,7V -.. figure:: img/m5stack_core2.webp - :align: center - :alt: M5Stack-Core2 - :width: 400 px - - M5Stack-Core2 module - Functional Description ********************** diff --git a/boards/m5stack/m5stack_core2/m5stack_core2_appcpu.dts b/boards/m5stack/m5stack_core2/m5stack_core2_appcpu.dts index 875d0eaea2a..4f7258310b7 100644 --- a/boards/m5stack/m5stack_core2/m5stack_core2_appcpu.dts +++ b/boards/m5stack/m5stack_core2/m5stack_core2_appcpu.dts @@ -6,15 +6,18 @@ /dts-v1/; #include +#include / { model = "M5Stack Core2 APPCPU"; compatible = "espressif,esp32"; chosen { - zephyr,sram = &sram0; + zephyr,sram = &sram1; zephyr,ipc_shm = &shm0; zephyr,ipc = &ipm0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_appcpu_partition; }; }; @@ -25,42 +28,3 @@ &trng0 { status = "okay"; }; - -&flash0 { - status = "okay"; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Reserve 60kB for the bootloader */ - boot_partition: partition@1000 { - label = "mcuboot"; - reg = <0x00001000 0x0000F000>; - read-only; - }; - - /* Reserve 1024kB for the application in slot 0 */ - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 0x00100000>; - }; - - /* Reserve 1024kB for the application in slot 1 */ - slot1_partition: partition@110000 { - label = "image-1"; - reg = <0x00110000 0x00100000>; - }; - - /* Reserve 256kB for the scratch partition */ - scratch_partition: partition@210000 { - label = "image-scratch"; - reg = <0x00210000 0x00040000>; - }; - - storage_partition: partition@250000 { - label = "storage"; - reg = <0x00250000 0x00006000>; - }; - }; -}; diff --git a/boards/m5stack/m5stack_core2/m5stack_core2_procpu.dts b/boards/m5stack/m5stack_core2/m5stack_core2_procpu.dts index 841dcdf38be..554e1885488 100644 --- a/boards/m5stack/m5stack_core2/m5stack_core2_procpu.dts +++ b/boards/m5stack/m5stack_core2/m5stack_core2_procpu.dts @@ -11,6 +11,7 @@ #include "m5stack_mbus_connectors.dtsi" #include #include +#include / { model = "M5Stack Core2 PROCPU"; @@ -27,7 +28,7 @@ }; chosen { - zephyr,sram = &sram0; + zephyr,sram = &sram1; zephyr,console = &uart0; zephyr,shell-uart = &uart0; zephyr,flash = &flash0; @@ -35,6 +36,7 @@ zephyr,code-partition = &slot0_partition; zephyr,rtc = &pfc8563_rtc; zephyr,bt-hci = &esp32_bt_hci; + zephyr,touch = &ft5336_touch; }; leds { @@ -72,6 +74,16 @@ rotation = <0>; }; }; + + bus_5v: bus_5v { + compatible = "regulator-fixed"; + regulator-name = "bus_5v"; + enable-gpios = <&axp192_gpio 5 GPIO_ACTIVE_HIGH>; + }; +}; + +&flash0 { + reg = <0x0 DT_SIZE_M(16)>; }; &psram0 { @@ -176,12 +188,6 @@ }; }; - bus_5v: bus_5v { - compatible = "regulator-fixed"; - regulator-name = "bus_5v"; - enable-gpios = <&axp192_gpio 5 GPIO_ACTIVE_HIGH>; - }; - ft5336_touch: ft5336@38 { compatible = "focaltech,ft5336"; reg = <0x38>; @@ -216,6 +222,7 @@ spi-max-frequency = <20000000>; mmc { compatible = "zephyr,sdmmc-disk"; + disk-name = "SD"; status = "okay"; }; @@ -243,48 +250,6 @@ status = "okay"; }; -&flash0 { - status = "okay"; - reg = <0 DT_SIZE_M(16)>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Reserve 60kB for the bootloader */ - boot_partition: partition@1000 { - label = "mcuboot"; - reg = <0x00001000 0x0000F000>; - read-only; - }; - - /* Reserve 1024kB for the application in slot 0 */ - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 0x00100000>; - }; - - /* Reserve 1024kB for the application in slot 1 */ - slot1_partition: partition@110000 { - label = "image-1"; - reg = <0x00110000 0x00100000>; - }; - - /* Reserve 256kB for the scratch partition */ - scratch_partition: partition@210000 { - label = "image-scratch"; - reg = <0x00210000 0x00040000>; - }; - - /* 14MB storage */ - storage_partition: partition@250000 { - label = "storage"; - reg = <0x00250000 0x00db0000>; - }; - }; -}; - &esp32_bt_hci { status = "okay"; }; diff --git a/boards/m5stack/m5stack_core2/m5stack_core2_procpu.yaml b/boards/m5stack/m5stack_core2/m5stack_core2_procpu.yaml index 5a95351e16d..5e7edaca6fe 100644 --- a/boards/m5stack/m5stack_core2/m5stack_core2_procpu.yaml +++ b/boards/m5stack/m5stack_core2/m5stack_core2_procpu.yaml @@ -13,8 +13,4 @@ supported: - uart - pinmux - nvs -testing: - ignore_tags: - - net - - bluetooth vendor: m5stack diff --git a/boards/m5stack/m5stack_cores3/Kconfig b/boards/m5stack/m5stack_cores3/Kconfig new file mode 100644 index 00000000000..8cef5ae03ed --- /dev/null +++ b/boards/m5stack/m5stack_cores3/Kconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Zhang Xingtao +# SPDX-License-Identifier: Apache-2.0 + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 4096 if BOARD_M5STACK_CORES3_ESP32S3_PROCPU || \ + BOARD_M5STACK_CORES3_ESP32S3_PROCPU_SE + default 256 if BOARD_M5STACK_CORES3_ESP32S3_APPCPU diff --git a/boards/m5stack/m5stack_cores3/Kconfig.defconfig b/boards/m5stack/m5stack_cores3/Kconfig.defconfig new file mode 100644 index 00000000000..b31bac7c90a --- /dev/null +++ b/boards/m5stack/m5stack_cores3/Kconfig.defconfig @@ -0,0 +1,14 @@ +# M5Stack CoreS3 board defconfig + +# Copyright (c) 2024 TOKITA Hiroshi +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_M5STACK_CORES3_ESP32S3_PROCPU || BOARD_M5STACK_CORES3_ESP32S3_PROCPU_SE + +config INPUT_FT5336_INTERRUPT + default y if INPUT + +config INPUT + default y + +endif # BOARD_M5STACK_CORES3_ESP32S3_PROCPU || BOARD_M5STACK_CORES3_ESP32S3_PROCPU_SE diff --git a/boards/m5stack/m5stack_cores3/Kconfig.m5stack_cores3 b/boards/m5stack/m5stack_cores3/Kconfig.m5stack_cores3 new file mode 100644 index 00000000000..59a59123417 --- /dev/null +++ b/boards/m5stack/m5stack_cores3/Kconfig.m5stack_cores3 @@ -0,0 +1,10 @@ +# M5Stack CoreS3 board configuration + +# Copyright (c) 2024 Zhang Xingtao +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_M5STACK_CORES3 + select SOC_ESP32S3 + select SOC_ESP32S3_PROCPU if BOARD_M5STACK_CORES3_ESP32S3_PROCPU || \ + BOARD_M5STACK_CORES3_ESP32S3_PROCPU_SE + select SOC_ESP32S3_APPCPU if BOARD_M5STACK_CORES3_ESP32S3_APPCPU diff --git a/boards/m5stack/m5stack_cores3/Kconfig.sysbuild b/boards/m5stack/m5stack_cores3/Kconfig.sysbuild new file mode 100644 index 00000000000..3a2d17ac5cf --- /dev/null +++ b/boards/m5stack/m5stack_cores3/Kconfig.sysbuild @@ -0,0 +1,10 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +choice BOOTLOADER + default BOOTLOADER_MCUBOOT +endchoice + +choice BOOT_SIGNATURE_TYPE + default BOOT_SIGNATURE_TYPE_NONE +endchoice diff --git a/boards/m5stack/m5stack_cores3/board.cmake b/boards/m5stack/m5stack_cores3/board.cmake new file mode 100644 index 00000000000..2f04d1fe886 --- /dev/null +++ b/boards/m5stack/m5stack_cores3/board.cmake @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +if(NOT "${OPENOCD}" MATCHES "^${ESPRESSIF_TOOLCHAIN_PATH}/.*") + set(OPENOCD OPENOCD-NOTFOUND) +endif() +find_program(OPENOCD openocd PATHS ${ESPRESSIF_TOOLCHAIN_PATH}/openocd-esp32/bin NO_DEFAULT_PATH) + +include(${ZEPHYR_BASE}/boards/common/esp32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/m5stack/m5stack_cores3/board.yml b/boards/m5stack/m5stack_cores3/board.yml new file mode 100644 index 00000000000..765c6b9eba2 --- /dev/null +++ b/boards/m5stack/m5stack_cores3/board.yml @@ -0,0 +1,9 @@ +board: + name: m5stack_cores3 + full_name: CoreS3 + vendor: m5stack + socs: + - name: esp32s3 + variants: + - name: se + cpucluster: procpu diff --git a/boards/m5stack/m5stack_cores3/doc/img/m5stack_cores3.webp b/boards/m5stack/m5stack_cores3/doc/img/m5stack_cores3.webp new file mode 100644 index 00000000000..37ee8f6b8ee Binary files /dev/null and b/boards/m5stack/m5stack_cores3/doc/img/m5stack_cores3.webp differ diff --git a/boards/m5stack/m5stack_cores3/doc/img/m5stack_cores3_se.webp b/boards/m5stack/m5stack_cores3/doc/img/m5stack_cores3_se.webp new file mode 100644 index 00000000000..90e4450a8e7 Binary files /dev/null and b/boards/m5stack/m5stack_cores3/doc/img/m5stack_cores3_se.webp differ diff --git a/boards/m5stack/m5stack_cores3/doc/index.rst b/boards/m5stack/m5stack_cores3/doc/index.rst new file mode 100644 index 00000000000..d9025e3f6d8 --- /dev/null +++ b/boards/m5stack/m5stack_cores3/doc/index.rst @@ -0,0 +1,266 @@ +.. zephyr:board:: m5stack_cores3 + +Overview +******** + +M5Stack CoreS3 is an ESP32-based development board from M5Stack. It is the third generation of the M5Stack Core series. +M5Stack CoreS3 SE is the compact version of CoreS3. It has the same form factor as the original M5Stack, +and some features were reduced from CoreS3. + +M5Stack CoreS3/CoreS3 SE features consist of: + +- ESP32-S3 chip (dual-core Xtensa LX7 processor @240MHz, WIFI, OTG and CDC functions) +- PSRAM 8MB +- Flash 16MB +- LCD ISP 2", 320x240 pixel ILI9342C +- Capacitive multi touch FT6336U +- Speaker 1W AW88298 +- Dual Microphones ES7210 Audio decoder +- RTC BM8563 +- USB-C +- SD-Card slot +- PMIC AXP2101 +- Battery 500mAh 3.7 V (Not available for CoreS3 SE) +- Camera 30W pixel GC0308 (Not available for CoreS3 SE) +- Geomagnetic sensor BMM150 (Not available for CoreS3 SE) +- Proximity sensor LTR-553ALS-WA (Not available for CoreS3 SE) +- 6-Axis IMU BMI270 (Not available for CoreS3 SE) + +Start Application Development +***************************** + +Before powering up your M5Stack CoreS3, please make sure that the board is in good +condition with no obvious signs of damage. + +System requirements +=================== + +Prerequisites +------------- + +Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command +below to retrieve those files. + +.. code-block:: console + + west blobs fetch hal_espressif + +.. note:: + + It is recommended running the command above after :file:`west update`. + +Building & Flashing +******************* + +Simple boot +=========== + +The board could be loaded using the single binary image, without 2nd stage bootloader. +It is the default option when building the application without additional configuration. + +.. note:: + + Simple boot does not provide any security features nor OTA updates. + +MCUboot bootloader +================== + +User may choose to use MCUboot bootloader instead. In that case the bootloader +must be built (and flashed) at least once. + +There are two options to be used when building an application: + +1. Sysbuild +2. Manual build + +.. note:: + + User can select the MCUboot bootloader by adding the following line + to the board default configuration file. + + .. code:: cfg + + CONFIG_BOOTLOADER_MCUBOOT=y + +Sysbuild +======== + +The sysbuild makes possible to build and flash all necessary images needed to +bootstrap the board with the ESP32 SoC. + +To build the sample application using sysbuild use the command: + +.. tabs:: + + .. group-tab:: M5Stack CoreS3 + + .. zephyr-app-commands:: + :tool: west + :zephyr-app: samples/hello_world + :board: m5stack_cores3/esp32s3/procpu + :goals: build + :west-args: --sysbuild + :compact: + + .. group-tab:: M5Stack CoreS3 SE + + .. zephyr-app-commands:: + :tool: west + :zephyr-app: samples/hello_world + :board: m5stack_cores3/esp32s3/procpu/se + :goals: build + :west-args: --sysbuild + :compact: + +By default, the ESP32 sysbuild creates bootloader (MCUboot) and application +images. But it can be configured to create other kind of images. + +Build directory structure created by sysbuild is different from traditional +Zephyr build. Output is structured by the domain subdirectories: + +.. code-block:: + + build/ + ├── hello_world + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + ├── mcuboot + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + └── domains.yaml + +.. note:: + + With ``--sysbuild`` option the bootloader will be re-build and re-flash + every time the pristine build is used. + +For more information about the system build please read the :ref:`sysbuild` documentation. + +Manual build +============ + +During the development cycle, it is intended to build & flash as quickly possible. +For that reason, images can be built one at a time using traditional build. + +The instructions following are relevant for both manual build and sysbuild. +The only difference is the structure of the build directory. + +.. note:: + + Remember that bootloader (MCUboot) needs to be flash at least once. + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +.. tabs:: + + .. group-tab:: M5Stack CoreS3 + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: m5stack_cores3/esp32s3/procpu + :goals: build + + .. group-tab:: M5Stack CoreS3 SE + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: m5stack_cores3/esp32s3/procpu/se + :goals: build + +The usual ``flash`` target will work with the ``m5stack_cores3/esp32s3/procpu`` board +configuration. Here is an example for the :zephyr:code-sample:`hello_world` +application. + +.. tabs:: + + .. group-tab:: M5Stack CoreS3 + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: m5stack_cores3/esp32s3/procpu + :goals: flash + + .. group-tab:: M5Stack CoreS3 SE + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: m5stack_cores3/esp32s3/procpu/se + :goals: flash + +The baud rate of 921600bps is set by default. If experiencing issues when flashing, +try using different values by using ``--esp-baud-rate `` option during +``west flash`` (e.g. ``west flash --esp-baud-rate 115200``). + +You can also open the serial monitor using the following command: + +.. code-block:: shell + + west espressif monitor + +After the board has automatically reset and booted, you should see the following +message in the monitor: + +.. code-block:: console + + *** Booting Zephyr OS build vx.x.x-xxx-gxxxxxxxxxxxx *** + Hello World! m5stack_cores3/esp32s3/procpu + +Debugging +********* + +ESP32-S3 support on OpenOCD is available at `OpenOCD ESP32`_. + +ESP32-S3 has a built-in JTAG circuitry and can be debugged without any additional chip. Only an USB cable connected to the D+/D- pins is necessary. + +Further documentation can be obtained from the SoC vendor in `JTAG debugging for ESP32-S3`_. + +Here is an example for building the :zephyr:code-sample:`hello_world` application. + +.. tabs:: + + .. group-tab:: M5Stack CoreS3 + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: m5stack_cores3/esp32s3/procpu + :goals: debug + + .. group-tab:: M5Stack CoreS3 SE + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: m5stack_cores3/esp32s3/procpu/se + :goals: debug + +You can debug an application in the usual way. Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. tabs:: + + .. group-tab:: M5Stack CoreS3 + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: m5stack_cores3/esp32s3/procpu + :goals: debug + + .. group-tab:: M5Stack CoreS3 SE + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: m5stack_cores3/esp32s3/procpu/se + :goals: debug + +References +********** + +.. target-notes:: + +.. _`M5Stack CoreS3 Documentation`: http://docs.m5stack.com/en/core/CoreS3 +.. _`M5Stack CoreS3 Schematic`: https://m5stack.oss-cn-shenzhen.aliyuncs.com/resource/docs/datasheet/core/K128%20CoreS3/Sch_M5_CoreS3_v1.0.pdf +.. _`M5Stack CoreS3 SE Documentation`: https://docs.m5stack.com/en/core/M5CoreS3%20SE +.. _`M5Stack CoreS3 SE Schematic`: https://m5stack.oss-cn-shenzhen.aliyuncs.com/resource/docs/products/core/M5CORES3%20SE/M5_CoreS3SE.pdf +.. _`OpenOCD ESP32`: https://github.com/espressif/openocd-esp32/releases +.. _`JTAG debugging for ESP32-S3`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32s3/api-guides/jtag-debugging/ diff --git a/boards/m5stack/m5stack_cores3/grove_connectors.dtsi b/boards/m5stack/m5stack_cores3/grove_connectors.dtsi new file mode 100644 index 00000000000..4139a48b867 --- /dev/null +++ b/boards/m5stack/m5stack_cores3/grove_connectors.dtsi @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2024 TOKITA Hiroshi + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + grove_header: grove_header { + compatible = "grove-header"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpio0 1 0>, + <1 0 &gpio0 2 0>; + }; +}; + +grove_i2c: &i2c1 {}; +grove_uart: &uart2 {}; diff --git a/boards/m5stack/m5stack_cores3/m5stack_cores3-pinctrl.dtsi b/boards/m5stack/m5stack_cores3/m5stack_cores3-pinctrl.dtsi new file mode 100644 index 00000000000..78f4c841147 --- /dev/null +++ b/boards/m5stack/m5stack_cores3/m5stack_cores3-pinctrl.dtsi @@ -0,0 +1,82 @@ +/* + * Copyright (c) 2024 Zhang Xingtao + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +&pinctrl { + uart0_default: uart0_default { + group1 { + pinmux = ; + output-high; + }; + group2 { + pinmux = ; + bias-pull-up; + }; + }; + + uart1_default: uart1_default { + group1 { + pinmux = ; + output-high; + }; + group2 { + pinmux = ; + bias-pull-up; + }; + }; + + uart2_default: uart2_default { + group1 { + pinmux = ; + output-high; + }; + group2 { + pinmux = ; + bias-pull-up; + }; + }; + + spim2_default: spim2_default { + group1 { + pinmux = , + ; + }; + group2 { + pinmux = ; + output-low; + }; + }; + + i2c0_default: i2c0_default { + group1 { + pinmux = , + ; + bias-pull-up; + drive-open-drain; + output-high; + }; + }; + + i2c1_default: i2c1_default { + group1 { + pinmux = , + ; + bias-pull-up; + drive-open-drain; + output-high; + }; + }; + + twai_default: twai_default { + group1 { + pinmux = , + ; + }; + }; +}; diff --git a/boards/m5stack/m5stack_cores3/m5stack_cores3_appcpu.dts b/boards/m5stack/m5stack_cores3/m5stack_cores3_appcpu.dts new file mode 100644 index 00000000000..ff04bc68817 --- /dev/null +++ b/boards/m5stack/m5stack_cores3/m5stack_cores3_appcpu.dts @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include +#include +#include "m5stack_cores3-pinctrl.dtsi" + +/ { + model = "M5Stack CoreS3 APPCPU"; + compatible = "espressif,esp32s3"; + + chosen { + zephyr,sram = &sram1; + zephyr,ipc_shm = &shm0; + zephyr,ipc = &ipm0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_appcpu_partition; + }; +}; + +&ipm0 { + status = "okay"; +}; + +&trng0 { + status = "okay"; +}; diff --git a/boards/m5stack/m5stack_cores3/m5stack_cores3_appcpu.yaml b/boards/m5stack/m5stack_cores3/m5stack_cores3_appcpu.yaml new file mode 100644 index 00000000000..19e6b770c68 --- /dev/null +++ b/boards/m5stack/m5stack_cores3/m5stack_cores3_appcpu.yaml @@ -0,0 +1,27 @@ +identifier: m5stack_cores3/esp32s3/appcpu +name: M5Stack CoreS3 APPCPU +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - uart +testing: + ignore_tags: + - net + - bluetooth + - flash + - cpp + - posix + - watchdog + - logging + - kernel + - pm + - gpio + - crypto + - eeprom + - heap + - cmsis_rtos + - jwt + - zdsp +vendor: m5stack diff --git a/boards/m5stack/m5stack_cores3/m5stack_cores3_appcpu_defconfig b/boards/m5stack/m5stack_cores3/m5stack_cores3_appcpu_defconfig new file mode 100644 index 00000000000..9abf2ff0430 --- /dev/null +++ b/boards/m5stack/m5stack_cores3/m5stack_cores3_appcpu_defconfig @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 +CONFIG_CLOCK_CONTROL=y diff --git a/boards/m5stack/m5stack_cores3/m5stack_cores3_procpu.dts b/boards/m5stack/m5stack_cores3/m5stack_cores3_procpu.dts new file mode 100644 index 00000000000..1def598cdec --- /dev/null +++ b/boards/m5stack/m5stack_cores3/m5stack_cores3_procpu.dts @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2024 TOKITA Hiroshi + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include "m5stack_cores3_procpu_common.dtsi" + +/ { + model = "M5Stack CoreS3 PROCPU"; + compatible = "m5stack,cores3"; + + aliases { + accel0 = &bmi270; + magn0 = &bmm150; + }; +}; + +&i2c0 { + bmi270: bmi270@69 { + compatible = "bosch,bmi270"; + reg = <0x69>; + }; + + bmm150: bmm150@10 { + compatible = "bosch,bmm150"; + status = "okay"; + reg = <0x10>; + }; +}; diff --git a/boards/m5stack/m5stack_cores3/m5stack_cores3_procpu.yaml b/boards/m5stack/m5stack_cores3/m5stack_cores3_procpu.yaml new file mode 100644 index 00000000000..1db3de005d2 --- /dev/null +++ b/boards/m5stack/m5stack_cores3/m5stack_cores3_procpu.yaml @@ -0,0 +1,19 @@ +identifier: m5stack_cores3/esp32s3/procpu +name: M5Stack CoreS3 PROCPU +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - gpio + - uart + - i2c + - spi + - can + - counter + - watchdog + - entropy + - pwm + - dma + - pinmux +vendor: m5stack diff --git a/boards/m5stack/m5stack_cores3/m5stack_cores3_procpu_common.dtsi b/boards/m5stack/m5stack_cores3/m5stack_cores3_procpu_common.dtsi new file mode 100644 index 00000000000..9b9b8991a15 --- /dev/null +++ b/boards/m5stack/m5stack_cores3/m5stack_cores3_procpu_common.dtsi @@ -0,0 +1,158 @@ +/* + * Copyright (c) 2024 Zhang Xingtao + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include "m5stack_cores3-pinctrl.dtsi" +#include "m5stack_mbus_connectors.dtsi" +#include "grove_connectors.dtsi" + +/ { + chosen { + zephyr,sram = &sram1; + zephyr,console = &usb_serial; + zephyr,shell-uart = &usb_serial; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + zephyr,rtc = &bm8563_rtc; + zephyr,bt-hci = &esp32_bt_hci; + zephyr,touch = &ft6336_touch; + }; + + aliases { + uart-0 = &uart0; + uart-1 = &uart1; + uart-2 = &uart2; + i2c-0 = &i2c0; + i2c-1 = &i2c1; + watchdog0 = &wdt0; + rtc = &bm8563_rtc; + sdhc0 = &sd0; + }; + + lvgl_pointer { + compatible = "zephyr,lvgl-pointer-input"; + input = <&ft6336_touch>; + }; +}; + +&usb_serial { + status = "okay"; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; +}; + +&uart1 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart1_default>; + pinctrl-names = "default"; +}; + +&uart2 { + status = "disabled"; + current-speed = <115200>; + pinctrl-0 = <&uart2_default>; + pinctrl-names = "default"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = ; + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; + + bm8563_rtc: bm8563@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + status = "okay"; + }; + + aw9523b@58 { + compatible = "awinic,aw9523b"; + reg = <0x58>; + status = "okay"; + + aw9523b_gpio: gpio { + compatible = "awinic,aw9523b-gpio"; + gpio-controller; + #gpio-cells = <2>; + port0-push-pull; + int-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; + }; + }; + + ft6336_touch: ft5336@38 { + status = "okay"; + compatible = "focaltech,ft5336"; + reg = <0x38>; + int-gpios = <&aw9523b_gpio 10 GPIO_ACTIVE_LOW>; + reset-gpios = <&aw9523b_gpio 0 GPIO_ACTIVE_LOW>; + }; +}; + +&i2c1 { + status = "okay"; + clock-frequency = ; + pinctrl-0 = <&i2c1_default>; + pinctrl-names = "default"; +}; + +&spi2 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim2_default>; + pinctrl-names = "default"; + clock-frequency = <20000000>; + cs-gpios = <&gpio0 3 GPIO_ACTIVE_LOW>, /* LCD */ + <&gpio0 4 GPIO_ACTIVE_LOW>; /* TF-CARD */ + + sd0: sd@1 { + compatible = "zephyr,sdhc-spi-slot"; + reg = <1>; + status = "okay"; + spi-max-frequency = <20000000>; + mmc { + compatible = "zephyr,sdmmc-disk"; + disk-name = "SD"; + status = "okay"; + }; + + }; +}; + +&twai { + status = "disabled"; + pinctrl-0 = <&twai_default>; + pinctrl-names = "default"; +}; + +&wdt0 { + status = "okay"; +}; + +&trng0 { + status = "okay"; +}; + +&esp32_bt_hci { + status = "okay"; +}; diff --git a/boards/m5stack/m5stack_cores3/m5stack_cores3_procpu_defconfig b/boards/m5stack/m5stack_cores3/m5stack_cores3_procpu_defconfig new file mode 100644 index 00000000000..6539bd42e59 --- /dev/null +++ b/boards/m5stack/m5stack_cores3/m5stack_cores3_procpu_defconfig @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_GPIO=y diff --git a/boards/m5stack/m5stack_cores3/m5stack_cores3_procpu_se.dts b/boards/m5stack/m5stack_cores3/m5stack_cores3_procpu_se.dts new file mode 100644 index 00000000000..93cdeda68cb --- /dev/null +++ b/boards/m5stack/m5stack_cores3/m5stack_cores3_procpu_se.dts @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2024 TOKITA Hiroshi + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include "m5stack_cores3_procpu_common.dtsi" + +/ { + model = "M5Stack CoreS3 SE PROCPU"; + compatible = "m5stack,cores3-se"; +}; diff --git a/boards/m5stack/m5stack_cores3/m5stack_cores3_procpu_se.yaml b/boards/m5stack/m5stack_cores3/m5stack_cores3_procpu_se.yaml new file mode 100644 index 00000000000..0427aa4f120 --- /dev/null +++ b/boards/m5stack/m5stack_cores3/m5stack_cores3_procpu_se.yaml @@ -0,0 +1,19 @@ +identifier: m5stack_cores3/esp32s3/procpu/se +name: M5Stack CoreS3 SE PROCPU +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - gpio + - uart + - i2c + - spi + - can + - counter + - watchdog + - entropy + - pwm + - dma + - pinmux +vendor: m5stack diff --git a/boards/m5stack/m5stack_cores3/m5stack_cores3_procpu_se_defconfig b/boards/m5stack/m5stack_cores3/m5stack_cores3_procpu_se_defconfig new file mode 100644 index 00000000000..6539bd42e59 --- /dev/null +++ b/boards/m5stack/m5stack_cores3/m5stack_cores3_procpu_se_defconfig @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_GPIO=y diff --git a/boards/m5stack/m5stack_cores3/m5stack_mbus_connectors.dtsi b/boards/m5stack/m5stack_cores3/m5stack_mbus_connectors.dtsi new file mode 100644 index 00000000000..c91d0b372d0 --- /dev/null +++ b/boards/m5stack/m5stack_cores3/m5stack_mbus_connectors.dtsi @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2024 TOKITA Hiroshi + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + m5stack_mbus_header: m5stack_mbus_connector { + compatible = "m5stack,mbus-header"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = /* GND */ <1 0 &gpio 10 0>, /* ADC */ + /* GND */ <3 0 &gpio 8 0>, /* PB_IN */ + /* GND */ /* RESET/EN */ + /* MOSI */ <6 0 &gpio 37 0>, <7 0 &gpio 5 0>, /* GPIO */ + /* MISO */ <8 0 &gpio 35 0>, <9 0 &gpio 9 0>, /* PB_OUT */ + /* SCK */ <10 0 &gpio 36 0>, /* 3.3V */ + /* RXD0 */ <12 0 &gpio 44 0>, <13 0 &gpio 43 0>, /* TXD0 */ + /* PC_RX */ <14 0 &gpio 18 0>, <15 0 &gpio 17 0>, /* PC_TX */ + /* intSDA */ <16 0 &gpio 12 0>, <17 0 &gpio 11 0>, /* intSCL */ + /* PA_SDA */ <18 0 &gpio 2 0>, <19 0 &gpio 1 0>, /* PA_SCL */ + /* GPIO */ <20 0 &gpio 6 0>, <21 0 &gpio 7 0>, /* GPIO */ + /* I2S_DOUT */ <22 0 &gpio 13 0>, <23 0 &gpio 0 0>, /* I2S_LRCK */ + /* NC */ <25 0 &gpio 3 0>; /* I2S_DIN */ + /* NC */ /* 5V */ + /* NC */ /* BAT */ + }; +}; + +m5stack_mbus_i2c0: &i2c0 {}; +m5stack_mbus_i2c1: &i2c1 {}; +m5stack_mbus_uart0: &uart0 {}; +m5stack_mbus_uart1: &uart1 {}; +m5stack_mbus_spi: &spi2 {}; diff --git a/boards/m5stack/m5stack_cores3/support/openocd.cfg b/boards/m5stack/m5stack_cores3/support/openocd.cfg new file mode 100644 index 00000000000..2f740b4a36a --- /dev/null +++ b/boards/m5stack/m5stack_cores3/support/openocd.cfg @@ -0,0 +1,7 @@ +set ESP_RTOS none +set ESP32_ONLYCPU 1 + +# Source the JTAG interface configuration file +source [find interface/esp_usb_jtag.cfg] +# Source the ESP32-S3 configuration file +source [find target/esp32s3.cfg] diff --git a/boards/m5stack/m5stack_stamps3/Kconfig b/boards/m5stack/m5stack_stamps3/Kconfig new file mode 100644 index 00000000000..65e8c315b93 --- /dev/null +++ b/boards/m5stack/m5stack_stamps3/Kconfig @@ -0,0 +1,7 @@ +# Copyright (c) 2023 Martin Kiepfer +# SPDX-License-Identifier: Apache-2.0 + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 4096 if BOARD_M5STACK_STAMPS3_ESP32S3_PROCPU + default 256 if BOARD_M5STACK_STAMPS3_ESP32S3_APPCPU diff --git a/boards/m5stack/m5stack_stamps3/Kconfig.defconfig b/boards/m5stack/m5stack_stamps3/Kconfig.defconfig index 903059dffbc..13f079ac915 100644 --- a/boards/m5stack/m5stack_stamps3/Kconfig.defconfig +++ b/boards/m5stack/m5stack_stamps3/Kconfig.defconfig @@ -4,21 +4,7 @@ if BOARD_M5STACK_STAMPS3_ESP32S3_PROCPU -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 65535 if WIFI && BT - default 51200 if WIFI - default 40960 if BT - default 4096 - config KERNEL_MEM_POOL default y endif # BOARD_M5STACK_STAMPS3_ESP32S3_PROCPU - -if BOARD_M5STACK_STAMPS3_ESP32S3_APPCPU - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - default 256 - -endif # BOARD_M5STACK_STAMPS3_ESP32S3_APPCPU diff --git a/boards/m5stack/m5stack_stamps3/doc/index.rst b/boards/m5stack/m5stack_stamps3/doc/index.rst index 36881121e8a..3762fd49b1c 100644 --- a/boards/m5stack/m5stack_stamps3/doc/index.rst +++ b/boards/m5stack/m5stack_stamps3/doc/index.rst @@ -1,7 +1,4 @@ -.. _m5stack_stamps3: - -M5Stack StampS3 -############### +.. zephyr:board:: m5stack_stamps3 Overview ******** @@ -17,13 +14,6 @@ It features the following integrated components: - Bluetooth - User-Button -.. figure:: img/m5stack_stamps3.webp - :align: center - :alt: M5Stack StampS3 - :width: 400 px - - M5Stack StampS3 module - Functional Description ********************** diff --git a/boards/m5stack/m5stack_stamps3/m5stack_stamps3_appcpu.dts b/boards/m5stack/m5stack_stamps3/m5stack_stamps3_appcpu.dts index ce947b57972..f6af6a54e42 100644 --- a/boards/m5stack/m5stack_stamps3/m5stack_stamps3_appcpu.dts +++ b/boards/m5stack/m5stack_stamps3/m5stack_stamps3_appcpu.dts @@ -5,15 +5,19 @@ */ /dts-v1/; -#include +#include +#include + / { model = "M5Stack StampS3 APPCPU"; compatible = "espressif,esp32s3"; chosen { - zephyr,sram = &sram0; + zephyr,sram = &sram1; zephyr,ipc_shm = &shm0; zephyr,ipc = &ipm0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_appcpu_partition; }; }; @@ -24,42 +28,3 @@ &ipm0 { status = "okay"; }; - -&flash0 { - status = "okay"; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Reserve 64kB for the bootloader */ - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x00010000>; - read-only; - }; - - /* Reserve 1024kB for the application in slot 0 */ - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 0x00100000>; - }; - - /* Reserve 1024kB for the application in slot 1 */ - slot1_partition: partition@110000 { - label = "image-1"; - reg = <0x00110000 0x00100000>; - }; - - /* Reserve 256kB for the scratch partition */ - scratch_partition: partition@210000 { - label = "image-scratch"; - reg = <0x00210000 0x00040000>; - }; - - storage_partition: partition@250000 { - label = "storage"; - reg = <0x00250000 0x00006000>; - }; - }; -}; diff --git a/boards/m5stack/m5stack_stamps3/m5stack_stamps3_procpu.dts b/boards/m5stack/m5stack_stamps3/m5stack_stamps3_procpu.dts index 9e231fba57f..f2733a57195 100644 --- a/boards/m5stack/m5stack_stamps3/m5stack_stamps3_procpu.dts +++ b/boards/m5stack/m5stack_stamps3/m5stack_stamps3_procpu.dts @@ -12,13 +12,14 @@ #include #include #include +#include / { model = "M5Stack StampS3 PROCPU"; compatible = "m5stack,stamps3"; chosen { - zephyr,sram = &sram0; + zephyr,sram = &sram1; zephyr,console = &usb_serial; zephyr,shell-uart = &usb_serial; zephyr,flash = &flash0; @@ -152,41 +153,6 @@ status = "okay"; }; -&flash0 { - status = "okay"; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x0000F000>; - read-only; - }; - - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 0x00100000>; - }; - - slot1_partition: partition@110000 { - label = "image-1"; - reg = <0x00110000 0x00100000>; - }; - - scratch_partition: partition@210000 { - label = "image-scratch"; - reg = <0x00210000 0x00040000>; - }; - - storage_partition: partition@250000 { - label = "storage"; - reg = <0x00250000 0x00006000>; - }; - }; -}; - &esp32_bt_hci { status = "okay"; }; diff --git a/boards/m5stack/m5stack_stamps3/m5stack_stamps3_procpu.yaml b/boards/m5stack/m5stack_stamps3/m5stack_stamps3_procpu.yaml index 746a5d2916e..762db7cbd76 100644 --- a/boards/m5stack/m5stack_stamps3/m5stack_stamps3_procpu.yaml +++ b/boards/m5stack/m5stack_stamps3/m5stack_stamps3_procpu.yaml @@ -13,8 +13,4 @@ supported: - pwm - pinmux - nvs -testing: - ignore_tags: - - net - - bluetooth vendor: m5stack diff --git a/boards/m5stack/m5stickc_plus/Kconfig b/boards/m5stack/m5stickc_plus/Kconfig new file mode 100644 index 00000000000..735b5d5ce6b --- /dev/null +++ b/boards/m5stack/m5stickc_plus/Kconfig @@ -0,0 +1,7 @@ +# Copyright (c) 2022 AVSystem Sławomir Wolf Sp.j. (AVSystem) +# SPDX-License-Identifier: Apache-2.0 + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 4096 if BOARD_M5STICKC_PLUS_ESP32_PROCPU + default 256 if BOARD_M5STICKC_PLUS_ESP32_APPCPU diff --git a/boards/m5stack/m5stickc_plus/Kconfig.defconfig b/boards/m5stack/m5stickc_plus/Kconfig.defconfig index a6b957227be..86819dba82d 100644 --- a/boards/m5stack/m5stickc_plus/Kconfig.defconfig +++ b/boards/m5stack/m5stickc_plus/Kconfig.defconfig @@ -5,13 +5,6 @@ if BOARD_M5STICKC_PLUS_ESP32_PROCPU -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 65535 if WIFI && BT - default 51200 if WIFI - default 40960 if BT - default 4096 - config GPIO_HOGS_INIT_PRIORITY default 70 @@ -28,10 +21,3 @@ config REGULATOR_FIXED_INIT_PRIORITY default 75 endif # BOARD_M5STICKC_PLUS_ESP32_PROCPU - -if BOARD_M5STICKC_PLUS_ESP32_APPCPU - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - default 256 - -endif # BOARD_M5STICKC_PLUS_ESP32_APPCPU diff --git a/boards/m5stack/m5stickc_plus/doc/index.rst b/boards/m5stack/m5stickc_plus/doc/index.rst index 4fe431fea84..f40e21fbd5e 100644 --- a/boards/m5stack/m5stickc_plus/doc/index.rst +++ b/boards/m5stack/m5stickc_plus/doc/index.rst @@ -1,7 +1,4 @@ -.. _m5stickc_plus: - -M5StickC PLUS -############# +.. zephyr:board:: m5stickc_plus Overview ******** diff --git a/boards/m5stack/m5stickc_plus/m5stickc_plus_appcpu.dts b/boards/m5stack/m5stickc_plus/m5stickc_plus_appcpu.dts index 1911e4fe56d..23e942449c1 100644 --- a/boards/m5stack/m5stickc_plus/m5stickc_plus_appcpu.dts +++ b/boards/m5stack/m5stickc_plus/m5stickc_plus_appcpu.dts @@ -5,16 +5,19 @@ */ /dts-v1/; -#include +#include +#include / { model = "M5StickC Plus APPCPU"; compatible = "espressif,esp32"; chosen { - zephyr,sram = &sram0; + zephyr,sram = &sram1; zephyr,ipc_shm = &shm0; zephyr,ipc = &ipm0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_appcpu_partition; }; }; @@ -25,42 +28,3 @@ &trng0 { status = "okay"; }; - -&flash0 { - status = "okay"; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Reserve 60kB for the bootloader */ - boot_partition: partition@1000 { - label = "mcuboot"; - reg = <0x00001000 0x0000F000>; - read-only; - }; - - /* Reserve 1024kB for the application in slot 0 */ - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 0x00100000>; - }; - - /* Reserve 1024kB for the application in slot 1 */ - slot1_partition: partition@110000 { - label = "image-1"; - reg = <0x00110000 0x00100000>; - }; - - /* Reserve 256kB for the scratch partition */ - scratch_partition: partition@210000 { - label = "image-scratch"; - reg = <0x00210000 0x00040000>; - }; - - storage_partition: partition@250000 { - label = "storage"; - reg = <0x00250000 0x00006000>; - }; - }; -}; diff --git a/boards/m5stack/m5stickc_plus/m5stickc_plus_procpu.dts b/boards/m5stack/m5stickc_plus/m5stickc_plus_procpu.dts index 28779d87ecb..6b1a2dd8ba2 100644 --- a/boards/m5stack/m5stickc_plus/m5stickc_plus_procpu.dts +++ b/boards/m5stack/m5stickc_plus/m5stickc_plus_procpu.dts @@ -10,6 +10,7 @@ #include #include #include +#include / { model = "M5StickC Plus PROCPU"; @@ -27,7 +28,7 @@ }; chosen { - zephyr,sram = &sram0; + zephyr,sram = &sram1; zephyr,console = &uart0; zephyr,shell-uart = &uart0; zephyr,flash = &flash0; @@ -95,7 +96,7 @@ nvgam-param = [d0 00 02 07 0a 28 31 54 47 0e 1c 17 1b 1e]; ram-param = [00 F0]; rgb-param = [40 02 14]; - mipi-mode = ; + mipi-mode = "MIPI_DBI_MODE_SPI_4WIRE"; }; }; }; @@ -214,45 +215,6 @@ status = "okay"; }; -&flash0 { - status = "okay"; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Reserve 60kB for the bootloader */ - boot_partition: partition@1000 { - label = "mcuboot"; - reg = <0x00001000 0x0000F000>; - read-only; - }; - - /* Reserve 1024kB for the application in slot 0 */ - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 0x00100000>; - }; - - /* Reserve 1024kB for the application in slot 1 */ - slot1_partition: partition@110000 { - label = "image-1"; - reg = <0x00110000 0x00100000>; - }; - - /* Reserve 256kB for the scratch partition */ - scratch_partition: partition@210000 { - label = "image-scratch"; - reg = <0x00210000 0x00040000>; - }; - - storage_partition: partition@250000 { - label = "storage"; - reg = <0x00250000 0x00006000>; - }; - }; -}; - &esp32_bt_hci { status = "okay"; }; diff --git a/boards/m5stack/m5stickc_plus/m5stickc_plus_procpu.yaml b/boards/m5stack/m5stickc_plus/m5stickc_plus_procpu.yaml index 69741a72d8f..25fc452b8a9 100644 --- a/boards/m5stack/m5stickc_plus/m5stickc_plus_procpu.yaml +++ b/boards/m5stack/m5stickc_plus/m5stickc_plus_procpu.yaml @@ -14,8 +14,4 @@ supported: - nvs - regulator - display -testing: - ignore_tags: - - net - - bluetooth vendor: m5stack diff --git a/boards/m5stack/stamp_c3/Kconfig b/boards/m5stack/stamp_c3/Kconfig new file mode 100644 index 00000000000..264a7fc7beb --- /dev/null +++ b/boards/m5stack/stamp_c3/Kconfig @@ -0,0 +1,6 @@ +# Copyright 2022 TOKITA Hiroshi +# SPDX-License-Identifier: Apache-2.0 + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 4096 diff --git a/boards/m5stack/stamp_c3/Kconfig.defconfig b/boards/m5stack/stamp_c3/Kconfig.defconfig deleted file mode 100644 index dcc3a422548..00000000000 --- a/boards/m5stack/stamp_c3/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# M5Stack STAMP-C3 board configuration - -# Copyright 2022 TOKITA Hiroshi -# SPDX-License-Identifier: Apache-2.0 - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 65535 if WIFI && BT - default 51200 if WIFI - default 40960 if BT - default 4096 diff --git a/boards/m5stack/stamp_c3/Kconfig.stamp_c3 b/boards/m5stack/stamp_c3/Kconfig.stamp_c3 index dd126de3dfd..096e78bfe0b 100644 --- a/boards/m5stack/stamp_c3/Kconfig.stamp_c3 +++ b/boards/m5stack/stamp_c3/Kconfig.stamp_c3 @@ -4,4 +4,4 @@ # SPDX-License-Identifier: Apache-2.0 config BOARD_STAMP_C3 - select SOC_ESP32C3_FX4 + select SOC_ESP32C3_FN4 diff --git a/boards/m5stack/stamp_c3/doc/index.rst b/boards/m5stack/stamp_c3/doc/index.rst index 40869ee0166..a953b595b2c 100644 --- a/boards/m5stack/stamp_c3/doc/index.rst +++ b/boards/m5stack/stamp_c3/doc/index.rst @@ -1,7 +1,4 @@ -.. _stamp_c3: - -M5Stack STAMP-C3 -################## +.. zephyr:board:: stamp_c3 Overview ******** diff --git a/boards/m5stack/stamp_c3/stamp_c3.dts b/boards/m5stack/stamp_c3/stamp_c3.dts index ef026e94454..cbd3a3fdd92 100644 --- a/boards/m5stack/stamp_c3/stamp_c3.dts +++ b/boards/m5stack/stamp_c3/stamp_c3.dts @@ -9,13 +9,14 @@ #include #include "stamp_c3-pinctrl.dtsi" #include +#include / { model = "M5Stack STAMP-C3"; compatible = "m5stack,stamp_c3"; chosen { - zephyr,sram = &sram0; + zephyr,sram = &sram1; zephyr,console = &uart0; zephyr,shell-uart = &uart0; zephyr,flash = &flash0; @@ -92,45 +93,6 @@ pinctrl-names = "default"; }; -&flash0 { - status = "okay"; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Reserve 60kB for the bootloader */ - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x0000F000>; - read-only; - }; - - /* Reserve 1024kB for the application in slot 0 */ - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 0x00100000>; - }; - - /* Reserve 1024kB for the application in slot 1 */ - slot1_partition: partition@110000 { - label = "image-1"; - reg = <0x00110000 0x00100000>; - }; - - /* Reserve 256kB for the scratch partition */ - scratch_partition: partition@210000 { - label = "image-scratch"; - reg = <0x00210000 0x00040000>; - }; - - storage_partition: partition@250000 { - label = "storage"; - reg = <0x00250000 0x00006000>; - }; - }; -}; - &esp32_bt_hci { status = "okay"; }; diff --git a/boards/m5stack/stamp_c3/stamp_c3.yaml b/boards/m5stack/stamp_c3/stamp_c3.yaml index d196fd357c6..4b272b9e8e7 100644 --- a/boards/m5stack/stamp_c3/stamp_c3.yaml +++ b/boards/m5stack/stamp_c3/stamp_c3.yaml @@ -10,8 +10,4 @@ supported: - spi - uart - watchdog -testing: - ignore_tags: - - net - - bluetooth vendor: m5stack diff --git a/boards/madmachine/mm_feather/doc/index.rst b/boards/madmachine/mm_feather/doc/index.rst index 0a556bc42b0..7c1b985fc70 100644 --- a/boards/madmachine/mm_feather/doc/index.rst +++ b/boards/madmachine/mm_feather/doc/index.rst @@ -1,7 +1,4 @@ -.. _mm_feather: - -MadMachine SwiftIO Feather -########################## +.. zephyr:board:: mm_feather Overview ******** @@ -16,10 +13,6 @@ at: - `MadMachine Homepage`_ - `SwiftIO API Reference`_ -.. image:: mm_feather.jpg - :align: center - :alt: SwiftIO Feather Board - Hardware ******** diff --git a/boards/madmachine/mm_feather/mm_feather.dts b/boards/madmachine/mm_feather/mm_feather.dts index 58aaac234bd..0b655edd1c2 100644 --- a/boards/madmachine/mm_feather/mm_feather.dts +++ b/boards/madmachine/mm_feather/mm_feather.dts @@ -61,7 +61,7 @@ compatible = "nxp,imx-flexspi-nor"; size = <67108864>; reg = <0>; - spi-max-frequency = <133000000>; + spi-max-frequency = <104000000>; status = "okay"; jedec-id = [9d 70 17]; }; diff --git a/boards/madmachine/mm_feather/mm_feather_defconfig b/boards/madmachine/mm_feather/mm_feather_defconfig index 65cb3610d48..da5dded1e40 100644 --- a/boards/madmachine/mm_feather/mm_feather_defconfig +++ b/boards/madmachine/mm_feather/mm_feather_defconfig @@ -11,4 +11,3 @@ CONFIG_GPIO=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=600000000 CONFIG_ARM_MPU=y CONFIG_HW_STACK_PROTECTION=y -CONFIG_PINCTRL=y diff --git a/boards/madmachine/mm_swiftio/doc/index.rst b/boards/madmachine/mm_swiftio/doc/index.rst index 5fb0837e1ea..6845fa1fa36 100644 --- a/boards/madmachine/mm_swiftio/doc/index.rst +++ b/boards/madmachine/mm_swiftio/doc/index.rst @@ -1,7 +1,4 @@ -.. _mm_swiftio: - -MadMachine SwiftIO -################## +.. zephyr:board:: mm_swiftio Overview ******** @@ -16,12 +13,6 @@ at: - `MadMachine Homepage`_ - `SwiftIO API Reference`_ - - -.. image:: mm_swiftio.jpg - :align: center - :alt: SwiftIO Board - Hardware ******** diff --git a/boards/madmachine/mm_swiftio/mm_swiftio.dts b/boards/madmachine/mm_swiftio/mm_swiftio.dts index e4212cd8294..cbdf85c3c12 100644 --- a/boards/madmachine/mm_swiftio/mm_swiftio.dts +++ b/boards/madmachine/mm_swiftio/mm_swiftio.dts @@ -61,7 +61,7 @@ compatible = "nxp,imx-flexspi-nor"; size = <67108864>; reg = <0>; - spi-max-frequency = <133000000>; + spi-max-frequency = <104000000>; status = "okay"; jedec-id = [9d 70 17]; }; @@ -115,7 +115,7 @@ port { ov7725_ep_out: endpoint { - remote-endpoint = <&csi_ep_in>; + remote-endpoint-label = "csi_ep_in"; }; }; }; @@ -186,19 +186,19 @@ pinctrl-names = "default", "slow", "med", "fast"; mmc { compatible = "zephyr,sdmmc-disk"; + disk-name = "SD"; status = "okay"; }; }; &csi { status = "okay"; - source = <&ov7725>; pinctrl-0 = <&pinmux_csi>; pinctrl-names = "default"; port { csi_ep_in: endpoint { - remote-endpoint = <&ov7725_ep_out>; + remote-endpoint-label = "ov7725_ep_out"; }; }; }; diff --git a/boards/madmachine/mm_swiftio/mm_swiftio_defconfig b/boards/madmachine/mm_swiftio/mm_swiftio_defconfig index 0aee57c3625..4767b1fe6ce 100644 --- a/boards/madmachine/mm_swiftio/mm_swiftio_defconfig +++ b/boards/madmachine/mm_swiftio/mm_swiftio_defconfig @@ -11,4 +11,3 @@ CONFIG_GPIO=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=600000000 CONFIG_ARM_MPU=y CONFIG_HW_STACK_PROTECTION=y -CONFIG_PINCTRL=y diff --git a/boards/makerbase/index.rst b/boards/makerbase/index.rst new file mode 100644 index 00000000000..4e8d4a84c93 --- /dev/null +++ b/boards/makerbase/index.rst @@ -0,0 +1,10 @@ +.. _boards-makerbase: + +Makerbase +######### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/makerbase/mks_canable_v20/Kconfig.mks_canable_v20 b/boards/makerbase/mks_canable_v20/Kconfig.mks_canable_v20 new file mode 100644 index 00000000000..ef676f4ffcd --- /dev/null +++ b/boards/makerbase/mks_canable_v20/Kconfig.mks_canable_v20 @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Alexander Kozhinov +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MKS_CANABLE_V20 + select SOC_STM32G431XX diff --git a/boards/makerbase/mks_canable_v20/board.cmake b/boards/makerbase/mks_canable_v20/board.cmake new file mode 100644 index 00000000000..5b98199c697 --- /dev/null +++ b/boards/makerbase/mks_canable_v20/board.cmake @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Alexander Kozhinov +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(openocd "--config=${BOARD_DIR}/support/openocd.cfg") + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/makerbase/mks_canable_v20/board.yml b/boards/makerbase/mks_canable_v20/board.yml new file mode 100644 index 00000000000..ac103e7655a --- /dev/null +++ b/boards/makerbase/mks_canable_v20/board.yml @@ -0,0 +1,6 @@ +board: + name: mks_canable_v20 + full_name: MKS CANable V2.0 + vendor: makerbase + socs: + - name: stm32g431xx diff --git a/boards/makerbase/mks_canable_v20/doc/img/mks_canable_v20.webp b/boards/makerbase/mks_canable_v20/doc/img/mks_canable_v20.webp new file mode 100644 index 00000000000..7f92a5ed81d Binary files /dev/null and b/boards/makerbase/mks_canable_v20/doc/img/mks_canable_v20.webp differ diff --git a/boards/makerbase/mks_canable_v20/doc/index.rst b/boards/makerbase/mks_canable_v20/doc/index.rst new file mode 100644 index 00000000000..0a86e6fa6fc --- /dev/null +++ b/boards/makerbase/mks_canable_v20/doc/index.rst @@ -0,0 +1,170 @@ +.. zephyr:board:: mks_canable_v20 + +Overview +******** + +The Makerbase MKS CANable V2.0 board features an ARM Cortex-M4 based STM32G431C8 MCU +with a CAN, USB and debugger connections. +Here are some highlights of the MKS CANable V2.0 board: + +- STM32 microcontroller in LQFP48 package +- USB Type-C connector (J1) +- CAN-Bus connector (J2) +- ST-LINK/V3E debugger/programmer header (J4) +- USB VBUS power supply (5 V) +- Three LEDs: red/power_led (D1), blue/stat_led (D2), green/word_led (D3) +- One push-button for RESET +- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell. + +The LED red/power_led (D1) is connected directly to on-board 3.3 V and not controllable by the MCU. + +More information about the board can be found at the `MKS CANable V2.0 website`_. +It is very advisable to take a look in on user manual `MKS CANable V2.0 User Manual`_ and +schematic `MKS CANable V2.0 schematic`_ before start. + +More information about STM32G431KB can be found here: + +- `STM32G431C8 on www.st.com`_ +- `STM32G4 reference manual`_ + +Supported Features +================== + +The Zephyr ``mks_canable_v20`` board target supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| USB | on-chip | universal-serial-bus | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| FDCAN | on-chip | can | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/makerbase/mks_canable_v20/mks_canable_v20_defconfig` + + +Connections and IOs +=================== + +Default Zephyr Peripheral Mapping: +---------------------------------- + +.. rst-class:: rst-columns + +- CAN_RX/BOOT0 : PB8 +- CAN_TX : PB9 +- D2 : PA15 +- D3 : PA0 +- USB_DN : PA11 +- USB_DP : PA12 +- SWDIO : PA13 +- SWCLK : PA14 +- NRST : PG10 + +For more details please refer to `MKS CANable V2.0 schematic`_. + +System Clock +------------ + +The MKS CANable V2.0 system clock is driven by internal high speed oscillator. +By default system clock is driven by PLL clock at 160 MHz, +the PLL is driven by the 16 MHz high speed internal oscillator. + +The FDCAN1 peripheral is driven by PLLQ, which has 80 MHz frequency. + +Programming and Debugging +************************* + +MKS CANable V2.0 board includes an SWDIO debug connector header J4. + +.. note:: + + The debugger is not the part of the board! + +Applications for the ``mks_canable_v20`` board target can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +The board could be flashed using west. + +Flashing an application to MKS CANable V2.0 +------------------------------------------- + +The debugger shall be wired to MKS CANable V2.0 board's J4 connector +according `MKS CANable V2.0 schematic`_. + +Build and flash an application. Here is an example for +:zephyr:code-sample:`hello_world`. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: mks_canable_v20 + :goals: build flash + :west-args: -S rtt-console + :compact: + +The argument ``-S rtt-console`` is needed for debug purposes with SEGGER RTT protocol. +This option is optional and may be omitted. Omitting it frees up RAM space but prevents RTT usage. + +If option ``-S rtt-console`` is selected, the connection to the target can be established as follows: + +.. code-block:: console + + $ telnet localhost 9090 + +You should see the following message on the console: + +.. code-block:: console + + $ Hello World! mks_canable_v20/stm32g431xx + +.. note:: + + Current OpenOCD config will skip Segger RTT for OpenOCD under 0.12.0. + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: mks_canable_v20 + :maybe-skip-config: + :goals: debug + +References +********** + +.. target-notes:: + +.. _MKS CANable V2.0 website: + https://github.com/makerbase-mks/CANable-MKS + +.. _MKS CANable V2.0 User Manual: + https://github.com/makerbase-mks/CANable-MKS/blob/main/User%20Manual/CANable%20V2.0/Makerbase%20CANable%20V2.0%20Use%20Manual.pdf + +.. _MKS CANable V2.0 schematic: + https://github.com/makerbase-mks/CANable-MKS/blob/main/Hardware/MKS%20CANable%20V2.0/MKS%20CANable%20V2.0_001%20schematic.pdf + +.. _STM32G431C8 on www.st.com: + https://www.st.com/en/microcontrollers-microprocessors/stm32g431c8.html + +.. _STM32G4 reference manual: + https://www.st.com/resource/en/reference_manual/rm0440-stm32g4-series-advanced-armbased-32bit-mcus-stmicroelectronics.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/makerbase/mks_canable_v20/mks_canable_v20.dts b/boards/makerbase/mks_canable_v20/mks_canable_v20.dts new file mode 100644 index 00000000000..2f2e54565f9 --- /dev/null +++ b/boards/makerbase/mks_canable_v20/mks_canable_v20.dts @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2024 Alexander Kozhinov + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include + +/ { + model = "Makerbase MKS CANable V2.0"; + compatible = "makerbase,mks-canable-v20"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,canbus = &fdcan1; + }; + + aliases { + led0 = &blue_led; + led1 = &green_led; + }; + + leds: leds { + compatible = "gpio-leds"; + blue_led: led_2 { + gpios = <&gpioa 15 GPIO_ACTIVE_LOW>; + label = "blue-status D2"; + }; + green_led: led_3 { + gpios = <&gpioa 0 GPIO_ACTIVE_LOW>; + label = "green-word D3"; + }; + }; +}; + +&clk_hsi { + /* Internal 16 MHz clock used to drive PLL */ + status = "okay"; +}; + +&clk_hsi48 { + /* Internal 48 MHz clock used to drive USB */ + status = "okay"; +}; + +/* Adjust the pll for a SYSTEM Clock of 160 MHz */ +&pll { + div-m = <4>; + mul-n = <80>; + div-p = <2>; + div-q = <4>; + div-r = <2>; + clocks = <&clk_hsi>; + status = "okay"; +}; + +&rcc { + clocks = <&pll>; + clock-frequency = ; + ahb-prescaler = <1>; + apb1-prescaler = <1>; + apb2-prescaler = <1>; +}; + +stm32_lp_tick_source: &lptim1 { + clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>, + <&rcc STM32_SRC_LSE LPTIM1_SEL(3)>; + status = "okay"; +}; + +zephyr_udc0: &usb { + pinctrl-0 = <&usb_dm_pa11 &usb_dp_pa12>; + pinctrl-names = "default"; + clocks = <&rcc STM32_CLOCK(APB1, 23U)>, + <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>; + status = "okay"; +}; + +&fdcan1 { + pinctrl-0 = <&fdcan1_rx_pb8 &fdcan1_tx_pb9>; + pinctrl-names = "default"; + clocks = <&rcc STM32_CLOCK(APB1, 25U)>, + <&rcc STM32_SRC_PLL_Q FDCAN_SEL(1)>; + status = "okay"; +}; diff --git a/boards/makerbase/mks_canable_v20/mks_canable_v20.yaml b/boards/makerbase/mks_canable_v20/mks_canable_v20.yaml new file mode 100644 index 00000000000..3ff3138b106 --- /dev/null +++ b/boards/makerbase/mks_canable_v20/mks_canable_v20.yaml @@ -0,0 +1,16 @@ +identifier: mks_canable_v20 +name: MKS CANable V2.0 +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb +ram: 32 +flash: 64 +supported: + - can + - counter + - gpio + - usb_device + - usbd +vendor: makerbase diff --git a/boards/makerbase/mks_canable_v20/mks_canable_v20_defconfig b/boards/makerbase/mks_canable_v20/mks_canable_v20_defconfig new file mode 100644 index 00000000000..f2613819bf5 --- /dev/null +++ b/boards/makerbase/mks_canable_v20/mks_canable_v20_defconfig @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Alexander Kozhinov +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_GPIO=y +CONFIG_ARM_MPU=y diff --git a/boards/makerbase/mks_canable_v20/support/openocd.cfg b/boards/makerbase/mks_canable_v20/support/openocd.cfg new file mode 100644 index 00000000000..b614de4fbf5 --- /dev/null +++ b/boards/makerbase/mks_canable_v20/support/openocd.cfg @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Alexander Kozhinov +# SPDX-License-Identifier: Apache-2.0 + +source [find interface/stlink.cfg] +source [find target/stm32g4x.cfg] diff --git a/boards/makerdiary/nrf52832_mdk/Kconfig.defconfig b/boards/makerdiary/nrf52832_mdk/Kconfig.defconfig index 13d65f68be1..471e9717248 100644 --- a/boards/makerdiary/nrf52832_mdk/Kconfig.defconfig +++ b/boards/makerdiary/nrf52832_mdk/Kconfig.defconfig @@ -5,7 +5,4 @@ if BOARD_NRF52832_MDK -config BT_CTLR - default BT - endif # BOARD_NRF52832_MDK diff --git a/boards/makerdiary/nrf52832_mdk/doc/index.rst b/boards/makerdiary/nrf52832_mdk/doc/index.rst index 2c8667bfacd..61ec37c09e8 100644 --- a/boards/makerdiary/nrf52832_mdk/doc/index.rst +++ b/boards/makerdiary/nrf52832_mdk/doc/index.rst @@ -1,7 +1,4 @@ -.. _nrf52832_mdk: - -nRF52832-mdk -################# +.. zephyr:board:: nrf52832_mdk Overview ******** diff --git a/boards/makerdiary/nrf52840_mdk/Kconfig.defconfig b/boards/makerdiary/nrf52840_mdk/Kconfig.defconfig index 4ffd9e4ea08..52e88201e3c 100644 --- a/boards/makerdiary/nrf52840_mdk/Kconfig.defconfig +++ b/boards/makerdiary/nrf52840_mdk/Kconfig.defconfig @@ -5,7 +5,4 @@ if BOARD_NRF52840_MDK -config BT_CTLR - default BT - endif # BOARD_NRF52840_MDK diff --git a/boards/makerdiary/nrf52840_mdk/doc/index.rst b/boards/makerdiary/nrf52840_mdk/doc/index.rst index 6e0b24b65f2..e2bc31dabca 100644 --- a/boards/makerdiary/nrf52840_mdk/doc/index.rst +++ b/boards/makerdiary/nrf52840_mdk/doc/index.rst @@ -1,7 +1,4 @@ -.. _nrf52840_mdk: - -nRF52840-mdk -################# +.. zephyr:board:: nrf52840_mdk Overview ******** diff --git a/boards/makerdiary/nrf52840_mdk_usb_dongle/Kconfig.defconfig b/boards/makerdiary/nrf52840_mdk_usb_dongle/Kconfig.defconfig index eb2cfed745d..5c7419ff43c 100644 --- a/boards/makerdiary/nrf52840_mdk_usb_dongle/Kconfig.defconfig +++ b/boards/makerdiary/nrf52840_mdk_usb_dongle/Kconfig.defconfig @@ -23,15 +23,6 @@ config FLASH_LOAD_OFFSET default 0x1000 depends on BOARD_HAS_NRF5_BOOTLOADER && !USE_DT_CODE_PARTITION -if USB_DEVICE_STACK - -# Enable UART driver, needed for CDC ACM -config SERIAL - default y - -endif # USB_DEVICE_STACK - -config BT_CTLR - default BT +source "boards/common/usb/Kconfig.cdc_acm_serial.defconfig" endif # BOARD_NRF52840_MDK_USB_DONGLE diff --git a/boards/makerdiary/nrf52840_mdk_usb_dongle/doc/index.rst b/boards/makerdiary/nrf52840_mdk_usb_dongle/doc/index.rst index 82202ec51ac..ac4743c7748 100644 --- a/boards/makerdiary/nrf52840_mdk_usb_dongle/doc/index.rst +++ b/boards/makerdiary/nrf52840_mdk_usb_dongle/doc/index.rst @@ -1,7 +1,4 @@ -.. _nrf52840_mdk_usb_dongle: - -nRF52840 MDK USB Dongle -####################### +.. zephyr:board:: nrf52840_mdk_usb_dongle Overview ******** @@ -15,12 +12,6 @@ Bluetooth5/Tread/802.15.4/ANT/2.4GHz multiprotocol node or development board. Alternatively the USB Dongle can be used as a Network Co-Processor(NCP) with a simple connection to a PC or other USB enabled device. -.. figure:: nrf52840-mdk-usb-dongle-pinout.jpg - :align: center - :alt: nRF52840 MDK USB Dongle - - nRF52840 MDK USB Dongle - See `nrf52840-mdk-usb-dongle website`_ for more information about the development board and `nRF52840 website`_ for the official reference on the IC itself. diff --git a/boards/makerdiary/nrf52840_mdk_usb_dongle/nrf52840_mdk_usb_dongle.dts b/boards/makerdiary/nrf52840_mdk_usb_dongle/nrf52840_mdk_usb_dongle.dts index 763aebe86e7..0c9dd6b4496 100644 --- a/boards/makerdiary/nrf52840_mdk_usb_dongle/nrf52840_mdk_usb_dongle.dts +++ b/boards/makerdiary/nrf52840_mdk_usb_dongle/nrf52840_mdk_usb_dongle.dts @@ -16,11 +16,6 @@ compatible = "nrf52840_mdk_usb_dongle"; chosen { - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - zephyr,uart-mcumgr = &uart0; - zephyr,bt-mon-uart = &uart0; - zephyr,bt-c2h-uart = &uart0; zephyr,sram = &sram0; zephyr,flash = &flash0; zephyr,code-partition = &slot0_partition; @@ -128,3 +123,5 @@ zephyr_udc0: &usbd { compatible = "nordic,nrf-usbd"; status = "okay"; }; + +#include <../boards/common/usb/cdc_acm_serial.dtsi> diff --git a/boards/mediatek/index.rst b/boards/mediatek/index.rst new file mode 100644 index 00000000000..4c41e0b4d86 --- /dev/null +++ b/boards/mediatek/index.rst @@ -0,0 +1,166 @@ +.. _boards-mtk_adsp: + +Mediatek Audio DSPs +################### + +Zephyr can be built and run on the Audio DSPs included in various +members of the Mediatek MT8xxx series of ARM SOCs used in Chromebooks +from various manufacturers. + +Two of these DSPs are in the market already, implemented via the +MT8195 ("Kompanio 1380") and MT8186 ("Kompanio 520") SOCs. +Development has been done on and validation performed on at least +these devices, though more exist: + + ====== ============= =================================== ================= + SOC Product Name Example Device ChromeOS Codename + ====== ============= =================================== ================= + MT8195 Kompanio 1380 HP Chromebook x360 13b dojo + MT8186 Kompanio 520 Lenovo 300e Yoga Chromebook Gen 4 steelix + ====== ============= =================================== ================= + +Hardware +******** + +These devices are Xtensa DSP cores, very similar to the Intel ADSP +series in concept (with the notable difference that these are all +single-core devices, no parallel SMP is available, but at the same +time there are fewer worries about the incoherent cache). + +Their memory space is split between dedicated, fast SRAM and ~16MB of +much slower system DRAM. Zephyr currently loads and links into the +DRAM area, a convention it inherits from SOF (these devices have +comparatively large caches which are used for all accesses, unlike +with intel_adsp). SRAM is used for interrupt vectors and stacks, +currently. + +There is comparatively little on-device hardware. The architecture is +that interaction with the off-chip audio hardware (e.g. I2S codecs, +DMIC inputs, etc...) is managed by the host kernel. The DSP receives +its data via a single array of custom DMA controllers. + +Beyond that the Zephyr-visible hardware is limited to a bounty of +timer devices (of which Zephyr uses two), and a "mailbox" +bidirectional interrupt source it uses to communicate with the host +kernel. + +Programming and Debugging +************************* + +These devices work entirely in RAM, so there is no "flash" process as +such. Their memory state is initialized by the host Linux +environment. This process works under the control of a +``mtk_adsp_load.py`` python script, which has no dependencies outside +the standard library and can be run (as root, of course) on any +reasonably compatible Linux environment with a Python 3.8 or later +interpreter. A chromebook in development mode with the dev packages +installed works great. See the ChromiumOS developer library for more +detail: + +* `Developer mode `__ +* `Dev-Install: Installing Developer and Test packages onto a Chrome OS device `__ + +Once you have the device set up, the process is as simple as copying +the ``zephyr.img`` file from the build directory to the device +(typically via ssh) and running it with the script. For example for +my mt8186 device named "steelix": + +.. code-block:: console + + user@dev_host:~$ west build -b mt8186//adsp samples/hello_world + ... + ... # build output + ... + user@dev_host:~$ scp build/zephyr/zephyr.img root@steelix: + user@dev_host:~$ scp soc/mediatek/mt8xxx/mtk_adsp_load.py root@steelix: + user@dev_host:~$ ssh steelix + + root@steelix:~ # ./mtk_adsp_load.py load zephyr.img + *** Booting Zephyr OS build v3.6.0-5820-gd2a89b3c089e *** + Hello World! mt8186_adsp/mt8186_adsp + +Debugging +========= + +Given the limited I/O facilities, debugging support remains limited on +these platforms. Users with access to hardware-level debug and trace +tools (e.g. from Cadence) will be able to use them as-is. Zephyr +debugging itself is limited to printk/logging techniques at the +moment. In theory a bidirectional console like winstream can be used +with gdb_stub, which has support on Xtensa and via the SDK debuggers, +but this is still unintegrated. + +Toolchains +********** + +The MT8195 toolchain is already part of the Zephyr SDK, so builds for +the ``mt8195//adsp`` board should work out of the box simply following +the generic Zephyr build instructions in the Getting Started guide. + +The MT8186 toolchain is not, and given the proliferation of Xtensa +toolchains in the SDK may not be. The overlay files for the device +are maintained by the SOF project, however, and building a toolchain +yourself using crosstools-ng is not difficult or time-consuming. This +script should work for most users: + +.. code-block:: shell + + #!/bin/sh + + TC=mtk_mt818x_adsp + + # Grab source (these are small) + git clone https://github.com/crosstool-ng/crosstool-ng + git clone https://github.com/thesofproject/xtensa-overlay + + # Build ct-ng itself + cd crosstool-ng + ./bootstrap + ./configure --enable-local + make -j$(nproc) + + mkdir overlays + (cd overlays; ln -s ../../xtensa-overlay/xtensa_mt8186.tar.gz xtensa_${TC}.tar.gz) + + # Construct a .config file + cat >.config < + +/dts-v1/; +/ { + #address-cells = <1>; + #size-cells = <1>; + + sram0: memory@4e100000 { + device_type = "memory"; + compatible = "mmio-sram"; + reg = <0x4e100000 DT_SIZE_K(1024)>; + }; + + dram0: memory@60000000 { + device_type = "memory"; + compatible = "mmio-sram"; + reg = <0x60000000 DT_SIZE_M(16)>; + }; + + dram1: memory@61000000 { + device_type = "memory"; + compatible = "mmio-sram"; + reg = <0x61000000 DT_SIZE_K(1024)>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + + core_intc: core_intc@0 { + compatible = "cdns,xtensa-core-intc"; + reg = <0 4>; + interrupt-controller; + #interrupt-cells = <3>; + }; + + intc2: intc@10680050 { + compatible = "mediatek,adsp_intc"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x10680050 4>; + status-reg = <0x10680010>; + interrupts = <2 0 0>; + mask = <0x3f>; + interrupt-parent = <&core_intc>; + }; + + ostimer64: ostimer64@10683080 { + compatible = "mediatek,ostimer64"; + reg = <0x10683080 28>; + }; + + ostimer0: ostimer@10683000 { + compatible = "mediatek,ostimer"; + reg = <0x10683000 16>; + interrupt-parent = <&core_intc>; + interrupts = <18 0 0>; + }; + + mbox0: mbox@10686100 { + compatible = "mediatek,mbox"; + reg = <0x10686100 16>; + interrupt-parent = <&intc2>; + interrupts = <1 0 0>; + }; + + mbox1: mbox@10687100 { + compatible = "mediatek,mbox"; + reg = <0x10687100 16>; + interrupt-parent = <&intc2>; + interrupts = <2 0 0>; + }; + }; /* soc */ + + chosen { }; + aliases { }; +}; diff --git a/boards/mediatek/mt8188/Kconfig.mt8188 b/boards/mediatek/mt8188/Kconfig.mt8188 new file mode 100644 index 00000000000..cc549945b91 --- /dev/null +++ b/boards/mediatek/mt8188/Kconfig.mt8188 @@ -0,0 +1,5 @@ +# Copyright 2024 The ChromiumOS Authors +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MT8188 + select SOC_MT8188 diff --git a/boards/mediatek/mt8188/board.yml b/boards/mediatek/mt8188/board.yml new file mode 100644 index 00000000000..f50e9227a82 --- /dev/null +++ b/boards/mediatek/mt8188/board.yml @@ -0,0 +1,5 @@ +boards: + - name: mt8188 + vendor: mediatek + socs: + - name: mt8188 diff --git a/boards/mediatek/mt8188/mt8188_adsp.dts b/boards/mediatek/mt8188/mt8188_adsp.dts new file mode 100644 index 00000000000..5f676bf1158 --- /dev/null +++ b/boards/mediatek/mt8188/mt8188_adsp.dts @@ -0,0 +1,81 @@ +/* Copyright 2024 The ChromiumOS Authors + * SPDX-License-Identifier: Apache-2.0 + */ +#include + +/dts-v1/; +/ { + + #address-cells = <1>; + #size-cells = <1>; + + sram0: memory@4e100000 { + device_type = "memory"; + compatible = "mmio-sram"; + reg = <0x4e100000 DT_SIZE_K(512)>; + }; + + dram0: memory@60000000 { + device_type = "memory"; + compatible = "mmio-sram"; + reg = <0x60000000 DT_SIZE_M(15)>; + }; + + dram1: memory@61000000 { + device_type = "memory"; + compatible = "mmio-sram"; + reg = <0x61000000 DT_SIZE_K(1024)>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + + core_intc: core_intc@0 { + compatible = "cdns,xtensa-core-intc"; + reg = <0 4>; + interrupt-controller; + #interrupt-cells = <3>; + }; + + intc2: intc@10b80050 { + compatible = "mediatek,adsp_intc"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x10b80050 4>; + status-reg = <0x10b80010>; + interrupts = <2 0 0>; + mask = <0x3f>; + interrupt-parent = <&core_intc>; + }; + + ostimer64: ostimer64@10b83080 { + compatible = "mediatek,ostimer64"; + reg = <0x10b83080 28>; + }; + + ostimer0: ostimer@10b83000 { + compatible = "mediatek,ostimer"; + reg = <0x10b83000 16>; + interrupt-parent = <&core_intc>; + interrupts = <18 0 0>; + }; + + mbox0: mbox@10b86100 { + compatible = "mediatek,mbox"; + reg = <0x10b86100 16>; + interrupt-parent = <&intc2>; + interrupts = <1 0 0>; + }; + + mbox1: mbox@10b87100 { + compatible = "mediatek,mbox"; + reg = <0x10b87100 16>; + interrupt-parent = <&intc2>; + interrupts = <2 0 0>; + }; + }; /* soc */ + + chosen { }; + aliases { }; +}; diff --git a/boards/mediatek/mt8195/Kconfig.mt8195 b/boards/mediatek/mt8195/Kconfig.mt8195 new file mode 100644 index 00000000000..0fb211185c9 --- /dev/null +++ b/boards/mediatek/mt8195/Kconfig.mt8195 @@ -0,0 +1,7 @@ +# Copyright 2023 The ChromiumOS Authors +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MT8195 + select SOC_MT8195 + help + Board with Mediatek MT8195 Audio DSP diff --git a/boards/mediatek/mt8195/board.yml b/boards/mediatek/mt8195/board.yml new file mode 100644 index 00000000000..7a9bb707c1d --- /dev/null +++ b/boards/mediatek/mt8195/board.yml @@ -0,0 +1,6 @@ +boards: + - name: mt8195 + full_name: MT8195 ADSP + vendor: mediatek + socs: + - name: mt8195 diff --git a/boards/mediatek/mt8195/mt8195_adsp.dts b/boards/mediatek/mt8195/mt8195_adsp.dts new file mode 100644 index 00000000000..76a2b94415a --- /dev/null +++ b/boards/mediatek/mt8195/mt8195_adsp.dts @@ -0,0 +1,100 @@ +/* Copyright 2023 The ChromiumOS Authors + * SPDX-License-Identifier: Apache-2.0 + */ +#include + +/dts-v1/; +/ { + + #address-cells = <1>; + #size-cells = <1>; + + sram0: memory@40000000 { + device_type = "memory"; + compatible = "mmio-sram"; + reg = <0x40000000 DT_SIZE_K(256)>; + }; + + dram0: memory@60000000 { + device_type = "memory"; + compatible = "mmio-sram"; + reg = <0x60000000 DT_SIZE_K(13824)>; + }; + + dram1: memory@60e80000 { + device_type = "memory"; + compatible = "mmio-sram"; + reg = <0x60e80000 DT_SIZE_K(2560)>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + + cpuclk: cpuclk@10000000 { + compatible = "mediatek,mt8195_cpuclk"; + reg = <0x10000000 380>; + cg_reg = <0x10720180>; + pll_ctrl_reg = <0x1000c7e0>; + freqs_mhz = <26 370 540 720>; + }; + + core_intc: core_intc@0 { + compatible = "cdns,xtensa-core-intc"; + reg = <0 4>; + interrupt-controller; + #interrupt-cells = <3>; + }; + + intc1: intc@10680130 { + compatible = "mediatek,adsp_intc"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x10680130 4>; + status-reg = <0x10680150>; + interrupts = <1 0 0>; + mask = <0x3ffffff0>; + interrupt-parent = <&core_intc>; + }; + + intc23: intc@108030f4 { + compatible = "mediatek,adsp_intc"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x108030f4 4>; + status-reg = <0x108030fc>; + interrupts = <23 0 0>; + mask = <0xffff>; + interrupt-parent = <&core_intc>; + }; + + ostimer64: ostimer64@1080d080 { + compatible = "mediatek,ostimer64"; + reg = <0x1080d080 28>; + }; + + ostimer0: ostimer@1080d000 { + compatible = "mediatek,ostimer"; + reg = <0x1080d000 16>; + interrupt-parent = <&intc23>; + interrupts = <11 0 0>; + }; + + mbox0: mbox@10816000 { + compatible = "mediatek,mbox"; + reg = <0x10816000 56>; + interrupt-parent = <&intc23>; + interrupts = <0 0 0>; + }; + + mbox1: mbox@10817000 { + compatible = "mediatek,mbox"; + reg = <0x10817000 56>; + interrupt-parent = <&intc23>; + interrupts = <1 0 0>; + }; + }; /* soc */ + + chosen { }; + aliases { }; +}; diff --git a/boards/mediatek/mt8195_adsp/Kconfig.defconfig b/boards/mediatek/mt8195_adsp/Kconfig.defconfig deleted file mode 100644 index 31f557670b1..00000000000 --- a/boards/mediatek/mt8195_adsp/Kconfig.defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright 2023 The ChromiumOS Authors -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_MT8195_ADSP - -config BOARD - default "mt8195_adsp" - -endif # BOARD_MT8195_ADSP diff --git a/boards/mediatek/mt8195_adsp/Kconfig.mt8195_adsp b/boards/mediatek/mt8195_adsp/Kconfig.mt8195_adsp deleted file mode 100644 index 43a3a49f9e1..00000000000 --- a/boards/mediatek/mt8195_adsp/Kconfig.mt8195_adsp +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright 2023 The ChromiumOS Authors -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_MT8195_ADSP - select SOC_MT8195_ADSP - help - Board with Mediatek MT8195 Audio DSP diff --git a/boards/mediatek/mt8195_adsp/board.yml b/boards/mediatek/mt8195_adsp/board.yml deleted file mode 100644 index a58b33ecf8d..00000000000 --- a/boards/mediatek/mt8195_adsp/board.yml +++ /dev/null @@ -1,6 +0,0 @@ -boards: - - name: mt8195_adsp - full_name: MT8195 ADSP - vendor: mediatek - socs: - - name: mt8195_adsp diff --git a/boards/mediatek/mt8195_adsp/mt8195_adsp.dts b/boards/mediatek/mt8195_adsp/mt8195_adsp.dts deleted file mode 100644 index c26e2dd0f40..00000000000 --- a/boards/mediatek/mt8195_adsp/mt8195_adsp.dts +++ /dev/null @@ -1,95 +0,0 @@ -/* Copyright 2023 The ChromiumOS Authors - * SPDX-License-Identifier: Apache-2.0 - */ -#include - -/dts-v1/; -/ { - -#address-cells = <1>; -#size-cells = <1>; - -sram0: memory@40000000 { - device_type = "memory"; - compatible = "mmio-sram"; - reg = <0x40000000 DT_SIZE_K(256)>; -}; - -dram0: memory@60000000 { - device_type = "memory"; - compatible = "mmio-sram"; - reg = <0x60000000 DT_SIZE_M(17)>; -}; - -soc { - #address-cells = <1>; - #size-cells = <1>; - - cpuclk: cpuclk@10000000 { - compatible = "mediatek,mt8195_cpuclk"; - reg = <0x10000000 380>; - cg_reg = <0x10720180>; - pll_ctrl_reg = <0x1000c7e0>; - freqs_mhz = <26 370 540 720>; - }; - - core_intc: core_intc@0 { - compatible = "cdns,xtensa-core-intc"; - reg = <0 4>; - interrupt-controller; - #interrupt-cells = <3>; - }; - - intc1: intc@10680130 { - compatible = "mediatek,adsp_intc"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x10680130 4>; - status-reg = <0x10680150>; - interrupts = <1 0 0>; - mask = <0x3ffffff0>; - interrupt-parent = <&core_intc>; - }; - - intc23: intc@108030f4 { - compatible = "mediatek,adsp_intc"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x108030f4 4>; - status-reg = <0x108030fc>; - interrupts = <23 0 0>; - mask = <0xffff>; - interrupt-parent = <&core_intc>; - }; - - ostimer64: ostimer64@1080d080 { - compatible = "mediatek,ostimer64"; - reg = <0x1080d080 28>; - }; - - ostimer0: ostimer@1080d000 { - compatible = "mediatek,ostimer"; - reg = <0x1080d000 16>; - interrupt-parent = <&intc23>; - interrupts = <11 0 0>; - }; - - mbox0: mbox@10816000 { - compatible = "mediatek,mbox"; - reg = <0x10816000 56>; - interrupt-parent = <&intc23>; - interrupts = <0 0 0>; - }; - - mbox1: mbox@10817000 { - compatible = "mediatek,mbox"; - reg = <0x10817000 56>; - interrupt-parent = <&intc23>; - interrupts = <1 0 0>; - }; -}; /* soc */ - -chosen { }; -aliases { }; - -}; diff --git a/boards/mediatek/mt8195_adsp/mt8195_adsp_defconfig b/boards/mediatek/mt8195_adsp/mt8195_adsp_defconfig deleted file mode 100644 index 1110a4cfeb1..00000000000 --- a/boards/mediatek/mt8195_adsp/mt8195_adsp_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright 2023 The ChromiumOS Authors -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=13000000 diff --git a/boards/mediatek/mt8196/Kconfig.mt8196 b/boards/mediatek/mt8196/Kconfig.mt8196 new file mode 100644 index 00000000000..7167a092755 --- /dev/null +++ b/boards/mediatek/mt8196/Kconfig.mt8196 @@ -0,0 +1,5 @@ +# Copyright 2024 The ChromiumOS Authors +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MT8196 + select SOC_MT8196 diff --git a/boards/mediatek/mt8196/board.yml b/boards/mediatek/mt8196/board.yml new file mode 100644 index 00000000000..cf5a2e27699 --- /dev/null +++ b/boards/mediatek/mt8196/board.yml @@ -0,0 +1,5 @@ +boards: + - name: mt8196 + vendor: mediatek + socs: + - name: mt8196 diff --git a/boards/mediatek/mt8196/mt8196_adsp.dts b/boards/mediatek/mt8196/mt8196_adsp.dts new file mode 100644 index 00000000000..27fc2f0048a --- /dev/null +++ b/boards/mediatek/mt8196/mt8196_adsp.dts @@ -0,0 +1,109 @@ +/* Copyright 2024 The ChromiumOS Authors + * SPDX-License-Identifier: Apache-2.0 + */ +#include + +/dts-v1/; +/ { + + #address-cells = <1>; + #size-cells = <1>; + + sram0: memory@4e100000 { + device_type = "memory"; + compatible = "mmio-sram"; + reg = <0x4e100000 DT_SIZE_K(512)>; + }; + + dram0: memory@90000000 { + device_type = "memory"; + compatible = "mmio-sram"; + reg = <0x90000000 DT_SIZE_M(6)>; + }; + + dram1: memory@90800000 { + device_type = "memory"; + compatible = "mmio-sram"; + reg = <0x90800000 DT_SIZE_M(1)>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + + core_intc: core_intc@0 { + compatible = "cdns,xtensa-core-intc"; + reg = <0 4>; + interrupt-controller; + #interrupt-cells = <3>; + }; + + /* The 8196 interrupt controller is actually more complicated + * than the driver here supports. There are 64 total + * interrupt inputs, each of which is a associated with one of + * 16 "groups", each of which is wired to a separate Xtensa + * architectural interrupt. (Whether the mapping of external + * interrupts to groups is mutable is an open question, the + * values here appear to be hardware defaults). We represent + * each group (strictly each of the high and low 32 interrupts + * of each group) as a separate adsp_intc controller, pointing + * at the same status and enable registers, but with disjoint + * masks. Note that this disallows configurations where a + * single controller needs to manage interrupts in both the + * high and low 32 bits of the set, but no current drivers + * rely on such a configuration. + */ + + intc_g1: intc_g1@1a014010 { + compatible = "mediatek,adsp_intc"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x1a014010 4>; + status-reg = <0x1a014008>; + mask = <0x00007f3f>; + interrupts = <1 0 0>; + interrupt-parent = <&core_intc>; + }; + + intc_g2: intc_g2@1a014010 { + compatible = "mediatek,adsp_intc"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x1a014010 4>; + status-reg = <0x1a014008>; + mask = <0x000000c0>; + interrupts = <2 0 0>; + interrupt-parent = <&core_intc>; + }; + + ostimer64: ostimer64@1a00b080 { + compatible = "mediatek,ostimer64"; + reg = <0x1a00b080 28>; + }; + + ostimer0: ostimer@1a00b000 { + compatible = "mediatek,ostimer"; + reg = <0x1a00b000 16>; + interrupt-parent = <&intc_g1>; + interrupts = <8 0 0>; + }; + + mbox0: mbox@1a350100 { + compatible = "mediatek,mbox"; + reg = <0x1a350100 16>; + interrupt-parent = <&intc_g2>; + interrupts = <6 0 0>; + }; + + mbox1: mbox@1a360100 { + compatible = "mediatek,mbox"; + reg = <0x1a360100 16>; + interrupt-parent = <&intc_g2>; + interrupts = <7 0 0>; + }; + }; /* soc */ + + chosen { }; + aliases { }; + +}; diff --git a/boards/mediatek/twister.yaml b/boards/mediatek/twister.yaml new file mode 100644 index 00000000000..e941f640048 --- /dev/null +++ b/boards/mediatek/twister.yaml @@ -0,0 +1,18 @@ +arch: xtensa +type: mcu +toolchain: + - xt-clang +testing: + ignore_tags: + - net + - bluetooth + - mcumgr +variants: + mt8195/mt8195/adsp: + name: MediaTek MT8195 Audio DSP + mt8188/mt8188/adsp: + name: MediaTek MT8188 Audio DSP + mt8186/mt8186/adsp: + name: MediaTek MT8186 Audio DSP + mt8196/mt8196/adsp: + name: MediaTek MT8196 Audio DSP diff --git a/boards/microchip/ev11l78a/doc/index.rst b/boards/microchip/ev11l78a/doc/index.rst index 2197ede6331..95d05add0c0 100644 --- a/boards/microchip/ev11l78a/doc/index.rst +++ b/boards/microchip/ev11l78a/doc/index.rst @@ -1,7 +1,4 @@ -.. _ev11l78a: - -UPD301C Basic Sink Application Example -###################################### +.. zephyr:board:: ev11l78a Overview ******** @@ -12,13 +9,6 @@ Programmable USB Power Delivery (PD) Controller. This RoHS-compliant evaluation platform comes in a small form factor and adheres to the USB Type-C™ Connector Specification and USB PD 3.0 specification. -.. figure:: img/ev11l78a.jpg - :width: 500px - :align: center - :alt: EV11L78A - - UPD301C Basic Sink Application Example (Credit: `Microchip Technology`_) - Hardware ******** diff --git a/boards/microchip/ev11l78a/ev11l78a.dts b/boards/microchip/ev11l78a/ev11l78a.dts index 02fa9f35915..5eb279c7ac2 100644 --- a/boards/microchip/ev11l78a/ev11l78a.dts +++ b/boards/microchip/ev11l78a/ev11l78a.dts @@ -39,7 +39,7 @@ csa_i_sense: i_sense { compatible = "current-sense-amplifier"; io-channels = <&adc 5>; - sense-resistor-micro-ohms = <4000>; + sense-resistor-milli-ohms = <4>; sense-gain-mult = <100>; }; diff --git a/boards/microchip/m2gl025_miv/doc/index.rst b/boards/microchip/m2gl025_miv/doc/index.rst index cc9a24c866b..88a4fa2b951 100644 --- a/boards/microchip/m2gl025_miv/doc/index.rst +++ b/boards/microchip/m2gl025_miv/doc/index.rst @@ -1,7 +1,4 @@ -.. _m2gl025-miv: - -Microchip M2GL025 Mi-V -###################### +.. zephyr:board:: m2gl025_miv Overview ******** diff --git a/boards/microchip/m2gl025_miv/m2gl025_miv.yaml b/boards/microchip/m2gl025_miv/m2gl025_miv.yaml index 4ba9e126a7f..692892d248d 100644 --- a/boards/microchip/m2gl025_miv/m2gl025_miv.yaml +++ b/boards/microchip/m2gl025_miv/m2gl025_miv.yaml @@ -5,8 +5,9 @@ arch: riscv toolchain: - zephyr ram: 64 -simulation: renode -simulation_exec: renode +simulation: + - name: renode + exec: renode testing: default: true ignore_tags: diff --git a/boards/microchip/mec1501modular_assy6885/doc/index.rst b/boards/microchip/mec1501modular_assy6885/doc/index.rst index a70c20ee961..910ba104da1 100644 --- a/boards/microchip/mec1501modular_assy6885/doc/index.rst +++ b/boards/microchip/mec1501modular_assy6885/doc/index.rst @@ -1,7 +1,4 @@ -.. _mec1501modular_assy6885: - -Microchip MEC1501 Modular card ASSY6885 -####################################### +.. zephyr:board:: mec1501modular_assy6885 Overview ******** @@ -10,10 +7,6 @@ The MEC1501 Modular card ASSY6885 is a development board to evaluate the Microch MEC152X series microcontrollers. This board can work standalone or be mated with any platform that complies with MECC specification. -.. image:: mec1501modular_assy6885.jpg - :align: center - :alt: MEC1501 Modular ASSY 6885 - Hardware ******** diff --git a/boards/microchip/mec1501modular_assy6885/mec1501modular_assy6885_defconfig b/boards/microchip/mec1501modular_assy6885/mec1501modular_assy6885_defconfig index 1f9a9f937c5..3039d18174e 100644 --- a/boards/microchip/mec1501modular_assy6885/mec1501modular_assy6885_defconfig +++ b/boards/microchip/mec1501modular_assy6885/mec1501modular_assy6885_defconfig @@ -10,11 +10,9 @@ CONFIG_SOC_MEC1501_VCI_PINS_AS_GPIOS=n CONFIG_RTOS_TIMER=y CONFIG_CLOCK_CONTROL=y -CONFIG_PINCTRL=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y CONFIG_GPIO=y -CONFIG_PINCTRL=y CONFIG_PM=y diff --git a/boards/microchip/mec15xxevb_assy6853/doc/index.rst b/boards/microchip/mec15xxevb_assy6853/doc/index.rst index 4eafd2e758c..c712d74b563 100644 --- a/boards/microchip/mec15xxevb_assy6853/doc/index.rst +++ b/boards/microchip/mec15xxevb_assy6853/doc/index.rst @@ -1,7 +1,4 @@ -.. _mec15xxevb_assy6853: - -Microchip MEC15xxEVB ASSY6853 -############################# +.. zephyr:board:: mec15xxevb_assy6853 Overview ******** @@ -15,10 +12,6 @@ been updated requiring a new SPI image tool. MEC1501 and MEC152x SPI image formats are not compatible with each other. Evaluation and cpu boards are compatible. -.. image:: mec15xxevb_assy6853.jpg - :align: center - :alt: MEC15XX EVB ASSY 6853 - Hardware ******** diff --git a/boards/microchip/mec15xxevb_assy6853/mec15xxevb_assy6853_defconfig b/boards/microchip/mec15xxevb_assy6853/mec15xxevb_assy6853_defconfig index ca03d9409cf..51e8498df60 100644 --- a/boards/microchip/mec15xxevb_assy6853/mec15xxevb_assy6853_defconfig +++ b/boards/microchip/mec15xxevb_assy6853/mec15xxevb_assy6853_defconfig @@ -9,11 +9,9 @@ CONFIG_RTOS_TIMER=y CONFIG_CLOCK_CONTROL=y CONFIG_CONSOLE=y -CONFIG_PINCTRL=y CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y CONFIG_GPIO=y -CONFIG_PINCTRL=y # power management stuff CONFIG_PM=y diff --git a/boards/microchip/mec172xevb_assy6906/doc/index.rst b/boards/microchip/mec172xevb_assy6906/doc/index.rst index 4765d787d94..0671beb4143 100644 --- a/boards/microchip/mec172xevb_assy6906/doc/index.rst +++ b/boards/microchip/mec172xevb_assy6906/doc/index.rst @@ -1,7 +1,4 @@ -.. _mec172xevb_assy6906: - -Microchip MEC172xEVB ASSY6906 -############################# +.. zephyr:board:: mec172xevb_assy6906 Overview ******** @@ -11,10 +8,6 @@ Microchip MEC172X series microcontrollers. This board needs to be mated with part number MEC172x 144WFBGA SOLDER DC ASSY 6914 (cpu board) in order to operate. MEC172x and MEC152x SPI image formats are not compatible with each other. -.. image:: mec172xevb_assy6906.jpg - :align: center - :alt: MEC172X EVB ASSY 6906 - Hardware ******** diff --git a/boards/microchip/mec172xevb_assy6906/mec172xevb_assy6906_defconfig b/boards/microchip/mec172xevb_assy6906/mec172xevb_assy6906_defconfig index a925bc7538d..d1aeaeaac58 100644 --- a/boards/microchip/mec172xevb_assy6906/mec172xevb_assy6906_defconfig +++ b/boards/microchip/mec172xevb_assy6906/mec172xevb_assy6906_defconfig @@ -8,7 +8,6 @@ CONFIG_RTOS_TIMER=y CONFIG_CLOCK_CONTROL=y CONFIG_GPIO=y -CONFIG_PINCTRL=y CONFIG_SERIAL=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y diff --git a/boards/microchip/mec172xmodular_assy6930/doc/mec172xmodular_assy6930.rst b/boards/microchip/mec172xmodular_assy6930/doc/mec172xmodular_assy6930.rst index a85226e87d0..a6bc75fc8fb 100644 --- a/boards/microchip/mec172xmodular_assy6930/doc/mec172xmodular_assy6930.rst +++ b/boards/microchip/mec172xmodular_assy6930/doc/mec172xmodular_assy6930.rst @@ -1,7 +1,4 @@ -.. _mec172xmodular_6930: - -Microchip MEC172x Modular Card ASSY6930 (Rev. B) -################################################ +.. zephyr:board:: mec172xmodular_assy6930 Overview ******** @@ -9,13 +6,6 @@ The MEC172x Modular Card ASSY6930 (Rev. B) is a development board to evaluate th Microchip MEC172X series microcontrollers. This board can work standalone or be mated with any platform that complies with MECC specification. - -.. image:: ./mec172xmodular_assy6930.jpg - :width: 576px - :align: center - :alt: MEC172x Modular ASSY 6930 - - Hardware ******** diff --git a/boards/microchip/mec172xmodular_assy6930/mec172xmodular_assy6930_defconfig b/boards/microchip/mec172xmodular_assy6930/mec172xmodular_assy6930_defconfig index 0df404e408f..c191b0b1555 100644 --- a/boards/microchip/mec172xmodular_assy6930/mec172xmodular_assy6930_defconfig +++ b/boards/microchip/mec172xmodular_assy6930/mec172xmodular_assy6930_defconfig @@ -8,7 +8,6 @@ CONFIG_RTOS_TIMER=y CONFIG_CLOCK_CONTROL=y CONFIG_GPIO=y -CONFIG_PINCTRL=y CONFIG_SERIAL=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y diff --git a/boards/microchip/mpfs_icicle/doc/index.rst b/boards/microchip/mpfs_icicle/doc/index.rst index 10ab696ae03..ee5d07b5bda 100644 --- a/boards/microchip/mpfs_icicle/doc/index.rst +++ b/boards/microchip/mpfs_icicle/doc/index.rst @@ -1,7 +1,4 @@ -.. _mpfs_icicle: - -Microchip mpfs_icicle -##################### +.. zephyr:board:: mpfs_icicle Overview ******** diff --git a/boards/mikroe/clicker_2/doc/mikroe_clicker_2.rst b/boards/mikroe/clicker_2/doc/mikroe_clicker_2.rst index a1ef4aa09ec..a33f76d8beb 100644 --- a/boards/mikroe/clicker_2/doc/mikroe_clicker_2.rst +++ b/boards/mikroe/clicker_2/doc/mikroe_clicker_2.rst @@ -1,7 +1,4 @@ -.. _mikroe_clicker_2: - -MikroE Clicker 2 for STM32 -########################## +.. zephyr:board:: mikroe_clicker_2 Overview ******** @@ -12,13 +9,6 @@ The board also has battery connection and a battery management unit on board. It can be powered either from a battery pack, such as a LiPo or from USB. The board is equipped with a 25MHz crystal as well as a 32.768kHz clock crystal. - -.. figure:: img/clicker-2-stm32f4-thickbox_default-2.jpg - :align: center - :alt: Clicker 2 For STM32 - - Clicker 2 For STM32 (Credit: MikroElektronika d.o.o.) - Hardware ******** The Clicker 2 board contains the following connections: diff --git a/boards/mikroe/clicker_2/mikroe_clicker_2.dts b/boards/mikroe/clicker_2/mikroe_clicker_2.dts index 74ec6b395bb..aba4652f126 100644 --- a/boards/mikroe/clicker_2/mikroe_clicker_2.dts +++ b/boards/mikroe/clicker_2/mikroe_clicker_2.dts @@ -146,7 +146,7 @@ zephyr_udc0: &usbotg_fs { status ="okay"; pinctrl-0 = <&adc1_in2_pa2 &adc1_in3_pa3>; pinctrl-names = "default"; - st,adc-clock-source = ; + st,adc-clock-source = "SYNC"; st,adc-prescaler = <2>; }; diff --git a/boards/mikroe/clicker_ra4m1/doc/index.rst b/boards/mikroe/clicker_ra4m1/doc/index.rst index 5af9aa1125a..56099ee6f42 100644 --- a/boards/mikroe/clicker_ra4m1/doc/index.rst +++ b/boards/mikroe/clicker_ra4m1/doc/index.rst @@ -1,7 +1,4 @@ -.. _mikroe_clicker_ra4m1: - -Mikroe Clicker RA4M1 -#################### +.. zephyr:board:: mikroe_clicker_ra4m1 Overview ******** @@ -10,12 +7,6 @@ The Mikroe Clicker RA4M1 development board contains a Renesas Cortex-M4 based R7FA4M1AB3CFM Microcontroller operating at up to 48 MHz with 256 KB of Flash memory and 32 KB of SRAM. -.. figure:: img/mikroe_clicker_ra4m1.jpg - :align: center - :alt: Clicker RA4M1 - - Clicker RA4M1 (Credit: MikroElektronika d.o.o.) - Hardware ******** diff --git a/boards/mikroe/clicker_ra4m1/mikroe_clicker_ra4m1.dts b/boards/mikroe/clicker_ra4m1/mikroe_clicker_ra4m1.dts index b15242c5fea..5a626a78364 100644 --- a/boards/mikroe/clicker_ra4m1/mikroe_clicker_ra4m1.dts +++ b/boards/mikroe/clicker_ra4m1/mikroe_clicker_ra4m1.dts @@ -6,9 +6,9 @@ /dts-v1/; #include -#include #include #include +#include / { model = "Mikroe Clicker RA4M1"; @@ -42,6 +42,29 @@ }; }; + mikrobus_header: mikrobus-connector { + compatible = "mikro-bus"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &ioport0 0 0>, /* AN */ + <1 0 &ioport4 7 0>, /* RST */ + <2 0 &ioport1 3 0>, /* CS */ + <3 0 &ioport1 2 0>, /* SCK */ + <4 0 &ioport1 0 0>, /* MISO */ + <5 0 &ioport1 1 0>, /* MOSI */ + /* +3.3V */ + /* GND */ + <6 0 &ioport1 7 0>, /* PWM */ + <7 0 &ioport3 2 0>, /* INT */ + <8 0 &ioport4 10 0>, /* RX */ + <9 0 &ioport4 11 0>, /* TX */ + <10 0 &ioport2 5 0>, /* SCL */ + <11 0 &ioport2 6 0>; /* SDA */ + /* +5V */ + /* GND */ + }; + aliases { led0 = &ld1; led1 = &ld2; @@ -52,7 +75,12 @@ &pinctrl { sci0_default: sci0_default { group1 { - pinmux = , ; + /* tx */ + psels = ; + }; + group2 { + /* rx */ + psels = ; }; }; }; @@ -67,6 +95,18 @@ }; }; +&ioport0 { + status = "okay"; +}; + +&ioport1 { + status = "okay"; +}; + +&ioport2 { + status = "okay"; +}; + &ioport3 { status = "okay"; }; @@ -79,17 +119,35 @@ status = "okay"; }; -&mosc { +&xtal { status = "okay"; clock-frequency = <12000000>; }; -&cgc { - clock-source = <&mosc>; - iclk-div = <1>; - pclka-div = <1>; - pclkb-div = <2>; - pclkc-div = <1>; - pclkd-div = <1>; - fclk-div = <2>; +&pclkblock { + clocks = <&xtal>; +}; + +&iclk { + div = <1>; +}; + +&pclka { + div = <1>; +}; + +&pclkb { + div = <2>; +}; + +&pclkc { + div = <1>; +}; + +&pclkd { + div = <1>; +}; + +&fclk { + div = <2>; }; diff --git a/boards/mikroe/clicker_ra4m1/mikroe_clicker_ra4m1_defconfig b/boards/mikroe/clicker_ra4m1/mikroe_clicker_ra4m1_defconfig index 3d89bdc283d..2e434ba45ea 100644 --- a/boards/mikroe/clicker_ra4m1/mikroe_clicker_ra4m1_defconfig +++ b/boards/mikroe/clicker_ra4m1/mikroe_clicker_ra4m1_defconfig @@ -5,18 +5,15 @@ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=12000000 CONFIG_BUILD_OUTPUT_HEX=y -# enable uart driver +# Enable uart driver CONFIG_SERIAL=y -# enable console +# Enable console CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y -# enable GPIO +# Enable GPIO CONFIG_GPIO=y -# enable pin controller -CONFIG_PINCTRL=y - -# enable Clocks +# Enable Clocks CONFIG_CLOCK_CONTROL=y diff --git a/boards/mikroe/mini_m4_for_stm32/doc/mikroe_mini_m4_for_stm32.rst b/boards/mikroe/mini_m4_for_stm32/doc/mikroe_mini_m4_for_stm32.rst index 6194953b1da..02208b66bf3 100644 --- a/boards/mikroe/mini_m4_for_stm32/doc/mikroe_mini_m4_for_stm32.rst +++ b/boards/mikroe/mini_m4_for_stm32/doc/mikroe_mini_m4_for_stm32.rst @@ -1,7 +1,4 @@ -.. _mikroe_mini_m4_for_stm32: - -Mikroe MINI-M4 for STM32 -######################## +.. zephyr:board:: mikroe_mini_m4_for_stm32 Overview ******** @@ -15,10 +12,6 @@ It has a reset button and three signal LEDs. It operates on a 3.3V power supply. An on-board voltage regulator allows the board to be powered directly from a USB cable. -.. image:: img/mikroe_mini_m4_for_stm32.jpg - :align: center - :alt: MINI-M4 for STM32 - Pin Mapping =========== diff --git a/boards/mikroe/mini_m4_for_stm32/mikroe_mini_m4_for_stm32.yaml b/boards/mikroe/mini_m4_for_stm32/mikroe_mini_m4_for_stm32.yaml index 479eb6e4887..e83b864f1ab 100644 --- a/boards/mikroe/mini_m4_for_stm32/mikroe_mini_m4_for_stm32.yaml +++ b/boards/mikroe/mini_m4_for_stm32/mikroe_mini_m4_for_stm32.yaml @@ -14,5 +14,4 @@ supported: - i2c - spi - pwm - - usb vendor: mikroe diff --git a/boards/mikroe/stm32_m4_clicker/Kconfig.defconfig b/boards/mikroe/stm32_m4_clicker/Kconfig.defconfig index 082d099f4b8..6caedb91cfc 100644 --- a/boards/mikroe/stm32_m4_clicker/Kconfig.defconfig +++ b/boards/mikroe/stm32_m4_clicker/Kconfig.defconfig @@ -3,22 +3,6 @@ if BOARD_MIKROE_STM32_M4_CLICKER -if USB_DEVICE_STACK - -config UART_CONSOLE - default CONSOLE - -config USB_DEVICE_INITIALIZE_AT_BOOT - default y - -endif # USB_DEVICE_STACK - -if LOG - -# Logger cannot use itself to log -config USB_CDC_ACM_LOG_LEVEL - default 0 - -endif # LOG +source "boards/common/usb/Kconfig.cdc_acm_serial.defconfig" endif # BOARD_MIKROE_STM32_M4_CLICKER diff --git a/boards/mikroe/stm32_m4_clicker/doc/index.rst b/boards/mikroe/stm32_m4_clicker/doc/index.rst index c1f9f809ac7..8bddfd3f7aa 100644 --- a/boards/mikroe/stm32_m4_clicker/doc/index.rst +++ b/boards/mikroe/stm32_m4_clicker/doc/index.rst @@ -1,7 +1,4 @@ -.. _mikroe_stm32_m4_clicker: - -Mikroe STM32 M4 Clicker -####################### +.. zephyr:board:: mikroe_stm32_m4_clicker Overview ******** @@ -10,12 +7,6 @@ The Mikroe STM32 M4 Clicker development board contains a STMicroelectronics Cortex-M4 based STM32F415RG Microcontroller operating at up to 168 MHz with 1 MB of Flash memory and 192 KB of SRAM. -.. figure:: img/stm32_m4_clicker.webp - :align: center - :alt: STM32 M4 Clicker - - STM32 M4 Clicker (Credit: MikroElektronika d.o.o.) - Hardware ******** diff --git a/boards/mikroe/stm32_m4_clicker/mikroe_stm32_m4_clicker.dts b/boards/mikroe/stm32_m4_clicker/mikroe_stm32_m4_clicker.dts index 1fa6b5f0762..b6225a2579f 100644 --- a/boards/mikroe/stm32_m4_clicker/mikroe_stm32_m4_clicker.dts +++ b/boards/mikroe/stm32_m4_clicker/mikroe_stm32_m4_clicker.dts @@ -14,8 +14,6 @@ compatible = "st,stm32f415rg"; chosen { - zephyr,console = &usb_cdc_acm_uart; - zephyr,shell-uart = &usb_cdc_acm_uart; zephyr,sram = &sram0; zephyr,flash = &flash0; }; @@ -62,7 +60,7 @@ <6 0 &gpiob 0 0>, /* PWM */ <7 0 &gpiob 1 0>, /* INT */ <8 0 &gpioc 11 0>, /* RX */ - <9 0 &gpioc 12 0>, /* TX */ + <9 0 &gpioc 10 0>, /* TX */ <10 0 &gpiob 10 0>, /* SCL */ <11 0 &gpiob 11 0>; /* SDA */ /* +5V */ @@ -126,12 +124,10 @@ zephyr_udc0: &usbotg_fs { pinctrl-0 = <&usb_otg_fs_dm_pa11 &usb_otg_fs_dp_pa12>; pinctrl-names = "default"; status = "okay"; - - usb_cdc_acm_uart: cdc_acm_uart { - compatible = "zephyr,cdc-acm-uart"; - }; }; +#include <../boards/common/usb/cdc_acm_serial.dtsi> + mikrobus_spi: &spi2 {}; mikrobus_serial: &usart3 {}; mikrobus_i2c: &i2c2 {}; diff --git a/boards/mikroe/stm32_m4_clicker/mikroe_stm32_m4_clicker_defconfig b/boards/mikroe/stm32_m4_clicker/mikroe_stm32_m4_clicker_defconfig index f964f048f77..549aff1e682 100644 --- a/boards/mikroe/stm32_m4_clicker/mikroe_stm32_m4_clicker_defconfig +++ b/boards/mikroe/stm32_m4_clicker/mikroe_stm32_m4_clicker_defconfig @@ -16,6 +16,3 @@ CONFIG_GPIO=y # Enable Clocks CONFIG_CLOCK_CONTROL=y - -# Enable USB -CONFIG_USB_DEVICE_STACK=y diff --git a/boards/mxchip/az3166_iotdevkit/doc/index.rst b/boards/mxchip/az3166_iotdevkit/doc/index.rst index 694d53517a6..230073f8295 100644 --- a/boards/mxchip/az3166_iotdevkit/doc/index.rst +++ b/boards/mxchip/az3166_iotdevkit/doc/index.rst @@ -1,7 +1,4 @@ -.. _az3166_iotdevkit: - -AZ3166 MXChip IoT DevKit -######################## +.. zephyr:board:: az3166_iotdevkit Overview ******** @@ -11,12 +8,6 @@ projects. It's an all-in-one board powered by an Arm Cortex-M4 processor. On-boa include an OLED screen, headphone output, stereo microphone and abundant sensors like humidity & temperature, pressure, motion (accelerometer & gyroscope) and magnetometer. -.. figure:: img/az3166-iotdevkit.webp - :align: center - :alt: AZ3166 MXChip IoT DevKit - - AZ3166 MXChip IoT DevKit (Credit: MXChip) - More information about the board can be found at the `MXChip AZ3166 website`_. Hardware diff --git a/boards/native/doc/arch_soc.rst b/boards/native/doc/arch_soc.rst index d07a9c589a2..8906001f177 100644 --- a/boards/native/doc/arch_soc.rst +++ b/boards/native/doc/arch_soc.rst @@ -11,8 +11,8 @@ The POSIX architecture Overview ******** -The POSIX architecture, in combination with the inf_clock SOC layer, -provides the foundation, architecture and SOC layers for a set of virtual test +The native simulator in combination with the POSIX architecture and the inf_clock SOC layer, +provide the foundation, architecture and SOC layers for a set of virtual test boards. Using these, a Zephyr application can be compiled together with @@ -63,8 +63,8 @@ This port is designed and tested to run in Linux. .. note:: - The 32 bit version of this port does not directly work in Windows Subsystem - for Linux (WSL) because WSL does not support native 32-bit binaries. + The 32 bit version of this port does not directly work in the old Windows Subsystem + for Linux (WSL1) because WSL1 does not support native 32-bit binaries. You may want to consider WSL2, or, if using :ref:`native_sim `, you can also just use the ``native_sim/native/64`` target: Check :ref:`32 and 64bit versions`. @@ -304,128 +304,171 @@ side-effects. Architecture and design *********************** -.. figure:: layering.svg +.. note:: + + This section does not describe anymore the old :ref:`native_posix` or + :kconfig:option:`CONFIG_NATIVE_APPLICATION` based architecture. + It only describes the new native simulator based architecture used by targets built with the + :kconfig:option:`CONFIG_NATIVE_LIBRARY` option. + +.. note:: + + This description applies to the boards on the tree, + but it is not a requirement for other POSIX arch based boards to follow what is described here. + +.. figure:: layering_natsim.svg + :align: center + :alt: Zephyr layering in a native simulator build + :figclass: align-center + + Zephyr layering when built against an embedded target (left), and targeting a native_simulator + based board (right) + +.. figure:: components_natsim.svg :align: center - :alt: Zephyr layering in native build + :alt: native_sim boards and the native simulator :figclass: align-center - Zephyr layering when built against an embedded target (left), and - targeting a POSIX arch based board (right) + Relationship between Zephyr, the native_sim target and the native simulator + +When building targeting Zephyr's :ref:`native_sim` board, we build our embedded SW, +that is, our application, the Zephyr kernel, and any subsystems and drivers we have selected, +with the :ref:`POSIX architecture` and the +:ref:`inf_clock` SOC layers. +The result of this build is a pre-linked elf library, which contains what we can call the +embedded SW. +Then the `native simulator `_ runner will be built. +And after both the "embedded SW" and the runner will be linked together to form the final Linux +executable. +This final executable is typically called ``zephyr.exe`` and can be run or debugged just like any +other normal Linux executable. + +The native simulator runner provides the Linux program entry point, command line argument parsing, +the HW models scheduler, as well as a component to emulate the CPU start/stop and CPU thread +switching. +It also provides a mechanism to register functions which need to be run at different points of the +executable lifetime. +When targeting native_sim, the native simulator is also built with some basic HW models like a +system timer and an interrupt controller. +You can find more information on these in the +`native simulator design documentation `_. + +The native_sim target is a single microcontroller (MCU) target with simple HW models. Other targets +like the :ref:`simulated nRF5340 (nrf5340bsim)` are multi MCU targets. Where one +embedded Zephyr image can be build for each MCU, and all MCU images and the runner are assembled +together into one executable with more elaborate HW models of those SOCs. + +Native simulator runner context and the embedded context +======================================================== + +It is worth noting that the embedded SW library is first pre-linked. That is that all symbols which +can be resolved inside that library will be resolved. And that, after, all these library symbols, +except a selected few marked with an special annotation, will be hidden from further linking. +In this way, the runner link stage will not link to or conflict with any of these hidden symbols, +neither from the runner itself or from other CPUs embedded SW libraries. +It is also worth noting that all expected Zephyr sections are built and ordered with the Zephyr +linker script in that first embedded SW library link. + +When the embedded SW is built, one has the option of linking an embedded C standard library with it, +or leave at that point all C library calls unresolved, and let them be linked in the final stage +with the host C library. + +Due to all this, we can conceptually see our build divided in two separate contexts: +One is the embedded/Zephyr context, in which we build the Zephyr OS, an application for a given MCU, +and which may be built with an embedded C library. +Another is the runner context, which is always built with the host C library and which has very +limited visibility into the embedded context. + +From the embedded context we can easily call into the runner context: All runner context symbols +will be linkable in the final link stage unless another embedded symbol with the same name was +already linked to it in the first pass. +But from the runner context only the symbols from the embedded context annotated with the +``NATIVE_SIMULATOR_IF`` macro will be linkable. + +From Zephyr's build system it is possible to request a file to be built in the runner context by +adding it to the cmake ``native_simulator`` library target. You can check +:zephyr_file:`arch/posix/CMakeLists.txt` for more information. + +You can find more information in the native simulator +`build documentation `_ .. _posix_arch_design_archl: Arch layer ========== -In this architecture each Zephyr thread is mapped to one POSIX pthread. -The POSIX architecture emulates a single threaded CPU/MCU by only allowing -one SW thread to execute at a time, as commanded by the Zephyr kernel. -Whenever the Zephyr kernel desires to context switch two threads, -the POSIX arch blocks and unblocks the corresponding pthreads. +The POSIX architecture is mainly responsible for two things: + +* Set up the Zephyr build to produce an static library for the host architecture to be later + used with the native simulator build and linked with the native simulator runner. +* Provide a thin adaptation between the API the Zephyr kernel expects from an architecture + layer and the native simulator CPU threading emulation (NCT). + +This layer together with the NCT maps each Zephyr thread into one POSIX pthread, and emulates a +single threaded CPU/MCU by only allowing one SW thread to execute at a time, as commanded by the +Zephyr kernel. Whenever the Zephyr kernel desires to context switch two threads, the POSIX arch, +using NCT, blocks and unblocks the corresponding pthreads. This architecture provides the same interface to the Kernel as other architectures and is therefore transparent for the application. +Note that all threads use a normal Linux pthread stack, and do not use +the Zephyr thread stack allocation for their call stacks or automatic +variables. The Zephyr stacks (which are allocated in "static memory") are +only used by the POSIX architecture to keep thread bookkeeping data. + When using this architecture, the code is compiled natively for the host system, and typically as a 32-bit binary assuming pointer and integer types are 32-bits wide. -Note that all threads use a normal Linux pthread stack, and do not use -the Zephyr thread stack allocation for their call stacks or automatic -variables. The Zephyr stacks (which are allocated in "static memory") are -only used by the POSIX architecture for thread bookkeeping. +.. _posix_arch_design_socl: -SOC and board layers -==================== +SOC layer +========= -.. note:: +This SOC layer is mainly a very thin layer on top of the native simulator CPU emulation layer, +which is responsible for handling the simulation of the CPU start/stop, as well as the +initialization of the arch layer, and calling into the Zephyr boot (:c:func:`z_cstart()`) during +the CPU boot itself. + +It also provides the :ref:`native_tasks`, and specifies +a few other hooks it expects the board layer to provide. + +Board layer +=========== + +The board layer is responsible to provide all the hooks the SOC layer and native simulator runner +expect. This includes the hooks to boot the CPU (which call into the SOC layer), to handle +interrupts, and the hooks for low level tracing and busy wait handling. + +The overall execution and scheduling is handled by the native simulator runner itself, which calls +when necessary into the board layer hooks. +You can find information about how the native simulator runs the embedded SW in its +`design documentation `_ + +For more complex simulated boards, like :ref:`bsim ones`, the board layer also provides +the necessary logic and configuration to mimic a real target and SOC. + +Note that the SOC/board split in this architecture is different than for other Zephyr targets. +This was done to enable very different real SOC simulations to share a common architecture and SOC +layer, while placing the real SOC specific replacement logic in the board layer. - This description applies to all current POSIX arch based boards on tree, - but it is not a requirement for another board to follow what is described here. - -When the executable process is started (that is the board -:c:func:`main`, which is the linux executable C :c:func:`main`), -first, early initialization steps are taken care of -(command line argument parsing, initialization of the HW models, etc). - -After, the "CPU simulation" is started, by creating a new pthread -and provisionally blocking the original thread. The original thread will only -be used for HW models after this; -while this newly created thread will be the first "SW" thread and start -executing the boot of the embedded code (including the POSIX arch code). - -During this MCU boot process, the Zephyr kernel will be initialized and -eventually this will call into the embedded application ``main()``, -just like in the embedded target. -As the embedded SW execution progresses, more Zephyr threads may be spawned, -and for each the POSIX architecture will create a dedicated pthread. - -Eventually the simulated CPU will be put to sleep by the embedded SW -(normally when the boot is completed). This whole simulated CPU boot, -until the first time it goes to sleep happens in 0 simulated time. - -At this point the last executing SW pthread will be blocked, -and the first thread (reserved for the HW models now) will be allowed -to execute again. This thread will, from now on, be the one handling both the -HW models and the device simulated time. - -The HW models are designed around timed events, -and this thread will check what is the next -scheduled HW event, advance simulated time until that point, and call the -corresponding HW model event function. - -Eventually one of these HW models will raise an interrupt to the -simulated CPU. When the IRQ controller wants to wake the simulated -CPU, the HW thread is blocked, and the simulated CPU is awakened by -letting the last SW thread continue executing. - -This process of getting the CPU to sleep, letting the HW models run, -and raising an interrupt which wake the CPU again is repeated until the end -of the simulation, where the CPU execution always takes 0 simulated time. - -When a SW thread is awakened by an interrupt, it will be made to enter the -interrupt handler by the soc_inf code. - -If the SW unmasks a pending interrupt while running, or triggers a SW -interrupt, the interrupt controller may raise the interrupt immediately -depending on interrupt priorities, masking, and locking state. - -Interrupts are executed in the context (and using the stack) of the SW -thread in which they are received. Meaning, there is no dedicated thread or -stack for interrupt handling. - -To ensure determinism when the Zephyr code is running, -and to ease application debugging, -the board uses a different time than real time: simulated time. -How and if simulated time relates to the host time, is up to the simulated -board. - -The Zephyr application sees the code executing as if the CPU were running at -an infinitely fast clock, and fully decoupled from the underlying host CPU -speed. -No simulated time passes while the application or kernel code execute. .. _posix_busy_wait: Busy waits ========== -Busy waits work thanks to provided board functionality. -This does not need to be the same for all boards, but both native_sim and the -nrf52_bsim board work similarly thru the combination of a board specific -:c:func:`arch_busy_wait()` and a special fake HW timer (provided by the board). +Busy waits work thanks to logic provided by the board and native simulator. +This does not need to be the same for all boards, but both :ref:`native_sim` and the +:ref:`nrf*bsim boards` work similarly through the combination of a board specific +:c:func:`arch_busy_wait()` and an special fake HW timer provided by the native simulator. -When a SW thread wants to busy wait, this fake timer will be programmed in -the future time corresponding to the end of the busy wait and the CPU will -be put immediately to sleep in the busy_wait caller context. -When this fake HW timer expires the CPU will be waken with a special -non-maskable phony interrupt which does not have a corresponding interrupt -handler but will resume the busy_wait SW execution. -Note that other interrupts may arrive while the busy wait is in progress, -which may delay the :c:func:`k_busy_wait()` return just like in real life. +Please check the +`native simulator busy wait design documentation `_ +for more info. -Interrupts may be locked out or masked during this time, but the special -fake-timer non-maskable interrupt will wake the CPU nonetheless. +.. _posix_arch_design_native_tasks: NATIVE_TASKS @@ -433,9 +476,13 @@ NATIVE_TASKS The soc_inf layer provides a special type of hook called the NATIVE_TASKS. -These allow registering (at build/link time) functions which will be called +These allow registering (at build/link time) embedded context functions which will be called at different stages during the process execution: Before command line parsing (so dynamic command line arguments can be registered using this hook), before initialization of the HW models, before the simulated CPU is started, after the simulated CPU goes to sleep for the first time, and when the application exists. + +These hooks are ultimately based on the +`native simulator tasks `_ +which the users may also register from code built in the runner context. diff --git a/boards/native/doc/components_natsim.svg b/boards/native/doc/components_natsim.svg new file mode 100644 index 00000000000..01723d32ed4 --- /dev/null +++ b/boards/native/doc/components_natsim.svg @@ -0,0 +1,4 @@ + + + +
Zephyr's native_sim target
Zephyr's native_sim...
native simulator
native simulator
Uses
Uses
Embedded SW:
Application + Zephyr kernel + subsystems + drivers
Embedded SW:...
Built for
Built for \ No newline at end of file diff --git a/boards/native/native_posix/native_posix.yaml b/boards/native/native_posix/native_posix.yaml index d3ba08cc9a6..28601c1647e 100644 --- a/boards/native/native_posix/native_posix.yaml +++ b/boards/native/native_posix/native_posix.yaml @@ -1,7 +1,8 @@ identifier: native_posix name: Native 32-bit POSIX port type: native -simulation: native +simulation: + - name: native arch: posix ram: 65536 flash: 65536 @@ -11,6 +12,7 @@ toolchain: supported: - can - counter + - display - dma - eeprom - netif:eth diff --git a/boards/native/native_posix/native_posix_native_64.yaml b/boards/native/native_posix/native_posix_native_64.yaml index f7081ced878..5510fc9ac50 100644 --- a/boards/native/native_posix/native_posix_native_64.yaml +++ b/boards/native/native_posix/native_posix_native_64.yaml @@ -1,7 +1,8 @@ identifier: native_posix/native/64 name: Native 64-bit POSIX port type: native -simulation: native +simulation: + - name: native arch: posix ram: 65536 flash: 65536 @@ -11,6 +12,7 @@ toolchain: supported: - can - counter + - display - dma - eeprom - netif:eth diff --git a/boards/native/native_sim/Kconfig b/boards/native/native_sim/Kconfig index c2610e840e7..fc84adda149 100644 --- a/boards/native/native_sim/Kconfig +++ b/boards/native/native_sim/Kconfig @@ -18,12 +18,13 @@ comment "Native Simular (Single Core) options" config NATIVE_SIM_NATIVE_POSIX_COMPAT bool "Pretend to be a native_posix board" - default y + select DEPRECATED help When this option is set the native_sim board will pretend to be a native_posix board from kconfig point of view, to allow using it directly with code which was meant for the native_posix board and checks for the macro CONFIG_BOARD_NATIVE_POSIX, or requires other kconfig options which depend on it. + This option is deprecated and will be removed in Zephyr v4.3 config NATIVE_SIM_SLOWDOWN_TO_REAL_TIME bool "Slow down execution to real time" diff --git a/boards/native/native_sim/Kconfig.defconfig b/boards/native/native_sim/Kconfig.defconfig index 0cb80bbcf45..c74a9fe041e 100644 --- a/boards/native/native_sim/Kconfig.defconfig +++ b/boards/native/native_sim/Kconfig.defconfig @@ -32,5 +32,4 @@ config UART_CONSOLE endif # CONSOLE - endif # BOARD_NATIVE_SIM diff --git a/boards/native/native_sim/doc/index.rst b/boards/native/native_sim/doc/index.rst index 3f6033884b3..5e8ec87935c 100644 --- a/boards/native/native_sim/doc/index.rst +++ b/boards/native/native_sim/doc/index.rst @@ -425,13 +425,14 @@ The following peripherals are currently provided with this board: A display driver is provided that creates a window on the host machine to render display content. - This driver requires a 32-bit version of the `SDL2`_ library on the host - machine and ``pkg-config`` settings to correctly pickup the SDL2 install path - and compiler flags. + When building for the default 32bit ``native_sim`` target this driver requires a 32-bit version of + the `SDL2`_ development library on the host machine. For + :ref:`64bit native_sim` builds you need to have the 64bit version installed. + You may also need to set ``pkg-config`` to correctly pickup the SDL2 install path. - On a Ubuntu 22.04 host system, for example, install the ``pkg-config`` and - ``libsdl2-dev:i386`` packages, and configure the pkg-config search path with - these commands: + On Ubuntu the package is ``libsdl2-dev`` whose 64bit version is likely installed by default. + On an Ubuntu 18.04 host system, you can install the ``pkg-config`` and the 32bit + ``libsdl2-dev:i386`` packages, and configure the pkg-config search path with these commands: .. code-block:: console @@ -441,7 +442,7 @@ The following peripherals are currently provided with this board: $ export PKG_CONFIG_PATH=/usr/lib/i386-linux-gnu/pkgconfig .. _SDL2: - https://www.libsdl.org/download-2.0.php + https://www.libsdl.org .. _nsim_per_flash_simu: @@ -702,7 +703,7 @@ host libC (:kconfig:option:`CONFIG_EXTERNAL_LIBC`): Console backend, :ref:`POSIX arch console `, :kconfig:option:`CONFIG_POSIX_ARCH_CONSOLE`, All Display, :ref:`Display SDL `, :kconfig:option:`CONFIG_SDL_DISPLAY`, All Entropy, :ref:`Native posix entropy `, :kconfig:option:`CONFIG_FAKE_ENTROPY_NATIVE_POSIX`, All - EEPROM, EEPROM simulator, :kconfig:option:`CONFIG_EEPROM_SIMULATOR`, Host libC + EEPROM, EEPROM simulator, :kconfig:option:`CONFIG_EEPROM_SIMULATOR`, All EEPROM, EEPROM emulator, :kconfig:option:`CONFIG_EEPROM_EMULATOR`, All Ethernet, :ref:`Eth native_posix `, :kconfig:option:`CONFIG_ETH_NATIVE_POSIX`, All Flash, :ref:`Flash simulator `, :kconfig:option:`CONFIG_FLASH_SIMULATOR`, All diff --git a/boards/native/native_sim/native_sim.dts b/boards/native/native_sim/native_sim.dts index 1f1b11ad9e7..162fcf07457 100644 --- a/boards/native/native_sim/native_sim.dts +++ b/boards/native/native_sim/native_sim.dts @@ -25,6 +25,7 @@ zephyr,canbus = &can_loopback0; zephyr,code-partition = &slot0_partition; zephyr,bt-hci = &bt_hci_userchan; + zephyr,touch = &input_sdl_touch; }; aliases { diff --git a/boards/native/native_sim/native_sim.yaml b/boards/native/native_sim/native_sim.yaml index 0a563c86881..8a476ba2771 100644 --- a/boards/native/native_sim/native_sim.yaml +++ b/boards/native/native_sim/native_sim.yaml @@ -1,7 +1,8 @@ identifier: native_sim name: Native Simulation port - 32-bit type: native -simulation: native +simulation: + - name: native arch: posix ram: 65536 flash: 65536 @@ -11,6 +12,7 @@ toolchain: supported: - can - counter + - display - dma - eeprom - netif:eth diff --git a/boards/native/native_sim/native_sim_native_64.yaml b/boards/native/native_sim/native_sim_native_64.yaml index 535cf513658..24a4bb082ea 100644 --- a/boards/native/native_sim/native_sim_native_64.yaml +++ b/boards/native/native_sim/native_sim_native_64.yaml @@ -1,7 +1,8 @@ identifier: native_sim/native/64 name: Native Simulation port - 64-bit variant type: native -simulation: native +simulation: + - name: native arch: posix ram: 65536 flash: 65536 @@ -11,6 +12,7 @@ toolchain: supported: - can - counter + - display - dma - eeprom - netif:eth diff --git a/boards/native/nrf_bsim/Kconfig.defconfig b/boards/native/nrf_bsim/Kconfig.defconfig index 629372e5e1d..393db8060de 100644 --- a/boards/native/nrf_bsim/Kconfig.defconfig +++ b/boards/native/nrf_bsim/Kconfig.defconfig @@ -38,10 +38,6 @@ config SYS_CLOCK_TICKS_PER_SEC default 10000 if NRF_GRTC_TIMER default 32768 -config BT_CTLR - default y if BOARD_NRF52_BSIM || BOARD_NRF5340BSIM_NRF5340_CPUNET || BOARD_NRF54L15BSIM_NRF54L15_CPUAPP - depends on BT - config HEAP_MEM_POOL_ADD_SIZE_BOARD int default 4096 if BT_HCI_IPC diff --git a/boards/native/nrf_bsim/doc/nrf52_bsim.rst b/boards/native/nrf_bsim/doc/nrf52_bsim.rst index 78c8e5c3279..01bd2c9f88e 100644 --- a/boards/native/nrf_bsim/doc/nrf52_bsim.rst +++ b/boards/native/nrf_bsim/doc/nrf52_bsim.rst @@ -120,10 +120,10 @@ most Zephyr samples and tests. When you want to run a simulation with radio activity you need to run also the BableSim 2G4 (2.4GHz) physical layer simulation (phy). -For example, if you would like to run a simple case with 1 BLE ``central_hr`` -sample application connecting to a BLE ``peripheral`` sample application: -Build the ``central_hr`` application targeting this board and copy the resulting -executable to the simulator bin folder with a sensible name: +For example, if you would like to run a simple case with a BLE :zephyr:code-sample:`ble_central_hr` +sample application connecting to a BLE :zephyr:code-sample:`ble_peripheral_hr` sample application: +Build the :zephyr:code-sample:`ble_central_hr` application targeting this board and copy the +resulting executable to the simulator bin folder with a sensible name: .. zephyr-app-commands:: :zephyr-app: samples/bluetooth/central_hr @@ -137,10 +137,10 @@ executable to the simulator bin folder with a sensible name: $ cp build/zephyr/zephyr.exe \ ${BSIM_OUT_PATH}/bin/bs_nrf52_bsim_samples_bluetooth_central_hr -Do the same for the ``peripheral`` sample app: +Do the same for the :zephyr:code-sample:`ble_peripheral_hr` sample app: .. zephyr-app-commands:: - :zephyr-app: samples/bluetooth/peripheral + :zephyr-app: samples/bluetooth/peripheral_hr :host-os: unix :board: nrf52_bsim :goals: build @@ -149,7 +149,7 @@ Do the same for the ``peripheral`` sample app: .. code-block:: console $ cp build/zephyr/zephyr.exe \ - ${BSIM_OUT_PATH}/bin/bs_nrf52_bsim_samples_bluetooth_peripheral + ${BSIM_OUT_PATH}/bin/bs_nrf52_bsim_samples_bluetooth_peripheral_hr And then run them together with BabbleSim's 2G4 physical layer simulation: diff --git a/boards/native/nrf_bsim/doc/nrf5340bsim.rst b/boards/native/nrf_bsim/doc/nrf5340bsim.rst index d726c9d8e7b..7e252511f33 100644 --- a/boards/native/nrf_bsim/doc/nrf5340bsim.rst +++ b/boards/native/nrf_bsim/doc/nrf5340bsim.rst @@ -99,7 +99,7 @@ you can provide that image to the Zephyr build of the second image using You can also use :ref:`System build (sysbuild) ` to build your dual MCU executable. The best way to understand how, may be to look into how this is done in one of the examples in the tree. For example, for :ref:`the nrf53_sync_rtc sample `, -:zephyr_file:`samples/boards/nrf/nrf53_sync_rtc/sysbuild.cmake`. +:zephyr_file:`samples/boards/nordic/nrf53_sync_rtc/sysbuild.cmake`. .. note:: diff --git a/boards/native/nrf_bsim/doc/nrf54l15bsim.rst b/boards/native/nrf_bsim/doc/nrf54l15bsim.rst index 5d7d67f7d1a..ae8b29d2aec 100644 --- a/boards/native/nrf_bsim/doc/nrf54l15bsim.rst +++ b/boards/native/nrf_bsim/doc/nrf54l15bsim.rst @@ -27,11 +27,13 @@ on the simulated nRF54L15 SOC. .. note:: - This simulated target does **not** yet support targeting the cpuflpr core. + Unlike real nRF54L15 devices, the nrf54l15bsim target has unlimited RAM, and code does not + occupy its RRAM. Therefore, as the nRF54L15, nRF54L10 and nRF54L05 SOCs only differ in the amount + of available RAM and RRAM either can be simulated using the nrf54l15bsim. -.. warning:: +.. note:: - This target is experimental. + This simulated target does **not** yet support targeting the cpuflpr core. This boards include models of some of the nRF54L15 SOC peripherals: @@ -57,9 +59,6 @@ and will use the same drivers as the nrf54l15dk targets for these. For more information on what is modeled to which level of detail, check the `HW models implementation status`_. -Note that unlike a real nrf54l15 device, the nrf54l15bsim boards have unlimited RAM, and code does -not occupy their RRAM. - .. _BabbleSim: https://BabbleSim.github.io @@ -91,5 +90,6 @@ ARM's TrustZone is not modeled in this board. This means that: can be labeled as restricted for secure or non secure access. * TF-M cannot be used. -Note that the CRACEN peripheral is not modeled. The mbedTLS library can still be used -but with a SW crypto backend. +Note that the CRACEN peripheral is not modeled. +As crypto library, Mbed TLS can be used with its SW crypto backend. +As entropy driver, the :dtcompatible:`zephyr,native-posix-rng` is enabled by default. diff --git a/boards/native/nrf_bsim/nrf52_bsim.yaml b/boards/native/nrf_bsim/nrf52_bsim.yaml index adff9a6add5..d0b087de4c5 100644 --- a/boards/native/nrf_bsim/nrf52_bsim.yaml +++ b/boards/native/nrf_bsim/nrf52_bsim.yaml @@ -2,7 +2,8 @@ identifier: nrf52_bsim name: NRF52 BabbleSim board type: native arch: posix -simulation: native +simulation: + - name: native env: - BSIM_OUT_PATH toolchain: diff --git a/boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpuapp.yaml b/boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpuapp.yaml index 9d31586454a..8509c052974 100644 --- a/boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpuapp.yaml +++ b/boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpuapp.yaml @@ -2,7 +2,8 @@ identifier: nrf5340bsim/nrf5340/cpuapp name: NRF53 BabbleSim - Application Core target type: native arch: posix -simulation: native +simulation: + - name: native env: - BSIM_OUT_PATH toolchain: diff --git a/boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpunet.yaml b/boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpunet.yaml index a0d6d2caa44..05f9edf82dc 100644 --- a/boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpunet.yaml +++ b/boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpunet.yaml @@ -2,7 +2,8 @@ identifier: nrf5340bsim/nrf5340/cpunet name: NRF53 Net Core BabbleSim board type: native arch: posix -simulation: native +simulation: + - name: native env: - BSIM_OUT_PATH toolchain: diff --git a/boards/native/nrf_bsim/nrf54l15bsim_nrf54l15_cpuapp.yaml b/boards/native/nrf_bsim/nrf54l15bsim_nrf54l15_cpuapp.yaml index e09184de96d..143f237289f 100644 --- a/boards/native/nrf_bsim/nrf54l15bsim_nrf54l15_cpuapp.yaml +++ b/boards/native/nrf_bsim/nrf54l15bsim_nrf54l15_cpuapp.yaml @@ -2,7 +2,8 @@ identifier: nrf54l15bsim/nrf54l15/cpuapp name: NRF54L15 BabbleSim - Application Core target type: native arch: posix -simulation: native +simulation: + - name: native env: - BSIM_OUT_PATH toolchain: diff --git a/boards/native/nrf_bsim/soc/soc_secure.h b/boards/native/nrf_bsim/soc/soc_secure.h index a39c02435a8..06e9cc64993 100644 --- a/boards/native/nrf_bsim/soc/soc_secure.h +++ b/boards/native/nrf_bsim/soc/soc_secure.h @@ -21,4 +21,10 @@ static inline void soc_secure_read_deviceid(uint32_t deviceid[2]) deviceid[1] = nrf_ficr_deviceid_get(NRF_FICR, 1); } +static inline int soc_secure_mem_read(void *dst, void *src, size_t len) +{ + (void)memcpy(dst, src, len); + return 0; +} + #endif /* BOARDS_POSIX_NRF52_BSIM_SOC_SECURE_H */ diff --git a/boards/nordic/nrf21540dk/Kconfig.defconfig b/boards/nordic/nrf21540dk/Kconfig.defconfig index 28a3f3e2c98..31642d14409 100644 --- a/boards/nordic/nrf21540dk/Kconfig.defconfig +++ b/boards/nordic/nrf21540dk/Kconfig.defconfig @@ -5,7 +5,4 @@ if BOARD_NRF21540DK -config BT_CTLR - default BT - endif # BOARD_NRF21540DK diff --git a/boards/nordic/nrf51dk/Kconfig.defconfig b/boards/nordic/nrf51dk/Kconfig.defconfig index ae8e85130f3..1f0b7bf0c49 100644 --- a/boards/nordic/nrf51dk/Kconfig.defconfig +++ b/boards/nordic/nrf51dk/Kconfig.defconfig @@ -5,7 +5,4 @@ if BOARD_NRF51DK_NRF51822 -config BT_CTLR - default BT - endif # BOARD_NRF51DK_NRF51822 diff --git a/boards/nordic/nrf51dk/doc/index.rst b/boards/nordic/nrf51dk/doc/index.rst index f5a2acbbcde..8cae453e2ed 100644 --- a/boards/nordic/nrf51dk/doc/index.rst +++ b/boards/nordic/nrf51dk/doc/index.rst @@ -1,4 +1,4 @@ -.. _nrf51dk_nrf51422: +.. _nrf51dk_nrf51822: nRF51 DK ######## diff --git a/boards/nordic/nrf51dongle/Kconfig.defconfig b/boards/nordic/nrf51dongle/Kconfig.defconfig index fed53a7a316..e6c8d45f810 100644 --- a/boards/nordic/nrf51dongle/Kconfig.defconfig +++ b/boards/nordic/nrf51dongle/Kconfig.defconfig @@ -5,7 +5,4 @@ if BOARD_NRF51DONGLE -config BT_CTLR - default BT - endif # BOARD_NRF51DONGLE diff --git a/boards/nordic/nrf52833dk/Kconfig.defconfig b/boards/nordic/nrf52833dk/Kconfig.defconfig index 30c49fa7fb7..dc6fbbdcf3d 100644 --- a/boards/nordic/nrf52833dk/Kconfig.defconfig +++ b/boards/nordic/nrf52833dk/Kconfig.defconfig @@ -5,7 +5,4 @@ if BOARD_NRF52833DK -config BT_CTLR - default BT - endif # BOARD_NRF52833DK diff --git a/boards/nordic/nrf52840dk/Kconfig.defconfig b/boards/nordic/nrf52840dk/Kconfig.defconfig index 7e932d27f7a..478445b229b 100644 --- a/boards/nordic/nrf52840dk/Kconfig.defconfig +++ b/boards/nordic/nrf52840dk/Kconfig.defconfig @@ -5,7 +5,4 @@ if BOARD_NRF52840DK -config BT_CTLR - default BT - endif # BOARD_NRF52840DK diff --git a/boards/nordic/nrf52840dongle/Kconfig b/boards/nordic/nrf52840dongle/Kconfig index b1cb32d2251..c8698ad0701 100644 --- a/boards/nordic/nrf52840dongle/Kconfig +++ b/boards/nordic/nrf52840dongle/Kconfig @@ -12,8 +12,4 @@ config BOARD_HAS_NRF5_BOOTLOADER If selected, applications are linked so that they can be loaded by Nordic nRF5 bootloader. -config BOARD_SERIAL_BACKEND_CDC_ACM - bool "USB CDC" - default y - endif # BOARD_NRF52840DONGLE diff --git a/boards/nordic/nrf52840dongle/Kconfig.defconfig b/boards/nordic/nrf52840dongle/Kconfig.defconfig index 1288e33bcdb..5bdbb6ce63b 100644 --- a/boards/nordic/nrf52840dongle/Kconfig.defconfig +++ b/boards/nordic/nrf52840dongle/Kconfig.defconfig @@ -22,62 +22,6 @@ config FLASH_LOAD_OFFSET default 0x1000 depends on BOARD_HAS_NRF5_BOOTLOADER && (MCUBOOT || !USE_DT_CODE_PARTITION) -if BOARD_SERIAL_BACKEND_CDC_ACM - -config USB_DEVICE_STACK - default y - -config USB_CDC_ACM - default SERIAL - -config CONSOLE - default y - -config UART_CONSOLE - default CONSOLE - -config USB_DEVICE_INITIALIZE_AT_BOOT - default y if !MCUBOOT && CONSOLE - -config SHELL_BACKEND_SERIAL_CHECK_DTR - default SHELL - depends on UART_LINE_CTRL - -config UART_LINE_CTRL - default SHELL - -config USB_DEVICE_REMOTE_WAKEUP - default n - -if LOG - -# Logger cannot use itself to log -choice USB_CDC_ACM_LOG_LEVEL_CHOICE - default USB_CDC_ACM_LOG_LEVEL_OFF -endchoice - -# Set USB log level to error only -choice USB_DEVICE_LOG_LEVEL_CHOICE - default USB_DEVICE_LOG_LEVEL_ERR -endchoice - -# Wait 4000ms at startup for logging -config LOG_PROCESS_THREAD_STARTUP_DELAY_MS - default 4000 - -endif # LOG - -if USB_DEVICE_STACK - -# Enable UART driver, needed for CDC ACM -config SERIAL - default y - -endif # USB_DEVICE_STACK - -endif # BOARD_SERIAL_BACKEND_CDC_ACM - -config BT_CTLR - default BT +source "boards/common/usb/Kconfig.cdc_acm_serial.defconfig" endif # BOARD_NRF52840DONGLE diff --git a/boards/nordic/nrf52840dongle/nrf52840dongle_nrf52840.dts b/boards/nordic/nrf52840dongle/nrf52840dongle_nrf52840.dts index 655ef346a65..1f1de703ade 100644 --- a/boards/nordic/nrf52840dongle/nrf52840dongle_nrf52840.dts +++ b/boards/nordic/nrf52840dongle/nrf52840dongle_nrf52840.dts @@ -15,11 +15,6 @@ compatible = "nordic,nrf52840-dongle-nrf52840"; chosen { - zephyr,console = &cdc_acm_uart; - zephyr,shell-uart = &cdc_acm_uart; - zephyr,uart-mcumgr = &cdc_acm_uart; - zephyr,bt-mon-uart = &cdc_acm_uart; - zephyr,bt-c2h-uart = &cdc_acm_uart; zephyr,sram = &sram0; zephyr,flash = &flash0; zephyr,code-partition = &slot0_partition; @@ -188,8 +183,6 @@ zephyr_udc0: &usbd { compatible = "nordic,nrf-usbd"; status = "okay"; - - cdc_acm_uart: cdc_acm_uart { - compatible = "zephyr,cdc-acm-uart"; - }; }; + +#include <../boards/common/usb/cdc_acm_serial.dtsi> diff --git a/boards/nordic/nrf52dk/Kconfig b/boards/nordic/nrf52dk/Kconfig index 7b41e21fc49..45c182b7b91 100644 --- a/boards/nordic/nrf52dk/Kconfig +++ b/boards/nordic/nrf52dk/Kconfig @@ -5,9 +5,4 @@ if BOARD_NRF52DK -# BT_CTLR depends on BT. When BT is enabled we should default to also -# enabling the controller. -config BT_CTLR - default y if BT - endif # BOARD_NRF52DK diff --git a/boards/nordic/nrf5340_audio_dk/Kconfig.defconfig b/boards/nordic/nrf5340_audio_dk/Kconfig.defconfig index f8315be4e25..7084af10d6b 100644 --- a/boards/nordic/nrf5340_audio_dk/Kconfig.defconfig +++ b/boards/nordic/nrf5340_audio_dk/Kconfig.defconfig @@ -64,7 +64,4 @@ endif # BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP || BOARD_NRF5340_AUDIO_DK_NRF5340_ if BOARD_NRF5340_AUDIO_DK_NRF5340_CPUNET -config BT_CTLR - default y if BT - endif # BOARD_NRF5340_AUDIO_DK_NRF5340_CPUNET diff --git a/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp_common.dtsi b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp_common.dtsi index 70517a604ea..f29db4cfeb2 100644 --- a/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp_common.dtsi +++ b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp_common.dtsi @@ -84,6 +84,11 @@ status = "okay"; }; +&lfxo { + load-capacitors = "internal"; + load-capacitance-picofarad = <7>; +}; + &adc { status = "okay"; #address-cells = <1>; @@ -209,6 +214,7 @@ arduino_spi: &spi4 { status = "okay"; sdmmc { compatible = "zephyr,sdmmc-disk"; + disk-name = "SD"; status = "okay"; }; diff --git a/boards/nordic/nrf5340dk/Kconfig.defconfig b/boards/nordic/nrf5340dk/Kconfig.defconfig index 1c10b3e7dca..b6186d4e074 100644 --- a/boards/nordic/nrf5340dk/Kconfig.defconfig +++ b/boards/nordic/nrf5340dk/Kconfig.defconfig @@ -64,7 +64,4 @@ endif # BOARD_NRF5340DK_NRF5340_CPUAPP || BOARD_NRF5340DK_NRF5340_CPUAPP_NS if BOARD_NRF5340DK_NRF5340_CPUNET -config BT_CTLR - default y if BT - endif # BOARD_NRF5340DK_NRF5340_CPUNET diff --git a/boards/nordic/nrf5340dk/nrf5340_cpuapp_common.dtsi b/boards/nordic/nrf5340dk/nrf5340_cpuapp_common.dtsi index 21701d9922d..71060ba1ba2 100644 --- a/boards/nordic/nrf5340dk/nrf5340_cpuapp_common.dtsi +++ b/boards/nordic/nrf5340dk/nrf5340_cpuapp_common.dtsi @@ -65,6 +65,11 @@ status = "okay"; }; +&lfxo { + load-capacitors = "internal"; + load-capacitance-picofarad = <7>; +}; + &adc { status = "okay"; }; diff --git a/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpuapp.yaml b/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpuapp.yaml index 50ed4733871..3daf13dbd4f 100644 --- a/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpuapp.yaml +++ b/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpuapp.yaml @@ -9,6 +9,10 @@ toolchain: ram: 448 flash: 1024 supported: + - arduino_gpio + - arduino_i2c + - arduino_serial + - arduino_spi - gpio - i2c - i2s diff --git a/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpunet.yaml b/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpunet.yaml index a55a7879fc0..a44099c4587 100644 --- a/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpunet.yaml +++ b/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpunet.yaml @@ -9,6 +9,7 @@ toolchain: ram: 64 flash: 256 supported: + - arduino_gpio - watchdog - gpio vendor: nordic diff --git a/boards/nordic/nrf54h20dk/Kconfig.defconfig b/boards/nordic/nrf54h20dk/Kconfig.defconfig index a2be74d3648..268722f5fe5 100644 --- a/boards/nordic/nrf54h20dk/Kconfig.defconfig +++ b/boards/nordic/nrf54h20dk/Kconfig.defconfig @@ -6,19 +6,14 @@ if BOARD_NRF54H20DK_NRF54H20_CPUAPP config BT_HCI_IPC default y if BT +config MAX_THREAD_BYTES + default 3 if USERSPACE + endif # BOARD_NRF54H20DK_NRF54H20_CPUAPP if BOARD_NRF54H20DK_NRF54H20_CPURAD -config BT_CTLR - default y if BT +config MAX_THREAD_BYTES + default 3 if USERSPACE endif # BOARD_NRF54H20DK_NRF54H20_CPURAD - -if BOARD_NRF54H20DK_NRF54H20_CPUPPR - -# As PPR has limited memory most of tests does not fit with asserts enabled. -config ASSERT - default n if ZTEST - -endif # BOARD_NRF54H20DK_NRF54H20_CPUPPR diff --git a/boards/nordic/nrf54h20dk/bicr.json b/boards/nordic/nrf54h20dk/bicr.json new file mode 100644 index 00000000000..9937860052b --- /dev/null +++ b/boards/nordic/nrf54h20dk/bicr.json @@ -0,0 +1,32 @@ +{ + "power": { + "scheme": "VDDH_2V1_5V5" + }, + "ioPortPower": { + "p1Supply": "EXTERNAL_1V8", + "p2Supply": "EXTERNAL_1V8", + "p6Supply": "EXTERNAL_1V8", + "p7Supply": "EXTERNAL_1V8", + "p9Supply": "EXTERNAL_FULL" + }, + "ioPortImpedance": { + "p6ImpedanceOhms": 50, + "p7ImpedanceOhms": 50 + }, + "lfosc": { + "source": "LFXO", + "lfxo": { + "mode": "CRYSTAL", + "accuracyPPM": 20, + "startupTimeMs": 600, + "builtInLoadCapacitancePf": 15, + "builtInLoadCapacitors": true + } + }, + "hfxo": { + "mode": "CRYSTAL", + "startupTimeUs": 850, + "builtInLoadCapacitors": true, + "builtInLoadCapacitancePf": 14 + } +} diff --git a/boards/nordic/nrf54h20dk/board.cmake b/boards/nordic/nrf54h20dk/board.cmake index 0c8376c1714..80963356dc9 100644 --- a/boards/nordic/nrf54h20dk/board.cmake +++ b/boards/nordic/nrf54h20dk/board.cmake @@ -12,3 +12,14 @@ if(CONFIG_BOARD_NRF54H20DK_NRF54H20_CPUAPP OR CONFIG_BOARD_NRF54H20DK_NRF54H20_C board_runner_args(jlink "--device=CORTEX-M33" "--speed=4000" "--tool-opt=-jlinkscriptfile ${JLINKSCRIPTFILE}") include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) endif() + +if(CONFIG_BOARD_NRF54H20DK_NRF54H20_CPUPPR OR CONFIG_BOARD_NRF54H20DK_NRF54H20_CPUFLPR) + if(CONFIG_BOARD_NRF54H20DK_NRF54H20_CPUPPR) + set(JLINKSCRIPTFILE ${CMAKE_CURRENT_LIST_DIR}/support/nrf54h20_cpuppr.JLinkScript) + else() + set(JLINKSCRIPTFILE ${CMAKE_CURRENT_LIST_DIR}/support/nrf54h20_cpuflpr.JLinkScript) + endif() + + board_runner_args(jlink "--device=RISC-V" "--speed=4000" "-if SW" "--tool-opt=-jlinkscriptfile ${JLINKSCRIPTFILE}") + include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +endif() diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_bicr.dtsi b/boards/nordic/nrf54h20dk/nrf54h20dk_bicr.dtsi deleted file mode 100644 index 34652755564..00000000000 --- a/boards/nordic/nrf54h20dk/nrf54h20dk_bicr.dtsi +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright (c) 2024 Nordic Semiconductor ASA - * - * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause - */ - -/ { - bicr: bicr@fff87b0 { - compatible = "nordic,nrf-bicr"; - reg = <0xfff87b0 0x48>; - - power-vddao5v0 = "external"; - power-vddao1v8 = "internal"; - power-vdd1v0 = "internal"; - power-vddrf1v0 = "shorted"; - power-vddao0v8 = "internal"; - power-vddvs0v8 = "internal"; - - inductor-present; - - ioport-power-rails = <&gpio1 2>, <&gpio2 2>, <&gpio6 2>, <&gpio7 2>, <&gpio9 4>; - ioport-drivectrls = <&gpio6 50>, <&gpio7 50>; - - lfosc-mode = "crystal"; - lfosc-loadcap = <15>; - - lfrc-autocalibration = <20 40 3>; - - hfxo-mode = "crystal"; - hfxo-loadcap = <56>; - }; -}; - -&gpio1 { - #ioport-power-rail-cells = <1>; -}; - -&gpio2 { - #ioport-power-rail-cells = <1>; -}; - -&gpio6 { - #ioport-power-rail-cells = <1>; - #ioport-drivectrl-cells = <1>; -}; - -&gpio7 { - #ioport-power-rail-cells = <1>; - #ioport-drivectrl-cells = <1>; -}; - -&gpio9 { - #ioport-power-rail-cells = <1>; -}; diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-common.dtsi b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-common.dtsi index 595307aec8c..0c5307c4c8c 100644 --- a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-common.dtsi +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-common.dtsi @@ -11,13 +11,8 @@ &hfxo { status = "okay"; accuracy-ppm = <30>; - startup-time-us = <850>; - mode = "crystal"; }; &lfxo { status = "okay"; - accuracy-ppm = <20>; - startup-time-us = <600000>; - mode = "crystal"; }; diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-memory_map.dtsi b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-memory_map.dtsi index f2937402554..165fa12ba80 100644 --- a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-memory_map.dtsi +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-memory_map.dtsi @@ -7,44 +7,44 @@ / { reserved-memory { - cpuapp_ram0x_region: memory@2f010000 { + cpurad_ram0x_region: memory@2f010000 { compatible = "nordic,owned-memory"; - reg = <0x2f010000 DT_SIZE_K(260)>; + reg = <0x2f010000 DT_SIZE_K(4)>; status = "disabled"; - nordic,access = ; + nordic,access = ; #address-cells = <1>; #size-cells = <1>; - ranges = <0x0 0x2f010000 0x41000>; + ranges = <0x0 0x2f010000 0x1000>; - cpusec_cpuapp_ipc_shm: memory@0 { + cpusec_cpurad_ipc_shm: memory@0 { reg = <0x0 DT_SIZE_K(2)>; }; - cpuapp_cpusec_ipc_shm: memory@800 { + cpurad_cpusec_ipc_shm: memory@800 { reg = <0x800 DT_SIZE_K(2)>; }; - - cpuapp_data: memory@1000 { - reg = <0x1000 DT_SIZE_K(256)>; - }; }; - cpurad_ram0x_region: memory@2f051000 { + cpuapp_ram0x_region: memory@2f011000 { compatible = "nordic,owned-memory"; - reg = <0x2f051000 DT_SIZE_K(4)>; + reg = <0x2f011000 DT_SIZE_K(260)>; status = "disabled"; - nordic,access = ; + nordic,access = ; #address-cells = <1>; #size-cells = <1>; - ranges = <0x0 0x2f051000 0x1000>; + ranges = <0x0 0x2f011000 0x41000>; - cpusec_cpurad_ipc_shm: memory@0 { + cpusec_cpuapp_ipc_shm: memory@0 { reg = <0x0 DT_SIZE_K(2)>; }; - cpurad_cpusec_ipc_shm: memory@800 { + cpuapp_cpusec_ipc_shm: memory@800 { reg = <0x800 DT_SIZE_K(2)>; }; + + cpuapp_data: memory@1000 { + reg = <0x1000 DT_SIZE_K(256)>; + }; }; etr_buf_ram0x_region: memory@2f0be000 { diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts index 171732d81e6..06e642948f3 100644 --- a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts @@ -8,7 +8,6 @@ #include #include "nrf54h20dk_nrf54h20-common.dtsi" -#include "nrf54h20dk_bicr.dtsi" /delete-node/ &cpurad_cpusys_ipc; /delete-node/ &cpusec_cpurad_ipc; @@ -150,11 +149,16 @@ }; &cpusec_cpuapp_ipc { + status = "okay"; mbox-names = "tx", "rx"; tx-region = <&cpuapp_cpusec_ipc_shm>; rx-region = <&cpusec_cpuapp_ipc_shm>; }; +&cpusec_bellboard { + status = "okay"; +}; + ipc0: &cpuapp_cpurad_ipc { status = "okay"; mbox-names = "rx", "tx"; @@ -192,10 +196,6 @@ ipc0: &cpuapp_cpurad_ipc { status = "okay"; }; -&dma_fast_region { - status = "okay"; -}; - &cpuapp_rx_partitions { status = "okay"; }; @@ -284,6 +284,8 @@ ipc0: &cpuapp_cpurad_ipc { t-enter-dpd = <10000>; t-exit-dpd = <30000>; reset-gpios = <&gpio6 12 GPIO_ACTIVE_LOW>; + t-reset-pulse = <10000>; + t-reset-recovery = <35000>; mspi-max-frequency = ; mspi-io-mode = "MSPI_IO_MODE_OCTAL"; diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad.dts b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad.dts index 049617e6dc6..8734ff9f745 100644 --- a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad.dts +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad.dts @@ -43,6 +43,10 @@ status = "okay"; }; +&cpurad_ram0x_region { + status = "okay"; +}; + &cpurad_bellboard { status = "okay"; interrupts = <96 NRF_DEFAULT_IRQ_PRIORITY>; @@ -60,11 +64,16 @@ }; &cpusec_cpurad_ipc { + status = "okay"; mbox-names = "tx", "rx"; tx-region = <&cpurad_cpusec_ipc_shm>; rx-region = <&cpusec_cpurad_ipc_shm>; }; +&cpusec_bellboard { + status = "okay"; +}; + ipc0: &cpuapp_cpurad_ipc { status = "okay"; mbox-names = "tx", "rx"; diff --git a/boards/nordic/nrf54h20dk/support/nrf54h20_cpuflpr.JLinkScript b/boards/nordic/nrf54h20dk/support/nrf54h20_cpuflpr.JLinkScript new file mode 100644 index 00000000000..10b83259fdd --- /dev/null +++ b/boards/nordic/nrf54h20dk/support/nrf54h20_cpuflpr.JLinkScript @@ -0,0 +1,9 @@ +int InitTarget(void) { + // Base address where DMI registers can be found in the APB address space + JLINK_ExecCommand("CORESIGHT_SetCoreBaseAddr = 0x5F8D4400"); + + // Use AP[x] to communicate with the RISC-V, flpr = APP + JLINK_ExecCommand("CORESIGHT_SetIndexAHBAPToUse = 0"); + + return 0; +} diff --git a/boards/nordic/nrf54h20dk/support/nrf54h20_cpuppr.JLinkScript b/boards/nordic/nrf54h20dk/support/nrf54h20_cpuppr.JLinkScript new file mode 100644 index 00000000000..127981a45c3 --- /dev/null +++ b/boards/nordic/nrf54h20dk/support/nrf54h20_cpuppr.JLinkScript @@ -0,0 +1,9 @@ +int InitTarget(void) { + // Base address where DMI registers can be found in the APB address space + JLINK_ExecCommand("CORESIGHT_SetCoreBaseAddr = 0x5F908400"); + + // Use AP[x] to communicate with the RISC-V, ppr = APP + JLINK_ExecCommand("CORESIGHT_SetIndexAHBAPToUse = 0"); + + return 0; +} diff --git a/boards/nordic/nrf54l09pdk/Kconfig.defconfig b/boards/nordic/nrf54l09pdk/Kconfig.defconfig new file mode 100644 index 00000000000..e495d3e67ce --- /dev/null +++ b/boards/nordic/nrf54l09pdk/Kconfig.defconfig @@ -0,0 +1,18 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NRF54L09PDK_NRF54L09_CPUAPP + +config BT_CTLR + default BT + +config ROM_START_OFFSET + default 0x800 if BOOTLOADER_MCUBOOT + +config SOC_NRF54LX_SKIP_CLOCK_CONFIG + default y + +config SOC_NRF54LX_SKIP_GLITCHDETECTOR_DISABLE + default y + +endif # BOARD_NRF54L09PDK_NRF54L09_CPUAPP diff --git a/boards/nordic/nrf54l09pdk/Kconfig.nrf54l09pdk b/boards/nordic/nrf54l09pdk/Kconfig.nrf54l09pdk new file mode 100644 index 00000000000..bc6aa676281 --- /dev/null +++ b/boards/nordic/nrf54l09pdk/Kconfig.nrf54l09pdk @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NRF54L09PDK + select SOC_NRF54L09_ENGA_CPUAPP if BOARD_NRF54L09PDK_NRF54L09_CPUAPP diff --git a/boards/nordic/nrf54l09pdk/board.cmake b/boards/nordic/nrf54l09pdk/board.cmake new file mode 100644 index 00000000000..5d36ac00a3e --- /dev/null +++ b/boards/nordic/nrf54l09pdk/board.cmake @@ -0,0 +1,7 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=cortex-m33" "--speed=4000") + +include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/nordic/nrf54l09pdk/board.yml b/boards/nordic/nrf54l09pdk/board.yml new file mode 100644 index 00000000000..b35f4c1fafe --- /dev/null +++ b/boards/nordic/nrf54l09pdk/board.yml @@ -0,0 +1,6 @@ +board: + name: nrf54l09pdk + full_name: nRF54L09 PDK + vendor: nordic + socs: + - name: nrf54l09 diff --git a/boards/nordic/nrf54l09pdk/doc/index.rst b/boards/nordic/nrf54l09pdk/doc/index.rst new file mode 100644 index 00000000000..0ef130b5473 --- /dev/null +++ b/boards/nordic/nrf54l09pdk/doc/index.rst @@ -0,0 +1,90 @@ +.. _nrf54l09pdk_nrf54l09: + +nRF54L09 PDK +############ + +Overview +******** + +.. note:: + + All software for the nRF54L09 SoC is experimental and hardware availability + is restricted to the participants in the limited sampling program. + +The nRF54L09 Preview Development Kit hardware provides +support for the Nordic Semiconductor nRF54L09 Arm Cortex-M33 CPU and +the following devices: + +* CLOCK +* RRAM +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`GRTC (Global real-time counter)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`UARTE (Universal asynchronous receiver-transmitter)` + +Hardware +******** + +nRF54L09 PDK has two crystal oscillators: + +* High-frequency 32 MHz crystal oscillator (HFXO) +* Low-frequency 32.768 kHz crystal oscillator (LFXO) + +The crystal oscillators can be configured to use either +internal or external capacitors. + +Supported Features +================== + +The ``nrf54l09pdk/nrf54l09/cpuapp`` board target supports the following hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| RRAM | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| GRTC | on-chip | system clock | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| UARTE | on-chip | serial | ++-----------+------------+----------------------+ + +Other hardware features have not been enabled yet for this board. + +Programming and Debugging +************************* + +Applications for the ``nrf54l09pdk/nrf54l09/cpuapp`` board target can be +built, flashed, and debugged in the usual way. See +:ref:`build_an_application` and :ref:`application_run` for more details on +building and running. + +Flashing +======== + +As an example, this section shows how to build and flash the :zephyr:code-sample:`hello_world` +application. + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. + +To build and program the sample to the nRF54L09 PDK, complete the following steps: + +First, connect the nRF54L09 PDK to you computer using the IMCU USB port on the PDK. +Next, build the sample by running the following command: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nrf54l09pdk/nrf54l09/cpuapp + :goals: build flash + +Testing the LEDs and buttons in the nRF54L09 PDK +************************************************ + +Test the nRF54L09 PDK with a :zephyr:code-sample:`blinky` sample. diff --git a/boards/nordic/nrf54l09pdk/nrf54l09_cpuapp_common.dtsi b/boards/nordic/nrf54l09pdk/nrf54l09_cpuapp_common.dtsi new file mode 100644 index 00000000000..c258cb2f4b7 --- /dev/null +++ b/boards/nordic/nrf54l09pdk/nrf54l09_cpuapp_common.dtsi @@ -0,0 +1,117 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* This file is common to the secure and non-secure domain */ + +#include +#include "nrf54l09pdk_nrf54l09-common.dtsi" + +/ { + chosen { + zephyr,console = &uart20; + zephyr,shell-uart = &uart20; + zephyr,uart-mcumgr = &uart20; + zephyr,bt-mon-uart = &uart20; + zephyr,bt-c2h-uart = &uart20; + zephyr,flash-controller = &rram_controller; + zephyr,flash = &cpuapp_rram; + zephyr,bt-hci = &bt_hci_controller; + zephyr,ieee802154 = &ieee802154; + }; +}; + +&cpuapp_sram { + status = "okay"; +}; + +&lfxo { + load-capacitors = "internal"; + load-capacitance-femtofarad = <15500>; +}; + +&hfxo { + load-capacitors = "internal"; + load-capacitance-femtofarad = <15000>; +}; + +&grtc { + owned-channels = <0 1 2 3 4 5 6 7 8 9 10 11>; + /* Channels 7-11 reserved for Zero Latency IRQs, 3-4 for FLPR */ + child-owned-channels = <3 4 7 8 9 10 11>; + status = "okay"; +}; + +&cpuapp_rram { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x0 DT_SIZE_K(64)>; + }; + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x10000 DT_SIZE_K(212)>; + }; + slot0_ns_partition: partition@45000 { + label = "image-0-nonsecure"; + reg = <0x45000 DT_SIZE_K(212)>; + }; + slot1_partition: partition@7a000 { + label = "image-1"; + reg = <0x7a000 DT_SIZE_K(212)>; + }; + slot1_ns_partition: partition@af000 { + label = "image-1-nonsecure"; + reg = <0xaf000 DT_SIZE_K(212)>; + }; + storage_partition: partition@e4000 { + label = "storage"; + reg = <0xe4000 DT_SIZE_K(36)>; + }; + }; +}; + +&uart20 { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpiote20 { + status = "okay"; +}; + +&gpiote30 { + status = "okay"; +}; + +&radio { + status = "okay"; +}; + +&temp { + status = "okay"; +}; + +&clock { + status = "okay"; +}; + +&bt_hci_controller { + status = "okay"; +}; + +&ieee802154 { + status = "okay"; +}; diff --git a/boards/nordic/nrf54l09pdk/nrf54l09pdk_nrf54l09-common.dtsi b/boards/nordic/nrf54l09pdk/nrf54l09pdk_nrf54l09-common.dtsi new file mode 100644 index 00000000000..2bdb42b9653 --- /dev/null +++ b/boards/nordic/nrf54l09pdk/nrf54l09pdk_nrf54l09-common.dtsi @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "nrf54l09pdk_nrf54l09-pinctrl.dtsi" + +/ { + leds { + compatible = "gpio-leds"; + led0: led_0 { + gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + label = "Green LED 1"; + }; + led1: led_1 { + gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>; + label = "Green LED 2"; + }; + }; + + buttons { + compatible = "gpio-keys"; + button0: button_0 { + gpios = <&gpio1 13 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button 0"; + zephyr,code = ; + }; + button1: button_1 { + gpios = <&gpio1 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button 1"; + zephyr,code = ; + }; + button2: button_2 { + gpios = <&gpio1 8 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button 2"; + zephyr,code = ; + }; + button3: button_3 { + gpios = <&gpio0 4 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button 3"; + zephyr,code = ; + }; + }; + + aliases { + led0 = &led0; + led1 = &led1; + sw0 = &button0; + sw1 = &button1; + sw2 = &button2; + sw3 = &button3; + watchdog0 = &wdt31; + }; +}; + +&uart20 { + current-speed = <115200>; + pinctrl-0 = <&uart20_default>; + pinctrl-1 = <&uart20_sleep>; + pinctrl-names = "default", "sleep"; +}; diff --git a/boards/nordic/nrf54l09pdk/nrf54l09pdk_nrf54l09-pinctrl.dtsi b/boards/nordic/nrf54l09pdk/nrf54l09pdk_nrf54l09-pinctrl.dtsi new file mode 100644 index 00000000000..83aa91d8a34 --- /dev/null +++ b/boards/nordic/nrf54l09pdk/nrf54l09pdk_nrf54l09-pinctrl.dtsi @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + /omit-if-no-ref/ uart20_default: uart20_default { + group1 { + psels = ; + }; + group2 { + psels = ; + bias-pull-up; + }; + }; + + /omit-if-no-ref/ uart20_sleep: uart20_sleep { + group1 { + psels = , + ; + low-power-enable; + }; + }; +}; diff --git a/boards/nordic/nrf54l09pdk/nrf54l09pdk_nrf54l09_cpuapp.dts b/boards/nordic/nrf54l09pdk/nrf54l09pdk_nrf54l09_cpuapp.dts new file mode 100644 index 00000000000..7281f237b66 --- /dev/null +++ b/boards/nordic/nrf54l09pdk/nrf54l09pdk_nrf54l09_cpuapp.dts @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include "nrf54l09_cpuapp_common.dtsi" + +/ { + compatible = "nordic,nrf54l09pdk_nrf54l09-cpuapp"; + model = "Nordic nRF54L09 PDK nRF54L09 Application MCU"; + + chosen { + zephyr,code-partition = &slot0_partition; + zephyr,sram = &cpuapp_sram; + }; +}; diff --git a/boards/nordic/nrf54l09pdk/nrf54l09pdk_nrf54l09_cpuapp.yaml b/boards/nordic/nrf54l09pdk/nrf54l09pdk_nrf54l09_cpuapp.yaml new file mode 100644 index 00000000000..e5d61a7c483 --- /dev/null +++ b/boards/nordic/nrf54l09pdk/nrf54l09pdk_nrf54l09_cpuapp.yaml @@ -0,0 +1,17 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +identifier: nrf54l09pdk/nrf54l09/cpuapp +name: nRF54L09-PDK-nRF54L09-Application +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +sysbuild: true +ram: 192 +flash: 200 +supported: + - counter + - gpio diff --git a/boards/nordic/nrf54l09pdk/nrf54l09pdk_nrf54l09_cpuapp_defconfig b/boards/nordic/nrf54l09pdk/nrf54l09pdk_nrf54l09_cpuapp_defconfig new file mode 100644 index 00000000000..02796a1361e --- /dev/null +++ b/boards/nordic/nrf54l09pdk/nrf54l09pdk_nrf54l09_cpuapp_defconfig @@ -0,0 +1,29 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# MPU-based null-pointer dereferencing detection cannot +# be applied as the (0x0 - 0x400) is unmapped for this target. +CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y + +# Enable Cache +CONFIG_CACHE_MANAGEMENT=y +CONFIG_EXTERNAL_CACHE=y + +# Start SYSCOUNTER on driver init +CONFIG_NRF_GRTC_START_SYSCOUNTER=y diff --git a/boards/nordic/nrf54l15dk/Kconfig.defconfig b/boards/nordic/nrf54l15dk/Kconfig.defconfig index bffc4ac3c86..ca46527e512 100644 --- a/boards/nordic/nrf54l15dk/Kconfig.defconfig +++ b/boards/nordic/nrf54l15dk/Kconfig.defconfig @@ -4,9 +4,6 @@ if BOARD_NRF54L15DK_NRF54L05_CPUAPP || BOARD_NRF54L15DK_NRF54L10_CPUAPP || \ BOARD_NRF54L15DK_NRF54L15_CPUAPP -config BT_CTLR - default BT - config ROM_START_OFFSET default 0 if PARTITION_MANAGER_ENABLED default 0x800 if BOOTLOADER_MCUBOOT diff --git a/boards/nordic/nrf54l15dk/board.cmake b/boards/nordic/nrf54l15dk/board.cmake index 664cb158a6a..81af434c648 100644 --- a/boards/nordic/nrf54l15dk/board.cmake +++ b/boards/nordic/nrf54l15dk/board.cmake @@ -6,7 +6,8 @@ if(CONFIG_SOC_NRF54L05_CPUAPP OR CONFIG_SOC_NRF54L10_CPUAPP OR board_runner_args(jlink "--device=cortex-m33" "--speed=4000") elseif(CONFIG_SOC_NRF54L05_CPUFLPR OR CONFIG_SOC_NRF54L10_CPUFLPR OR CONFIG_SOC_NRF54L15_CPUFLPR) - board_runner_args(jlink "--speed=4000") + set(JLINKSCRIPTFILE ${CMAKE_CURRENT_LIST_DIR}/support/nrf54l_05_10_15_cpuflpr.JLinkScript) + board_runner_args(jlink "--device=RISC-V" "--speed=4000" "-if SW" "--tool-opt=-jlinkscriptfile ${JLINKSCRIPTFILE}") endif() if(BOARD_NRF54L15DK_NRF54L15_CPUAPP_NS) diff --git a/boards/nordic/nrf54l15dk/doc/index.rst b/boards/nordic/nrf54l15dk/doc/index.rst index 4886cadde76..e4ad1e8ad09 100644 --- a/boards/nordic/nrf54l15dk/doc/index.rst +++ b/boards/nordic/nrf54l15dk/doc/index.rst @@ -7,9 +7,9 @@ Overview ******** .. note:: - - All software for the nRF54L15 SoC is experimental and hardware availability - is restricted to the participants in the limited sampling program. + You can find more information about the nRF54L15 SoC on the `nRF54L15 website`_. + For the nRF54L15 technical documentation and other resources (such as + SoC Datasheet), see the `nRF54L15 documentation`_ page. The nRF54L15 Development Kit hardware provides support for the Nordic Semiconductor nRF54L15 Arm Cortex-M33 CPU and the following devices: @@ -146,3 +146,45 @@ Testing the LEDs and buttons in the nRF54L15 DK ************************************************ Test the nRF54L15 DK with a :zephyr:code-sample:`blinky` sample. + + +.. _nRF54L15 website: https://www.nordicsemi.com/Products/nRF54L15 +.. _nRF54L15 documentation: https://docs.nordicsemi.com/bundle/ncs-latest/page/nrf/app_dev/device_guides/nrf54l/index.html + +.. _nrf54l15dk_nrf54l05: + +nRF54L05 emulation on nRF54L15 DK +################################# + +Overview +******** + +The ``nrf54l15dk/nrf54l05`` board is a modified version of the :ref:`nrf54l15dk_nrf54l15` +that enforces the limitations imposed by the nRF54L05 IC, which is a +cost-reduced variant of the original nRF54L15. Since Nordic does not offer a +development kit for the nRF54L05, you can use this board to develop for this +IC while using the nRF54L15 Development Kit (PCA10156). + +See :ref:`nrf54l15dk_nrf54l15` for more information about the development board and +`nRF54L05 website`_ for the official reference on the IC itself. + +.. _nRF54L05 website: https://www.nordicsemi.com/Products/nRF54L05 + +.. _nrf54l15dk_nrf54l10: + +nRF54L10 emulation on nRF54L15 DK +################################# + +Overview +******** + +The ``nrf54l15dk/nrf54l10`` board is a modified version of the :ref:`nrf54l15dk_nrf54l15` +that enforces the limitations imposed by the nRF54L10 IC, which is a +cost-reduced variant of the original nRF54L15. Since Nordic does not offer a +development kit for the nRF54L10 you can use this board to develop for this +IC while using the nRF54L15 Development Kit (PCA10156). + +See :ref:`nrf54l15dk_nrf54l15` for more information about the development board and +`nRF54L10 website`_ for the official reference on the IC itself. + +.. _nRF54L10 website: https://www.nordicsemi.com/Products/nRF54L10 diff --git a/boards/nordic/nrf54l15dk/support/nrf54l_05_10_15_cpuflpr.JLinkScript b/boards/nordic/nrf54l15dk/support/nrf54l_05_10_15_cpuflpr.JLinkScript new file mode 100644 index 00000000000..1cf94ee52a4 --- /dev/null +++ b/boards/nordic/nrf54l15dk/support/nrf54l_05_10_15_cpuflpr.JLinkScript @@ -0,0 +1,5 @@ +int InitTarget(void) { + // Base address where DMI registers can be found in the APB address space + JLINK_ExecCommand("CORESIGHT_SetCoreBaseAddr = 0x5004C400"); + return 0; +} diff --git a/boards/nordic/nrf54l20pdk/Kconfig.defconfig b/boards/nordic/nrf54l20pdk/Kconfig.defconfig index 850f69bdda0..f6987b80087 100644 --- a/boards/nordic/nrf54l20pdk/Kconfig.defconfig +++ b/boards/nordic/nrf54l20pdk/Kconfig.defconfig @@ -3,9 +3,6 @@ if BOARD_NRF54L20PDK_NRF54L20_CPUAPP -config BT_CTLR - default BT - config ROM_START_OFFSET default 0x800 if BOOTLOADER_MCUBOOT diff --git a/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20_cpuapp.yaml b/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20_cpuapp.yaml index d11ea0d869f..61266eb0da1 100644 --- a/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20_cpuapp.yaml +++ b/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20_cpuapp.yaml @@ -15,3 +15,5 @@ flash: 449 supported: - counter - gpio + - i2c + - watchdog diff --git a/boards/nordic/nrf7002dk/Kconfig b/boards/nordic/nrf7002dk/Kconfig index 1e2a7d09c93..bf5b239c98c 100644 --- a/boards/nordic/nrf7002dk/Kconfig +++ b/boards/nordic/nrf7002dk/Kconfig @@ -21,24 +21,9 @@ config HEAP_MEM_POOL_ADD_SIZE_BOARD int default 4096 if BT_HCI_IPC -config BOARD_ENABLE_CPUNET - bool "nRF53 Network MCU" - help - This option enables releasing the Network 'force off' signal, which - as a consequence will power up the Network MCU during system boot. - Additionally, the option allocates GPIO pins that will be used by UARTE - of the Network MCU. - Note: GPIO pin allocation can only be configured by the secure Application - MCU firmware, so when this option is used with the non-secure version of - the board, the application needs to take into consideration, that the - secure firmware image must already have configured GPIO allocation for the - Network MCU. - default y if (BT || NRF_802154_SER_HOST) - config DOMAIN_CPUNET_BOARD string default "nrf7002dk/nrf5340/cpunet" - depends on BOARD_ENABLE_CPUNET help The board which will be used for CPUNET domain when creating a multi image application where one or more images should be located on @@ -49,9 +34,6 @@ endif if BOARD_NRF7002DK_NRF5340_CPUNET -config BT_CTLR - default y if BT - config BT_ECC default y if BT diff --git a/boards/nordic/nrf7002dk/nrf5340_cpuapp_common.dtsi b/boards/nordic/nrf7002dk/nrf5340_cpuapp_common.dtsi index cff6e54fd5d..8a54d6da416 100644 --- a/boards/nordic/nrf7002dk/nrf5340_cpuapp_common.dtsi +++ b/boards/nordic/nrf7002dk/nrf5340_cpuapp_common.dtsi @@ -111,6 +111,15 @@ mcuboot-led0 = &led0; watchdog0 = &wdt0; }; + + nrf_radio_coex: coex { + status = "okay"; + compatible = "nordic,nrf7002-coex"; + req-gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; + status0-gpios = <&gpio0 30 GPIO_ACTIVE_HIGH>; + grant-gpios = <&gpio0 24 (GPIO_PULL_DOWN | GPIO_ACTIVE_LOW)>; + swctrl1-gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; + }; }; &vregmain { diff --git a/boards/nordic/nrf7002dk/nrf5340_cpunet_reset.c b/boards/nordic/nrf7002dk/nrf5340_cpunet_reset.c deleted file mode 100644 index b86b571db4b..00000000000 --- a/boards/nordic/nrf7002dk/nrf5340_cpunet_reset.c +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright (c) 2024 Nordic Semiconductor ASA - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include - -#include -#include - -LOG_MODULE_REGISTER(nrf7002dk_nrf5340_cpuapp, CONFIG_LOG_DEFAULT_LEVEL); - -#if defined(CONFIG_BT_CTLR_DEBUG_PINS_CPUAPP) -#include <../subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/debug.h> -#endif - -static void remoteproc_mgr_config(void) -{ -#if defined(CONFIG_BT_CTLR_DEBUG_PINS_CPUAPP) && \ - (!defined(CONFIG_TRUSTED_EXECUTION_NONSECURE) || defined(CONFIG_BUILD_WITH_TFM)) - /* Route Bluetooth Controller Debug Pins */ - DEBUG_SETUP(); -#endif /* !defined(CONFIG_TRUSTED_EXECUTION_NONSECURE) || defined(CONFIG_BUILD_WITH_TFM) */ - -#if !defined(CONFIG_TRUSTED_EXECUTION_NONSECURE) - /* Retain nRF5340 Network MCU in Secure domain (bus - * accesses by Network MCU will have Secure attribute set). - */ - NRF_SPU->EXTDOMAIN[0].PERM = BIT(4); -#endif /* !defined(CONFIG_TRUSTED_EXECUTION_NONSECURE) */ -} - -static int remoteproc_mgr_boot(void) -{ - - /* Secure domain may configure permissions for the Network MCU. */ - remoteproc_mgr_config(); - -#if !defined(CONFIG_TRUSTED_EXECUTION_SECURE) - /* - * Building Zephyr with CONFIG_TRUSTED_EXECUTION_SECURE=y implies - * building also a Non-Secure image. The Non-Secure image will, in - * this case do the remainder of actions to properly configure and - * boot the Network MCU. - */ - - /* Release the Network MCU, 'Release force off signal' */ - nrf_reset_network_force_off(NRF_RESET, false); - - LOG_DBG("Network MCU released."); -#endif /* !CONFIG_TRUSTED_EXECUTION_SECURE */ - - return 0; -} - -SYS_INIT(remoteproc_mgr_boot, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE); diff --git a/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_defconfig b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_defconfig index 24eee284902..8b28700426e 100644 --- a/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_defconfig +++ b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_defconfig @@ -12,12 +12,12 @@ CONFIG_ARM_TRUSTZONE_M=y # Enable GPIO CONFIG_GPIO=y -# Enable PINCTRL -CONFIG_PINCTRL=y - -# Enable uart driver +# Enable UART driver CONFIG_SERIAL=y -# enable console +# Enable console CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y + +# ISN needs CS-Rand which isn't supported upstream for nRF boards +CONFIG_NET_TCP_ISN_RFC6528=n diff --git a/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_nrf7001_defconfig b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_nrf7001_defconfig index 870fdf32425..33a414dc380 100644 --- a/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_nrf7001_defconfig +++ b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_nrf7001_defconfig @@ -10,15 +10,12 @@ CONFIG_HW_STACK_PROTECTION=y # Enable TrustZone-M CONFIG_ARM_TRUSTZONE_M=y -# enable GPIO +# Enable GPIO CONFIG_GPIO=y -# enable PINCTRL -CONFIG_PINCTRL=y - -# Enable uart driver +# Enable UART driver CONFIG_SERIAL=y -# enable console +# Enable console CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y diff --git a/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpunet_defconfig b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpunet_defconfig index ec4a0acd7a8..56940c43a09 100644 --- a/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpunet_defconfig +++ b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpunet_defconfig @@ -6,15 +6,12 @@ CONFIG_ARM_MPU=y # Enable hardware stack protection CONFIG_HW_STACK_PROTECTION=y -# enable GPIO +# Enable GPIO CONFIG_GPIO=y -# enable PINCTRL -CONFIG_PINCTRL=y - -# Enable uart driver +# Enable UART driver CONFIG_SERIAL=y -# enable console +# Enable console CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y diff --git a/boards/nordic/nrf9131ek/nrf9131ek_nrf9131_defconfig b/boards/nordic/nrf9131ek/nrf9131ek_nrf9131_defconfig index 4936d06617f..c486d832382 100644 --- a/boards/nordic/nrf9131ek/nrf9131ek_nrf9131_defconfig +++ b/boards/nordic/nrf9131ek/nrf9131ek_nrf9131_defconfig @@ -18,5 +18,3 @@ CONFIG_SERIAL=y # Enable console CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y - -CONFIG_PINCTRL=y diff --git a/boards/nordic/nrf9131ek/nrf9131ek_nrf9131_ns_defconfig b/boards/nordic/nrf9131ek/nrf9131ek_nrf9131_ns_defconfig index 4051bf70caa..5690c239b7b 100644 --- a/boards/nordic/nrf9131ek/nrf9131ek_nrf9131_ns_defconfig +++ b/boards/nordic/nrf9131ek/nrf9131ek_nrf9131_ns_defconfig @@ -22,8 +22,6 @@ CONFIG_SERIAL=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y -CONFIG_PINCTRL=y - # Enable PMIC CONFIG_I2C=y CONFIG_REGULATOR=y diff --git a/boards/nordic/nrf9160dk/Kconfig.defconfig b/boards/nordic/nrf9160dk/Kconfig.defconfig index 11880ae2a13..b26c68ef531 100644 --- a/boards/nordic/nrf9160dk/Kconfig.defconfig +++ b/boards/nordic/nrf9160dk/Kconfig.defconfig @@ -45,9 +45,6 @@ endif # BOARD_NRF9160DK_NRF9160 || BOARD_NRF9160DK_NRF9160_NS if BOARD_NRF9160DK_NRF52840 -config BT_CTLR - default BT - config BT_WAIT_NOP default BT && $(dt_nodelabel_enabled,reset_input) diff --git a/boards/nordic/nrf9280pdk/Kconfig.defconfig b/boards/nordic/nrf9280pdk/Kconfig.defconfig index c5c3576b4c2..d1252a0a3a2 100644 --- a/boards/nordic/nrf9280pdk/Kconfig.defconfig +++ b/boards/nordic/nrf9280pdk/Kconfig.defconfig @@ -10,9 +10,6 @@ endif # BOARD_NRF9280PDK_NRF9280_CPUAPP if BOARD_NRF9280PDK_NRF9280_CPURAD -config BT_CTLR - default y if BT - endif # BOARD_NRF9280PDK_NRF9280_CPURAD if BOARD_NRF9280PDK_NRF9280_CPUPPR diff --git a/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuapp.dts b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuapp.dts index 043f6f64f87..09bc9c554cc 100644 --- a/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuapp.dts +++ b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuapp.dts @@ -191,10 +191,6 @@ ipc0: &cpuapp_cpurad_ipc { status = "okay"; }; -&dma_fast_region { - status = "okay"; -}; - &cpuapp_rx_partitions { status = "okay"; }; @@ -275,6 +271,8 @@ ipc0: &cpuapp_cpurad_ipc { t-enter-dpd = <10000>; t-exit-dpd = <30000>; reset-gpios = <&gpio6 12 GPIO_ACTIVE_LOW>; + t-reset-pulse = <10000>; + t-reset-recovery = <35000>; mspi-max-frequency = ; mspi-io-mode = "MSPI_IO_MODE_OCTAL"; diff --git a/boards/nordic/thingy52/Kconfig.defconfig b/boards/nordic/thingy52/Kconfig.defconfig index 40bdd8c6cdf..9e50838b5c2 100644 --- a/boards/nordic/thingy52/Kconfig.defconfig +++ b/boards/nordic/thingy52/Kconfig.defconfig @@ -5,7 +5,4 @@ if BOARD_THINGY52 -config BT_CTLR - default BT - endif # BOARD_THINGY52 diff --git a/boards/nordic/thingy53/Kconfig b/boards/nordic/thingy53/Kconfig index 01b2ee7dfcf..a6781f63b0e 100644 --- a/boards/nordic/thingy53/Kconfig +++ b/boards/nordic/thingy53/Kconfig @@ -11,10 +11,6 @@ config THINGY53_INIT_PRIORITY if BOARD_THINGY53_NRF5340_CPUAPP || BOARD_THINGY53_NRF5340_CPUAPP_NS -config BOARD_SERIAL_BACKEND_CDC_ACM - bool "USB CDC" - default y - config DOMAIN_CPUNET_BOARD string default "thingy53/nrf5340/cpunet" diff --git a/boards/nordic/thingy53/Kconfig.defconfig b/boards/nordic/thingy53/Kconfig.defconfig index 31ac0093ba2..f024144451a 100644 --- a/boards/nordic/thingy53/Kconfig.defconfig +++ b/boards/nordic/thingy53/Kconfig.defconfig @@ -85,58 +85,7 @@ config REGULATOR endif # !TRUSTED_EXECUTION_SECURE -if BOARD_SERIAL_BACKEND_CDC_ACM - -config USB_DEVICE_PRODUCT - default "Thingy:53 Application" - -config USB_DEVICE_VID - default 0x1915 - -config USB_DEVICE_PID - default 0x530C - -config USB_DEVICE_STACK - default y - -config USB_CDC_ACM - default y - -config UART_CONSOLE - default CONSOLE - -config USB_DEVICE_INITIALIZE_AT_BOOT - default y if !MCUBOOT - -config SHELL_BACKEND_SERIAL_CHECK_DTR - default SHELL - depends on UART_LINE_CTRL - -config UART_LINE_CTRL - default SHELL - -config USB_DEVICE_REMOTE_WAKEUP - default n - -if LOG - -# Logger cannot use itself to log -choice USB_CDC_ACM_LOG_LEVEL_CHOICE - default USB_CDC_ACM_LOG_LEVEL_OFF -endchoice - -# Set USB log level to error only -choice USB_DEVICE_LOG_LEVEL_CHOICE - default USB_DEVICE_LOG_LEVEL_ERR -endchoice - -# Wait 4000ms at startup for logging -config LOG_PROCESS_THREAD_STARTUP_DELAY_MS - default 4000 - -endif # LOG - -endif # BOARD_SERIAL_BACKEND_CDC_ACM +source "boards/common/usb/Kconfig.cdc_acm_serial.defconfig" # By default, a USB CDC ACM instance is already enabled in the board's DTS. # It is not necessary for nRF Connect SDK to add another instance if MCUBoot @@ -152,9 +101,6 @@ endif # BOARD_THINGY53_NRF5340_CPUAPP || BOARD_THINGY53_NRF5340_CPUAPP_NS if BOARD_THINGY53_NRF5340_CPUNET -config BT_CTLR - default BT - config BT_ECC default BT diff --git a/boards/nordic/thingy53/thingy53_nrf5340_common.dtsi b/boards/nordic/thingy53/thingy53_nrf5340_common.dtsi index e4028edfc94..8bc98ef65b4 100644 --- a/boards/nordic/thingy53/thingy53_nrf5340_common.dtsi +++ b/boards/nordic/thingy53/thingy53_nrf5340_common.dtsi @@ -9,11 +9,6 @@ / { chosen { - zephyr,console = &cdc_acm_uart; - zephyr,shell-uart = &cdc_acm_uart; - zephyr,uart-mcumgr = &cdc_acm_uart; - zephyr,bt-mon-uart = &cdc_acm_uart; - zephyr,bt-c2h-uart = &cdc_acm_uart; zephyr,bt-hci-ipc = &ipc0; zephyr,bt-hci = &bt_hci_ipc0; nordic,802154-spinel-ipc = &ipc0; @@ -317,10 +312,6 @@ edge_connector_spi: &spi4 { zephyr_udc0: &usbd { compatible = "nordic,nrf-usbd"; status = "okay"; - - cdc_acm_uart: cdc_acm_uart { - compatible = "zephyr,cdc-acm-uart"; - }; }; /* Include default memory partition configuration file */ diff --git a/boards/nordic/thingy53/thingy53_nrf5340_cpuapp.dts b/boards/nordic/thingy53/thingy53_nrf5340_cpuapp.dts index d058f8da95b..9f3d7d46674 100644 --- a/boards/nordic/thingy53/thingy53_nrf5340_cpuapp.dts +++ b/boards/nordic/thingy53/thingy53_nrf5340_cpuapp.dts @@ -7,6 +7,7 @@ /dts-v1/; #include #include "thingy53_nrf5340_common.dtsi" +#include <../boards/common/usb/cdc_acm_serial.dtsi> / { model = "Nordic Thingy53 NRF5340 Application"; @@ -36,3 +37,8 @@ &vregh { status = "okay"; }; + +&lfxo { + load-capacitors = "internal"; + load-capacitance-picofarad = <7>; +}; diff --git a/boards/nordic/thingy53/thingy53_nrf5340_cpuapp_ns.dts b/boards/nordic/thingy53/thingy53_nrf5340_cpuapp_ns.dts index 84fb9fbfc94..8a754664325 100644 --- a/boards/nordic/thingy53/thingy53_nrf5340_cpuapp_ns.dts +++ b/boards/nordic/thingy53/thingy53_nrf5340_cpuapp_ns.dts @@ -7,6 +7,7 @@ /dts-v1/; #include #include "thingy53_nrf5340_common.dtsi" +#include <../boards/common/usb/cdc_acm_serial.dtsi> / { model = "Nordic Thingy53 NRF5340 Application"; @@ -34,3 +35,8 @@ &vregh { status = "okay"; }; + +&lfxo { + load-capacitors = "internal"; + load-capacitance-picofarad = <7>; +}; diff --git a/boards/norik/index.rst b/boards/norik/index.rst new file mode 100644 index 00000000000..11d8f1353f5 --- /dev/null +++ b/boards/norik/index.rst @@ -0,0 +1,10 @@ +.. _boards-norik: + +Norik Systems +############# + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/norik/octopus_io_board/CMakeLists.txt b/boards/norik/octopus_io_board/CMakeLists.txt new file mode 100644 index 00000000000..2e35c87b81d --- /dev/null +++ b/boards/norik/octopus_io_board/CMakeLists.txt @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Norik Systems +# SPDX-License-Identifier: Apache-2.0 + +zephyr_library() +zephyr_library_sources(board.c) diff --git a/boards/norik/octopus_io_board/Kconfig b/boards/norik/octopus_io_board/Kconfig new file mode 100644 index 00000000000..74f296b0e3e --- /dev/null +++ b/boards/norik/octopus_io_board/Kconfig @@ -0,0 +1,10 @@ +# Copyright (c) 2024 Norik Systems +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_OCTOPUS_IO_BOARD + select BOARD_LATE_INIT_HOOK + select GPIO + +module = OCTOPUS_IO_BOARD_CONTROL +module-str = Board Control +source "subsys/logging/Kconfig.template.log_config" diff --git a/boards/norik/octopus_io_board/Kconfig.defconfig b/boards/norik/octopus_io_board/Kconfig.defconfig new file mode 100644 index 00000000000..4c00ab52ab5 --- /dev/null +++ b/boards/norik/octopus_io_board/Kconfig.defconfig @@ -0,0 +1,33 @@ +# Copyright (c) 2024 Norik Systems +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_OCTOPUS_IO_BOARD + +# For the secure version of the board the firmware is linked at the beginning +# of the flash, or into the code-partition defined in DT if it is intended to +# be loaded by MCUboot. If the secure firmware is to be combined with a non- +# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always +# be restricted to the size of its code partition. +# For the non-secure version of the board, the firmware +# must be linked into the code-partition (non-secure) defined in DT, regardless. +# Apply this configuration below by setting the Kconfig symbols used by +# the linker according to the information extracted from DT partitions. + +# Workaround for not being able to have commas in macro arguments +DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + depends on BOARD_OCTOPUS_IO_BOARD && TRUSTED_EXECUTION_SECURE + +if BOARD_OCTOPUS_IO_BOARD_NRF9160_NS + +config FLASH_LOAD_OFFSET + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +endif # BOARD_OCTOPUS_IO_BOARD_NRF9160_NS + +endif # BOARD_OCTOPUS_IO_BOARD diff --git a/boards/norik/octopus_io_board/Kconfig.octopus_io_board b/boards/norik/octopus_io_board/Kconfig.octopus_io_board new file mode 100644 index 00000000000..1b24864afda --- /dev/null +++ b/boards/norik/octopus_io_board/Kconfig.octopus_io_board @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Norik Systems +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_OCTOPUS_IO_BOARD + select SOC_NRF9160_SICA diff --git a/boards/norik/octopus_io_board/board.c b/boards/norik/octopus_io_board/board.c new file mode 100644 index 00000000000..901bdae01d8 --- /dev/null +++ b/boards/norik/octopus_io_board/board.c @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2024 Norik Systems + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include + +LOG_MODULE_REGISTER(board_control, CONFIG_OCTOPUS_IO_BOARD_CONTROL_LOG_LEVEL); + +#define SIM_SELECT_NODE DT_PATH(sim_select) + +void board_late_init_hook(void) +{ + const struct gpio_dt_spec simctrl = GPIO_DT_SPEC_GET(DT_PATH(sim_select), sim_gpios); + + if (!gpio_is_ready_dt(&simctrl)) { + LOG_ERR("SIM select GPIO not available"); + return; + } + + if (DT_ENUM_IDX(SIM_SELECT_NODE, sim) == 0) { + (void)gpio_pin_configure_dt(&simctrl, GPIO_OUTPUT_LOW); + LOG_INF("On-board SIM selected"); + } else { + (void)gpio_pin_configure_dt(&simctrl, GPIO_OUTPUT_HIGH); + LOG_INF("External SIM selected"); + } +} diff --git a/boards/norik/octopus_io_board/board.cmake b/boards/norik/octopus_io_board/board.cmake new file mode 100644 index 00000000000..e1ae7b4e9b2 --- /dev/null +++ b/boards/norik/octopus_io_board/board.cmake @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Norik Systems +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=nRF9160_xxAA" "--speed=4000") +include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/norik/octopus_io_board/board.yml b/boards/norik/octopus_io_board/board.yml new file mode 100644 index 00000000000..fe114911b3a --- /dev/null +++ b/boards/norik/octopus_io_board/board.yml @@ -0,0 +1,8 @@ +board: + name: octopus_io_board + full_name: Octopus IO-Board + vendor: norik + socs: + - name: nrf9160 + variants: + - name: 'ns' diff --git a/boards/norik/octopus_io_board/doc/img/octopus_io_board.webp b/boards/norik/octopus_io_board/doc/img/octopus_io_board.webp new file mode 100644 index 00000000000..ea170c7e3c0 Binary files /dev/null and b/boards/norik/octopus_io_board/doc/img/octopus_io_board.webp differ diff --git a/boards/norik/octopus_io_board/doc/index.rst b/boards/norik/octopus_io_board/doc/index.rst new file mode 100644 index 00000000000..088a3b936d3 --- /dev/null +++ b/boards/norik/octopus_io_board/doc/index.rst @@ -0,0 +1,146 @@ +.. zephyr:board:: octopus_io_board + +Overview +******** + +Octopus IO-Board is an expansion to the Octopus SoM, which is built around the nRF9160 SiP +offering NB-IoT and LTE-M connectivity, GPS and accelerometer. Octopus IO-Board expands +the capabilities of the Octopus SoM by providing additional peripherals and interfaces for +development and prototyping of low-power IoT applications. + +nRF9160 SiP contains ARM Cortex-M33 application processor and the +following devices: + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* :abbr:`RTC (nRF RTC System Clock)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UARTE (Universal asynchronous receiver-transmitter with EasyDMA)` +* :abbr:`WDT (Watchdog Timer)` +* :abbr:`IDAU (Implementation Defined Attribution Unit)` + +Octopus IO-Board offers the following features: + +* Battery charger +* USB-C for power +* Solar charger +* Alkaline battery input +* LDO regulator to power Octopus SoM and peripherals +* Battery monitoring using ADC +* 64 Mbit SPI NOR flash +* Dedicated ADC, GPIO, I2C, SPI and UARTE pins for expansion +* Exposed headers for current measurements +* Nano SIM connector +* Tag-Connect TC2030-IDC 6-pin connector for SWD programming and debugging +* 2x3 pinheader for SWD programming and debugging + +More information about the board can be found at the `Octopus IO-Board Product Page`_ +and in the `Octopus IO-Board Documentation`_. + +Hardware +******** + +Connections and IOs +=================== + +The Octopus IO-Board features multiple dedicated pin headers for peripherals: + +* 3x I2C0 bus +* 2x SPI0 bus +* 3x I2C1/SPI1 bus (selectable) +* 1x UARTE0 bus +* 1x Analog input (5 input pins) +* 1x GPIO (7 I/O pins) + +The I2C1/SPI1 bus is selectable by the user by cutting/soldering SB8 and SB9 solder bridges and configuring the bus in the device tree. + +The GPIO pin header provides 7 I/O pins, which can be used as digital input/output. Some of them also serve as chip selects for SPI peripherals. + +Power supply +============ + +The Octopus IO-Board can be powered from the following sources: + +* USB-C connector +* Solar cell +* Alkaline battery +* Li-Po battery + +When powered from USB-C or solar cell, the board can charge the Li-Po battery. The battery voltage can be monitored using ADC which can +provide information about the battery State of charge (SOC). + +When powered from alkaline battery, the user needs to set switch SW1 to ALK position. This ensures that the Li-Ion battery is not charged from the alkaline battery. + +The board has a built-in LDO regulator that is used to power the Octopus SoM and peripherals. The EN2 pin can be used to enable/disable output 2 of the LDO regulator. +This can be used to power off peripherals to save power when they are not needed. + +The board also has multiple built-in test points for measuring current consumption of the board, which enables the user to measure and optimize the power consumption of the board. + +Programming and Debugging +************************* + +Norik Octopus IO-Board can be programmed and debugged using the Tag-Connect TC2030-IDC 6-pin connector or 6-pin SWD pinheader. + +Building an application +======================= + +In most case you'll need to use ``octopus_io_board/nrf9160/ns`` board target for building examples. +Some examples don't require non secure mode and can be built with ``octopus_io_board/nrf9160`` board target. + +Flashing +======== +Refer to the instruction in the :ref:`nordic_segger` page to install and +configure all the necessary software. + +Here is an example for the Hello World application. + +First, run your favorite terminal program to listen for output. + +.. code-block:: console + + $ minicom /dev/ 115200 + +Replace with the port where the Octopus IO-Board can be found. For example, under Linux, /dev/ttyACM0. + +Then build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: octopus_io_board/nrf9160 + :goals: build flash + +To build and flash the application in non-secure mode, use the following command: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: octopus_io_board/nrf9160/ns + :goals: build flash + +Debugging +========= +Refer to the instruction in the :ref:`nordic_segger` page for information on +debugging. + +Testing the on-board LED +======================== +Use the :zephyr:code-sample:`blinky` to test the on-board LED. Build and flash the example to make sure Zephyr is running correctly on your board. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: octopus_io_board/nrf9160 + :goals: build flash + +References +********** + +.. target-notes:: + +.. _Octopus IO-Board Product Page: https://www.norik.com/octopus-io-board/ +.. _Octopus IO-Board Documentation: https://www.norik.com/wp-content/uploads/2024/09/Octopus_IO-Board_Datasheet.pdf diff --git a/boards/norik/octopus_io_board/dts/bindings/norik,sim_select.yaml b/boards/norik/octopus_io_board/dts/bindings/norik,sim_select.yaml new file mode 100644 index 00000000000..2745afaac94 --- /dev/null +++ b/boards/norik/octopus_io_board/dts/bindings/norik,sim_select.yaml @@ -0,0 +1,26 @@ +# Copyright (c) 2024 Norik Systems +# SPDX-License-Identifier: Apache-2.0 + +description: | + The Octopus SoM provides the user 2 options for connecting + a SIM card to the nRF9160. Option one is to use on-board eSIM or + external nano SIM. Which SIM is used can be selected using the 'sim' + property of the 'sim_select' dt node. + +compatible: "norik,sim_select" + +include: base.yaml + +properties: + sim-gpios: + type: phandle-array + required: true + description: Pin used to select which SIM is used + + sim: + type: string + required: true + enum: + - "on-board" + - "external" + description: SIM choice (on-board eSIM or external nano SIM) diff --git a/boards/norik/octopus_io_board/octopus_io_board_common-pinctrl.dtsi b/boards/norik/octopus_io_board/octopus_io_board_common-pinctrl.dtsi new file mode 100644 index 00000000000..8f46475d246 --- /dev/null +++ b/boards/norik/octopus_io_board/octopus_io_board_common-pinctrl.dtsi @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2024 Norik Systems + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + i2c0_default: i2c0_default { + group1 { + psels = , + ; + }; + }; + + i2c0_sleep: i2c0_sleep { + group1 { + psels = , + ; + low-power-enable; + }; + }; + + i2c1_default: i2c1_default { + group1 { + psels = , + ; + }; + }; + + i2c1_sleep: i2c1_sleep { + group1 { + psels = , + ; + low-power-enable; + }; + }; +}; diff --git a/boards/norik/octopus_io_board/octopus_io_board_common.dtsi b/boards/norik/octopus_io_board/octopus_io_board_common.dtsi new file mode 100644 index 00000000000..f73a0e20b03 --- /dev/null +++ b/boards/norik/octopus_io_board/octopus_io_board_common.dtsi @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2024 Norik Systems + * SPDX-License-Identifier: Apache-2.0 + */ +#include "octopus_io_board_common-pinctrl.dtsi" +#include "../octopus_som/octopus_som_common.dtsi" + +/ { + model = "Norik Octopus IO-Board"; + compatible = "norik,octopus-io-board"; + + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,uart-mcumgr = &uart0; + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + watchdog0 = &wdt0; + }; +}; + +&i2c1 { + compatible = "nordic,nrf-twim"; + status = "okay"; + pinctrl-0 = <&i2c0_default>; + pinctrl-1 = <&i2c0_sleep>; + pinctrl-names = "default", "sleep"; + + bq25180: bq25180@6a { + compatible = "ti,bq25180"; + status = "okay"; + reg = <0x6a>; + constant-charge-current-max-microamp = <10000>; + }; +}; + +&spi3 { + status = "okay"; + cs-gpios = <&gpio0 11 GPIO_ACTIVE_LOW>,<&gpio0 5 GPIO_ACTIVE_LOW>; + + adxl362: adxl362@0 { + compatible = "adi,adxl362"; + spi-max-frequency = <8000000>; + reg = <0>; + int1-gpios = <&gpio0 12 0>; + }; + + w25q64: w25q64@1 { + compatible = "jedec,spi-nor"; + status = "okay"; + reg = <1>; + spi-max-frequency = <8000000>; + jedec-id = [ef 40 17]; + size = <0x4000000>; + has-dpd; + t-enter-dpd = <3500>; + t-exit-dpd = <3500>; + }; +}; diff --git a/boards/norik/octopus_io_board/octopus_io_board_defconfig b/boards/norik/octopus_io_board/octopus_io_board_defconfig new file mode 100644 index 00000000000..c486d832382 --- /dev/null +++ b/boards/norik/octopus_io_board/octopus_io_board_defconfig @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable TrustZone-M +CONFIG_ARM_TRUSTZONE_M=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/norik/octopus_io_board/octopus_io_board_nrf9160.dts b/boards/norik/octopus_io_board/octopus_io_board_nrf9160.dts new file mode 100644 index 00000000000..aae7cb1f345 --- /dev/null +++ b/boards/norik/octopus_io_board/octopus_io_board_nrf9160.dts @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2024 Norik Systems + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "octopus_io_board_common.dtsi" + +/ { + chosen { + zephyr,sram = &sram0_s; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + zephyr,sram-secure-partition = &sram0_s; + zephyr,sram-non-secure-partition = &sram0_ns; + }; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; +}; diff --git a/boards/norik/octopus_io_board/octopus_io_board_nrf9160.yaml b/boards/norik/octopus_io_board/octopus_io_board_nrf9160.yaml new file mode 100644 index 00000000000..e91c1da14b5 --- /dev/null +++ b/boards/norik/octopus_io_board/octopus_io_board_nrf9160.yaml @@ -0,0 +1,17 @@ +identifier: octopus_io_board/nrf9160 +name: Norik Octopus IO-Board +type: mcu +arch: arm +ram: 88 +flash: 1024 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - gpio + - i2c + - spi + - pwm + - watchdog +vendor: norik diff --git a/boards/norik/octopus_io_board/octopus_io_board_nrf9160_ns.dts b/boards/norik/octopus_io_board/octopus_io_board_nrf9160_ns.dts new file mode 100644 index 00000000000..fa24ffbf565 --- /dev/null +++ b/boards/norik/octopus_io_board/octopus_io_board_nrf9160_ns.dts @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2024 Norik Systems + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "octopus_io_board_common.dtsi" + +/ { + chosen { + zephyr,flash = &flash0; + zephyr,sram = &sram0_ns; + zephyr,code-partition = &slot0_ns_partition; + }; +}; + +/* Disable UART1, because it is used by default in TF-M */ + +&uart1 { + status = "disabled"; +}; diff --git a/boards/norik/octopus_io_board/octopus_io_board_nrf9160_ns.yaml b/boards/norik/octopus_io_board/octopus_io_board_nrf9160_ns.yaml new file mode 100644 index 00000000000..675c316f6c2 --- /dev/null +++ b/boards/norik/octopus_io_board/octopus_io_board_nrf9160_ns.yaml @@ -0,0 +1,17 @@ +identifier: octopus_io_board/nrf9160/ns +name: Norik Octopus IO-Board Non-Secure +type: mcu +arch: arm +ram: 128 +flash: 192 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - gpio + - i2c + - spi + - pwm + - watchdog +vendor: norik diff --git a/boards/norik/octopus_io_board/octopus_io_board_nrf9160_ns_defconfig b/boards/norik/octopus_io_board/octopus_io_board_nrf9160_ns_defconfig new file mode 100644 index 00000000000..0f0b3336db6 --- /dev/null +++ b/boards/norik/octopus_io_board/octopus_io_board_nrf9160_ns_defconfig @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable TrustZone-M +CONFIG_ARM_TRUSTZONE_M=y + +# This Board implies building Non-Secure firmware +CONFIG_TRUSTED_EXECUTION_NONSECURE=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/norik/octopus_som/CMakeLists.txt b/boards/norik/octopus_som/CMakeLists.txt new file mode 100644 index 00000000000..2e35c87b81d --- /dev/null +++ b/boards/norik/octopus_som/CMakeLists.txt @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Norik Systems +# SPDX-License-Identifier: Apache-2.0 + +zephyr_library() +zephyr_library_sources(board.c) diff --git a/boards/norik/octopus_som/Kconfig b/boards/norik/octopus_som/Kconfig new file mode 100644 index 00000000000..090a8e9af85 --- /dev/null +++ b/boards/norik/octopus_som/Kconfig @@ -0,0 +1,10 @@ +# Copyright (c) 2024 Norik Systems +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_OCTOPUS_SOM + select BOARD_LATE_INIT_HOOK + select GPIO + +module = OCTOPUS_SOM_CONTROL +module-str = Board Control +source "subsys/logging/Kconfig.template.log_config" diff --git a/boards/norik/octopus_som/Kconfig.defconfig b/boards/norik/octopus_som/Kconfig.defconfig new file mode 100644 index 00000000000..6fe9d1618a5 --- /dev/null +++ b/boards/norik/octopus_som/Kconfig.defconfig @@ -0,0 +1,33 @@ +# Copyright (c) 2024 Norik Systems +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_OCTOPUS_SOM + +# For the secure version of the board the firmware is linked at the beginning +# of the flash, or into the code-partition defined in DT if it is intended to +# be loaded by MCUboot. If the secure firmware is to be combined with a non- +# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always +# be restricted to the size of its code partition. +# For the non-secure version of the board, the firmware +# must be linked into the code-partition (non-secure) defined in DT, regardless. +# Apply this configuration below by setting the Kconfig symbols used by +# the linker according to the information extracted from DT partitions. + +# Workaround for not being able to have commas in macro arguments +DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + depends on BOARD_OCTOPUS_SOM && TRUSTED_EXECUTION_SECURE + +if BOARD_OCTOPUS_SOM_NRF9160_NS + +config FLASH_LOAD_OFFSET + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +endif # BOARD_OCTOPUS_SOM_NRF9160_NS + +endif # BOARD_OCTOPUS_SOM diff --git a/boards/norik/octopus_som/Kconfig.octopus_som b/boards/norik/octopus_som/Kconfig.octopus_som new file mode 100644 index 00000000000..c249d541948 --- /dev/null +++ b/boards/norik/octopus_som/Kconfig.octopus_som @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Norik Systems +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_OCTOPUS_SOM + select SOC_NRF9160_SICA diff --git a/boards/norik/octopus_som/board.c b/boards/norik/octopus_som/board.c new file mode 100644 index 00000000000..c741ca686aa --- /dev/null +++ b/boards/norik/octopus_som/board.c @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2024 Norik Systems + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include + +LOG_MODULE_REGISTER(board_control, CONFIG_OCTOPUS_SOM_CONTROL_LOG_LEVEL); + +#define SIM_SELECT_NODE DT_PATH(sim_select) + +void board_late_init_hook(void) +{ + const struct gpio_dt_spec simctrl = GPIO_DT_SPEC_GET(DT_PATH(sim_select), sim_gpios); + + if (!gpio_is_ready_dt(&simctrl)) { + LOG_ERR("SIM select GPIO not available"); + return; + } + + if (DT_ENUM_IDX(SIM_SELECT_NODE, sim) == 0) { + (void)gpio_pin_configure_dt(&simctrl, GPIO_OUTPUT_LOW); + LOG_INF("On-board SIM selected"); + } else { + (void)gpio_pin_configure_dt(&simctrl, GPIO_OUTPUT_HIGH); + LOG_INF("External SIM selected"); + } +} diff --git a/boards/norik/octopus_som/board.cmake b/boards/norik/octopus_som/board.cmake new file mode 100644 index 00000000000..e1ae7b4e9b2 --- /dev/null +++ b/boards/norik/octopus_som/board.cmake @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Norik Systems +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=nRF9160_xxAA" "--speed=4000") +include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/norik/octopus_som/board.yml b/boards/norik/octopus_som/board.yml new file mode 100644 index 00000000000..efd094baea7 --- /dev/null +++ b/boards/norik/octopus_som/board.yml @@ -0,0 +1,8 @@ +board: + name: octopus_som + full_name: Octopus SoM + vendor: norik + socs: + - name: nrf9160 + variants: + - name: 'ns' diff --git a/boards/norik/octopus_som/doc/img/octopus_som.webp b/boards/norik/octopus_som/doc/img/octopus_som.webp new file mode 100644 index 00000000000..9bd8e8ed2dd Binary files /dev/null and b/boards/norik/octopus_som/doc/img/octopus_som.webp differ diff --git a/boards/norik/octopus_som/doc/index.rst b/boards/norik/octopus_som/doc/index.rst new file mode 100644 index 00000000000..1d3790a04d7 --- /dev/null +++ b/boards/norik/octopus_som/doc/index.rst @@ -0,0 +1,125 @@ +.. zephyr:board:: octopus_som + +Overview +******** + +Octopus SoM is a System on Module (SoM) built around the nRF9160 SiP +offering NB-IoT and LTE-M connectivity, GPS and accelerometer. +It supports on board eSIM and external nano SIM connector. It's purpose +is to provide flexible hardware platform for IoT applications. + +nRF9160 SiP contains ARM Cortex-M33 application processor and the +following devices: + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* :abbr:`RTC (nRF RTC System Clock)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UARTE (Universal asynchronous receiver-transmitter with EasyDMA)` +* :abbr:`WDT (Watchdog Timer)` +* :abbr:`IDAU (Implementation Defined Attribution Unit)` + +More information about the board can be found at the `Octopus SoM Product Page`_ and +in the `Octopus SoM Documentation`_. + +Hardware +******** + +The ``octopus_som/nrf9160`` and ``octopus_som/nrf9160/ns`` board targets support the +following hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| RTT | Segger | console | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| SPU | on-chip | system protection | ++-----------+------------+----------------------+ +| UARTE | on-chip | serial | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ +| ACCEL | Analog | adxl362 | ++-----------+------------+----------------------+ + +Connections and IOs +=================== + +Accelerometer +------------- +* MISO = P0.05 +* MOSI = P0.09 +* SCK = P0.10 +* CS = P0.05 +* INT1 = P0.12 + +LED +--- +* LED1 (green) = P0.07 + +SIM select switch +----------------- +* Select = P0.25 + +Programming and Debugging +************************* + +Norik Octopus SoM can be programmed and debugged using the exposed SWD pins. + +Building an application +======================= + +In most case you'll need to use ``octopus_som/nrf9160/ns`` board target for building examples. +Some examples don't require non secure mode and can be built with ``octopus_som/nrf9160`` board target. + +Flashing +======== +Refer to the instruction in the :ref:`nordic_segger` page to install and +configure all the necessary software. + +Use the :zephyr:code-sample:`blinky` sample to test if Zephyr is running correctly on your board. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: octopus_som/nrf9160 + :goals: build flash + +Debugging +========= +Refer to the instruction in the :ref:`nordic_segger` page for information on +debugging. + +References +********** + +.. target-notes:: + +.. _Octopus SoM Product Page: https://www.norik.com/octopus-som/ +.. _Octopus SoM Documentation: https://www.norik.com/wp-content/uploads/2024/09/Octopus_SoM_Datasheet.pdf diff --git a/boards/norik/octopus_som/dts/bindings/norik,sim_select.yaml b/boards/norik/octopus_som/dts/bindings/norik,sim_select.yaml new file mode 100644 index 00000000000..2745afaac94 --- /dev/null +++ b/boards/norik/octopus_som/dts/bindings/norik,sim_select.yaml @@ -0,0 +1,26 @@ +# Copyright (c) 2024 Norik Systems +# SPDX-License-Identifier: Apache-2.0 + +description: | + The Octopus SoM provides the user 2 options for connecting + a SIM card to the nRF9160. Option one is to use on-board eSIM or + external nano SIM. Which SIM is used can be selected using the 'sim' + property of the 'sim_select' dt node. + +compatible: "norik,sim_select" + +include: base.yaml + +properties: + sim-gpios: + type: phandle-array + required: true + description: Pin used to select which SIM is used + + sim: + type: string + required: true + enum: + - "on-board" + - "external" + description: SIM choice (on-board eSIM or external nano SIM) diff --git a/boards/norik/octopus_som/octopus_som_common-pinctrl.dtsi b/boards/norik/octopus_som/octopus_som_common-pinctrl.dtsi new file mode 100644 index 00000000000..52e65b6302c --- /dev/null +++ b/boards/norik/octopus_som/octopus_som_common-pinctrl.dtsi @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2024 Norik Systems + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + uart0_default: uart0_default { + group1 { + psels = , + ; + }; + }; + + uart0_sleep: uart0_sleep { + group1 { + psels = , + ; + low-power-enable; + }; + }; + + pwm0_default: pwm0_default { + group1 { + psels = ; + }; + }; + + pwm0_sleep: pwm0_sleep { + group1 { + psels = ; + low-power-enable; + }; + }; + + spi3_default: spi3_default { + group1 { + psels = , + , + ; + }; + }; + + spi3_sleep: spi3_sleep { + group1 { + psels = , + , + ; + low-power-enable; + }; + }; +}; diff --git a/boards/norik/octopus_som/octopus_som_common.dtsi b/boards/norik/octopus_som/octopus_som_common.dtsi new file mode 100644 index 00000000000..538dfa3c0ec --- /dev/null +++ b/boards/norik/octopus_som/octopus_som_common.dtsi @@ -0,0 +1,94 @@ +/* + * Copyright (c) 2024 Norik Systems + * SPDX-License-Identifier: Apache-2.0 + */ +#include "octopus_som_common-pinctrl.dtsi" + +/ { + model = "Norik Octopus SoM"; + compatible = "norik,octopus-som"; + + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,uart-mcumgr = &uart0; + }; + + leds { + compatible = "gpio-leds"; + + led0: led_0 { + gpios = <&gpio0 7 0>; + label = "Green LED 1"; + }; + + }; + + pwmleds { + compatible = "pwm-leds"; + + pwm_led0: pwm_led_0 { + pwms = <&pwm0 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>; + }; + }; + + sim_select: sim_select { + compatible = "norik,sim_select"; + sim-gpios= <&gpio0 25 GPIO_ACTIVE_HIGH>; + sim = "external"; + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + led0 = &led0; + pwm-led0 = &pwm_led0; + watchdog0 = &wdt0; + accel0 = &adxl362; + }; +}; + +&adc { + status = "okay"; +}; + +&gpiote { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-1 = <&uart0_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&pwm0 { + status = "okay"; + pinctrl-0 = <&pwm0_default>; + pinctrl-1 = <&pwm0_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&spi3 { + compatible = "nordic,nrf-spim"; + status = "okay"; + cs-gpios = <&gpio0 11 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&spi3_default>; + pinctrl-1 = <&spi3_sleep>; + pinctrl-names = "default", "sleep"; + + adxl362: adxl362@0 { + compatible = "adi,adxl362"; + spi-max-frequency = <8000000>; + reg = <0>; + int1-gpios = <&gpio0 12 0>; + }; +}; + +/* Include default memory partition configuration file */ +#include diff --git a/boards/norik/octopus_som/octopus_som_defconfig b/boards/norik/octopus_som/octopus_som_defconfig new file mode 100644 index 00000000000..c486d832382 --- /dev/null +++ b/boards/norik/octopus_som/octopus_som_defconfig @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable TrustZone-M +CONFIG_ARM_TRUSTZONE_M=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/norik/octopus_som/octopus_som_nrf9160.dts b/boards/norik/octopus_som/octopus_som_nrf9160.dts new file mode 100644 index 00000000000..b0e9f77fe0d --- /dev/null +++ b/boards/norik/octopus_som/octopus_som_nrf9160.dts @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2024 Norik Systems + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "octopus_som_common.dtsi" + +/ { + chosen { + zephyr,sram = &sram0_s; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + zephyr,sram-secure-partition = &sram0_s; + zephyr,sram-non-secure-partition = &sram0_ns; + }; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; +}; diff --git a/boards/norik/octopus_som/octopus_som_nrf9160.yaml b/boards/norik/octopus_som/octopus_som_nrf9160.yaml new file mode 100644 index 00000000000..44a13234b8a --- /dev/null +++ b/boards/norik/octopus_som/octopus_som_nrf9160.yaml @@ -0,0 +1,17 @@ +identifier: octopus_som/nrf9160 +name: Norik Octopus SoM +type: mcu +arch: arm +ram: 88 +flash: 1024 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - gpio + - i2c + - spi + - pwm + - watchdog +vendor: norik diff --git a/boards/norik/octopus_som/octopus_som_nrf9160_ns.dts b/boards/norik/octopus_som/octopus_som_nrf9160_ns.dts new file mode 100644 index 00000000000..3cd80c2ca33 --- /dev/null +++ b/boards/norik/octopus_som/octopus_som_nrf9160_ns.dts @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2024 Norik Systems + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "octopus_som_common.dtsi" + +/ { + chosen { + zephyr,flash = &flash0; + zephyr,sram = &sram0_ns_app; + zephyr,code-partition = &slot0_ns_partition; + }; +}; diff --git a/boards/norik/octopus_som/octopus_som_nrf9160_ns.yaml b/boards/norik/octopus_som/octopus_som_nrf9160_ns.yaml new file mode 100644 index 00000000000..85bb40d75ab --- /dev/null +++ b/boards/norik/octopus_som/octopus_som_nrf9160_ns.yaml @@ -0,0 +1,17 @@ +identifier: octopus_som/nrf9160/ns +name: Norik Octopus SoM Non-Secure +type: mcu +arch: arm +ram: 128 +flash: 192 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - gpio + - i2c + - spi + - pwm + - watchdog +vendor: norik diff --git a/boards/norik/octopus_som/octopus_som_nrf9160_ns_defconfig b/boards/norik/octopus_som/octopus_som_nrf9160_ns_defconfig new file mode 100644 index 00000000000..0f0b3336db6 --- /dev/null +++ b/boards/norik/octopus_som/octopus_som_nrf9160_ns_defconfig @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable TrustZone-M +CONFIG_ARM_TRUSTZONE_M=y + +# This Board implies building Non-Secure firmware +CONFIG_TRUSTED_EXECUTION_NONSECURE=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/nuvoton/npcm400_evb/doc/index.rst b/boards/nuvoton/npcm400_evb/doc/index.rst index d5d9ee550c2..93c91eb474a 100644 --- a/boards/nuvoton/npcm400_evb/doc/index.rst +++ b/boards/nuvoton/npcm400_evb/doc/index.rst @@ -1,7 +1,4 @@ -.. _npcm400_evb: - -Nuvoton NPCM400_EVB -#################### +.. zephyr:board:: npcm400_evb Overview ******** @@ -10,10 +7,6 @@ The NPCM400_EVB kit is a development platform to evaluate the Nuvoton NPCM4 series microcontrollers. This board needs to be mated with part number NPCM400 Satellite Management Controller (SMC). -.. image:: npcm400_evb.webp - :align: center - :alt: NPCM400 Evaluation Board - Hardware ******** diff --git a/boards/nuvoton/npcm400_evb/npcm400_evb.yaml b/boards/nuvoton/npcm400_evb/npcm400_evb.yaml index c9628e4553d..f940445ff60 100644 --- a/boards/nuvoton/npcm400_evb/npcm400_evb.yaml +++ b/boards/nuvoton/npcm400_evb/npcm400_evb.yaml @@ -14,3 +14,5 @@ toolchain: ram: 768 flash: 1024 vendor: nuvoton +supported: + - clock diff --git a/boards/nuvoton/npcx4m8f_evb/doc/index.rst b/boards/nuvoton/npcx4m8f_evb/doc/index.rst index 928c4f2ce81..1fd1e7ae5d9 100644 --- a/boards/nuvoton/npcx4m8f_evb/doc/index.rst +++ b/boards/nuvoton/npcx4m8f_evb/doc/index.rst @@ -1,7 +1,4 @@ -.. _npcx4m8f_evb: - -Nuvoton NPCX4M8F_EVB -#################### +.. zephyr:board:: npcx4m8f_evb Overview ******** @@ -10,10 +7,6 @@ The NPCX4M8F_EVB kit is a development platform to evaluate the Nuvoton NPCX4 series microcontrollers. This board needs to be mated with part number NPCX498F. -.. image:: npcx4m8f_evb.jpg - :align: center - :alt: NPCX4M8F Evaluation Board - Hardware ******** diff --git a/boards/nuvoton/npcx4m8f_evb/npcx4m8f_evb.dts b/boards/nuvoton/npcx4m8f_evb/npcx4m8f_evb.dts index 2993b816956..e175105a7e1 100644 --- a/boards/nuvoton/npcx4m8f_evb/npcx4m8f_evb.dts +++ b/boards/nuvoton/npcx4m8f_evb/npcx4m8f_evb.dts @@ -7,6 +7,7 @@ /dts-v1/; #include +#include #include "npcx4m8f_evb-pinctrl.dtsi" / { diff --git a/boards/nuvoton/npcx4m8f_evb/npcx4m8f_evb_defconfig b/boards/nuvoton/npcx4m8f_evb/npcx4m8f_evb_defconfig index 05a91e020f3..f57da9fa69a 100644 --- a/boards/nuvoton/npcx4m8f_evb/npcx4m8f_evb_defconfig +++ b/boards/nuvoton/npcx4m8f_evb/npcx4m8f_evb_defconfig @@ -26,9 +26,6 @@ CONFIG_UART_INTERRUPT_DRIVEN=y # GPIO Driver CONFIG_GPIO=y -# Pin Controller Driver -CONFIG_PINCTRL=y - # Console Driver CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y diff --git a/boards/nuvoton/npcx7m6fb_evb/doc/index.rst b/boards/nuvoton/npcx7m6fb_evb/doc/index.rst index 3bcf013f84f..2dc8382d737 100644 --- a/boards/nuvoton/npcx7m6fb_evb/doc/index.rst +++ b/boards/nuvoton/npcx7m6fb_evb/doc/index.rst @@ -1,7 +1,4 @@ -.. _npcx7m6fb_evb: - -Nuvoton NPCX7M6FB_EVB -##################### +.. zephyr:board:: npcx7m6fb_evb Overview ******** @@ -10,10 +7,6 @@ The NPCX7M6FB_EVB kit is a development platform to evaluate the Nuvoton NPCX7 series microcontrollers. This board needs to be mated with part number NPCX796FB. -.. image:: npcx7m6fb_evb.jpg - :align: center - :alt: NPCX7M6FB Evaluation Board - Hardware ******** diff --git a/boards/nuvoton/npcx7m6fb_evb/npcx7m6fb_evb_defconfig b/boards/nuvoton/npcx7m6fb_evb/npcx7m6fb_evb_defconfig index 13dabc3f51c..0eb25c33a79 100644 --- a/boards/nuvoton/npcx7m6fb_evb/npcx7m6fb_evb_defconfig +++ b/boards/nuvoton/npcx7m6fb_evb/npcx7m6fb_evb_defconfig @@ -26,9 +26,6 @@ CONFIG_UART_INTERRUPT_DRIVEN=y # GPIO Driver CONFIG_GPIO=y -# Pin Controller Driver -CONFIG_PINCTRL=y - # Console Driver CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y diff --git a/boards/nuvoton/npcx9m6f_evb/doc/index.rst b/boards/nuvoton/npcx9m6f_evb/doc/index.rst index e9ed19970c5..2e9ac2e368b 100644 --- a/boards/nuvoton/npcx9m6f_evb/doc/index.rst +++ b/boards/nuvoton/npcx9m6f_evb/doc/index.rst @@ -1,7 +1,4 @@ -.. _npcx9m6f_evb: - -Nuvoton NPCX9M6F_EVB -#################### +.. zephyr:board:: npcx9m6f_evb Overview ******** @@ -10,10 +7,6 @@ The NPCX9M6F_EVB kit is a development platform to evaluate the Nuvoton NPCX9 series microcontrollers. This board needs to be mated with part number NPCX996F. -.. image:: npcx9m6f_evb.jpg - :align: center - :alt: NPCX9M6F Evaluation Board - Hardware ******** diff --git a/boards/nuvoton/npcx9m6f_evb/npcx9m6f_evb_defconfig b/boards/nuvoton/npcx9m6f_evb/npcx9m6f_evb_defconfig index c076f906112..443d5beff37 100644 --- a/boards/nuvoton/npcx9m6f_evb/npcx9m6f_evb_defconfig +++ b/boards/nuvoton/npcx9m6f_evb/npcx9m6f_evb_defconfig @@ -26,9 +26,6 @@ CONFIG_UART_INTERRUPT_DRIVEN=y # GPIO Driver CONFIG_GPIO=y -# Pin Controller Driver -CONFIG_PINCTRL=y - # Console Driver CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y diff --git a/boards/nuvoton/numaker_m2l31ki/doc/index.rst b/boards/nuvoton/numaker_m2l31ki/doc/index.rst index 8c2e8b8bf77..98838ae7e1d 100644 --- a/boards/nuvoton/numaker_m2l31ki/doc/index.rst +++ b/boards/nuvoton/numaker_m2l31ki/doc/index.rst @@ -1,7 +1,4 @@ -.. _nuvoton_m2l31ki: - -NUVOTON NUMAKER M2L31KI -######################## +.. zephyr:board:: numaker_m2l31ki Overview ******** @@ -10,10 +7,6 @@ The NuMaker M2L31KI is an Internet of Things (IoT) application focused platform specially developed by Nuvoton. The NuMaker-M2L31KI is based on the NuMicro® M2L31 series MCU with ARM® -Cortex®-M23 core. -.. image:: ./m2l31ki.webp - :align: center - :alt: M2L31KI - Features: ========= - 32-bit Arm Cortex®-M23 M2L31KIDAE MCU @@ -89,6 +82,8 @@ Step through the application in your debugger. References ********** +.. target-notes:: + .. _NuMaker M2L31KI User Manual: https://www.nuvoton.com/products/microcontrollers/arm-cortex-m23-mcus/m2l31-series/ .. _M2L31 TRM: diff --git a/boards/nuvoton/numaker_m2l31ki/numaker_m2l31ki-pinctrl.dtsi b/boards/nuvoton/numaker_m2l31ki/numaker_m2l31ki-pinctrl.dtsi index 983bdb1ac6d..7a99fd28839 100644 --- a/boards/nuvoton/numaker_m2l31ki/numaker_m2l31ki-pinctrl.dtsi +++ b/boards/nuvoton/numaker_m2l31ki/numaker_m2l31ki-pinctrl.dtsi @@ -24,4 +24,14 @@ ; }; }; + + /* USBD multi-function pins for VBUS, D+, D-, and ID pins */ + usbd_default: usbd_default { + group0 { + pinmux = , + , + , + ; + }; + }; }; diff --git a/boards/nuvoton/numaker_m2l31ki/numaker_m2l31ki.dts b/boards/nuvoton/numaker_m2l31ki/numaker_m2l31ki.dts index b874a0eb78e..8017f2efd01 100644 --- a/boards/nuvoton/numaker_m2l31ki/numaker_m2l31ki.dts +++ b/boards/nuvoton/numaker_m2l31ki/numaker_m2l31ki.dts @@ -35,12 +35,6 @@ }; }; -&scc { - /* For USB 1.1 Host/Device/OTG, configure to 192MHz, which can generate necessary 48MHz. */ - /* For USB 2.0 Host/Device/OTG or no USB application, comment out to use default. */ - core-clock = ; -}; - &gpioc { status = "okay"; }; @@ -80,3 +74,10 @@ pinctrl-names = "default"; status = "okay"; }; + +/* On enabled, usbd is required to be clocked in 48MHz. */ +zephyr_udc0: &usbd { + pinctrl-0 = <&usbd_default>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/boards/nuvoton/numaker_m2l31ki/numaker_m2l31ki.yaml b/boards/nuvoton/numaker_m2l31ki/numaker_m2l31ki.yaml index 4276ce3573c..3ed0f87a06c 100644 --- a/boards/nuvoton/numaker_m2l31ki/numaker_m2l31ki.yaml +++ b/boards/nuvoton/numaker_m2l31ki/numaker_m2l31ki.yaml @@ -13,4 +13,5 @@ ram: 168 flash: 512 supported: - gpio + - usbd vendor: nuvoton diff --git a/boards/nuvoton/numaker_m2l31ki/numaker_m2l31ki_defconfig b/boards/nuvoton/numaker_m2l31ki/numaker_m2l31ki_defconfig index e59234cb73c..a1da5acdf56 100644 --- a/boards/nuvoton/numaker_m2l31ki/numaker_m2l31ki_defconfig +++ b/boards/nuvoton/numaker_m2l31ki/numaker_m2l31ki_defconfig @@ -1,6 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_PINCTRL=y CONFIG_GPIO=y # Enable system clock controller driver diff --git a/boards/nuvoton/numaker_pfm_m467/doc/index.rst b/boards/nuvoton/numaker_pfm_m467/doc/index.rst index 6620acce559..70d4cba1ec0 100644 --- a/boards/nuvoton/numaker_pfm_m467/doc/index.rst +++ b/boards/nuvoton/numaker_pfm_m467/doc/index.rst @@ -1,7 +1,4 @@ -.. _nuvoton_pfm_m467: - -NUVOTON NUMAKER PFM M467 -######################## +.. zephyr:board:: numaker_pfm_m467 Overview ******** @@ -10,11 +7,6 @@ The NuMaker PFM M467 is an Internet of Things (IoT) application focused platform specially developed by Nuvoton. The PFM-M467 is based on the NuMicro® M467 Ethernet series MCU with ARM® -Cortex®-M4F core. -.. image:: ./pfm_m467.jpeg - :width: 720px - :align: center - :alt: PFM-M467 - Features: ========= - 32-bit Arm Cortex®-M4 M467HJHAE MCU @@ -93,6 +85,8 @@ Step through the application in your debugger. References ********** +.. target-notes:: + .. _PFM M467 User Manual: https://www.nuvoton.com/export/resource-files/UM_NuMaker-PFM-M467_User_Manual_EN_Rev1.01.pdf .. _M460 TRM: diff --git a/boards/nuvoton/numaker_pfm_m467/numaker_pfm_m467_defconfig b/boards/nuvoton/numaker_pfm_m467/numaker_pfm_m467_defconfig index a5396d157c3..921d54e4934 100644 --- a/boards/nuvoton/numaker_pfm_m467/numaker_pfm_m467_defconfig +++ b/boards/nuvoton/numaker_pfm_m467/numaker_pfm_m467_defconfig @@ -1,6 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_PINCTRL=y CONFIG_GPIO=y # Enable system clock controller driver diff --git a/boards/nuvoton/numaker_pfm_m487/doc/index.rst b/boards/nuvoton/numaker_pfm_m487/doc/index.rst index 180ae3c5665..ce0e583bf30 100644 --- a/boards/nuvoton/numaker_pfm_m487/doc/index.rst +++ b/boards/nuvoton/numaker_pfm_m487/doc/index.rst @@ -1,7 +1,4 @@ -.. _nuvoton_pfm_m487: - -NUVOTON NUMAKER PFM M487 -######################## +.. zephyr:board:: numaker_pfm_m487 Overview ******** @@ -10,10 +7,6 @@ The NuMaker PFM M487 is an Internet of Things (IoT) application focused platform specially developed by Nuvoton. The PFM-M487 is based on the NuMicro® M487 Ethernet series MCU with ARM® -Cortex®-M4F core. -.. image:: pfm_m487.jpg - :align: center - :alt: PFM-M487 - Features: ========= - 32-bit Arm Cortex®-M4 M487JIDAE MCU @@ -92,6 +85,8 @@ Step through the application in your debugger. References ********** +.. target-notes:: + .. _PFM M487 User Manual: https://www.nuvoton.com/export/resource-files/UM_NuMaker-PFM-M487_User_Manual_EN_Rev1.01.pdf .. _M480 TRM: diff --git a/boards/nuvoton/numaker_pfm_m487/numaker_pfm_m487_defconfig b/boards/nuvoton/numaker_pfm_m487/numaker_pfm_m487_defconfig index bd250a1e060..0873db33cf3 100644 --- a/boards/nuvoton/numaker_pfm_m487/numaker_pfm_m487_defconfig +++ b/boards/nuvoton/numaker_pfm_m487/numaker_pfm_m487_defconfig @@ -4,9 +4,8 @@ CONFIG_ARM_MPU=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=192000000 -# Enable GPIO and pinctrl drivers +# Enable GPIO driver CONFIG_GPIO=y -CONFIG_PINCTRL=y # Enable UART driver CONFIG_SERIAL=y diff --git a/boards/nxp/common/segger-ecc-systemview.rst b/boards/nxp/common/segger-ecc-systemview.rst new file mode 100644 index 00000000000..f60648e655c --- /dev/null +++ b/boards/nxp/common/segger-ecc-systemview.rst @@ -0,0 +1,17 @@ +:orphan: + +.. segger-ecc-systemview + +Using Segger SystemView and RTT +------------------------------- + +Note that when using SEGGER SystemView or RTT with this SOC, the RTT control +block address must be set manually within SystemView or the RTT Viewer. The +address provided to the tool should be the location of the ``_SEGGER_RTT`` +symbol, which can be found using a debugger or by examining the ``zephyr.map`` +file output by the linker. + +The RTT control block address must be provided manually because this SOC +supports ECC RAM. If the SEGGER tooling searches the ECC RAM space for the +control block a fault will occur, provided that ECC is enabled and the RAM +segment being searched has not been initialized to a known value. diff --git a/boards/nxp/frdm_k22f/board.cmake b/boards/nxp/frdm_k22f/board.cmake index debe44fba36..06434c613bb 100644 --- a/boards/nxp/frdm_k22f/board.cmake +++ b/boards/nxp/frdm_k22f/board.cmake @@ -2,7 +2,9 @@ board_runner_args(jlink "--device=MK22FN512xxx12") board_runner_args(pyocd "--target=k22f") +board_runner_args(linkserver "--device=MK22FN512xxx12:FRDM-K22F") +include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake) include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/nxp/frdm_k22f/doc/index.rst b/boards/nxp/frdm_k22f/doc/index.rst index 2e5ea18aab8..ef2420ac0f4 100644 --- a/boards/nxp/frdm_k22f/doc/index.rst +++ b/boards/nxp/frdm_k22f/doc/index.rst @@ -1,7 +1,4 @@ -.. _frdm_k22f: - -NXP FRDM-K22F -############## +.. zephyr:board:: frdm_k22f Overview ******** @@ -19,10 +16,6 @@ MCUs. running an open source bootloader, offers options for serial communication, flash programming, and run-control debugging -.. image:: frdm_k22f.jpg - :align: center - :alt: FRDM-K22F - Hardware ******** @@ -59,7 +52,7 @@ Supported Features The frdm_k22f board configuration supports the hardware features listed below. For additional features not yet supported, please also refer to the -:ref:`frdm_k64f`, which is the superset board in NXP's Kinetis K series. +:zephyr:board:`frdm_k64f`, which is the superset board in NXP's Kinetis K series. NXP prioritizes enabling the superset board with NXP's Full Platform Support for Zephyr. Therefore, the frdm_k64f board may have additional features already supported, which can also be re-used on this frdm_k22f board: @@ -191,12 +184,26 @@ instructions to update from the CMSIS-DAP bootloader to the DAPLink bootloader. Option 1: :ref:`opensda-daplink-onboard-debug-probe` (Recommended) ------------------------------------------------------------------ -Install the :ref:`pyocd-debug-host-tools` and make sure they are in your search -path. - Follow the instructions in :ref:`opensda-daplink-onboard-debug-probe` to program the `OpenSDA DAPLink FRDM-K22F Firmware`_. +Install the :ref:`linkserver-debug-host-tools` and make sure they are in your +search path. LinkServer works with the default CMSIS-DAP firmware included in +the on-board debugger. + +Linkserver is the default for this board, ``west flash`` and ``west debug`` will +call the linkserver runner. + +.. code-block:: console + + west flash + +Alternatively, pyOCD can be used to flash and debug the board by using the +``-r pyocd`` option with West. pyOCD is installed when you complete the +:ref:`gs_python_deps` step in the Getting Started Guide. The runners supported +by NXP are LinkServer and JLink. pyOCD is another potential option, but NXP +does not test or support the pyOCD runner. + Option 2: :ref:`opensda-jlink-onboard-debug-probe` -------------------------------------------------- diff --git a/boards/nxp/frdm_k22f/frdm_k22f.dts b/boards/nxp/frdm_k22f/frdm_k22f.dts index fd36a8285fe..69439718a36 100644 --- a/boards/nxp/frdm_k22f/frdm_k22f.dts +++ b/boards/nxp/frdm_k22f/frdm_k22f.dts @@ -28,6 +28,7 @@ red-pwm-led = &red_pwm_led; magn0 = &fxos8700; accel0 = &fxos8700; + mcuboot-button0 = &user_button_3; }; chosen { @@ -152,7 +153,7 @@ arduino_spi: &spi0 { &ftm0 { status = "okay"; - compatible = "nxp,kinetis-ftm-pwm"; + compatible = "nxp,ftm-pwm"; #pwm-cells = <3>; pinctrl-0 = <&ftm0_default>; pinctrl-names = "default"; diff --git a/boards/nxp/frdm_k22f/frdm_k22f.yaml b/boards/nxp/frdm_k22f/frdm_k22f.yaml index caad4fe8519..5354f6fb724 100644 --- a/boards/nxp/frdm_k22f/frdm_k22f.yaml +++ b/boards/nxp/frdm_k22f/frdm_k22f.yaml @@ -12,6 +12,7 @@ supported: - arduino_i2c - arduino_spi - dac + - flash - gpio - i2c - nvs diff --git a/boards/nxp/frdm_k22f/frdm_k22f_defconfig b/boards/nxp/frdm_k22f/frdm_k22f_defconfig index 28e4f2b6ec3..e54e0b09d76 100644 --- a/boards/nxp/frdm_k22f/frdm_k22f_defconfig +++ b/boards/nxp/frdm_k22f/frdm_k22f_defconfig @@ -10,6 +10,5 @@ CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y CONFIG_GPIO=y -CONFIG_PINCTRL=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=72000000 CONFIG_OSC_LOW_POWER=y diff --git a/boards/nxp/frdm_k64f/doc/index.rst b/boards/nxp/frdm_k64f/doc/index.rst index 17af8d4cf29..192398674c7 100644 --- a/boards/nxp/frdm_k64f/doc/index.rst +++ b/boards/nxp/frdm_k64f/doc/index.rst @@ -1,7 +1,4 @@ -.. _frdm_k64f: - -NXP FRDM-K64F -############## +.. zephyr:board:: frdm_k64f Overview ******** @@ -19,10 +16,6 @@ K63, and K24 MCUs. running an open source bootloader, offers options for serial communication, flash programming, and run-control debugging -.. image:: frdm_k64f.jpg - :align: center - :alt: FRDM-K64F - Hardware ******** diff --git a/boards/nxp/frdm_k64f/frdm_k64f.dts b/boards/nxp/frdm_k64f/frdm_k64f.dts index 7fbc1943ec9..100dd6e69dc 100644 --- a/boards/nxp/frdm_k64f/frdm_k64f.dts +++ b/boards/nxp/frdm_k64f/frdm_k64f.dts @@ -18,6 +18,7 @@ sw1 = &user_button_2; magn0 = &fxos8700; accel0 = &fxos8700; + mcuboot-button0 = &user_button_2; }; chosen { @@ -162,6 +163,7 @@ arduino_spi: &spi0 { status = "okay"; sdmmc { compatible = "zephyr,sdmmc-disk"; + disk-name = "SD"; status = "okay"; }; spi-max-frequency = <24000000>; @@ -170,7 +172,7 @@ arduino_spi: &spi0 { &ftm0 { status = "okay"; - compatible = "nxp,kinetis-ftm-pwm"; + compatible = "nxp,ftm-pwm"; #pwm-cells = <3>; pinctrl-0 = <&ftm0_default>; pinctrl-names = "default"; @@ -179,7 +181,7 @@ arduino_spi: &spi0 { &ftm3 { status = "okay"; - compatible = "nxp,kinetis-ftm-pwm"; + compatible = "nxp,ftm-pwm"; #pwm-cells = <3>; pinctrl-0 = <&ftm3_default>; pinctrl-names = "default"; diff --git a/boards/nxp/frdm_k64f/frdm_k64f.yaml b/boards/nxp/frdm_k64f/frdm_k64f.yaml index ca78929f69e..578ac4edd0d 100644 --- a/boards/nxp/frdm_k64f/frdm_k64f.yaml +++ b/boards/nxp/frdm_k64f/frdm_k64f.yaml @@ -18,6 +18,7 @@ supported: - counter - dac - dma + - flash - gpio - i2c - netif:eth diff --git a/boards/nxp/frdm_k64f/frdm_k64f_defconfig b/boards/nxp/frdm_k64f/frdm_k64f_defconfig index 74d8a115b89..5196f9e1a39 100644 --- a/boards/nxp/frdm_k64f/frdm_k64f_defconfig +++ b/boards/nxp/frdm_k64f/frdm_k64f_defconfig @@ -4,7 +4,6 @@ CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y CONFIG_GPIO=y -CONFIG_PINCTRL=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=120000000 CONFIG_OSC_EXTERNAL=y diff --git a/boards/nxp/frdm_k82f/doc/index.rst b/boards/nxp/frdm_k82f/doc/index.rst index 9903e1b4493..4693e0dd244 100644 --- a/boards/nxp/frdm_k82f/doc/index.rst +++ b/boards/nxp/frdm_k82f/doc/index.rst @@ -1,7 +1,4 @@ -.. _frdm_k82f: - -NXP FRDM-K82F -############## +.. zephyr:board:: frdm_k82f Overview ******** @@ -19,10 +16,6 @@ and K82 MCUs. running an open source bootloader, offers options for serial communication, flash programming, and run-control debugging -.. image:: frdm_k82f.jpg - :align: center - :alt: FRDM-K82F - Hardware ******** @@ -60,7 +53,7 @@ Supported Features The frdm_k82f board configuration supports the hardware features listed below. For additional features not yet supported, please also refer to the -:ref:`frdm_k64f`, which is the superset board in NXP's Kinetis K series. +:zephyr:board:`frdm_k64f`, which is the superset board in NXP's Kinetis K series. NXP prioritizes enabling the superset board with NXP's Full Platform Support for Zephyr. Therefore, the frdm_k64f board may have additional features already supported, which can also be re-used on this frdm_k82f board: diff --git a/boards/nxp/frdm_k82f/frdm_k82f.dts b/boards/nxp/frdm_k82f/frdm_k82f.dts index d2f4ed51457..d28c32e5127 100644 --- a/boards/nxp/frdm_k82f/frdm_k82f.dts +++ b/boards/nxp/frdm_k82f/frdm_k82f.dts @@ -27,6 +27,7 @@ sw1 = &user_button_1; magn0 = &fxos8700; accel0 = &fxos8700; + mcuboot-button0 = &user_button_0; }; chosen { @@ -205,7 +206,7 @@ &ftm3 { status = "okay"; - compatible = "nxp,kinetis-ftm-pwm"; + compatible = "nxp,ftm-pwm"; #pwm-cells = <3>; pinctrl-0 = <&ftm3_default>; pinctrl-names = "default"; diff --git a/boards/nxp/frdm_k82f/frdm_k82f.yaml b/boards/nxp/frdm_k82f/frdm_k82f.yaml index 49480e2404b..2a4c29652cb 100644 --- a/boards/nxp/frdm_k82f/frdm_k82f.yaml +++ b/boards/nxp/frdm_k82f/frdm_k82f.yaml @@ -15,6 +15,7 @@ supported: - arduino_spi - counter - dma + - flash - gpio - i2c - nvs diff --git a/boards/nxp/frdm_k82f/frdm_k82f_defconfig b/boards/nxp/frdm_k82f/frdm_k82f_defconfig index 752e5539cbb..bc585171301 100644 --- a/boards/nxp/frdm_k82f/frdm_k82f_defconfig +++ b/boards/nxp/frdm_k82f/frdm_k82f_defconfig @@ -4,7 +4,6 @@ CONFIG_SERIAL=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_PINCTRL=y CONFIG_GPIO=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=120000000 CONFIG_OSC_LOW_POWER=y diff --git a/boards/nxp/frdm_ke15z/doc/index.rst b/boards/nxp/frdm_ke15z/doc/index.rst index 772de4f8678..c8d155be6fb 100644 --- a/boards/nxp/frdm_ke15z/doc/index.rst +++ b/boards/nxp/frdm_ke15z/doc/index.rst @@ -1,7 +1,4 @@ -.. _frdm_ke15z: - -NXP FRDM-KE15Z -############## +.. zephyr:board:: frdm_ke15z Overview ******** @@ -12,10 +9,6 @@ with up to 50 channels which makes this board highly flexible for touch keys. Offers options for serial communication, flash programming, and run-control debugging. -.. figure:: frdm_ke15z.webp - :align: center - :alt: FRDM-KE15Z - Hardware ******** diff --git a/boards/nxp/frdm_ke15z/frdm_ke15z.yaml b/boards/nxp/frdm_ke15z/frdm_ke15z.yaml index 9a2a7ac4b27..bb9212fc7b5 100644 --- a/boards/nxp/frdm_ke15z/frdm_ke15z.yaml +++ b/boards/nxp/frdm_ke15z/frdm_ke15z.yaml @@ -9,5 +9,6 @@ toolchain: flash: 256 ram: 24 supported: + - flash - gpio - uart diff --git a/boards/nxp/frdm_ke15z/frdm_ke15z_defconfig b/boards/nxp/frdm_ke15z/frdm_ke15z_defconfig index 69a85bdc43d..eb3936d7e4f 100644 --- a/boards/nxp/frdm_ke15z/frdm_ke15z_defconfig +++ b/boards/nxp/frdm_ke15z/frdm_ke15z_defconfig @@ -12,6 +12,3 @@ CONFIG_GPIO=y # Clock Control CONFIG_CLOCK_CONTROL=y - -# Enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/nxp/frdm_ke17z/doc/index.rst b/boards/nxp/frdm_ke17z/doc/index.rst index 1f15fc99fb9..3f9f7aa3049 100644 --- a/boards/nxp/frdm_ke17z/doc/index.rst +++ b/boards/nxp/frdm_ke17z/doc/index.rst @@ -1,7 +1,4 @@ -.. _frdm_ke17z: - -NXP FRDM-KE17Z -############## +.. zephyr:board:: frdm_ke17z Overview ******** @@ -12,12 +9,6 @@ with up to 50 channels which makes this board highly flexible for touch keys. Offers options for serial communication, flash programming, and run-control debugging. -.. figure:: frdmke17z.webp - :align: center - :alt: FRDM-KE17Z - - FRDM-KE17Z (Credit: NXP) - Hardware ******** diff --git a/boards/nxp/frdm_ke17z/frdm_ke17z.dts b/boards/nxp/frdm_ke17z/frdm_ke17z.dts index 46d5ba94c71..08590e6ee66 100644 --- a/boards/nxp/frdm_ke17z/frdm_ke17z.dts +++ b/boards/nxp/frdm_ke17z/frdm_ke17z.dts @@ -25,11 +25,14 @@ pwm-led0 = &red_pwm_led; pwm-led1 = &green_pwm_led; pwm-led2 = &blue_pwm_led; + mcuboot-button0 = &user_button_0; }; chosen { zephyr,sram = &sram_u; zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + zephyr,uart-mcumgr = &lpuart0; zephyr,console = &lpuart0; zephyr,shell-uart = &lpuart0; }; @@ -123,7 +126,7 @@ &ftm2 { status = "okay"; - compatible = "nxp,kinetis-ftm-pwm"; + compatible = "nxp,ftm-pwm"; #pwm-cells = <3>; clocks = <&scg KINETIS_SCG_SIRC_CLK>; prescaler = <128>; diff --git a/boards/nxp/frdm_ke17z/frdm_ke17z.yaml b/boards/nxp/frdm_ke17z/frdm_ke17z.yaml index f4069357439..17ccc33e871 100644 --- a/boards/nxp/frdm_ke17z/frdm_ke17z.yaml +++ b/boards/nxp/frdm_ke17z/frdm_ke17z.yaml @@ -9,13 +9,14 @@ toolchain: - gnuarmemb - xtools supported: + - adc - counter + - dma + - flash - gpio - - adc - - uart - - pwm - i2c + - pwm - spi - - dma + - uart - watchdog vendor: nxp diff --git a/boards/nxp/frdm_ke17z/frdm_ke17z_defconfig b/boards/nxp/frdm_ke17z/frdm_ke17z_defconfig index 906371815be..30c5915a7f1 100644 --- a/boards/nxp/frdm_ke17z/frdm_ke17z_defconfig +++ b/boards/nxp/frdm_ke17z/frdm_ke17z_defconfig @@ -14,6 +14,3 @@ CONFIG_GPIO=y # Clock Control CONFIG_CLOCK_CONTROL=y - -# Enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/nxp/frdm_ke17z512/doc/index.rst b/boards/nxp/frdm_ke17z512/doc/index.rst index ab4948307da..09ac1d95c67 100644 --- a/boards/nxp/frdm_ke17z512/doc/index.rst +++ b/boards/nxp/frdm_ke17z512/doc/index.rst @@ -1,7 +1,4 @@ -.. _frdm_ke17z512: - -NXP FRDM-KE17Z512 -################## +.. zephyr:board:: frdm_ke17z512 Overview ******** @@ -11,12 +8,6 @@ MCU-based platforms. The onboard OpenSDAv2 serial and debug adapter, running an open source bootloader, offers options for serial communication, flash programming, and run-control debugging. -.. figure:: frdm_ke17z512.webp - :align: center - :alt: FRDM-KE17Z512 - - FRDM-KE17Z512 (Credit: NXP) - Hardware ******** diff --git a/boards/nxp/frdm_ke17z512/frdm_ke17z512.dts b/boards/nxp/frdm_ke17z512/frdm_ke17z512.dts index 4fa5c16df02..c4c42776e29 100644 --- a/boards/nxp/frdm_ke17z512/frdm_ke17z512.dts +++ b/boards/nxp/frdm_ke17z512/frdm_ke17z512.dts @@ -18,6 +18,8 @@ chosen { zephyr,sram = &sram_u; zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + zephyr,uart-mcumgr = &lpuart2; zephyr,console = &lpuart2; zephyr,shell-uart = &lpuart2; }; @@ -32,6 +34,7 @@ pwm-led0 = &red_pwm_led; pwm-led1 = &green_pwm_led; pwm-led2 = &blue_pwm_led; + mcuboot-button0 = &user_button_2; }; leds { @@ -140,7 +143,7 @@ &ftm2 { status = "okay"; - compatible = "nxp,kinetis-ftm-pwm"; + compatible = "nxp,ftm-pwm"; #pwm-cells = <3>; clocks = <&scg KINETIS_SCG_SIRC_CLK>; prescaler = <128>; @@ -160,20 +163,20 @@ reg = <0x00000000 DT_SIZE_K(64)>; read-only; }; - /* The MCUBoot swap-move algorithm uses the last 2 sectors + /* The MCUBoot swap-move algorithm uses the last 3 sectors * of the primary slot0 for swap status and move. */ slot0_partition: partition@10000 { label = "image-0"; - reg = <0x00010000 (DT_SIZE_K(202) + DT_SIZE_K(4))>; + reg = <0x00010000 (DT_SIZE_K(202) + DT_SIZE_K(6))>; }; - slot1_partition: partition@43800 { + slot1_partition: partition@44000 { label = "image-1"; - reg = <0x00043800 DT_SIZE_K(202)>; + reg = <0x00044000 DT_SIZE_K(202)>; }; - storage_partition: partition@76000 { + storage_partition: partition@76800 { label = "storage"; - reg = <0x00076000 DT_SIZE_K(40)>; + reg = <0x00076800 DT_SIZE_K(38)>; }; }; }; diff --git a/boards/nxp/frdm_ke17z512/frdm_ke17z512.yaml b/boards/nxp/frdm_ke17z512/frdm_ke17z512.yaml index 6b817b1fb94..3b9dae0fa6b 100644 --- a/boards/nxp/frdm_ke17z512/frdm_ke17z512.yaml +++ b/boards/nxp/frdm_ke17z512/frdm_ke17z512.yaml @@ -18,6 +18,7 @@ supported: - counter - gpio - adc + - flash - uart - pwm - i2c diff --git a/boards/nxp/frdm_ke17z512/frdm_ke17z512_defconfig b/boards/nxp/frdm_ke17z512/frdm_ke17z512_defconfig index 508db6da853..3d640c35842 100644 --- a/boards/nxp/frdm_ke17z512/frdm_ke17z512_defconfig +++ b/boards/nxp/frdm_ke17z512/frdm_ke17z512_defconfig @@ -8,4 +8,3 @@ CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y CONFIG_GPIO=y -CONFIG_PINCTRL=y diff --git a/boards/nxp/frdm_kl25z/doc/index.rst b/boards/nxp/frdm_kl25z/doc/index.rst index 215c476df03..134f577ce1e 100644 --- a/boards/nxp/frdm_kl25z/doc/index.rst +++ b/boards/nxp/frdm_kl25z/doc/index.rst @@ -1,7 +1,4 @@ -.. _frdm_kl25z: - -NXP FRDM-KL25Z -############## +.. zephyr:board:: frdm_kl25z Overview ******** @@ -14,11 +11,6 @@ The FRDM-KL25Z features include easy access to MCU I/O, battery-ready, low-power operation, a standard-based form factor with expansion board options and a built-in debug interface for flash programming and run-control. - -.. image:: frdm_kl25z.jpg - :align: center - :alt: FRDM-KL25Z - Hardware ******** diff --git a/boards/nxp/frdm_kl25z/frdm_kl25z.yaml b/boards/nxp/frdm_kl25z/frdm_kl25z.yaml index d930aed2127..79c0082e156 100644 --- a/boards/nxp/frdm_kl25z/frdm_kl25z.yaml +++ b/boards/nxp/frdm_kl25z/frdm_kl25z.yaml @@ -16,6 +16,7 @@ supported: - adc - arduino_gpio - gpio + - flash - i2c - usb_device vendor: nxp diff --git a/boards/nxp/frdm_kl25z/frdm_kl25z_defconfig b/boards/nxp/frdm_kl25z/frdm_kl25z_defconfig index 0645bba8800..522e94ae746 100644 --- a/boards/nxp/frdm_kl25z/frdm_kl25z_defconfig +++ b/boards/nxp/frdm_kl25z/frdm_kl25z_defconfig @@ -4,6 +4,5 @@ CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y CONFIG_GPIO=y -CONFIG_PINCTRL=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=48000000 CONFIG_OSC_LOW_POWER=y diff --git a/boards/nxp/frdm_kw41z/doc/index.rst b/boards/nxp/frdm_kw41z/doc/index.rst index b1643939f8e..20b83687106 100644 --- a/boards/nxp/frdm_kw41z/doc/index.rst +++ b/boards/nxp/frdm_kw41z/doc/index.rst @@ -1,7 +1,4 @@ -.. _frdm_kw41z: - -NXP FRDM-KW41Z -############## +.. zephyr:board:: frdm_kw41z Overview ******** @@ -22,10 +19,6 @@ F-antenna which can be bypassed to test via SMA connection, multiple power supply options, push/capacitive touch buttons, switches, LEDs and integrated sensors. -.. image:: frdm_kw41z.jpg - :align: center - :alt: FRDM-KW41Z - Hardware ******** diff --git a/boards/nxp/frdm_kw41z/frdm_kw41z.yaml b/boards/nxp/frdm_kw41z/frdm_kw41z.yaml index 63cffff2786..9855726bc16 100644 --- a/boards/nxp/frdm_kw41z/frdm_kw41z.yaml +++ b/boards/nxp/frdm_kw41z/frdm_kw41z.yaml @@ -12,6 +12,7 @@ supported: - adc - arduino_gpio - counter + - flash - gpio - i2c - spi diff --git a/boards/nxp/frdm_kw41z/frdm_kw41z_defconfig b/boards/nxp/frdm_kw41z/frdm_kw41z_defconfig index ec5a311d8fe..90d5fe82223 100644 --- a/boards/nxp/frdm_kw41z/frdm_kw41z_defconfig +++ b/boards/nxp/frdm_kw41z/frdm_kw41z_defconfig @@ -4,6 +4,5 @@ CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y CONFIG_GPIO=y -CONFIG_PINCTRL=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=40000000 CONFIG_OSC_EXTERNAL=y diff --git a/boards/nxp/frdm_mcxa156/Kconfig.defconfig b/boards/nxp/frdm_mcxa156/Kconfig.defconfig new file mode 100644 index 00000000000..117b55f95e8 --- /dev/null +++ b/boards/nxp/frdm_mcxa156/Kconfig.defconfig @@ -0,0 +1,15 @@ +# FRDM-MCXA156 board + +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_FRDM_MCXA156 + +if BOOTLOADER_MCUBOOT +choice MCUBOOT_BOOTLOADER_MODE + # Board only supports MCUBoot via "upgrade only" method: + default MCUBOOT_BOOTLOADER_MODE_OVERWRITE_ONLY +endchoice +endif #BOOTLOADER_MCUBOOT + +endif # BOARD_FRDM_MCXA156 diff --git a/boards/nxp/frdm_mcxa156/Kconfig.sysbuild b/boards/nxp/frdm_mcxa156/Kconfig.sysbuild new file mode 100644 index 00000000000..4625c7d2929 --- /dev/null +++ b/boards/nxp/frdm_mcxa156/Kconfig.sysbuild @@ -0,0 +1,6 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +choice MCUBOOT_MODE + default MCUBOOT_MODE_OVERWRITE_ONLY +endchoice diff --git a/boards/nxp/frdm_mcxa156/board.c b/boards/nxp/frdm_mcxa156/board.c index 84347c4715c..f73cbb9c8c6 100644 --- a/boards/nxp/frdm_mcxa156/board.c +++ b/boards/nxp/frdm_mcxa156/board.c @@ -116,6 +116,116 @@ static int frdm_mcxa156_init(void) CLOCK_AttachClk(kFRO12M_to_LPUART0); #endif +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpuart1)) + CLOCK_SetClockDiv(kCLOCK_DivLPUART1, 1u); + CLOCK_AttachClk(kFRO12M_to_LPUART1); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(ctimer0)) + CLOCK_SetClockDiv(kCLOCK_DivCTIMER0, 1u); + CLOCK_AttachClk(kFRO_HF_to_CTIMER0); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(ctimer1)) + CLOCK_SetClockDiv(kCLOCK_DivCTIMER1, 1u); + CLOCK_AttachClk(kFRO_HF_to_CTIMER1); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(ctimer2)) + CLOCK_SetClockDiv(kCLOCK_DivCTIMER2, 1u); + CLOCK_AttachClk(kFRO_HF_to_CTIMER2); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(ctimer3)) + CLOCK_SetClockDiv(kCLOCK_DivCTIMER3, 1u); + CLOCK_AttachClk(kFRO_HF_to_CTIMER3); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(ctimer4)) + CLOCK_SetClockDiv(kCLOCK_DivCTIMER4, 1u); + CLOCK_AttachClk(kFRO_HF_to_CTIMER4); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(dac0)) + SPC_EnableActiveModeAnalogModules(SPC0, kSPC_controlDac0); + CLOCK_SetClockDiv(kCLOCK_DivDAC0, 1u); + CLOCK_AttachClk(kFRO12M_to_DAC0); + + CLOCK_EnableClock(kCLOCK_GateDAC0); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexcan0)) + CLOCK_SetClockDiv(kCLOCK_DivFLEXCAN0, 1U); + CLOCK_SetClockDiv(kCLOCK_DivFRO_HF_DIV, 1U); + CLOCK_AttachClk(kFRO_HF_DIV_to_FLEXCAN0); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexio0)) + CLOCK_SetClockDiv(kCLOCK_DivFLEXIO0, 1u); + CLOCK_AttachClk(kFRO_HF_to_FLEXIO0); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpadc0)) + CLOCK_SetClockDiv(kCLOCK_DivADC0, 1u); + CLOCK_AttachClk(kFRO12M_to_ADC0); + + CLOCK_EnableClock(kCLOCK_GateADC0); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpcmp0)) + CLOCK_AttachClk(kFRO12M_to_CMP0); + CLOCK_SetClockDiv(kCLOCK_DivCMP0_FUNC, 1U); + SPC_EnableActiveModeAnalogModules(SPC0, (kSPC_controlCmp0 | kSPC_controlCmp0Dac)); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpi2c0)) + CLOCK_SetClockDiv(kCLOCK_DivLPI2C0, 1u); + CLOCK_AttachClk(kFRO12M_to_LPI2C0); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpi2c1)) + CLOCK_SetClockDiv(kCLOCK_DivLPI2C1, 1u); + CLOCK_AttachClk(kFRO12M_to_LPI2C1); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpi2c2)) + CLOCK_SetClockDiv(kCLOCK_DivLPI2C2, 1u); + CLOCK_AttachClk(kFRO12M_to_LPI2C2); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpi2c3)) + CLOCK_SetClockDiv(kCLOCK_DivLPI2C3, 1u); + CLOCK_AttachClk(kFRO12M_to_LPI2C3); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lptmr0)) + +/* + * Clock Select Decides what input source the lptmr will clock from + * + * 0 <- Reserved + * 1 <- 16K FRO + * 2 <- Reserved + * 3 <- Combination of clocks configured in MRCC_LPTMR0_CLKSEL[MUX] field + */ +#if DT_PROP(DT_NODELABEL(lptmr0), clk_source) == 0x1 + CLOCK_SetupFRO16KClocking(kCLKE_16K_SYSTEM | kCLKE_16K_COREMAIN); +#elif DT_PROP(DT_NODELABEL(lptmr0), clk_source) == 0x3 + CLOCK_SetClockDiv(kCLOCK_DivLPTMR0, 1u); + CLOCK_AttachClk(kFRO12M_to_LPTMR0); +#endif /* DT_PROP(DT_NODELABEL(lptmr0), clk_source) */ + +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(usb)) + RESET_PeripheralReset(kUSB0_RST_SHIFT_RSTn); + CLOCK_EnableUsbfsClock(); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(wwdt0)) + CLOCK_SetClockDiv(kCLOCK_DivWWDT0, 1u); +#endif + /* Set SystemCoreClock variable. */ SystemCoreClock = CLOCK_INIT_CORE_CLOCK; diff --git a/boards/nxp/frdm_mcxa156/doc/index.rst b/boards/nxp/frdm_mcxa156/doc/index.rst index df622a40ddf..0bcc9d6e9ee 100644 --- a/boards/nxp/frdm_mcxa156/doc/index.rst +++ b/boards/nxp/frdm_mcxa156/doc/index.rst @@ -1,21 +1,14 @@ -.. _frdm_mcxa156: - -NXP FRDM-MCXA156 -################ +.. zephyr:board:: frdm_mcxa156 Overview ******** FRDM-MCXA156 are compact and scalable development boards for rapid prototyping of -MCX A15X MCUs. They offer industry standard headers for easy access to the -MCUs I/Os, integrated open-standard serial interfaces, external flash memory and -an on-board MCU-Link debugger. MCX N Series are high-performance, low-power -microcontrollers with intelligent peripherals and accelerators providing multi-tasking -capabilities and performance efficiency. - -.. image:: frdm_mcxa156.webp - :align: center - :alt: FRDM-MCXA156 +MCX A144/5/6 A154/5/6 MCUs. They offer industry standard headers for easy access +to the MCU's I/Os, integrated open-standard serial interfaces, external flash +memory and an on-board MCU-Link debugger. Additional tools like our Expansion +Board Hub for add-on boards and the Application Code Hub for software examples +are available through the MCUXpresso Developer Experience. Hardware ******** @@ -23,8 +16,8 @@ Hardware - MCX-A156 Arm Cortex-M33 microcontroller running at 96 MHz - 1MB dual-bank on chip Flash - 128 KB RAM -- USB high-speed (Host/Device) with on-chip HS PHY. HS USB Type-C connectors -- 2x FlexCAN with FD, 2x I3Cs, 2x SAI +- USB full-speed with on-chip FS PHY. USB Type-C connectors +- 1x FlexCAN with FD, 1x I3Cs - On-board MCU-Link debugger with CMSIS-DAP - Arduino Header, FlexIO/LCD Header, SmartDMA/Camera Header, mikroBUS @@ -61,6 +54,33 @@ The FRDM-MCXA156 board configuration supports the following hardware features: +-----------+------------+-------------------------------------+ | FLASH | on-chip | soc flash | +-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| CTIMER | on-chip | counter | ++-----------+------------+-------------------------------------+ +| DAC | on-chip | dac | ++-----------+------------+-------------------------------------+ +| DMA | on-chip | dma | ++-----------+------------+-------------------------------------+ +| FLEXCAN | on-chip | CAN | ++-----------+------------+-------------------------------------+ +| FLEXIO | on-chip | flexio | ++-----------+------------+-------------------------------------+ +| DISPLAY | on-chip | flexio; MIPI-DBI. Tested with | +| | | :ref:`lcd_par_s035` | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| LPCMP | on-chip | sensor(comparator) | ++-----------+------------+-------------------------------------+ +| LPTMR | on-chip | counter | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| USB | on-chip | USB device | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | watchdog | ++-----------+------------+-------------------------------------+ Targets available ================== @@ -182,6 +202,12 @@ should see the following message in the terminal: *** Booting Zephyr OS build v3.6.0-4478-ge6c3a42f5f52 *** Hello World! frdm_mcxa156/mcxa156 +Troubleshooting +=============== + +.. include:: ../../common/segger-ecc-systemview.rst + :start-after: segger-ecc-systemview + .. _MCX-A156 SoC Website: https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/mcx-arm-cortex-m/mcx-a-series-microcontrollers/mcx-a13x-14x-15x-mcus-with-arm-cortex-m33-scalable-device-options-low-power-and-intelligent-peripherals:MCX-A13X-A14X-A15X diff --git a/boards/nxp/frdm_mcxa156/frdm_mcxa156-pinctrl.dtsi b/boards/nxp/frdm_mcxa156/frdm_mcxa156-pinctrl.dtsi index a4e241c1bfe..7fa90600ee2 100644 --- a/boards/nxp/frdm_mcxa156/frdm_mcxa156-pinctrl.dtsi +++ b/boards/nxp/frdm_mcxa156/frdm_mcxa156-pinctrl.dtsi @@ -13,7 +13,129 @@ ; drive-strength = "low"; slew-rate = "fast"; + input-enable; + }; + }; + pinmux_lpuart1: pinmux_lpuart1 { + group0 { + pinmux = , + ; + drive-strength = "low"; + slew-rate = "fast"; + input-enable; + }; + }; + pinmux_dac0: pinmux_dac0 { + group0 { + pinmux = ; + drive-strength = "low"; + slew-rate = "fast"; + }; + }; + pinmux_flexcan0: pinmux_flexcan0 { + group0 { + pinmux = , + ; + slew-rate = "fast"; + drive-strength = "low"; + input-enable; + }; + }; + pinmux_flexio_lcd: pinmux_flexio_lcd { + group0 { + pinmux = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + slew-rate = "fast"; + drive-strength = "low"; + input-enable; + }; + group1 { + pinmux = ; + slew-rate = "fast"; + drive-strength = "low"; + input-enable; + bias-pull-up; + }; + group2 { + pinmux = ; + slew-rate = "slow"; + drive-strength = "low"; + input-enable; + bias-pull-up; + }; + }; + pinmux_flexpwm0_pwm0: pinmux_flexpwm0_pwm0 { + group0 { + pinmux = , + ; + slew-rate = "fast"; + drive-strength = "low"; + }; + }; + pinmux_lpadc0: pinmux_lpadc0 { + group0 { + pinmux = , + ; + slew-rate = "fast"; + drive-strength = "low"; + }; + }; + pinmux_lpcmp0: pinmux_lpcmp0 { + group0 { + pinmux = ; + drive-strength = "low"; + slew-rate = "fast"; + bias-pull-up; + }; + }; + pinmux_lpi2c0: pinmux_lpi2c0 { + group0 { + pinmux = , + ; + slew-rate = "fast"; + drive-strength = "low"; + input-enable; + bias-pull-up; + drive-open-drain; + }; + }; + pinmux_lpi2c2: pinmux_lpi2c2 { + group0 { + pinmux = , + ; + slew-rate = "fast"; + drive-strength = "low"; + input-enable; + bias-pull-up; + drive-open-drain; + }; + }; + pinmux_lpi2c3: pinmux_lpi2c3 { + group0 { + pinmux = , + ; + slew-rate = "fast"; + drive-strength = "low"; + input-enable; + bias-pull-up; + drive-open-drain; }; }; - }; diff --git a/boards/nxp/frdm_mcxa156/frdm_mcxa156.dts b/boards/nxp/frdm_mcxa156/frdm_mcxa156.dts index 73c872a0337..7aef98641a1 100644 --- a/boards/nxp/frdm_mcxa156/frdm_mcxa156.dts +++ b/boards/nxp/frdm_mcxa156/frdm_mcxa156.dts @@ -20,14 +20,20 @@ led2 = &red_led; sw0 = &user_button_2; sw1 = &user_button_3; + pwm-0 = &flexpwm0_pwm0; + mcuboot-button0 = &user_button_2; + watchdog0 = &wwdt0; }; chosen { zephyr,sram = &sram0; zephyr,flash = &flash; zephyr,flash-controller = &fmu; + zephyr,code-partition = &slot0_partition; zephyr,console = &lpuart0; zephyr,shell-uart = &lpuart0; + zephyr,uart-mcumgr = &lpuart0; + zephyr,canbus = &flexcan0; }; leds { @@ -60,6 +66,18 @@ }; }; + /* + * This node describes the GPIO pins of the LCD-PAR-S035 panel 8080 interface. + */ + nxp_lcd_8080_connector: lcd-8080-connector { + compatible = "nxp,lcd-8080"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <9 0 &gpio2 15 0>, /* Pin 9, LCD touch INT */ + <10 0 &gpio3 22 0>, /* Pin 10, LCD backlight control */ + <11 0 &gpio3 0 0>; /* Pin 11, LCD and touch reset */ + }; }; &gpio0 { @@ -88,3 +106,124 @@ pinctrl-0 = <&pinmux_lpuart0>; pinctrl-names = "default"; }; + +&lpuart1 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&pinmux_lpuart1>; + pinctrl-names = "default"; +}; + +&ctimer0 { + status = "okay"; +}; + +&dac0 { + status = "okay"; + pinctrl-0 = <&pinmux_dac0>; + pinctrl-names = "default"; +}; + +&edma0 { + status = "okay"; +}; + +&flexcan0 { + status = "okay"; + pinctrl-0 = <&pinmux_flexcan0>; + pinctrl-names = "default"; +}; + +&flexio0 { + status = "okay"; +}; + +nxp_8080_touch_panel_i2c: &lpi2c2 { + pinctrl-0 = <&pinmux_lpi2c2>; + pinctrl-names = "default"; +}; + +zephyr_mipi_dbi_parallel: &flexio0_lcd { + /* DMA channels 0, muxed to FlexIO TX */ + dmas = <&edma0 0 71>; + dma-names = "tx"; + shifters-count = <4>; + timers-count = <1>; + enwr-pin = <31>; + rd-pin = <28>; + data-pin-start = <0>; + reset-gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>; + rs-gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&pinmux_flexio_lcd>; + pinctrl-names = "default"; +}; + +&flexpwm0_pwm0 { + status = "okay"; + pinctrl-0 = <&pinmux_flexpwm0_pwm0>; + pinctrl-names = "default"; +}; + +&lpadc0 { + status = "okay"; + pinctrl-0 = <&pinmux_lpadc0>; + pinctrl-names = "default"; +}; + +&lpcmp0 { + status = "okay"; + pinctrl-0 = <&pinmux_lpcmp0>; + pinctrl-names = "default"; +}; + +&lpi2c0 { + status = "okay"; + pinctrl-0 = <&pinmux_lpi2c0>; + pinctrl-names = "default"; +}; + +&lpi2c3 { + status = "okay"; + pinctrl-0 = <&pinmux_lpi2c3>; + pinctrl-names = "default"; +}; + +&lptmr0 { + status = "okay"; +}; + +zephyr_udc0: &usb { + status = "okay"; + num-bidir-endpoints = <8>; +}; + +&wwdt0 { + status = "okay"; +}; + +&flash { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 DT_SIZE_K(64)>; + read-only; + }; + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 DT_SIZE_K(424)>; + }; + slot1_partition: partition@7a000 { + label = "image-1"; + reg = <0x0007a000 DT_SIZE_K(424)>; + }; + storage_partition: partition@e4000 { + label = "storage"; + reg = <0x000e4000 DT_SIZE_K(112)>; + }; + }; +}; diff --git a/boards/nxp/frdm_mcxa156/frdm_mcxa156.yaml b/boards/nxp/frdm_mcxa156/frdm_mcxa156.yaml index c7809e4548b..2a3960c25eb 100644 --- a/boards/nxp/frdm_mcxa156/frdm_mcxa156.yaml +++ b/boards/nxp/frdm_mcxa156/frdm_mcxa156.yaml @@ -15,5 +15,16 @@ toolchain: - gnuarmemb - xtools supported: + - adc + - flash - gpio + - can + - counter + - dac + - dma + - i2c + - pwm + - usb_device + - usbd + - watchdog vendor: nxp diff --git a/boards/nxp/frdm_mcxa156/frdm_mcxa156_defconfig b/boards/nxp/frdm_mcxa156/frdm_mcxa156_defconfig index 3fc86cf38dc..8a733179c9f 100644 --- a/boards/nxp/frdm_mcxa156/frdm_mcxa156_defconfig +++ b/boards/nxp/frdm_mcxa156/frdm_mcxa156_defconfig @@ -9,4 +9,3 @@ CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y CONFIG_UART_INTERRUPT_DRIVEN=y CONFIG_GPIO=y -CONFIG_PINCTRL=y diff --git a/boards/nxp/frdm_mcxc242/doc/index.rst b/boards/nxp/frdm_mcxc242/doc/index.rst index ecde1643da9..447cebd8dfa 100644 --- a/boards/nxp/frdm_mcxc242/doc/index.rst +++ b/boards/nxp/frdm_mcxc242/doc/index.rst @@ -1,7 +1,4 @@ -.. _frdm_mcxc242: - -NXP FRDM-MCXC242 -################ +.. zephyr:board:: frdm_mcxc242 Overview ******** @@ -13,11 +10,6 @@ interfaces and on-board MCU-Link debugger. The MCXC is a general purpose ultra-low-power MCU family, providing additional memory, communications and analog peripheral. - -.. image:: frdm_mcxc242.webp - :align: center - :alt: FRDM-MCXC242 - Hardware ******** @@ -66,6 +58,18 @@ The ``frdm_mcxc242`` board target supports the following hardware features: +-----------+------------+-------------------------------------+ | I2C | on-chip | i2c | +-----------+------------+-------------------------------------+ +| USB | on-chip | USB device | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| LPTMR | on-chip | counter | ++-----------+------------+-------------------------------------+ +| PIT | on-chip | counter | ++-----------+------------+-------------------------------------+ +| RTC | on-chip | counter | ++-----------+------------+-------------------------------------+ Targets available diff --git a/boards/nxp/frdm_mcxc242/frdm_mcxc242-pinctrl.dtsi b/boards/nxp/frdm_mcxc242/frdm_mcxc242-pinctrl.dtsi index 972cba958e7..2e8908e954e 100644 --- a/boards/nxp/frdm_mcxc242/frdm_mcxc242-pinctrl.dtsi +++ b/boards/nxp/frdm_mcxc242/frdm_mcxc242-pinctrl.dtsi @@ -16,6 +16,14 @@ slew-rate = "slow"; }; }; + pinmux_uart2: pinmux_uart2 { + group0 { + pinmux = , + ; + drive-strength = "low"; + slew-rate = "slow"; + }; + }; pinmux_i2c1: pinmux_i2c1 { group0 { pinmux = , @@ -25,4 +33,28 @@ slew-rate = "fast"; }; }; + pinmux_tpm1: pinmux_tpm1 { + group0 { + pinmux = , + ; + drive-strength = "low"; + slew-rate = "slow"; + }; + }; + pinmux_tpm2: pinmux_tpm2 { + group0 { + pinmux = , + ; + drive-strength = "low"; + slew-rate = "slow"; + }; + }; + pinmux_adc0: pinmux_adc0 { + group0 { + pinmux = , + ; + drive-strength = "low"; + slew-rate = "slow"; + }; + }; }; diff --git a/boards/nxp/frdm_mcxc242/frdm_mcxc242.dts b/boards/nxp/frdm_mcxc242/frdm_mcxc242.dts index 5961363441d..7c4a9da5004 100644 --- a/boards/nxp/frdm_mcxc242/frdm_mcxc242.dts +++ b/boards/nxp/frdm_mcxc242/frdm_mcxc242.dts @@ -17,10 +17,17 @@ aliases { led0 = &red_led; led1 = &green_led; - led2 = &red_led; + led2 = &blue_led; + pwm-led0 = &red_pwm_led; + pwm-led1 = &green_pwm_led; + pwm-led2 = &blue_pwm_led; + red-pwm-led = &red_pwm_led; + green-pwm-led = &green_pwm_led; + blue-pwm-led = &blue_pwm_led; sw0 = &user_button_2; sw1 = &user_button_3; accel0 = &fxls8974; + pwm-0 = &tpm1; }; chosen { @@ -46,6 +53,23 @@ }; }; + pwmleds { + compatible = "pwm-leds"; + status = "disabled"; + red_pwm_led: pwm_led_0 { + pwms = <&tpm2 0 PWM_MSEC(20) PWM_POLARITY_INVERTED>; + label = "PWM Red LED"; + }; + green_pwm_led: pwm_led_1 { + pwms = <&tpm2 1 PWM_MSEC(20) PWM_POLARITY_INVERTED>; + label = "PWM Green LED"; + }; + blue_pwm_led: pwm_led_2 { + pwms = <&tpm1 1 PWM_MSEC(20) PWM_POLARITY_INVERTED>; + label = "PWM Blue LED"; + }; + }; + gpio_keys { compatible = "gpio-keys"; user_button_2: button_2 { @@ -63,7 +87,7 @@ &sim { pllfll-select = ; - er32k-select = ; + er32k-select = ; }; &cpu0 { @@ -98,6 +122,13 @@ pinctrl-names = "default"; }; +&uart2 { + status = "disabled"; + current-speed = <115200>; + pinctrl-0 = <&pinmux_uart2>; + pinctrl-names = "default"; +}; + i2c1: &i2c1 { status = "okay"; pinctrl-0 = <&pinmux_i2c1>; @@ -111,3 +142,46 @@ i2c1: &i2c1 { int2-gpios = <&gpioc 3 GPIO_ACTIVE_LOW>; }; }; + +zephyr_udc0: &usb { + status = "okay"; + num-bidir-endpoints = <8>; +}; + +&tpm1 { + status = "okay"; + pinctrl-0 = <&pinmux_tpm1>; + pinctrl-names = "default"; +}; + +&tpm2 { + status = "okay"; + pinctrl-0 = <&pinmux_tpm2>; + pinctrl-names = "default"; +}; + +&adc0 { + status = "okay"; + pinctrl-0 = <&pinmux_adc0>; + pinctrl-names = "default"; +}; + +&lptmr0 { + status = "okay"; +}; + +&rtc { + status = "okay"; +}; + +&pit0 { + status = "okay"; +}; + +&pit0_channel0 { + status = "okay"; +}; + +&pit0_channel1 { + status = "okay"; +}; diff --git a/boards/nxp/frdm_mcxc242/frdm_mcxc242.yaml b/boards/nxp/frdm_mcxc242/frdm_mcxc242.yaml index 285b86dde68..778d8428495 100644 --- a/boards/nxp/frdm_mcxc242/frdm_mcxc242.yaml +++ b/boards/nxp/frdm_mcxc242/frdm_mcxc242.yaml @@ -15,8 +15,15 @@ toolchain: - gnuarmemb - xtools supported: + - adc + - counter + - flash - gpio - i2c + - pwm + - uart + - usb_device + - usbd testing: ignore_tags: - net diff --git a/boards/nxp/frdm_mcxc444/doc/index.rst b/boards/nxp/frdm_mcxc444/doc/index.rst index db72f8d6fad..601bc9877a7 100644 --- a/boards/nxp/frdm_mcxc444/doc/index.rst +++ b/boards/nxp/frdm_mcxc444/doc/index.rst @@ -1,7 +1,4 @@ -.. _frdm_mcxc444: - -NXP FRDM-MCXC444 -################ +.. zephyr:board:: frdm_mcxc444 Overview ******** @@ -13,11 +10,6 @@ interfaces and on-board MCU-Link debugger. The MCXC is a general purpose ultra-low-power MCU family, providing additional memory, communications and analog peripheral. - -.. image:: frdm_mcxc444.webp - :align: center - :alt: FRDM-MCXC444 - Hardware ******** @@ -63,6 +55,18 @@ The ``frdm_mcxc444`` board target supports the following hardware features: +-----------+------------+-------------------------------------+ | FLASH | on-chip | soc flash | +-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| LPTMR | on-chip | counter | ++-----------+------------+-------------------------------------+ +| PIT | on-chip | counter | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| RTC | on-chip | counter | ++-----------+------------+-------------------------------------+ +| USB | on-chip | USB device | ++-----------+------------+-------------------------------------+ Targets available diff --git a/boards/nxp/frdm_mcxc444/frdm_mcxc444-pinctrl.dtsi b/boards/nxp/frdm_mcxc444/frdm_mcxc444-pinctrl.dtsi index 7f0010c3cbe..36b40c40abc 100644 --- a/boards/nxp/frdm_mcxc444/frdm_mcxc444-pinctrl.dtsi +++ b/boards/nxp/frdm_mcxc444/frdm_mcxc444-pinctrl.dtsi @@ -8,6 +8,15 @@ #include &pinctrl { + pinmux_i2c0: pinmux_i2c0 { + group0 { + pinmux = , + ; + drive-strength = "low"; + drive-open-drain; + slew-rate = "fast"; + }; + }; pinmux_lpuart0: pinmux_lpuart0 { group0 { pinmux = , @@ -16,4 +25,21 @@ slew-rate = "slow"; }; }; + pinmux_uart2: pinmux_uart2 { + group0 { + pinmux = , + ; + drive-strength = "low"; + slew-rate = "slow"; + }; + }; + pinmux_tpm0: pinmux_tpm0 { + group0 { + pinmux = , + , + ; + drive-strength = "low"; + slew-rate = "slow"; + }; + }; }; diff --git a/boards/nxp/frdm_mcxc444/frdm_mcxc444.dts b/boards/nxp/frdm_mcxc444/frdm_mcxc444.dts index 7e771a60725..df6c55e5721 100644 --- a/boards/nxp/frdm_mcxc444/frdm_mcxc444.dts +++ b/boards/nxp/frdm_mcxc444/frdm_mcxc444.dts @@ -17,9 +17,17 @@ aliases { led0 = &red_led; led1 = &green_led; - led2 = &red_led; + led2 = &blue_led; + pwm-led0 = &red_pwm_led; + pwm-led1 = &green_pwm_led; + pwm-led2 = &blue_pwm_led; + red-pwm-led = &red_pwm_led; + green-pwm-led = &green_pwm_led; + blue-pwm-led = &blue_pwm_led; sw0 = &user_button_2; sw1 = &user_button_3; + accel0 = &fxls8974; + pwm-0 = &tpm0; }; chosen { @@ -36,7 +44,7 @@ label = "Red LED"; }; green_led: led_1 { - gpios = <&gpiob 5 GPIO_ACTIVE_LOW>; + gpios = <&gpiod 5 GPIO_ACTIVE_LOW>; label = "Green LED"; }; blue_led: led_2 { @@ -45,6 +53,23 @@ }; }; + pwmleds { + compatible = "pwm-leds"; + status = "disabled"; + red_pwm_led: pwm_led_0 { + pwms = <&tpm0 4 PWM_MSEC(20) PWM_POLARITY_INVERTED>; + label = "PWM Red LED"; + }; + green_pwm_led: pwm_led_1 { + pwms = <&tpm0 5 PWM_MSEC(20) PWM_POLARITY_INVERTED>; + label = "PWM Green LED"; + }; + blue_pwm_led: pwm_led_2 { + pwms = <&tpm0 2 PWM_MSEC(20) PWM_POLARITY_INVERTED>; + label = "PWM Blue LED"; + }; + }; + gpio_keys { compatible = "gpio-keys"; user_button_2: button_2 { @@ -62,7 +87,7 @@ &sim { pllfll-select = ; - er32k-select = ; + er32k-select = ; }; &cpu0 { @@ -86,13 +111,69 @@ status = "okay"; }; +&gpiod { + status = "okay"; +}; + &gpioe { status = "okay"; }; +i2c0: &i2c0 { + status = "okay"; + pinctrl-0 = <&pinmux_i2c0>; + pinctrl-names = "default"; + + fxls8974: fxls8974@18 { + status = "okay"; + compatible = "nxp,fxls8974"; + reg = <0x18>; + int1-gpios = <&gpiod 1 GPIO_ACTIVE_LOW>; + }; +}; + &lpuart0 { status = "okay"; current-speed = <115200>; pinctrl-0 = <&pinmux_lpuart0>; pinctrl-names = "default"; }; + +&lptmr0 { + status = "okay"; +}; + +&uart2 { + status = "disabled"; + current-speed = <115200>; + pinctrl-0 = <&pinmux_uart2>; + pinctrl-names = "default"; +}; + +&rtc { + status = "okay"; +}; + +&pit0 { + status = "okay"; +}; + +&pit0_channel0 { + status = "okay"; +}; + +&pit0_channel1 { + status = "okay"; +}; + +&tpm0 { + status = "okay"; + pinctrl-0 = <&pinmux_tpm0>; + pinctrl-names = "default"; + clocks = <&sim KINETIS_SIM_OSCERCLK 0x103C 24>; +}; + +zephyr_udc0: &usb { + status = "okay"; + num-bidir-endpoints = <8>; +}; diff --git a/boards/nxp/frdm_mcxc444/frdm_mcxc444.yaml b/boards/nxp/frdm_mcxc444/frdm_mcxc444.yaml index dc92b7dfeb2..a7aabf28a35 100644 --- a/boards/nxp/frdm_mcxc444/frdm_mcxc444.yaml +++ b/boards/nxp/frdm_mcxc444/frdm_mcxc444.yaml @@ -15,7 +15,14 @@ toolchain: - gnuarmemb - xtools supported: + - counter + - flash - gpio + - i2c + - uart + - pwm + - usb_device + - usbd testing: ignore_tags: - net diff --git a/boards/nxp/frdm_mcxn236/board.c b/boards/nxp/frdm_mcxn236/board.c index fbaf20ccd65..0f26f857242 100644 --- a/boards/nxp/frdm_mcxn236/board.c +++ b/boards/nxp/frdm_mcxn236/board.c @@ -8,6 +8,15 @@ #include #include #include +#if CONFIG_USB_DC_NXP_EHCI +#include "usb_phy.h" +#include "usb.h" + +/* USB PHY condfiguration */ +#define BOARD_USB_PHY_D_CAL 0x04U +#define BOARD_USB_PHY_TXCAL45DP 0x07U +#define BOARD_USB_PHY_TXCAL45DM 0x07U +#endif /* Board xtal frequency in Hz */ #define BOARD_XTAL0_CLK_HZ 24000000U @@ -88,6 +97,27 @@ static int frdm_mcxn236_init(void) /* Set AHBCLKDIV divider to value 1 */ CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U); + CLOCK_SetupExtClocking(BOARD_XTAL0_CLK_HZ); + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexcan1)) + /* Set up PLL1 for 80 MHz FlexCAN clock */ + const pll_setup_t pll1Setup = { + .pllctrl = SCG_SPLLCTRL_SOURCE(1U) | SCG_SPLLCTRL_SELI(27U) | + SCG_SPLLCTRL_SELP(13U), + .pllndiv = SCG_SPLLNDIV_NDIV(3U), + .pllpdiv = SCG_SPLLPDIV_PDIV(1U), + .pllmdiv = SCG_SPLLMDIV_MDIV(10U), + .pllRate = 80000000U + }; + + /* Configure PLL1 to the desired values */ + CLOCK_SetPLL1Freq(&pll1Setup); + /* PLL1 Monitor is disabled */ + CLOCK_SetPll1MonitorMode(kSCG_Pll1MonitorDisable); + /* Set PLL1 CLK0 divider to value 1 */ + CLOCK_SetClkDiv(kCLOCK_DivPLL1Clk0, 1U); +#endif + #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexcomm1)) CLOCK_SetClkDiv(kCLOCK_DivFlexcom1Clk, 1u); CLOCK_AttachClk(kFRO12M_to_FLEXCOMM1); @@ -170,6 +200,105 @@ static int frdm_mcxn236_init(void) CLOCK_AttachClk(kPLL0_to_CTIMER4); #endif +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexcan1)) + CLOCK_SetClkDiv(kCLOCK_DivFlexcan1Clk, 1U); + CLOCK_AttachClk(kPLL1_CLK0_to_FLEXCAN1); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(vref)) + CLOCK_EnableClock(kCLOCK_Vref); + SPC_EnableActiveModeAnalogModules(SPC0, kSPC_controlVref); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpadc0)) + CLOCK_SetClkDiv(kCLOCK_DivAdc0Clk, 1U); + CLOCK_AttachClk(kFRO_HF_to_ADC0); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(usb1)) && CONFIG_USB_DC_NXP_EHCI + usb_phy_config_struct_t usbPhyConfig = { + BOARD_USB_PHY_D_CAL, BOARD_USB_PHY_TXCAL45DP, BOARD_USB_PHY_TXCAL45DM, + }; + + SPC0->ACTIVE_VDELAY = 0x0500; + /* Change the power DCDC to 1.8v (By default, DCDC is 1.8V), CORELDO to 1.1v (By default, + * CORELDO is 1.0V) + */ + SPC0->ACTIVE_CFG &= ~SPC_ACTIVE_CFG_CORELDO_VDD_DS_MASK; + SPC0->ACTIVE_CFG |= SPC_ACTIVE_CFG_DCDC_VDD_LVL(0x3) | SPC_ACTIVE_CFG_CORELDO_VDD_LVL(0x3) | + SPC_ACTIVE_CFG_SYSLDO_VDD_DS_MASK | SPC_ACTIVE_CFG_DCDC_VDD_DS(0x2u); + /* Wait until it is done */ + while (SPC0->SC & SPC_SC_BUSY_MASK) { + }; + if ((SCG0->LDOCSR & SCG_LDOCSR_LDOEN_MASK) == 0u) { + SCG0->TRIM_LOCK = SCG_TRIM_LOCK_TRIM_LOCK_KEY(0x5a5a) | + SCG_TRIM_LOCK_TRIM_UNLOCK_MASK; + SCG0->LDOCSR |= SCG_LDOCSR_LDOEN_MASK; + /* wait LDO ready */ + while ((SCG0->LDOCSR & SCG_LDOCSR_VOUT_OK_MASK) == 0u) { + }; + } + SYSCON->AHBCLKCTRLSET[2] |= SYSCON_AHBCLKCTRL2_USB_HS_MASK | + SYSCON_AHBCLKCTRL2_USB_HS_PHY_MASK; + SCG0->SOSCCFG &= ~(SCG_SOSCCFG_RANGE_MASK | SCG_SOSCCFG_EREFS_MASK); + /* xtal = 20 ~ 30MHz */ + SCG0->SOSCCFG = BIT(SCG_SOSCCFG_RANGE_SHIFT) | BIT(SCG_SOSCCFG_EREFS_SHIFT); + SCG0->SOSCCSR |= SCG_SOSCCSR_SOSCEN_MASK; + while (1) { + if (SCG0->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK) { + break; + } + } + SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK | + SYSCON_CLOCK_CTRL_CLKIN_ENA_FM_USBH_LPT_MASK; + CLOCK_EnableClock(kCLOCK_UsbHs); + CLOCK_EnableClock(kCLOCK_UsbHsPhy); + CLOCK_EnableUsbhsPhyPllClock(kCLOCK_Usbphy480M, BOARD_XTAL0_CLK_HZ); + CLOCK_EnableUsbhsClock(); + USB_EhciPhyInit(kUSB_ControllerEhci0, BOARD_XTAL0_CLK_HZ, &usbPhyConfig); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpcmp0)) + CLOCK_SetClkDiv(kCLOCK_DivCmp0FClk, 1U); + CLOCK_AttachClk(kFRO12M_to_CMP0F); + SPC_EnableActiveModeAnalogModules(SPC0, (kSPC_controlCmp0 | kSPC_controlCmp0Dac)); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexio0)) + CLOCK_SetClkDiv(kCLOCK_DivFlexioClk, 1u); + CLOCK_AttachClk(kPLL0_to_FLEXIO); +#endif + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lptmr0)) + +/* + * Clock Select Decides what input source the lptmr will clock from + * + * 0 <- 12MHz FRO + * 1 <- 16K FRO + * 2 <- 32K OSC + * 3 <- Output from the OSC_SYS + */ +#if DT_PROP(DT_NODELABEL(lptmr0), clk_source) == 0x0 + CLOCK_SetupClockCtrl(kCLOCK_FRO12MHZ_ENA); +#elif DT_PROP(DT_NODELABEL(lptmr0), clk_source) == 0x1 + CLOCK_SetupClk16KClocking(kCLOCK_Clk16KToVsys); +#elif DT_PROP(DT_NODELABEL(lptmr0), clk_source) == 0x2 + CLOCK_SetupOsc32KClocking(kCLOCK_Osc32kToVsys); +#elif DT_PROP(DT_NODELABEL(lptmr0), clk_source) == 0x3 + /* Value here should not exceed 25MHZ when using lptmr */ + CLOCK_SetupExtClocking(MHZ(24)); + CLOCK_SetupClockCtrl(kCLOCK_CLKIN_ENA_FM_USBH_LPT); +#endif /* DT_PROP(DT_NODELABEL(lptmr0), clk_source) */ + +#endif /* DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lptmr0)) */ + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(i3c1)) + CLOCK_SetClkDiv(kCLOCK_DivI3c1FClk, DT_PROP(DT_NODELABEL(i3c1), clk_divider)); + /* Attach PLL0 clock to I3C, 150MHz / 6 = 25MHz. */ + CLOCK_AttachClk(kPLL0_to_I3C1FCLK); +#endif + /* Set SystemCoreClock variable. */ SystemCoreClock = CLOCK_INIT_CORE_CLOCK; diff --git a/boards/nxp/frdm_mcxn236/doc/index.rst b/boards/nxp/frdm_mcxn236/doc/index.rst index 3ee20c5c1e8..48052ad4e56 100644 --- a/boards/nxp/frdm_mcxn236/doc/index.rst +++ b/boards/nxp/frdm_mcxn236/doc/index.rst @@ -1,7 +1,4 @@ -.. _frdm_mcxn236: - -NXP FRDM-MCXN236 -################ +.. zephyr:board:: frdm_mcxn236 Overview ******** @@ -13,10 +10,6 @@ an on-board MCU-Link debugger. MCX N Series are high-performance, low-power microcontrollers with intelligent peripherals and accelerators providing multi-tasking capabilities and performance efficiency. -.. image:: frdm_mcxn236.webp - :align: center - :alt: FRDM-MCXN236 - Hardware ******** @@ -62,12 +55,35 @@ The FRDM-MCXN236 board configuration supports the following hardware features: +-----------+------------+-------------------------------------+ | I2C | on-chip | i2c | +-----------+------------+-------------------------------------+ +| I3C | on-chip | i3c | ++-----------+------------+-------------------------------------+ | CLOCK | on-chip | clock_control | +-----------+------------+-------------------------------------+ | FLASH | on-chip | soc flash | +-----------+------------+-------------------------------------+ | WATCHDOG | on-chip | watchdog | +-----------+------------+-------------------------------------+ +| VREF | on-chip | regulator | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| USBHS | on-chip | USB device | ++-----------+------------+-------------------------------------+ +| LPCMP | on-chip | sensor(comparator) | ++-----------+------------+-------------------------------------+ +| FLEXCAN | on-chip | CAN | ++-----------+------------+-------------------------------------+ +| FLEXIO | on-chip | flexio | ++-----------+------------+-------------------------------------+ +| DISPLAY | on-chip | flexio; MIPI-DBI. Tested with | +| | | :ref:`lcd_par_s035` | ++-----------+------------+-------------------------------------+ +| LPTMR | on-chip | counter | ++-----------+------------+-------------------------------------+ +| MRT | on-chip | counter | ++-----------+------------+-------------------------------------+ +| RTC | on-chip | rtc | ++-----------+------------+-------------------------------------+ Targets available ================== @@ -189,6 +205,12 @@ should see the following message in the terminal: *** Booting Zephyr OS build v3.6.0-4478-ge6c3a42f5f52 *** Hello World! frdm_mcxn236/mcxn236 +Troubleshooting +=============== + +.. include:: ../../common/segger-ecc-systemview.rst + :start-after: segger-ecc-systemview + .. _MCX-N236 SoC Website: https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/mcx-arm-cortex-m/mcx-n-series-microcontrollers/mcx-n23x-highly-integrated-mcus-with-on-chip-accelerators-intelligent-peripherals-and-advanced-security:MCX-N23X diff --git a/boards/nxp/frdm_mcxn236/frdm_mcxn236-pinctrl.dtsi b/boards/nxp/frdm_mcxn236/frdm_mcxn236-pinctrl.dtsi index 7e587aad528..19a06b8453f 100644 --- a/boards/nxp/frdm_mcxn236/frdm_mcxn236-pinctrl.dtsi +++ b/boards/nxp/frdm_mcxn236/frdm_mcxn236-pinctrl.dtsi @@ -90,4 +90,91 @@ }; }; + + pinmux_lpadc0: pinmux_lpadc0 { + group0 { + pinmux = , + , + ; + slew-rate = "fast"; + drive-strength = "low"; + }; + }; + + pinmux_lpcmp0: pinmux_lpcmp0 { + group0 { + pinmux = ; + drive-strength = "low"; + slew-rate = "fast"; + bias-pull-up; + }; + }; + + pinmux_flexcan1: pinmux_flexcan1 { + group0 { + pinmux = , + ; + slew-rate = "fast"; + drive-strength = "low"; + input-enable; + }; + }; + + pinmux_i3c1: pinmux_i3c1 { + group0 { + pinmux = , + ; + slew-rate = "fast"; + drive-strength = "low"; + input-enable; + bias-pull-up; + }; + group1 { + pinmux = ; + slew-rate = "fast"; + drive-strength = "low"; + input-enable; + }; + }; + + pinmux_flexio_lcd: pinmux_flexio_lcd { + group0 { + pinmux = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + slew-rate = "fast"; + drive-strength = "low"; + input-enable; + }; + group1 { + pinmux = ; + slew-rate = "fast"; + drive-strength = "low"; + input-enable; + bias-pull-up; + }; + group2 { + pinmux = ; + slew-rate = "slow"; + drive-strength = "low"; + input-enable; + bias-pull-up; + }; + }; }; diff --git a/boards/nxp/frdm_mcxn236/frdm_mcxn236.dts b/boards/nxp/frdm_mcxn236/frdm_mcxn236.dts index fe0e60ddbb7..01e64e97085 100644 --- a/boards/nxp/frdm_mcxn236/frdm_mcxn236.dts +++ b/boards/nxp/frdm_mcxn236/frdm_mcxn236.dts @@ -21,11 +21,13 @@ zephyr,uart-mcumgr = &flexcomm4_lpuart4; zephyr,console = &flexcomm4_lpuart4; zephyr,shell-uart = &flexcomm4_lpuart4; + zephyr,canbus = &flexcan1; }; aliases{ watchdog0 = &wwdt0; pwm-0 = &flexpwm1_pwm0; + rtc = &rtc; }; }; @@ -110,6 +112,46 @@ status = "okay"; }; +&flexcan1 { + status = "okay"; +}; + &ctimer0 { status = "okay"; }; + +&vref { + status = "okay"; +}; + +&lpadc0 { + status = "okay"; +}; + +zephyr_udc0: &usb1 { + status = "okay"; +}; + +&lpcmp0 { + status = "okay"; +}; + +&i3c1 { + status = "okay"; +}; + +&flexio0 { + status = "okay"; +}; + +&lptmr0 { + status = "okay"; +}; + +&mrt0_channel0 { + status = "okay"; +}; + +&rtc { + status = "okay"; +}; diff --git a/boards/nxp/frdm_mcxn236/frdm_mcxn236.dtsi b/boards/nxp/frdm_mcxn236/frdm_mcxn236.dtsi index b4631c79afa..26515a78797 100644 --- a/boards/nxp/frdm_mcxn236/frdm_mcxn236.dtsi +++ b/boards/nxp/frdm_mcxn236/frdm_mcxn236.dtsi @@ -46,6 +46,19 @@ zephyr,code = ; }; }; + + /* + * This node describes the GPIO pins of the LCD-PAR-S035 panel 8080 interface. + */ + nxp_lcd_8080_connector: lcd-8080-connector { + compatible = "nxp,lcd-8080"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <9 0 &gpio0 23 0>, /* Pin 9, LCD touch INT */ + <10 0 &gpio4 6 0>, /* Pin 10, LCD backlight control */ + <11 0 &gpio4 7 0>; /* Pin 11, LCD and touch reset */ + }; }; &flexcomm2_lpuart2 { @@ -60,6 +73,12 @@ clock-frequency = ; }; +nxp_8080_touch_panel_i2c: &flexcomm2_lpi2c2 { + pinctrl-0 = <&pinmux_flexcomm2_lpi2c>; + pinctrl-names = "default"; + clock-frequency = ; +}; + &flexcomm3_lpspi3 { pinctrl-0 = <&pinmux_flexcomm3_lpspi>; pinctrl-names = "default"; @@ -118,3 +137,42 @@ pinctrl-0 = <&pinmux_flexpwm1_pwm0>; pinctrl-names = "default"; }; + +&lpadc0 { + pinctrl-0 = <&pinmux_lpadc0>; + pinctrl-names = "default"; +}; + +&lpcmp0 { + pinctrl-0 = <&pinmux_lpcmp0>; + pinctrl-names = "default"; +}; + +&flexcan1 { + pinctrl-0 = <&pinmux_flexcan1>; + pinctrl-names = "default"; +}; + +zephyr_mipi_dbi_parallel: &flexio0_lcd { + /* DMA channels 0, muxed to FlexIO TX */ + dmas = <&edma0 0 61>; + dma-names = "tx"; + shifters-count = <8>; + timers-count = <1>; + enwr-pin = <28>; + rd-pin = <27>; + data-pin-start = <4>; + reset-gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio4 14 GPIO_ACTIVE_HIGH>; + rs-gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&pinmux_flexio_lcd>; + pinctrl-names = "default"; +}; + +&i3c1 { + pinctrl-0 = <&pinmux_i3c1>; + pinctrl-names = "default"; +}; + +p3t1755dp_ard_i3c_interface: &i3c1 {}; +p3t1755dp_ard_i2c_interface: &flexcomm5_lpi2c5 {}; diff --git a/boards/nxp/frdm_mcxn236/frdm_mcxn236.yaml b/boards/nxp/frdm_mcxn236/frdm_mcxn236.yaml index ea8cdb1e2e4..6e2ef3c817c 100644 --- a/boards/nxp/frdm_mcxn236/frdm_mcxn236.yaml +++ b/boards/nxp/frdm_mcxn236/frdm_mcxn236.yaml @@ -15,11 +15,17 @@ toolchain: - gnuarmemb - xtools supported: + - adc + - can + - counter - dma + - flash - gpio - - spi - i2c - - watchdog + - i3c - pwm - - counter + - regulator + - spi + - watchdog + - usb_device vendor: nxp diff --git a/boards/nxp/frdm_mcxn236/frdm_mcxn236_defconfig b/boards/nxp/frdm_mcxn236/frdm_mcxn236_defconfig index 41ce4376bdc..2e0bfcbd83e 100644 --- a/boards/nxp/frdm_mcxn236/frdm_mcxn236_defconfig +++ b/boards/nxp/frdm_mcxn236/frdm_mcxn236_defconfig @@ -9,7 +9,6 @@ CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y CONFIG_UART_INTERRUPT_DRIVEN=y CONFIG_GPIO=y -CONFIG_PINCTRL=y CONFIG_ARM_MPU=y CONFIG_HW_STACK_PROTECTION=y diff --git a/boards/nxp/frdm_mcxn947/board.c b/boards/nxp/frdm_mcxn947/board.c index db21a4ae194..7bf3f8999cc 100644 --- a/boards/nxp/frdm_mcxn947/board.c +++ b/boards/nxp/frdm_mcxn947/board.c @@ -16,6 +16,10 @@ #define BOARD_USB_PHY_D_CAL (0x04U) #define BOARD_USB_PHY_TXCAL45DP (0x07U) #define BOARD_USB_PHY_TXCAL45DM (0x07U) + +usb_phy_config_struct_t usbPhyConfig = { + BOARD_USB_PHY_D_CAL, BOARD_USB_PHY_TXCAL45DP, BOARD_USB_PHY_TXCAL45DM, +}; #endif /* Board xtal frequency in Hz */ @@ -161,6 +165,11 @@ static int frdm_mcxn947_init(void) CLOCK_AttachClk(kFRO12M_to_FLEXCOMM4); #endif +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexcomm7)) + CLOCK_SetClkDiv(kCLOCK_DivFlexcom7Clk, 1u); + CLOCK_AttachClk(kFRO12M_to_FLEXCOMM7); +#endif + #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(os_timer)) CLOCK_AttachClk(kCLK_1M_to_OSTIMER); #endif @@ -185,10 +194,6 @@ static int frdm_mcxn947_init(void) CLOCK_EnableClock(kCLOCK_Gpio4); #endif -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio5)) - CLOCK_EnableClock(kCLOCK_Gpio5); -#endif - #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(dac0)) SPC_EnableActiveModeAnalogModules(SPC0, kSPC_controlDac0); CLOCK_SetClkDiv(kCLOCK_DivDac0Clk, 1u); @@ -260,6 +265,19 @@ static int frdm_mcxn947_init(void) enable_cache64(); #endif +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(smartdma)) + CLOCK_EnableClock(kCLOCK_Smartdma); + RESET_PeripheralReset(kSMART_DMA_RST_SHIFT_RSTn); +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(video_sdma)) + /* Drive CLKOUT from main clock, divided by 25 to yield 6MHz clock + * The camera will use this clock signal to generate + * PCLK, HSYNC, and VSYNC + */ + CLOCK_AttachClk(kMAIN_CLK_to_CLKOUT); + CLOCK_SetClkDiv(kCLOCK_DivClkOut, 25U); +#endif +#endif + #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(vref)) CLOCK_EnableClock(kCLOCK_Vref); SPC_EnableActiveModeAnalogModules(SPC0, kSPC_controlVref); @@ -270,11 +288,7 @@ static int frdm_mcxn947_init(void) CLOCK_AttachClk(kFRO_HF_to_ADC0); #endif -#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(usb1)) && CONFIG_USB_DC_NXP_EHCI - usb_phy_config_struct_t usbPhyConfig = { - BOARD_USB_PHY_D_CAL, BOARD_USB_PHY_TXCAL45DP, BOARD_USB_PHY_TXCAL45DM, - }; - +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(usb1)) && (CONFIG_USB_DC_NXP_EHCI || CONFIG_UDC_NXP_EHCI) SPC0->ACTIVE_VDELAY = 0x0500; /* Change the power DCDC to 1.8v (By default, DCDC is 1.8V), CORELDO to 1.1v (By default, * CORELDO is 1.0V) @@ -309,8 +323,10 @@ static int frdm_mcxn947_init(void) CLOCK_EnableClock(kCLOCK_UsbHsPhy); CLOCK_EnableUsbhsPhyPllClock(kCLOCK_Usbphy480M, BOARD_XTAL0_CLK_HZ); CLOCK_EnableUsbhsClock(); +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(usb1)) && CONFIG_USB_DC_NXP_EHCI USB_EhciPhyInit(kUSB_ControllerEhci0, BOARD_XTAL0_CLK_HZ, &usbPhyConfig); #endif +#endif #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpcmp0)) CLOCK_SetClkDiv(kCLOCK_DivCmp0FClk, 1U); @@ -347,6 +363,26 @@ static int frdm_mcxn947_init(void) CLOCK_AttachClk(kPLL0_to_FLEXIO); #endif +#if DT_NODE_HAS_STATUS(DT_NODELABEL(i3c1), okay) + /* Enable 1MHz clock. */ + SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK; + + CLOCK_SetClkDiv(kCLOCK_DivI3c1FClk, DT_PROP(DT_NODELABEL(i3c1), clk_divider)); + CLOCK_SetClkDiv(kCLOCK_DivI3c1FClkS, DT_PROP(DT_NODELABEL(i3c1), clk_divider_slow)); + CLOCK_SetClkDiv(kCLOCK_DivI3c1FClkStc, DT_PROP(DT_NODELABEL(i3c1), clk_divider_tc)); + + /* Attach PLL0 clock to I3C, 150MHz / 6 = 25MHz. */ + CLOCK_AttachClk(kPLL0_to_I3C1FCLK); + CLOCK_AttachClk(kCLK_1M_to_I3C1FCLKS); + CLOCK_AttachClk(kI3C1FCLK_to_I3C1FCLKSTC); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(sc_timer), okay) + /* attach FRO HF to SCT */ + CLOCK_SetClkDiv(kCLOCK_DivSctClk, 1u); + CLOCK_AttachClk(kFRO_HF_to_SCT); +#endif + /* Set SystemCoreClock variable. */ SystemCoreClock = CLOCK_INIT_CORE_CLOCK; diff --git a/boards/nxp/frdm_mcxn947/doc/index.rst b/boards/nxp/frdm_mcxn947/doc/index.rst index 1559dcea969..e923d67b9ab 100644 --- a/boards/nxp/frdm_mcxn947/doc/index.rst +++ b/boards/nxp/frdm_mcxn947/doc/index.rst @@ -1,7 +1,4 @@ -.. _frdm_mcxn947: - -NXP FRDM-MCXN947 -################ +.. zephyr:board:: frdm_mcxn947 Overview ******** @@ -13,10 +10,6 @@ an on-board MCU-Link debugger. MCX N Series are high-performance, low-power microcontrollers with intelligent peripherals and accelerators providing multi-tasking capabilities and performance efficiency. -.. image:: frdm_mcxn947.webp - :align: center - :alt: FRDM-MCXN947 - Hardware ******** @@ -66,6 +59,8 @@ The FRDM-MCXN947 board configuration supports the following hardware features: +-----------+------------+-------------------------------------+ | I2C | on-chip | i2c | +-----------+------------+-------------------------------------+ +| I3C | on-chip | i3c | ++-----------+------------+-------------------------------------+ | CLOCK | on-chip | clock_control | +-----------+------------+-------------------------------------+ | FLASH | on-chip | soc flash | @@ -80,6 +75,8 @@ The FRDM-MCXN947 board configuration supports the following hardware features: +-----------+------------+-------------------------------------+ | PWM | on-chip | pwm | +-----------+------------+-------------------------------------+ +| SCTimer | on-chip | pwm | ++-----------+------------+-------------------------------------+ | CTIMER | on-chip | counter | +-----------+------------+-------------------------------------+ | USDHC | on-chip | sdhc | @@ -88,6 +85,8 @@ The FRDM-MCXN947 board configuration supports the following hardware features: +-----------+------------+-------------------------------------+ | ADC | on-chip | adc | +-----------+------------+-------------------------------------+ +| HWINFO | on-chip | Unique device serial number | ++-----------+------------+-------------------------------------+ | USBHS | on-chip | USB device | +-----------+------------+-------------------------------------+ | LPCMP | on-chip | sensor(comparator) | @@ -101,6 +100,8 @@ The FRDM-MCXN947 board configuration supports the following hardware features: | DISPLAY | on-chip | flexio; MIPI-DBI. Tested with | | | | :ref:`lcd_par_s035` | +-----------+------------+-------------------------------------+ +| MRT | on-chip | counter | ++-----------+------------+-------------------------------------+ Targets available ================== @@ -260,6 +261,12 @@ should see the following message in the terminal: *** Booting Zephyr OS build v3.6.0-479-g91faa20c6741 *** Hello World! frdm_mcxn947/mcxn947/cpu0 +Troubleshooting +=============== + +.. include:: ../../common/segger-ecc-systemview.rst + :start-after: segger-ecc-systemview + .. _MCX-N947 SoC Website: https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/mcx-arm-cortex-m/mcx-n-series-microcontrollers/mcx-n94x-54x-highly-integrated-multicore-mcus-with-on-chip-accelerators-intelligent-peripherals-and-advanced-security:MCX-N94X-N54X diff --git a/boards/nxp/frdm_mcxn947/frdm_mcxn947-pinctrl.dtsi b/boards/nxp/frdm_mcxn947/frdm_mcxn947-pinctrl.dtsi index 68a1fa17301..ce4995b6d1c 100644 --- a/boards/nxp/frdm_mcxn947/frdm_mcxn947-pinctrl.dtsi +++ b/boards/nxp/frdm_mcxn947/frdm_mcxn947-pinctrl.dtsi @@ -31,6 +31,18 @@ }; }; + pinmux_flexcomm7_lpi2c: pimux_flexcomm7_lpi2c { + group0 { + pinmux = , + ; + slew-rate = "fast"; + drive-strength = "low"; + input-enable; + bias-pull-up; + drive-open-drain; + }; + }; + pinmux_flexcomm2_lpuart: pinmux_flexcomm2_lpuart { group0 { pinmux = , @@ -129,6 +141,31 @@ }; }; + pinmux_smartdma_camera: pinmux_smartdma_camera { + group0 { + /* + * SmartDMA pinmux is not defined by SOC header, so + * we encode it manually + */ + pinmux = , + , + , + , + , + , + , + , + , + , + , + , + ; + drive-strength = "low"; + slew-rate = "fast"; + input-enable; + }; + }; + pinmux_usdhc0: pinmux_usdhc0 { group0 { pinmux = , @@ -178,6 +215,32 @@ }; }; + pinmux_i3c1: pinmux_i3c1 { + group0 { + pinmux = , + ; + slew-rate = "fast"; + drive-strength = "low"; + input-enable; + bias-pull-up; + }; + group1 { + pinmux = ; + slew-rate = "fast"; + drive-strength = "low"; + input-enable; + }; + }; + + pinmux_sctimer: pinmux_sctimer { + group0 { + pinmux = ; + slew-rate = "fast"; + drive-strength = "low"; + input-enable; + }; + }; + pinmux_flexio_lcd: pinmux_flexio_lcd { group0 { pinmux = , diff --git a/boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi b/boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi index 7e95ec16144..574f20aecaf 100644 --- a/boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi +++ b/boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi @@ -16,6 +16,7 @@ sw0 = &user_button_2; sw1 = &user_button_3; sdhc0 = &usdhc0; + mcuboot-button0 = &user_button_2; }; leds { @@ -90,6 +91,34 @@ nxp_8080_touch_panel_i2c: &flexcomm2_lpi2c2 { pinctrl-names = "default"; }; +&flexcomm7_lpi2c7 { + pinctrl-0 = <&pinmux_flexcomm7_lpi2c>; + pinctrl-names = "default"; + clock-frequency = ; + ov7670: ov7670@21 { + compatible = "ovti,ov7670"; + reset-gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>; + pwdn-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>; + reg = <0x21>; + }; +}; + +/* SmartDMA is used for video driver on this board */ +&smartdma { + status = "okay"; + program-mem = <0x4000000>; + video_sdma: video-sdma { + status = "okay"; + compatible = "nxp,video-smartdma"; + pinctrl-0 = <&pinmux_smartdma_camera>; + pinctrl-names = "default"; + sensor = <&ov7670>; + vsync-pin = <4>; + hsync-pin = <11>; + pclk-pin = <5>; + }; +}; + /* * MCXN947 board uses OS timer as the kernel timer * In case we need to switch to SYSTICK timer, then @@ -111,18 +140,18 @@ nxp_8080_touch_panel_i2c: &flexcomm2_lpi2c2 { boot_partition: partition@0 { label = "mcuboot"; - reg = <0x00000000 DT_SIZE_K(64)>; + reg = <0x00000000 DT_SIZE_K(80)>; }; /* For the MCUBoot "upgrade only" method, * the slot sizes must be equal. */ - slot0_partition: partition@10000 { + slot0_partition: partition@14000 { label = "image-0"; - reg = <0x00010000 DT_SIZE_K(992)>; + reg = <0x00014000 DT_SIZE_K(984)>; }; - slot1_partition: partition@108000 { + slot1_partition: partition@10A000 { label = "image-1"; - reg = <0x00108000 DT_SIZE_K(992)>; + reg = <0x0010A000 DT_SIZE_K(984)>; }; /* storage_partition is placed in WINBOND flash memory*/ }; @@ -209,7 +238,7 @@ nxp_8080_touch_panel_i2c: &flexcomm2_lpi2c2 { pinctrl-names = "default"; }; -nxp_flexio_lcd: &flexio0_lcd { +zephyr_mipi_dbi_parallel: &flexio0_lcd { /* DMA channels 0, muxed to FlexIO TX */ dmas = <&edma0 0 61>; dma-names = "tx"; @@ -230,7 +259,17 @@ nxp_flexio_lcd: &flexio0_lcd { pinctrl-names = "default"; }; +&i3c1 { + pinctrl-0 = <&pinmux_i3c1>; + pinctrl-names = "default"; +}; + &flexcan0 { pinctrl-0 = <&pinmux_flexcan0>; pinctrl-names = "default"; }; + +&sc_timer { + pinctrl-0 = <&pinmux_sctimer>; + pinctrl-names = "default"; +}; diff --git a/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.dtsi b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.dtsi index d571d35384f..789f4d8c18e 100644 --- a/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.dtsi +++ b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.dtsi @@ -32,6 +32,8 @@ aliases{ watchdog0 = &wwdt0; pwm-0 = &flexpwm1_pwm0; + pwm-1 = &sc_timer; + rtc = &rtc; }; }; @@ -113,6 +115,14 @@ status = "okay"; }; +&flexcomm7 { + status = "okay"; +}; + +&flexcomm7_lpi2c7 { + status = "okay"; +}; + &flexspi { status = "okay"; }; @@ -157,6 +167,7 @@ status = "okay"; sdmmc { compatible = "zephyr,sdmmc-disk"; + disk-name = "SD"; status = "okay"; }; }; @@ -171,6 +182,14 @@ zephyr_udc0: &usb1 { status = "okay"; + phy_handle = <&usbphy1>; +}; + +&usbphy1 { + status = "okay"; + tx-d-cal = <4>; + tx-cal-45-dp-ohms = <7>; + tx-cal-45-dm-ohms = <7>; }; &lpcmp0 { @@ -181,6 +200,22 @@ zephyr_udc0: &usb1 { status = "okay"; }; +&i3c1 { + status = "okay"; +}; + &flexio0 { status = "okay"; }; + +&mrt0_channel0 { + status = "okay"; +}; + +&rtc { + status = "okay"; +}; + +&sc_timer { + status = "okay"; +}; diff --git a/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.yaml b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.yaml index 76f937fb1e5..8578e55b931 100644 --- a/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.yaml +++ b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.yaml @@ -15,17 +15,19 @@ toolchain: - gnuarmemb - xtools supported: + - adc - can + - counter + - dac - dma + - flash - gpio - - spi - - dac - i2c - - watchdog + - i3c - pwm - - counter - - sdhc - regulator - - adc + - sdhc + - spi - usb_device + - watchdog vendor: nxp diff --git a/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0_defconfig b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0_defconfig index 41ce4376bdc..2e0bfcbd83e 100644 --- a/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0_defconfig +++ b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0_defconfig @@ -9,7 +9,6 @@ CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y CONFIG_UART_INTERRUPT_DRIVEN=y CONFIG_GPIO=y -CONFIG_PINCTRL=y CONFIG_ARM_MPU=y CONFIG_HW_STACK_PROTECTION=y diff --git a/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0_qspi.yaml b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0_qspi.yaml index 6cd7ad2e40c..15648a75da5 100644 --- a/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0_qspi.yaml +++ b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0_qspi.yaml @@ -15,17 +15,19 @@ toolchain: - gnuarmemb - xtools supported: + - adc - can + - counter + - dac - dma + - flash - gpio - - spi - - dac - i2c - - watchdog + - i3c - pwm - - counter - - sdhc - regulator - - adc + - sdhc + - spi - usb_device + - watchdog vendor: nxp diff --git a/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0_qspi_defconfig b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0_qspi_defconfig index 41ce4376bdc..2e0bfcbd83e 100644 --- a/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0_qspi_defconfig +++ b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0_qspi_defconfig @@ -9,7 +9,6 @@ CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y CONFIG_UART_INTERRUPT_DRIVEN=y CONFIG_GPIO=y -CONFIG_PINCTRL=y CONFIG_ARM_MPU=y CONFIG_HW_STACK_PROTECTION=y diff --git a/boards/nxp/frdm_mcxw71/board.cmake b/boards/nxp/frdm_mcxw71/board.cmake index 27c59c8d358..ba8d5b735de 100644 --- a/boards/nxp/frdm_mcxw71/board.cmake +++ b/boards/nxp/frdm_mcxw71/board.cmake @@ -1,6 +1,8 @@ # Copyright 2024 NXP # SPDX-License-Identifier: Apache-2.0 +board_runner_args(linkserver "--device=MCXW716CxxxA:FRDM-MCXW71") board_runner_args(jlink "--device=mcxw716" "--reset-after-load") +include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/nxp/frdm_mcxw71/doc/index.rst b/boards/nxp/frdm_mcxw71/doc/index.rst index 2ed258c39a4..d7d979fbe40 100644 --- a/boards/nxp/frdm_mcxw71/doc/index.rst +++ b/boards/nxp/frdm_mcxw71/doc/index.rst @@ -1,7 +1,4 @@ -.. _frdm_mcxw71: - -NXP FRDM-MCXW71 -################ +.. zephyr:board:: frdm_mcxw71 Overview ******** @@ -19,10 +16,6 @@ LE. The independent radio subsystem, with a dedicated core and memory, offloads the main CPU, preserving it for the primary application and allowing firmware updates to support future wireless standards. -.. image:: frdm_mcxw71.webp - :align: center - :alt: FRDM-MCXW71 - Hardware ******** @@ -55,6 +48,36 @@ The ``frdm_mcxw71`` board target in Zephyr currently supports the following feat | LPUART | on-chip | serial port-polling; | | | | serial port-interrupt | +-----------+------------+-------------------------------------+ +| LPI2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| LPSPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| FMU | on-chip | flash | ++-----------+------------+-------------------------------------+ +| TPM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| WDOG32 | on-chip | watchdog | ++-----------+------------+-------------------------------------+ +| LPTMR | on-chip | counter | ++-----------+------------+-------------------------------------+ +| BLE | on-chip | Bluetooth | ++-----------+------------+-------------------------------------+ +| FLEXCAN | on-chip | can | ++-----------+------------+-------------------------------------+ +| VREF | on-chip | regulator | ++-----------+------------+-------------------------------------+ +| LPADC | on-chip | adc | ++-----------+------------+-------------------------------------+ + +Fetch Binary Blobs +****************** + +To support Bluetooth, frdm_mcxw71 requires fetching binary blobs, which can be +achieved by running the following command: + +.. code-block:: console + + west blobs fetch hal_nxp Programming and Debugging ************************* @@ -68,6 +91,16 @@ Configuring a Debug Probe A debug probe is used for both flashing and debugging the board. This board is configured by default to use the MCU-Link CMSIS-DAP Onboard Debug Probe. +Using LinkServer +---------------- + +Linkserver is the default runner for this board, and supports the factory +default MCU-Link firmware. Follow the instructions in +:ref:`mcu-link-cmsis-onboard-debug-probe` to reprogram the default MCU-Link +firmware. This only needs to be done if the default onboard debug circuit +firmware was changed. To put the board in ``DFU mode`` to program the firmware, +short jumper J5. + Using J-Link ------------ @@ -131,9 +164,55 @@ should see the following message in the terminal: *** Booting Zephyr OS build v3.7.0-xxx-xxxx *** Hello World! frdm_mcxw71/mcxw716c +Bluetooth +========= + +BLE functionality requires to fetch binary blobs, so make sure to follow +the ``Fetch Binary Blobs`` section first. + +Two images must be written to the board: one for the host (CM33) and one for the NBU (CM3). +- To flash the application (CM33) refer to the ``Flashing`` section above. +- To flash the NBU, follow the instructions below: + + * Install ``blhost`` from NXP's website. This is the tool that will allow you to flash the NBU. + * Enter ISP mode. To boot the MCU in ISP mode, follow these steps: + - Disconnect the ``FRDM-MCXW71`` board from all power sources. + - Keep the ``SW3`` (ISP) button on the board pressed, while connecting the board to the host computer USB port. + - Release the ``SW3`` (ISP) button. The MCXW71 MCU boots in ISP mode. + - Reconnect any external power supply, if needed. + * Use the following command to flash NBU file: + +.. code-block:: console + + # On Windows + blhost.exe -p COMxx -- receive-sb-file mcxw71_nbu_ble.sb3 + + # On Linux + ./blhost -p /dev/ttyxx -- receive-sb-file mcxw71_nbu_ble.sb3 + +Please consider changing ``COMxx`` on Windows or ``ttyxx`` on Linux to the serial port used by your board. + +The NBU file can be found in : ``/modules/hal/nxp/zephyr/blobs/mcxw71/mcxw71_nbu_ble.sb3`` + +For more details: + +.. _MCXW71 In-System Programming Utility: + https://docs.nxp.com/bundle/AN14427/page/topics/introduction.html + +.. _blhost Website: + https://www.nxp.com/search?keyword=blhost&start=0 + +Troubleshooting +=============== + +.. include:: ../../common/segger-ecc-systemview.rst + :start-after: segger-ecc-systemview + References ********** +.. target-notes:: + .. _MCXW71 SoC Website: https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/mcx-arm-cortex-m/mcx-w-series-microcontrollers/mcx-w71x-secure-and-ultra-low-power-mcus-for-matter-thread-zigbee-and-bluetooth-le:MCX-W71X diff --git a/boards/nxp/frdm_mcxw71/frdm_mcxw71-pinctrl.dtsi b/boards/nxp/frdm_mcxw71/frdm_mcxw71-pinctrl.dtsi index d834ed38453..29e41f6926e 100644 --- a/boards/nxp/frdm_mcxw71/frdm_mcxw71-pinctrl.dtsi +++ b/boards/nxp/frdm_mcxw71/frdm_mcxw71-pinctrl.dtsi @@ -6,6 +6,14 @@ #include &pinctrl { + pinmux_lpuart0: pinmux_lpuart0 { + group0 { + pinmux = , ; + drive-strength = "low"; + slew-rate = "fast"; + }; + }; + pinmux_lpuart1: pinmux_lpuart1 { group0 { pinmux = , ; @@ -13,4 +21,51 @@ slew-rate = "fast"; }; }; + + pinmux_tpm0: pinmux_tpm0 { + group0 { + pinmux = , + , + ; + drive-strength = "low"; + slew-rate = "fast"; + }; + }; + + pinmux_lpi2c1: pinmux_lpi2c1 { + group0 { + pinmux = , + ; + drive-strength = "low"; + slew-rate = "fast"; + drive-open-drain; + }; + }; + + pinmux_lpspi1: pinmux_lpspi1 { + group0 { + pinmux = , + ; + slew-rate = "fast"; + drive-strength = "low"; + }; + }; + + pinmux_flexcan: pinmux_flexcan { + group0 { + pinmux = , ; + slew-rate = "slow"; + drive-strength = "low"; + }; + }; + + pinmux_lpadc0: pinmux_lpadc0 { + group0 { + pinmux = , + , + ; + drive-strength = "low"; + slew-rate = "fast"; + }; + }; }; diff --git a/boards/nxp/frdm_mcxw71/frdm_mcxw71.dts b/boards/nxp/frdm_mcxw71/frdm_mcxw71.dts index 6577fe5ccca..65e2e7a2f6a 100644 --- a/boards/nxp/frdm_mcxw71/frdm_mcxw71.dts +++ b/boards/nxp/frdm_mcxw71/frdm_mcxw71.dts @@ -12,29 +12,60 @@ model = "NXP FRDM-MCXW71 board"; aliases { - led0 = &green_led; + led0 = &blue_led; + blue-pwm-led = &blue_pwm_led; + green-pwm-led = &green_pwm_led; + red-pwm-led = &red_pwm_led; }; chosen { zephyr,flash = &flash; - zephyr,code-partition = &code_partition; + zephyr,flash-controller = &fmu; + zephyr,code-partition = &slot0_partition; zephyr,sram = &stcm0; zephyr,console = &lpuart1; zephyr,shell-uart = &lpuart1; + zephyr,uart-pipe = &lpuart0; + zephyr,canbus = &flexcan0; + zephyr,uart-mcumgr = &lpuart0; }; user_led { compatible = "gpio-leds"; - green_led: led { + blue_led: led { gpios = <&gpioc 1 GPIO_ACTIVE_LOW>; }; }; + + pwmleds { + compatible = "pwm-leds"; + blue_pwm_led: pwm_led_0 { + pwms = <&tpm0 1 PWM_MSEC(20) PWM_POLARITY_INVERTED>; + }; + green_pwm_led: pwm_led_1 { + pwms = <&tpm0 2 PWM_MSEC(20) PWM_POLARITY_INVERTED>; + }; + red_pwm_led: pwm_led_2 { + pwms = <&tpm0 0 PWM_MSEC(20) PWM_POLARITY_INVERTED>; + }; + }; +}; + +&vref { + status = "okay"; }; &gpioc { status = "okay"; }; +&lpuart0 { + current-speed = <115200>; + status = "okay"; + pinctrl-0 = <&pinmux_lpuart0>; + pinctrl-names = "default"; +}; + &lpuart1 { current-speed = <115200>; status = "okay"; @@ -42,21 +73,72 @@ pinctrl-names = "default"; }; +&lpi2c1 { + status = "okay"; + pinctrl-0 = <&pinmux_lpi2c1>; + pinctrl-names = "default"; +}; + +&lpspi1 { + status = "okay"; + pinctrl-0 = <&pinmux_lpspi1>; + pinctrl-names = "default"; +}; + &flash { partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; - - code_partition: partition@0 { - reg = <0x0 DT_SIZE_K(896)>; - label = "code"; - read-only; + /* The MCUBoot swap-move algorithm uses the last 2 sectors + * of the primary slot0 for swap status and move. + */ + boot_partition: partition@0 { + reg = <0x0 DT_SIZE_K(64)>; }; - - storage_partition: partition@e0000 { - reg = <0xe0000 DT_SIZE_K(128)>; - label = "storage"; + slot0_partition: partition@10000 { + reg = <0x10000 (DT_SIZE_K(416) + DT_SIZE_K(16))>; + }; + slot1_partition: partition@7C000 { + reg = <0x7C000 DT_SIZE_K(416)>; }; + storage_partition: partition@E4000 { + reg = <0xE4000 DT_SIZE_K(112)>; + }; + }; +}; + +&fmu { + status = "okay"; +}; + +&tpm0 { + status = "okay"; + pinctrl-0 = <&pinmux_tpm0>; + pinctrl-names = "default"; +}; + +&lptmr0 { + status = "okay"; +}; + +&flexcan0 { + status = "okay"; + pinctrl-0 = <&pinmux_flexcan>; + pinctrl-names = "default"; + + can-transceiver { + max-bitrate = <5000000>; }; }; + +&adc0 { + pinctrl-0 = <&pinmux_lpadc0>; + pinctrl-names = "default"; + status = "okay"; +}; + +&nbu { + status = "okay"; + wakeup-source; +}; diff --git a/boards/nxp/frdm_mcxw71/frdm_mcxw71.yaml b/boards/nxp/frdm_mcxw71/frdm_mcxw71.yaml index bdc3c13959b..54cbe67d972 100644 --- a/boards/nxp/frdm_mcxw71/frdm_mcxw71.yaml +++ b/boards/nxp/frdm_mcxw71/frdm_mcxw71.yaml @@ -9,7 +9,15 @@ toolchain: - gnuarmemb - xtools supported: + - adc + - can + - counter + - flash - gpio - - uart + - i2c - pinctrl - - flash + - pwm + - regulator + - spi + - uart + - watchdog diff --git a/boards/nxp/frdm_mcxw71/frdm_mcxw71_defconfig b/boards/nxp/frdm_mcxw71/frdm_mcxw71_defconfig index ef284e16e65..0f5f85050b2 100644 --- a/boards/nxp/frdm_mcxw71/frdm_mcxw71_defconfig +++ b/boards/nxp/frdm_mcxw71/frdm_mcxw71_defconfig @@ -6,7 +6,6 @@ CONFIG_ARM_MPU=y CONFIG_TRUSTED_EXECUTION_SECURE=y -CONFIG_PINCTRL=y CONFIG_SERIAL=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y diff --git a/boards/nxp/frdm_rw612/doc/frdm_rw612.webp b/boards/nxp/frdm_rw612/doc/frdm_rw612.webp new file mode 100644 index 00000000000..5a63358d199 Binary files /dev/null and b/boards/nxp/frdm_rw612/doc/frdm_rw612.webp differ diff --git a/boards/nxp/frdm_rw612/doc/index.rst b/boards/nxp/frdm_rw612/doc/index.rst index 0044b09cb9c..a1a9b7dc817 100644 --- a/boards/nxp/frdm_rw612/doc/index.rst +++ b/boards/nxp/frdm_rw612/doc/index.rst @@ -1,7 +1,4 @@ -.. _frdm_rw612: - -NXP FRDM_RW612 -############## +.. zephyr:board:: frdm_rw612 Overview ******** @@ -39,8 +36,6 @@ Supported Features +-----------+------------+-----------------------------------+ | USART | on-chip | serial | +-----------+------------+-----------------------------------+ -| BLE | on-chip | Bluetooth | -+-----------+------------+-----------------------------------+ | DMA | on-chip | dma | +-----------+------------+-----------------------------------+ | SPI | on-chip | spi | @@ -55,10 +50,25 @@ Supported Features +-----------+------------+-----------------------------------+ | CTIMER | on-chip | counter | +-----------+------------+-----------------------------------+ +| SCTIMER | on-chip | pwm | ++-----------+------------+-----------------------------------+ | MRT | on-chip | counter | +-----------+------------+-----------------------------------+ | OS_TIMER | on-chip | os timer | +-----------+------------+-----------------------------------+ +| PM | on-chip | power management; uses SoC Power | +| | | Modes 1 and 2 | ++-----------+------------+-----------------------------------+ +| BLE | on-chip | Bluetooth | ++-----------+------------+-----------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-----------------------------------+ +| DAC | on-chip | dac | ++-----------+------------+-----------------------------------+ +| ENET | on-chip | ethernet | ++-----------+------------+-----------------------------------+ +| Wi-Fi | on-chip | Wi-Fi | ++-----------+------------+-----------------------------------+ The default configuration can be found in the defconfig file: @@ -69,7 +79,7 @@ Other hardware features are not currently supported Fetch Binary Blobs ****************** -To support Bluetooth, frdm_rw612 requires fetching binary blobs, which can be +To support Bluetooth or Wi-Fi, frdm_rw612 requires fetching binary blobs, which can be achieved by running the following command: .. code-block:: console @@ -143,20 +153,19 @@ Bluetooth BLE functionality requires to fetch binary blobs, so make sure to follow the ``Fetch Binary Blobs`` section first. -Those binary blobs can be used in two different ways, depending if :kconfig:option:`CONFIG_NXP_MONOLITHIC_BT` -is enabled or not: - -- :kconfig:option:`CONFIG_NXP_MONOLITHIC_BT` is enabled (default): +frdm_rw612 platform supports the monolithic feature. The required binary blob +``/modules/hal/nxp/zephyr/blobs/rw61x_sb_ble_a2.bin`` will be linked +with the application image directly, forming one single monolithic image. -The required binary blob will be linked with the application image directly, forming -one single monolithic image. -The user has nothing else to do other than flashing the application to the board. +Wi-Fi +===== -- :kconfig:option:`CONFIG_NXP_MONOLITHIC_BT` is disabled: +Wi-Fi functionality requires to fetch binary blobs, so make sure to follow +the ``Fetch Binary Blobs`` section first. -In this case, the BLE blob won't be linked with the application, so the user needs to manually -flash the BLE binary blob to the board at the address ``0x18540000``. -The binary blob will be located here: ``/modules/hal/nxp/zephyr/blobs/rw61x/rw61x_sb_ble_a2.bin`` +frdm_rw612 platform supports the monolithic feature. The required binary blob +``/modules/hal/nxp/zephyr/blobs/rw61x_sb_wifi_a2.bin`` will be linked +with the application image directly, forming one single monolithic image. Resources ========= diff --git a/boards/nxp/frdm_rw612/frdm_rw612-pinctrl.dtsi b/boards/nxp/frdm_rw612/frdm_rw612-pinctrl.dtsi index 80a6caa12ed..12ecaa90f40 100644 --- a/boards/nxp/frdm_rw612/frdm_rw612-pinctrl.dtsi +++ b/boards/nxp/frdm_rw612/frdm_rw612-pinctrl.dtsi @@ -53,4 +53,11 @@ slew-rate = "ultra"; }; }; + + pinmux_pwm0: pinmux_pwm0 { + group0 { + pinmux = ; + slew-rate = "normal"; + }; + }; }; diff --git a/boards/nxp/frdm_rw612/frdm_rw612.dts b/boards/nxp/frdm_rw612/frdm_rw612.dts index 03c8adc3287..39a58571779 100644 --- a/boards/nxp/frdm_rw612/frdm_rw612.dts +++ b/boards/nxp/frdm_rw612/frdm_rw612.dts @@ -7,160 +7,4 @@ /dts-v1/; #include -#include "frdm_rw612-pinctrl.dtsi" - -/ { - model = "nxp,frdm_rw612"; - - aliases { - led0 = &green_led; - watchdog0 = &wwdt; - usart-0 = &flexcomm3; - i2c-0 = &flexcomm2; - }; - - chosen { - zephyr,sram = &sram_data; - zephyr,flash = &w25q512jvfiq; - zephyr,console = &flexcomm3; - zephyr,shell-uart = &flexcomm3; - }; - - leds { - compatible = "gpio-leds"; - green_led: led_1 { - gpios = <&hsgpio0 12 0>; - }; - }; -}; - -&flexcomm3 { - compatible = "nxp,lpc-usart"; - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&pinmux_flexcomm3_usart>; - pinctrl-names = "default"; -}; - -&flexcomm0 { - compatible = "nxp,lpc-usart"; - status = "disabled"; - current-speed = <115200>; - pinctrl-0 = <&pinmux_flexcomm0_usart>; - pinctrl-names = "default"; -}; - -&hsgpio0 { - status = "okay"; -}; - -&flexspi { - status = "okay"; - /* Winbond external flash */ - w25q512jvfiq: w25q512jvfiq@0 { - compatible = "nxp,imx-flexspi-nor"; - reg = <0>; - size = ; - status = "okay"; - erase-block-size = <4096>; - write-block-size = <1>; - spi-max-frequency = <133000000>; - }; -}; - -&hci { - status = "okay"; - wakeup-source; -}; - -&enet_mac { - status = "okay"; - pinctrl-0 = <&pinmux_enet>; - pinctrl-names = "default"; - phy-handle = <&phy>; - zephyr,random-mac-address; - phy-connection-type = "rmii"; -}; - -&enet_mdio { - status = "okay"; - pinctrl-0 = <&pinmux_mdio>; - pinctrl-names = "default"; - phy: phy@2 { - compatible = "microchip,ksz8081"; - reg = <2>; - status = "okay"; - reset-gpios = <&hsgpio1 23 GPIO_ACTIVE_HIGH>; - int-gpios = <&hsgpio0 21 GPIO_ACTIVE_HIGH>; - microchip,interface-type = "rmii"; - }; -}; - -&wwdt { - status = "okay"; -}; - -&dma0 { - status = "okay"; -}; - -&mrt0_channel0 { - status = "okay"; -}; - -&ctimer0 { - status = "okay"; -}; - -&pmu { - reset-causes-en = , - , - ; -}; - -/* OS Timer is the wakeup source for PM mode 2 */ -&os_timer { - status = "okay"; - wakeup-source; -}; - -&systick { - status = "disabled"; -}; - -&adc0 { - status = "okay"; -}; - -&dac0 { - status = "okay"; -}; - -zephyr_udc0: &usb_otg { - status = "okay"; -}; - -/* - * the default resistors on the board breaks out the MOSI/MISO - * pins to the nets labelled "UART" which go to J1 2 and 4, - * but we are using it for spi mosi and miso here. - * SCK is on J2 6 as labelled. - */ -&flexcomm1 { - compatible = "nxp,lpc-spi"; - pinctrl-0 = <&pinmux_flexcomm1_spi>; - pinctrl-names = "default"; - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; -}; - -arduino_i2c: &flexcomm2 { - compatible = "nxp,lpc-i2c"; - status = "okay"; - clock-frequency = ; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pinmux_flexcomm2_i2c>; - pinctrl-names = "default"; -}; +#include "frdm_rw612_common.dtsi" diff --git a/boards/nxp/frdm_rw612/frdm_rw612.yaml b/boards/nxp/frdm_rw612/frdm_rw612.yaml index 813330e2b56..0ad00472dc2 100644 --- a/boards/nxp/frdm_rw612/frdm_rw612.yaml +++ b/boards/nxp/frdm_rw612/frdm_rw612.yaml @@ -23,6 +23,8 @@ supported: - usb_device - watchdog - counter + - pwm - hwinfo - adc - dac + - netif:eth diff --git a/boards/nxp/frdm_rw612/frdm_rw612_common.dtsi b/boards/nxp/frdm_rw612/frdm_rw612_common.dtsi new file mode 100644 index 00000000000..2f496ca7796 --- /dev/null +++ b/boards/nxp/frdm_rw612/frdm_rw612_common.dtsi @@ -0,0 +1,227 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "frdm_rw612-pinctrl.dtsi" + +/ { + model = "nxp,frdm_rw612"; + + aliases { + led0 = &green_led; + watchdog0 = &wwdt; + usart-0 = &flexcomm3; + i2c-0 = &flexcomm2; + pwm-0 = &sctimer; + }; + + chosen { + zephyr,sram = &sram_data; + zephyr,flash = &w25q512jvfiq; + zephyr,console = &flexcomm3; + zephyr,shell-uart = &flexcomm3; + }; + + leds { + compatible = "gpio-leds"; + green_led: led_1 { + gpios = <&hsgpio0 12 0>; + }; + }; +}; + +&flexcomm3 { + compatible = "nxp,lpc-usart"; + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&pinmux_flexcomm3_usart>; + pinctrl-names = "default"; +}; + +&flexcomm0 { + compatible = "nxp,lpc-usart"; + status = "disabled"; + current-speed = <115200>; + pinctrl-0 = <&pinmux_flexcomm0_usart>; + pinctrl-names = "default"; +}; + +&hsgpio0 { + status = "okay"; +}; + +&flexspi { + status = "okay"; + ahb-bufferable; + ahb-prefetch; + ahb-cacheable; + ahb-read-addr-opt; + ahb-boundary = "1024"; + rx-clock-source = <1>; + rx-clock-source-b = <1>; + /* Winbond external flash */ + w25q512jvfiq: w25q512jvfiq@0 { + compatible = "nxp,imx-flexspi-nor"; + reg = <0>; + size = ; + status = "okay"; + erase-block-size = <4096>; + write-block-size = <1>; + spi-max-frequency = <104000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 DT_SIZE_K(128)>; + }; + /* The MCUBoot swap-move algorithm uses the last 2 sectors + * of the primary slot0 for swap status and move. + */ + slot0_partition: partition@20000 { + label = "image-0"; + reg = <0x00020000 (DT_SIZE_M(3) + DT_SIZE_K(2 * 4))>; + }; + slot1_partition: partition@323000 { + label = "image-1"; + reg = <0x00323000 DT_SIZE_M(3)>; + }; + storage_partition: partition@623000 { + label = "storage"; + reg = <0x00623000 (DT_SIZE_M(58) - DT_SIZE_K(136))>; + }; + }; + }; + aps6404l: aps6404l@2 { + compatible = "nxp,imx-flexspi-aps6404l"; + /* APS6404L is 8MB, 64MBit pSRAM */ + size = ; + reg = <2>; + spi-max-frequency = <109000000>; + /* PSRAM cannot be enabled while board is in default XIP + * configuration, as it will conflict with flash chip. + */ + status = "disabled"; + cs-interval-unit = <1>; + cs-interval = <2>; + cs-hold-time = <3>; + cs-setup-time = <3>; + data-valid-time = <6>; + column-space = <0>; + ahb-write-wait-unit = <2>; + ahb-write-wait-interval = <0>; + }; +}; + +&hci { + status = "okay"; + wakeup-source; +}; + +&enet_mac { + status = "okay"; + pinctrl-0 = <&pinmux_enet>; + pinctrl-names = "default"; + phy-handle = <&phy>; + zephyr,random-mac-address; + phy-connection-type = "rmii"; +}; + +&enet_mdio { + status = "okay"; + pinctrl-0 = <&pinmux_mdio>; + pinctrl-names = "default"; + phy: phy@2 { + compatible = "microchip,ksz8081"; + reg = <2>; + status = "okay"; + reset-gpios = <&hsgpio1 23 GPIO_ACTIVE_HIGH>; + int-gpios = <&hsgpio0 21 GPIO_ACTIVE_HIGH>; + microchip,interface-type = "rmii"; + }; +}; + +&wwdt { + status = "okay"; +}; + +&dma0 { + status = "okay"; +}; + +&mrt0_channel0 { + status = "okay"; +}; + +&ctimer0 { + status = "okay"; +}; + +&pmu { + reset-causes-en = , + , + ; +}; + +/* OS Timer is the wakeup source for PM mode 2 */ +&os_timer { + status = "okay"; + wakeup-source; +}; + +&systick { + status = "disabled"; +}; + +&adc0 { + status = "okay"; +}; + +&dac0 { + status = "okay"; +}; + +&sctimer { + status = "okay"; + pinctrl-0 = <&pinmux_pwm0>; + pinctrl-names = "default"; +}; + +&nbu { + status = "okay"; + wakeup-source; +}; + +zephyr_udc0: &usb_otg { + status = "okay"; +}; + +/* + * the default resistors on the board breaks out the MOSI/MISO + * pins to the nets labelled "UART" which go to J1 2 and 4, + * but we are using it for spi mosi and miso here. + * SCK is on J2 6 as labelled. + */ +&flexcomm1 { + compatible = "nxp,lpc-spi"; + pinctrl-0 = <&pinmux_flexcomm1_spi>; + pinctrl-names = "default"; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; +}; + +arduino_i2c: &flexcomm2 { + compatible = "nxp,lpc-i2c"; + status = "okay"; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pinmux_flexcomm2_i2c>; + pinctrl-names = "default"; +}; diff --git a/boards/nxp/frdm_rw612/frdm_rw612_defconfig b/boards/nxp/frdm_rw612/frdm_rw612_defconfig index b987fa24dc0..8c5e9ace7be 100644 --- a/boards/nxp/frdm_rw612/frdm_rw612_defconfig +++ b/boards/nxp/frdm_rw612/frdm_rw612_defconfig @@ -7,7 +7,6 @@ CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y -CONFIG_PINCTRL=y CONFIG_UART_INTERRUPT_DRIVEN=y CONFIG_GPIO=y CONFIG_ARM_MPU=y diff --git a/boards/nxp/hexiwear/hexiwear_mk64f12.dts b/boards/nxp/hexiwear/hexiwear_mk64f12.dts index f41b3410c2c..b70479153d4 100644 --- a/boards/nxp/hexiwear/hexiwear_mk64f12.dts +++ b/boards/nxp/hexiwear/hexiwear_mk64f12.dts @@ -103,7 +103,7 @@ &ftm3 { status = "okay"; - compatible = "nxp,kinetis-ftm-pwm"; + compatible = "nxp,ftm-pwm"; #pwm-cells = <3>; pinctrl-0 = <&ftm3_default>; pinctrl-names = "default"; diff --git a/boards/nxp/hexiwear/hexiwear_mk64f12.yaml b/boards/nxp/hexiwear/hexiwear_mk64f12.yaml index d8f165c7131..ecf1aa1b8aa 100644 --- a/boards/nxp/hexiwear/hexiwear_mk64f12.yaml +++ b/boards/nxp/hexiwear/hexiwear_mk64f12.yaml @@ -9,6 +9,7 @@ toolchain: supported: - adc - ble + - flash - gpio - i2c - pwm diff --git a/boards/nxp/hexiwear/hexiwear_mk64f12_defconfig b/boards/nxp/hexiwear/hexiwear_mk64f12_defconfig index 8609fa1f8da..02af29fba70 100644 --- a/boards/nxp/hexiwear/hexiwear_mk64f12_defconfig +++ b/boards/nxp/hexiwear/hexiwear_mk64f12_defconfig @@ -4,7 +4,6 @@ CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y CONFIG_GPIO=y -CONFIG_PINCTRL=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=120000000 CONFIG_OSC_LOW_POWER=y CONFIG_ARM_MPU=y diff --git a/boards/nxp/hexiwear/hexiwear_mkw40z4_defconfig b/boards/nxp/hexiwear/hexiwear_mkw40z4_defconfig index 4f25cadc1ee..1c24b1986fe 100644 --- a/boards/nxp/hexiwear/hexiwear_mkw40z4_defconfig +++ b/boards/nxp/hexiwear/hexiwear_mkw40z4_defconfig @@ -3,7 +3,6 @@ CONFIG_CONSOLE=y CONFIG_RTT_CONSOLE=y CONFIG_USE_SEGGER_RTT=y -CONFIG_PINCTRL=y CONFIG_GPIO=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=40000000 CONFIG_OSC_EXTERNAL=y diff --git a/boards/nxp/imx8mm_evk/doc/index.rst b/boards/nxp/imx8mm_evk/doc/index.rst index d834726d0c1..6984f06a8e6 100644 --- a/boards/nxp/imx8mm_evk/doc/index.rst +++ b/boards/nxp/imx8mm_evk/doc/index.rst @@ -1,7 +1,4 @@ -.. _imx8mm_evk: - -NXP i.MX8MM EVK -############### +.. zephyr:board:: imx8mm_evk Overview ******** @@ -114,21 +111,32 @@ CPU's UART4. This is used for the M4 and A53 core targets. Programming and Debugging (A53) ******************************* +U-Boot "cpu" command is used to load and kick Zephyr to Cortex-A secondary Core, Currently +it is supported in : `Real-Time Edge U-Boot`_ (use the branch "uboot_vxxxx.xx-y.y.y, +xxxx.xx is uboot version and y.y.y is Real-Time Edge Software version, for example +"uboot_v2023.04-2.9.0" branch is U-Boot v2023.04 used in Real-Time Edge Software release +v2.9.0), and pre-build images and user guide can be found at `Real-Time Edge Software`_. + +.. _Real-Time Edge U-Boot: + https://github.com/nxp-real-time-edge-sw/real-time-edge-uboot +.. _Real-Time Edge Software: + https://www.nxp.com/rtedge + Copy the compiled ``zephyr.bin`` to the first FAT partition of the SD card and plug the SD card into the board. Power it up and stop the u-boot execution at prompt. -Use U-Boot to load and kick zephyr.bin: +Use U-Boot to load and kick zephyr.bin to Cortex-A53 Core0: .. code-block:: console - fatload mmc 1:1 0x93c00000 zephyr.bin; dcache flush; icache flush; dcache off; icache off; go 0x93c00000 + fatload mmc 1:1 0x93c00000 zephyr.bin; dcache flush; icache flush; go 0x93c00000 -Or kick SMP zephyr.bin: +Or kick zephyr.bin to the other Cortex-A53 Core, for example Core2: .. code-block:: console - fatload mmc 1:1 0x93c00000 zephyr.bin; dcache flush; icache flush; dcache off; icache off; cpu 2 release 0x93c00000 + fatload mmc 1:1 0x93c00000 zephyr.bin; dcache flush; icache flush; cpu 2 release 0x93c00000 Use this configuration to run basic Zephyr applications and kernel tests, diff --git a/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53.dts b/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53.dts index 57f0a5f1ea6..13213ee010c 100644 --- a/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53.dts +++ b/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53.dts @@ -16,7 +16,8 @@ chosen { zephyr,console = &uart4; zephyr,shell-uart = &uart4; - zephyr,sram = &sram0; + /* sram node actually locates at DDR DRAM */ + zephyr,sram = &dram; }; cpus { @@ -31,7 +32,7 @@ }; }; - sram0: memory@93c00000 { + dram: memory@93c00000 { reg = <0x93c00000 DT_SIZE_M(1)>; }; }; diff --git a/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53.yaml b/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53.yaml index 1ab75987c38..4132df2e1f6 100644 --- a/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53.yaml +++ b/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53.yaml @@ -11,9 +11,11 @@ arch: arm64 toolchain: - zephyr - cross-compile -ram: 128 +ram: 1024 +supported: + - uart + - net testing: ignore_tags: - - net - bluetooth vendor: nxp diff --git a/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53_defconfig b/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53_defconfig index 03f34114970..3772b1d5281 100644 --- a/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53_defconfig +++ b/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53_defconfig @@ -24,4 +24,3 @@ CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_CLOCK_CONTROL=y -CONFIG_PINCTRL=y diff --git a/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53_smp.dts b/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53_smp.dts index f9d9793bba7..0c1e9c9f867 100644 --- a/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53_smp.dts +++ b/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53_smp.dts @@ -16,7 +16,8 @@ chosen { zephyr,console = &uart4; zephyr,shell-uart = &uart4; - zephyr,sram = &sram0; + /* sram node actually locates at DDR DRAM */ + zephyr,sram = &dram; }; cpus { @@ -33,7 +34,7 @@ method = "smc"; }; - sram0: memory@93c00000 { + dram: memory@93c00000 { reg = <0x93c00000 DT_SIZE_M(1)>; }; }; diff --git a/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53_smp.yaml b/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53_smp.yaml index 1ff3cd7af45..75c85be9542 100644 --- a/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53_smp.yaml +++ b/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53_smp.yaml @@ -11,11 +11,12 @@ arch: arm64 toolchain: - zephyr - cross-compile -ram: 128 +ram: 1024 supported: - smp + - uart + - net testing: ignore_tags: - - net - bluetooth vendor: nxp diff --git a/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53_smp_defconfig b/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53_smp_defconfig index 3c7bc851bf3..4eea7df24ae 100644 --- a/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53_smp_defconfig +++ b/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53_smp_defconfig @@ -29,4 +29,3 @@ CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_CLOCK_CONTROL=y -CONFIG_PINCTRL=y diff --git a/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_m4_defconfig b/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_m4_defconfig index e0223e4f71f..2eda7d3028f 100644 --- a/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_m4_defconfig +++ b/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_m4_defconfig @@ -11,4 +11,3 @@ CONFIG_SERIAL=y CONFIG_UART_INTERRUPT_DRIVEN=y CONFIG_CONSOLE=y CONFIG_XIP=y -CONFIG_PINCTRL=y diff --git a/boards/nxp/imx8mn_evk/doc/index.rst b/boards/nxp/imx8mn_evk/doc/index.rst index fd80ad82075..265c30be41c 100644 --- a/boards/nxp/imx8mn_evk/doc/index.rst +++ b/boards/nxp/imx8mn_evk/doc/index.rst @@ -1,7 +1,4 @@ -.. _imx8mn_evk: - -NXP i.MX8MN EVK (Cortex-A53) -############################ +.. zephyr:board:: imx8mn_evk Overview ******** @@ -84,21 +81,27 @@ CPU's UART4. Programming and Debugging ************************* +U-Boot "cpu" command is used to load and kick Zephyr to Cortex-A secondary Core, Currently +it has been supported in latest U-Boot version by `patch serials`_. + +.. _patch serials: + https://patchwork.ozlabs.org/project/uboot/list/?series=417536&archive=both&state=* + Copy the compiled ``zephyr.bin`` to the first FAT partition of the SD card and plug the SD card into the board. Power it up and stop the u-boot execution at prompt. -Use U-Boot to load and kick zephyr.bin: +Use U-Boot to load and kick zephyr.bin to Cortex-A53 Core0: .. code-block:: console - fatload mmc 1:1 0x93c00000 zephyr.bin; dcache flush; icache flush; dcache off; icache off; go 0x93c00000 + fatload mmc 1:1 0x93c00000 zephyr.bin; dcache flush; icache flush; go 0x93c00000 -Or kick SMP zephyr.bin: +Or kick zephyr.bin to the other Cortex-A53 Core, for example Core2: .. code-block:: console - fatload mmc 1:1 0x93c00000 zephyr.bin; dcache flush; icache flush; dcache off; icache off; cpu 2 release 0x93c00000 + fatload mmc 1:1 0x93c00000 zephyr.bin; dcache flush; icache flush; cpu 2 release 0x93c00000 Use this configuration to run basic Zephyr applications and kernel tests, diff --git a/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53.dts b/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53.dts index 08fd3d7b19c..60ab0ae04ed 100644 --- a/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53.dts +++ b/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53.dts @@ -16,7 +16,8 @@ chosen { zephyr,console = &uart4; zephyr,shell-uart = &uart4; - zephyr,sram = &sram0; + /* sram node actually locates at DDR DRAM */ + zephyr,sram = &dram; }; cpus { @@ -31,7 +32,7 @@ }; }; - sram0: memory@93c00000 { + dram: memory@93c00000 { reg = <0x93c00000 DT_SIZE_M(1)>; }; }; diff --git a/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53.yaml b/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53.yaml index b75fb589d21..a4a5dd0b50a 100644 --- a/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53.yaml +++ b/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53.yaml @@ -12,8 +12,10 @@ toolchain: - zephyr - cross-compile ram: 1024 +supported: + - uart + - net testing: ignore_tags: - - net - bluetooth vendor: nxp diff --git a/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53_defconfig b/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53_defconfig index 03f34114970..3772b1d5281 100644 --- a/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53_defconfig +++ b/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53_defconfig @@ -24,4 +24,3 @@ CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_CLOCK_CONTROL=y -CONFIG_PINCTRL=y diff --git a/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53_smp.dts b/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53_smp.dts index 0d115e359bc..2a846615a3a 100644 --- a/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53_smp.dts +++ b/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53_smp.dts @@ -16,7 +16,8 @@ chosen { zephyr,console = &uart4; zephyr,shell-uart = &uart4; - zephyr,sram = &sram0; + /* sram node actually locates at DDR DRAM */ + zephyr,sram = &dram; }; cpus { @@ -33,7 +34,7 @@ method = "smc"; }; - sram0: memory@93c00000 { + dram: memory@93c00000 { reg = <0x93c00000 DT_SIZE_M(1)>; }; }; diff --git a/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53_smp.yaml b/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53_smp.yaml index d82cced07a9..38390d6df28 100644 --- a/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53_smp.yaml +++ b/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53_smp.yaml @@ -14,8 +14,9 @@ toolchain: ram: 1024 supported: - smp + - uart + - net testing: ignore_tags: - - net - bluetooth vendor: nxp diff --git a/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53_smp_defconfig b/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53_smp_defconfig index 3c7bc851bf3..4eea7df24ae 100644 --- a/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53_smp_defconfig +++ b/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53_smp_defconfig @@ -29,4 +29,3 @@ CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_CLOCK_CONTROL=y -CONFIG_PINCTRL=y diff --git a/boards/nxp/imx8mp_evk/doc/index.rst b/boards/nxp/imx8mp_evk/doc/index.rst index 69a9b463b74..7afafb33593 100644 --- a/boards/nxp/imx8mp_evk/doc/index.rst +++ b/boards/nxp/imx8mp_evk/doc/index.rst @@ -1,7 +1,4 @@ -.. _imx8mp_evk: - -NXP i.MX8MP EVK -############### +.. zephyr:board:: imx8mp_evk Overview ******** @@ -102,21 +99,32 @@ CPU's UART4. Programming and Debugging (A53) ******************************* +U-Boot "cpu" command is used to load and kick Zephyr to Cortex-A secondary Core, Currently +it is supported in : `Real-Time Edge U-Boot`_ (use the branch "uboot_vxxxx.xx-y.y.y, +xxxx.xx is uboot version and y.y.y is Real-Time Edge Software version, for example +"uboot_v2023.04-2.9.0" branch is U-Boot v2023.04 used in Real-Time Edge Software release +v2.9.0), and pre-build images and user guide can be found at `Real-Time Edge Software`_. + +.. _Real-Time Edge U-Boot: + https://github.com/nxp-real-time-edge-sw/real-time-edge-uboot +.. _Real-Time Edge Software: + https://www.nxp.com/rtedge + Copy the compiled ``zephyr.bin`` to the first FAT partition of the SD card and plug the SD card into the board. Power it up and stop the u-boot execution at prompt. -Use U-Boot to load and kick non-smp zephyr.bin: +Use U-Boot to load and kick zephyr.bin to Cortex-A53 Core0: .. code-block:: console - fatload mmc 1:1 0xc0000000 zephyr.bin; dcache flush; icache flush; dcache off; icache off; go 0xc0000000 + fatload mmc 1:1 0xc0000000 zephyr.bin; dcache flush; icache flush; go 0xc0000000 -Or kick SMP zephyr.bin: +Or kick zephyr.bin to the other Cortex-A53 Core, for example Core2: .. code-block:: console - fatload mmc 1:1 0xc0000000 zephyr.bin; dcache flush; icache flush; dcache off; icache off; cpu 2 release 0xc0000000 + fatload mmc 1:1 0xc0000000 zephyr.bin; dcache flush; icache flush; cpu 2 release 0xc0000000 Use this configuration to run basic Zephyr applications and kernel tests, for example, with the :zephyr:code-sample:`synchronization` sample: @@ -266,7 +274,6 @@ board defconfig. @@ -12,3 +12,4 @@ CONFIG_CONSOLE=y CONFIG_XIP=y CONFIG_CODE_DDR=y - CONFIG_PINCTRL=y +CONFIG_ROMSTART_RELOCATION_ROM=y Then use the following steps to boot Zephyr kernel: diff --git a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53.dts b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53.dts index 692435c87d3..c50173e3f3a 100644 --- a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53.dts +++ b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53.dts @@ -16,7 +16,8 @@ chosen { zephyr,console = &uart4; zephyr,shell-uart = &uart4; - zephyr,sram = &sram0; + /* sram node actually locates at DDR DRAM */ + zephyr,sram = &dram; }; cpus { @@ -31,7 +32,7 @@ }; }; - sram0: memory@c0000000 { + dram: memory@c0000000 { reg = <0xc0000000 DT_SIZE_M(1)>; }; diff --git a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53.yaml b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53.yaml index f1c632d8298..dff021eab7e 100644 --- a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53.yaml +++ b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53.yaml @@ -11,9 +11,11 @@ arch: arm64 toolchain: - zephyr - cross-compile -ram: 128 +ram: 1024 +supported: + - uart + - net testing: ignore_tags: - - net - bluetooth vendor: nxp diff --git a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53_defconfig b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53_defconfig index 03f34114970..3772b1d5281 100644 --- a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53_defconfig +++ b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53_defconfig @@ -24,4 +24,3 @@ CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_CLOCK_CONTROL=y -CONFIG_PINCTRL=y diff --git a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53_smp.dts b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53_smp.dts index 3822987d2a4..ce1ffeac629 100644 --- a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53_smp.dts +++ b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53_smp.dts @@ -16,7 +16,8 @@ chosen { zephyr,console = &uart4; zephyr,shell-uart = &uart4; - zephyr,sram = &sram0; + /* sram node actually locates at DDR DRAM */ + zephyr,sram = &dram; }; cpus { @@ -33,7 +34,7 @@ method = "smc"; }; - sram0: memory@c0000000 { + dram: memory@c0000000 { reg = <0xc0000000 DT_SIZE_M(1)>; }; diff --git a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53_smp.yaml b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53_smp.yaml index c1b90505235..fcf5ace4a9b 100644 --- a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53_smp.yaml +++ b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53_smp.yaml @@ -11,11 +11,12 @@ arch: arm64 toolchain: - zephyr - cross-compile -ram: 128 +ram: 1024 supported: - smp + - uart + - net testing: ignore_tags: - - net - bluetooth vendor: nxp diff --git a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53_smp_defconfig b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53_smp_defconfig index 3c7bc851bf3..4eea7df24ae 100644 --- a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53_smp_defconfig +++ b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53_smp_defconfig @@ -29,4 +29,3 @@ CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_CLOCK_CONTROL=y -CONFIG_PINCTRL=y diff --git a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_adsp_defconfig b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_adsp_defconfig index e2c64fa2e0d..e1e35b5e450 100644 --- a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_adsp_defconfig +++ b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_adsp_defconfig @@ -21,5 +21,11 @@ CONFIG_CONSOLE=y # uart console (overrides remote proc console) CONFIG_UART_CONSOLE=y -# enable pin controller -CONFIG_PINCTRL=y +CONFIG_MULTI_LEVEL_INTERRUPTS=y +CONFIG_2ND_LEVEL_INTERRUPTS=y +CONFIG_2ND_LVL_ISR_TBL_OFFSET=32 +CONFIG_MAX_IRQ_PER_AGGREGATOR=64 +CONFIG_NUM_2ND_LEVEL_AGGREGATORS=3 +CONFIG_2ND_LVL_INTR_00_OFFSET=19 +CONFIG_2ND_LVL_INTR_01_OFFSET=20 +CONFIG_2ND_LVL_INTR_02_OFFSET=21 diff --git a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7_ddr_defconfig b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7_ddr_defconfig index 17542cb4eec..dd7e1a866f9 100644 --- a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7_ddr_defconfig +++ b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7_ddr_defconfig @@ -11,4 +11,3 @@ CONFIG_UART_INTERRUPT_DRIVEN=y CONFIG_CONSOLE=y CONFIG_XIP=y CONFIG_CODE_DDR=y -CONFIG_PINCTRL=y diff --git a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7_defconfig b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7_defconfig index 0f7d91f447e..e985ee6b2af 100644 --- a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7_defconfig +++ b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7_defconfig @@ -11,4 +11,3 @@ CONFIG_UART_INTERRUPT_DRIVEN=y CONFIG_CONSOLE=y CONFIG_XIP=y CONFIG_CODE_ITCM=y -CONFIG_PINCTRL=y diff --git a/boards/nxp/imx8mq_evk/doc/index.rst b/boards/nxp/imx8mq_evk/doc/index.rst index 8f21c6e9328..6022aeb6667 100644 --- a/boards/nxp/imx8mq_evk/doc/index.rst +++ b/boards/nxp/imx8mq_evk/doc/index.rst @@ -1,7 +1,4 @@ -.. _mimx8mq_evk: - -NXP MIMX8MQ EVK -############### +.. zephyr:board:: imx8mq_evk Overview ******** @@ -37,10 +34,6 @@ Zephyr OS is ported to run on the Cortex®-M4 core. - JTAG 10-pin connector - MicroUSB for UART debug, two COM ports for A53 and M4 -.. image:: img/mimx8mq_evk.jpg - :align: center - :alt: MIMX8MQ EVK - More information about the board can be found at the `NXP website`_. diff --git a/boards/nxp/imx8mq_evk/imx8mq_evk_mimx8mq6_m4_defconfig b/boards/nxp/imx8mq_evk/imx8mq_evk_mimx8mq6_m4_defconfig index e169a060eab..2f9b996f6c5 100644 --- a/boards/nxp/imx8mq_evk/imx8mq_evk_mimx8mq6_m4_defconfig +++ b/boards/nxp/imx8mq_evk/imx8mq_evk_mimx8mq6_m4_defconfig @@ -11,4 +11,3 @@ CONFIG_SERIAL=y CONFIG_UART_INTERRUPT_DRIVEN=y CONFIG_CONSOLE=y CONFIG_XIP=y -CONFIG_PINCTRL=y diff --git a/boards/nxp/imx8qm_mek/imx8qm_mek_mimx8qm6_adsp.dts b/boards/nxp/imx8qm_mek/imx8qm_mek_mimx8qm6_adsp.dts index 9eddb9385b0..81daabb579f 100644 --- a/boards/nxp/imx8qm_mek/imx8qm_mek_mimx8qm6_adsp.dts +++ b/boards/nxp/imx8qm_mek/imx8qm_mek_mimx8qm6_adsp.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include +#include #include "imx8qm_mek_mimx8qm6_adsp-pinctrl.dtsi" / { diff --git a/boards/nxp/imx8qm_mek/imx8qm_mek_mimx8qm6_adsp_defconfig b/boards/nxp/imx8qm_mek/imx8qm_mek_mimx8qm6_adsp_defconfig index aaf7764dfb5..c3e7dd9a6c8 100644 --- a/boards/nxp/imx8qm_mek/imx8qm_mek_mimx8qm6_adsp_defconfig +++ b/boards/nxp/imx8qm_mek/imx8qm_mek_mimx8qm6_adsp_defconfig @@ -1,6 +1,9 @@ # SPDX-License-Identifier: Apache-2.0 CONFIG_MAIN_STACK_SIZE=3072 +CONFIG_PM_DEVICE=y +CONFIG_PM_DEVICE_RUNTIME=y +CONFIG_POWER_DOMAIN=y # board/soc-related configurations CONFIG_LOG=y diff --git a/boards/nxp/imx8qxp_mek/imx8qxp_mek_mimx8qx6_adsp.dts b/boards/nxp/imx8qxp_mek/imx8qxp_mek_mimx8qx6_adsp.dts index f7b1d061d1a..460ca19029c 100644 --- a/boards/nxp/imx8qxp_mek/imx8qxp_mek_mimx8qx6_adsp.dts +++ b/boards/nxp/imx8qxp_mek/imx8qxp_mek_mimx8qx6_adsp.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include +#include #include "imx8qxp_mek_mimx8qx6_adsp-pinctrl.dtsi" / { @@ -31,7 +31,3 @@ pinctrl-0 = <&sai1_default>; pinctrl-names = "default"; }; - -&irqsteer { - reg = <0x51080000 DT_SIZE_K(64)>; -}; diff --git a/boards/nxp/imx8qxp_mek/imx8qxp_mek_mimx8qx6_adsp_defconfig b/boards/nxp/imx8qxp_mek/imx8qxp_mek_mimx8qx6_adsp_defconfig index aaf7764dfb5..c3e7dd9a6c8 100644 --- a/boards/nxp/imx8qxp_mek/imx8qxp_mek_mimx8qx6_adsp_defconfig +++ b/boards/nxp/imx8qxp_mek/imx8qxp_mek_mimx8qx6_adsp_defconfig @@ -1,6 +1,9 @@ # SPDX-License-Identifier: Apache-2.0 CONFIG_MAIN_STACK_SIZE=3072 +CONFIG_PM_DEVICE=y +CONFIG_PM_DEVICE_RUNTIME=y +CONFIG_POWER_DOMAIN=y # board/soc-related configurations CONFIG_LOG=y diff --git a/boards/nxp/imx93_evk/Kconfig.imx93_evk b/boards/nxp/imx93_evk/Kconfig.imx93_evk index 412da581ac6..3dec8b2b8ba 100644 --- a/boards/nxp/imx93_evk/Kconfig.imx93_evk +++ b/boards/nxp/imx93_evk/Kconfig.imx93_evk @@ -3,5 +3,5 @@ config BOARD_IMX93_EVK select SOC_MIMX9352_A55 if BOARD_IMX93_EVK_MIMX9352_A55 - select SOC_MIMX9352_M33 if BOARD_IMX93_EVK_MIMX9352_M33 + select SOC_MIMX9352_M33 if BOARD_IMX93_EVK_MIMX9352_M33 || BOARD_IMX93_EVK_MIMX9352_M33_DDR select SOC_PART_NUMBER_MIMX9352DVVXM diff --git a/boards/nxp/imx93_evk/board.yml b/boards/nxp/imx93_evk/board.yml index 008156c5fa5..f85fa29a0c3 100644 --- a/boards/nxp/imx93_evk/board.yml +++ b/boards/nxp/imx93_evk/board.yml @@ -4,3 +4,6 @@ board: vendor: nxp socs: - name: mimx9352 + variants: + - name: ddr + cpucluster: m33 diff --git a/boards/nxp/imx93_evk/doc/index.rst b/boards/nxp/imx93_evk/doc/index.rst index c37ad2eea1e..d410cd5dd26 100644 --- a/boards/nxp/imx93_evk/doc/index.rst +++ b/boards/nxp/imx93_evk/doc/index.rst @@ -1,7 +1,4 @@ -.. _imx93_evk: - -NXP i.MX93 EVK -############## +.. zephyr:board:: imx93_evk Overview ******** @@ -140,9 +137,42 @@ over dts config. For instance, if ``CONFIG_CAN`` is enabled, MUX A is selected even if ``mux="B";`` is configured in dts, and an warning would be reported in the log. +User Button GPIO Option +-------------------------- + +The user buttons RFU_BTN1 and RFU_BTN2 is connected to i.MX 93 GPIO by default, +but can be changed to connect to onboard GPIO expander PCAL6524 with on-board DIP +switches. To do this, switch SW1006 to 0000, then switch SW1005 to 0101. An devicetree +overlay is included to support this. + +Run following command to test user buttons on PCAL6524: + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/button + :host-os: unix + :board: imx93_evk/mimx9352/a55 + :goals: build + :gen-args: -DEXTRA_DTC_OVERLAY_FILE=imx93_evk_mimx9352_exp_btn.overlay + +Run the app, press RFU_BTN1 and the red LED turns on accordingly. + +Note: The overlay only supports ``mimx9352/a55``, but can be extended to support +``mimx9352/m33`` if I2C and PCAL6524 is enabled. + Programming and Debugging (A55) ******************************* +U-Boot "cpu" command is used to load and kick Zephyr to Cortex-A secondary Core, Currently +it is supported in : `Real-Time Edge U-Boot`_ (use the branch "uboot_vxxxx.xx-y.y.y, +xxxx.xx is uboot version and y.y.y is Real-Time Edge Software version, for example +"uboot_v2023.04-2.9.0" branch is U-Boot v2023.04 used in Real-Time Edge Software release +v2.9.0), and pre-build images and user guide can be found at `Real-Time Edge Software`_. + +.. _Real-Time Edge U-Boot: + https://github.com/nxp-real-time-edge-sw/real-time-edge-uboot +.. _Real-Time Edge Software: + https://www.nxp.com/rtedge + Copy the compiled ``zephyr.bin`` to the first FAT partition of the SD card and plug the SD card into the board. Power it up and stop the u-boot execution at prompt. @@ -151,14 +181,14 @@ Use U-Boot to load and kick zephyr.bin to Cortex-A55 Core1: .. code-block:: console - fatload mmc 1:1 0xd0000000 zephyr.bin; dcache flush; icache flush; dcache off; icache off; cpu 1 release 0xd0000000 + fatload mmc 1:1 0xd0000000 zephyr.bin; dcache flush; icache flush; cpu 1 release 0xd0000000 Or use the following command to kick zephyr.bin to Cortex-A55 Core0: .. code-block:: console - fatload mmc 1:1 0xd0000000 zephyr.bin; dcache flush; icache flush; dcache off; icache off; go 0xd0000000 + fatload mmc 1:1 0xd0000000 zephyr.bin; dcache flush; icache flush; go 0xd0000000 Use this configuration to run basic Zephyr applications and kernel tests, @@ -210,10 +240,26 @@ prompt. Use U-Boot to load and kick zephyr.bin to Cortex-M33 Core: +Boot with code from TCM +======================= + .. code-block:: console load mmc 1:1 0x80000000 zephyr.bin;cp.b 0x80000000 0x201e0000 0x30000;bootaux 0x1ffe0000 0 +Boot with code from DDR +======================= + +.. code-block:: console + + load mmc 1:1 0x84000000 zephyr.bin;dcache flush;bootaux 0x84000000 0 + +Note: Cortex M33 need execute permission to run code from DDR memory. In order +to enable this, `imx-atf`_ can to be modified in "plat/imx/imx93/trdc_config.h". + +.. _imx-atf: + https://github.com/nxp-imx/imx-atf + Use this configuration to run basic Zephyr applications and kernel tests, for example, with the :zephyr:code-sample:`synchronization` sample: diff --git a/boards/nxp/imx93_evk/dts/imx93_evk_mimx9352_exp_btn.overlay b/boards/nxp/imx93_evk/dts/imx93_evk_mimx9352_exp_btn.overlay new file mode 100644 index 00000000000..7ebb35dd483 --- /dev/null +++ b/boards/nxp/imx93_evk/dts/imx93_evk_mimx9352_exp_btn.overlay @@ -0,0 +1,35 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * Apply this overlay to test RFU_BTN1 and RFU_BTN2 on PCAL6524. + * + * The user buttons RFU_BTN1 and RFU_BTN2 is connected to i.MX 93 GPIO by default, + * but can be changed to connect to onboard GPIO expander PCAL6524. To do this, + * switch SW1006 to 0000, then switch SW1005 to 0101. + */ + +/* Remove default keys */ +/delete-node/ &btn_1; +/delete-node/ &btn_2; + +/ { + keys { + compatible = "gpio-keys"; + + btn_1: btn_1{ + label = "BTN1"; + gpios = <&gpio_exp1 5 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + + btn_2: btn_2{ + label = "BTN2"; + gpios = <&gpio_exp1 6 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + }; +}; diff --git a/boards/nxp/imx93_evk/imx93_evk_mimx9352_a55.dts b/boards/nxp/imx93_evk/imx93_evk_mimx9352_a55.dts index 8fbf9edf6ba..67272c846b5 100644 --- a/boards/nxp/imx93_evk/imx93_evk_mimx9352_a55.dts +++ b/boards/nxp/imx93_evk/imx93_evk_mimx9352_a55.dts @@ -8,6 +8,7 @@ #include #include "imx93_evk-pinctrl.dtsi" +#include / { model = "NXP i.MX93 A55"; @@ -16,7 +17,8 @@ chosen { zephyr,console = &lpuart2; zephyr,shell-uart = &lpuart2; - zephyr,sram = &sram0; + /* sram node actually locates at DDR DRAM */ + zephyr,sram = &dram; zephyr,canbus = &flexcan2; }; @@ -26,7 +28,7 @@ }; }; - sram0: memory@d0000000 { + dram: memory@d0000000 { reg = <0xd0000000 DT_SIZE_M(1)>; }; @@ -58,11 +60,13 @@ btn_1: btn_1{ label = "BTN1"; gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; + zephyr,code = ; }; btn_2: btn_2{ label = "BTN2"; gpios = <&gpio2 24 GPIO_ACTIVE_LOW>; + zephyr,code = ; }; }; diff --git a/boards/nxp/imx93_evk/imx93_evk_mimx9352_a55.yaml b/boards/nxp/imx93_evk/imx93_evk_mimx9352_a55.yaml index 89cc546d7b3..feeb48fe805 100644 --- a/boards/nxp/imx93_evk/imx93_evk_mimx9352_a55.yaml +++ b/boards/nxp/imx93_evk/imx93_evk_mimx9352_a55.yaml @@ -18,8 +18,8 @@ supported: - i2c - spi - can + - net testing: ignore_tags: - - net - bluetooth vendor: nxp diff --git a/boards/nxp/imx93_evk/imx93_evk_mimx9352_a55_defconfig b/boards/nxp/imx93_evk/imx93_evk_mimx9352_a55_defconfig index 6b4743c4643..fb142f3cf4a 100644 --- a/boards/nxp/imx93_evk/imx93_evk_mimx9352_a55_defconfig +++ b/boards/nxp/imx93_evk/imx93_evk_mimx9352_a55_defconfig @@ -28,4 +28,3 @@ CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_CLOCK_CONTROL=y -CONFIG_PINCTRL=y diff --git a/boards/nxp/imx93_evk/imx93_evk_mimx9352_m33.dts b/boards/nxp/imx93_evk/imx93_evk_mimx9352_m33.dts index 5c75e10ccc9..e8db0b54929 100644 --- a/boards/nxp/imx93_evk/imx93_evk_mimx9352_m33.dts +++ b/boards/nxp/imx93_evk/imx93_evk_mimx9352_m33.dts @@ -8,6 +8,7 @@ #include #include "imx93_evk-pinctrl.dtsi" +#include / { model = "NXP i.MX93 EVK board"; @@ -50,11 +51,13 @@ btn_1: btn_1{ label = "BTN1"; gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; + zephyr,code = ; }; btn_2: btn_2{ label = "BTN2"; gpios = <&gpio2 24 GPIO_ACTIVE_LOW>; + zephyr,code = ; }; }; }; diff --git a/boards/nxp/imx93_evk/imx93_evk_mimx9352_m33_ddr.dts b/boards/nxp/imx93_evk/imx93_evk_mimx9352_m33_ddr.dts new file mode 100644 index 00000000000..7c690afd3f3 --- /dev/null +++ b/boards/nxp/imx93_evk/imx93_evk_mimx9352_m33_ddr.dts @@ -0,0 +1,23 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include "imx93_evk_mimx9352_m33.dts" + +/ { + model = "NXP i.MX93 EVK board DDR variant"; + + chosen { + zephyr,sram = &ddr; + /delete-property/ zephyr,flash; + }; + + ddr: memory@84000000 { + device_type = "memory"; + reg = <0x84000000 DT_SIZE_M(4)>; + }; +}; diff --git a/boards/nxp/imx93_evk/imx93_evk_mimx9352_m33_ddr.yaml b/boards/nxp/imx93_evk/imx93_evk_mimx9352_m33_ddr.yaml new file mode 100644 index 00000000000..a322cb1ed7c --- /dev/null +++ b/boards/nxp/imx93_evk/imx93_evk_mimx9352_m33_ddr.yaml @@ -0,0 +1,16 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +identifier: imx93_evk/mimx9352/m33/ddr +name: NXP i.MX93 EVK M33 DDR +type: mcu +arch: arm +toolchain: + - zephyr + - cross-compile +ram: 4096 +flash: 0 +supported: + - gpio + - uart +vendor: nxp diff --git a/boards/nxp/imx93_evk/imx93_evk_mimx9352_m33_ddr_defconfig b/boards/nxp/imx93_evk/imx93_evk_mimx9352_m33_ddr_defconfig new file mode 100644 index 00000000000..75cc3357682 --- /dev/null +++ b/boards/nxp/imx93_evk/imx93_evk_mimx9352_m33_ddr_defconfig @@ -0,0 +1,9 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_CLOCK_CONTROL=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_CONSOLE=y +CONFIG_XIP=n diff --git a/boards/nxp/imx93_evk/imx93_evk_mimx9352_m33_defconfig b/boards/nxp/imx93_evk/imx93_evk_mimx9352_m33_defconfig index 028b1fc71d1..3b790374be6 100644 --- a/boards/nxp/imx93_evk/imx93_evk_mimx9352_m33_defconfig +++ b/boards/nxp/imx93_evk/imx93_evk_mimx9352_m33_defconfig @@ -2,7 +2,6 @@ # SPDX-License-Identifier: Apache-2.0 CONFIG_CLOCK_CONTROL=y -CONFIG_PINCTRL=y CONFIG_SERIAL=y CONFIG_UART_CONSOLE=y CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/nxp/imx95_evk/CMakeLists.txt b/boards/nxp/imx95_evk/CMakeLists.txt new file mode 100644 index 00000000000..4b246954743 --- /dev/null +++ b/boards/nxp/imx95_evk/CMakeLists.txt @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: Apache-2.0 + +if (CONFIG_SOF AND CONFIG_BOARD_IMX95_EVK_MIMX9596_M7_DDR) + add_custom_target(zephyr.ri ALL + DEPENDS ${CMAKE_BINARY_DIR}/zephyr/zephyr.ri + ) + + add_custom_command( + OUTPUT ${CMAKE_BINARY_DIR}/zephyr/zephyr.ri + COMMAND west sign --if-tool-available --tool rimage --build-dir ${CMAKE_BINARY_DIR} ${WEST_SIGN_OPTS} + DEPENDS ${CMAKE_BINARY_DIR}/zephyr/${KERNEL_ELF_NAME} + ) +endif() diff --git a/boards/nxp/imx95_evk/board.cmake b/boards/nxp/imx95_evk/board.cmake new file mode 100644 index 00000000000..57089c3f1b0 --- /dev/null +++ b/boards/nxp/imx95_evk/board.cmake @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: Apache-2.0 + +if (CONFIG_SOF AND CONFIG_BOARD_IMX95_EVK_MIMX9596_M7_DDR) + board_set_rimage_target(imx95) +endif() diff --git a/boards/nxp/imx95_evk/doc/index.rst b/boards/nxp/imx95_evk/doc/index.rst index 078b0abcdac..1acf8cc536f 100644 --- a/boards/nxp/imx95_evk/doc/index.rst +++ b/boards/nxp/imx95_evk/doc/index.rst @@ -1,7 +1,4 @@ -.. _imx95_evk: - -NXP i.MX95 EVK -############## +.. zephyr:board:: imx95_evk Overview ******** @@ -91,6 +88,10 @@ The Zephyr ``imx95_evk/mimx9596/m7`` board target supports the following hardwar +-----------+------------+-------------------------------------+ | UART | on-chip | serial port | +-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| TPM | on-chip | tpm | ++-----------+------------+-------------------------------------+ The Zephyr ``imx95_evk/mimx9596/a55`` and ``imx95_evk/mimx9596/a55/smp`` board targets support the following hardware features: @@ -122,6 +123,15 @@ Serial Port This board configuration uses a single serial communication channel with the CPU's UART1 for Cortex-A55, UART3 for Cortex-M7. +TPM +--- + +Two channels are enabled on TPM2 for PWM for M7. Signals can be observerd with +oscilloscope. +Channel 2 signal routed to resistance R881. +Channel 3 signal routed to resistance R882. + + Programming and Debugging (A55) ******************************* diff --git a/boards/nxp/imx95_evk/imx95_evk-pinctrl.dtsi b/boards/nxp/imx95_evk/imx95_evk-pinctrl.dtsi index bb4a8db2298..fecd72a46f1 100644 --- a/boards/nxp/imx95_evk/imx95_evk-pinctrl.dtsi +++ b/boards/nxp/imx95_evk/imx95_evk-pinctrl.dtsi @@ -6,6 +6,27 @@ #include &pinctrl { + lpi2c5_default: lpi2c5_default { + group0 { + pinmux = <&iomuxc_gpio_io23_lpi2c_scl_lpi2c5_scl>, + <&iomuxc_gpio_io22_lpi2c_sda_lpi2c5_sda>; + drive-open-drain; + slew-rate = "slightly_fast"; + drive-strength = "x4"; + input-enable; + }; + }; + + lpi2c7_default: lpi2c7_default { + group0 { + pinmux = <&iomuxc_gpio_io09_lpi2c_scl_lpi2c7_scl>, + <&iomuxc_gpio_io08_lpi2c_sda_lpi2c7_sda>; + drive-open-drain; + slew-rate = "slightly_fast"; + drive-strength = "x4"; + input-enable; + }; + }; lpuart1_default: lpuart1_default { group0 { @@ -26,4 +47,28 @@ drive-strength = "x4"; }; }; + + sai3_default: sai3_default { + group0 { + pinmux = <&iomuxc_gpio_io16_sai_tx_bclk_sai3_tx_bclk>, + <&iomuxc_gpio_io17_sai_mclk_sai3_mclk>, + <&iomuxc_gpio_io20_sai_rx_data_bit_sai3_rx_data_bit0>, + <&iomuxc_gpio_io21_sai_tx_data_bit_sai3_tx_data_bit0>, + <&iomuxc_gpio_io26_sai_tx_sync_sai3_tx_sync>; + bias-pull-up; + slew-rate = "slightly_fast"; + drive-strength = "x4"; + }; + }; + + tpm2_default: tpm2_default { + group0 { + pinmux = <&iomuxc_i2c2_scl_tpm_ch_tpm2_ch2>, + <&iomuxc_i2c2_sda_tpm_ch_tpm2_ch3>; + drive-open-drain; + slew-rate = "slightly_fast"; + drive-strength = "x4"; + input-enable; + }; + }; }; diff --git a/boards/nxp/imx95_evk/imx95_evk_mimx9596_a55.dts b/boards/nxp/imx95_evk/imx95_evk_mimx9596_a55.dts index 8cf6aa2a949..62997746f44 100644 --- a/boards/nxp/imx95_evk/imx95_evk_mimx9596_a55.dts +++ b/boards/nxp/imx95_evk/imx95_evk_mimx9596_a55.dts @@ -16,7 +16,8 @@ chosen { zephyr,console = &lpuart1; zephyr,shell-uart = &lpuart1; - zephyr,sram = &sram0; + /* sram node actually locates at DDR DRAM */ + zephyr,sram = &dram; }; cpus { @@ -41,7 +42,7 @@ }; }; - sram0: memory@d0000000 { + dram: memory@d0000000 { reg = <0xd0000000 DT_SIZE_M(1)>; }; }; diff --git a/boards/nxp/imx95_evk/imx95_evk_mimx9596_a55_smp.dts b/boards/nxp/imx95_evk/imx95_evk_mimx9596_a55_smp.dts index 3cf7ce362a8..cdb7edf2f74 100644 --- a/boards/nxp/imx95_evk/imx95_evk_mimx9596_a55_smp.dts +++ b/boards/nxp/imx95_evk/imx95_evk_mimx9596_a55_smp.dts @@ -16,7 +16,7 @@ chosen { zephyr,console = &lpuart1; zephyr,shell-uart = &lpuart1; - zephyr,sram = &sram0; + zephyr,sram = &dram; }; psci { @@ -24,7 +24,7 @@ method = "smc"; }; - sram0: memory@d0000000 { + dram: memory@d0000000 { reg = <0xd0000000 DT_SIZE_M(1)>; }; }; diff --git a/boards/nxp/imx95_evk/imx95_evk_mimx9596_m7.dts b/boards/nxp/imx95_evk/imx95_evk_mimx9596_m7.dts index 5ffc24e8df6..ebc22540f8e 100644 --- a/boards/nxp/imx95_evk/imx95_evk_mimx9596_m7.dts +++ b/boards/nxp/imx95_evk/imx95_evk_mimx9596_m7.dts @@ -23,9 +23,32 @@ }; }; +&lpi2c5 { + pinctrl-0 = <&lpi2c5_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&lpi2c7 { + pinctrl-0 = <&lpi2c7_default>; + pinctrl-names = "default"; + status = "okay"; +}; + &lpuart3 { status = "okay"; current-speed = <115200>; pinctrl-0 = <&lpuart3_default>; pinctrl-names = "default"; }; + +&sai3 { + pinctrl-0 = <&sai3_default>; + pinctrl-names = "default"; +}; + +&tpm2 { + pinctrl-0 = <&tpm2_default>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/boards/nxp/imx95_evk/imx95_evk_mimx9596_m7.yaml b/boards/nxp/imx95_evk/imx95_evk_mimx9596_m7.yaml index c8543538d0a..23fab0caeab 100644 --- a/boards/nxp/imx95_evk/imx95_evk_mimx9596_m7.yaml +++ b/boards/nxp/imx95_evk/imx95_evk_mimx9596_m7.yaml @@ -16,4 +16,6 @@ toolchain: - xtools supported: - uart + - i2c + - pwm vendor: nxp diff --git a/boards/nxp/lpcxpresso11u68/doc/index.rst b/boards/nxp/lpcxpresso11u68/doc/index.rst index 244fb7427b0..4fe74d245c8 100644 --- a/boards/nxp/lpcxpresso11u68/doc/index.rst +++ b/boards/nxp/lpcxpresso11u68/doc/index.rst @@ -1,7 +1,4 @@ -.. _lpcxpresso11u68: - -NXP LPCXpresso11U68 -################### +.. zephyr:board:: lpcxpresso11u68 Overview ******** @@ -9,10 +6,6 @@ Overview The LPCXpresso11u68 development board uses an NXP LPC11U68 MCU based on an ARM Cortex-M0+ core. -.. figure:: lpcxpresso11u68.jpg - :align: center - :alt: LPCXpresso11U68 - Hardware ******** diff --git a/boards/nxp/lpcxpresso51u68/doc/index.rst b/boards/nxp/lpcxpresso51u68/doc/index.rst index 491aa2beab1..3246a9f9393 100644 --- a/boards/nxp/lpcxpresso51u68/doc/index.rst +++ b/boards/nxp/lpcxpresso51u68/doc/index.rst @@ -1,7 +1,4 @@ -.. _lpcxpresso51u68: - -NXP LPCXPRESSO51U68 -################### +.. zephyr:board:: lpcxpresso51u68 Overview ******** @@ -9,10 +6,6 @@ Overview The LPCXpresso51u68 development board uses an NXP LPC51U68 MCU based on an ARM CORTEX-M0+ core. -.. figure:: lpcxpresso51u68.jpg - :align: center - :alt: LPCXpresso51U68 - Hardware ******** diff --git a/boards/nxp/lpcxpresso54114/doc/index.rst b/boards/nxp/lpcxpresso54114/doc/index.rst index df2e2aabf0d..410a052b433 100644 --- a/boards/nxp/lpcxpresso54114/doc/index.rst +++ b/boards/nxp/lpcxpresso54114/doc/index.rst @@ -1,7 +1,4 @@ -.. _lpcxpresso54114: - -NXP LPCXPRESSO54114 -################### +.. zephyr:board:: lpcxpresso54114 Overview ******** @@ -13,10 +10,6 @@ microcontrollers. LPCXpresso is an end-to-end solution enabling embedded engineers to develop their applications from initial evaluation to final production. -.. image:: lpcxpresso54114_m4.jpg - :align: center - :alt: LPCXPRESSO54114 - Hardware ******** diff --git a/boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m0_defconfig b/boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m0_defconfig index 9242d2359a0..fb30ae49fbe 100644 --- a/boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m0_defconfig +++ b/boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m0_defconfig @@ -8,4 +8,3 @@ CONFIG_USE_SEGGER_RTT=y CONFIG_SERIAL=n CONFIG_GPIO=n CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=48000000 -CONFIG_PINCTRL=y diff --git a/boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m4.yaml b/boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m4.yaml index c539b58e442..f2ed30e6976 100644 --- a/boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m4.yaml +++ b/boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m4.yaml @@ -17,6 +17,7 @@ toolchain: supported: - arduino_i2c - arduino_spi + - flash - gpio - i2c - spi diff --git a/boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m4_defconfig b/boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m4_defconfig index 921c68d49ad..f12168a9c4a 100644 --- a/boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m4_defconfig +++ b/boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m4_defconfig @@ -9,7 +9,6 @@ CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y CONFIG_UART_INTERRUPT_DRIVEN=y CONFIG_GPIO=y -CONFIG_PINCTRL=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=48000000 CONFIG_ARM_MPU=y CONFIG_HW_STACK_PROTECTION=y diff --git a/boards/nxp/lpcxpresso55s06/doc/index.rst b/boards/nxp/lpcxpresso55s06/doc/index.rst index 10a1b6728ca..a4f5234aa70 100644 --- a/boards/nxp/lpcxpresso55s06/doc/index.rst +++ b/boards/nxp/lpcxpresso55s06/doc/index.rst @@ -1,7 +1,4 @@ -.. _lpcxpresso55s06: - -NXP LPCXpresso55S06 -################### +.. zephyr:board:: lpcxpresso55s06 Overview ******** @@ -13,10 +10,6 @@ with additional expansion ports around the Arduino footprint, along with a PMod/host interface port and MikroElektronika Click module site. -.. image:: lpcxpress55s06.jpg - :align: center - :alt: LPCXpresso55S06 - Hardware ******** @@ -45,7 +38,7 @@ Supported Features The lpcxpresso55s06 board configuration supports the hardware features listed below. For additional features not yet supported, please also refer to the -:ref:`lpcxpresso55s69` , which is the superset board in NXP's LPC55xx series. +:zephyr:board:`lpcxpresso55s69` , which is the superset board in NXP's LPC55xx series. NXP prioritizes enabling the superset board with NXP's Full Platform Support for Zephyr. Therefore, the lpcxpresso55s69 board may have additional features already supported, which can also be re-used on this lpcxpresso55s06 board: diff --git a/boards/nxp/lpcxpresso55s06/lpcxpresso55s06.yaml b/boards/nxp/lpcxpresso55s06/lpcxpresso55s06.yaml index fcf89bfe0ad..f6cbb2e4e6e 100644 --- a/boards/nxp/lpcxpresso55s06/lpcxpresso55s06.yaml +++ b/boards/nxp/lpcxpresso55s06/lpcxpresso55s06.yaml @@ -14,6 +14,7 @@ toolchain: - gnuarmemb - xtools supported: - - gpio - can + - flash + - gpio vendor: nxp diff --git a/boards/nxp/lpcxpresso55s06/lpcxpresso55s06_common.dtsi b/boards/nxp/lpcxpresso55s06/lpcxpresso55s06_common.dtsi index dd3529fa641..20f427b3b93 100644 --- a/boards/nxp/lpcxpresso55s06/lpcxpresso55s06_common.dtsi +++ b/boards/nxp/lpcxpresso55s06/lpcxpresso55s06_common.dtsi @@ -29,6 +29,7 @@ sw1 = &btn_usr; sw2 = &btn_isp; usart-0 = &flexcomm0; + mcuboot-button0 = &btn_wk; }; leds { diff --git a/boards/nxp/lpcxpresso55s06/lpcxpresso55s06_defconfig b/boards/nxp/lpcxpresso55s06/lpcxpresso55s06_defconfig index 6fcd01d4551..6eb2963ddac 100644 --- a/boards/nxp/lpcxpresso55s06/lpcxpresso55s06_defconfig +++ b/boards/nxp/lpcxpresso55s06/lpcxpresso55s06_defconfig @@ -9,7 +9,6 @@ CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y CONFIG_UART_INTERRUPT_DRIVEN=y CONFIG_GPIO=y -CONFIG_PINCTRL=y CONFIG_ARM_MPU=y CONFIG_RUNTIME_NMI=y diff --git a/boards/nxp/lpcxpresso55s16/doc/index.rst b/boards/nxp/lpcxpresso55s16/doc/index.rst index 8089e3de0ef..f38fd083c8a 100644 --- a/boards/nxp/lpcxpresso55s16/doc/index.rst +++ b/boards/nxp/lpcxpresso55s16/doc/index.rst @@ -1,7 +1,4 @@ -.. _lpcxpresso55s16: - -NXP LPCXpresso55S16 -################### +.. zephyr:board:: lpcxpresso55s16 Overview ******** @@ -13,10 +10,6 @@ with additional expansion ports around the Arduino footprint, along with a PMod/host interface port and MikroElektronika Click module site. -.. image:: lpcxpresso55S16.jpg - :align: center - :alt: LPCXpresso55S16 - Hardware ******** @@ -50,7 +43,7 @@ Supported Features The lpcxpresso55s16 board configuration supports the hardware features listed below. For additional features not yet supported, please also refer to the -:ref:`lpcxpresso55s69` , which is the superset board in NXP's LPC55xx series. +:zephyr:board:`lpcxpresso55s69` , which is the superset board in NXP's LPC55xx series. NXP prioritizes enabling the superset board with NXP's Full Platform Support for Zephyr. Therefore, the lpcxpresso55s69 board may have additional features already supported, which can also be re-used on this lpcxpresso55s16 board: diff --git a/boards/nxp/lpcxpresso55s16/lpcxpresso55s16.yaml b/boards/nxp/lpcxpresso55s16/lpcxpresso55s16.yaml index 22bd86054f7..8b930b43ae5 100644 --- a/boards/nxp/lpcxpresso55s16/lpcxpresso55s16.yaml +++ b/boards/nxp/lpcxpresso55s16/lpcxpresso55s16.yaml @@ -20,6 +20,7 @@ supported: - arduino_spi - can - counter + - flash - gpio - i2c - spi diff --git a/boards/nxp/lpcxpresso55s16/lpcxpresso55s16_common.dtsi b/boards/nxp/lpcxpresso55s16/lpcxpresso55s16_common.dtsi index 54ef8478814..55e2e661ac4 100644 --- a/boards/nxp/lpcxpresso55s16/lpcxpresso55s16_common.dtsi +++ b/boards/nxp/lpcxpresso55s16/lpcxpresso55s16_common.dtsi @@ -31,6 +31,7 @@ usart-0 = &flexcomm0; magn0 = &fxos8700; accel0 = &fxos8700; + mcuboot-button0 = &btn_wk; }; leds { diff --git a/boards/nxp/lpcxpresso55s16/lpcxpresso55s16_defconfig b/boards/nxp/lpcxpresso55s16/lpcxpresso55s16_defconfig index e327fa910d7..a6b7ba148b6 100644 --- a/boards/nxp/lpcxpresso55s16/lpcxpresso55s16_defconfig +++ b/boards/nxp/lpcxpresso55s16/lpcxpresso55s16_defconfig @@ -9,7 +9,6 @@ CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y CONFIG_UART_INTERRUPT_DRIVEN=y CONFIG_GPIO=y -CONFIG_PINCTRL=y CONFIG_ARM_MPU=y CONFIG_RUNTIME_NMI=y diff --git a/boards/nxp/lpcxpresso55s28/doc/index.rst b/boards/nxp/lpcxpresso55s28/doc/index.rst index df40571a18b..b0cea1547be 100644 --- a/boards/nxp/lpcxpresso55s28/doc/index.rst +++ b/boards/nxp/lpcxpresso55s28/doc/index.rst @@ -1,7 +1,4 @@ -.. _lpcxpresso55s28: - -NXP LPCXpresso55S28 -################### +.. zephyr:board:: lpcxpresso55s28 Overview ******** @@ -12,10 +9,6 @@ architecture. The board includes a high-performance onboard debug probe, audio subsystem and accelerometer, with several options for adding off-the-shelf add-on boards for networking, sensors, displays, and other interfaces. -.. image:: LPC55S28-EVK.jpg - :align: center - :alt: LPCXpresso55S28 - Hardware ******** @@ -50,7 +43,7 @@ Supported Features The lpcxpresso55s28 board configuration supports the hardware features listed below. For additional features not yet supported, please also refer to the -:ref:`lpcxpresso55s69` , which is the superset board in NXP's LPC55xx series. +:zephyr:board:`lpcxpresso55s69` , which is the superset board in NXP's LPC55xx series. NXP prioritizes enabling the superset board with NXP's Full Platform Support for Zephyr. Therefore, the lpcxpresso55s69 board may have additional features already supported, which can also be re-used on this lpcxpresso55s28 board: diff --git a/boards/nxp/lpcxpresso55s28/lpcxpresso55s28.dts b/boards/nxp/lpcxpresso55s28/lpcxpresso55s28.dts index 9fe9ed0c3d5..a2407a2004a 100644 --- a/boards/nxp/lpcxpresso55s28/lpcxpresso55s28.dts +++ b/boards/nxp/lpcxpresso55s28/lpcxpresso55s28.dts @@ -21,6 +21,7 @@ sw2 = &user_button_3; watchdog0 = &wwdt0; accel0 = &mma8652fc; + mcuboot-button0 = &user_button_1; }; chosen { diff --git a/boards/nxp/lpcxpresso55s28/lpcxpresso55s28.yaml b/boards/nxp/lpcxpresso55s28/lpcxpresso55s28.yaml index 77bdb93e90f..898d75c9c27 100644 --- a/boards/nxp/lpcxpresso55s28/lpcxpresso55s28.yaml +++ b/boards/nxp/lpcxpresso55s28/lpcxpresso55s28.yaml @@ -16,8 +16,10 @@ toolchain: - xtools supported: - adc + - arduino_gpio - arduino_i2c - arduino_spi + - flash - gpio - i2c - spi diff --git a/boards/nxp/lpcxpresso55s28/lpcxpresso55s28_defconfig b/boards/nxp/lpcxpresso55s28/lpcxpresso55s28_defconfig index 1a23b7b3d78..89c400f362f 100644 --- a/boards/nxp/lpcxpresso55s28/lpcxpresso55s28_defconfig +++ b/boards/nxp/lpcxpresso55s28/lpcxpresso55s28_defconfig @@ -10,7 +10,6 @@ CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y CONFIG_UART_INTERRUPT_DRIVEN=y CONFIG_GPIO=y -CONFIG_PINCTRL=y CONFIG_ARM_MPU=y CONFIG_HW_STACK_PROTECTION=y diff --git a/boards/nxp/lpcxpresso55s36/doc/index.rst b/boards/nxp/lpcxpresso55s36/doc/index.rst index 32c7993c3a3..f361f1ea796 100644 --- a/boards/nxp/lpcxpresso55s36/doc/index.rst +++ b/boards/nxp/lpcxpresso55s36/doc/index.rst @@ -1,7 +1,4 @@ -.. _lpcxpresso55s36: - -NXP LPCXpresso55S36 -################### +.. zephyr:board:: lpcxpresso55s36 Overview ******** @@ -13,10 +10,6 @@ with additional expansion ports around the Arduino footprint, along with a PMod/host interface port and MikroElektronika Click module site. -.. image:: lpcxpresso55S36.jpg - :align: center - :alt: LPCXpresso55S36 - Hardware ******** @@ -52,7 +45,7 @@ family of MCUs. This board is a focus for NXP's Full Platform Support for Zephyr, to better enable the entire LPC55(S)3x family. NXP prioritizes enabling this board with new support for Zephyr features. The lpcxpresso55s36 board configuration supports the hardware features below. Another similar superset -board is the :ref:`lpcxpresso55s69`, and that board may have additional features +board is the :zephyr:board:`lpcxpresso55s69`, and that board may have additional features already supported, which can also be re-used on this lpcxpresso55s36 board: +-----------+------------+-------------------------------------+ @@ -166,19 +159,17 @@ and :ref:`application_run` for more details). Configuring a Debug Probe ========================= -A debug probe is used for both flashing and debugging the board. This -board is configured by default to use the LPC-Link2 CMSIS-DAP Onboard -Debug Probe, however the :ref:`pyocd-debug-host-tools` does not yet -support the LPC55S36 so you must reconfigure the board for one of the -J-Link debug probe instead. - -First install the :ref:`jlink-debug-host-tools` and make sure they are -in your search path. - -Then follow the instructions in -:ref:`lpclink2-jlink-onboard-debug-probe` to program the J-Link -firmware. Please make sure you have the latest firmware for this -board. +A debug probe is used for both flashing and debugging the board. This board is +configured by default to use the integrated :ref:`mcu-link-onboard-debug-probe` +in the CMSIS-DAP mode. To use this probe with Zephyr, you need to install the +:ref:`linkserver-debug-host-tools` and make sure they are in your search path. +Then, use the ``linkserver`` runner option to flash and debug the board. Refer +to the detailed overview about :ref:`application_debugging` for additional +information. + +The integrated MCU-Link hardware can also be used as a J-Link probe with a +firmware update, as described in :ref:`mcu-link-jlink-onboard-debug-probe`. +The :ref:`jlink-debug-host-tools` should be available in this case. Configuring a Console ===================== diff --git a/boards/nxp/lpcxpresso55s36/lpcxpresso55s36.dts b/boards/nxp/lpcxpresso55s36/lpcxpresso55s36.dts index d81a21d48ff..acec9939307 100644 --- a/boards/nxp/lpcxpresso55s36/lpcxpresso55s36.dts +++ b/boards/nxp/lpcxpresso55s36/lpcxpresso55s36.dts @@ -33,6 +33,7 @@ sw1 = &btn_usr; usart-0 = &flexcomm0; pwm-0 = &flexpwm1_pwm0; + mcuboot-button0 = &btn_wk; }; leds { diff --git a/boards/nxp/lpcxpresso55s36/lpcxpresso55s36.yaml b/boards/nxp/lpcxpresso55s36/lpcxpresso55s36.yaml index 806fadc48d3..aec2ca1f6ac 100644 --- a/boards/nxp/lpcxpresso55s36/lpcxpresso55s36.yaml +++ b/boards/nxp/lpcxpresso55s36/lpcxpresso55s36.yaml @@ -15,10 +15,12 @@ toolchain: - gnuarmemb - xtools supported: + - arduino_gpio - can + - dac + - flash - gpio - pwm - - dac - usb_device - usbd vendor: nxp diff --git a/boards/nxp/lpcxpresso55s36/lpcxpresso55s36_defconfig b/boards/nxp/lpcxpresso55s36/lpcxpresso55s36_defconfig index 9aaf3ff8452..b9fc46bd29e 100644 --- a/boards/nxp/lpcxpresso55s36/lpcxpresso55s36_defconfig +++ b/boards/nxp/lpcxpresso55s36/lpcxpresso55s36_defconfig @@ -9,7 +9,6 @@ CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y CONFIG_UART_INTERRUPT_DRIVEN=y CONFIG_GPIO=y -CONFIG_PINCTRL=y CONFIG_ARM_MPU=y CONFIG_RUNTIME_NMI=y diff --git a/boards/nxp/lpcxpresso55s69/board.cmake b/boards/nxp/lpcxpresso55s69/board.cmake index 137b2e614f3..554ff716de3 100644 --- a/boards/nxp/lpcxpresso55s69/board.cmake +++ b/boards/nxp/lpcxpresso55s69/board.cmake @@ -8,15 +8,19 @@ ## DAP Link implementation in pyocd is underway, ## until then jlink can be used or copy image to storage -if(CONFIG_BOARD_LPCXPRESSO55S69_LPC55S69_CPU0 OR - CONFIG_BOARD_LPCXPRESSO55S69_LPC55S69_CPU0_NS OR - CONFIG_SECOND_CORE_MCUX) +board_runner_args(linkserver "--device=LPC55S69:LPCXpresso55S69") + +if(CONFIG_SECOND_CORE_MCUX) + board_runner_args(linkserver "--core=all") +elseif(CONFIG_BOARD_LPCXPRESSO55S69_LPC55S69_CPU0 OR + CONFIG_BOARD_LPCXPRESSO55S69_LPC55S69_CPU0_NS) board_runner_args(jlink "--device=LPC55S69_M33_0") - board_runner_args(linkserver "--device=LPC55S69:LPCXpresso55S69") board_runner_args(linkserver "--override=/device/memory/0/flash-driver=LPC55xx_S.cfx") board_runner_args(linkserver "--override=/device/memory/0/location=0x10000000") + board_runner_args(linkserver "--core=cm33_core0") elseif(CONFIG_BOARD_LPCXPRESSO55S69_LPC55S69_CPU1) board_runner_args(jlink "--device=LPC55S69_M33_1") + board_runner_args(linkserver "--core=cm33_core1") endif() board_runner_args(pyocd "--target=lpc55s69") @@ -25,6 +29,6 @@ if(CONFIG_BUILD_WITH_TFM) set_property(TARGET runners_yaml_props_target PROPERTY hex_file tfm_merged.hex) endif() +include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) -include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake) diff --git a/boards/nxp/lpcxpresso55s69/doc/index.rst b/boards/nxp/lpcxpresso55s69/doc/index.rst index 85336fa2855..8e1a41e11fc 100644 --- a/boards/nxp/lpcxpresso55s69/doc/index.rst +++ b/boards/nxp/lpcxpresso55s69/doc/index.rst @@ -1,7 +1,4 @@ -.. _lpcxpresso55s69: - -NXP LPCXPRESSO55S69 -################### +.. zephyr:board:: lpcxpresso55s69 Overview ******** @@ -12,10 +9,6 @@ architecture. The board includes a high performance onboard debug probe, audio subsystem, and accelerometer, with several options for adding off-the-shelf add-on boards for networking, sensors, displays, and other interfaces. -.. image:: lpcxpresso55s69.jpg - :align: center - :alt: LPCXPRESSO55S69 - Hardware ******** @@ -280,6 +273,7 @@ Build and flash applications as usual (see :ref:`build_an_application` and Configuring a Debug Probe ========================= +LinkServer is the default runner for this board. A debug probe is used for both flashing and debugging the board. This board is configured by default to use the LPC-Link2 CMSIS-DAP Onboard Debug Probe, however the :ref:`pyocd-debug-host-tools` does not yet support this probe so you @@ -323,7 +317,7 @@ Flashing ======== Here is an example for the :zephyr:code-sample:`hello_world` application. This example uses the -:ref:`jlink-debug-host-tools` as default. +:ref:`linkserver-debug-host-tools` as default. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -335,8 +329,8 @@ see the following message in the terminal: .. code-block:: console - ***** Booting Zephyr OS v1.14.0 ***** - Hello World! lpcxpresso55s69 + ***** Booting Zephyr OS v3.7.0 ***** + Hello World! lpcxpresso55s69/lpc55s69/cpu0 Building and flashing secure/non-secure with Arm |reg| TrustZone |reg| ---------------------------------------------------------------------- diff --git a/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0.dts b/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0.dts index bf583af5342..e87cb04fc79 100644 --- a/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0.dts +++ b/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0.dts @@ -31,6 +31,7 @@ sdhc0 = &sdhc0; accel0 = &mma8652fc; sdhc0 = &sdif; + mcuboot-button0 = &user_button_1; }; chosen { @@ -120,6 +121,7 @@ pinctrl-names = "default"; mmc { compatible = "zephyr,sdmmc-disk"; + disk-name = "SD"; status = "okay"; }; }; diff --git a/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0.yaml b/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0.yaml index ae375cdeb66..bd616045798 100644 --- a/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0.yaml +++ b/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0.yaml @@ -16,10 +16,12 @@ toolchain: - xtools supported: - adc + - arduino_gpio - arduino_i2c - arduino_serial - arduino_spi - counter + - flash - gpio - i2c - i2s diff --git a/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0_defconfig b/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0_defconfig index 873503cfc73..3f6ecf8772c 100644 --- a/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0_defconfig +++ b/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0_defconfig @@ -5,7 +5,6 @@ # CONFIG_GPIO=y -CONFIG_PINCTRL=y CONFIG_RUNTIME_NMI=y diff --git a/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0_ns_defconfig b/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0_ns_defconfig index 98721c751a9..c6da4ff7bad 100644 --- a/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0_ns_defconfig +++ b/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0_ns_defconfig @@ -5,7 +5,6 @@ # CONFIG_GPIO=y -CONFIG_PINCTRL=y CONFIG_RUNTIME_NMI=y diff --git a/boards/nxp/ls1046ardb/doc/index.rst b/boards/nxp/ls1046ardb/doc/index.rst index c6065c4f312..28ad3259ed0 100644 --- a/boards/nxp/ls1046ardb/doc/index.rst +++ b/boards/nxp/ls1046ardb/doc/index.rst @@ -1,7 +1,4 @@ -.. _nxp_ls1046ardb: - -NXP LS1046A RDB -################################# +.. zephyr:board:: ls1046ardb Overview ******** diff --git a/boards/nxp/mimxrt1010_evk/doc/index.rst b/boards/nxp/mimxrt1010_evk/doc/index.rst index 6422927371e..7b2d5d8c5ef 100644 --- a/boards/nxp/mimxrt1010_evk/doc/index.rst +++ b/boards/nxp/mimxrt1010_evk/doc/index.rst @@ -1,7 +1,4 @@ -.. _mimxrt1010_evk: - -NXP MIMXRT1010-EVK -################## +.. zephyr:board:: mimxrt1010_evk Overview ******** @@ -11,10 +8,6 @@ series by providing the lowest-cost LQFP package option, combined with the high performance and ease-of-use known throughout the entire i.MX RT series. This device is fully supported by NXP’s MCUXpresso Software and Tools. -.. image:: mimxrt1010_evk.jpg - :align: center - :alt: MIMXRT1010-EVK - Hardware ******** @@ -69,7 +62,7 @@ Supported Features The mimxrt1010_evk board configuration supports the hardware features listed below. For additional features not yet supported, please also refer to the -:ref:`mimxrt1064_evk` , which is the superset board in NXP's i.MX RT10xx family. +:zephyr:board:`mimxrt1064_evk` , which is the superset board in NXP's i.MX RT10xx family. NXP prioritizes enabling the superset board with NXP's Full Platform Support for Zephyr. Therefore, the mimxrt1064_evk board may have additional features already supported, which can also be re-used on this mimxrt1010_evk board: diff --git a/boards/nxp/mimxrt1010_evk/mimxrt1010_evk.dts b/boards/nxp/mimxrt1010_evk/mimxrt1010_evk.dts index 0b879fb44a2..fa2860dfe9b 100644 --- a/boards/nxp/mimxrt1010_evk/mimxrt1010_evk.dts +++ b/boards/nxp/mimxrt1010_evk/mimxrt1010_evk.dts @@ -18,6 +18,7 @@ aliases { led0 = &green_led; sw0 = &user_button; + mcuboot-button0 = &user_button; }; chosen { @@ -69,7 +70,7 @@ <12 0 &gpio1 15 0>, /* D6 (shared with A4) */ <13 0 &gpio1 16 0>, /* D7 (shared with A5) */ <14 0 &gpio2 2 0>, /* D8 */ - /* R795 not populated, D9 */ + <15 0 &gpio2 3 0>, /* D9 R795 not populated */ <16 0 &gpio1 19 0>, /* D10 (shared with D2) */ <17 0 &gpio1 18 0>, /* D11 */ <18 0 &gpio1 17 0>, /* D12 */ diff --git a/boards/nxp/mimxrt1010_evk/mimxrt1010_evk.yaml b/boards/nxp/mimxrt1010_evk/mimxrt1010_evk.yaml index 5441b064091..f9c8719a8de 100644 --- a/boards/nxp/mimxrt1010_evk/mimxrt1010_evk.yaml +++ b/boards/nxp/mimxrt1010_evk/mimxrt1010_evk.yaml @@ -16,15 +16,16 @@ toolchain: ram: 64 flash: 16384 supported: + - adc - arduino_gpio - arduino_i2c - arduino_serial - arduino_spi - - i2c - counter - dma - - usb_device - - spi - - adc + - flash - gpio + - i2c + - spi + - usb_device vendor: nxp diff --git a/boards/nxp/mimxrt1010_evk/mimxrt1010_evk_defconfig b/boards/nxp/mimxrt1010_evk/mimxrt1010_evk_defconfig index dc0fdc31f2a..aa92258dda9 100644 --- a/boards/nxp/mimxrt1010_evk/mimxrt1010_evk_defconfig +++ b/boards/nxp/mimxrt1010_evk/mimxrt1010_evk_defconfig @@ -10,4 +10,3 @@ CONFIG_SERIAL=y CONFIG_GPIO=y CONFIG_ARM_MPU=y CONFIG_HW_STACK_PROTECTION=y -CONFIG_PINCTRL=y diff --git a/boards/nxp/mimxrt1015_evk/doc/index.rst b/boards/nxp/mimxrt1015_evk/doc/index.rst index 7e22bd4c554..a4bf7bf6756 100644 --- a/boards/nxp/mimxrt1015_evk/doc/index.rst +++ b/boards/nxp/mimxrt1015_evk/doc/index.rst @@ -1,7 +1,4 @@ -.. _mimxrt1015_evk: - -NXP MIMXRT1015-EVK -################## +.. zephyr:board:: mimxrt1015_evk Overview ******** @@ -11,10 +8,6 @@ high-performance feature set in low-cost LQFP packages, further simplifying board design and layout for customers. The i.MX RT1015 runs on the Arm® Cortex®-M7 core at 500 MHz. -.. image:: mimxrt1015_evk.jpg - :align: center - :alt: MIMXRT1015-EVK - Hardware ******** @@ -69,7 +62,7 @@ Supported Features The mimxrt1015_evk board configuration supports the hardware features listed below. For additional features not yet supported, please also refer to the -:ref:`mimxrt1064_evk` , which is the superset board in NXP's i.MX RT10xx family. +:zephyr:board:`mimxrt1064_evk` , which is the superset board in NXP's i.MX RT10xx family. NXP prioritizes enabling the superset board with NXP's Full Platform Support for Zephyr. Therefore, the mimxrt1064_evk board may have additional features already supported, which can also be re-used on this mimxrt1015_evk board: diff --git a/boards/nxp/mimxrt1015_evk/mimxrt1015_evk.dts b/boards/nxp/mimxrt1015_evk/mimxrt1015_evk.dts index 10959b0edae..319d1ddb320 100644 --- a/boards/nxp/mimxrt1015_evk/mimxrt1015_evk.dts +++ b/boards/nxp/mimxrt1015_evk/mimxrt1015_evk.dts @@ -17,6 +17,7 @@ aliases { led0 = &green_led; sw0 = &user_button; + mcuboot-button0 = &user_button; }; chosen { diff --git a/boards/nxp/mimxrt1015_evk/mimxrt1015_evk.yaml b/boards/nxp/mimxrt1015_evk/mimxrt1015_evk.yaml index b3c0b6d4d9c..80afd63da22 100644 --- a/boards/nxp/mimxrt1015_evk/mimxrt1015_evk.yaml +++ b/boards/nxp/mimxrt1015_evk/mimxrt1015_evk.yaml @@ -15,13 +15,14 @@ toolchain: ram: 32 flash: 16384 supported: + - adc - arduino_gpio - arduino_serial - counter - dma + - flash - gpio - i2c - - usb_device - spi - - adc + - usb_device vendor: nxp diff --git a/boards/nxp/mimxrt1015_evk/mimxrt1015_evk_defconfig b/boards/nxp/mimxrt1015_evk/mimxrt1015_evk_defconfig index dc0fdc31f2a..aa92258dda9 100644 --- a/boards/nxp/mimxrt1015_evk/mimxrt1015_evk_defconfig +++ b/boards/nxp/mimxrt1015_evk/mimxrt1015_evk_defconfig @@ -10,4 +10,3 @@ CONFIG_SERIAL=y CONFIG_GPIO=y CONFIG_ARM_MPU=y CONFIG_HW_STACK_PROTECTION=y -CONFIG_PINCTRL=y diff --git a/boards/nxp/mimxrt1020_evk/doc/index.rst b/boards/nxp/mimxrt1020_evk/doc/index.rst index 0057dcd58ab..88e62be8b9e 100644 --- a/boards/nxp/mimxrt1020_evk/doc/index.rst +++ b/boards/nxp/mimxrt1020_evk/doc/index.rst @@ -1,7 +1,4 @@ -.. _mimxrt1020_evk: - -NXP MIMXRT1020-EVK -################## +.. zephyr:board:: mimxrt1020_evk Overview ******** @@ -11,10 +8,6 @@ high-performance feature set in low-cost LQFP packages, further simplifying board design and layout for customers. The i.MX RT1020 runs on the Arm® Cortex®-M7 core at 500 MHz. -.. image:: mimxrt1020_evk.jpg - :align: center - :alt: MIMXRT1020-EVK - Hardware ******** @@ -81,7 +74,7 @@ Supported Features The mimxrt1020_evk board configuration supports the hardware features listed below. For additional features not yet supported, please also refer to the -:ref:`mimxrt1064_evk` , which is the superset board in NXP's i.MX RT10xx family. +:zephyr:board:`mimxrt1064_evk` , which is the superset board in NXP's i.MX RT10xx family. NXP prioritizes enabling the superset board with NXP's Full Platform Support for Zephyr. Therefore, the mimxrt1064_evk board may have additional features already supported, which can also be re-used on this mimxrt1020_evk board: diff --git a/boards/nxp/mimxrt1020_evk/mimxrt1020_evk.dts b/boards/nxp/mimxrt1020_evk/mimxrt1020_evk.dts index 34997b73f1f..6c3d096ff8e 100644 --- a/boards/nxp/mimxrt1020_evk/mimxrt1020_evk.dts +++ b/boards/nxp/mimxrt1020_evk/mimxrt1020_evk.dts @@ -18,11 +18,12 @@ led0 = &green_led; sw0 = &user_button; sdhc0 = &usdhc1; + mcuboot-button0 = &user_button; }; chosen { - zephyr,flash-controller = &is25wp064; - zephyr,flash = &is25wp064; + zephyr,flash-controller = &is25lp064; + zephyr,flash = &is25lp064; zephyr,code-partition = &slot0_partition; zephyr,uart-mcumgr = &lpuart1; zephyr,sram = &sdram0; @@ -94,11 +95,11 @@ arduino_serial: &lpuart2 { &flexspi { status = "okay"; reg = <0x402a8000 0x4000>, <0x60000000 DT_SIZE_M(8)>; - is25wp064: is25wp064@0 { + is25lp064: is25lp064@0 { compatible = "nxp,imx-flexspi-nor"; size = <67108864>; reg = <0>; - spi-max-frequency = <133000000>; + spi-max-frequency = <104000000>; status = "okay"; jedec-id = [9d 70 17]; erase-block-size = <4096>; @@ -205,6 +206,7 @@ zephyr_udc0: &usb1 { pwr-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>; sdmmc { compatible = "zephyr,sdmmc-disk"; + disk-name = "SD"; status = "okay"; }; }; diff --git a/boards/nxp/mimxrt1020_evk/mimxrt1020_evk.yaml b/boards/nxp/mimxrt1020_evk/mimxrt1020_evk.yaml index eebbc18ba84..88c5629fa0c 100644 --- a/boards/nxp/mimxrt1020_evk/mimxrt1020_evk.yaml +++ b/boards/nxp/mimxrt1020_evk/mimxrt1020_evk.yaml @@ -15,15 +15,16 @@ toolchain: ram: 32768 flash: 8192 supported: + - adc - arduino_gpio - arduino_serial - counter - dma + - flash - gpio - i2c - netif:eth + - sdhc - spi - usb_device - - adc - - sdhc vendor: nxp diff --git a/boards/nxp/mimxrt1020_evk/mimxrt1020_evk_defconfig b/boards/nxp/mimxrt1020_evk/mimxrt1020_evk_defconfig index 8af2d462809..29f9a37ea90 100644 --- a/boards/nxp/mimxrt1020_evk/mimxrt1020_evk_defconfig +++ b/boards/nxp/mimxrt1020_evk/mimxrt1020_evk_defconfig @@ -10,4 +10,3 @@ CONFIG_SERIAL=y CONFIG_GPIO=y CONFIG_ARM_MPU=y CONFIG_HW_STACK_PROTECTION=y -CONFIG_PINCTRL=y diff --git a/boards/nxp/mimxrt1024_evk/board.cmake b/boards/nxp/mimxrt1024_evk/board.cmake index 78b82131274..b0b8952cacd 100644 --- a/boards/nxp/mimxrt1024_evk/board.cmake +++ b/boards/nxp/mimxrt1024_evk/board.cmake @@ -1,11 +1,14 @@ # -# Copyright (c) 2020, NXP +# Copyright (c) 2020, 2024 NXP # # SPDX-License-Identifier: Apache-2.0 # board_runner_args(pyocd "--target=mimxrt1024") board_runner_args(jlink "--device=MIMXRT1024xxx5A") +# MIMXRT1024xxxxx MIMXRT1024-EVK cm7 +board_runner_args(linkserver "--device=MIMXRT1024xxxxx:MIMXRT1024-EVK") +include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/nxp/mimxrt1024_evk/doc/index.rst b/boards/nxp/mimxrt1024_evk/doc/index.rst index e451a027432..62a5a987128 100644 --- a/boards/nxp/mimxrt1024_evk/doc/index.rst +++ b/boards/nxp/mimxrt1024_evk/doc/index.rst @@ -1,7 +1,4 @@ -.. _mimxrt1024_evk: - -NXP MIMXRT1024-EVK -################## +.. zephyr:board:: mimxrt1024_evk Overview ******** @@ -11,10 +8,6 @@ high-performance feature set in low-cost LQFP packages, further simplifying board design and layout for customers. The i.MX RT1024 runs on the Arm® Cortex®-M7 core at 500 MHz. -.. image:: mimxrt1024_evk.jpg - :align: center - :alt: MIMXRT1024-EVK - Hardware ******** @@ -82,7 +75,7 @@ Supported Features The mimxrt1024_evk board configuration supports the hardware features listed below. For additional features not yet supported, please also refer to the -:ref:`mimxrt1064_evk` , which is the superset board in NXP's i.MX RT10xx family. +:zephyr:board:`mimxrt1064_evk` , which is the superset board in NXP's i.MX RT10xx family. NXP prioritizes enabling the superset board with NXP's Full Platform Support for Zephyr. Therefore, the mimxrt1064_evk board may have additional features already supported, which can also be re-used on this mimxrt1024_evk board: @@ -206,11 +199,12 @@ remaining are not used. Programming and Debugging ************************* -This board supports 2 debug host tools. Please install your preferred host +This board supports 3 debug host tools. Please install your preferred host tool, then follow the instructions in `Configuring a Debug Probe`_ to configure the board appropriately. -* :ref:`jlink-debug-host-tools` (Default, Supported by NXP) +* :ref:`linkserver-debug-host-tools` (Default, Supported by NXP) +* :ref:`jlink-debug-host-tools` (Supported by NXP) * :ref:`pyocd-debug-host-tools` (Not supported by NXP) Configuring a Debug Probe diff --git a/boards/nxp/mimxrt1024_evk/mimxrt1024_evk.dts b/boards/nxp/mimxrt1024_evk/mimxrt1024_evk.dts index 4a1811afa41..bc20298898a 100644 --- a/boards/nxp/mimxrt1024_evk/mimxrt1024_evk.dts +++ b/boards/nxp/mimxrt1024_evk/mimxrt1024_evk.dts @@ -21,6 +21,7 @@ magn0 = &fxos8700; accel0 = &fxos8700; sdhc0 = &usdhc1; + mcuboot-button0 = &user_button; }; chosen { @@ -240,6 +241,7 @@ zephyr_udc0: &usb1 { no-1-8-v; sdmmc { compatible = "zephyr,sdmmc-disk"; + disk-name = "SD"; status = "okay"; }; }; diff --git a/boards/nxp/mimxrt1024_evk/mimxrt1024_evk.yaml b/boards/nxp/mimxrt1024_evk/mimxrt1024_evk.yaml index ca12b2517c0..67fad31a54d 100644 --- a/boards/nxp/mimxrt1024_evk/mimxrt1024_evk.yaml +++ b/boards/nxp/mimxrt1024_evk/mimxrt1024_evk.yaml @@ -15,17 +15,18 @@ toolchain: ram: 32768 flash: 4096 supported: + - adc - arduino_gpio - arduino_serial - can - dma + - flash + - gpio - hwinfo - netif:eth - - watchdog - - spi + - pwm - sdhc - - adc + - spi - usb_device - - pwm - - gpio + - watchdog vendor: nxp diff --git a/boards/nxp/mimxrt1024_evk/mimxrt1024_evk_defconfig b/boards/nxp/mimxrt1024_evk/mimxrt1024_evk_defconfig index 591d8071552..d24c6ad60d5 100644 --- a/boards/nxp/mimxrt1024_evk/mimxrt1024_evk_defconfig +++ b/boards/nxp/mimxrt1024_evk/mimxrt1024_evk_defconfig @@ -10,4 +10,3 @@ CONFIG_SERIAL=y CONFIG_GPIO=y CONFIG_ARM_MPU=y CONFIG_HW_STACK_PROTECTION=y -CONFIG_PINCTRL=y diff --git a/boards/nxp/mimxrt1040_evk/doc/index.rst b/boards/nxp/mimxrt1040_evk/doc/index.rst index fffd3873fa5..8f9f4edf8da 100644 --- a/boards/nxp/mimxrt1040_evk/doc/index.rst +++ b/boards/nxp/mimxrt1040_evk/doc/index.rst @@ -1,7 +1,4 @@ -.. _mimxrt1040_evk: - -NXP MIMXRT1040-EVK -################## +.. zephyr:board:: mimxrt1040_evk Overview ******** @@ -12,10 +9,6 @@ extended temperature range up to 125° C. The i.MX RT1040 MCU has a compact 2-layer PCB design. The i.MX RT1040 MCUs run on the Arm® Cortex®-M7 core at 600 MHz. -.. image:: mimxrt1040_evk.jpg - :align: center - :alt: MIMXRT1040-EVK - Hardware ******** @@ -91,7 +84,7 @@ Supported Features The mimxrt1040_evk board configuration supports the hardware features listed below. For additional features not yet supported, please also refer to the -:ref:`mimxrt1064_evk` , which is the superset board in NXP's i.MX RT10xx family. +:zephyr:board:`mimxrt1064_evk` , which is the superset board in NXP's i.MX RT10xx family. NXP prioritizes enabling the superset board with NXP's Full Platform Support for Zephyr. Therefore, the mimxrt1064_evk board may have additional features already supported, which can also be re-used on this mimxrt1040_evk board: @@ -118,6 +111,8 @@ already supported, which can also be re-used on this mimxrt1040_evk board: +-----------+------------+-------------------------------------+ | I2C | on-chip | i2c | +-----------+------------+-------------------------------------+ +| GPT | on-chip | gpt | ++-----------+------------+-------------------------------------+ | DISPLAY | on-chip | eLCDIF. Tested with | | | | :ref:`rk043fn02h_ct`, and | | | | :ref:`rk043fn66hs_ctg` shields | diff --git a/boards/nxp/mimxrt1040_evk/mimxrt1040_evk.dts b/boards/nxp/mimxrt1040_evk/mimxrt1040_evk.dts index 37467121ca3..d5a31991ab1 100644 --- a/boards/nxp/mimxrt1040_evk/mimxrt1040_evk.dts +++ b/boards/nxp/mimxrt1040_evk/mimxrt1040_evk.dts @@ -19,6 +19,7 @@ sw0 = &user_button; pwm-0 = &flexpwm1_pwm3; accel0 = &fxls8974; + mcuboot-button0 = &user_button; }; chosen { diff --git a/boards/nxp/mimxrt1040_evk/mimxrt1040_evk.yaml b/boards/nxp/mimxrt1040_evk/mimxrt1040_evk.yaml index 415ca704d60..3d5aeefadcd 100644 --- a/boards/nxp/mimxrt1040_evk/mimxrt1040_evk.yaml +++ b/boards/nxp/mimxrt1040_evk/mimxrt1040_evk.yaml @@ -15,10 +15,12 @@ toolchain: ram: 32768 flash: 8192 supported: + - adc - arduino_gpio + - counter + - flash - gpio + - i2c - pwm - - adc - spi - - i2c vendor: nxp diff --git a/boards/nxp/mimxrt1040_evk/mimxrt1040_evk_defconfig b/boards/nxp/mimxrt1040_evk/mimxrt1040_evk_defconfig index 5d1b150c729..48d8cb6bc73 100644 --- a/boards/nxp/mimxrt1040_evk/mimxrt1040_evk_defconfig +++ b/boards/nxp/mimxrt1040_evk/mimxrt1040_evk_defconfig @@ -10,4 +10,3 @@ CONFIG_SERIAL=y CONFIG_GPIO=y CONFIG_ARM_MPU=y CONFIG_HW_STACK_PROTECTION=y -CONFIG_PINCTRL=y diff --git a/boards/nxp/mimxrt1050_evk/Kconfig.defconfig b/boards/nxp/mimxrt1050_evk/Kconfig.defconfig index 56603850195..90fc7a76598 100644 --- a/boards/nxp/mimxrt1050_evk/Kconfig.defconfig +++ b/boards/nxp/mimxrt1050_evk/Kconfig.defconfig @@ -10,6 +10,7 @@ config DEVICE_CONFIGURATION_DATA config NXP_IMX_EXTERNAL_SDRAM default y + if NETWORKING config NET_L2_ETHERNET diff --git a/boards/nxp/mimxrt1050_evk/board.cmake b/boards/nxp/mimxrt1050_evk/board.cmake index c53e6474ca1..321eeee8134 100644 --- a/boards/nxp/mimxrt1050_evk/board.cmake +++ b/boards/nxp/mimxrt1050_evk/board.cmake @@ -3,10 +3,17 @@ # # SPDX-License-Identifier: Apache-2.0 # + +if(NOT ("${BOARD_QUALIFIERS}" MATCHES "qspi" + OR "${BOARD_QUALIFIERS}" MATCHES "hyperflash")) + message(FATAL_ERROR "Please specify a board flash variant for the mimxrt1050_evk:\n" + "mimxrt1050_evk/mimxrt1052/qspi or mimxrt1050_evk/mimxrt1052/hyperflash\n") +endif() + board_runner_args(jlink "--device=MCIMXRT1052") board_runner_args(linkserver "--device=MIMXRT1052xxxxB:EVKB-IMXRT1050") -if("${BOARD_REVISION}" STREQUAL "qspi") +if("${BOARD_QUALIFIERS}" MATCHES "qspi") board_runner_args(jlink "--loader=BankAddr=0x60000000&Loader=QSPI") board_runner_args(pyocd "--target=mimxrt1050_quadspi") board_runner_args(linkserver "--override=/device/memory/3/flash-driver=MIMXRT1050_SFDP_QSPI.cfx") diff --git a/boards/nxp/mimxrt1050_evk/board.yml b/boards/nxp/mimxrt1050_evk/board.yml index 48b8680e4b5..0d06dbd8d1a 100644 --- a/boards/nxp/mimxrt1050_evk/board.yml +++ b/boards/nxp/mimxrt1050_evk/board.yml @@ -4,9 +4,6 @@ board: vendor: nxp socs: - name: mimxrt1052 - revision: - format: "custom" - default: "hyperflash" - revisions: - - name: "hyperflash" - - name: "qspi" + variants: + - name: hyperflash + - name: qspi diff --git a/boards/nxp/mimxrt1050_evk/doc/index.rst b/boards/nxp/mimxrt1050_evk/doc/index.rst index 19deec55f09..379498dd33b 100644 --- a/boards/nxp/mimxrt1050_evk/doc/index.rst +++ b/boards/nxp/mimxrt1050_evk/doc/index.rst @@ -1,7 +1,4 @@ -.. _mimxrt1050_evk: - -NXP MIMXRT1050-EVK -################## +.. zephyr:board:: mimxrt1050_evk Overview ******** @@ -17,10 +14,6 @@ and camera sensors. As with other i.MX processors, i.MX RT1050 also has rich audio and video features, including LCD display, basic 2D graphics, camera interface, SPDIF, and I2S audio interface. -.. image:: mimxrt1050_evk.jpg - :align: center - :alt: MIMXRT1050-EVK - Hardware ******** @@ -104,7 +97,7 @@ Supported Features The mimxrt1050_evk board configuration supports the hardware features listed below. For additional features not yet supported, please also refer to the -:ref:`mimxrt1064_evk` , which is the superset board in NXP's i.MX RT10xx family. +:zephyr:board:`mimxrt1064_evk` , which is the superset board in NXP's i.MX RT10xx family. NXP prioritizes enabling the superset board with NXP's Full Platform Support for Zephyr. Therefore, the mimxrt1064_evk board may have additional features already supported, which can also be re-used on this mimxrt1050_evk board: @@ -145,7 +138,7 @@ already supported, which can also be re-used on this mimxrt1050_evk board: +-----------+------------+-------------------------------------+ The default configuration can be found in -:zephyr_file:`boards/nxp/mimxrt1050_evk/mimxrt1050_evk_defconfig` +:zephyr_file:`boards/nxp/mimxrt1050_evk/mimxrt1050_evk_hyperflash_defconfig` Other hardware features are not currently supported by the port. @@ -305,6 +298,17 @@ The RT1050 SoC has two USB OTG (USBOTG) controllers that supports both device and host functions through its micro USB connectors. Only USB device function is supported in Zephyr at the moment. +Board Targets +************* + +This board has two variants that can be targeted, +depending on which flash to set as ``zephyr,flash``: + +* ``mimxrt1050_evk/mimxrt1052/hyperflash`` is the default variant for the out of box + setup of the board using hyperflash. +* ``mimxrt1050_evk/mimxrt1052/qspi`` is for a board that has been reworked to use the + qspi flash instead of hyperflash. + Programming and Debugging ************************* @@ -371,7 +375,7 @@ Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world - :board: mimxrt1050_evk + :board: mimxrt1050_evk//hyperflash :goals: flash Open a serial terminal, reset the board (press the SW4 button), and you should @@ -380,7 +384,7 @@ see the following message in the terminal: .. code-block:: console ***** Booting Zephyr OS v1.14.0-rc1 ***** - Hello World! mimxrt1050_evk + Hello World! mimxrt1050_evk//hyperflash Debugging ========= @@ -389,7 +393,7 @@ Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world - :board: mimxrt1050_evk + :board: mimxrt1050_evk//hyperflash :goals: debug Open a serial terminal, step through the application in your debugger, and you @@ -398,7 +402,7 @@ should see the following message in the terminal: .. code-block:: console ***** Booting Zephyr OS v1.14.0-rc1 ***** - Hello World! mimxrt1050_evk + Hello World! mimxrt1050_evk//hyperflash Troubleshooting =============== diff --git a/boards/nxp/mimxrt1050_evk/mimxrt1050_evk.dts b/boards/nxp/mimxrt1050_evk/mimxrt1050_evk.dts deleted file mode 100644 index 7edf96e9517..00000000000 --- a/boards/nxp/mimxrt1050_evk/mimxrt1050_evk.dts +++ /dev/null @@ -1,249 +0,0 @@ -/* - * Copyright (c) 2017, NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include -#include "mimxrt1050_evk-pinctrl.dtsi" -#include - -/ { - model = "NXP MIMXRT1050-EVK board"; - compatible = "nxp,mimxrt1052"; - - aliases { - led0 = &green_led; - sw0 = &user_button; - watchdog0 = &wdog0; - magn0 = &fxos8700; - accel0 = &fxos8700; - sdhc0 = &usdhc1; - }; - - chosen { - zephyr,sram = &sdram0; - zephyr,itcm = &itcm; - zephyr,dtcm = &dtcm; - zephyr,uart-mcumgr = &lpuart1; - zephyr,console = &lpuart1; - zephyr,shell-uart = &lpuart1; - }; - - sdram0: memory@80000000 { - /* Micron MT48LC16M16A2B4-6AIT:G */ - device_type = "memory"; - reg = <0x80000000 DT_SIZE_M(32)>; - }; - - /* - * This node describes the GPIO pins of the parallel FPC interface, - * This interface is standard to several NXP EVKs, and is used with - * several parallel LCD displays (available as zephyr shields) - */ - nxp_parallel_lcd_connector: parallel-connector { - compatible = "nxp,parallel-lcd-connector"; - #gpio-cells = <2>; - gpio-map-mask = <0xffffffff 0xffffffc0>; - gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpio2 31 0>; /* Pin 1, BL+ */ - }; - - /* - * This node describes the GPIO pins of the I2C display FPC interface, - * This interface is standard to several NXP EVKs, and is used with - * several parallel LCD displays (available as zephyr shields) - */ - nxp_i2c_touch_fpc: i2c-touch-connector { - compatible = "nxp,i2c-tsc-fpc"; - #gpio-cells = <2>; - gpio-map-mask = <0xffffffff 0xffffffc0>; - gpio-map-pass-thru = <0 0x3f>; - gpio-map = <1 0 &gpio1 2 0>, /* Pin 2, LCD touch RST */ - <2 0 &gpio1 11 0>; /* Pin 3, LCD touch INT */ - }; - - leds { - compatible = "gpio-leds"; - green_led: led_0 { - gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; - label = "User LD1"; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - user_button: button_0 { - label = "User SW8"; - gpios = <&gpio5 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - zephyr,code = ; - }; - }; - - arduino_header: connector { - compatible = "arduino-header-r3"; - #gpio-cells = <2>; - gpio-map-mask = <0xffffffff 0xffffffc0>; - gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpio1 26 0>, /* A0 */ - <1 0 &gpio1 27 0>, /* A1 */ - <2 0 &gpio1 20 0>, /* A2 */ - <3 0 &gpio1 21 0>, /* A3 */ - <4 0 &gpio1 17 0>, /* A4 */ - <5 0 &gpio1 16 0>, /* A5 */ - <6 0 &gpio1 23 0>, /* D0 */ - <7 0 &gpio1 22 0>, /* D1 */ - <8 0 &gpio1 11 0>, /* D2 */ - <9 0 &gpio1 24 0>, /* D3 */ - <10 0 &gpio1 9 0>, /* D4 */ - <11 0 &gpio1 10 0>, /* D5 */ - <12 0 &gpio1 18 0>, /* D6 */ - <13 0 &gpio1 19 0>, /* D7 */ - <14 0 &gpio1 3 0>, /* D8 */ - <15 0 &gpio1 2 0>, /* D9 */ - <16 0 &gpio3 13 0>, /* D10 */ - <17 0 &gpio3 14 0>, /* D11 */ - <18 0 &gpio3 15 0>, /* D12 */ - <19 0 &gpio3 12 0>, /* D13 */ - <20 0 &gpio1 1 0>, /* D14 */ - <21 0 &gpio1 0 0>; /* D15 */ - }; -}; - -arduino_serial: &lpuart3 { - pinctrl-0 = <&pinmux_lpuart3>; - pinctrl-1 = <&pinmux_lpuart3_sleep>; - pinctrl-names = "default", "sleep"; -}; - -&adc1 { - status = "okay"; - pinctrl-0 = <&pinmux_adc1>; - pinctrl-names = "default"; -}; - -nxp_touch_i2c: &lpi2c1 {}; - -zephyr_lcdif: &lcdif { - pinctrl-0 = <&pinmux_lcdif>; - pinctrl-names = "default"; -}; - -&lpi2c1 { - status = "okay"; - pinctrl-0 = <&pinmux_lpi2c1>; - pinctrl-names = "default"; - - fxos8700: fxos8700@1f { - compatible = "nxp,fxos8700"; - reg = <0x1f>; - - /* Two zero ohm resistors (R263 and R264) isolate sensor - * interrupt gpios from the soc and are unpopulated by default. - * Note that if you populate them, they conflict with LCD and - * Ethernet interrupt gpios. - */ - int1-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; - int2-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; - }; -}; - -&lpuart1 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&pinmux_lpuart1>; - pinctrl-1 = <&pinmux_lpuart1_sleep>; - pinctrl-names = "default", "sleep"; -}; - -&lpspi1 { - status = "okay"; - /* DMA channels 0 and 1, muxed to LPSPI1 RX and TX */ - dmas = <&edma0 0 13>, <&edma0 1 14>; - dma-names = "rx", "tx"; - pinctrl-0 = <&pinmux_lpspi1>; - pinctrl-names = "default"; -}; - -&lpspi3 { - status = "okay"; - /* DMA channels 2 and 3, muxed to LPSPI3 RX and TX */ - dmas = <&edma0 2 15>, <&edma0 3 16>; - dma-names = "rx", "tx"; - pinctrl-0 = <&pinmux_lpspi3>; - pinctrl-names = "default"; -}; - -&enet_mac { - status = "okay"; - pinctrl-0 = <&pinmux_enet>; - pinctrl-names = "default"; - phy-handle = <&phy>; - zephyr,random-mac-address; - phy-connection-type = "rmii"; -}; - -&enet_mdio { - status = "okay"; - pinctrl-0 = <&pinmux_enet_mdio>; - pinctrl-names = "default"; - phy: phy@0 { - compatible = "microchip,ksz8081"; - reg = <0>; - status = "okay"; - reset-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; - int-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; - microchip,interface-type = "rmii"; - }; -}; - -&enet_ptp_clock { - status = "okay"; - pinctrl-0 = <&pinmux_ptp>; - pinctrl-names = "default"; -}; - -zephyr_udc0: &usb1 { - status = "okay"; -}; - -&usdhc1 { - status = "okay"; - pwr-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; - cd-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pinmux_usdhc1>; - pinctrl-1 = <&pinmux_usdhc1_slow>; - pinctrl-2 = <&pinmux_usdhc1_med>; - pinctrl-3 = <&pinmux_usdhc1_fast>; - pinctrl-names = "default", "slow", "med", "fast"; - sdmmc { - compatible = "zephyr,sdmmc-disk"; - status = "okay"; - }; -}; - -&wdog0 { - status = "okay"; -}; - -&edma0 { - status = "okay"; -}; - -&pxp { - status = "okay"; -}; - -/* GPT and Systick are enabled. If power management is enabled, the GPT - * timer will be used instead of systick, as allows the core clock to - * be gated. - */ -&gpt_hw_timer { - status = "okay"; -}; - -&systick { - status = "okay"; -}; diff --git a/boards/nxp/mimxrt1050_evk/mimxrt1050_evk.dtsi b/boards/nxp/mimxrt1050_evk/mimxrt1050_evk.dtsi new file mode 100644 index 00000000000..3879b04cb50 --- /dev/null +++ b/boards/nxp/mimxrt1050_evk/mimxrt1050_evk.dtsi @@ -0,0 +1,251 @@ +/* + * Copyright (c) 2017, NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "mimxrt1050_evk-pinctrl.dtsi" +#include + +/ { + model = "NXP MIMXRT1050-EVK board"; + compatible = "nxp,mimxrt1052"; + + aliases { + led0 = &green_led; + sw0 = &user_button; + watchdog0 = &wdog0; + magn0 = &fxos8700; + accel0 = &fxos8700; + sdhc0 = &usdhc1; + mcuboot-button0 = &user_button; + }; + + chosen { + zephyr,sram = &sdram0; + zephyr,itcm = &itcm; + zephyr,dtcm = &dtcm; + zephyr,uart-mcumgr = &lpuart1; + zephyr,console = &lpuart1; + zephyr,shell-uart = &lpuart1; + }; + + sdram0: memory@80000000 { + /* Micron MT48LC16M16A2B4-6AIT:G */ + device_type = "memory"; + reg = <0x80000000 DT_SIZE_M(32)>; + }; + + /* + * This node describes the GPIO pins of the parallel FPC interface, + * This interface is standard to several NXP EVKs, and is used with + * several parallel LCD displays (available as zephyr shields) + */ + nxp_parallel_lcd_connector: parallel-connector { + compatible = "nxp,parallel-lcd-connector"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpio2 31 0>; /* Pin 1, BL+ */ + }; + + /* + * This node describes the GPIO pins of the I2C display FPC interface, + * This interface is standard to several NXP EVKs, and is used with + * several parallel LCD displays (available as zephyr shields) + */ + nxp_i2c_touch_fpc: i2c-touch-connector { + compatible = "nxp,i2c-tsc-fpc"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <1 0 &gpio1 2 0>, /* Pin 2, LCD touch RST */ + <2 0 &gpio1 11 0>; /* Pin 3, LCD touch INT */ + }; + + leds { + compatible = "gpio-leds"; + green_led: led_0 { + gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; + label = "User LD1"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + user_button: button_0 { + label = "User SW8"; + gpios = <&gpio5 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + zephyr,code = ; + }; + }; + + arduino_header: connector { + compatible = "arduino-header-r3"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpio1 26 0>, /* A0 */ + <1 0 &gpio1 27 0>, /* A1 */ + <2 0 &gpio1 20 0>, /* A2 */ + <3 0 &gpio1 21 0>, /* A3 */ + <4 0 &gpio1 17 0>, /* A4 */ + <5 0 &gpio1 16 0>, /* A5 */ + <6 0 &gpio1 23 0>, /* D0 */ + <7 0 &gpio1 22 0>, /* D1 */ + <8 0 &gpio1 11 0>, /* D2 */ + <9 0 &gpio1 24 0>, /* D3 */ + <10 0 &gpio1 9 0>, /* D4 */ + <11 0 &gpio1 10 0>, /* D5 */ + <12 0 &gpio1 18 0>, /* D6 */ + <13 0 &gpio1 19 0>, /* D7 */ + <14 0 &gpio1 3 0>, /* D8 */ + <15 0 &gpio1 2 0>, /* D9 */ + <16 0 &gpio3 13 0>, /* D10 */ + <17 0 &gpio3 14 0>, /* D11 */ + <18 0 &gpio3 15 0>, /* D12 */ + <19 0 &gpio3 12 0>, /* D13 */ + <20 0 &gpio1 1 0>, /* D14 */ + <21 0 &gpio1 0 0>; /* D15 */ + }; +}; + +arduino_serial: &lpuart3 { + pinctrl-0 = <&pinmux_lpuart3>; + pinctrl-1 = <&pinmux_lpuart3_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&adc1 { + status = "okay"; + pinctrl-0 = <&pinmux_adc1>; + pinctrl-names = "default"; +}; + +nxp_touch_i2c: &lpi2c1 {}; + +zephyr_lcdif: &lcdif { + pinctrl-0 = <&pinmux_lcdif>; + pinctrl-names = "default"; +}; + +&lpi2c1 { + status = "okay"; + pinctrl-0 = <&pinmux_lpi2c1>; + pinctrl-names = "default"; + + fxos8700: fxos8700@1f { + compatible = "nxp,fxos8700"; + reg = <0x1f>; + + /* Two zero ohm resistors (R263 and R264) isolate sensor + * interrupt gpios from the soc and are unpopulated by default. + * Note that if you populate them, they conflict with LCD and + * Ethernet interrupt gpios. + */ + int1-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; + int2-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; + }; +}; + +&lpuart1 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&pinmux_lpuart1>; + pinctrl-1 = <&pinmux_lpuart1_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&lpspi1 { + status = "okay"; + /* DMA channels 0 and 1, muxed to LPSPI1 RX and TX */ + dmas = <&edma0 0 13>, <&edma0 1 14>; + dma-names = "rx", "tx"; + pinctrl-0 = <&pinmux_lpspi1>; + pinctrl-names = "default"; +}; + +&lpspi3 { + status = "okay"; + /* DMA channels 2 and 3, muxed to LPSPI3 RX and TX */ + dmas = <&edma0 2 15>, <&edma0 3 16>; + dma-names = "rx", "tx"; + pinctrl-0 = <&pinmux_lpspi3>; + pinctrl-names = "default"; +}; + +&enet_mac { + status = "okay"; + pinctrl-0 = <&pinmux_enet>; + pinctrl-names = "default"; + phy-handle = <&phy>; + zephyr,random-mac-address; + phy-connection-type = "rmii"; +}; + +&enet_mdio { + status = "okay"; + pinctrl-0 = <&pinmux_enet_mdio>; + pinctrl-names = "default"; + phy: phy@0 { + compatible = "microchip,ksz8081"; + reg = <0>; + status = "okay"; + reset-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; + int-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; + microchip,interface-type = "rmii"; + }; +}; + +&enet_ptp_clock { + status = "okay"; + pinctrl-0 = <&pinmux_ptp>; + pinctrl-names = "default"; +}; + +zephyr_udc0: &usb1 { + status = "okay"; +}; + +&usdhc1 { + status = "okay"; + pwr-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; + cd-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pinmux_usdhc1>; + pinctrl-1 = <&pinmux_usdhc1_slow>; + pinctrl-2 = <&pinmux_usdhc1_med>; + pinctrl-3 = <&pinmux_usdhc1_fast>; + pinctrl-names = "default", "slow", "med", "fast"; + sdmmc { + compatible = "zephyr,sdmmc-disk"; + disk-name = "SD"; + status = "okay"; + }; +}; + +&wdog0 { + status = "okay"; +}; + +&edma0 { + status = "okay"; +}; + +&pxp { + status = "okay"; +}; + +/* GPT and Systick are enabled. If power management is enabled, the GPT + * timer will be used instead of systick, as allows the core clock to + * be gated. + */ +&gpt_hw_timer { + status = "okay"; +}; + +&systick { + status = "okay"; +}; diff --git a/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_defconfig b/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_defconfig deleted file mode 100644 index e4f0cbedcc2..00000000000 --- a/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_defconfig +++ /dev/null @@ -1,13 +0,0 @@ -# -# Copyright (c) 2017, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_GPIO=y -CONFIG_ARM_MPU=y -CONFIG_HW_STACK_PROTECTION=y -CONFIG_PINCTRL=y diff --git a/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_hyperflash_defconfig b/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_hyperflash_defconfig new file mode 100644 index 00000000000..a9e39fa1d73 --- /dev/null +++ b/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_hyperflash_defconfig @@ -0,0 +1,12 @@ +# +# Copyright (c) 2017, NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_GPIO=y +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y diff --git a/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_hyperflash.dts b/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_hyperflash.dts new file mode 100644 index 00000000000..e0aa389326a --- /dev/null +++ b/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_hyperflash.dts @@ -0,0 +1,72 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "mimxrt1050_evk.dtsi" + +/ { + chosen { + zephyr,flash-controller = &s26ks512s0; + zephyr,flash = &s26ks512s0; + zephyr,code-partition = &slot0_partition; + }; +}; + +&flexspi { + status = "okay"; + ahb-prefetch; + ahb-read-addr-opt; + pinctrl-0 = <&pinmux_flexspi1>; + pinctrl-names = "default"; + ahb-bufferable; + ahb-cacheable; + sck-differential-clock; + combination-mode; + rx-clock-source = <3>; + reg = <0x402a8000 0x4000>, <0x60000000 DT_SIZE_M(64)>; + s26ks512s0: s26ks512s@0 { + compatible = "nxp,imx-flexspi-hyperflash"; + size = ; + reg = <0>; + spi-max-frequency = <166000000>; + word-addressable; + cs-interval-unit = <1>; + cs-interval = <2>; + cs-hold-time = <0>; + cs-setup-time = <3>; + data-valid-time = <1>; + column-space = <3>; + ahb-write-wait-unit = <2>; + ahb-write-wait-interval = <20>; + status = "okay"; + erase-block-size = ; + write-block-size = <16>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 DT_SIZE_K(256)>; + }; + /* The MCUBoot swap-move algorithm uses the last 2 sectors + * of the primary slot0 for swap status and move. + */ + slot0_partition: partition@40000 { + label = "image-0"; + reg = <0x00040000 (DT_SIZE_M(3) + DT_SIZE_K(512))>; + }; + slot1_partition: partition@3C0000 { + label = "image-1"; + reg = <0x003C0000 DT_SIZE_M(3)>; + }; + storage_partition: partition@6C0000 { + label = "storage"; + reg = <0x006C0000 (DT_SIZE_M(58) - DT_SIZE_K(768))>; + }; + }; + }; +}; diff --git a/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_hyperflash.overlay b/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_hyperflash.overlay deleted file mode 100644 index 4b3923c36d9..00000000000 --- a/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_hyperflash.overlay +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Copyright 2024 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/ { - chosen { - zephyr,flash-controller = &s26ks512s0; - zephyr,flash = &s26ks512s0; - zephyr,code-partition = &slot0_partition; - }; -}; - -&flexspi { - status = "okay"; - ahb-prefetch; - ahb-read-addr-opt; - pinctrl-0 = <&pinmux_flexspi1>; - pinctrl-names = "default"; - ahb-bufferable; - ahb-cacheable; - sck-differential-clock; - combination-mode; - rx-clock-source = <3>; - reg = <0x402a8000 0x4000>, <0x60000000 DT_SIZE_M(64)>; - s26ks512s0: s26ks512s@0 { - compatible = "nxp,imx-flexspi-hyperflash"; - size = ; - reg = <0>; - spi-max-frequency = <166000000>; - word-addressable; - cs-interval-unit = <1>; - cs-interval = <2>; - cs-hold-time = <0>; - cs-setup-time = <3>; - data-valid-time = <1>; - column-space = <3>; - ahb-write-wait-unit = <2>; - ahb-write-wait-interval = <20>; - status = "okay"; - erase-block-size = <4096>; - write-block-size = <16>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 DT_SIZE_K(128)>; - }; - /* The MCUBoot swap-move algorithm uses the last 14 sectors - * of the primary slot0 for swap status and move. - */ - slot0_partition: partition@20000 { - label = "image-0"; - reg = <0x00020000 (DT_SIZE_M(3) + DT_SIZE_K(56))>; - }; - slot1_partition: partition@32E000 { - label = "image-1"; - reg = <0x0032E000 DT_SIZE_M(3)>; - }; - storage_partition: partition@62E000 { - label = "storage"; - reg = <0x0062E000 (DT_SIZE_M(58) - DT_SIZE_K(184))>; - }; - }; - }; -}; diff --git a/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_hyperflash.yaml b/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_hyperflash.yaml index 211c0e9aebd..c44f53326df 100644 --- a/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_hyperflash.yaml +++ b/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_hyperflash.yaml @@ -4,7 +4,7 @@ # SPDX-License-Identifier: Apache-2.0 # -identifier: mimxrt1050_evk +identifier: mimxrt1050_evk/mimxrt1052/hyperflash name: NXP MIMXRT1050-EVK type: mcu arch: arm @@ -15,11 +15,13 @@ toolchain: ram: 32768 flash: 65536 supported: + - adc - arduino_gpio - arduino_serial - counter - display - dma + - flash - gpio - i2c - netif:eth @@ -28,5 +30,4 @@ supported: - usb_device - usbd - watchdog - - adc vendor: nxp diff --git a/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_qspi.dts b/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_qspi.dts new file mode 100644 index 00000000000..ca5a924d282 --- /dev/null +++ b/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_qspi.dts @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2017, NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "mimxrt1050_evk.dtsi" + +/ { + chosen { + zephyr,flash-controller = &is25wp064; + zephyr,flash = &is25wp064; + zephyr,code-partition = &slot0_partition; + }; +}; + +&flexspi { + status = "okay"; + ahb-prefetch; + ahb-read-addr-opt; + rx-clock-source = <1>; + reg = <0x402a8000 0x4000>, <0x60000000 DT_SIZE_M(8)>; + is25wp064: is25wp064@0 { + compatible = "nxp,imx-flexspi-nor"; + size = <67108864>; + reg = <0>; + spi-max-frequency = <104000000>; + status = "okay"; + jedec-id = [9d 70 17]; + erase-block-size = <4096>; + write-block-size = <1>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 DT_SIZE_K(128)>; + }; + /* The MCUBoot swap-move algorithm uses the last 2 sectors + * of the primary slot0 for swap status and move. + */ + slot0_partition: partition@20000 { + label = "image-0"; + reg = <0x00020000 (DT_SIZE_M(3) + DT_SIZE_K(8))>; + }; + slot1_partition: partition@322000 { + label = "image-1"; + reg = <0x00322000 DT_SIZE_M(3)>; + }; + storage_partition: partition@622000 { + label = "storage"; + reg = <0x00622000 (DT_SIZE_M(2) - DT_SIZE_K(136))>; + }; + }; + }; +}; diff --git a/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_qspi.overlay b/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_qspi.overlay deleted file mode 100644 index d18cda45c60..00000000000 --- a/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_qspi.overlay +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright (c) 2017, NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/ { - chosen { - zephyr,flash-controller = &is25wp064; - zephyr,flash = &is25wp064; - zephyr,code-partition = &slot0_partition; - }; -}; - -&flexspi { - status = "okay"; - ahb-prefetch; - ahb-read-addr-opt; - rx-clock-source = <1>; - reg = <0x402a8000 0x4000>, <0x60000000 DT_SIZE_M(8)>; - is25wp064: is25wp064@0 { - compatible = "nxp,imx-flexspi-nor"; - size = <67108864>; - reg = <0>; - spi-max-frequency = <133000000>; - status = "okay"; - jedec-id = [9d 70 17]; - erase-block-size = <4096>; - write-block-size = <1>; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 DT_SIZE_K(128)>; - }; - /* The MCUBoot swap-move algorithm uses the last 2 sectors - * of the primary slot0 for swap status and move. - */ - slot0_partition: partition@20000 { - label = "image-0"; - reg = <0x00020000 (DT_SIZE_M(3) + DT_SIZE_K(8))>; - }; - slot1_partition: partition@322000 { - label = "image-1"; - reg = <0x00322000 DT_SIZE_M(3)>; - }; - storage_partition: partition@622000 { - label = "storage"; - reg = <0x00622000 (DT_SIZE_M(2) - DT_SIZE_K(136))>; - }; - }; - }; -}; diff --git a/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_qspi.yaml b/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_qspi.yaml index a9adaba0526..68c150c9366 100644 --- a/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_qspi.yaml +++ b/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_qspi.yaml @@ -4,7 +4,7 @@ # SPDX-License-Identifier: Apache-2.0 # -identifier: mimxrt1050_evk@qspi +identifier: mimxrt1050_evk/mimxrt1052/qspi name: NXP MIMXRT1050-EVK-QSPI type: mcu arch: arm @@ -15,11 +15,13 @@ toolchain: ram: 32768 flash: 8192 supported: + - adc - arduino_gpio - arduino_serial - counter - display - dma + - flash - gpio - i2c - netif:eth @@ -28,5 +30,4 @@ supported: - usb_device - usbd - watchdog - - adc vendor: nxp diff --git a/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_qspi_defconfig b/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_qspi_defconfig new file mode 100644 index 00000000000..a9e39fa1d73 --- /dev/null +++ b/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_qspi_defconfig @@ -0,0 +1,12 @@ +# +# Copyright (c) 2017, NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_GPIO=y +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y diff --git a/boards/nxp/mimxrt1050_evk/revision.cmake b/boards/nxp/mimxrt1050_evk/revision.cmake deleted file mode 100644 index 3e6f006a735..00000000000 --- a/boards/nxp/mimxrt1050_evk/revision.cmake +++ /dev/null @@ -1,7 +0,0 @@ -if (NOT DEFINED BOARD_REVISION) - set(BOARD_REVISION "hyperflash") -else () - if (NOT (BOARD_REVISION STREQUAL "hyperflash") AND NOT (BOARD_REVISION STREQUAL "qspi")) - message(FATAL_ERROR "Invalid board revision, ${BOARD_REVISION}, valid revisions are: hyperflash, qspi") - endif() -endif() diff --git a/boards/nxp/mimxrt1060_evk/CMakeLists.txt b/boards/nxp/mimxrt1060_evk/CMakeLists.txt index 29c2d6f9068..2778972698b 100644 --- a/boards/nxp/mimxrt1060_evk/CMakeLists.txt +++ b/boards/nxp/mimxrt1060_evk/CMakeLists.txt @@ -12,7 +12,7 @@ endif() if(CONFIG_NXP_IMXRT_BOOT_HEADER) zephyr_library() - if(CONFIG_BOARD_MIMXRT1060_EVKB) + if(${BOARD_REVISION} STREQUAL "B") set(FLASH_CONF evkbmimxrt1060_flexspi_nor_config.c) set(BOARD_NAME evkbmimxrt1060) elseif(CONFIG_DT_HAS_NXP_IMX_FLEXSPI_NOR_ENABLED) diff --git a/boards/nxp/mimxrt1060_evk/Kconfig.defconfig b/boards/nxp/mimxrt1060_evk/Kconfig.defconfig index 899e8b3ffe0..bc06c96f7b8 100644 --- a/boards/nxp/mimxrt1060_evk/Kconfig.defconfig +++ b/boards/nxp/mimxrt1060_evk/Kconfig.defconfig @@ -3,7 +3,7 @@ # Copyright 2018,2023 NXP # SPDX-License-Identifier: Apache-2.0 -if BOARD_MIMXRT1060_EVK || BOARD_MIMXRT1060_EVKB +if BOARD_MIMXRT1060_EVK config DEVICE_CONFIGURATION_DATA default y @@ -25,4 +25,4 @@ endif # ETH_MCUX endif # NETWORKING -endif # BOARD_MIMXRT1060_EVK || BOARD_MIMXRT1060_EVKB +endif # BOARD_MIMXRT1060_EVK diff --git a/boards/nxp/mimxrt1060_evk/Kconfig.mimxrt1060_evkb b/boards/nxp/mimxrt1060_evk/Kconfig.mimxrt1060_evkb deleted file mode 100644 index d2f59c8c9cf..00000000000 --- a/boards/nxp/mimxrt1060_evk/Kconfig.mimxrt1060_evkb +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright 2024 NXP -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_MIMXRT1060_EVKB - select SOC_PART_NUMBER_MIMXRT1062DVL6A diff --git a/boards/nxp/mimxrt1060_evk/board.cmake b/boards/nxp/mimxrt1060_evk/board.cmake index 722afd541f7..e6748688a78 100644 --- a/boards/nxp/mimxrt1060_evk/board.cmake +++ b/boards/nxp/mimxrt1060_evk/board.cmake @@ -4,13 +4,19 @@ # SPDX-License-Identifier: Apache-2.0 # +if(NOT ("${BOARD_QUALIFIERS}" MATCHES "qspi" + OR "${BOARD_QUALIFIERS}" MATCHES "hyperflash")) + message(FATAL_ERROR "Please specify a board flash variant for the mimxrt1060_evk:\n" + "mimxrt1060_evk/mimxrt1062/qspi or mimxrt1060_evk/mimxrt1062/hyperflash\n") +endif() + board_runner_args(pyocd "--target=mimxrt1060") board_runner_args(jlink "--device=MIMXRT1062xxx6A") board_runner_args(linkserver "--device=MIMXRT1062xxxxA:EVK-MIMXRT1060") -if (("${BOARD_REVISION}" STREQUAL "qspi") OR CONFIG_BOARD_MIMXRT1060_EVKB) +if(("${BOARD_QUALIFIERS}" MATCHES "qspi") OR ("${BOARD_REVISION}" STREQUAL "B")) board_runner_args(jlink "--loader=BankAddr=0x60000000&Loader=QSPI") -elseif ("${BOARD_REVISION}" STREQUAL "hyperflash") +elseif ("${BOARD_QUALIFIERS}" MATCHES "hyperflash") board_runner_args(jlink "--loader=BankAddr=0x60000000&Loader=HyperFlash") endif() diff --git a/boards/nxp/mimxrt1060_evk/board.yml b/boards/nxp/mimxrt1060_evk/board.yml index c3787a5385e..30a5701b1fe 100644 --- a/boards/nxp/mimxrt1060_evk/board.yml +++ b/boards/nxp/mimxrt1060_evk/board.yml @@ -4,10 +4,12 @@ boards: vendor: nxp socs: - name: mimxrt1062 + variants: + - name: "qspi" + - name: "hyperflash" revision: - format: "custom" - - name: mimxrt1060_evkb - full_name: MIMXRT1060-EVKB - vendor: nxp - socs: - - name: mimxrt1062 + format: "letter" + default: "A" + revisions: + - name: "A" + - name: "B" diff --git a/boards/nxp/mimxrt1060_evk/doc/index.rst b/boards/nxp/mimxrt1060_evk/doc/index.rst index e17f57ee77f..940ca2a593e 100644 --- a/boards/nxp/mimxrt1060_evk/doc/index.rst +++ b/boards/nxp/mimxrt1060_evk/doc/index.rst @@ -1,7 +1,4 @@ -.. _mimxrt1060_evk: - -NXP MIMXRT1060-EVK -################## +.. zephyr:board:: mimxrt1060_evk Overview ******** @@ -15,9 +12,6 @@ ideal for real-time applications such as High-Speed GPIO, CAN FD, and synchronous parallel NAND/NOR/PSRAM controller. The i.MX RT1060 runs on the Arm® Cortex-M7® core up to 600 MHz. -.. image:: mimxrt1060_evk.jpg - :align: center - :alt: MIMXRT1060-EVK Hardware ******** @@ -103,7 +97,7 @@ Supported Features The mimxrt1060_evk board configuration supports the hardware features listed below. For additional features not yet supported, please also refer to the -:ref:`mimxrt1064_evk` , which is the superset board in NXP's i.MX RT10xx family. +:zephyr:board:`mimxrt1064_evk` , which is the superset board in NXP's i.MX RT10xx family. NXP prioritizes enabling the superset board with NXP's Full Platform Support for Zephyr. Therefore, the mimxrt1064_evk board may have additional features already supported, which can also be re-used on this mimxrt1060_evk board: @@ -156,7 +150,7 @@ already supported, which can also be re-used on this mimxrt1060_evk board: +-----------+------------+-------------------------------------+ The default configuration can be found in -:zephyr_file:`boards/nxp/mimxrt1060_evk/mimxrt1060_evk_defconfig` +:zephyr_file:`boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_qspi_defconfig` Other hardware features are not currently supported by the port. @@ -322,6 +316,19 @@ The MIMXRT1060 SoC has eight UARTs. ``LPUART1`` is configured for the console, ``LPUART3`` for the Bluetooth Host Controller Interface (BT HCI), and the remaining are not used. +Board Targets +************* + +This board has two variants that can be targeted, +depending on which flash to set as ``zephyr,flash``: + +* ``mimxrt1060_evk/mimxrt1062/qspi`` is the default variant for the out of box + setup of the board using the qspi flash. +* ``mimxrt1060_evk/mimxrt1062/hyperflash`` is for a board that has been reworked to use the + hyperflash instead of the qspi flash. +* This board also has two revisions, the EVKA and EVKB. EVKA is the default target for this board. + To target EVKB, the board target string would become ``mimxrt1060_evk@B//qspi``, for example. + Programming and Debugging ************************* @@ -382,7 +389,7 @@ Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world - :board: mimxrt1060_evk + :board: mimxrt1060_evk//qspi :goals: flash Open a serial terminal, reset the board (press the SW9 button), and you should @@ -391,7 +398,7 @@ see the following message in the terminal: .. code-block:: console ***** Booting Zephyr OS v1.14.0-rc1 ***** - Hello World! mimxrt1060_evk + Hello World! mimxrt1060_evk//qspi Debugging ========= @@ -400,7 +407,7 @@ Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world - :board: mimxrt1060_evk + :board: mimxrt1060_evk//qspi :goals: debug Open a serial terminal, step through the application in your debugger, and you @@ -409,7 +416,7 @@ should see the following message in the terminal: .. code-block:: console ***** Booting Zephyr OS v1.14.0-rc1 ***** - Hello World! mimxrt1060_evk + Hello World! mimxrt1060_evk//qspi Troubleshooting =============== diff --git a/boards/nxp/mimxrt1060_evk/mimxrt1060_evk.dts b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk.dts deleted file mode 100644 index 4f0be3d23bd..00000000000 --- a/boards/nxp/mimxrt1060_evk/mimxrt1060_evk.dts +++ /dev/null @@ -1,309 +0,0 @@ -/* - * Copyright 2018,2024 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include -#include "mimxrt1060_evk-pinctrl.dtsi" -#include - -/ { - model = "NXP MIMXRT1060-EVK board"; - compatible = "nxp,mimxrt1062"; - - aliases { - led0 = &green_led; - pwm-led0 = &green_pwm_led; - sw0 = &user_button; - watchdog0 = &wdog0; - sdhc0 = &usdhc1; - }; - - chosen { - zephyr,sram = &sdram0; - zephyr,itcm = &itcm; - zephyr,dtcm = &dtcm; - zephyr,uart-mcumgr = &lpuart1; - zephyr,console = &lpuart1; - zephyr,shell-uart = &lpuart1; - zephyr,canbus = &flexcan3; - }; - - sdram0: memory@80000000 { - /* Micron MT48LC16M16A2B4-6AIT:G */ - device_type = "memory"; - reg = <0x80000000 DT_SIZE_M(32)>; - }; - - /* - * This node describes the GPIO pins of the parallel FPC interface, - * This interface is standard to several NXP EVKs, and is used with - * several parallel LCD displays (available as zephyr shields) - */ - nxp_parallel_lcd_connector: parallel-connector { - compatible = "nxp,parallel-lcd-connector"; - #gpio-cells = <2>; - gpio-map-mask = <0xffffffff 0xffffffc0>; - gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpio2 31 0>; /* Pin 1, BL+ */ - }; - - /* - * This node describes the GPIO pins of the I2C display FPC interface, - * This interface is standard to several NXP EVKs, and is used with - * several parallel LCD displays (available as zephyr shields) - */ - nxp_i2c_touch_fpc: i2c-touch-connector { - compatible = "nxp,i2c-tsc-fpc"; - #gpio-cells = <2>; - gpio-map-mask = <0xffffffff 0xffffffc0>; - gpio-map-pass-thru = <0 0x3f>; - gpio-map = <1 0 &gpio1 2 0>, /* Pin 2, LCD touch RST */ - <2 0 &gpio1 11 0>; /* Pin 3, LCD touch INT */ - }; - - leds { - compatible = "gpio-leds"; - green_led: led-1 { - gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; - label = "User LED1"; - }; - }; - - pwmleds { - compatible = "pwm-leds"; - green_pwm_led: green_pwm_led { - pwms = <&flexpwm2_pwm3 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - user_button: button-1 { - label = "User SW8"; - gpios = <&gpio5 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - zephyr,code = ; - }; - }; - - arduino_header: connector { - compatible = "arduino-header-r3"; - #gpio-cells = <2>; - gpio-map-mask = <0xffffffff 0xffffffc0>; - gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpio1 26 0>, /* A0 */ - <1 0 &gpio1 27 0>, /* A1 */ - <2 0 &gpio1 20 0>, /* A2 */ - <3 0 &gpio1 21 0>, /* A3 */ - <4 0 &gpio1 17 0>, /* A4 */ - <5 0 &gpio1 16 0>, /* A5 */ - <6 0 &gpio1 23 0>, /* D0 */ - <7 0 &gpio1 22 0>, /* D1 */ - <8 0 &gpio1 11 0>, /* D2 */ - <9 0 &gpio1 24 0>, /* D3 */ - <10 0 &gpio1 9 0>, /* D4 */ - <11 0 &gpio1 10 0>, /* D5 */ - <12 0 &gpio1 18 0>, /* D6 */ - <13 0 &gpio1 19 0>, /* D7 */ - <14 0 &gpio1 3 0>, /* D8 */ - <15 0 &gpio1 2 0>, /* D9 */ - <16 0 &gpio3 13 0>, /* D10 */ - <17 0 &gpio3 14 0>, /* D11 */ - <18 0 &gpio3 15 0>, /* D12 */ - <19 0 &gpio3 12 0>, /* D13 */ - <20 0 &gpio1 17 0>, /* D14 */ - <21 0 &gpio1 16 0>; /* D15 */ - }; -}; - -arduino_serial: &lpuart3 { - pinctrl-0 = <&pinmux_lpuart3>; - pinctrl-1 = <&pinmux_lpuart3_flow_control>; - pinctrl-2 = <&pinmux_lpuart3_sleep>; - pinctrl-names = "default", "flowcontrol", "sleep"; -}; - -zephyr_lcdif: &lcdif { - pinctrl-0 = <&pinmux_lcdif>; - pinctrl-names = "default"; -}; - -nxp_touch_i2c: &lpi2c1 {}; - -arduino_i2c: &lpi2c1 { - status = "okay"; - pinctrl-0 = <&pinmux_lpi2c1>; - pinctrl-names = "default"; -}; - -&lpuart1 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&pinmux_lpuart1>; - pinctrl-1 = <&pinmux_lpuart1_sleep>; - pinctrl-names = "default", "sleep"; -}; - -&enet_mac { - status = "okay"; - pinctrl-0 = <&pinmux_enet>; - pinctrl-names = "default"; - phy-handle = <&phy>; - zephyr,random-mac-address; - phy-connection-type = "rmii"; -}; - -&enet_mdio { - status = "okay"; - pinctrl-0 = <&pinmux_enet_mdio>; - pinctrl-names = "default"; - phy: phy@0 { - compatible = "microchip,ksz8081"; - reg = <0>; - status = "okay"; - reset-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; - int-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; - microchip,interface-type = "rmii"; - }; -}; - -&enet_ptp_clock { - status = "okay"; - pinctrl-0 = <&pinmux_ptp>; - pinctrl-names = "default"; -}; - -&adc1 { - status = "okay"; - pinctrl-0 = <&pinmux_adc1>; - pinctrl-names = "default"; -}; - -zephyr_udc0: &usb1 { - status = "okay"; - phy_handle = <&usbphy1>; -}; - -&usbphy1 { - status = "okay"; - tx-d-cal = <12>; - tx-cal-45-dp-ohms = <6>; - tx-cal-45-dm-ohms = <6>; -}; - -&csi { - pinctrl-0 = <&pinmux_csi>; - pinctrl-names = "default"; -}; - -&flexpwm2_pwm3 { - status = "okay"; - pinctrl-0 = <&pinmux_flexpwm2_3>; - pinctrl-names = "default"; -}; - -&flexpwm1_pwm0 { - pinctrl-0 = <&pinmux_flexpwm1_0>; - pinctrl-names = "default"; -}; - -&flexpwm1_pwm3 { - pinctrl-0 = <&pinmux_flexpwm1>; - pinctrl-names = "default"; -}; - -&usdhc1 { - status = "okay"; - power-delay-ms = <1000>; - pwr-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; - cd-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; - status = "okay"; - pinctrl-0 = <&pinmux_usdhc1>; - pinctrl-1 = <&pinmux_usdhc1_slow>; - pinctrl-2 = <&pinmux_usdhc1_med>; - pinctrl-3 = <&pinmux_usdhc1_fast>; - pinctrl-names = "default", "slow", "med", "fast"; - sdmmc { - compatible = "zephyr,sdmmc-disk"; - status = "okay"; - }; -}; - -&edma0 { - status = "okay"; -}; - -&flexcan3 { - status = "okay"; - pinctrl-0 = <&pinmux_flexcan3>; - pinctrl-names = "default"; - - can-transceiver { - max-bitrate = <5000000>; - }; -}; - -&wdog0 { - status = "okay"; -}; - -arduino_spi: &lpspi1 { - status = "okay"; - /* DMA channels 0 and 1, muxed to LPSPI1 RX and TX */ - dmas = <&edma0 0 13>, <&edma0 1 14>; - dma-names = "rx", "tx"; - pinctrl-0 = <&pinmux_lpspi1>; - pinctrl-names = "default"; -}; - -&lpspi3 { - status = "okay"; - /* DMA channels 2 and 3, muxed to LPSPI3 RX and TX */ - dmas = <&edma0 2 15>, <&edma0 3 16>; - dma-names = "rx", "tx"; - pinctrl-0 = <&pinmux_lpspi3>; - pinctrl-names = "default"; - -}; - -&sai1 { - status = "okay"; - pinctrl-0 = <&pinmux_sai1>; - pinctrl-names = "default"; -}; - -/* GPT and Systick are enabled. If power management is enabled, the GPT - * timer will be used instead of systick, as allows the core clock to - * be gated. - */ -&gpt_hw_timer { - status = "okay"; -}; - -&systick { - status = "okay"; -}; - -&iomuxcgpr { - status = "okay"; -}; - -&itm { - pinctrl-0 = <&pinmux_swo>; - pinctrl-names = "default"; -}; - -&pxp { - status = "okay"; -}; - -&pit0 { - status = "okay"; -}; - -dvp_fpc24_i2c: &lpi2c1 {}; - -dvp_fpc24_interface: &csi {}; diff --git a/boards/nxp/mimxrt1060_evk/mimxrt1060_evk.dtsi b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk.dtsi new file mode 100644 index 00000000000..84dbaac3ae4 --- /dev/null +++ b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk.dtsi @@ -0,0 +1,311 @@ +/* + * Copyright 2018,2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "mimxrt1060_evk-pinctrl.dtsi" +#include + +/ { + model = "NXP MIMXRT1060-EVK board"; + compatible = "nxp,mimxrt1062"; + + aliases { + led0 = &green_led; + pwm-led0 = &green_pwm_led; + sw0 = &user_button; + watchdog0 = &wdog0; + sdhc0 = &usdhc1; + mcuboot-button0 = &user_button; + }; + + chosen { + zephyr,sram = &sdram0; + zephyr,itcm = &itcm; + zephyr,dtcm = &dtcm; + zephyr,uart-mcumgr = &lpuart1; + zephyr,console = &lpuart1; + zephyr,shell-uart = &lpuart1; + zephyr,canbus = &flexcan3; + }; + + sdram0: memory@80000000 { + /* Micron MT48LC16M16A2B4-6AIT:G */ + device_type = "memory"; + reg = <0x80000000 DT_SIZE_M(32)>; + }; + + /* + * This node describes the GPIO pins of the parallel FPC interface, + * This interface is standard to several NXP EVKs, and is used with + * several parallel LCD displays (available as zephyr shields) + */ + nxp_parallel_lcd_connector: parallel-connector { + compatible = "nxp,parallel-lcd-connector"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpio2 31 0>; /* Pin 1, BL+ */ + }; + + /* + * This node describes the GPIO pins of the I2C display FPC interface, + * This interface is standard to several NXP EVKs, and is used with + * several parallel LCD displays (available as zephyr shields) + */ + nxp_i2c_touch_fpc: i2c-touch-connector { + compatible = "nxp,i2c-tsc-fpc"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <1 0 &gpio1 2 0>, /* Pin 2, LCD touch RST */ + <2 0 &gpio1 11 0>; /* Pin 3, LCD touch INT */ + }; + + leds { + compatible = "gpio-leds"; + green_led: led-1 { + gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; + label = "User LED1"; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + green_pwm_led: green_pwm_led { + pwms = <&flexpwm2_pwm3 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + user_button: button-1 { + label = "User SW8"; + gpios = <&gpio5 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + zephyr,code = ; + }; + }; + + arduino_header: connector { + compatible = "arduino-header-r3"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpio1 26 0>, /* A0 */ + <1 0 &gpio1 27 0>, /* A1 */ + <2 0 &gpio1 20 0>, /* A2 */ + <3 0 &gpio1 21 0>, /* A3 */ + <4 0 &gpio1 17 0>, /* A4 */ + <5 0 &gpio1 16 0>, /* A5 */ + <6 0 &gpio1 23 0>, /* D0 */ + <7 0 &gpio1 22 0>, /* D1 */ + <8 0 &gpio1 11 0>, /* D2 */ + <9 0 &gpio1 24 0>, /* D3 */ + <10 0 &gpio1 9 0>, /* D4 */ + <11 0 &gpio1 10 0>, /* D5 */ + <12 0 &gpio1 18 0>, /* D6 */ + <13 0 &gpio1 19 0>, /* D7 */ + <14 0 &gpio1 3 0>, /* D8 */ + <15 0 &gpio1 2 0>, /* D9 */ + <16 0 &gpio3 13 0>, /* D10 */ + <17 0 &gpio3 14 0>, /* D11 */ + <18 0 &gpio3 15 0>, /* D12 */ + <19 0 &gpio3 12 0>, /* D13 */ + <20 0 &gpio1 17 0>, /* D14 */ + <21 0 &gpio1 16 0>; /* D15 */ + }; +}; + +arduino_serial: &lpuart3 { + pinctrl-0 = <&pinmux_lpuart3>; + pinctrl-1 = <&pinmux_lpuart3_flow_control>; + pinctrl-2 = <&pinmux_lpuart3_sleep>; + pinctrl-names = "default", "flowcontrol", "sleep"; +}; + +zephyr_lcdif: &lcdif { + pinctrl-0 = <&pinmux_lcdif>; + pinctrl-names = "default"; +}; + +nxp_touch_i2c: &lpi2c1 {}; + +arduino_i2c: &lpi2c1 { + status = "okay"; + pinctrl-0 = <&pinmux_lpi2c1>; + pinctrl-names = "default"; +}; + +&lpuart1 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&pinmux_lpuart1>; + pinctrl-1 = <&pinmux_lpuart1_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&enet_mac { + status = "okay"; + pinctrl-0 = <&pinmux_enet>; + pinctrl-names = "default"; + phy-handle = <&phy>; + zephyr,random-mac-address; + phy-connection-type = "rmii"; +}; + +&enet_mdio { + status = "okay"; + pinctrl-0 = <&pinmux_enet_mdio>; + pinctrl-names = "default"; + phy: phy@0 { + compatible = "microchip,ksz8081"; + reg = <0>; + status = "okay"; + reset-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; + int-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; + microchip,interface-type = "rmii"; + }; +}; + +&enet_ptp_clock { + status = "okay"; + pinctrl-0 = <&pinmux_ptp>; + pinctrl-names = "default"; +}; + +&adc1 { + status = "okay"; + pinctrl-0 = <&pinmux_adc1>; + pinctrl-names = "default"; +}; + +zephyr_udc0: &usb1 { + status = "okay"; + phy_handle = <&usbphy1>; +}; + +&usbphy1 { + status = "okay"; + tx-d-cal = <12>; + tx-cal-45-dp-ohms = <6>; + tx-cal-45-dm-ohms = <6>; +}; + +&csi { + pinctrl-0 = <&pinmux_csi>; + pinctrl-names = "default"; +}; + +&flexpwm2_pwm3 { + status = "okay"; + pinctrl-0 = <&pinmux_flexpwm2_3>; + pinctrl-names = "default"; +}; + +&flexpwm1_pwm0 { + pinctrl-0 = <&pinmux_flexpwm1_0>; + pinctrl-names = "default"; +}; + +&flexpwm1_pwm3 { + pinctrl-0 = <&pinmux_flexpwm1>; + pinctrl-names = "default"; +}; + +&usdhc1 { + status = "okay"; + power-delay-ms = <1000>; + pwr-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; + cd-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; + status = "okay"; + pinctrl-0 = <&pinmux_usdhc1>; + pinctrl-1 = <&pinmux_usdhc1_slow>; + pinctrl-2 = <&pinmux_usdhc1_med>; + pinctrl-3 = <&pinmux_usdhc1_fast>; + pinctrl-names = "default", "slow", "med", "fast"; + sdmmc { + compatible = "zephyr,sdmmc-disk"; + disk-name = "SD"; + status = "okay"; + }; +}; + +&edma0 { + status = "okay"; +}; + +&flexcan3 { + status = "okay"; + pinctrl-0 = <&pinmux_flexcan3>; + pinctrl-names = "default"; + + can-transceiver { + max-bitrate = <5000000>; + }; +}; + +&wdog0 { + status = "okay"; +}; + +arduino_spi: &lpspi1 { + status = "okay"; + /* DMA channels 0 and 1, muxed to LPSPI1 RX and TX */ + dmas = <&edma0 0 13>, <&edma0 1 14>; + dma-names = "rx", "tx"; + pinctrl-0 = <&pinmux_lpspi1>; + pinctrl-names = "default"; +}; + +&lpspi3 { + status = "okay"; + /* DMA channels 2 and 3, muxed to LPSPI3 RX and TX */ + dmas = <&edma0 2 15>, <&edma0 3 16>; + dma-names = "rx", "tx"; + pinctrl-0 = <&pinmux_lpspi3>; + pinctrl-names = "default"; + +}; + +&sai1 { + status = "okay"; + pinctrl-0 = <&pinmux_sai1>; + pinctrl-names = "default"; +}; + +/* GPT and Systick are enabled. If power management is enabled, the GPT + * timer will be used instead of systick, as allows the core clock to + * be gated. + */ +&gpt_hw_timer { + status = "okay"; +}; + +&systick { + status = "okay"; +}; + +&iomuxcgpr { + status = "okay"; +}; + +&itm { + pinctrl-0 = <&pinmux_swo>; + pinctrl-names = "default"; +}; + +&pxp { + status = "okay"; +}; + +&pit0 { + status = "okay"; +}; + +dvp_fpc24_i2c: &lpi2c1 {}; + +dvp_fpc24_interface: &csi {}; diff --git a/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_defconfig b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_defconfig deleted file mode 100644 index 8af2d462809..00000000000 --- a/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_defconfig +++ /dev/null @@ -1,13 +0,0 @@ -# -# Copyright (c) 2018, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_GPIO=y -CONFIG_ARM_MPU=y -CONFIG_HW_STACK_PROTECTION=y -CONFIG_PINCTRL=y diff --git a/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_B_defconfig b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_B_defconfig new file mode 100644 index 00000000000..05f3e067e72 --- /dev/null +++ b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_B_defconfig @@ -0,0 +1,12 @@ +# +# Copyright (c) 2022, Whisper.ai +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_GPIO=y +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y diff --git a/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_hyperflash.dts b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_hyperflash.dts new file mode 100644 index 00000000000..125f0fecd18 --- /dev/null +++ b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_hyperflash.dts @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2018, NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "mimxrt1060_evk.dtsi" + +/ { + chosen { + zephyr,flash-controller = &s26ks512s0; + zephyr,flash = &s26ks512s0; + zephyr,code-partition = &slot0_partition; + }; +}; + +&flexspi { + status = "okay"; + ahb-prefetch; + ahb-read-addr-opt; + ahb-bufferable; + ahb-cacheable; + sck-differential-clock; + combination-mode; + rx-clock-source = <3>; + reg = <0x402a8000 0x4000>, <0x60000000 DT_SIZE_M(64)>; + s26ks512s0: s26ks512s@0 { + compatible = "nxp,imx-flexspi-hyperflash"; + size = ; + reg = <0>; + spi-max-frequency = <166000000>; + word-addressable; + cs-interval-unit = <1>; + cs-interval = <2>; + cs-hold-time = <0>; + cs-setup-time = <3>; + data-valid-time = <1>; + column-space = <3>; + ahb-write-wait-unit = <2>; + ahb-write-wait-interval = <20>; + status = "okay"; + erase-block-size = ; + write-block-size = <16>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 DT_SIZE_K(256)>; + }; + /* The MCUBoot swap-move algorithm uses the last 2 sectors + * of the primary slot0 for swap status and move. + */ + slot0_partition: partition@40000 { + label = "image-0"; + reg = <0x00040000 (DT_SIZE_M(3) + DT_SIZE_K(512))>; + }; + slot1_partition: partition@3C0000 { + label = "image-1"; + reg = <0x003C0000 DT_SIZE_M(3)>; + }; + storage_partition: partition@6C0000 { + label = "storage"; + reg = <0x006C0000 (DT_SIZE_M(58) - DT_SIZE_K(768))>; + }; + }; + }; +}; diff --git a/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_hyperflash.overlay b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_hyperflash.overlay deleted file mode 100644 index 25d33e462a0..00000000000 --- a/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_hyperflash.overlay +++ /dev/null @@ -1,68 +0,0 @@ -/* - * Copyright (c) 2018, NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/ { - chosen { - zephyr,flash-controller = &s26ks512s0; - zephyr,flash = &s26ks512s0; - zephyr,code-partition = &slot0_partition; - }; -}; - -&flexspi { - status = "okay"; - ahb-prefetch; - ahb-read-addr-opt; - ahb-bufferable; - ahb-cacheable; - sck-differential-clock; - combination-mode; - rx-clock-source = <3>; - reg = <0x402a8000 0x4000>, <0x60000000 DT_SIZE_M(64)>; - s26ks512s0: s26ks512s@0 { - compatible = "nxp,imx-flexspi-hyperflash"; - size = ; - reg = <0>; - spi-max-frequency = <166000000>; - word-addressable; - cs-interval-unit = <1>; - cs-interval = <2>; - cs-hold-time = <0>; - cs-setup-time = <3>; - data-valid-time = <1>; - column-space = <3>; - ahb-write-wait-unit = <2>; - ahb-write-wait-interval = <20>; - status = "okay"; - erase-block-size = <4096>; - write-block-size = <16>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 DT_SIZE_K(128)>; - }; - /* The MCUBoot swap-move algorithm uses the last 14 sectors - * of the primary slot0 for swap status and move. - */ - slot0_partition: partition@20000 { - label = "image-0"; - reg = <0x00020000 (DT_SIZE_M(3) + DT_SIZE_K(56))>; - }; - slot1_partition: partition@32E000 { - label = "image-1"; - reg = <0x0032E000 DT_SIZE_M(3)>; - }; - storage_partition: partition@62E000 { - label = "storage"; - reg = <0x0062E000 (DT_SIZE_M(58) - DT_SIZE_K(184))>; - }; - }; - }; -}; diff --git a/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_hyperflash.yaml b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_hyperflash.yaml index c453d1c9ee6..1d81a48175a 100644 --- a/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_hyperflash.yaml +++ b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_hyperflash.yaml @@ -4,7 +4,7 @@ # SPDX-License-Identifier: Apache-2.0 # -identifier: mimxrt1060_evk@hyperflash +identifier: mimxrt1060_evk/mimxrt1062/hyperflash name: NXP MIMXRT1060-EVK-HYPERFLASH type: mcu arch: arm @@ -22,6 +22,7 @@ supported: - counter - display - dma + - flash - gpio - i2c - netif:eth diff --git a/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_hyperflash_defconfig b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_hyperflash_defconfig new file mode 100644 index 00000000000..29f9a37ea90 --- /dev/null +++ b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_hyperflash_defconfig @@ -0,0 +1,12 @@ +# +# Copyright (c) 2018, NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_GPIO=y +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y diff --git a/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_qspi.dts b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_qspi.dts new file mode 100644 index 00000000000..1e2876fc45d --- /dev/null +++ b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_qspi.dts @@ -0,0 +1,60 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "mimxrt1060_evk.dtsi" + +/ { + chosen { + zephyr,flash-controller = &is25wp064; + zephyr,flash = &is25wp064; + zephyr,code-partition = &slot0_partition; + }; +}; + +&flexspi { + status = "okay"; + pinctrl-0 = <&pinmux_flexspi1>; + pinctrl-names = "default"; + ahb-prefetch; + ahb-read-addr-opt; + rx-clock-source = <1>; + reg = <0x402a8000 0x4000>, <0x60000000 DT_SIZE_M(8)>; + is25wp064: is25wp064@0 { + compatible = "nxp,imx-flexspi-nor"; + size = <67108864>; + reg = <0>; + spi-max-frequency = <104000000>; + status = "okay"; + jedec-id = [9d 70 17]; + erase-block-size = <4096>; + write-block-size = <1>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 DT_SIZE_K(128)>; + }; + /* The MCUBoot swap-move algorithm uses the last 2 sectors + * of the primary slot0 for swap status and move. + */ + slot0_partition: partition@20000 { + label = "image-0"; + reg = <0x00020000 (DT_SIZE_M(3) + DT_SIZE_K(8))>; + }; + slot1_partition: partition@322000 { + label = "image-1"; + reg = <0x00322000 DT_SIZE_M(3)>; + }; + storage_partition: partition@622000 { + label = "storage"; + reg = <0x00622000 (DT_SIZE_M(2) - DT_SIZE_K(136))>; + }; + }; + }; +}; diff --git a/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_qspi.overlay b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_qspi.overlay deleted file mode 100644 index 8a0abae2fb3..00000000000 --- a/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_qspi.overlay +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Copyright 2024 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/ { - chosen { - zephyr,flash-controller = &is25wp064; - zephyr,flash = &is25wp064; - zephyr,code-partition = &slot0_partition; - }; -}; - -&flexspi { - status = "okay"; - pinctrl-0 = <&pinmux_flexspi1>; - pinctrl-names = "default"; - ahb-prefetch; - ahb-read-addr-opt; - rx-clock-source = <1>; - reg = <0x402a8000 0x4000>, <0x60000000 DT_SIZE_M(8)>; - is25wp064: is25wp064@0 { - compatible = "nxp,imx-flexspi-nor"; - size = <67108864>; - reg = <0>; - spi-max-frequency = <133000000>; - status = "okay"; - jedec-id = [9d 70 17]; - erase-block-size = <4096>; - write-block-size = <1>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 DT_SIZE_K(128)>; - }; - /* The MCUBoot swap-move algorithm uses the last 2 sectors - * of the primary slot0 for swap status and move. - */ - slot0_partition: partition@20000 { - label = "image-0"; - reg = <0x00020000 (DT_SIZE_M(3) + DT_SIZE_K(8))>; - }; - slot1_partition: partition@322000 { - label = "image-1"; - reg = <0x00322000 DT_SIZE_M(3)>; - }; - storage_partition: partition@622000 { - label = "storage"; - reg = <0x00622000 (DT_SIZE_M(2) - DT_SIZE_K(136))>; - }; - }; - }; -}; diff --git a/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_qspi.yaml b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_qspi.yaml index 41181dd8bb3..cd57a0bc6c2 100644 --- a/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_qspi.yaml +++ b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_qspi.yaml @@ -4,7 +4,7 @@ # SPDX-License-Identifier: Apache-2.0 # -identifier: mimxrt1060_evk +identifier: mimxrt1060_evk/mimxrt1062/qspi name: NXP MIMXRT1060-EVK type: mcu arch: arm @@ -15,15 +15,16 @@ toolchain: ram: 32768 flash: 8192 supported: + - adc - arduino_gpio - arduino_i2c - arduino_serial - arduino_spi - - adc - can - counter - display - dma + - flash - gpio - i2c - netif:eth diff --git a/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_qspi_B.overlay b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_qspi_B.overlay new file mode 100644 index 00000000000..284679eaa9f --- /dev/null +++ b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_qspi_B.overlay @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2022, Whisper.ai + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* FLEXPWM not routed to LED on this EVK */ +&flexpwm2_pwm3 { + status = "disabled"; +}; + +&green_led { + gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; + label = "User LED1"; +}; diff --git a/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_qspi_B.yaml b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_qspi_B.yaml new file mode 100644 index 00000000000..5c9f42d5ef7 --- /dev/null +++ b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_qspi_B.yaml @@ -0,0 +1,34 @@ +# +# Copyright (c) 2022, Whisper.ai +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: mimxrt1060_evk@B/mimxrt1062/qspi +name: NXP MIMXRT1060-EVKB +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 32768 +flash: 8192 +supported: + - arduino_gpio + - arduino_i2c + - arduino_serial + - arduino_spi + - counter + - display + - gpio + - i2c + - netif:eth + - sdhc + - spi + - usb_device + - dma + - can + - watchdog + - adc +vendor: nxp diff --git a/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_qspi_defconfig b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_qspi_defconfig new file mode 100644 index 00000000000..29f9a37ea90 --- /dev/null +++ b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_qspi_defconfig @@ -0,0 +1,12 @@ +# +# Copyright (c) 2018, NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_GPIO=y +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y diff --git a/boards/nxp/mimxrt1060_evk/mimxrt1060_evkb.dts b/boards/nxp/mimxrt1060_evk/mimxrt1060_evkb.dts deleted file mode 100644 index 506f0d0d7a7..00000000000 --- a/boards/nxp/mimxrt1060_evk/mimxrt1060_evkb.dts +++ /dev/null @@ -1,18 +0,0 @@ -/* - * Copyright (c) 2022, Whisper.ai - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "mimxrt1060_evk.dts" -#include "mimxrt1060_evk_mimxrt1062_qspi.overlay" - -/* FLEXPWM not routed to LED on this EVK */ -&flexpwm2_pwm3 { - status = "disabled"; -}; - -&green_led { - gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; - label = "User LED1"; -}; diff --git a/boards/nxp/mimxrt1060_evk/mimxrt1060_evkb.yaml b/boards/nxp/mimxrt1060_evk/mimxrt1060_evkb.yaml deleted file mode 100644 index 3f9306c1e03..00000000000 --- a/boards/nxp/mimxrt1060_evk/mimxrt1060_evkb.yaml +++ /dev/null @@ -1,34 +0,0 @@ -# -# Copyright (c) 2022, Whisper.ai -# -# SPDX-License-Identifier: Apache-2.0 -# - -identifier: mimxrt1060_evkb -name: NXP MIMXRT1060-EVKB -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb - - xtools -ram: 32768 -flash: 8192 -supported: - - arduino_gpio - - arduino_i2c - - arduino_serial - - arduino_spi - - counter - - display - - gpio - - i2c - - netif:eth - - sdhc - - spi - - usb_device - - dma - - can - - watchdog - - adc -vendor: nxp diff --git a/boards/nxp/mimxrt1060_evk/mimxrt1060_evkb_defconfig b/boards/nxp/mimxrt1060_evk/mimxrt1060_evkb_defconfig deleted file mode 100644 index 365bcc53c40..00000000000 --- a/boards/nxp/mimxrt1060_evk/mimxrt1060_evkb_defconfig +++ /dev/null @@ -1,13 +0,0 @@ -# -# Copyright (c) 2022, Whisper.ai -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_GPIO=y -CONFIG_ARM_MPU=y -CONFIG_HW_STACK_PROTECTION=y -CONFIG_PINCTRL=y diff --git a/boards/nxp/mimxrt1060_evk/revision.cmake b/boards/nxp/mimxrt1060_evk/revision.cmake deleted file mode 100644 index 97a3da96ea4..00000000000 --- a/boards/nxp/mimxrt1060_evk/revision.cmake +++ /dev/null @@ -1,9 +0,0 @@ -if (NOT DEFINED BOARD_REVISION) - set(BOARD_REVISION "qspi") -else () - if (NOT (BOARD_REVISION STREQUAL "hyperflash") AND NOT (BOARD_REVISION STREQUAL "qspi")) - message(FATAL_ERROR "Invalid board revision, ${BOARD_REVISION}, valid revisions are: hyperflash, qspi") - elseif (BOARD_REVISION STREQUAL "hyperflash" AND CONFIG_BOARD_MIMXRT1060_EVKB) - message(FATAL_ERROR "hyperflash not supported on RT1060 EVKB") - endif() -endif() diff --git a/boards/nxp/mimxrt1062_fmurt6/doc/index.rst b/boards/nxp/mimxrt1062_fmurt6/doc/index.rst index e587a8c5087..25dd714bf73 100644 --- a/boards/nxp/mimxrt1062_fmurt6/doc/index.rst +++ b/boards/nxp/mimxrt1062_fmurt6/doc/index.rst @@ -1,7 +1,4 @@ -.. _fmurt6: - -NXP FMURT6 -################## +.. zephyr:board:: mimxrt1062_fmurt6 Overview ******** @@ -15,10 +12,6 @@ ideal for real-time applications such as High-Speed GPIO, CAN FD, and synchronous parallel NAND/NOR/PSRAM controller. The i.MX RT1062 runs on the Arm® Cortex-M7® core up to 600 MHz. -.. image:: mimxrt1062_fmurt6.jpg - :align: center - :alt: MIMXRT1062_FMURT6 - Hardware ******** @@ -77,7 +70,7 @@ Supported Features The mimxrt1062_fmurt6 board configuration supports the hardware features listed below. For additional features not yet supported, please also refer to the -:ref:`mimxrt1064_evk` , which is the superset board in NXP's i.MX RT10xx family. +:zephyr:board:`mimxrt1064_evk` , which is the superset board in NXP's i.MX RT10xx family. NXP prioritizes enabling the superset board with NXP's Full Platform Support for Zephyr. Therefore, the mimxrt1064_evk board may have additional features already supported, which can also be re-used on this mimxrt1060_evk board: diff --git a/boards/nxp/mimxrt1062_fmurt6/doc/mimxrt1062_fmurt6.jpg b/boards/nxp/mimxrt1062_fmurt6/doc/mimxrt1062_fmurt6.jpg deleted file mode 100644 index 40e1024491f..00000000000 Binary files a/boards/nxp/mimxrt1062_fmurt6/doc/mimxrt1062_fmurt6.jpg and /dev/null differ diff --git a/boards/nxp/mimxrt1062_fmurt6/doc/mimxrt1062_fmurt6.webp b/boards/nxp/mimxrt1062_fmurt6/doc/mimxrt1062_fmurt6.webp new file mode 100644 index 00000000000..1f530bdd813 Binary files /dev/null and b/boards/nxp/mimxrt1062_fmurt6/doc/mimxrt1062_fmurt6.webp differ diff --git a/boards/nxp/mimxrt1062_fmurt6/mimxrt1062_fmurt6.dts b/boards/nxp/mimxrt1062_fmurt6/mimxrt1062_fmurt6.dts index 96a96958a03..de159e4ce24 100644 --- a/boards/nxp/mimxrt1062_fmurt6/mimxrt1062_fmurt6.dts +++ b/boards/nxp/mimxrt1062_fmurt6/mimxrt1062_fmurt6.dts @@ -200,7 +200,7 @@ ahb-write-wait-unit = <2>; ahb-write-wait-interval = <20>; status = "okay"; - erase-block-size = <4096>; + erase-block-size = ; write-block-size = <16>; partitions { @@ -209,22 +209,22 @@ #size-cells = <1>; boot_partition: partition@0 { label = "mcuboot"; - reg = <0x00000000 DT_SIZE_K(128)>; + reg = <0x00000000 DT_SIZE_K(256)>; }; - /* The MCUBoot swap-move algorithm uses the last 14 sectors + /* The MCUBoot swap-move algorithm uses the last 2 sectors * of the primary slot0 for swap status and move. */ - slot0_partition: partition@20000 { + slot0_partition: partition@40000 { label = "image-0"; - reg = <0x00020000 (DT_SIZE_M(3) + DT_SIZE_K(56))>; + reg = <0x00040000 (DT_SIZE_M(3) + DT_SIZE_K(512))>; }; - slot1_partition: partition@32E000 { + slot1_partition: partition@3C0000 { label = "image-1"; - reg = <0x0032E000 DT_SIZE_M(3)>; + reg = <0x003C0000 DT_SIZE_M(3)>; }; - storage_partition: partition@62E000 { + storage_partition: partition@6C0000 { label = "storage"; - reg = <0x0062E000 (DT_SIZE_M(58) - DT_SIZE_K(184))>; + reg = <0x006C0000 (DT_SIZE_M(58) - DT_SIZE_K(768))>; }; }; }; @@ -385,12 +385,17 @@ nxp,prescaler = <64>; }; +&enet2 { + status = "okay"; +}; + &enet2_mac { pinctrl-0 = <&pinmux_enet>; pinctrl-names = "default"; zephyr,random-mac-address; phy-connection-type = "rmii"; phy-handle = <&phy>; + status = "okay"; }; &enet2_mdio { @@ -420,6 +425,7 @@ zephyr_udc0: &usb1 { pinctrl-names = "default", "slow", "med", "fast"; sdmmc { compatible = "zephyr,sdmmc-disk"; + disk-name = "SD"; status = "okay"; }; }; diff --git a/boards/nxp/mimxrt1062_fmurt6/mimxrt1062_fmurt6.yaml b/boards/nxp/mimxrt1062_fmurt6/mimxrt1062_fmurt6.yaml index 01824d0b3bc..9e4a523d944 100644 --- a/boards/nxp/mimxrt1062_fmurt6/mimxrt1062_fmurt6.yaml +++ b/boards/nxp/mimxrt1062_fmurt6/mimxrt1062_fmurt6.yaml @@ -15,17 +15,18 @@ toolchain: ram: 768 flash: 65536 supported: + - adc + - can - counter - - uart - dma + - flash - gpio - i2c - netif:eth + - pwm - sdhc - spi + - uart - usb_device - - can - watchdog - - adc - - pwm vendor: nxp diff --git a/boards/nxp/mimxrt1062_fmurt6/mimxrt1062_fmurt6_defconfig b/boards/nxp/mimxrt1062_fmurt6/mimxrt1062_fmurt6_defconfig index 3db75b19e6d..5de68171b06 100644 --- a/boards/nxp/mimxrt1062_fmurt6/mimxrt1062_fmurt6_defconfig +++ b/boards/nxp/mimxrt1062_fmurt6/mimxrt1062_fmurt6_defconfig @@ -10,7 +10,6 @@ CONFIG_SERIAL=y CONFIG_GPIO=y CONFIG_ARM_MPU=y CONFIG_HW_STACK_PROTECTION=y -CONFIG_PINCTRL=y # Enable Regulators CONFIG_REGULATOR=y diff --git a/boards/nxp/mimxrt1064_evk/doc/index.rst b/boards/nxp/mimxrt1064_evk/doc/index.rst index 4f6fab6f0f6..865b1c2764f 100644 --- a/boards/nxp/mimxrt1064_evk/doc/index.rst +++ b/boards/nxp/mimxrt1064_evk/doc/index.rst @@ -1,7 +1,4 @@ -.. _mimxrt1064_evk: - -NXP MIMXRT1064-EVK -################## +.. zephyr:board:: mimxrt1064_evk Overview ******** @@ -14,10 +11,6 @@ ideal for real-time applications such as High-Speed GPIO, CAN FD, and synchronous parallel NAND/NOR/PSRAM controller. The i.MX RT1064 runs on the Arm® Cortex-M7® core up to 600 MHz. -.. image:: mimxrt1064_evk.jpg - :align: center - :alt: MIMXRT1064-EVK - Hardware ******** diff --git a/boards/nxp/mimxrt1064_evk/mimxrt1064_evk.dts b/boards/nxp/mimxrt1064_evk/mimxrt1064_evk.dts index f3d060d7283..8d9f2437d6a 100644 --- a/boards/nxp/mimxrt1064_evk/mimxrt1064_evk.dts +++ b/boards/nxp/mimxrt1064_evk/mimxrt1064_evk.dts @@ -20,6 +20,7 @@ sw0 = &user_button; watchdog0 = &wdog0; sdhc0 = &usdhc1; + mcuboot-button0 = &user_button; }; chosen { @@ -33,6 +34,7 @@ zephyr,console = &lpuart1; zephyr,shell-uart = &lpuart1; zephyr,canbus = &flexcan2; + zephyr,touch = &ft5336; }; sdram0: memory@80000000 { @@ -162,7 +164,7 @@ nxp_parallel_i2c: &lpi2c1 {}; compatible = "nxp,imx-flexspi-nor"; size = <67108864>; reg = <0>; - spi-max-frequency = <133000000>; + spi-max-frequency = <104000000>; status = "okay"; jedec-id = [9d 70 17]; @@ -274,6 +276,7 @@ zephyr_udc0: &usb1 { pinctrl-names = "default", "slow", "med", "fast"; sdmmc { compatible = "zephyr,sdmmc-disk"; + disk-name = "SD"; status = "okay"; }; }; diff --git a/boards/nxp/mimxrt1064_evk/mimxrt1064_evk.yaml b/boards/nxp/mimxrt1064_evk/mimxrt1064_evk.yaml index a9d454a5083..eab16e277e5 100644 --- a/boards/nxp/mimxrt1064_evk/mimxrt1064_evk.yaml +++ b/boards/nxp/mimxrt1064_evk/mimxrt1064_evk.yaml @@ -15,11 +15,14 @@ toolchain: ram: 32768 flash: 4096 supported: + - adc - arduino_gpio - arduino_serial + - can - counter - display - dma + - flash - gpio - hwinfo - i2c @@ -29,7 +32,5 @@ supported: - spi - usb_device - video - - can - watchdog - - adc vendor: nxp diff --git a/boards/nxp/mimxrt1064_evk/mimxrt1064_evk_defconfig b/boards/nxp/mimxrt1064_evk/mimxrt1064_evk_defconfig index 8af2d462809..29f9a37ea90 100644 --- a/boards/nxp/mimxrt1064_evk/mimxrt1064_evk_defconfig +++ b/boards/nxp/mimxrt1064_evk/mimxrt1064_evk_defconfig @@ -10,4 +10,3 @@ CONFIG_SERIAL=y CONFIG_GPIO=y CONFIG_ARM_MPU=y CONFIG_HW_STACK_PROTECTION=y -CONFIG_PINCTRL=y diff --git a/boards/nxp/mimxrt1160_evk/doc/index.rst b/boards/nxp/mimxrt1160_evk/doc/index.rst index 5b8a110d1b0..b0d513ec8bd 100644 --- a/boards/nxp/mimxrt1160_evk/doc/index.rst +++ b/boards/nxp/mimxrt1160_evk/doc/index.rst @@ -1,7 +1,4 @@ -.. _mimxrt1160_evk: - -NXP MIMXRT1160-EVK -################## +.. zephyr:board:: mimxrt1160_evk Overview ******** @@ -11,10 +8,6 @@ Cortex-M4 at 240 MHz. The i.MX RT1160 MCU offers support over a wide temperature range and is qualified for consumer, industrial and automotive markets. -.. image:: mimxrt1160_evk.jpg - :align: center - :alt: MIMXRT1160-EVK - Hardware ******** @@ -100,7 +93,7 @@ Supported Features The mimxrt1160_evk board configuration supports the hardware features listed below. For additional features not yet supported, please also refer to the -:ref:`mimxrt1170_evk` , which is the superset board in NXP's i.MX RT11xx family. +:zephyr:board:`mimxrt1170_evk` , which is the superset board in NXP's i.MX RT11xx family. NXP prioritizes enabling the superset board with NXP's Full Platform Support for Zephyr. Therefore, the mimxrt1170_evk board may have additional features already supported, which can also be re-used on this mimxrt1160_evk board: @@ -272,6 +265,25 @@ however the :ref:`pyocd-debug-host-tools` do not yet support programming the external flashes on this board so you must reconfigure the board for one of the following debug probes instead. +Launching Images Targeting M4 Core +================================== +If building targeting the M4 core, the M7 core must first run code to launch +the M4 image, by copying it into the ``ocram`` region then kicking off the M4 +core. When building using sysbuild targeting the M4 core, a minimal "launcher" +image will be built and flashed to the M7 core, which loads and kicks off +the M4 core. Therefore when developing an application intended to run +standalone on the M4 core, it is recommended to build with sysbuild, like +so: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: mimxrt1160_evk/mimxrt1166/cm4 + :west-args: --sysbuild + :goals: flash + +If desired, this behavior can be disabled by building with +``-DSB_CONFIG_SECOND_CORE_MCUX_LAUNCHER=n`` + Using J-Link ------------ diff --git a/boards/nxp/mimxrt1160_evk/mimxrt1160_evk.dtsi b/boards/nxp/mimxrt1160_evk/mimxrt1160_evk.dtsi index 3d74d093105..575c605c275 100644 --- a/boards/nxp/mimxrt1160_evk/mimxrt1160_evk.dtsi +++ b/boards/nxp/mimxrt1160_evk/mimxrt1160_evk.dtsi @@ -15,6 +15,7 @@ magn0 = &fxos8700; accel0 = &fxos8700; sdhc0 = &usdhc1; + mcuboot-button0 = &user_button; }; leds { @@ -94,7 +95,7 @@ compatible = "nxp,imx-flexspi-nor"; size = ; reg = <0>; - spi-max-frequency = <133000000>; + spi-max-frequency = <104000000>; status = "okay"; jedec-id = [9d 70 17]; erase-block-size = <4096>; diff --git a/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm4.dts b/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm4.dts index a92f93feb8d..475a166e787 100644 --- a/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm4.dts +++ b/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm4.dts @@ -20,7 +20,7 @@ * sram region is changed and DMA is in use, you will * encounter issues! */ - zephyr,sram = &sram1; + zephyr,sram = &ocram; zephyr,console = &lpuart1; zephyr,shell-uart = &lpuart1; zephyr,flash-controller = &is25wp128; diff --git a/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm4.yaml b/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm4.yaml index 400e501406f..b265336cb24 100644 --- a/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm4.yaml +++ b/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm4.yaml @@ -16,8 +16,9 @@ ram: 128 flash: 128 supported: - dma - - i2c + - flash - gpio + - i2c - pwm - uart vendor: nxp diff --git a/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm4_defconfig b/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm4_defconfig index 5139427b850..d30c21bbab4 100644 --- a/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm4_defconfig +++ b/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm4_defconfig @@ -10,4 +10,3 @@ CONFIG_SERIAL=y CONFIG_GPIO=y CONFIG_ARM_MPU=y CONFIG_HW_STACK_PROTECTION=y -CONFIG_PINCTRL=y diff --git a/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm7.yaml b/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm7.yaml index 9ff9b57258d..b9780a95746 100644 --- a/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm7.yaml +++ b/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm7.yaml @@ -15,9 +15,10 @@ toolchain: ram: 256 flash: 16384 supported: - - counter - can + - counter - dma + - flash - gpio - hwinfo - i2c diff --git a/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm7_defconfig b/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm7_defconfig index 78f5191a154..69b98c5be66 100644 --- a/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm7_defconfig +++ b/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm7_defconfig @@ -11,4 +11,3 @@ CONFIG_GPIO=y CONFIG_ARM_MPU=y CONFIG_HW_STACK_PROTECTION=y CONFIG_FLEXSPI_CONFIG_BLOCK_OFFSET=0x400 -CONFIG_PINCTRL=y diff --git a/boards/nxp/mimxrt1170_evk/Kconfig.sysbuild b/boards/nxp/mimxrt1170_evk/Kconfig.sysbuild deleted file mode 100644 index aa90200fe71..00000000000 --- a/boards/nxp/mimxrt1170_evk/Kconfig.sysbuild +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -choice MCUBOOT_MODE - default MCUBOOT_MODE_SWAP_WITHOUT_SCRATCH if BOARD_MIMXRT1170_EVK_MIMXRT1176_CM7 -endchoice diff --git a/boards/nxp/mimxrt1170_evk/board.cmake b/boards/nxp/mimxrt1170_evk/board.cmake index d1438e4a7b1..8781a87cdd6 100644 --- a/boards/nxp/mimxrt1170_evk/board.cmake +++ b/boards/nxp/mimxrt1170_evk/board.cmake @@ -7,6 +7,9 @@ if(CONFIG_SOC_MIMXRT1176_CM7 OR CONFIG_SECOND_CORE_MCUX) board_runner_args(pyocd "--target=mimxrt1170_cm7") board_runner_args(jlink "--device=MIMXRT1176xxxA_M7" "--reset-after-load") + # ITCM is not defined in RT1170's LinkServer device file + board_runner_args(linkserver "--override=/device/memory/-=\{\"location\":\"0x00000000\",\ + \"size\":\"0x00040000\",\"type\":\"RAM\"\}") if(${BOARD_REVISION} STREQUAL "A") board_runner_args(linkserver "--device=MIMXRT1176xxxxx:MIMXRT1170-EVK") @@ -27,6 +30,6 @@ elseif(CONFIG_SOC_MIMXRT1176_CM4) board_runner_args(linkserver "--core=cm4") endif() +include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) -include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake) diff --git a/boards/nxp/mimxrt1170_evk/doc/index.rst b/boards/nxp/mimxrt1170_evk/doc/index.rst index 7500442bd1b..0f69b3d1416 100644 --- a/boards/nxp/mimxrt1170_evk/doc/index.rst +++ b/boards/nxp/mimxrt1170_evk/doc/index.rst @@ -1,7 +1,4 @@ -.. _mimxrt1170_evk: - -NXP MIMXRT1170-EVK/EVKB -####################### +.. zephyr:board:: mimxrt1170_evk Overview ******** @@ -11,10 +8,6 @@ at 400 MHz. The i.MX RT1170 MCU offers support over a wide temperature range and is qualified for consumer, industrial and automotive markets. Zephyr supports the initial revision of this EVK, as well as rev EVKB. -.. image:: mimxrt1170_evk.jpg - :align: center - :alt: MIMXRT1170-EVK - Hardware ******** @@ -160,11 +153,11 @@ RT1170 EVKB (``mimxrt1170_evk@B//cm7/cm4``) | | | :ref:`rk055hdmipi4ma0`, | | | | | | and :ref:`g1120b0mipi` shields | | | +-----------+------------+-------------------------------------+-----------------+-----------------+ -| ACMP | on-chip | analog comparator | Supported | No support | +| ACMP | on-chip | sensor | Supported | No support | +-----------+------------+-------------------------------------+-----------------+-----------------+ | CAAM RNG | on-chip | entropy | Supported (M7) | No support | +-----------+------------+-------------------------------------+-----------------+-----------------+ -| FLEXSPI | on-chip | flash programming | Supported (M7) | No support | +| FLEXSPI | on-chip | flash programming | Supported (M7) | Supported (M7) | +-----------+------------+-------------------------------------+-----------------+-----------------+ | SDHC | on-chip | SD host controller | Supported (M7) | Supported (M7) | +-----------+------------+-------------------------------------+-----------------+-----------------+ @@ -338,6 +331,25 @@ The secondary core can be debugged normally in single core builds secondary core should be placed into a loop, then a debugger can be attached (see `AN13264`_, section 4.2.3 for more information) +Launching Images Targeting M4 Core +================================== +If building targeting the M4 core, the M7 core must first run code to launch +the M4 image, by copying it into the ``ocram`` region then kicking off the M4 +core. When building using sysbuild targeting the M4 core, a minimal "launcher" +image will be built and flashed to the M7 core, which loads and kicks off +the M4 core. Therefore when developing an application intended to run +standalone on the M4 core, it is recommended to build with sysbuild, like +so: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: mimxrt1170_evk/mimxrt1176/cm4 + :west-args: --sysbuild + :goals: flash + +If desired, this behavior can be disabled by building with +``-DSB_CONFIG_SECOND_CORE_MCUX_LAUNCHER=n`` + Configuring a Debug Probe ========================= @@ -362,11 +374,6 @@ EVK. See `Using J-Link with MIMXRT1170-EVKB`_ or Using LinkServer ---------------- -Known limitations with LinkServer and these boards include: -- ``west flash`` will not write images to non-flash locations. The flash -command only works when all data in the image is written to flash memory -regions. - Install the :ref:`linkserver-debug-host-tools` and make sure they are in your search path. LinkServer works with the default CMSIS-DAP firmware included in the on-board debugger. diff --git a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk.dtsi b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk.dtsi index c479300c8a9..91286ab6fb3 100644 --- a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk.dtsi +++ b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk.dtsi @@ -17,6 +17,7 @@ accel0 = &fxos8700; sdhc0 = &usdhc1; pwm-led0 = &green_pwm_led; + mcuboot-button0 = &user_button; }; leds { @@ -221,7 +222,7 @@ compatible = "nxp,imx-flexspi-nor"; size = ; reg = <0>; - spi-max-frequency = <133000000>; + spi-max-frequency = <104000000>; status = "okay"; jedec-id = [9d 70 17]; erase-block-size = <4096>; diff --git a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4.dts b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4.dts index cbef2377dab..5cd416c9c73 100644 --- a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4.dts +++ b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4.dts @@ -25,7 +25,7 @@ zephyr,shell-uart = &lpuart1; zephyr,canbus = &flexcan2; zephyr,flash-controller = &is25wp128; - zephyr,flash = &sram0; + zephyr,flash = &ocram; nxp,m4-partition = &slot1_partition; zephyr,ipc = &mailbox_b; }; diff --git a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4.yaml b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4.yaml index 87788b3a015..08bbfa3e6b9 100644 --- a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4.yaml +++ b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4.yaml @@ -16,6 +16,7 @@ ram: 128 flash: 128 supported: - dma + - flash - gpio - i2c - pwm diff --git a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4_B.yaml b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4_B.yaml index da1f36a162c..061366570f2 100644 --- a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4_B.yaml +++ b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4_B.yaml @@ -16,8 +16,9 @@ ram: 128 flash: 128 supported: - dma + - flash - gpio - i2c - - spi - pwm + - spi vendor: nxp diff --git a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4_defconfig b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4_defconfig index 822498def23..e34fb332113 100644 --- a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4_defconfig +++ b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4_defconfig @@ -10,4 +10,3 @@ CONFIG_SERIAL=y CONFIG_GPIO=y CONFIG_ARM_MPU=y CONFIG_HW_STACK_PROTECTION=y -CONFIG_PINCTRL=y diff --git a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7.dts b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7.dts index f01c8f7f431..7e2a6c182fb 100644 --- a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7.dts +++ b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7.dts @@ -118,6 +118,7 @@ nxp_mipi_i2c: &lpi2c5 { pwr-gpios = <&gpio10 2 GPIO_ACTIVE_LOW>; sdmmc { compatible = "zephyr,sdmmc-disk"; + disk-name = "SD"; status = "okay"; }; }; diff --git a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7.yaml b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7.yaml index 05eabe8136c..bf2f139da10 100644 --- a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7.yaml +++ b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7.yaml @@ -16,9 +16,11 @@ ram: 256 flash: 16384 supported: - adc - - counter - can + - counter + - display - dma + - flash - gpio - hwinfo - i2c @@ -27,7 +29,7 @@ supported: - pwm - spi - usb_device - - watchdog - - video - usbd + - video + - watchdog vendor: nxp diff --git a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7_B.overlay b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7_B.overlay index bc7995fcb4e..c457d55fa54 100644 --- a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7_B.overlay +++ b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7_B.overlay @@ -89,7 +89,7 @@ m2_hci_uart: &lpuart2 { compatible = "nxp,bt-hci-uart"; sdio-reset-gpios = <&gpio9 15 GPIO_ACTIVE_HIGH>; w-disable-gpios = <&gpio9 30 GPIO_ACTIVE_HIGH>; - hci-operation-speed = <115200>; + hci-operation-speed = <3000000>; hw-flow-control; fw-download-primary-speed = <115200>; fw-download-secondary-speed = <3000000>; diff --git a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7_B.yaml b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7_B.yaml index 62eeec200ea..9935c53c7d0 100644 --- a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7_B.yaml +++ b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7_B.yaml @@ -16,15 +16,16 @@ ram: 65536 flash: 65536 supported: - adc - - counter - can + - counter - dma + - flash - gpio - hwinfo - i2c - mipi_dsi - spi - usb_device - - watchdog - video + - watchdog vendor: nxp diff --git a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7_defconfig b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7_defconfig index 822498def23..e34fb332113 100644 --- a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7_defconfig +++ b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7_defconfig @@ -10,4 +10,3 @@ CONFIG_SERIAL=y CONFIG_GPIO=y CONFIG_ARM_MPU=y CONFIG_HW_STACK_PROTECTION=y -CONFIG_PINCTRL=y diff --git a/boards/nxp/mimxrt1180_evk/CMakeLists.txt b/boards/nxp/mimxrt1180_evk/CMakeLists.txt index beb30185675..1fbff933116 100644 --- a/boards/nxp/mimxrt1180_evk/CMakeLists.txt +++ b/boards/nxp/mimxrt1180_evk/CMakeLists.txt @@ -4,8 +4,10 @@ # SPDX-License-Identifier: Apache-2.0 # +zephyr_library() +zephyr_library_sources(board.c) + if(CONFIG_NXP_IMXRT_BOOT_HEADER) - zephyr_library() if(NOT ((DEFINED CONFIG_BOARD_MIMXRT1180_EVK_MIMXRT1189_CM33) OR (DEFINED CONFIG_BOARD_MIMXRT1180_EVK_MIMXRT1189_CM7))) message(WARNING "It appears you are using the board definition for " @@ -20,11 +22,12 @@ if(CONFIG_NXP_IMXRT_BOOT_HEADER) # used on your custom board. zephyr_compile_definitions(XIP_EXTERNAL_FLASH=1) zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) - if(CONFIG_EXTERNAL_MEM_CONFIG_DATA AND CONFIG_NXP_IMX_EXTERNAL_HYPERRAM) - zephyr_compile_definitions(USE_HYPERRAM) - endif() zephyr_library_sources(${RT1180_BOARD_DIR}/xip/evkmimxrt1180_flexspi_nor_config.c) zephyr_library_include_directories(${RT1180_BOARD_DIR}/xip) zephyr_library_include_directories(${RT1180_BOARD_DIR}) endif() + if(CONFIG_EXTERNAL_MEM_CONFIG_DATA AND CONFIG_NXP_IMX_EXTERNAL_HYPERRAM) + zephyr_compile_definitions(USE_HYPERRAM) + zephyr_library_sources(${RT1180_BOARD_DIR}/xip/evkmimxrt1180_flexspi_nor_config.c) + endif() endif() diff --git a/boards/nxp/mimxrt1180_evk/Kconfig.defconfig b/boards/nxp/mimxrt1180_evk/Kconfig.defconfig index 3b62e522d2d..a71be9a7729 100644 --- a/boards/nxp/mimxrt1180_evk/Kconfig.defconfig +++ b/boards/nxp/mimxrt1180_evk/Kconfig.defconfig @@ -12,4 +12,6 @@ config EXTERNAL_MEM_CONFIG_DATA config NXP_IMX_EXTERNAL_HYPERRAM default y if CPU_CORTEX_M33 +config BOARD_EARLY_INIT_HOOK + default y endif # BOARD_MIMXRT1180_EVK diff --git a/boards/nxp/mimxrt1180_evk/board.c b/boards/nxp/mimxrt1180_evk/board.c new file mode 100644 index 00000000000..6ecd6a868b0 --- /dev/null +++ b/boards/nxp/mimxrt1180_evk/board.c @@ -0,0 +1,37 @@ +/* + * Copyright 2024 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +#if CONFIG_BOARD_EARLY_INIT_HOOK +void board_early_init_hook(void) +{ +#if defined(CONFIG_ETH_NXP_IMX_NETC) && (DT_CHILD_NUM_STATUS_OKAY(DT_NODELABEL(netc)) != 0) + /* RMII mode */ + BLK_CTRL_WAKEUPMIX->NETC_LINK_CFG[4] = BLK_CTRL_WAKEUPMIX_NETC_LINK_CFG_MII_PROT(1); + + /* Output reference clock for RMII */ + BLK_CTRL_WAKEUPMIX->NETC_PORT_MISC_CFG |= + BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_PORT4_RMII_REF_CLK_DIR_MASK; + + /* Unlock the IERB. It will warm reset whole NETC. */ + NETC_PRIV->NETCRR &= ~NETC_PRIV_NETCRR_LOCK_MASK; + + while ((NETC_PRIV->NETCRR & NETC_PRIV_NETCRR_LOCK_MASK) != 0U) { + } + + /* Set the access attribute, otherwise MSIX access will be blocked. */ + NETC_IERB->ARRAY_NUM_RC[0].RCMSIAMQR &= ~(7U << 27); + NETC_IERB->ARRAY_NUM_RC[0].RCMSIAMQR |= (1U << 27); + + /* Lock the IERB. */ + NETC_PRIV->NETCRR |= NETC_PRIV_NETCRR_LOCK_MASK; + while ((NETC_PRIV->NETCSR & NETC_PRIV_NETCSR_STATE_MASK) != 0U) { + } +#endif +} +#endif diff --git a/boards/nxp/mimxrt1180_evk/doc/index.rst b/boards/nxp/mimxrt1180_evk/doc/index.rst index 71066d77f3f..d9dcdaed721 100644 --- a/boards/nxp/mimxrt1180_evk/doc/index.rst +++ b/boards/nxp/mimxrt1180_evk/doc/index.rst @@ -1,7 +1,4 @@ -.. _mimxrt1180_evk: - -NXP MIMXRT1180-EVK -################## +.. zephyr:board:: mimxrt1180_evk Overview ******** @@ -11,10 +8,6 @@ Cortex-M7 at 792 MHz. The i.MX RT1180 MCU offers support over a wide temperature range and is qualified for consumer, industrial and automotive markets. -.. image:: mimxrt1180_evk.webp - :align: center - :alt: MIMXRT1180-EVK - Hardware ******** @@ -102,12 +95,30 @@ configuration supports the following hardware features: +-----------+------------+-------------------------------------+ | GPT | on-chip | counter | +-----------+------------+-------------------------------------+ +| QTMR | on-chip | counter | ++-----------+------------+-------------------------------------+ | UART | on-chip | serial port-polling; | | | | serial port-interrupt | +-----------+------------+-------------------------------------+ | I2C | on-chip | i2c | +-----------+------------+-------------------------------------+ -| ACMP | on-chip | analog comparator | +| ACMP | on-chip | sensor | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| NETC | on-chip | ethernet, mdio | ++-----------+------------+-------------------------------------+ +| CAN | on-chip | can | ++-----------+------------+-------------------------------------+ +| LPTMR | on-chip | counter | ++-----------+------------+-------------------------------------+ +| FLEXSPI | on-chip | flash programming | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | tpm | ++-----------+------------+-------------------------------------+ +| I3C | on-chip | i3c | +-----------+------------+-------------------------------------+ The default configuration can be found in the defconfig file: @@ -146,6 +157,11 @@ Serial Port The MIMXRT1180 SoC has 12 UARTs. One is configured for the console and the remaining are not used. +Ethernet +======== + +NETC driver supports to manage the Physical Station Interface (PSI). + Programming and Debugging ************************* diff --git a/boards/nxp/mimxrt1180_evk/mimxrt1180_evk-pinctrl.dtsi b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk-pinctrl.dtsi index 5b2eba4f8c1..bfaa7852dce 100644 --- a/boards/nxp/mimxrt1180_evk/mimxrt1180_evk-pinctrl.dtsi +++ b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk-pinctrl.dtsi @@ -7,6 +7,38 @@ #include &pinctrl { + emdio_default: emdio_default { + group1 { + pinmux = <&iomuxc_gpio_ad_30_netc_emdc>, + <&iomuxc_gpio_ad_31_netc_emdio>; + bias-pull-down; + slew-rate = "fast"; + drive-strength = "high"; + }; + }; + + eth4_default: eth4_default { + group1 { + pinmux = <&iomuxc_gpio_emc_b2_13_eth4_tx_data0>, + <&iomuxc_gpio_emc_b2_14_eth4_tx_data1>, + <&iomuxc_gpio_emc_b2_15_eth4_tx_en>, + <&iomuxc_gpio_emc_b2_17_eth4_rx_data0>, + <&iomuxc_gpio_emc_b2_18_eth4_rx_data1>, + <&iomuxc_gpio_emc_b2_19_eth4_rx_en>, + <&iomuxc_gpio_emc_b2_20_eth4_rx_er>; + bias-pull-down; + slew-rate = "fast"; + drive-strength = "high"; + }; + group2 { + pinmux = <&iomuxc_gpio_emc_b2_16_eth4_tx_clk>; + input-enable; + bias-pull-down; + slew-rate = "fast"; + drive-strength = "high"; + }; + }; + pinmux_lpspi3: pinmux_lpspi3 { group0 { pinmux = <&iomuxc_gpio_sd_b1_00_lpspi3_pcs0>, @@ -63,4 +95,71 @@ input-enable; }; }; + + pinmux_lpadc1: pinmux_lpadc1 { + group0 { + pinmux = <&iomuxc_gpio_ad_16_adc1_ch0a>, + <&iomuxc_gpio_ad_14_adc1_ch1a>; + drive-strength = "high"; + bias-pull-down; + slew-rate = "fast"; + }; + }; + + /* Need to weld pin header on J35 */ + pinmux_flexcan3: pinmux_flexcan3 { + group0 { + pinmux = <&iomuxc_aon_gpio_aon_03_flexcan3_rx>, + <&iomuxc_aon_gpio_aon_18_flexcan3_tx>; + drive-strength = "high"; + slew-rate = "fast"; + }; + }; + + pinmux_flexspi1: pinmux_flexspi1 { + group0 { + pinmux = <&iomuxc_gpio_sd_b2_05_flexspi1_b_dqs>, + <&iomuxc_gpio_sd_b2_06_flexspi1_b_ss0_b>, + <&iomuxc_gpio_sd_b2_07_flexspi1_b_sclk>, + <&iomuxc_gpio_sd_b2_08_flexspi1_b_data0>, + <&iomuxc_gpio_sd_b2_09_flexspi1_b_data1>, + <&iomuxc_gpio_sd_b2_10_flexspi1_b_data2>, + <&iomuxc_gpio_sd_b2_11_flexspi1_b_data3>; + bias-pull-down; + input-enable; + }; + }; + + pinmux_flexpwm2: pinmux_flexpwm2 { + group0 { + pinmux = <&iomuxc_gpio_ad_27_flexpwm2_pwm1_b>; + drive-strength = "high"; + slew-rate = "fast"; + }; + }; + + pinmux_tpm5: pinmux_tpm5 { + group0 { + pinmux = <&iomuxc_gpio_b1_00_tpm5_ch0>; + drive-strength = "normal"; + slew-rate = "slow"; + }; + }; + + pinmux_i3c2: pinmux_i3c2 { + group0 { + pinmux = <&iomuxc_gpio_ad_18_i3c2_scl>, + <&iomuxc_gpio_ad_19_i3c2_sda>; + drive-strength = "normal"; + drive-open-drain; + slew-rate = "fast"; + input-enable; + }; + + group1 { + pinmux = <&iomuxc_gpio_ad_17_i3c2_pur>; + slew-rate = "fast"; + drive-strength = "high"; + }; + }; }; diff --git a/boards/nxp/mimxrt1180_evk/mimxrt1180_evk.dtsi b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk.dtsi index a6b51df8239..5af9c455524 100644 --- a/boards/nxp/mimxrt1180_evk/mimxrt1180_evk.dtsi +++ b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk.dtsi @@ -11,6 +11,7 @@ aliases { led0 = &green_led; sw0 = &user_button; + pwm-led0 = &green_pwm_led; }; leds { @@ -29,6 +30,13 @@ zephyr,code = ; }; }; + + pwmleds { + compatible = "pwm-leds"; + green_pwm_led: green_pwm_led { + pwms = <&flexpwm2_pwm1 1 PWM_MSEC(20) PWM_POLARITY_NORMAL>; + }; + }; }; &lpuart1 { @@ -55,20 +63,51 @@ status = "okay"; }; -&flexspi1 { +&flexspi { + pinctrl-0 = <&pinmux_flexspi1>; + pinctrl-names = "default"; +}; + +&flexspi { status = "okay"; ahb-prefetch; ahb-read-addr-opt; rx-clock-source = <1>; w25q128jw: w25q128jw@0 { compatible = "nxp,imx-flexspi-nor"; - size = <134217728>; + size = ; reg = <0>; spi-max-frequency = <133000000>; status = "okay"; - jedec-id = [ef 80 18]; + jedec-id = [ef 60 18]; erase-block-size = <4096>; write-block-size = <1>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 DT_SIZE_K(128)>; + }; + /* The MCUBoot swap-move algorithm uses the last 3 sectors + * of the primary slot0 for swap status and move. + */ + slot0_partition: partition@20000 { + label = "image-0"; + reg = <0x00020000 (DT_SIZE_M(7) + DT_SIZE_K(12))>; + }; + slot1_partition: partition@723000 { + label = "image-1"; + reg = <0x00723000 DT_SIZE_M(7)>; + }; + storage_partition: partition@E23000 { + label = "storage"; + reg = <0x00E23000 (DT_SIZE_M(2) - DT_SIZE_K(140))>; + }; + }; }; }; @@ -81,3 +120,35 @@ pinctrl-0 = <&pinmux_lpi2c3>; pinctrl-names = "default"; }; + +&lpadc1 { + pinctrl-0 = <&pinmux_lpadc1>; + pinctrl-names = "default"; +}; + +&flexcan3 { + pinctrl-0 = <&pinmux_flexcan3>; + pinctrl-names = "default"; + can-transceiver { + max-bitrate = <5000000>; + }; +}; + +&flexpwm2_pwm1 { + status = "okay"; + pinctrl-0 = <&pinmux_flexpwm2>; + pinctrl-names = "default"; +}; + +&tpm5 { + pinctrl-0 = <&pinmux_tpm5>; + pinctrl-names = "default"; +}; + +&i3c2 { + pinctrl-0 = <&pinmux_i3c2>; + pinctrl-names = "default"; +}; + +p3t1755dp_ard_i3c_interface: &i3c2 {}; +p3t1755dp_ard_i2c_interface: &lpi2c2 {}; diff --git a/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm33.dts b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm33.dts index 5b9d29bd58d..97a3752628b 100644 --- a/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm33.dts +++ b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm33.dts @@ -21,6 +21,7 @@ zephyr,flash = &w25q128jw; zephyr,console = &lpuart1; zephyr,shell-uart = &lpuart1; + zephyr,canbus = &flexcan3; }; hyperram0: memory@14000000 { @@ -30,11 +31,34 @@ }; }; +&emdio { + pinctrl-0 = <&emdio_default>; + pinctrl-names = "default"; + status = "okay"; + + phy4: phy@3 { + compatible = "ethernet-phy"; + reg = <0x3>; + status = "okay"; + }; +}; + +&enetc_psi0 { + local-mac-address = [00 00 00 01 02 00]; + pinctrl-0 = <ð4_default>; + pinctrl-names = "default"; + phy-handle = <&phy4>; + status = "okay"; +}; + &lpuart1 { status = "okay"; current-speed = <115200>; }; +&lpadc1 { + status = "okay"; +}; &systick { status = "okay"; @@ -43,3 +67,15 @@ &gpt2 { status = "okay"; }; + +&flexcan3 { + status = "okay"; +}; + +&lptmr1 { + status = "okay"; +}; + +&i3c2 { + status = "okay"; +}; diff --git a/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm33.yaml b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm33.yaml index 485f26734ac..bddd1e8a0a3 100644 --- a/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm33.yaml +++ b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm33.yaml @@ -15,8 +15,14 @@ toolchain: ram: 128 flash: 16384 supported: + - adc + - can + - counter + - flash - gpio - - uart - i2c - - counter + - netif:eth + - pwm + - uart + - i3c vendor: nxp diff --git a/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm33_defconfig b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm33_defconfig index d5b8dbd0d80..6fa68d1d2c6 100644 --- a/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm33_defconfig +++ b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm33_defconfig @@ -10,6 +10,5 @@ CONFIG_SERIAL=y CONFIG_GPIO=y CONFIG_ARM_MPU=y CONFIG_HW_STACK_PROTECTION=y -CONFIG_PINCTRL=y # Enable TrustZone-M CONFIG_TRUSTED_EXECUTION_SECURE=y diff --git a/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm7.dts b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm7.dts index e6a55ae5dc9..7e003fe903e 100644 --- a/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm7.dts +++ b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm7.dts @@ -19,6 +19,7 @@ zephyr,flash = &itcm; zephyr,console = &lpuart1; zephyr,shell-uart = &lpuart1; + zephyr,canbus = &flexcan3; }; }; @@ -27,6 +28,10 @@ current-speed = <115200>; }; +&lpadc1 { + status = "okay"; +}; + &systick { status = "okay"; }; @@ -34,3 +39,15 @@ &gpt2 { status = "okay"; }; + +&flexcan3 { + status = "okay"; +}; + +&lptmr1 { + status = "okay"; +}; + +&i3c2 { + status = "okay"; +}; diff --git a/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm7.yaml b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm7.yaml index 504ce887ac0..60b954ec533 100644 --- a/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm7.yaml +++ b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm7.yaml @@ -15,8 +15,13 @@ toolchain: ram: 256 flash: 256 supported: + - adc + - can + - counter + - flash - gpio - - uart - i2c - - counter + - pwm + - uart + - i3c vendor: nxp diff --git a/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm7_defconfig b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm7_defconfig index 89be0a5ebab..11eeb96fa6a 100644 --- a/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm7_defconfig +++ b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm7_defconfig @@ -10,5 +10,4 @@ CONFIG_SERIAL=y CONFIG_GPIO=y CONFIG_ARM_MPU=y CONFIG_HW_STACK_PROTECTION=y -CONFIG_PINCTRL=y CONFIG_NXP_IMXRT_BOOT_HEADER=n diff --git a/boards/nxp/mimxrt595_evk/CMakeLists.txt b/boards/nxp/mimxrt595_evk/CMakeLists.txt index f7db55d9430..79cb85e0664 100644 --- a/boards/nxp/mimxrt595_evk/CMakeLists.txt +++ b/boards/nxp/mimxrt595_evk/CMakeLists.txt @@ -28,5 +28,5 @@ if(CONFIG_NXP_IMXRT_BOOT_HEADER) endif() # Add custom linker section to relocate framebuffers to PSRAM -zephyr_linker_sources_ifdef(CONFIG_LV_Z_VBD_CUSTOM_SECTION +zephyr_linker_sources_ifdef(CONFIG_LV_Z_VDB_CUSTOM_SECTION SECTIONS dc_ram.ld) diff --git a/boards/nxp/mimxrt595_evk/board.c b/boards/nxp/mimxrt595_evk/board.c index 8db60fdcb6b..ecb6cbcd129 100644 --- a/boards/nxp/mimxrt595_evk/board.c +++ b/boards/nxp/mimxrt595_evk/board.c @@ -5,6 +5,7 @@ #include #include "fsl_power.h" +#include "fsl_inputmux.h" #include #include "board.h" @@ -306,6 +307,52 @@ static int mimxrt595_evk_init(void) #endif /* CONFIG_I2S_TEST_SEPARATE_DEVICES */ #endif /* CONFIG_I2S */ + /* Configure the DMA requests in the INPUTMUX */ + INPUTMUX_Init(INPUTMUX); +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(dma0)) + /* Enable the DMA requests with only 1 mux option. The other request + * choices should be configured for the application + */ + INPUTMUX_EnableSignal(INPUTMUX, + kINPUTMUX_Flexcomm11RxToDmac0Ch32RequestEna, true); + INPUTMUX_EnableSignal(INPUTMUX, + kINPUTMUX_Flexcomm11TxToDmac0Ch33RequestEna, true); + INPUTMUX_EnableSignal(INPUTMUX, + kINPUTMUX_Flexcomm12RxToDmac0Ch34RequestEna, true); + INPUTMUX_EnableSignal(INPUTMUX, + kINPUTMUX_Flexcomm12TxToDmac0Ch35RequestEna, true); + INPUTMUX_EnableSignal(INPUTMUX, + kINPUTMUX_Flexcomm16RxToDmac0Ch28RequestEna, true); + INPUTMUX_EnableSignal(INPUTMUX, + kINPUTMUX_Flexcomm16TxToDmac0Ch29RequestEna, true); + INPUTMUX_EnableSignal(INPUTMUX, + kINPUTMUX_I3c1RxToDmac0Ch30RequestEna, true); + INPUTMUX_EnableSignal(INPUTMUX, + kINPUTMUX_I3c1TxToDmac0Ch31RequestEna, true); +#endif /* dma0 */ + +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(dma1)) + /* Enable the DMA requests with only 1 mux option. The other request + * choices should be configured for the application + */ + INPUTMUX_EnableSignal(INPUTMUX, + kINPUTMUX_Flexcomm11RxToDmac1Ch32RequestEna, true); + INPUTMUX_EnableSignal(INPUTMUX, + kINPUTMUX_Flexcomm11TxToDmac1Ch33RequestEna, true); + INPUTMUX_EnableSignal(INPUTMUX, + kINPUTMUX_Flexcomm12RxToDmac1Ch34RequestEna, true); + INPUTMUX_EnableSignal(INPUTMUX, + kINPUTMUX_Flexcomm12TxToDmac1Ch35RequestEna, true); + INPUTMUX_EnableSignal(INPUTMUX, + kINPUTMUX_Flexcomm16RxToDmac1Ch28RequestEna, true); + INPUTMUX_EnableSignal(INPUTMUX, + kINPUTMUX_Flexcomm16TxToDmac1Ch29RequestEna, true); + INPUTMUX_EnableSignal(INPUTMUX, + kINPUTMUX_I3c1RxToDmac1Ch30RequestEna, true); + INPUTMUX_EnableSignal(INPUTMUX, + kINPUTMUX_I3c1TxToDmac1Ch31RequestEna, true); +#endif /* dma1 */ + INPUTMUX_Deinit(INPUTMUX); #ifdef CONFIG_REBOOT /* @@ -344,7 +391,7 @@ static int mimxrt595_evk_init(void) } -#ifdef CONFIG_LV_Z_VBD_CUSTOM_SECTION +#ifdef CONFIG_LV_Z_VDB_CUSTOM_SECTION extern char __flexspi2_start[]; extern char __flexspi2_end[]; @@ -358,14 +405,14 @@ static int init_psram_framebufs(void) return 0; } -#endif /* CONFIG_LV_Z_VBD_CUSTOM_SECTION */ +#endif /* CONFIG_LV_Z_VDB_CUSTOM_SECTION */ #if CONFIG_REGULATOR /* PMIC setup is dependent on the regulator API */ SYS_INIT(board_config_pmic, POST_KERNEL, CONFIG_APPLICATION_INIT_PRIORITY); #endif -#ifdef CONFIG_LV_Z_VBD_CUSTOM_SECTION +#ifdef CONFIG_LV_Z_VDB_CUSTOM_SECTION /* Framebuffers should be setup after PSRAM is initialized but before * Graphics framework init */ diff --git a/boards/nxp/mimxrt595_evk/doc/index.rst b/boards/nxp/mimxrt595_evk/doc/index.rst index 5465a912e8b..899d777a6ff 100644 --- a/boards/nxp/mimxrt595_evk/doc/index.rst +++ b/boards/nxp/mimxrt595_evk/doc/index.rst @@ -1,7 +1,4 @@ -.. _mimxrt595_evk: - -NXP MIMXRT595-EVK -################## +.. zephyr:board:: mimxrt595_evk Overview ******** @@ -16,9 +13,6 @@ i.MX RT500 MCUs provides up to 5MB of on-chip SRAM and several high-bandwidth in to access off-chip flash, including an Octal/Quad SPI interface with an on-the-fly decryption engine. -.. image:: mimxrt595_evk.jpg - :align: center - :alt: MIMXRT595-EVK Hardware ******** @@ -62,7 +56,7 @@ family of MCUs. This board is a focus for NXP's Full Platform Support for Zephyr, to better enable the entire RT5xx family. NXP prioritizes enabling this board with new support for Zephyr features. The mimxrt595_evk board configuration supports the hardware features below. Another very similar -board is the :ref:`mimxrt685_evk`, and that board may have additional features +board is the :zephyr:board:`mimxrt685_evk`, and that board may have additional features already supported, which can also be re-used on this mimxrt595_evk board: +-----------+------------+-------------------------------------+ diff --git a/boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_cm33.dts b/boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_cm33.dts index 2bccfcbed57..efa9d9d244a 100644 --- a/boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_cm33.dts +++ b/boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_cm33.dts @@ -29,6 +29,7 @@ sdhc0 = &usdhc0; pwm-0 = &sc_timer; dmic-dev = &dmic0; + mcuboot-button0 = &user_button_1; }; chosen { @@ -370,6 +371,7 @@ zephyr_udc0: &usbhs { cd-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>; mmc { compatible = "zephyr,mmc-disk"; + disk-name = "SD2"; status = "okay"; }; pinctrl-0 = <&pinmux_usdhc>; diff --git a/boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_cm33.yaml b/boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_cm33.yaml index 532fa9519ea..a2e8406c02b 100644 --- a/boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_cm33.yaml +++ b/boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_cm33.yaml @@ -20,13 +20,14 @@ supported: - arduino_serial - counter - dma + - dmic + - flash - gpio - i2c + - i2s + - pwm + - sdhc - spi - usb_device - watchdog - - sdhc - - pwm - - i2s - - dmic vendor: nxp diff --git a/boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_cm33_defconfig b/boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_cm33_defconfig index a25ec7156e7..113785dfb45 100644 --- a/boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_cm33_defconfig +++ b/boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_cm33_defconfig @@ -7,7 +7,6 @@ CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y -CONFIG_PINCTRL=y CONFIG_UART_INTERRUPT_DRIVEN=y CONFIG_GPIO=y # Enable TrustZone-M diff --git a/boards/nxp/mimxrt685_evk/doc/index.rst b/boards/nxp/mimxrt685_evk/doc/index.rst index 4f53d6435b5..ebd1d9c1d31 100644 --- a/boards/nxp/mimxrt685_evk/doc/index.rst +++ b/boards/nxp/mimxrt685_evk/doc/index.rst @@ -1,7 +1,4 @@ -.. _mimxrt685_evk: - -NXP MIMXRT685-EVK -################## +.. zephyr:board:: mimxrt685_evk Overview ******** @@ -17,10 +14,6 @@ The i.MX RT600 family provides up to 4.5MB of on-chip SRAM and several high-bandwidth interfaces to access off-chip flash, including an Octal/Quad SPI interface with an on-the-fly decryption engine. -.. image:: mimxrt685_evk.jpg - :align: center - :alt: MIMXRT685-EVK - Hardware ******** @@ -59,7 +52,7 @@ family of MCUs. This board is a focus for NXP's Full Platform Support for Zephyr, to better enable the entire RT6xx family. NXP prioritizes enabling this board with new support for Zephyr features. The mimxrt685_evk board configuration supports the hardware features below. Another very similar -board is the :ref:`mimxrt595_evk`, and that board may have additional features +board is the :zephyr:board:`mimxrt595_evk`, and that board may have additional features already supported, which can also be re-used on this mimxrt685_evk board: +-----------+------------+-------------------------------------+ diff --git a/boards/nxp/mimxrt685_evk/mimxrt685_evk_mimxrt685s_cm33.dts b/boards/nxp/mimxrt685_evk/mimxrt685_evk_mimxrt685s_cm33.dts index 3228147ec31..bc091a2abf4 100644 --- a/boards/nxp/mimxrt685_evk/mimxrt685_evk_mimxrt685s_cm33.dts +++ b/boards/nxp/mimxrt685_evk/mimxrt685_evk_mimxrt685s_cm33.dts @@ -34,6 +34,7 @@ accel0 = &fxos8700; sdhc0 = &usdhc0; dmic-dev = &dmic0; + mcuboot-button0 = &user_button_1; }; chosen { @@ -343,6 +344,7 @@ i2s1: &flexcomm3 { cd-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>; sdmmc { compatible = "zephyr,sdmmc-disk"; + disk-name = "SD"; status = "okay"; }; pinctrl-0 = <&pinmux_usdhc>; diff --git a/boards/nxp/mimxrt685_evk/mimxrt685_evk_mimxrt685s_cm33.yaml b/boards/nxp/mimxrt685_evk/mimxrt685_evk_mimxrt685s_cm33.yaml index 59ccb0922be..75124a8e7da 100644 --- a/boards/nxp/mimxrt685_evk/mimxrt685_evk_mimxrt685s_cm33.yaml +++ b/boards/nxp/mimxrt685_evk/mimxrt685_evk_mimxrt685s_cm33.yaml @@ -21,15 +21,16 @@ supported: - arduino_spi - counter - dma - - pwm + - flash - gpio - hwinfo - i2c - - i3c - i2s + - i3c + - pwm - sdhc - spi - - watchdog - usb_device - usbd + - watchdog vendor: nxp diff --git a/boards/nxp/mimxrt685_evk/mimxrt685_evk_mimxrt685s_cm33_defconfig b/boards/nxp/mimxrt685_evk/mimxrt685_evk_mimxrt685s_cm33_defconfig index 47128760e08..8b8e14d542b 100644 --- a/boards/nxp/mimxrt685_evk/mimxrt685_evk_mimxrt685s_cm33_defconfig +++ b/boards/nxp/mimxrt685_evk/mimxrt685_evk_mimxrt685s_cm33_defconfig @@ -7,7 +7,6 @@ CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y -CONFIG_PINCTRL=y CONFIG_UART_INTERRUPT_DRIVEN=y CONFIG_GPIO=y # Enable TrustZone-M diff --git a/boards/nxp/mr_canhubk3/doc/index.rst b/boards/nxp/mr_canhubk3/doc/index.rst index 1de065e202a..fcb813b882d 100644 --- a/boards/nxp/mr_canhubk3/doc/index.rst +++ b/boards/nxp/mr_canhubk3/doc/index.rst @@ -1,7 +1,4 @@ -.. _mr_canhubk3: - -NXP MR-CANHUBK3 -############### +.. zephyr:board:: mr_canhubk3 Overview ******** @@ -11,10 +8,6 @@ as autonomous mobile robots (AMR) and automated guided vehicles (AGV). It features an `NXP S32K344`_ general-purpose automotive microcontroller based on an Arm Cortex-M7 core (Lock-Step). -.. image:: img/mr_canhubk3_top.jpg - :align: center - :alt: NXP MR-CANHUBK3 (TOP) - Hardware ******** diff --git a/boards/nxp/mr_canhubk3/mr_canhubk3.yaml b/boards/nxp/mr_canhubk3/mr_canhubk3.yaml index 7fd4f2b7996..da732b56863 100644 --- a/boards/nxp/mr_canhubk3/mr_canhubk3.yaml +++ b/boards/nxp/mr_canhubk3/mr_canhubk3.yaml @@ -10,16 +10,17 @@ flash: 1024 toolchain: - zephyr supported: - - gpio - - uart + - adc - can + - counter + - display + - dma + - flash + - gpio - i2c - - adc - - spi - - watchdog - netif:eth - pwm - - dma - - display - - counter + - spi + - uart + - watchdog vendor: nxp diff --git a/boards/nxp/mr_canhubk3/mr_canhubk3_defconfig b/boards/nxp/mr_canhubk3/mr_canhubk3_defconfig index b6d3e6e78c7..42dd17cc516 100644 --- a/boards/nxp/mr_canhubk3/mr_canhubk3_defconfig +++ b/boards/nxp/mr_canhubk3/mr_canhubk3_defconfig @@ -16,7 +16,6 @@ CONFIG_ARM_MPU=y CONFIG_NOCACHE_MEMORY=y # Drivers -CONFIG_PINCTRL=y CONFIG_SERIAL=y CONFIG_WATCHDOG=y diff --git a/boards/nxp/rd_rw612_bga/CMakeLists.txt b/boards/nxp/rd_rw612_bga/CMakeLists.txt index 45052c065fb..1317c39df31 100644 --- a/boards/nxp/rd_rw612_bga/CMakeLists.txt +++ b/boards/nxp/rd_rw612_bga/CMakeLists.txt @@ -12,9 +12,6 @@ if(CONFIG_NXP_RW6XX_BOOT_HEADER) endif() zephyr_compile_definitions(BOOT_HEADER_ENABLE=1) zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) - set(RW612_BOARD_DIR - "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/boards/rdrw612bga") zephyr_library() - zephyr_library_sources(${RW612_BOARD_DIR}/flash_config/flash_config.c) - zephyr_library_include_directories(${RW612_BOARD_DIR}/flash_config) + zephyr_library_sources(MX25U51245GZ4I00_FCB.c) endif() diff --git a/boards/nxp/rd_rw612_bga/MX25U51245GZ4I00_FCB.c b/boards/nxp/rd_rw612_bga/MX25U51245GZ4I00_FCB.c new file mode 100644 index 00000000000..48a6e9ca08a --- /dev/null +++ b/boards/nxp/rd_rw612_bga/MX25U51245GZ4I00_FCB.c @@ -0,0 +1,99 @@ +/* + * Copyright 2021-2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include + +__attribute__((section(".flash_conf"), used)) +const fc_flexspi_nor_config_t flexspi_config = { + .memConfig = { + .tag = FC_BLOCK_TAG, + .version = FC_BLOCK_VERSION, + .readSampleClkSrc = 1, + .csHoldTime = 3, + .csSetupTime = 3, + .deviceModeCfgEnable = 1, + .deviceModeSeq = {.seqNum = 1, .seqId = 2}, + .deviceModeArg = 0xC740, + .configCmdEnable = 0, + .deviceType = 0x1, + .sflashPadType = kSerialFlash_4Pads, + .serialClkFreq = 7, + .sflashA1Size = 0x4000000U, + .sflashA2Size = 0, + .sflashB1Size = 0, + .sflashB2Size = 0, + .lookupTable = { + /* Read */ + [0] = FC_FLEXSPI_LUT_SEQ( + FC_CMD_SDR, FC_FLEXSPI_1PAD, + 0xEC, FC_RADDR_SDR, + FC_FLEXSPI_4PAD, 0x20), + [1] = FC_FLEXSPI_LUT_SEQ( + FC_DUMMY_SDR, + FC_FLEXSPI_4PAD, 0x0A, + FC_READ_SDR, + FC_FLEXSPI_4PAD, 0x04), + + /* Read Status */ + [4 * 1 + 0] = FC_FLEXSPI_LUT_SEQ( + FC_CMD_SDR, FC_FLEXSPI_1PAD, + 0x05, FC_READ_SDR, + FC_FLEXSPI_1PAD, 0x04), + + /* Write Status */ + [4 * 2 + 0] = FC_FLEXSPI_LUT_SEQ( + FC_CMD_SDR, FC_FLEXSPI_1PAD, + 0x01, FC_WRITE_SDR, + FC_FLEXSPI_1PAD, 0x02), + + /* Write Enable */ + [4 * 3 + 0] = FC_FLEXSPI_LUT_SEQ( + FC_CMD_SDR, FC_FLEXSPI_1PAD, + 0x06, FC_STOP_EXE, + FC_FLEXSPI_1PAD, 0x00), + + /* Sector erase */ + [4 * 5 + 0] = FC_FLEXSPI_LUT_SEQ( + FC_CMD_SDR, FC_FLEXSPI_1PAD, + 0x21, FC_RADDR_SDR, + FC_FLEXSPI_1PAD, 0x20), + + /* Block erase */ + [4 * 8 + 0] = + FC_FLEXSPI_LUT_SEQ(FC_CMD_SDR, + FC_FLEXSPI_1PAD, + 0x5C, FC_RADDR_SDR, + FC_FLEXSPI_1PAD, + 0x20), + + /* Page program */ + [4 * 9 + 0] = + FC_FLEXSPI_LUT_SEQ(FC_CMD_SDR, + FC_FLEXSPI_1PAD, + 0x12, FC_RADDR_SDR, + FC_FLEXSPI_1PAD, + 0x20), + [4 * 9 + 1] = + FC_FLEXSPI_LUT_SEQ(FC_WRITE_SDR, + FC_FLEXSPI_1PAD, + 0x00, + FC_STOP_EXE, FC_FLEXSPI_1PAD, + 0x00), + + /* chip erase */ + [4 * 11 + 0] = FC_FLEXSPI_LUT_SEQ(FC_CMD_SDR, + FC_FLEXSPI_1PAD, + 0x60, FC_STOP_EXE, + FC_FLEXSPI_1PAD, + 0x00), + }, + }, + .pageSize = 0x100, + .sectorSize = 0x1000, + .ipcmdSerialClkFreq = 0, + .blockSize = 0x8000, + .fcb_fill[0] = 0xFFFFFFFF, +}; diff --git a/boards/nxp/rd_rw612_bga/doc/index.rst b/boards/nxp/rd_rw612_bga/doc/index.rst index e0215ececad..340dcccbd01 100644 --- a/boards/nxp/rd_rw612_bga/doc/index.rst +++ b/boards/nxp/rd_rw612_bga/doc/index.rst @@ -1,7 +1,4 @@ -.. _rd_rw612_bga: - -NXP RD-RW612-BGA -################ +.. zephyr:board:: rd_rw612_bga Overview ******** @@ -59,6 +56,8 @@ Supported Features +-----------+------------+-----------------------------------+ | CTIMER | on-chip | counter | +-----------+------------+-----------------------------------+ +| SCTIMER | on-chip | pwm | ++-----------+------------+-----------------------------------+ | MRT | on-chip | counter | +-----------+------------+-----------------------------------+ | OS_TIMER | on-chip | os timer | @@ -68,6 +67,14 @@ Supported Features +-----------+------------+-----------------------------------+ | BLE | on-chip | Bluetooth | +-----------+------------+-----------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-----------------------------------+ +| DAC | on-chip | dac | ++-----------+------------+-----------------------------------+ +| ENET | on-chip | ethernet | ++-----------+------------+-----------------------------------+ +| Wi-Fi | on-chip | Wi-Fi | ++-----------+------------+-----------------------------------+ The default configuration can be found in the defconfig file: @@ -75,10 +82,63 @@ The default configuration can be found in the defconfig file: Other hardware features are not currently supported + +Display Support +*************** + +The rd_rw612_bga board supports several in-tree display modules. Setup for +each module is described below: + +GoWorld 16880 LCM +================= + +This module does not connect directly to the board, and must be connected +via an adapter board and jumper wires. Connections are described in +:zephyr_file:`boards/nxp/rd_rw612_bga/dts/goworld_16880_lcm.overlay`. The +display sample can be built for this board like so: + +.. zephyr-app-commands:: + :board: rd_rw612_bga + :gen-args: -DDTC_OVERLAY_FILE=goworld_16880_lcm.overlay + :zephyr-app: samples/drivers/display + :goals: build + :compact: + +Adafruit 2.8 TFT +================ + +The :ref:`adafruit_2_8_tft_touch_v2` connects to the board's Arduino headers +directly, but some modifications are required (see +:zephyr_file:`boards/shields/adafruit_2_8_tft_touch_v2/boards/rd_rw612_bga.overlay` +for a list). The display sample can be built for this module like so: + +.. zephyr-app-commands:: + :board: rd_rw612_bga + :shield: adafruit_2_8_tft_touch_v2 + :zephyr-app: samples/drivers/display + :goals: build + :compact: + +NXP LCD_PAR_S035 +================ + +The :ref:`lcd_par_s035` does not connect directly to the board, and must be +connected via jumper wires. Connections and required board changes are +described in +:zephyr_file:`boards/shields/lcd_par_s035/boards/rd_rw612_bga.overlay`. The +display sample can be built for the module like so: + +.. zephyr-app-commands:: + :board: rd_rw612_bga + :shield: lcd_par_s035_8080 + :zephyr-app: samples/drivers/display + :goals: build + :compact: + Fetch Binary Blobs ****************** -To support Bluetooth, rd_rw612_bga requires fetching binary blobs, which can be +To support Bluetooth or Wi-Fi, rd_rw612_bga requires fetching binary blobs, which can be achieved by running the following command: .. code-block:: console @@ -152,20 +212,19 @@ Bluetooth BLE functionality requires to fetch binary blobs, so make sure to follow the ``Fetch Binary Blobs`` section first. -Those binary blobs can be used in two different ways, depending if :kconfig:option:`CONFIG_NXP_MONOLITHIC_BT` -is enabled or not: +rd_rw612_bga platform supports the monolithic feature. The required binary blob +``/modules/hal/nxp/zephyr/blobs/rw61x_sb_ble_a2.bin`` will be linked +with the application image directly, forming one single monolithic image. -- :kconfig:option:`CONFIG_NXP_MONOLITHIC_BT` is enabled (default): +Wi-Fi +***** -The required binary blob will be linked with the application image directly, forming -one single monolithic image. -The user has nothing else to do other than flashing the application to the board. - -- :kconfig:option:`CONFIG_NXP_MONOLITHIC_BT` is disabled: +Wi-Fi functionality requires to fetch binary blobs, so make sure to follow +the ``Fetch Binary Blobs`` section first. -In this case, the BLE blob won't be linked with the application, so the user needs to manually -flash the BLE binary blob to the board at the address ``0x18540000``. -The binary blob will be located here: ``/modules/hal/nxp/zephyr/blobs/rw61x/rw61x_sb_ble_a2.bin`` +rd_rw612_bga platform supports the monolithic feature. The required binary blob +``/modules/hal/nxp/zephyr/blobs/rw61x_sb_wifi_a2.bin`` will be linked +with the application image directly, forming one single monolithic image. Board variants ************** @@ -201,5 +260,7 @@ Then, build for the board target ``rd_rw612_bga//ethernet``. Resources ********* +.. target-notes:: + .. _RW612 Website: https://www.nxp.com/products/wireless-connectivity/wi-fi-plus-bluetooth-plus-802-15-4/wireless-mcu-with-integrated-tri-radiobr1x1-wi-fi-6-plus-bluetooth-low-energy-5-3-802-15-4:RW612 diff --git a/boards/nxp/rd_rw612_bga/dts/goworld_16880_lcm.overlay b/boards/nxp/rd_rw612_bga/dts/goworld_16880_lcm.overlay index 8b9dbe92491..658778d373b 100644 --- a/boards/nxp/rd_rw612_bga/dts/goworld_16880_lcm.overlay +++ b/boards/nxp/rd_rw612_bga/dts/goworld_16880_lcm.overlay @@ -3,6 +3,7 @@ / { chosen { zephyr,display = &st7796s_lcdic; + zephyr,touch = &ft7401; }; lvgl_pointer { @@ -16,6 +17,8 @@ &lcdic { status = "okay"; nxp,swap-bytes; + /* Raise the timer0 ratio to enable longer reset delay */ + nxp,timer0-ratio = <15>; /* * Settings to connect this display: * Populate the following resistors: diff --git a/boards/nxp/rd_rw612_bga/rd_rw612_bga-pinctrl.dtsi b/boards/nxp/rd_rw612_bga/rd_rw612_bga-pinctrl.dtsi index 78193e6b512..a82b286091a 100644 --- a/boards/nxp/rd_rw612_bga/rd_rw612_bga-pinctrl.dtsi +++ b/boards/nxp/rd_rw612_bga/rd_rw612_bga-pinctrl.dtsi @@ -112,4 +112,11 @@ slew-rate = "fast"; }; }; + + pinmux_pwm0: pinmux_pwm0 { + group0 { + pinmux = ; + slew-rate = "normal"; + }; + }; }; diff --git a/boards/nxp/rd_rw612_bga/rd_rw612_bga.dtsi b/boards/nxp/rd_rw612_bga/rd_rw612_bga.dtsi index ace4c03c56c..8d8bd71cd61 100644 --- a/boards/nxp/rd_rw612_bga/rd_rw612_bga.dtsi +++ b/boards/nxp/rd_rw612_bga/rd_rw612_bga.dtsi @@ -14,11 +14,12 @@ aliases { usart-0 = &flexcomm3; - led0 = &green_led; sw0 = &sw_4; i2c-0 = &flexcomm2; watchdog0 = &wwdt; dmic-dev = &dmic0; + mcuboot-button0 = &sw_4; + pwm-0 = &sctimer; }; chosen { @@ -31,14 +32,6 @@ zephyr,shell-uart = &flexcomm3; }; - leds { - compatible = "gpio-leds"; - green_led: led_1 { - gpios = <&hsgpio1 20 0>; - label = "User LED_GREEN"; - }; - }; - gpio_keys { compatible = "gpio-keys"; sw_4: sw_4 { @@ -76,6 +69,22 @@ <20 0 &hsgpio0 16 0>, /* D14 */ <21 0 &hsgpio0 17 0>; /* D15 */ }; + + + /* + * The pins for this interface are chosen arbitrarily- the RD-RW612 + * board does not have the NXP 8080 interface, but can support displays + * using it by connecting signals directly with jumper wires. + */ + nxp_lcd_8080_connector: lcd-8080-connector { + compatible = "nxp,lcd-8080"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <9 0 &hsgpio0 3 0>, /* Pin 9, LCD touch INT */ + <10 0 &hsgpio0 2 0>, /* Pin 10, LCD backlight control */ + <11 0 &hsgpio0 4 0>; /* Pin 11, LCD and touch reset */ + }; }; &wwdt { @@ -144,30 +153,20 @@ arduino_i2c: &flexcomm2 { label = "mcuboot"; reg = <0x00000000 DT_SIZE_K(128)>; }; - /* Note slot 0 has one additional sector, - * this is intended for use with the swap move algorithm + /* The MCUBoot swap-move algorithm uses the last 2 sectors + * of the primary slot0 for swap status and move. */ slot0_partition: partition@20000 { label = "image-0"; - reg = <0x00020000 0x3e0000>; + reg = <0x00020000 (DT_SIZE_M(3) + DT_SIZE_K(2 * 4))>; }; - - /* This partition is reserved for connectivity firmwares storage - * and shouldn't be moved. - */ - fw_storage: partition@400000 { - label = "fw_storage"; - reg = <0x400000 0x280000>; - read-only; - }; - - slot1_partition: partition@680000 { + slot1_partition: partition@323000 { label = "image-1"; - reg = <0x680000 0x3e0000>; + reg = <0x00323000 DT_SIZE_M(3)>; }; - storage_partition: partition@a60000 { + storage_partition: partition@623000 { label = "storage"; - reg = <0xa60000 0x35a0000>; + reg = <0x00623000 (DT_SIZE_M(58) - DT_SIZE_K(136))>; }; }; }; @@ -241,12 +240,22 @@ zephyr_udc0: &usb_otg { status = "okay"; }; -&lcdic { +zephyr_mipi_dbi_parallel: &lcdic { status = "okay"; pinctrl-0 = <&pinmux_lcdic>; pinctrl-names = "default"; }; +/* + * Similar to the flexio connection, these pins are not + * broken out in the format required to connect directly to + * an NXP 8080 display, but they can be connected with jumper + * wires. + */ +nxp_8080_touch_panel_i2c: &arduino_i2c { + status = "okay"; +}; + &mrt0_channel0 { status = "okay"; }; @@ -255,6 +264,12 @@ zephyr_udc0: &usb_otg { status = "okay"; }; +&sctimer { + status = "okay"; + pinctrl-0 = <&pinmux_pwm0>; + pinctrl-names = "default"; +}; + &pmu { reset-causes-en = , , @@ -279,12 +294,12 @@ zephyr_udc0: &usb_otg { status = "disabled"; }; -&hci { +&pin1 { status = "okay"; - wakeup-source; + wakeup-level = "low"; }; -&pin1 { +&nbu { status = "okay"; - wakeup-level = "low"; + wakeup-source; }; diff --git a/boards/nxp/rd_rw612_bga/rd_rw612_bga.yaml b/boards/nxp/rd_rw612_bga/rd_rw612_bga.yaml index 919f10479ee..1971325463b 100644 --- a/boards/nxp/rd_rw612_bga/rd_rw612_bga.yaml +++ b/boards/nxp/rd_rw612_bga/rd_rw612_bga.yaml @@ -15,15 +15,17 @@ toolchain: ram: 960 flash: 65536 supported: + - adc + - counter + - dac - dma - dmic + - entropy + - flash - gpio - - spi + - hwinfo - i2c - - entropy + - pwm + - spi - usb_device - watchdog - - counter - - hwinfo - - adc - - dac diff --git a/boards/nxp/rd_rw612_bga/rd_rw612_bga_defconfig b/boards/nxp/rd_rw612_bga/rd_rw612_bga_defconfig index b987fa24dc0..8c5e9ace7be 100644 --- a/boards/nxp/rd_rw612_bga/rd_rw612_bga_defconfig +++ b/boards/nxp/rd_rw612_bga/rd_rw612_bga_defconfig @@ -7,7 +7,6 @@ CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y -CONFIG_PINCTRL=y CONFIG_UART_INTERRUPT_DRIVEN=y CONFIG_GPIO=y CONFIG_ARM_MPU=y diff --git a/boards/nxp/rd_rw612_bga/rd_rw612_bga_rw612_ethernet_defconfig b/boards/nxp/rd_rw612_bga/rd_rw612_bga_rw612_ethernet_defconfig index b987fa24dc0..8c5e9ace7be 100644 --- a/boards/nxp/rd_rw612_bga/rd_rw612_bga_rw612_ethernet_defconfig +++ b/boards/nxp/rd_rw612_bga/rd_rw612_bga_rw612_ethernet_defconfig @@ -7,7 +7,6 @@ CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y -CONFIG_PINCTRL=y CONFIG_UART_INTERRUPT_DRIVEN=y CONFIG_GPIO=y CONFIG_ARM_MPU=y diff --git a/boards/nxp/rddrone_fmuk66/doc/index.rst b/boards/nxp/rddrone_fmuk66/doc/index.rst index e938c685ba7..f83f310974b 100644 --- a/boards/nxp/rddrone_fmuk66/doc/index.rst +++ b/boards/nxp/rddrone_fmuk66/doc/index.rst @@ -1,7 +1,4 @@ -.. _rddrone_fmuk66: - -NXP RDDRONE-FMUK66 -################## +.. zephyr:board:: rddrone_fmuk66 Overview ******** @@ -11,10 +8,6 @@ connectors and a Kinetis K66 on board. - Comes with a J-Link Edu Mini for programming and UART console. -.. image:: rddrone_fmuk66.jpg - :align: center - :alt: RDDRONE-FMUK66 - Hardware ******** diff --git a/boards/nxp/rddrone_fmuk66/rddrone_fmuk66.dts b/boards/nxp/rddrone_fmuk66/rddrone_fmuk66.dts index 1dbc7ec3e12..b2b3fefa4fe 100644 --- a/boards/nxp/rddrone_fmuk66/rddrone_fmuk66.dts +++ b/boards/nxp/rddrone_fmuk66/rddrone_fmuk66.dts @@ -142,7 +142,7 @@ /* PWM header is powered by FlexTimer 0 for channels 1 to 4 */ &ftm0 { status = "okay"; - compatible = "nxp,kinetis-ftm-pwm"; + compatible = "nxp,ftm-pwm"; #pwm-cells = <3>; pinctrl-0 = <&ftm0_default>; pinctrl-names = "default"; @@ -153,7 +153,7 @@ /* RGB LED powered by FlexTimer 3, and PWM headers for channel 5 and 6 */ &ftm3 { status = "okay"; - compatible = "nxp,kinetis-ftm-pwm"; + compatible = "nxp,ftm-pwm"; #pwm-cells = <3>; pinctrl-0 = <&ftm3_default>; pinctrl-names = "default"; @@ -240,20 +240,20 @@ zephyr_udc0: &usbotg { reg = <0x00000000 DT_SIZE_K(64)>; read-only; }; - /* The MCUBoot swap-move algorithm uses the last 2 sectors + /* The MCUBoot swap-move algorithm uses the last 3 sectors * of the primary slot0 for swap status and move. */ slot0_partition: partition@10000 { label = "image-0"; - reg = <0x00010000 (DT_SIZE_K(928) + DT_SIZE_K(8))>; + reg = <0x00010000 (DT_SIZE_K(928) + DT_SIZE_K(12))>; }; - slot1_partition: partition@FA000 { + slot1_partition: partition@FB000 { label = "image-1"; - reg = <0x000FA000 DT_SIZE_K(928)>; + reg = <0x000FB000 DT_SIZE_K(928)>; }; - storage_partition: partition@1E2000 { + storage_partition: partition@1E3000 { label = "storage"; - reg = <0x001E2000 DT_SIZE_K(120)>; + reg = <0x001E3000 DT_SIZE_K(116)>; }; }; }; diff --git a/boards/nxp/rddrone_fmuk66/rddrone_fmuk66.yaml b/boards/nxp/rddrone_fmuk66/rddrone_fmuk66.yaml index 44723b330b3..e71803feb3c 100644 --- a/boards/nxp/rddrone_fmuk66/rddrone_fmuk66.yaml +++ b/boards/nxp/rddrone_fmuk66/rddrone_fmuk66.yaml @@ -10,6 +10,7 @@ toolchain: supported: - can - counter + - flash - gpio - i2c - nvs diff --git a/boards/nxp/rddrone_fmuk66/rddrone_fmuk66_defconfig b/boards/nxp/rddrone_fmuk66/rddrone_fmuk66_defconfig index fe63a4dd234..d029940e517 100644 --- a/boards/nxp/rddrone_fmuk66/rddrone_fmuk66_defconfig +++ b/boards/nxp/rddrone_fmuk66/rddrone_fmuk66_defconfig @@ -4,7 +4,6 @@ CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y CONFIG_GPIO=y -CONFIG_PINCTRL=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=160000000 CONFIG_OSC_EXTERNAL=y diff --git a/boards/nxp/s32z2xxdc2/Kconfig.defconfig b/boards/nxp/s32z2xxdc2/Kconfig.defconfig index 2b5dffc8933..4e0448afc1e 100644 --- a/boards/nxp/s32z2xxdc2/Kconfig.defconfig +++ b/boards/nxp/s32z2xxdc2/Kconfig.defconfig @@ -30,4 +30,20 @@ config NET_L2_ETHERNET endif # NETWORKING +if XIP +# Offset between CRAM AXIM and CRAM AXIF, code will be downloaded +# over AXIM interface +config BUILD_OUTPUT_ADJUST_LMA + default "-0x47800000" + +config CPU_CORTEX_R52_CACHE_SEGREGATION + default y + +config CPU_CORTEX_R52_ICACHE_FLASH_WAY + default 4 + +config CPU_CORTEX_R52_DCACHE_FLASH_WAY + default 1 +endif # XIP + endif # BOARD_S32Z2XXDC2_S32Z270_RTU0 || BOARD_S32Z2XXDC2_S32Z270_RTU1 diff --git a/boards/nxp/s32z2xxdc2/doc/index.rst b/boards/nxp/s32z2xxdc2/doc/index.rst index d864059de00..9cb0972bf8f 100644 --- a/boards/nxp/s32z2xxdc2/doc/index.rst +++ b/boards/nxp/s32z2xxdc2/doc/index.rst @@ -1,7 +1,4 @@ -.. _s32z2xxdc2: - -NXP X-S32Z27X-DC (DC2) -###################### +.. zephyr:board:: s32z2xxdc2 Overview ******** @@ -59,6 +56,10 @@ The boards support the following hardware features: +-----------+------------+-------------------------------------+ | LPI2C | on-chip | i2c | +-----------+------------+-------------------------------------+ +| EDMA | on-chip | dma | ++-----------+------------+-------------------------------------+ +| DSPI | on-chip | spi | ++-----------+------------+-------------------------------------+ Other hardware features are not currently supported by the port. @@ -163,6 +164,12 @@ ADC is provided through ADC SAR controller with 2 instances. Each ADC SAR instan .. note:: All channels of an instance only run on 1 group channel at the same time. +EDMA +==== + +The EDMA modules feature four EDMA3 instances: Instance 0 with 32 channels, +and instances 1, 4, and 5, each with 16 channels. + Programming and Debugging ************************* diff --git a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.dts b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.dts index 3db4df08388..da6b9645614 100644 --- a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.dts +++ b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.dts @@ -13,7 +13,8 @@ compatible = "nxp,s32z270"; chosen { - zephyr,sram = &sram0; + zephyr,sram = &dram0; + zephyr,flash = &cram0; zephyr,canbus = &canxl0; }; diff --git a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.yaml b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.yaml index 1ec2dc27de4..070c33e6bfd 100644 --- a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.yaml +++ b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.yaml @@ -18,4 +18,5 @@ supported: - counter - adc - i2c + - dma vendor: nxp diff --git a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0_D.yaml b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0_D.yaml index 329e11384c7..9d692144a76 100644 --- a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0_D.yaml +++ b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0_D.yaml @@ -18,4 +18,5 @@ supported: - counter - adc - i2c + - dma vendor: nxp diff --git a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0_defconfig b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0_defconfig index d7f502c0af0..e498ea98543 100644 --- a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0_defconfig +++ b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0_defconfig @@ -1,11 +1,10 @@ # Copyright 2022,2024 NXP # SPDX-License-Identifier: Apache-2.0 -CONFIG_XIP=n +CONFIG_XIP=y CONFIG_ISR_STACK_SIZE=512 CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000 CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=8000000 CONFIG_ARM_MPU=y -CONFIG_PINCTRL=y CONFIG_SERIAL=y CONFIG_CONSOLE=y diff --git a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.dts b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.dts index 4aadfbebb1d..286fd8d094c 100644 --- a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.dts +++ b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.dts @@ -13,9 +13,8 @@ compatible = "nxp,s32z270"; chosen { - zephyr,sram = &sram1; - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; + zephyr,sram = &dram1; + zephyr,flash = &cram1; zephyr,canbus = &flexcan0; }; diff --git a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.yaml b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.yaml index ff384e953be..3de95effa80 100644 --- a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.yaml +++ b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.yaml @@ -18,4 +18,5 @@ supported: - counter - adc - i2c + - dma vendor: nxp diff --git a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1_D.yaml b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1_D.yaml index 1165ca80194..ef45138807e 100644 --- a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1_D.yaml +++ b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1_D.yaml @@ -18,4 +18,5 @@ supported: - counter - adc - i2c + - dma vendor: nxp diff --git a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1_defconfig b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1_defconfig index d7f502c0af0..e498ea98543 100644 --- a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1_defconfig +++ b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1_defconfig @@ -1,11 +1,10 @@ # Copyright 2022,2024 NXP # SPDX-License-Identifier: Apache-2.0 -CONFIG_XIP=n +CONFIG_XIP=y CONFIG_ISR_STACK_SIZE=512 CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000 CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=8000000 CONFIG_ARM_MPU=y -CONFIG_PINCTRL=y CONFIG_SERIAL=y CONFIG_CONSOLE=y diff --git a/boards/nxp/s32z2xxdc2/support/startup.cmm b/boards/nxp/s32z2xxdc2/support/startup.cmm index a0cbca67470..ca26d84ae08 100644 --- a/boards/nxp/s32z2xxdc2/support/startup.cmm +++ b/boards/nxp/s32z2xxdc2/support/startup.cmm @@ -20,20 +20,17 @@ ; - Core0 and Core2 (redundancy) operate as a lockstep pair * ; - Core1 and Core3 (redundancy) operate as a lockstep pair * ; default: yes * -; - thumb set to "yes" to select the T32 instruction set at reset * -; default: no * ; * ;******************************************************************************* ENTRY %LINE &args -LOCAL &rtuStartAddr &cfgCoreAddr &coreId &rtuId &thumbBit &spltLckBit +LOCAL &rtuStartAddr &cfgCoreAddr &coreId &rtuId &spltLckBit &command=STRing.SCANAndExtract("&args","command=","debug") &elfFile=STRing.SCANAndExtract("&args","elfFile=","") &rtu=STRing.SCANAndExtract("&args","rtu=","0") &core=STRing.SCANAndExtract("&args","core=","0") &lockstep=STRing.SCANAndExtract("&args","lockstep=","yes") -&thumb=STRing.SCANAndExtract("&args","thumb=","no") IF ("&elfFile"=="") ( @@ -59,12 +56,6 @@ IF (&core<0||&core>3) ENDDO ) -; select ARMv8 instruction set at reset for all Cortex-R52 cores (CFG_CORE.THUMB bit) -IF ("&thumb"=="yes") - &thumbBit="1" -ELSE - &thumbBit="0" - ; select lock-step or split-lock mode (CFG_CORE.SPLT_LCK bit) IF ("&lockstep"=="yes") &spltLckBit="0" @@ -126,8 +117,8 @@ GOSUB EnableRTU1 ; Init RTU SRAM DO ~~/demo/arm/hardware/s32z27/misc/s32z27_init_rtu&(rtu)_sram.cmm -; Set reset value for TE bit and split-lock mode -Data.Set EZAXI:&cfgCoreAddr %Long 0yXXXXxxxxXXXXxxxxXXXXxxxxXXXXx&(thumbBit)x&(spltLckBit) ; CFG_CORE +; Set reset value for split-lock mode +Data.Set EZAXI:&cfgCoreAddr %Long 0yXXXXxxxxXXXXxxxxXXXXxxxxXXXXxxx&(spltLckBit) ; CFG_CORE ; Write loop to self instruction Data.Set EAXI:&rtuStartAddr %Long 0xFFFEF7FF diff --git a/boards/nxp/twr_ke18f/Kconfig b/boards/nxp/twr_ke18f/Kconfig index 55f834aea20..b909e9adf24 100644 --- a/boards/nxp/twr_ke18f/Kconfig +++ b/boards/nxp/twr_ke18f/Kconfig @@ -7,6 +7,7 @@ if BOARD_TWR_KE18F config BOARD_TWR_KE18F_FLEXIO_CLKOUT bool "CLKOUT signal on FlexIO header" + select PINCTRL help Enable the CLKOUT signal on FlexIO header pin 7 (PTE10). diff --git a/boards/nxp/twr_ke18f/doc/index.rst b/boards/nxp/twr_ke18f/doc/index.rst index 4d91e6e3352..5bdf3dcf51e 100644 --- a/boards/nxp/twr_ke18f/doc/index.rst +++ b/boards/nxp/twr_ke18f/doc/index.rst @@ -1,7 +1,4 @@ -.. _twr_ke18f: - -NXP TWR-KE18F -############# +.. zephyr:board:: twr_ke18f Overview ******** @@ -11,12 +8,6 @@ MCU-based platforms. The onboard OpenSDAv2 serial and debug adapter, running an open source bootloader, offers options for serial communication, flash programming, and run-control debugging. -.. figure:: TWR-KE18F-DEVICE.jpg - :align: center - :alt: TWR-KE18F - - TWR-KE18F (Credit: NXP) - Hardware ******** @@ -85,7 +76,7 @@ features: +-----------+------------+-------------------------------------+ | DAC | on-chip | dac | +-----------+------------+-------------------------------------+ -| ACMP | on-chip | analog comparator | +| ACMP | on-chip | sensor | +-----------+------------+-------------------------------------+ The default configuration can be found in the defconfig file: diff --git a/boards/nxp/twr_ke18f/twr_ke18f.dts b/boards/nxp/twr_ke18f/twr_ke18f.dts index a3cfd3d54dc..66e10594521 100644 --- a/boards/nxp/twr_ke18f/twr_ke18f.dts +++ b/boards/nxp/twr_ke18f/twr_ke18f.dts @@ -35,6 +35,7 @@ sw1 = &user_button_2; magn0 = &fxos8700; accel0 = &fxos8700; + mcuboot-button0 = &user_button_3; }; chosen { @@ -223,7 +224,7 @@ &ftm0 { status = "okay"; - compatible = "nxp,kinetis-ftm-pwm"; + compatible = "nxp,ftm-pwm"; #pwm-cells = <3>; pinctrl-0 = <&ftm0_default>; pinctrl-names = "default"; @@ -232,7 +233,7 @@ &ftm3 { status = "okay"; - compatible = "nxp,kinetis-ftm-pwm"; + compatible = "nxp,ftm-pwm"; #pwm-cells = <3>; pinctrl-0 = <&ftm3_default>; pinctrl-names = "default"; diff --git a/boards/nxp/twr_ke18f/twr_ke18f.yaml b/boards/nxp/twr_ke18f/twr_ke18f.yaml index ddd4df467f0..2ee4b9bef15 100644 --- a/boards/nxp/twr_ke18f/twr_ke18f.yaml +++ b/boards/nxp/twr_ke18f/twr_ke18f.yaml @@ -15,6 +15,7 @@ supported: - dac - dma - i2c + - flash - pwm - spi - watchdog diff --git a/boards/nxp/twr_ke18f/twr_ke18f_defconfig b/boards/nxp/twr_ke18f/twr_ke18f_defconfig index 1890a440902..a0033d82781 100644 --- a/boards/nxp/twr_ke18f/twr_ke18f_defconfig +++ b/boards/nxp/twr_ke18f/twr_ke18f_defconfig @@ -4,7 +4,6 @@ CONFIG_SERIAL=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_PINCTRL=y CONFIG_GPIO=y # Enable MPU diff --git a/boards/nxp/twr_kv58f220m/doc/index.rst b/boards/nxp/twr_kv58f220m/doc/index.rst index f9adc60064a..69b5add3505 100644 --- a/boards/nxp/twr_kv58f220m/doc/index.rst +++ b/boards/nxp/twr_kv58f220m/doc/index.rst @@ -1,7 +1,4 @@ -.. _twr_kv58f220m: - -NXP TWR-KV58F220M -################# +.. zephyr:board:: twr_kv58f220m Overview ******** @@ -11,12 +8,6 @@ MCU-based platforms. The onboard OpenSDAv2 serial and debug adapter, running an open source bootloader, offers options for serial communication, flash programming, and run-control debugging. -.. figure:: twr_kv58f220m.jpg - :align: center - :alt: TWR-KV58F220M - - TWR-KV58F220M (Credit: NXP) - Hardware ******** diff --git a/boards/nxp/twr_kv58f220m/twr_kv58f220m.dts b/boards/nxp/twr_kv58f220m/twr_kv58f220m.dts index f42607c334f..4a920fb39b9 100644 --- a/boards/nxp/twr_kv58f220m/twr_kv58f220m.dts +++ b/boards/nxp/twr_kv58f220m/twr_kv58f220m.dts @@ -25,6 +25,7 @@ sw3 = &user_button_3; magn0 = &fxos8700; accel0 = &fxos8700; + mcuboot-button0 = &user_button_0; }; chosen { diff --git a/boards/nxp/twr_kv58f220m/twr_kv58f220m.yaml b/boards/nxp/twr_kv58f220m/twr_kv58f220m.yaml index 6118c0c0b11..453ce7d004c 100644 --- a/boards/nxp/twr_kv58f220m/twr_kv58f220m.yaml +++ b/boards/nxp/twr_kv58f220m/twr_kv58f220m.yaml @@ -9,5 +9,6 @@ toolchain: ram: 128 flash: 1024 supported: + - flash - i2c vendor: nxp diff --git a/boards/nxp/twr_kv58f220m/twr_kv58f220m_defconfig b/boards/nxp/twr_kv58f220m/twr_kv58f220m_defconfig index 88afd604b5b..2b1df4eb6e4 100644 --- a/boards/nxp/twr_kv58f220m/twr_kv58f220m_defconfig +++ b/boards/nxp/twr_kv58f220m/twr_kv58f220m_defconfig @@ -4,7 +4,6 @@ CONFIG_SERIAL=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_PINCTRL=y CONFIG_GPIO=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=237500000 diff --git a/boards/nxp/ucans32k1sic/doc/index.rst b/boards/nxp/ucans32k1sic/doc/index.rst index 3eca2900922..8468d46669b 100644 --- a/boards/nxp/ucans32k1sic/doc/index.rst +++ b/boards/nxp/ucans32k1sic/doc/index.rst @@ -1,7 +1,4 @@ -.. _ucans32k1sic: - -NXP UCANS32K1SIC -################ +.. zephyr:board:: ucans32k1sic Overview ******** @@ -11,10 +8,6 @@ board designed for both automotive and industrial applications. The UCANS32K1SIC provides two CAN SIC interfaces and is based on the 32-bit Arm Cortex-M4F `NXP S32K146`_ microcontroller. -.. image:: img/ucans32k1sic_top.webp - :align: center - :alt: NXP UCANS32K1SIC (TOP) - Hardware ******** @@ -67,7 +60,7 @@ This board has 5 GPIO ports named from ``gpioa`` to ``gpioe``. Pin control can be further configured from your application overlay by adding children nodes with the desired pinmux configuration to the singleton node ``pinctrl``. Supported properties are described in -:zephyr_file:`dts/bindings/pinctrl/nxp,kinetis-pinctrl.yaml`. +:zephyr_file:`dts/bindings/pinctrl/nxp,port-pinctrl.yaml`. LEDs ---- diff --git a/boards/nxp/ucans32k1sic/ucans32k1sic.dts b/boards/nxp/ucans32k1sic/ucans32k1sic.dts index 4c1fdeb0732..a22a3918c8e 100644 --- a/boards/nxp/ucans32k1sic/ucans32k1sic.dts +++ b/boards/nxp/ucans32k1sic/ucans32k1sic.dts @@ -150,7 +150,7 @@ }; &ftm0 { - compatible = "nxp,kinetis-ftm-pwm"; + compatible = "nxp,ftm-pwm"; pinctrl-0 = <&ftm0_default>; pinctrl-names = "default"; clock-source = "system"; @@ -160,7 +160,7 @@ }; &ftm1 { - compatible = "nxp,kinetis-ftm-pwm"; + compatible = "nxp,ftm-pwm"; pinctrl-0 = <&ftm1_default>; pinctrl-names = "default"; clock-source = "system"; @@ -170,7 +170,7 @@ }; &ftm2 { - compatible = "nxp,kinetis-ftm-pwm"; + compatible = "nxp,ftm-pwm"; pinctrl-0 = <&ftm2_default>; pinctrl-names = "default"; clock-source = "system"; diff --git a/boards/nxp/ucans32k1sic/ucans32k1sic_defconfig b/boards/nxp/ucans32k1sic/ucans32k1sic_defconfig index 6be7cd5f2a7..08e047dd7bb 100644 --- a/boards/nxp/ucans32k1sic/ucans32k1sic_defconfig +++ b/boards/nxp/ucans32k1sic/ucans32k1sic_defconfig @@ -9,6 +9,5 @@ CONFIG_XIP=y # Enable MPU CONFIG_ARM_MPU=y -CONFIG_PINCTRL=y CONFIG_SERIAL=y CONFIG_CONSOLE=y diff --git a/boards/nxp/usb_kw24d512/doc/index.rst b/boards/nxp/usb_kw24d512/doc/index.rst index 37bbb88726d..4706d94cc0d 100644 --- a/boards/nxp/usb_kw24d512/doc/index.rst +++ b/boards/nxp/usb_kw24d512/doc/index.rst @@ -1,7 +1,4 @@ -.. _usb_kw24d512: - -NXP USB-KW24D512 -################ +.. zephyr:board:: usb_kw24d512 Overview ******** diff --git a/boards/nxp/usb_kw24d512/usb_kw24d512.yaml b/boards/nxp/usb_kw24d512/usb_kw24d512.yaml index 5344593b029..1252d6418fc 100644 --- a/boards/nxp/usb_kw24d512/usb_kw24d512.yaml +++ b/boards/nxp/usb_kw24d512/usb_kw24d512.yaml @@ -9,6 +9,7 @@ toolchain: - gnuarmemb - xtools supported: + - flash - usb_device - watchdog vendor: nxp diff --git a/boards/nxp/usb_kw24d512/usb_kw24d512_defconfig b/boards/nxp/usb_kw24d512/usb_kw24d512_defconfig index 005cd998960..5100bd3c175 100644 --- a/boards/nxp/usb_kw24d512/usb_kw24d512_defconfig +++ b/boards/nxp/usb_kw24d512/usb_kw24d512_defconfig @@ -5,6 +5,5 @@ CONFIG_RTT_CONSOLE=y CONFIG_USE_SEGGER_RTT=y CONFIG_SERIAL=y CONFIG_GPIO=y -CONFIG_PINCTRL=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=48000000 CONFIG_OSC_EXTERNAL=y diff --git a/boards/nxp/vmu_rt1170/doc/index.rst b/boards/nxp/vmu_rt1170/doc/index.rst index 4ad7bad0c17..4b5d72f9ba9 100644 --- a/boards/nxp/vmu_rt1170/doc/index.rst +++ b/boards/nxp/vmu_rt1170/doc/index.rst @@ -1,7 +1,4 @@ -.. _VMU RT1170: - -NXP VMU RT1170 -################## +.. zephyr:board:: vmu_rt1170 Overview ******** @@ -13,10 +10,6 @@ and is qualified for consumer, industrial and automotive markets. The VMU RT1170 is the default VMU for CogniPilot's Cerebri, a Zephyr RTOS based Autopilot. -.. image:: vmu_rt1170.jpg - :align: center - :alt: VMU RT1170 - Hardware ******** @@ -119,7 +112,7 @@ following hardware features: +-----------+------------+-------------------------------------+ | DISPLAY | on-chip | display | +-----------+------------+-------------------------------------+ -| ACMP | on-chip | analog comparator | +| ACMP | on-chip | sensor | +-----------+------------+-------------------------------------+ | CAAM RNG | on-chip | entropy | +-----------+------------+-------------------------------------+ diff --git a/boards/nxp/vmu_rt1170/vmu_rt1170.yaml b/boards/nxp/vmu_rt1170/vmu_rt1170.yaml index 9446ece2d95..0ad33d74855 100644 --- a/boards/nxp/vmu_rt1170/vmu_rt1170.yaml +++ b/boards/nxp/vmu_rt1170/vmu_rt1170.yaml @@ -16,9 +16,10 @@ ram: 256 flash: 65536 supported: - adc - - counter - can + - counter - dma + - flash - gpio - hwinfo - i2c diff --git a/boards/nxp/vmu_rt1170/vmu_rt1170_mimxrt1176_cm7.dts b/boards/nxp/vmu_rt1170/vmu_rt1170_mimxrt1176_cm7.dts index b6011a38098..205b2149c8b 100644 --- a/boards/nxp/vmu_rt1170/vmu_rt1170_mimxrt1176_cm7.dts +++ b/boards/nxp/vmu_rt1170/vmu_rt1170_mimxrt1176_cm7.dts @@ -22,6 +22,7 @@ sdhc0 = &usdhc1; sw0 = &arming_button; pwm-led0 = &buzzer0; + mcuboot-button0 = &arming_button; }; chosen { @@ -458,6 +459,7 @@ cd-gpios = <&gpio3 31 (GPIO_ACTIVE_LOW | GPIO_PULL_DOWN)>; sdmmc { compatible = "zephyr,sdmmc-disk"; + disk-name = "SD"; status = "okay"; }; }; diff --git a/boards/nxp/vmu_rt1170/vmu_rt1170_mimxrt1176_cm7_defconfig b/boards/nxp/vmu_rt1170/vmu_rt1170_mimxrt1176_cm7_defconfig index e6d72e55f46..5c88c2339dc 100644 --- a/boards/nxp/vmu_rt1170/vmu_rt1170_mimxrt1176_cm7_defconfig +++ b/boards/nxp/vmu_rt1170/vmu_rt1170_mimxrt1176_cm7_defconfig @@ -12,7 +12,6 @@ CONFIG_GPIO=y CONFIG_ARM_MPU=y CONFIG_HW_STACK_PROTECTION=y CONFIG_FLEXSPI_CONFIG_BLOCK_OFFSET=0x400 -CONFIG_PINCTRL=y # Enable Regulators CONFIG_REGULATOR=y diff --git a/boards/olimex/lora_stm32wl_devkit/doc/olimex_lora_stm32wl_devkit.rst b/boards/olimex/lora_stm32wl_devkit/doc/olimex_lora_stm32wl_devkit.rst index 84e219fc170..1755c3cdc72 100644 --- a/boards/olimex/lora_stm32wl_devkit/doc/olimex_lora_stm32wl_devkit.rst +++ b/boards/olimex/lora_stm32wl_devkit/doc/olimex_lora_stm32wl_devkit.rst @@ -1,7 +1,4 @@ -.. _olimex_lora_stm32wl_devkit: - -Olimex LoRa STM32WL DevKit -########################## +.. zephyr:board:: olimex_lora_stm32wl_devkit Overview ******** @@ -9,12 +6,6 @@ Overview LoRaWAN development kit based on Olimex BB-STM32WL module using the STM32WLE5CCU6 MCU. -.. figure:: olimex-stm32wl-devkit.jpg - :align: center - :alt: Olimex LoRa STM32WL DevKit - - Olimex LoRa STM32WL DevKit (credit: OLIMEX) - Hardware ******** diff --git a/boards/olimex/olimex_esp32_evb/Kconfig b/boards/olimex/olimex_esp32_evb/Kconfig new file mode 100644 index 00000000000..e931c751cab --- /dev/null +++ b/boards/olimex/olimex_esp32_evb/Kconfig @@ -0,0 +1,7 @@ +# Copyright (c) 2022 Henrik Brix Andersen +# SPDX-License-Identifier: Apache-2.0 + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 4096 if BOARD_OLIMEX_ESP32_EVB_ESP32_PROCPU + default 256 if BOARD_OLIMEX_ESP32_EVB_ESP32_APPCPU diff --git a/boards/olimex/olimex_esp32_evb/Kconfig.defconfig b/boards/olimex/olimex_esp32_evb/Kconfig.defconfig deleted file mode 100644 index e3269639038..00000000000 --- a/boards/olimex/olimex_esp32_evb/Kconfig.defconfig +++ /dev/null @@ -1,22 +0,0 @@ -# Olimex ESP32-EVB board configuration - -# Copyright (c) 2022 Henrik Brix Andersen -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_OLIMEX_ESP32_EVB_ESP32_PROCPU - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 65535 if WIFI && BT - default 51200 if WIFI - default 40960 if BT - default 4096 - -endif # BOARD_OLIMEX_ESP32_EVB_ESP32_PROCPU - -if BOARD_OLIMEX_ESP32_EVB_ESP32_APPCPU - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - default 256 - -endif # BOARD_OLIMEX_ESP32_EVB_ESP32_APPCPU diff --git a/boards/olimex/olimex_esp32_evb/doc/index.rst b/boards/olimex/olimex_esp32_evb/doc/index.rst index 5af913a1273..880e3933ab9 100644 --- a/boards/olimex/olimex_esp32_evb/doc/index.rst +++ b/boards/olimex/olimex_esp32_evb/doc/index.rst @@ -1,7 +1,4 @@ -.. _olimex_esp32_evb: - -Olimex ESP32-EVB -################ +.. zephyr:board:: olimex_esp32_evb Overview ******** @@ -15,12 +12,6 @@ The board can operate from a single LiPo backup battery as it has an internal LiPo battery charger. There is no step-up converter, so relays, CAN, and USB power does not work when running off battery. -.. figure:: ESP32-EVB.jpg - :align: center - :alt: ESP32-EVB - - ESP32-EVB (Credit: Olimex) - Hardware ******** @@ -256,6 +247,8 @@ You can debug an application in the usual way. Here is an example for the :zephy References ********** +.. target-notes:: + .. _ESP32-EVB Website: https://www.olimex.com/Products/IoT/ESP32/ESP32-EVB/open-source-hardware diff --git a/boards/olimex/olimex_esp32_evb/olimex_esp32_evb_appcpu.dts b/boards/olimex/olimex_esp32_evb/olimex_esp32_evb_appcpu.dts index ae7a2e1e7f6..c88ae757867 100644 --- a/boards/olimex/olimex_esp32_evb/olimex_esp32_evb_appcpu.dts +++ b/boards/olimex/olimex_esp32_evb/olimex_esp32_evb_appcpu.dts @@ -6,15 +6,18 @@ /dts-v1/; #include +#include / { model = "Espressif ESP32-DevkitC APPCPU"; compatible = "espressif,esp32"; chosen { - zephyr,sram = &sram0; + zephyr,sram = &sram1; zephyr,ipc_shm = &shm0; zephyr,ipc = &ipm0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_appcpu_partition; }; }; @@ -25,42 +28,3 @@ &trng0 { status = "okay"; }; - -&flash0 { - status = "okay"; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Reserve 60kB for the bootloader */ - boot_partition: partition@1000 { - label = "mcuboot"; - reg = <0x00001000 0x0000F000>; - read-only; - }; - - /* Reserve 1024kB for the application in slot 0 */ - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 0x00100000>; - }; - - /* Reserve 1024kB for the application in slot 1 */ - slot1_partition: partition@110000 { - label = "image-1"; - reg = <0x00110000 0x00100000>; - }; - - /* Reserve 256kB for the scratch partition */ - scratch_partition: partition@210000 { - label = "image-scratch"; - reg = <0x00210000 0x00040000>; - }; - - storage_partition: partition@250000 { - label = "storage"; - reg = <0x00250000 0x00006000>; - }; - }; -}; diff --git a/boards/olimex/olimex_esp32_evb/olimex_esp32_evb_procpu.dts b/boards/olimex/olimex_esp32_evb/olimex_esp32_evb_procpu.dts index c239263ea53..c39916c6de6 100644 --- a/boards/olimex/olimex_esp32_evb/olimex_esp32_evb_procpu.dts +++ b/boards/olimex/olimex_esp32_evb/olimex_esp32_evb_procpu.dts @@ -9,6 +9,7 @@ #include #include "olimex_esp32_evb-pinctrl.dtsi" #include +#include / { model = "Olimex ESP32-EVB"; @@ -17,7 +18,7 @@ chosen { zephyr,console = &uart0; zephyr,shell-uart = &uart0; - zephyr,sram = &sram0; + zephyr,sram = &sram1; zephyr,flash = &flash0; zephyr,code-partition = &slot0_partition; zephyr,bt-hci = &esp32_bt_hci; @@ -127,45 +128,6 @@ uext_spi: &spi2 {}; status = "okay"; }; -&flash0 { - status = "okay"; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Reserve 60kB for the bootloader */ - boot_partition: partition@1000 { - label = "mcuboot"; - reg = <0x00001000 DT_SIZE_K(60)>; - read-only; - }; - - /* Reserve 1024kB for the application in slot 0 */ - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 DT_SIZE_K(1024)>; - }; - - /* Reserve 1024kB for the application in slot 1 */ - slot1_partition: partition@110000 { - label = "image-1"; - reg = <0x00110000 DT_SIZE_K(1024)>; - }; - - /* Reserve 256kB for the scratch partition */ - scratch_partition: partition@210000 { - label = "image-scratch"; - reg = <0x00210000 DT_SIZE_K(256)>; - }; - - storage_partition: partition@250000 { - label = "storage"; - reg = <0x00250000 DT_SIZE_K(24)>; - }; - }; -}; - &esp32_bt_hci { status = "okay"; }; diff --git a/boards/olimex/olimex_esp32_evb/olimex_esp32_evb_procpu.yaml b/boards/olimex/olimex_esp32_evb/olimex_esp32_evb_procpu.yaml index c897a546214..3084a2cf60c 100644 --- a/boards/olimex/olimex_esp32_evb/olimex_esp32_evb_procpu.yaml +++ b/boards/olimex/olimex_esp32_evb/olimex_esp32_evb_procpu.yaml @@ -13,8 +13,4 @@ supported: - spi - uart - watchdog -testing: - ignore_tags: - - net - - bluetooth vendor: olimex diff --git a/boards/olimex/olimexino_stm32/doc/index.rst b/boards/olimex/olimexino_stm32/doc/index.rst index 913b6faa8d6..af42d6b0ac1 100644 --- a/boards/olimex/olimexino_stm32/doc/index.rst +++ b/boards/olimex/olimexino_stm32/doc/index.rst @@ -1,7 +1,4 @@ -.. _olimexino_stm32: - -OLIMEXINO-STM32 -############### +.. zephyr:board:: olimexino_stm32 Overview ******** @@ -9,12 +6,6 @@ Overview The OLIMEXINO-STM32 board is based on the STMicroelectronics STM32F103RB ARM Cortex-M3 CPU. -.. figure:: img/olimexino_stm32.jpg - :align: center - :alt: OLIMEXINO-STM32 - - OLIMEXINO-STM32 - More information about the board can be found at the `OLIMEXINO-STM32 website`_ and `OLIMEXINO-STM32 user manual`_. The `ST STM32F103xB Datasheet`_ contains the processor's diff --git a/boards/olimex/olimexino_stm32/olimexino_stm32.dts b/boards/olimex/olimexino_stm32/olimexino_stm32.dts index 8c3a3b1491a..604c58a94fa 100644 --- a/boards/olimex/olimexino_stm32/olimexino_stm32.dts +++ b/boards/olimex/olimexino_stm32/olimexino_stm32.dts @@ -136,6 +136,7 @@ uext_serial: &usart1 {}; spi-max-frequency = <24000000>; mmc { compatible = "zephyr,sdmmc-disk"; + disk-name = "SD"; status = "okay"; }; }; diff --git a/boards/olimex/stm32_e407/doc/index.rst b/boards/olimex/stm32_e407/doc/index.rst index 6af85cf75e0..98a698b3c14 100644 --- a/boards/olimex/stm32_e407/doc/index.rst +++ b/boards/olimex/stm32_e407/doc/index.rst @@ -1,7 +1,4 @@ -.. _olimex_stm32_e407: - -OLIMEX-STM32-E407 -################# +.. zephyr:board:: olimex_stm32_e407 Overview ******** @@ -9,12 +6,6 @@ Overview The OLIMEX-STM32-E407 board is open source hardware and is based on the STMicroelectronics STM32F407ZG ARM Cortex-M4 CPU. -.. figure:: img/olimex_stm32_e407.jpg - :align: center - :alt: OLIMEX-STM32-E407 - - OLIMEX-STM32-E407 - Hardware ******** diff --git a/boards/olimex/stm32_h103/doc/img/olimex_stm32_h103_bottom.jpg b/boards/olimex/stm32_h103/doc/img/olimex_stm32_h103_bottom.jpg deleted file mode 100644 index 829a9b3396a..00000000000 Binary files a/boards/olimex/stm32_h103/doc/img/olimex_stm32_h103_bottom.jpg and /dev/null differ diff --git a/boards/olimex/stm32_h103/doc/index.rst b/boards/olimex/stm32_h103/doc/index.rst index 291b34bfc34..3055207f476 100644 --- a/boards/olimex/stm32_h103/doc/index.rst +++ b/boards/olimex/stm32_h103/doc/index.rst @@ -1,7 +1,4 @@ -.. _olimex_stm32_h103: - -OLIMEX-STM32-H103 -################# +.. zephyr:board:: olimex_stm32_h103 Overview ******** @@ -10,16 +7,6 @@ The OLIMEX-STM32-H103 is a simple development board based on the STMicroelectronics STM32F103RBT6 ARM Cortex-M3 CPU, with all the MCU pins populated and accessible through two male 26-pin connectors. -.. figure:: img/olimex_stm32_h103_top.jpg - :align: center - :alt: OLIMEX-STM32-H103 top - -.. figure:: img/olimex_stm32_h103_bottom.jpg - :align: center - :alt: OLIMEX-STM32-H103 bottom - - OLIMEX-STM32-H103 - Hardware ******** diff --git a/boards/olimex/stm32_h405/doc/index.rst b/boards/olimex/stm32_h405/doc/index.rst index ff3c8b2bf46..4d06e17c991 100644 --- a/boards/olimex/stm32_h405/doc/index.rst +++ b/boards/olimex/stm32_h405/doc/index.rst @@ -1,7 +1,4 @@ -.. _olimex_stm32_h405: - -OLIMEX-STM32-H405 -################# +.. zephyr:board:: olimex_stm32_h405 Overview ******** @@ -9,18 +6,6 @@ Overview The OLIMEX-STM32-H405 board is based on the STMicroelectronics STM32F405RG ARM Cortex-M4 CPU. -.. figure:: olimex_stm32_h405_top.jpg - :align: center - :alt: OLIMEX-STM32-H405 - - OLIMEX-STM32-H405 top - -.. figure:: olimex_stm32_h405_bottom.jpg - :align: center - :alt: OLIMEX-STM32-H405 - - OLIMEX-STM32-H405 bottom - Hardware ******** diff --git a/boards/olimex/stm32_h405/doc/olimex_stm32_h405_bottom.jpg b/boards/olimex/stm32_h405/doc/olimex_stm32_h405_bottom.jpg deleted file mode 100644 index 8c275f128bf..00000000000 Binary files a/boards/olimex/stm32_h405/doc/olimex_stm32_h405_bottom.jpg and /dev/null differ diff --git a/boards/olimex/stm32_h407/doc/index.rst b/boards/olimex/stm32_h407/doc/index.rst index 114543e27cf..13ad7db8ce3 100644 --- a/boards/olimex/stm32_h407/doc/index.rst +++ b/boards/olimex/stm32_h407/doc/index.rst @@ -1,7 +1,4 @@ -.. _olimex_stm32_h407: - -OLIMEX-STM32-H407 -################# +.. zephyr:board:: olimex_stm32_h407 Overview ******** diff --git a/boards/olimex/stm32_p405/doc/index.rst b/boards/olimex/stm32_p405/doc/index.rst index c754213c954..87a3d409d59 100644 --- a/boards/olimex/stm32_p405/doc/index.rst +++ b/boards/olimex/stm32_p405/doc/index.rst @@ -1,7 +1,4 @@ -.. _olimex_stm32_p405: - -OLIMEX-STM32-P405 -################# +.. zephyr:board:: olimex_stm32_p405 Overview ******** @@ -9,12 +6,6 @@ Overview The OLIMEX-STM32-P405 board is based on the STMicroelectronics STM32F405RG ARM Cortex-M4 CPU. -.. figure:: img/olimex_stm32_p405.jpg - :align: center - :alt: OLIMEX-STM32-P405 - - OLIMEX-STM32-P405 - Hardware ******** diff --git a/boards/olimex/stm32_p405/olimex_stm32_p405_defconfig b/boards/olimex/stm32_p405/olimex_stm32_p405_defconfig index a6763abd156..51eadcb4809 100644 --- a/boards/olimex/stm32_p405/olimex_stm32_p405_defconfig +++ b/boards/olimex/stm32_p405/olimex_stm32_p405_defconfig @@ -14,5 +14,3 @@ CONFIG_UART_CONSOLE=y # enable GPIO CONFIG_GPIO=y - -CONFIG_ENTROPY_GENERATOR=y diff --git a/boards/openisa/rv32m1_vega/Kconfig.defconfig b/boards/openisa/rv32m1_vega/Kconfig.defconfig index 08279d8ed04..c6a785858b5 100644 --- a/boards/openisa/rv32m1_vega/Kconfig.defconfig +++ b/boards/openisa/rv32m1_vega/Kconfig.defconfig @@ -5,9 +5,6 @@ if BOARD_RV32M1_VEGA if BT -config BT_CTLR - default y - #TODO: Resolve the complete non-BLE support for crypto CAU3 firmware/driver #config HAS_RV32M1_CAU3 # bool diff --git a/boards/openisa/rv32m1_vega/doc/index.rst b/boards/openisa/rv32m1_vega/doc/index.rst index a8ff0b6c4b8..d5cf180bb1b 100644 --- a/boards/openisa/rv32m1_vega/doc/index.rst +++ b/boards/openisa/rv32m1_vega/doc/index.rst @@ -1,9 +1,6 @@ .. highlight:: sh -.. _rv32m1_vega: - -OpenISA VEGAboard -################# +.. zephyr:board:: rv32m1_vega Overview ******** @@ -13,12 +10,6 @@ on-die XIP flash, and a full complement of peripherals, including a 2.4 GHz multi-protocol radio. It also has built-in sensors and Arduino-style expansion connectors. -.. figure:: rv32m1_vega.jpg - :align: center - :alt: RV32M1-VEGA - - OpenISA VEGAboard (image copyright: www.open-isa.org) - The two RISC-V CPUs are named RI5CY and ZERO-RISCY, and are respectively based on the `PULP platform`_ designs by the same names: `RI5CY`_ and `ZERO-RISCY`_. RI5CY is the "main" core; it has more diff --git a/boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1_ri5cy_defconfig b/boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1_ri5cy_defconfig index 908f07c0198..085a1552710 100644 --- a/boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1_ri5cy_defconfig +++ b/boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1_ri5cy_defconfig @@ -2,7 +2,6 @@ # Copyright 2018 Foundries.io Ltd CONFIG_GPIO=y -CONFIG_PINCTRL=y CONFIG_SERIAL=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y diff --git a/boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1_zero_riscy_defconfig b/boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1_zero_riscy_defconfig index 908f07c0198..085a1552710 100644 --- a/boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1_zero_riscy_defconfig +++ b/boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1_zero_riscy_defconfig @@ -2,7 +2,6 @@ # Copyright 2018 Foundries.io Ltd CONFIG_GPIO=y -CONFIG_PINCTRL=y CONFIG_SERIAL=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y diff --git a/boards/others/black_f407ve/black_f407ve.yaml b/boards/others/black_f407ve/black_f407ve.yaml index 580b22630df..3b37380ff48 100644 --- a/boards/others/black_f407ve/black_f407ve.yaml +++ b/boards/others/black_f407ve/black_f407ve.yaml @@ -12,6 +12,5 @@ supported: - can - pwm - counter - - usb - spi - gpio diff --git a/boards/others/black_f407ve/doc/index.rst b/boards/others/black_f407ve/doc/index.rst index cffdd4d41be..f6f088b3998 100644 --- a/boards/others/black_f407ve/doc/index.rst +++ b/boards/others/black_f407ve/doc/index.rst @@ -1,7 +1,4 @@ -.. _black_f407ve_board: - -Black STM32 F407VE Development Board -#################################### +.. zephyr:board:: black_f407ve Overview ******** @@ -27,10 +24,6 @@ Here are some highlights of the BLACK_F407VE board: - Four push-buttons: RESET, K0, K1 and WK_UP - Mini-AB connector -.. image:: img/black_f407ve.jpg - :align: center - :alt: BLACK_F407VE - See also board descriptions at `STM32-base website`_, `STM32F407VET6 black board`_ and `MCUDev Black STM32F407VET6`_ diff --git a/boards/others/black_f407zg_pro/black_f407zg_pro.yaml b/boards/others/black_f407zg_pro/black_f407zg_pro.yaml index c551916e8ac..a686cf3a54c 100644 --- a/boards/others/black_f407zg_pro/black_f407zg_pro.yaml +++ b/boards/others/black_f407zg_pro/black_f407zg_pro.yaml @@ -12,6 +12,5 @@ supported: - can - pwm - counter - - usb - spi - gpio diff --git a/boards/others/black_f407zg_pro/doc/index.rst b/boards/others/black_f407zg_pro/doc/index.rst index 4857e8bb8da..ec7e6313c10 100644 --- a/boards/others/black_f407zg_pro/doc/index.rst +++ b/boards/others/black_f407zg_pro/doc/index.rst @@ -1,7 +1,4 @@ -.. _black_f407zg_pro_board: - -Black STM32 F407ZG Pro Development Board -######################################## +.. zephyr:board:: black_f407zg_pro Overview ******** @@ -27,10 +24,6 @@ Here are some highlights of the BLACK_F407ZG_PRO board: - Four push-buttons: RESET, K0, K1 and WK_UP - Mini-AB connector -.. image:: img/black_f407zg_pro.jpg - :align: center - :alt: BLACK_F407ZG_PRO - .. warning:: The +5V pins on this board are directly connected to the +5V pin of the USB connector. There is no protection in place. Do not power this board through USB and an external power supply at diff --git a/boards/others/candlelight/Kconfig.candlelight b/boards/others/candlelight/Kconfig.candlelight new file mode 100644 index 00000000000..e941cb7a473 --- /dev/null +++ b/boards/others/candlelight/Kconfig.candlelight @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Henrik Brix Andersen +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_CANDLELIGHT + select SOC_STM32F072XB diff --git a/boards/others/candlelight/board.cmake b/boards/others/candlelight/board.cmake new file mode 100644 index 00000000000..c383530f74c --- /dev/null +++ b/boards/others/candlelight/board.cmake @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Henrik Brix Andersen +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(dfu-util "--pid=0483:df11" "--alt=0" "--dfuse") +board_runner_args(jlink "--device=STM32F072CB") + +include(${ZEPHYR_BASE}/boards/common/dfu-util.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/others/candlelight/board.yml b/boards/others/candlelight/board.yml new file mode 100644 index 00000000000..aaea4c39edb --- /dev/null +++ b/boards/others/candlelight/board.yml @@ -0,0 +1,6 @@ +board: + name: candlelight + full_name: candleLight + vendor: others + socs: + - name: stm32f072xb diff --git a/boards/others/candlelight/candlelight.dts b/boards/others/candlelight/candlelight.dts new file mode 100644 index 00000000000..ae1d7208615 --- /dev/null +++ b/boards/others/candlelight/candlelight.dts @@ -0,0 +1,96 @@ +/* + * Copyright (c) 2024 Henrik Brix Andersen + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include + +/ { + model = "candleLight"; + compatible = "candlelight"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + zephyr,canbus = &can1; + }; + + aliases { + led0 = &led_rx; + led1 = &led_tx; + }; + + leds { + compatible = "gpio-leds"; + led_rx: led_rx { + gpios = <&gpioa 0 GPIO_ACTIVE_LOW>; + label = "LED RX"; + }; + led_tx: led_tx { + gpios = <&gpioa 1 GPIO_ACTIVE_LOW>; + label = "LED TX"; + }; + }; + + transceiver0: can-phy0 { + compatible = "nxp,tja1051", "can-transceiver-gpio"; + enable-gpios = <&gpioc 13 GPIO_ACTIVE_LOW>; + max-bitrate = <1000000>; + #phy-cells = <0>; + }; +}; + +&clk_hsi { + status = "okay"; + clock-frequency = ; +}; + +&pll { + prediv = <1>; + mul = <6>; + clocks = <&clk_hsi>; + status = "okay"; +}; + +&rcc { + clocks = <&pll>; + clock-frequency = ; + ahb-prescaler = <1>; + apb1-prescaler = <1>; +}; + +zephyr_udc0: &usb { + pinctrl-0 = <&usb_dm_pa11 &usb_dp_pa12>; + pinctrl-names = "default"; + status = "okay"; +}; + +&can1 { + pinctrl-0 = <&can_rx_pb8 &can_tx_pb9>; + pinctrl-names = "default"; + phys = <&transceiver0>; + status = "okay"; +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 DT_SIZE_K(48)>; + read-only; + }; + slot0_partition: partition@c000 { + label = "image-0"; + reg = <0x0000c000 DT_SIZE_K(80)>; + }; + }; +}; diff --git a/boards/others/candlelight/candlelight.yaml b/boards/others/candlelight/candlelight.yaml new file mode 100644 index 00000000000..aaf11b3f977 --- /dev/null +++ b/boards/others/candlelight/candlelight.yaml @@ -0,0 +1,15 @@ +identifier: candlelight +name: candleLight +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb +ram: 16 +flash: 128 +supported: + - can + - gpio + - usb_device + - usbd +vendor: others diff --git a/boards/others/candlelight/candlelight_defconfig b/boards/others/candlelight/candlelight_defconfig new file mode 100644 index 00000000000..91c3c15b37d --- /dev/null +++ b/boards/others/candlelight/candlelight_defconfig @@ -0,0 +1 @@ +CONFIG_GPIO=y diff --git a/boards/others/candlelight/doc/candlelight.webp b/boards/others/candlelight/doc/candlelight.webp new file mode 100644 index 00000000000..e54d14a4831 Binary files /dev/null and b/boards/others/candlelight/doc/candlelight.webp differ diff --git a/boards/others/candlelight/doc/index.rst b/boards/others/candlelight/doc/index.rst new file mode 100644 index 00000000000..ac61b2a5eed --- /dev/null +++ b/boards/others/candlelight/doc/index.rst @@ -0,0 +1,65 @@ +.. zephyr:board:: candlelight + +Overview +******** + +The candleLight is an open-hardware USB to CAN 2.0B adapter board available from a number of +sources. + +Hardware +******** + +The candleLight board is equipped with a STM32F072CB microcontroller and features an USB connector, +a DB-9M connector for the CAN bus, and two user LEDs. Schematics and component placement drawings +are available in the `candleLight GitHub repository`_. + +Supported Features +================== + +The ``candlelight`` board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| USB | on-chip | USB | ++-----------+------------+-------------------------------------+ +| CAN1 | on-chip | CAN controller | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/others/candlelight/candlelight_defconfig`. + +Other hardware features are not currently supported by the port. + +System Clock +============ + +The STM32F072CB PLL is driven by the internal RC oscillator (HSI) running at 8 MHz and +configured to provide a system clock of 48 MHz. + +Programming and Debugging +************************* + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +If flashing via USB DFU, short resistor ``R203`` when applying power to the candleLight in order to +enter the built-in DFU mode. + +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: candlelight + :goals: flash + +.. _candleLight GitHub repository: + https://github.com/HubertD/candleLight diff --git a/boards/others/candlelightfd/Kconfig.candlelightfd b/boards/others/candlelightfd/Kconfig.candlelightfd new file mode 100644 index 00000000000..ec6bb9d40a8 --- /dev/null +++ b/boards/others/candlelightfd/Kconfig.candlelightfd @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Sean Nyekjaer +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_CANDLELIGHTFD + select SOC_STM32G0B1XX diff --git a/boards/others/candlelightfd/board.cmake b/boards/others/candlelightfd/board.cmake new file mode 100644 index 00000000000..f52f1430d4c --- /dev/null +++ b/boards/others/candlelightfd/board.cmake @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Sean Nyekjaer +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(dfu-util "--pid=0483:df11" "--alt=0" "--dfuse") +board_runner_args(jlink "--device=STM32G0B1CB") + +include(${ZEPHYR_BASE}/boards/common/dfu-util.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/others/candlelightfd/board.yml b/boards/others/candlelightfd/board.yml new file mode 100644 index 00000000000..089e2a8bbaf --- /dev/null +++ b/boards/others/candlelightfd/board.yml @@ -0,0 +1,8 @@ +board: + name: candlelightfd + full_name: candleLightFD + vendor: others + socs: + - name: stm32g0b1xx + variants: + - name: 'dual' diff --git a/boards/others/candlelightfd/candlelightfd.dtsi b/boards/others/candlelightfd/candlelightfd.dtsi new file mode 100644 index 00000000000..0e87cfadbab --- /dev/null +++ b/boards/others/candlelightfd/candlelightfd.dtsi @@ -0,0 +1,101 @@ +/* + * Copyright (c) 2024 Sean Nyekjaer + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + zephyr,canbus = &fdcan1; + }; + + aliases { + led0 = &led_rx; + led1 = &led_tx; + }; + + leds { + compatible = "gpio-leds"; + led_rx: led_rx { + gpios = <&gpioa 3 GPIO_ACTIVE_LOW>; + label = "LED RX"; + }; + led_tx: led_tx { + gpios = <&gpioa 4 GPIO_ACTIVE_LOW>; + label = "LED TX"; + }; + }; + + transceiver0: can-phy0 { + compatible = "nxp,tja1051", "can-transceiver-gpio"; + enable-gpios = <&gpioa 15 GPIO_ACTIVE_LOW>; + max-bitrate = <5000000>; + #phy-cells = <0>; + }; +}; + +&clk_hse { + status = "okay"; + clock-frequency = ; +}; + +&clk_hsi48 { + status = "okay"; + crs-usb-sof; +}; + +&pll { + div-m = <1>; + mul-n = <30>; + div-p = <2>; + div-q = <3>; + div-r = <4>; + clocks = <&clk_hse>; + status = "okay"; +}; + +&rcc { + clocks = <&pll>; + clock-frequency = ; + ahb-prescaler = <1>; + apb1-prescaler = <1>; +}; + +zephyr_udc0: &usb { + pinctrl-0 = <&usb_dm_pa11 &usb_dp_pa12>; + pinctrl-names = "default"; + status = "okay"; +}; + +&fdcan1 { + clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00001000>, + <&rcc STM32_SRC_PLL_Q FDCAN_SEL(1)>; + pinctrl-0 = <&fdcan1_rx_pd0 &fdcan1_tx_pd1>; + pinctrl-names = "default"; + phys = <&transceiver0>; + status = "okay"; +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 DT_SIZE_K(48)>; + read-only; + }; + slot0_partition: partition@c000 { + label = "image-0"; + reg = <0x0000c000 DT_SIZE_K(80)>; + }; + }; +}; diff --git a/boards/others/candlelightfd/candlelightfd_stm32g0b1xx.dts b/boards/others/candlelightfd/candlelightfd_stm32g0b1xx.dts new file mode 100644 index 00000000000..ce8b6cc46b2 --- /dev/null +++ b/boards/others/candlelightfd/candlelightfd_stm32g0b1xx.dts @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2024 Sean Nyekjaer + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include "candlelightfd.dtsi" + +/ { + model = "candleLight FD"; + compatible = "candlelightfd"; +}; diff --git a/boards/others/candlelightfd/candlelightfd_stm32g0b1xx.yaml b/boards/others/candlelightfd/candlelightfd_stm32g0b1xx.yaml new file mode 100644 index 00000000000..b017c2bb538 --- /dev/null +++ b/boards/others/candlelightfd/candlelightfd_stm32g0b1xx.yaml @@ -0,0 +1,10 @@ +identifier: candlelightfd/stm32g0b1xx +name: candleLightFD +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb +ram: 144 +flash: 128 +vendor: others diff --git a/boards/others/candlelightfd/candlelightfd_stm32g0b1xx_defconfig b/boards/others/candlelightfd/candlelightfd_stm32g0b1xx_defconfig new file mode 100644 index 00000000000..8cb5d0f6364 --- /dev/null +++ b/boards/others/candlelightfd/candlelightfd_stm32g0b1xx_defconfig @@ -0,0 +1,8 @@ +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable HW stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable GPIO +CONFIG_GPIO=y diff --git a/boards/others/candlelightfd/candlelightfd_stm32g0b1xx_dual.dts b/boards/others/candlelightfd/candlelightfd_stm32g0b1xx_dual.dts new file mode 100644 index 00000000000..2e2767dd536 --- /dev/null +++ b/boards/others/candlelightfd/candlelightfd_stm32g0b1xx_dual.dts @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2024 Sean Nyekjaer + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include "candlelightfd.dtsi" + +/ { + model = "candleLight FD Dual"; + compatible = "candlelightfd"; + + transceiver1: can-phy1 { + compatible = "nxp,tja1051", "can-transceiver-gpio"; + enable-gpios = <&gpiob 2 GPIO_ACTIVE_LOW>; + max-bitrate = <5000000>; + #phy-cells = <0>; + }; +}; + +&fdcan2 { + clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00001000>, + <&rcc STM32_SRC_PLL_Q FDCAN_SEL(1)>; + pinctrl-0 = <&fdcan2_rx_pb0 &fdcan2_tx_pb1>; + pinctrl-names = "default"; + phys = <&transceiver1>; + status = "okay"; +}; diff --git a/boards/others/candlelightfd/candlelightfd_stm32g0b1xx_dual.yaml b/boards/others/candlelightfd/candlelightfd_stm32g0b1xx_dual.yaml new file mode 100644 index 00000000000..7841d562cb8 --- /dev/null +++ b/boards/others/candlelightfd/candlelightfd_stm32g0b1xx_dual.yaml @@ -0,0 +1,10 @@ +identifier: candlelightfd/stm32g0b1xx/dual +name: candleLightFD Dual +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb +ram: 144 +flash: 128 +vendor: others diff --git a/boards/others/candlelightfd/candlelightfd_stm32g0b1xx_dual_defconfig b/boards/others/candlelightfd/candlelightfd_stm32g0b1xx_dual_defconfig new file mode 100644 index 00000000000..8cb5d0f6364 --- /dev/null +++ b/boards/others/candlelightfd/candlelightfd_stm32g0b1xx_dual_defconfig @@ -0,0 +1,8 @@ +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable HW stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable GPIO +CONFIG_GPIO=y diff --git a/boards/others/candlelightfd/doc/candlelightfd.webp b/boards/others/candlelightfd/doc/candlelightfd.webp new file mode 100644 index 00000000000..08313925065 Binary files /dev/null and b/boards/others/candlelightfd/doc/candlelightfd.webp differ diff --git a/boards/others/candlelightfd/doc/index.rst b/boards/others/candlelightfd/doc/index.rst new file mode 100644 index 00000000000..ea622f4db72 --- /dev/null +++ b/boards/others/candlelightfd/doc/index.rst @@ -0,0 +1,77 @@ +.. zephyr:board:: candlelightfd + +Overview +******** + +The candleLight FD is an open-hardware USB to CAN FD adapter board available from Linux Automation GmBH. +Find more information about the board at the `Linux Automation website`_. + +Hardware +******** + +The candleLight FD board is equipped with a STM32G0B1CBT6 microcontroller and features an USB-C connector, +a DB-9M connector for the CAN bus, and two user LEDs. Schematics and component placement drawings +are available in the `candleLight FD GitHub repository`_. + +Supported Features +================== + +The ``candlelightfd/stm32g0b1xx`` board target supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| USB | on-chip | USB | ++-----------+------------+-------------------------------------+ +| CAN1 | on-chip | CAN controller | ++-----------+------------+-------------------------------------+ +| CAN2 | on-chip | CAN controller | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/others/candlelightfd/candlelightfd_stm32g0b1xx_defconfig`. + +System Clock +============ + +The STM32G0B1CBT6 PLL is driven by an external crystal oscillator (HSE) running at 8 MHz and +configured to provide a system clock of 60 MHz. This allows generating a FDCAN1 and FDCAN2 core +clock of 80 MHz. + +Programming and Debugging +************************* + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +If flashing via USB DFU, short jumper ``BOOT`` when applying power to the candleLight FD in order to +enter the built-in DFU mode. + +Variants +======== + +The candleLight FD is can be retrofitted with a second transceiver, making it a dual CAN FD device: + +- ``candlelightfd``: The default variant. +- ``candlelightfd_stm32g0b1xx_dual``: Variant for the dual CAN FD. + +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: candlelightfd + :goals: flash + +.. _Linux Automation website: + https://linux-automation.com/en/products/candlelight-fd.html + +.. _candleLight FD GitHub repository: + https://github.com/linux-automation/candleLightFD diff --git a/boards/others/esp32c3_supermini/Kconfig b/boards/others/esp32c3_supermini/Kconfig new file mode 100644 index 00000000000..d7b9f494bc9 --- /dev/null +++ b/boards/others/esp32c3_supermini/Kconfig @@ -0,0 +1,8 @@ +# ESP32C3 supermini board configuration + +# Copyright (c) 2024 Arrel Neumiller +# SPDX-License-Identifier: Apache-2.0 + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 4096 diff --git a/boards/others/esp32c3_supermini/Kconfig.esp32c3_supermini b/boards/others/esp32c3_supermini/Kconfig.esp32c3_supermini new file mode 100644 index 00000000000..3b1718b1480 --- /dev/null +++ b/boards/others/esp32c3_supermini/Kconfig.esp32c3_supermini @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Arrel Neumiller +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ESP32C3_SUPERMINI + select SOC_ESP32C3_FH4 diff --git a/boards/others/esp32c3_supermini/Kconfig.sysbuild b/boards/others/esp32c3_supermini/Kconfig.sysbuild new file mode 100644 index 00000000000..f4b8b8fb2be --- /dev/null +++ b/boards/others/esp32c3_supermini/Kconfig.sysbuild @@ -0,0 +1,10 @@ +# Copyright (c) 2024 Arrel Neumiller +# SPDX-License-Identifier: Apache-2.0 + +choice BOOTLOADER + default BOOTLOADER_MCUBOOT +endchoice + +choice BOOT_SIGNATURE_TYPE + default BOOT_SIGNATURE_TYPE_NONE +endchoice diff --git a/boards/others/esp32c3_supermini/board.cmake b/boards/others/esp32c3_supermini/board.cmake new file mode 100644 index 00000000000..4c8b1b1822e --- /dev/null +++ b/boards/others/esp32c3_supermini/board.cmake @@ -0,0 +1,10 @@ +# Copyright (c) 2024 Arrel Neumiller +# SPDX-License-Identifier: Apache-2.0 + +if(NOT "${OPENOCD}" MATCHES "^${ESPRESSIF_TOOLCHAIN_PATH}/.*") + set(OPENOCD OPENOCD-NOTFOUND) +endif() +find_program(OPENOCD openocd PATHS ${ESPRESSIF_TOOLCHAIN_PATH}/openocd-esp32/bin NO_DEFAULT_PATH) + +include(${ZEPHYR_BASE}/boards/common/esp32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/others/esp32c3_supermini/board.yml b/boards/others/esp32c3_supermini/board.yml new file mode 100644 index 00000000000..ee28029260b --- /dev/null +++ b/boards/others/esp32c3_supermini/board.yml @@ -0,0 +1,9 @@ +# Copyright (c) 2024 Arrel Neumiller +# SPDX-License-Identifier: Apache-2.0 + +board: + name: esp32c3_supermini + full_name: ESP32-C3-SUPERMINI + vendor: others + socs: + - name: esp32c3 diff --git a/boards/others/esp32c3_supermini/doc/img/esp32c3_supermini.webp b/boards/others/esp32c3_supermini/doc/img/esp32c3_supermini.webp new file mode 100644 index 00000000000..59e34716261 Binary files /dev/null and b/boards/others/esp32c3_supermini/doc/img/esp32c3_supermini.webp differ diff --git a/boards/others/esp32c3_supermini/doc/index.rst b/boards/others/esp32c3_supermini/doc/index.rst new file mode 100644 index 00000000000..7a7ff21dbd1 --- /dev/null +++ b/boards/others/esp32c3_supermini/doc/index.rst @@ -0,0 +1,249 @@ +.. zephyr:board:: esp32c3_supermini + +Overview +******** + +ESP32-C3-SUPERMINI is based on the ESP32-C3, a single-core Wi-Fi and Bluetooth 5 (LE) microcontroller SoC, +based on the open-source RISC-V architecture. This board also includes a Type-C USB Serial/JTAG port. +There may be multiple variations depending on the specific vendor. For more information a reasonbly well documented version of this board can be found at `ESP32-C3-SUPERMINI`_ + +Hardware +******** + +SoC Features: + +- IEEE 802.11 b/g/n-compliant +- Bluetooth 5, Bluetooth mesh +- 32-bit RISC-V single-core processor, up to 160MHz +- 384 KB ROM +- 400 KB SRAM (16 KB for cache) +- 8 KB SRAM in RTC +- 22 x programmable GPIOs +- 3 x SPI +- 2 x UART +- 1 x I2C +- 1 x I2S +- 2 x 54-bit general-purpose timers +- 3 x watchdog timers +- 1 x 52-bit system timer +- Remote Control Peripheral (RMT) +- LED PWM controller (LEDC) +- Full-speed USB Serial/JTAG controller +- General DMA controller (GDMA) +- 1 x TWAI® +- 2 x 12-bit SAR ADCs, up to 6 channels +- 1 x soc core temperature sensor + +For more information on the ESP32-C3 SOC, check the datasheet at `ESP32-C3 Datasheet`_ or the technical reference +manual at `ESP32-C3 Technical Reference Manual`_. + +Supported Features +================== + +Currently Zephyr's ``esp32c3_supermini`` board target supports the following features: + ++------------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++============+============+=====================================+ +| UART | on-chip | serial port | ++------------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++------------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++------------+------------+-------------------------------------+ +| USB-JTAG | on-chip | hardware interface | ++------------+------------+-------------------------------------+ +| SPI Master | on-chip | spi | ++------------+------------+-------------------------------------+ +| Timers | on-chip | counter | ++------------+------------+-------------------------------------+ +| Watchdog | on-chip | watchdog | ++------------+------------+-------------------------------------+ +| TRNG | on-chip | entropy | ++------------+------------+-------------------------------------+ +| LEDC | on-chip | pwm | ++------------+------------+-------------------------------------+ +| SPI DMA | on-chip | spi | ++------------+------------+-------------------------------------+ +| TWAI | on-chip | can | ++------------+------------+-------------------------------------+ +| USB-CDC | on-chip | serial | ++------------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++------------+------------+-------------------------------------+ +| Wi-Fi | on-chip | | ++------------+------------+-------------------------------------+ +| Bluetooth | on-chip | | ++------------+------------+-------------------------------------+ + +System requirements +******************* + +Prerequisites +============= + +Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command +below to retrieve those files. + +.. code-block:: console + + west blobs fetch hal_espressif + +.. note:: + + It is recommended running the command above after :file:`west update`. + +Building & Flashing +******************* + +Simple boot +=========== + +The board could be loaded using the single binary image, without 2nd stage bootloader. +It is the default option when building the application without additional configuration. + +.. note:: + + Simple boot does not provide any security features nor OTA updates. + +MCUboot bootloader +================== + +User may choose to use MCUboot bootloader instead. In that case the bootloader +must be built (and flashed) at least once. + +There are two options to be used when building an application: + +1. Sysbuild +2. Manual build + +.. note:: + + User can select the MCUboot bootloader by adding the following line + to the board default configuration file. + + .. code:: cfg + + CONFIG_BOOTLOADER_MCUBOOT=y + +Sysbuild +======== + +The sysbuild makes possible to build and flash all necessary images needed to +bootstrap the board with the ESP32 SoC. + +To build the sample application using sysbuild use the command: + +.. zephyr-app-commands:: + :tool: west + :zephyr-app: samples/hello_world + :board: esp32c3_supermini + :goals: build + :west-args: --sysbuild + :compact: + +By default, the ESP32 sysbuild creates bootloader (MCUboot) and application +images. But it can be configured to create other kind of images. + +Build directory structure created by sysbuild is different from traditional +Zephyr build. Output is structured by the domain subdirectories: + +.. code-block:: + + build/ + ├── hello_world + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + ├── mcuboot + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + └── domains.yaml + +.. note:: + + With ``--sysbuild`` option the bootloader will be re-build and re-flash + every time the pristine build is used. + +For more information about the system build please read the :ref:`sysbuild` documentation. + +Manual build +============ + +During the development cycle, it is intended to build & flash as quickly possible. +For that reason, images can be built one at a time using traditional build. + +The instructions following are relevant for both manual build and sysbuild. +The only difference is the structure of the build directory. + +.. note:: + + Remember that bootloader (MCUboot) needs to be flash at least once. + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32c3_supermini + :goals: build + +The usual ``flash`` target will work with the ``esp32c3_supermini`` board +configuration. Here is an example for the :zephyr:code-sample:`hello_world` +application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32c3_supermini + :goals: flash + +Open the serial monitor using the following command: + +.. code-block:: shell + + west espressif monitor + +After the board has automatically reset and booted, you should see the following +message in the monitor: + +.. code-block:: console + + ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** + Hello World! esp32c3_supermini + +Debugging +********* + +As with much custom hardware, the ESP32-C3 modules require patches to +OpenOCD that are not upstreamed yet. Espressif maintains their own fork of +the project. The custom OpenOCD can be obtained at `OpenOCD ESP32`_. + +The Zephyr SDK uses a bundled version of OpenOCD by default. You can overwrite that behavior by adding the +``-DOPENOCD= -DOPENOCD_DEFAULT_PATH=`` +parameter when building. + +Here is an example for building the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32c3_supermini + :goals: build flash + :gen-args: -DOPENOCD= -DOPENOCD_DEFAULT_PATH= + +You can debug an application in the usual way. Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32c3_supermini + :goals: debug + +References +********** + +.. target-notes:: + +.. _`ESP32-C3-SUPERMINI`: https://www.nologo.tech/product/esp32/esp32c3SuperMini/esp32C3SuperMini.html +.. _`ESP32-C3 Datasheet`: https://www.espressif.com/sites/default/files/documentation/esp32-c3_datasheet_en.pdf +.. _`ESP32-C3 Technical Reference Manual`: https://espressif.com/sites/default/files/documentation/esp32-c3_technical_reference_manual_en.pdf +.. _`OpenOCD ESP32`: https://github.com/espressif/openocd-esp32/releases diff --git a/boards/others/esp32c3_supermini/esp32c3_supermini-pinctrl.dtsi b/boards/others/esp32c3_supermini/esp32c3_supermini-pinctrl.dtsi new file mode 100644 index 00000000000..9ac04070866 --- /dev/null +++ b/boards/others/esp32c3_supermini/esp32c3_supermini-pinctrl.dtsi @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2024 Arrel Neumiller + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +&pinctrl { + + uart0_default: uart0_default { + group1 { + pinmux = ; + output-high; + }; + group2 { + pinmux = ; + bias-pull-up; + }; + }; + + spim2_default: spim2_default { + group1 { + pinmux = , + , + ; + }; + group2 { + pinmux = ; + output-low; + }; + }; + + i2c0_default: i2c0_default { + group1 { + pinmux = , + ; + bias-pull-up; + drive-open-drain; + output-high; + }; + }; +}; diff --git a/boards/others/esp32c3_supermini/esp32c3_supermini.dts b/boards/others/esp32c3_supermini/esp32c3_supermini.dts new file mode 100644 index 00000000000..ebbd64d4f81 --- /dev/null +++ b/boards/others/esp32c3_supermini/esp32c3_supermini.dts @@ -0,0 +1,91 @@ +/* + * Copyright (c) 2024 Arrel Neumiller + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "esp32c3_supermini-pinctrl.dtsi" +#include +#include +#include + +/ { + model = "ESP32C3-SUPERMINI"; + compatible = "espressif,esp32c3_supermini"; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &usb_serial; + zephyr,shell-uart = &usb_serial; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + }; + + aliases { + led0 = &blue_led_0; + sw0 = &user_button1; + i2c-0 = &i2c0; + watchdog0 = &wdt0; + }; + + gpio_keys { + compatible = "gpio-keys"; + user_button1: button_1 { + label = "User SW1"; + gpios = <&gpio0 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + zephyr,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + blue_led_0: led_0 { + gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>; + label = "Blue LED 0"; + }; + }; + +}; + +&spi2 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim2_default>; + pinctrl-names = "default"; + +}; + +&usb_serial { + status = "okay"; +}; + + +&i2c0 { + status = "okay"; + clock-frequency = ; + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; +}; + +&trng0 { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&wdt0 { + status = "okay"; +}; + +&uart0 { + status = "disabled"; +}; + +&esp32_bt_hci { + status = "okay"; +}; diff --git a/boards/others/esp32c3_supermini/esp32c3_supermini.yaml b/boards/others/esp32c3_supermini/esp32c3_supermini.yaml new file mode 100644 index 00000000000..edc7252f583 --- /dev/null +++ b/boards/others/esp32c3_supermini/esp32c3_supermini.yaml @@ -0,0 +1,21 @@ +# Copyright (c) 2024 Arrel Neumiller +# SPDX-License-Identifier: Apache-2.0 + +identifier: esp32c3_supermini +name: ESP32-C3-SUPERMINI +type: mcu +arch: riscv +toolchain: + - zephyr +supported: + - adc + - gpio + - i2c + - watchdog + - uart + - dma + - pwm + - spi + - counter + - entropy +vendor: others diff --git a/boards/others/esp32c3_supermini/esp32c3_supermini_defconfig b/boards/others/esp32c3_supermini/esp32c3_supermini_defconfig new file mode 100644 index 00000000000..bf6c07714fa --- /dev/null +++ b/boards/others/esp32c3_supermini/esp32c3_supermini_defconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2024 Arrel Neumiller +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_GPIO=y diff --git a/boards/others/esp32c3_supermini/support/openocd.cfg b/boards/others/esp32c3_supermini/support/openocd.cfg new file mode 100644 index 00000000000..7fa9d136247 --- /dev/null +++ b/boards/others/esp32c3_supermini/support/openocd.cfg @@ -0,0 +1,14 @@ +# Copyright (c) 2024 Arrel Neumiller +# SPDX-License-Identifier: Apache-2.0 + +set ESP_RTOS none + +# ESP32C3 has built-in JTAG interface over USB port in pins GPIO18/GPIO19 (D-/D+). +# Uncomment the line below to enable USB debugging. +#source [find interface/esp_usb_jtag.cfg] + +# Otherwise, use external JTAG programmer as ESP-Prog +source [find interface/ftdi/esp32_devkitj_v1.cfg] + +source [find target/esp32c3.cfg] +adapter speed 5000 diff --git a/boards/others/icev_wireless/Kconfig b/boards/others/icev_wireless/Kconfig new file mode 100644 index 00000000000..78f243a23b2 --- /dev/null +++ b/boards/others/icev_wireless/Kconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2022 Friedt Professional Engineering Services, Inc +# SPDX-License-Identifier: Apache-2.0 + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 4096 diff --git a/boards/others/icev_wireless/Kconfig.defconfig b/boards/others/icev_wireless/Kconfig.defconfig deleted file mode 100644 index b7c82093375..00000000000 --- a/boards/others/icev_wireless/Kconfig.defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2022 Friedt Professional Engineering Services, Inc -# SPDX-License-Identifier: Apache-2.0 - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 65535 if WIFI && BT - default 51200 if WIFI - default 40960 if BT - default 4096 diff --git a/boards/others/icev_wireless/doc/index.rst b/boards/others/icev_wireless/doc/index.rst index 5b56cd94c3d..91c4ee1ff98 100644 --- a/boards/others/icev_wireless/doc/index.rst +++ b/boards/others/icev_wireless/doc/index.rst @@ -1,7 +1,4 @@ -.. _icev_wireless: - -ICE-V Wireless -############## +.. zephyr:board:: icev_wireless Overview ******** @@ -10,12 +7,6 @@ The ICE-V Wireless is a combined ESP32C3 and iCE40 FPGA board. See the `ICE-V Wireless Github Project`_ for details. -.. figure:: img/icev_wireless.jpg - :align: center - :alt: ICE-V Wireless - - ICE-V Wireless - Hardware ******** @@ -244,6 +235,8 @@ You can debug an application in the usual way. Here is an example for the References ********** +.. target-notes:: + .. _ICE-V Wireless Github Project: https://github.com/ICE-V-Wireless/ICE-V-Wireless diff --git a/boards/others/icev_wireless/icev_wireless.dts b/boards/others/icev_wireless/icev_wireless.dts index 6209aeac7c2..b91814c3b43 100644 --- a/boards/others/icev_wireless/icev_wireless.dts +++ b/boards/others/icev_wireless/icev_wireless.dts @@ -9,13 +9,14 @@ #include #include "icev_wireless-pinctrl.dtsi" #include +#include / { model = "ICEV Wireless"; compatible = "espressif,esp32c3"; chosen { - zephyr,sram = &sram0; + zephyr,sram = &sram1; zephyr,console = &usb_serial; zephyr,shell-uart = &usb_serial; zephyr,flash = &flash0; @@ -93,41 +94,6 @@ status = "okay"; }; -&flash0 { - status = "okay"; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x0000F000>; - read-only; - }; - - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 0x00100000>; - }; - - slot1_partition: partition@110000 { - label = "image-1"; - reg = <0x00110000 0x00100000>; - }; - - scratch_partition: partition@210000 { - label = "image-scratch"; - reg = <0x00210000 0x00040000>; - }; - - storage_partition: partition@250000 { - label = "storage"; - reg = <0x00250000 0x00006000>; - }; - }; -}; - &esp32_bt_hci { status = "okay"; }; diff --git a/boards/others/icev_wireless/icev_wireless.yaml b/boards/others/icev_wireless/icev_wireless.yaml index 1850577054c..2ba46d2c763 100644 --- a/boards/others/icev_wireless/icev_wireless.yaml +++ b/boards/others/icev_wireless/icev_wireless.yaml @@ -4,8 +4,4 @@ type: mcu arch: riscv toolchain: - zephyr -testing: - ignore_tags: - - net - - bluetooth vendor: espressif diff --git a/boards/others/neorv32/doc/index.rst b/boards/others/neorv32/doc/index.rst index a2dedba0a76..066377bbf25 100644 --- a/boards/others/neorv32/doc/index.rst +++ b/boards/others/neorv32/doc/index.rst @@ -1,7 +1,4 @@ -.. _neorv32: - -NEORV32 -####### +.. zephyr:board:: neorv32 Overview ******** diff --git a/boards/others/promicro_nrf52840/Kconfig b/boards/others/promicro_nrf52840/Kconfig new file mode 100644 index 00000000000..d49f34b3762 --- /dev/null +++ b/boards/others/promicro_nrf52840/Kconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2024 MASSDRIVER EI (massdriver.space) +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_PROMICRO_NRF52840 + +config BOARD_HAS_NRF5_BOOTLOADER + bool "Board has nRF5 bootloader" + default y + help + If selected, applications are linked so that they can be loaded by Nordic + nRF5 bootloader. + +endif # BOARD_PROMICRO_NRF52840 diff --git a/boards/others/promicro_nrf52840/Kconfig.defconfig b/boards/others/promicro_nrf52840/Kconfig.defconfig new file mode 100644 index 00000000000..85e9768bccc --- /dev/null +++ b/boards/others/promicro_nrf52840/Kconfig.defconfig @@ -0,0 +1,29 @@ +# Copyright (c) 2024 MASSDRIVER EI (massdriver.space) +# Copyright (c) 2018-2023 Nordic Semiconductor ASA +# +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_PROMICRO_NRF52840 + +source "boards/common/usb/Kconfig.cdc_acm_serial.defconfig" + +# To let the nRF5 bootloader load an application, the application +# must be linked after Nordic MBR, that is factory-programmed on the board. + +# Nordic nRF5 bootloader exists outside of the partitions specified in the +# DTS file, so we manually override FLASH_LOAD_OFFSET to link the application +# correctly, after Nordic MBR. + +# When building MCUBoot, MCUBoot itself will select USE_DT_CODE_PARTITION +# which will make it link into the correct partition specified in DTS file, +# the offset is applied here so that the full partition size can be used when +# the bootloader Kconfig option has been disabled. + +config FLASH_LOAD_OFFSET + default 0x1000 + depends on BOARD_HAS_NRF5_BOOTLOADER && (MCUBOOT || !USE_DT_CODE_PARTITION) + +config BT_CTLR + default BT + +endif # BOARD_PROMICRO_NRF52840 diff --git a/boards/others/promicro_nrf52840/Kconfig.promicro_nrf52840 b/boards/others/promicro_nrf52840/Kconfig.promicro_nrf52840 new file mode 100644 index 00000000000..ec026e8a7f7 --- /dev/null +++ b/boards/others/promicro_nrf52840/Kconfig.promicro_nrf52840 @@ -0,0 +1,5 @@ +# Copyright (c) 2024 MASSDRIVER EI (massdriver.space) +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_PROMICRO_NRF52840 + select SOC_NRF52840_QIAA diff --git a/boards/others/promicro_nrf52840/board.cmake b/boards/others/promicro_nrf52840/board.cmake new file mode 100644 index 00000000000..af0f4a93426 --- /dev/null +++ b/boards/others/promicro_nrf52840/board.cmake @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=nRF52840_xxAA" "--speed=4000") +board_runner_args(pyocd "--target=nrf52840" "--frequency=4000000") +if(CONFIG_BUILD_OUTPUT_UF2) + include(${ZEPHYR_BASE}/boards/common/uf2.board.cmake) +endif() +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/others/promicro_nrf52840/board.yml b/boards/others/promicro_nrf52840/board.yml new file mode 100644 index 00000000000..dc4a01a47e4 --- /dev/null +++ b/boards/others/promicro_nrf52840/board.yml @@ -0,0 +1,8 @@ +board: + name: promicro_nrf52840 + full_name: Pro Micro nRF52840 + vendor: others + socs: + - name: nrf52840 + variants: + - name: uf2 diff --git a/boards/others/promicro_nrf52840/doc/img/others_promicro_nrf52840.webp b/boards/others/promicro_nrf52840/doc/img/others_promicro_nrf52840.webp new file mode 100644 index 00000000000..9d81bdc2715 Binary files /dev/null and b/boards/others/promicro_nrf52840/doc/img/others_promicro_nrf52840.webp differ diff --git a/boards/others/promicro_nrf52840/doc/index.rst b/boards/others/promicro_nrf52840/doc/index.rst new file mode 100644 index 00000000000..857644d03d5 --- /dev/null +++ b/boards/others/promicro_nrf52840/doc/index.rst @@ -0,0 +1,190 @@ +.. _promicro_nrf52840_nrf52840: + +Pro Micro nRF52840 +################## + +More of a board type than a unique board, It is based on Nice!Nano. +Also referred to as Pro Micro, Promicro, SuperMini nRF52840 boards. + +Overview +******** + +The hardware provides support for the Nordic +Semiconductor nRF52840 ARM Cortex-M4F CPU and the following devices: + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* RADIO (Bluetooth Low Energy and 802.15.4) +* :abbr:`RTC (nRF RTC System Clock)` +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UART (Universal asynchronous receiver-transmitter)` +* :abbr:`USB (Universal Serial Bus)` +* :abbr:`WDT (Watchdog Timer)` + +.. figure:: img/others_promicro_nrf52840.webp + :align: center + :alt: Tenstar Pro Micro nRF52840 + + Tenstar Pro Micro nRF5284 + +More information about the original board can be found at the +`Nice!Nano website`_. + +Information about clones can be found at `Clone Wiki`_. + +Pinout and Schematic are available in the `Nice!Nano Documentation`_ + + +Supported Features +================== + +The ``promicro_nrf52840/nrf52840`` board target supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth, | +| | | ieee802154 | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| USB | on-chip | usb | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +Connections and IOs +=================== + +LED +--- + +* LED0 = P0.15, can be any color. + +Programming and Debugging +************************* + +Applications for the ``promicro_nrf52840/nrf52840`` board target can be +built in the usual way (see :ref:`build_an_application` for more details). + +Flashing +======== + +The board is factory-programmed with Adafruit's UF2 booloader + +#. Reset the board into the bootloader by bridging ground and RST 2 times +quickly + + The status LED should start a fade pattern, signalling the bootloader is + running. + +#. Compile a Zephyr application; we'll use :zephyr:code-sample:`blinky`. + + .. zephyr-app-commands:: + :app: zephyr/samples/basic/blinky + :board: promicro_nrf52840/nrf52840/uf2 + :goals: build + +#. Flash it onto the board. You may need to mount the device. + + .. code-block:: console + + west flash + + When this command exits, observe the red LED on the board blinking, + + +Debugging +========= + +You may debug this board using the broken out pads on the back. +PyOCD and openOCD can be used to flash and debug this board. + +Recovery +======== + +In case of a error resulting in a board's bootloader becoming inaccessible, +it is possible to flash anything directly using openOCD: + +#. Setup OpenOCD correctly, here for WCH linkE in ARM mode: + + .. code-block:: console + + openocd -f interface/cmsis-dap.cfg -f target/nrf52.cfg + +Note interface and target folders are from openOCD's tcl folder. + +#. Connect to openOCD, for example with telnet or GDB: + + .. code-block:: console + + telnet localhost 4444 + + .. code-block:: console + + target extended-remote localhost:3333 + +#. Erase flash: + + .. code-block:: console + + reset halt + nrf5 mass_erase + +or + + .. code-block:: console + + mon reset halt + mon nrf5 mass_erase + +#. Flash Bootloader + + .. code-block:: console + + flash write_image erase nice_nano_bootloader-0.9.2_s140_6.1.1.hex + +or + + .. code-block:: console + + mon flash write_image erase nice_nano_bootloader-0.9.2_s140_6.1.1.hex + +References +********** + +.. target-notes:: + +.. _Nice!Nano website: + https://nicekeyboards.com/docs/nice-nano/ +.. _Clone Wiki: + https://github.com/joric/nrfmicro/wiki/Alternatives +.. _Nice!Nano Documentation: + https://nicekeyboards.com/docs/nice-nano/pinout-schematic diff --git a/boards/rak/rak4631/pre_dt_board.cmake b/boards/others/promicro_nrf52840/pre_dt_board.cmake similarity index 100% rename from boards/rak/rak4631/pre_dt_board.cmake rename to boards/others/promicro_nrf52840/pre_dt_board.cmake diff --git a/boards/others/promicro_nrf52840/promicro_nrf52840-pinctrl.dtsi b/boards/others/promicro_nrf52840/promicro_nrf52840-pinctrl.dtsi new file mode 100644 index 00000000000..d4e61141803 --- /dev/null +++ b/boards/others/promicro_nrf52840/promicro_nrf52840-pinctrl.dtsi @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2024 MASSDRIVER EI (massdriver.space) + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + uart0_default: uart0_default { + group1 { + psels = , + ; + }; + }; + + uart0_sleep: uart0_sleep { + group1 { + psels = , + ; + low-power-enable; + }; + }; + + i2c0_default: i2c0_default { + group1 { + psels = , + ; + }; + }; + + i2c0_sleep: i2c0_sleep { + group1 { + psels = , + ; + low-power-enable; + }; + }; + + i2c1_default: i2c1_default { + group1 { + psels = , + ; + }; + }; + + i2c1_sleep: i2c1_sleep { + group1 { + psels = , + ; + low-power-enable; + }; + }; + + spi2_default: spi2_default { + group1 { + psels = , + , + ; + }; + }; + + spi2_sleep: spi2_sleep { + group1 { + psels = , + , + ; + low-power-enable; + }; + }; + + pwm0_default: pwm0_default { + group1 { + psels = ; + }; + }; + + pwm0_sleep: pwm0_sleep { + group1 { + psels = ; + low-power-enable; + }; + }; +}; diff --git a/boards/others/promicro_nrf52840/promicro_nrf52840.yaml b/boards/others/promicro_nrf52840/promicro_nrf52840.yaml new file mode 100644 index 00000000000..35afde899eb --- /dev/null +++ b/boards/others/promicro_nrf52840/promicro_nrf52840.yaml @@ -0,0 +1,20 @@ +identifier: promicro_nrf52840/nrf52840 +name: Pro Micro nRF52840 +type: mcu +arch: arm +ram: 256 +flash: 1024 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - adc + - usb_device + - ble + - pwm + - spi + - watchdog + - counter + - netif:openthread + - gpio diff --git a/boards/others/promicro_nrf52840/promicro_nrf52840_nrf52840.dts b/boards/others/promicro_nrf52840/promicro_nrf52840_nrf52840.dts new file mode 100644 index 00000000000..3f68b9ababf --- /dev/null +++ b/boards/others/promicro_nrf52840/promicro_nrf52840_nrf52840.dts @@ -0,0 +1,9 @@ +/* + * Copyright (c) 2024 MASSDRIVER EI (massdriver.space) + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include "promicro_nrf52840_nrf52840_common.dts" +#include diff --git a/boards/others/promicro_nrf52840/promicro_nrf52840_nrf52840_common.dts b/boards/others/promicro_nrf52840/promicro_nrf52840_nrf52840_common.dts new file mode 100644 index 00000000000..c8a8b77e62c --- /dev/null +++ b/boards/others/promicro_nrf52840/promicro_nrf52840_nrf52840_common.dts @@ -0,0 +1,120 @@ +/* + * Copyright (c) 2024 MASSDRIVER EI (massdriver.space) + * Copyright (c) 2018-2023 Nordic Semiconductor ASA + * Copyright (c) 2017 Linaro Limited + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "promicro_nrf52840-pinctrl.dtsi" +#include + +/ { + model = "Pro Micro nRF52840"; + compatible = "others,promicro-nrf52840"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,ieee802154 = &ieee802154; + }; + + leds { + compatible = "gpio-leds"; + led0: led_0 { + gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; + label = "Red LED"; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + red_pwm_led: led_pwm_0 { + pwms = <&pwm0 0 PWM_MSEC(20) PWM_POLARITY_INVERTED>; + label = "Red PWM LED"; + }; + }; + + aliases { + led0 = &led0; + pwm-led0 = &red_pwm_led; + red-pwm-led = &red_pwm_led; + bootloader-led0 = &led0; + mcuboot-led0 = &led0; + spi = &spi2; + watchdog0 = &wdt0; + }; +}; + +&adc { + status = "okay"; +}; + +&gpiote { + status = "okay"; +}; + +&uicr { + nfct-pins-as-gpios; + gpio-as-nreset; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&uart0 { + compatible = "nordic,nrf-uarte"; + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-1 = <&uart0_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&i2c0 { + compatible = "nordic,nrf-twi"; + status = "okay"; + pinctrl-0 = <&i2c0_default>; + pinctrl-1 = <&i2c0_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&i2c1 { + compatible = "nordic,nrf-twi"; + status = "okay"; + pinctrl-0 = <&i2c1_default>; + pinctrl-1 = <&i2c1_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&pwm0 { + status = "okay"; + pinctrl-0 = <&pwm0_default>; + pinctrl-1 = <&pwm0_sleep>; + pinctrl-names = "default", "sleep"; +}; + + +&spi2 { + compatible = "nordic,nrf-spi"; + status = "okay"; + pinctrl-0 = <&spi2_default>; + pinctrl-1 = <&spi2_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&ieee802154 { + status = "okay"; +}; + +zephyr_udc0: &usbd { + status = "okay"; +}; +#include <../boards/common/usb/cdc_acm_serial.dtsi> diff --git a/boards/others/promicro_nrf52840/promicro_nrf52840_nrf52840_defconfig b/boards/others/promicro_nrf52840/promicro_nrf52840_nrf52840_defconfig new file mode 100644 index 00000000000..d0b5322cfeb --- /dev/null +++ b/boards/others/promicro_nrf52840/promicro_nrf52840_nrf52840_defconfig @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable GPIO +CONFIG_GPIO=y + +# Board Kconfig.defconfig enables USB CDC ACM and should disable USB remote +# wakeup by default. It needs to be disabled here, because the USB nrfx +# driver always overwrites option from Kconfig mentioned above with the +# imply from CONFIG_USB_NRFX. +CONFIG_USB_DEVICE_REMOTE_WAKEUP=n diff --git a/boards/others/promicro_nrf52840/promicro_nrf52840_nrf52840_uf2.dts b/boards/others/promicro_nrf52840/promicro_nrf52840_nrf52840_uf2.dts new file mode 100644 index 00000000000..d0c2ff473a6 --- /dev/null +++ b/boards/others/promicro_nrf52840/promicro_nrf52840_nrf52840_uf2.dts @@ -0,0 +1,9 @@ +/* + * Copyright (c) 2024 MASSDRIVER EI (massdriver.space) + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include "promicro_nrf52840_nrf52840_common.dts" +#include diff --git a/boards/others/promicro_nrf52840/promicro_nrf52840_nrf52840_uf2.yaml b/boards/others/promicro_nrf52840/promicro_nrf52840_nrf52840_uf2.yaml new file mode 100644 index 00000000000..6d1862dbad6 --- /dev/null +++ b/boards/others/promicro_nrf52840/promicro_nrf52840_nrf52840_uf2.yaml @@ -0,0 +1,20 @@ +identifier: promicro_nrf52840/nrf52840/uf2 +name: Pro Micro nRF52840 +type: mcu +arch: arm +ram: 256 +flash: 1024 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - adc + - usb_device + - ble + - pwm + - spi + - watchdog + - counter + - netif:openthread + - gpio diff --git a/boards/others/promicro_nrf52840/promicro_nrf52840_nrf52840_uf2_defconfig b/boards/others/promicro_nrf52840/promicro_nrf52840_nrf52840_uf2_defconfig new file mode 100644 index 00000000000..51b5aae9f83 --- /dev/null +++ b/boards/others/promicro_nrf52840/promicro_nrf52840_nrf52840_uf2_defconfig @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable GPIO +CONFIG_GPIO=y + +# Board Kconfig.defconfig enables USB CDC ACM and should disable USB remote +# wakeup by default. It needs to be disabled here, because the USB nrfx +# driver always overwrites option from Kconfig mentioned above with the +# imply from CONFIG_USB_NRFX. +CONFIG_USB_DEVICE_REMOTE_WAKEUP=n + +# Build UF2 by default, supported by the Adafruit nRF52 Bootloader +CONFIG_BUILD_OUTPUT_UF2=y + +# UF2 Bootloader can use DT offset +CONFIG_BOARD_HAS_NRF5_BOOTLOADER=n +CONFIG_USE_DT_CODE_PARTITION=y diff --git a/boards/others/serpente/doc/index.rst b/boards/others/serpente/doc/index.rst index e7140707d74..0894427ff3e 100644 --- a/boards/others/serpente/doc/index.rst +++ b/boards/others/serpente/doc/index.rst @@ -1,7 +1,4 @@ -.. _serpente: - -Arturo182 Serpente -################## +.. zephyr:board:: serpente Overview ******** @@ -11,10 +8,6 @@ board equipped with 4MiB flash storage, a PWM enabled RGB led and 6 I/O pins. The board comes with 3 different USB connector options: USB Type-C plug, USB Type-C socket and USB Type-A plug. -.. image:: img/serpente.jpg - :align: center - :alt: Serpente Boards - Hardware ******** diff --git a/boards/others/serpente/serpente.yaml b/boards/others/serpente/serpente.yaml index df7cff28db1..7d3c1e68e58 100644 --- a/boards/others/serpente/serpente.yaml +++ b/boards/others/serpente/serpente.yaml @@ -17,6 +17,5 @@ supported: - pwm - spi - uart - - usb - usb_device - watchdog diff --git a/boards/others/stm32_min_dev/board.yml b/boards/others/stm32_min_dev/board.yml index 3ac7dfb8958..5b28a16fe38 100644 --- a/boards/others/stm32_min_dev/board.yml +++ b/boards/others/stm32_min_dev/board.yml @@ -4,5 +4,9 @@ board: vendor: others revision: format: custom + default: "blue" + revisions: + - name: "blue" + - name: "black" socs: - name: stm32f103xb diff --git a/boards/others/stm32_min_dev/doc/index.rst b/boards/others/stm32_min_dev/doc/index.rst index e27ea5c59f5..29d5a75b27e 100644 --- a/boards/others/stm32_min_dev/doc/index.rst +++ b/boards/others/stm32_min_dev/doc/index.rst @@ -1,7 +1,4 @@ -.. _stm32_min_dev: - -STM32 Minimum Development Board -############################### +.. zephyr:board:: stm32_min_dev Overview ******** @@ -16,12 +13,6 @@ are two variants of the board: Zephyr applications can use the stm32_min_dev@blue or stm32_min_dev@black board configuration to use these boards. -.. figure:: img/stm32_min_dev.jpg - :align: center - :alt: STM32 Minimum Development Board - - STM32 Minimum Development Board - As the name suggests, these boards have the bare minimum components required to power on the CPU. For practical use, you'll need to add additional components and circuits using a breadboard, for example. diff --git a/boards/others/stm32_min_dev/stm32_min_dev_black.yaml b/boards/others/stm32_min_dev/stm32_min_dev_black.yaml deleted file mode 100644 index 543b58db837..00000000000 --- a/boards/others/stm32_min_dev/stm32_min_dev_black.yaml +++ /dev/null @@ -1,15 +0,0 @@ -identifier: stm32_min_dev@black -name: STM32 Minimum Development Board (black) -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb - - xtools -ram: 20 -supported: - - i2c - - pwm - - spi - - adc - - gpio diff --git a/boards/others/stm32_min_dev/stm32_min_dev_blue.yaml b/boards/others/stm32_min_dev/stm32_min_dev_blue.yaml deleted file mode 100644 index 3a7f4ad7308..00000000000 --- a/boards/others/stm32_min_dev/stm32_min_dev_blue.yaml +++ /dev/null @@ -1,15 +0,0 @@ -identifier: stm32_min_dev@blue -name: STM32 Minimum Development Board (blue) -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb - - xtools -ram: 20 -supported: - - i2c - - pwm - - spi - - adc - - gpio diff --git a/boards/others/stm32_min_dev/twister.yaml b/boards/others/stm32_min_dev/twister.yaml new file mode 100644 index 00000000000..bcb30a9fdd0 --- /dev/null +++ b/boards/others/stm32_min_dev/twister.yaml @@ -0,0 +1,13 @@ +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 20 +supported: + - i2c + - pwm + - spi + - adc + - gpio diff --git a/boards/others/stm32f030_demo/doc/index.rst b/boards/others/stm32f030_demo/doc/index.rst index 8080f2b33d9..84d619b38b0 100644 --- a/boards/others/stm32f030_demo/doc/index.rst +++ b/boards/others/stm32f030_demo/doc/index.rst @@ -1,7 +1,4 @@ -.. _stm32f030_demo: - -STM32F030 DEMO BOARD -#################### +.. zephyr:board:: stm32f030_demo This board has the bare minimum components required to power on the STM32F030F4P6 MCU. Most of the GPIOs on the STM32 SoC have @@ -11,10 +8,6 @@ that match the SoC's pin names. For practical use, you'll need to add additional components and circuits using a breadboard, for example. -.. image:: img/stm32f030_demo.jpg - :align: center - :alt: STM32F030 DEMO BOARD - More information about the board can be found at the `stm32-base.org website`_. More information about STM32F030F4P6 can be found here: diff --git a/boards/others/stm32f103_mini/doc/index.rst b/boards/others/stm32f103_mini/doc/index.rst index c6938020f99..0377a9b5952 100644 --- a/boards/others/stm32f103_mini/doc/index.rst +++ b/boards/others/stm32f103_mini/doc/index.rst @@ -1,7 +1,4 @@ -.. _stm32f103_mini_board: - -STM32F103 Mini -################ +.. zephyr:board:: stm32f103_mini Overview ******** @@ -79,7 +76,7 @@ The Zephyr stm32f103_mini board configuration supports the following hardware fe Other hardware features are not yet supported in this Zephyr port. The default configuration can be found in -:zephyr_file:`boards/st/stm32f103_mini/stm32f103_mini_defconfig` +:zephyr_file:`boards/others/stm32f103_mini/stm32f103_mini_defconfig` Connections and IOs =================== diff --git a/boards/others/stm32f401_mini/doc/index.rst b/boards/others/stm32f401_mini/doc/index.rst index b24538f3137..5cfa267f712 100644 --- a/boards/others/stm32f401_mini/doc/index.rst +++ b/boards/others/stm32f401_mini/doc/index.rst @@ -1,7 +1,4 @@ -.. _stm32f401_mini: - -STM32 Mini F401 -############### +.. zephyr:board:: stm32f401_mini Overview ******** @@ -10,10 +7,6 @@ The STM32 Mini F401 is an extremely low cost and bare-bones development board featuring the STM32F401CC, see `STM32F401CC website`_. More info about the board with schematics available `here `_ -.. image:: img/STM32_Mini_F401-1.jpg - :align: center - :alt: STM32 Mini F401 - Hardware ******** diff --git a/boards/others/stm32f401_mini/stm32f401_mini.dts b/boards/others/stm32f401_mini/stm32f401_mini.dts index 8553bd8edf4..64c1da9af27 100644 --- a/boards/others/stm32f401_mini/stm32f401_mini.dts +++ b/boards/others/stm32f401_mini/stm32f401_mini.dts @@ -117,7 +117,7 @@ zephyr_udc0: &usbotg_fs { &adc1 { pinctrl-0 = <&adc1_in1_pa1>; pinctrl-names = "default"; - st,adc-clock-source = ; + st,adc-clock-source = "SYNC"; st,adc-prescaler = <2>; status = "okay"; }; diff --git a/boards/others/stm32f401_mini/stm32f401_mini.yaml b/boards/others/stm32f401_mini/stm32f401_mini.yaml index 9ef69362175..ba3cdefd138 100644 --- a/boards/others/stm32f401_mini/stm32f401_mini.yaml +++ b/boards/others/stm32f401_mini/stm32f401_mini.yaml @@ -9,7 +9,6 @@ toolchain: supported: - counter - spi - - usb - i2c - uart - pwm diff --git a/boards/panasonic/pan1770_evb/Kconfig.defconfig b/boards/panasonic/pan1770_evb/Kconfig.defconfig index 8a91e35369a..fc9670a22db 100644 --- a/boards/panasonic/pan1770_evb/Kconfig.defconfig +++ b/boards/panasonic/pan1770_evb/Kconfig.defconfig @@ -5,7 +5,4 @@ if BOARD_PAN1770_EVB -config BT_CTLR - default BT - endif # BOARD_PAN1770_EVB diff --git a/boards/panasonic/pan1770_evb/doc/index.rst b/boards/panasonic/pan1770_evb/doc/index.rst index dd0efd1c8c4..c518d4baa82 100644 --- a/boards/panasonic/pan1770_evb/doc/index.rst +++ b/boards/panasonic/pan1770_evb/doc/index.rst @@ -1,7 +1,4 @@ -.. _pan1770_evb: - -PAN1770 Evaluation Board -######################## +.. zephyr:board:: pan1770_evb Overview ******** @@ -13,19 +10,15 @@ It is basically a clone of the official nRF52840 development kit (PCA10056) from Nordic Semiconductor. Please refer to :ref:`nrf52840dk_nrf52840` for further information. -.. figure:: pan1770_evaluation_board.jpg - :align: center - :alt: PAN1770 Evaluation Board - You can find more information about the PAN1770 module and the PAN1770 evaluation board on the `product website`_. The PAN1770 evaluation board is closely linked to these other evaluation boards: -* :ref:`pan1780_evb` -* :ref:`pan1781_evb` -* :ref:`pan1782_evb` +* :zephyr:board:`pan1780_evb` +* :zephyr:board:`pan1781_evb` +* :zephyr:board:`pan1782_evb` Usage ***** diff --git a/boards/panasonic/pan1780_evb/Kconfig.defconfig b/boards/panasonic/pan1780_evb/Kconfig.defconfig index 81bb7a60819..7c4acfad4b6 100644 --- a/boards/panasonic/pan1780_evb/Kconfig.defconfig +++ b/boards/panasonic/pan1780_evb/Kconfig.defconfig @@ -5,7 +5,4 @@ if BOARD_PAN1780_EVB -config BT_CTLR - default BT - endif # BOARD_PAN1780_EVB diff --git a/boards/panasonic/pan1780_evb/doc/index.rst b/boards/panasonic/pan1780_evb/doc/index.rst index 714b7b870f4..aac1ce9bd83 100644 --- a/boards/panasonic/pan1780_evb/doc/index.rst +++ b/boards/panasonic/pan1780_evb/doc/index.rst @@ -1,7 +1,4 @@ -.. _pan1780_evb: - -PAN1780 Evaluation Board -######################## +.. zephyr:board:: pan1780_evb Overview ******** @@ -13,18 +10,14 @@ It is basically a clone of the official nRF52840 development kit (PCA10056) from Nordic Semiconductor. Please refer to :ref:`nrf52840dk_nrf52840` for further information. -.. figure:: pan1780_evaluation_board.jpg - :align: center - :alt: PAN1780 Evaluation Board - You can find more information about the PAN1780 module and the PAN1780 evaluation board on the `product website`_. The PAN1780 evaluation board is closely linked to these other evaluation boards: -* :ref:`pan1781_evb` -* :ref:`pan1782_evb` +* :zephyr:board:`pan1781_evb` +* :zephyr:board:`pan1782_evb` Usage ***** diff --git a/boards/panasonic/pan1781_evb/Kconfig.defconfig b/boards/panasonic/pan1781_evb/Kconfig.defconfig index 518676e3643..aacad9968c2 100644 --- a/boards/panasonic/pan1781_evb/Kconfig.defconfig +++ b/boards/panasonic/pan1781_evb/Kconfig.defconfig @@ -5,7 +5,4 @@ if BOARD_PAN1781_EVB -config BT_CTLR - default BT - endif # BOARD_PAN1781_EVB diff --git a/boards/panasonic/pan1781_evb/doc/index.rst b/boards/panasonic/pan1781_evb/doc/index.rst index 312aa581e01..e8dc75b84ec 100644 --- a/boards/panasonic/pan1781_evb/doc/index.rst +++ b/boards/panasonic/pan1781_evb/doc/index.rst @@ -1,7 +1,4 @@ -.. _pan1781_evb: - -PAN1781 Evaluation Board -######################## +.. zephyr:board:: pan1781_evb Overview ******** @@ -9,10 +6,6 @@ Overview The PAN1781 Evaluation Board is a development tool for the PAN1781 module which is based on the nRF52820 chipset from Nordic Semiconductor. -.. figure:: pan1781_evaluation_board.jpg - :align: center - :alt: PAN1781 Evaluation Board - You can find more information about the PAN1781 module and the PAN1781 evaluation board on the `product website`_. @@ -22,8 +15,8 @@ development kits for the nRF52820 from Nordic Semiconductor. The PAN1781 evaluation board is closely linked to these other evaluation boards: -* :ref:`pan1780_evb` -* :ref:`pan1782_evb` +* :zephyr:board:`pan1780_evb` +* :zephyr:board:`pan1782_evb` Usage ***** diff --git a/boards/panasonic/pan1782_evb/Kconfig.defconfig b/boards/panasonic/pan1782_evb/Kconfig.defconfig index c9136006be4..f3ad6583017 100644 --- a/boards/panasonic/pan1782_evb/Kconfig.defconfig +++ b/boards/panasonic/pan1782_evb/Kconfig.defconfig @@ -5,7 +5,4 @@ if BOARD_PAN1782_EVB -config BT_CTLR - default BT - endif # BOARD_PAN1782_EVB diff --git a/boards/panasonic/pan1782_evb/doc/index.rst b/boards/panasonic/pan1782_evb/doc/index.rst index c69b23c7bdc..eb158172a88 100644 --- a/boards/panasonic/pan1782_evb/doc/index.rst +++ b/boards/panasonic/pan1782_evb/doc/index.rst @@ -1,7 +1,4 @@ -.. _pan1782_evb: - -PAN1782 Evaluation Board -######################## +.. zephyr:board:: pan1782_evb Overview ******** @@ -9,10 +6,6 @@ Overview The PAN1782 Evaluation Board is a development tool for the PAN1782 module which is based on the nRF52833 chipset from Nordic Semiconductor. -.. figure:: pan1782_evaluation_board.jpg - :align: center - :alt: PAN1782 Evaluation Board - You can find more information about the PAN1782 module and the PAN1782 evaluation board on the `product website`_. @@ -22,8 +15,8 @@ development kits for the nRF52833 from Nordic Semiconductor. The PAN1782 evaluation board is closely linked to these other evaluation boards: -* :ref:`pan1780_evb` -* :ref:`pan1781_evb` +* :zephyr:board:`pan1780_evb` +* :zephyr:board:`pan1781_evb` Usage ***** diff --git a/boards/panasonic/pan1783/Kconfig.defconfig b/boards/panasonic/pan1783/Kconfig.defconfig index 9f69518027a..f240f37ef85 100644 --- a/boards/panasonic/pan1783/Kconfig.defconfig +++ b/boards/panasonic/pan1783/Kconfig.defconfig @@ -16,7 +16,4 @@ endif # SOC_NRF5340_CPUAPP_QKAA if SOC_NRF5340_CPUNET_QKAA -config BT_CTLR - default y if BT - endif # SOC_NRF5340_CPUNET_QKAA diff --git a/boards/panasonic/pan1783/doc/index.rst b/boards/panasonic/pan1783/doc/index.rst index 95b8b94444b..72759be8d62 100644 --- a/boards/panasonic/pan1783/doc/index.rst +++ b/boards/panasonic/pan1783/doc/index.rst @@ -1,7 +1,4 @@ -.. _pan1783_evb: - -PAN1783, PAN1783A and PAN1783A-PA Evaluation Boards -################################################### +.. zephyr:board:: pan1783_evb Overview ******** @@ -17,11 +14,7 @@ Evaluation Boards can be found on the `product website`_. PAN1783 EVB *********** -.. figure:: img/pan1783_evb.webp - :align: center - :alt: PAN1783 EVB - - PAN1783 EVB (Credit: Panasonic) +This variant of the board is depicted in the "Board Overview" sidebar. PAN1783A EVB ************ diff --git a/boards/panasonic/pan1783/pan1783_nrf5340_cpuapp_common.dtsi b/boards/panasonic/pan1783/pan1783_nrf5340_cpuapp_common.dtsi index 421ca523925..ad66cff5c5d 100644 --- a/boards/panasonic/pan1783/pan1783_nrf5340_cpuapp_common.dtsi +++ b/boards/panasonic/pan1783/pan1783_nrf5340_cpuapp_common.dtsi @@ -171,6 +171,11 @@ status = "okay"; }; +&lfxo { + load-capacitors = "internal"; + load-capacitance-picofarad = <7>; +}; + &adc { status = "okay"; }; diff --git a/boards/particle/argon/Kconfig.defconfig b/boards/particle/argon/Kconfig.defconfig index 72954154c71..7d17a09d99b 100644 --- a/boards/particle/argon/Kconfig.defconfig +++ b/boards/particle/argon/Kconfig.defconfig @@ -5,7 +5,4 @@ if BOARD_PARTICLE_ARGON -config BT_CTLR - default BT - endif # BOARD_PARTICLE_ARGON diff --git a/boards/particle/argon/doc/index.rst b/boards/particle/argon/doc/index.rst index 0cfedf946db..d0391a102a4 100644 --- a/boards/particle/argon/doc/index.rst +++ b/boards/particle/argon/doc/index.rst @@ -1,7 +1,4 @@ -.. _particle_argon: - -Particle Argon -############## +.. zephyr:board:: particle_argon Overview ******** @@ -29,12 +26,6 @@ Hardware On the front of the board are RGB-LED, LED and LIPO circuitry. The RGB-LED is controlled by the nRF52840 via GPIO pins. -.. figure:: img/particle_argon.jpg - :align: center - :alt: Particle Argon - - Particle Argon (Credit: Particle Industries) - Power supply ============ diff --git a/boards/particle/boron/Kconfig.defconfig b/boards/particle/boron/Kconfig.defconfig index cce1a36897f..6fefbf76846 100644 --- a/boards/particle/boron/Kconfig.defconfig +++ b/boards/particle/boron/Kconfig.defconfig @@ -5,9 +5,6 @@ if BOARD_PARTICLE_BORON -config BT_CTLR - default BT - if MODEM config MODEM_UBLOX_SARA diff --git a/boards/particle/boron/doc/index.rst b/boards/particle/boron/doc/index.rst index da87b144a0d..73ece4387d6 100644 --- a/boards/particle/boron/doc/index.rst +++ b/boards/particle/boron/doc/index.rst @@ -1,7 +1,4 @@ -.. _particle_boron: - -Particle Boron -############## +.. zephyr:board:: particle_boron Overview ******** @@ -29,12 +26,6 @@ Hardware On the front of the board are RGB-LED, LED and LIPO circuitry. The RGB-LED is controlled by the nRF52840 via GPIO pins. -.. figure:: img/particle_boron.jpg - :align: center - :alt: Particle Boron - - Particle Boron (Credit: Particle Industries) - Power supply ============ diff --git a/boards/particle/nrf51_blenano/Kconfig.defconfig b/boards/particle/nrf51_blenano/Kconfig.defconfig index fb61b031143..a5f58e09899 100644 --- a/boards/particle/nrf51_blenano/Kconfig.defconfig +++ b/boards/particle/nrf51_blenano/Kconfig.defconfig @@ -5,7 +5,4 @@ if BOARD_NRF51_BLENANO -config BT_CTLR - default BT - endif # BOARD_NRF51_BLENANO diff --git a/boards/particle/nrf51_blenano/doc/index.rst b/boards/particle/nrf51_blenano/doc/index.rst index 1d6d2ea4a2a..5cedb0aa100 100644 --- a/boards/particle/nrf51_blenano/doc/index.rst +++ b/boards/particle/nrf51_blenano/doc/index.rst @@ -1,7 +1,4 @@ -.. _nrf51_blenano: - -Redbear Labs Nano -################# +.. zephyr:board:: nrf51_blenano Overview ******** diff --git a/boards/particle/nrf52_blenano2/Kconfig.defconfig b/boards/particle/nrf52_blenano2/Kconfig.defconfig index df0bcd9b33a..5e57d952594 100644 --- a/boards/particle/nrf52_blenano2/Kconfig.defconfig +++ b/boards/particle/nrf52_blenano2/Kconfig.defconfig @@ -5,7 +5,4 @@ if BOARD_NRF52_BLENANO2 -config BT_CTLR - default BT - endif # BOARD_NRF52_BLENANO2 diff --git a/boards/particle/nrf52_blenano2/doc/index.rst b/boards/particle/nrf52_blenano2/doc/index.rst index b2d0824bfc1..5fd77e80c67 100644 --- a/boards/particle/nrf52_blenano2/doc/index.rst +++ b/boards/particle/nrf52_blenano2/doc/index.rst @@ -1,7 +1,4 @@ -.. _nrf52_blenano2: - -Redbear Labs Nano v2 -#################### +.. zephyr:board:: nrf52_blenano2 Overview ******** diff --git a/boards/particle/xenon/Kconfig.defconfig b/boards/particle/xenon/Kconfig.defconfig index 1cd3ad31f06..f58b2e11792 100644 --- a/boards/particle/xenon/Kconfig.defconfig +++ b/boards/particle/xenon/Kconfig.defconfig @@ -6,7 +6,4 @@ if BOARD_PARTICLE_XENON -config BT_CTLR - default BT - endif # BOARD_PARTICLE_XENON diff --git a/boards/particle/xenon/doc/index.rst b/boards/particle/xenon/doc/index.rst index d28b8aac1c0..795393b09f4 100644 --- a/boards/particle/xenon/doc/index.rst +++ b/boards/particle/xenon/doc/index.rst @@ -1,7 +1,4 @@ -.. _particle_xenon: - -Particle Xenon -############## +.. zephyr:board:: particle_xenon Overview ******** @@ -28,12 +25,6 @@ Hardware On the front of the board are RGB-LED, LED and LIPO circuitry. The RGB-LED is controlled by the nRF52840 via GPIO pins. -.. figure:: img/particle_xenon.jpg - :align: center - :alt: Particle Xenon - - Particle Xenon (Credit: Particle Industries) - Power supply ============ diff --git a/boards/phytec/mimx8mm_phyboard_polis/Kconfig.mimx8mm_phyboard_polis b/boards/phytec/mimx8mm_phyboard_polis/Kconfig.mimx8mm_phyboard_polis deleted file mode 100644 index 0039e251a76..00000000000 --- a/boards/phytec/mimx8mm_phyboard_polis/Kconfig.mimx8mm_phyboard_polis +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2022 PHYTEC Messtechnik GmbH -# Copyright 2024 NXP -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_MIMX8MM_PHYBOARD_POLIS - select SOC_PART_NUMBER_MIMX8MM6DVTLZ - select SOC_MIMX8MM6_M4 if BOARD_MIMX8MM_PHYBOARD_POLIS_MIMX8MM6_M4 diff --git a/boards/phytec/mimx8mm_phyboard_polis/board.yml b/boards/phytec/mimx8mm_phyboard_polis/board.yml deleted file mode 100644 index 8f834205354..00000000000 --- a/boards/phytec/mimx8mm_phyboard_polis/board.yml +++ /dev/null @@ -1,6 +0,0 @@ -board: - name: mimx8mm_phyboard_polis - full_name: PhyBOARD Polis (NXP i.MX8M Mini) - vendor: phytec - socs: - - name: mimx8mm6 diff --git a/boards/phytec/mimx8mm_phyboard_polis/doc/index.rst b/boards/phytec/mimx8mm_phyboard_polis/doc/index.rst deleted file mode 100644 index dc388d52c07..00000000000 --- a/boards/phytec/mimx8mm_phyboard_polis/doc/index.rst +++ /dev/null @@ -1,337 +0,0 @@ -.. _mimx8mm_phyboard_polis: - -PhyBOARD Polis (NXP i.MX8M Mini) -################################ - -Overview -******** - -The phyBOARD-Polis, either a development platform for the -phyCORE-i.MX 8M Mini/Nano, or a powerful, industry-compatible single-board -computer for immediate implementation of your product idea. As a development -platform, the phyBOARD-Polis serves as reference design for your -customer-specific application and enables parallel development of the software -and carrier board for the phyCORE-i.MX 8M Mini/Nano. - - -As a powerful, industrial single-board computer (SBC), the phyBOARD-Polis is -equipped with a variety of standard interfaces which are available on standard -or socket/pin header connectors, while interesting extensions of the -phyCORE-i.MX 8M Mini/Nano features such as CAN FD, WLAN and an integrated -TPM chip further extend the range of applications that can be developed with -the phyCORE-i.MX 8M Mini/Nano. - -- Board features: - - - RAM: 512MB - 4GB (LPDDR4) - - Storage: - - - 4GB - 128GB eMMC - - 8MB - 128MB SPI NOR Flash - - microSD Interfacce - - 4kB EEPROM - - Wireless: - - - WiFi: 802.11 b/g/n (ac) 2,4 GHz / 5 GHz - - BLE 4.2 - - USB: - - - 1x USB2.0 OTG - - 1x USB2.0 - - Ethernet: 1x 10/100/1000BASE-T - - Interfaces: - - 1x RS232 / RS485 - - 2x UART - - 3x I²C - - 2x SPI - - Up to 4x PWM - - 4x SAI - - 1x MIPI CSI-2 - - 1x MIPI DSI-2 - - 2x MMC/SD/SDIO - - 1x PCIe (mini PCIE) - - LEDs: - - - 1x Status LED (3 Color LED) - - 1x Debug UART LED - - Debug - - - JTAG 20-pin connector - - MicroUSB for UART debug, two COM ports for A53 and M4 - -.. image:: img/phyBOARD-Polis.jpg - :align: center - :alt: PhyBOARD Polis - :width: 500 - -More information about the board can be found at the -`PHYTEC website`_. - -Supported Features -================== - -The Zephyr ``mimx8mm_phyboard_polis/mimx8mm6/m4`` board configuration supports the following -hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | GPIO output | -| | | GPIO input | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: -:zephyr_file:`boards/phytec/mimx8mm_phyboard_polis/mimx8mm_phyboard_polis_mimx8mm6_m4_defconfig`. - -It is recommended to disable peripherals used by the M4 core on the Linux host. - -Other hardware features are not currently supported with Zephyr on the -M4-Core. - -Connections and IOs -=================== - -The following components are tested and working correctly. - -UART: ------ - -Zephyr is configured to use UART4 on the PhyBoard Polis by default to minimize -problems with the A53-Core because UART4 is only accessible from the M4-Core. - -+---------------+-----------------+-----------------------------------+ -| Board Name | SoM Name | Usage | -+===============+=================+===================================+ -| RS232/485 | UART1 | RS232 / RS485 with flow-control | -+---------------+-----------------+-----------------------------------+ -| To WiFi Module| UART2 | UART to WiFi/BLE Module | -+---------------+-----------------+-----------------------------------+ -| Debug USB(A53)| UART3 | UART Debug Console via USB | -+---------------+-----------------+-----------------------------------+ -| Debug USB(M4) | UART4 | UART Debug Console via USB | -+---------------+-----------------+-----------------------------------+ - -.. note:: - Please note, that the to UART2 connected Wifi/BLE Module isn't working with - Zephyr yet. - -.. warning:: - On Boards with the version number 1532.1 UART4 isn't connected to the Debug - USB. UART4 connects to pin 10(RX) and 12(TX) on the X8 pinheader. - - -LEDs: ------ - -Zephyr has the 3-color status LED configured. The led0 alias (the standard -Zephyr led) is configured to be the blue led. The LED can also light up in red -and green. - -GPIO: ------ - -The pinmuxing for the GPIOs is the standard pinmuxing of the mimx8mm devicetree -created by NXP. You can find it here: - -:zephyr_file:`dts/arm/nxp/nxp_imx8m_m4.dtsi`. - -The Pinout of the PhyBOARD Polis can be found here: - -`PHYTEC website`_ - -System Clock -============ - -The M4 Core is configured to run at a 400 MHz clock speed. - - -Programming and Debugging -************************* - -The i.MX8MM does not have a separate flash for the M4-Core. Because of this -the A53-Core has to load the program for the M4-Core to the right memory -address, set the PC and start the processor. -This can be done with U-Boot or Phytec's Linux BSP via remoteproc. - -Because remoteproc in Phytec's BSP only writes to the TCM memory area, -everything was tested in this memory area. - -You can read more about remoteproc in Phytec's BSP here: `Remoteproc BSP`_ - -These are the memory mapping for A53 and M4: - -+------------+-------------------------+------------------------+-----------------------+----------------------+ -| Region | Cortex-A53 | Cortex-M4 (System Bus) | Cortex-M4 (Code Bus) | Size | -+============+=========================+========================+=======================+======================+ -| OCRAM | 0x00900000-0x0093FFFF | 0x20200000-0x2023FFFF | 0x00900000-0x0093FFFF | 256KB | -+------------+-------------------------+------------------------+-----------------------+----------------------+ -| TCMU | 0x00800000-0x0081FFFF | 0x20000000-0x2001FFFF | | 128KB | -+------------+-------------------------+------------------------+-----------------------+----------------------+ -| TCML | 0x007E0000-0x007FFFFF | | 0x1FFE0000-0x1FFFFFFF | 128KB | -+------------+-------------------------+------------------------+-----------------------+----------------------+ -| OCRAM_S | 0x00180000-0x00187FFF | 0x20180000-0x20187FFF | 0x00180000-0x00187FFF | 32KB | -+------------+-------------------------+------------------------+-----------------------+----------------------+ - -For more information about memory mapping see the -`i.MX 8M Applications Processor Reference Manual`_ (section 2.1.2 and 2.1.3) - -At compilation time you have to choose which RAM will be used. This -configuration is done in -:zephyr_file:`boards/phytec/mimx8mm_phyboard_polis/mimx8mm_phyboard_polis_mimx8mm6_m4.dts` -with "zephyr,flash" (when CONFIG_XIP=y) and "zephyr,sram" properties. - -You also have to set XIP=n or edit the boards defconfig file, if you don't want -the TCM memory area to be used. You can find the defconf file here: - -:zephyr_file:`boards/phytec/mimx8mm_phyboard_polis/mimx8mm_phyboard_polis_mimx8mm6_m4_defconfig`. - -The following configurations are possible for the flash and sram chosen nodes -to change the used memory area: - -.. code-block:: none - - "zephyr,flash" - - &tcml_code - - &ocram_code - - &ocram_s_code - - "zephyr,sram" - - &tcmu_sys - - &ocram_sys - - &ocram_s_sys - - -Starting the M4-Core via U-Boot -=============================== - -Load the compiled zephyr.bin to memory address 0x4800000. -This should output something like this: - -.. code-block:: console - - u-boot=> tftp 0x48000000 192.168.3.10:zephyr.bin - Using ethernet@30be0000 device - TFTP from server 192.168.3.10; our IP address is 192.168.3.11 - Filename 'zephyr.bin'. - Load address: 0x48000000 - Loading: ## - 2 KiB/s - done - Bytes transferred = 27240 (6a68 hex) - -Because it's not possible to load directly to the TCM memory area you have to -copy the binaries. The last argument given is the size of the file in bytes, -you can copy it from the output of the last command. - -.. code-block:: console - - u-boot=> cp.b 0x48000000 0x7e0000 27240 - -And finaly starting the M4-Core at the right memory address: - -.. code-block:: console - - u-boot=> bootaux 0x7e0000 - ## Starting auxiliary core stack = 0x20003A58, pc = 0x1FFE1905... - - -Starting the M4-Core via remoteproc -=================================== - -Copy the zephyr.elf to ``/lib/firmware`` on the target. Maybe a Zephyr sample -will be included in a future BSP release. - -.. note:: - In order to use remoteproc you have to add ``imx8mm-phycore-rpmsg.dtbo`` at - the end of the line in the ``/boot/bootenv.txt``, then reboot the target. - -.. warning:: - Remoteproc only reads firmware files from the ``/lib/firmware`` directory! - If you try to load a binary from another location unexpected errors will - occur! - -To load and start a firmware use this commands: - -.. code-block:: console - - target$ echo /lib/firmware/zephyr.elf > /sys/class/remoteproc/remoteproc0/firmware - target$ echo start > /sys/class/remoteproc/remoteproc0/state - [ 90.700611] remoteproc remoteproc0: powering up imx-rproc - [ 90.706114] remoteproc remoteproc0: Direct firmware load for /lib/firmware/zephyr.elf failed w2 - [ 90.716571] remoteproc remoteproc0: Falling back to sysfs fallback for: /lib/firmware/zephyr.elf - [ 90.739280] remoteproc remoteproc0: Booting fw image /lib/firmware/zephyr.elf, size 599356 - [ 90.804448] remoteproc remoteproc0: remote processor imx-rproc is now up - - -The M4-Core is now started up and running. You can see the output from Zephyr -on UART4. - -Debugging -========= - -The PhyBOARD Polis can be debugged using a JTAG Debugger. -The easiest way to do that is to use a SEGGER JLink Debugger and Phytec's -``PEB-EVAL-01`` Shield, which can be directly connected to the JLink. -You can find the JLink Software package here: `JLink Software`_ - -.. figure:: img/PEB-EVAL-01.jpg - :alt: PEB-EVAL-01 - :width: 350 - - PEB-EVAL-01 - -To debug efficiently you should use multiple terminals: - -(But its also possible to use ``west debug``) - -After connecting everything and building with west use this command while in -the directory of the program you build earlier to start a debug server: - -.. code-block:: console - - host$ west debugserver - -West automatically connects via the JLink to the Target. And keeps open a -debug server. - -Use another terminal, start gdb, connect to target and load Zephyr on the -target: - -.. code-block:: console - - host$ gdb-multiarch build/zephyr/zephyr.elf -tui - (gdb) targ rem :2331 - Remote debugging using :2331 - 0x1ffe0008 in _vector_table () - (gdb) mon halt - (gdb) mon reset - (gdb) c - Continuing. - -The program can be debugged using standard gdb techniques. - -.. _PHYTEC website: - https://www.phytec.de/produkte/single-board-computer/phyboard-polis-imx8m-mini/ - -.. _PhyBOARD Polis pinout: - https://download.phytec.de/Products/phyBOARD-Polis-iMX8M_Mini/TechData/phyCORE-i.MX8M_MINI_Pin_Muxing_Table.A1.xlsx?_ga=2.237582016.1177557183.1660563641-1900651135.1634193918 - -.. _Remoteproc BSP: - https://wiki.phytec.com/pages/releaseview.action?pageId=472257137#L1002e.A3i.MX8MMini/NanoBSPManual-RunningExamplesfromLinuxusingRemoteproc - -.. _i.MX 8M Applications Processor Reference Manual: - https://www.nxp.com/webapp/Download?colCode=IMX8MMRM - -.. _JLink Software: - https://www.segger.com/downloads/jlink/ diff --git a/boards/phytec/mimx8mm_phyboard_polis/mimx8mm_phyboard_polis-pinctrl.dtsi b/boards/phytec/mimx8mm_phyboard_polis/mimx8mm_phyboard_polis-pinctrl.dtsi deleted file mode 100644 index 928908a6162..00000000000 --- a/boards/phytec/mimx8mm_phyboard_polis/mimx8mm_phyboard_polis-pinctrl.dtsi +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright (c) 2022 PHYTEC Messtechnik GmbH - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include - -&pinctrl { - uart4_default: uart4_default { - group0 { - pinmux = <&iomuxc_uart4_rxd_uart_rx_uart4_rx>, - <&iomuxc_uart4_txd_uart_tx_uart4_tx>; - slew-rate = "fast"; - drive-strength = "x6"; - }; - }; - - uart3_default: uart3_default { - group0 { - pinmux = <&iomuxc_uart3_rxd_uart_rx_uart3_rx>, - <&iomuxc_uart3_txd_uart_tx_uart3_tx>; - slew-rate = "fast"; - drive-strength = "x6"; - }; - }; - - uart2_default: uart2_default { - group0 { - pinmux = <&iomuxc_sai3_rxd_uart_cts_b_uart2_rts_b>, - <&iomuxc_sai3_rxd_uart_rts_b_uart2_rts_b>, - <&iomuxc_sai3_txfs_uart_tx_uart2_rx>, - <&iomuxc_sai3_txc_uart_rx_uart2_tx>; - slew-rate = "fast"; - drive-strength = "x6"; - }; - }; - - uart1_default: uart1_default { - group0 { - pinmux = <&iomuxc_sai2_rxfs_uart_rx_uart1_tx>, - <&iomuxc_sai2_rxc_uart_rx_uart1_rx>, - <&iomuxc_sai2_rxd0_uart_rts_b_uart1_rts_b>, - <&iomuxc_sai2_txfs_uart_cts_b_uart1_cts_b>; - slew-rate = "fast"; - drive-strength = "x6"; - }; - }; -}; diff --git a/boards/phytec/mimx8mm_phyboard_polis/mimx8mm_phyboard_polis_mimx8mm6_m4.dts b/boards/phytec/mimx8mm_phyboard_polis/mimx8mm_phyboard_polis_mimx8mm6_m4.dts deleted file mode 100644 index 43879d81e25..00000000000 --- a/boards/phytec/mimx8mm_phyboard_polis/mimx8mm_phyboard_polis_mimx8mm6_m4.dts +++ /dev/null @@ -1,93 +0,0 @@ -/* - * Copyright (c) 2022 PHYTEC Messtechnik GmbH - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include -#include "mimx8mm_phyboard_polis-pinctrl.dtsi" - -/ { - model = "Phyboard Polis NXP i.MX8M Mini"; - compatible = "nxp,mimx8mm_phyboard_polis"; - - aliases { - uart-4 = &uart4; - uart-3 = &uart3; - uart-2 = &uart2; - uart-1 = &uart1; - led0 = &led_blue; - }; - - chosen { - zephyr,flash = &tcml_code; - zephyr,sram = &tcmu_sys; - zephyr,console = &uart4; - zephyr,shell-uart = &uart4; - }; - - leds { - compatible = "gpio-leds"; - - led_red: led_red { - gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; - }; - - led_blue: led_blue { - gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; - }; - - led_green: led_green { - gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; - }; - }; - -}; - -/* RS232 / RS485 pinheader on the board */ -&uart1 { - status = "disabled"; - pinctrl-0 = <&uart1_default>; - pinctrl-names = "default"; - hw-flow-control; -}; - -/* - * UART to bluetooth module / X18 header - * Currently there is no driver for the used module - */ -&uart2 { - status = "disabled"; - pinctrl-0 = <&uart2_default>; - pinctrl-names = "default"; - hw-flow-control; -}; - -/* UART usually used from A53 Core (1st tty on Debug USB connector */ -&uart3 { - status = "disabled"; - pinctrl-0 = <&uart3_default>; - pinctrl-names = "default"; -}; - -/* UART of the M4 Core (2nd tty on Debug USB connector) */ -&uart4 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart4_default>; - pinctrl-names = "default"; -}; - -/* - * needs to be configured, so the leds don't generate an error, - * but does not interfer with the A53-Core - */ -&gpio1 { - status = "okay"; -}; - -&mailbox0 { - status = "okay"; -}; diff --git a/boards/phytec/mimx8mm_phyboard_polis/mimx8mm_phyboard_polis_mimx8mm6_m4.yaml b/boards/phytec/mimx8mm_phyboard_polis/mimx8mm_phyboard_polis_mimx8mm6_m4.yaml deleted file mode 100644 index 0125a4fa399..00000000000 --- a/boards/phytec/mimx8mm_phyboard_polis/mimx8mm_phyboard_polis_mimx8mm6_m4.yaml +++ /dev/null @@ -1,21 +0,0 @@ -# -# Copyright (c) 2020 PHYTEC Messtechnik GmbH -# -# SPDX-License-Identifier: Apache-2.0 -# - -identifier: mimx8mm_phyboard_polis/mimx8mm6/m4 -name: Phyboard Polis i.MX8M Mini -type: mcu -arch: arm -ram: 128 -flash: 128 -toolchain: - - zephyr - - gnuarmemb - - xtools -testing: - ignore_tags: - - net - - bluetooth -vendor: nxp diff --git a/boards/phytec/mimx8mm_phyboard_polis/mimx8mm_phyboard_polis_mimx8mm6_m4_defconfig b/boards/phytec/mimx8mm_phyboard_polis/mimx8mm_phyboard_polis_mimx8mm6_m4_defconfig deleted file mode 100644 index 9fad86a42a7..00000000000 --- a/boards/phytec/mimx8mm_phyboard_polis/mimx8mm_phyboard_polis_mimx8mm6_m4_defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# -# Copyright (c) 2022 PHYTEC Messtechnik GmbH -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_CORTEX_M_SYSTICK=y -CONFIG_CLOCK_CONTROL=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_CONSOLE=y -CONFIG_PINCTRL=y -CONFIG_GPIO=y diff --git a/boards/phytec/mimx8mp_phyboard_pollux/Kconfig.mimx8mp_phyboard_pollux b/boards/phytec/mimx8mp_phyboard_pollux/Kconfig.mimx8mp_phyboard_pollux deleted file mode 100644 index d0f63578fe2..00000000000 --- a/boards/phytec/mimx8mp_phyboard_pollux/Kconfig.mimx8mp_phyboard_pollux +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2022 PHYTEC Messtechnik GmbH -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_MIMX8MP_PHYBOARD_POLLUX - select SOC_MIMX8ML8_M7 if BOARD_MIMX8MP_PHYBOARD_POLLUX_MIMX8ML8_M7 - select SOC_PART_NUMBER_MIMX8ML8DVNLZ diff --git a/boards/phytec/mimx8mp_phyboard_pollux/board.yml b/boards/phytec/mimx8mp_phyboard_pollux/board.yml deleted file mode 100644 index a8e5cbf9a0a..00000000000 --- a/boards/phytec/mimx8mp_phyboard_pollux/board.yml +++ /dev/null @@ -1,6 +0,0 @@ -board: - name: mimx8mp_phyboard_pollux - full_name: PhyBOARD Pollux (NXP i.MX8M Plus) - vendor: phytec - socs: - - name: mimx8ml8 diff --git a/boards/phytec/mimx8mp_phyboard_pollux/doc/index.rst b/boards/phytec/mimx8mp_phyboard_pollux/doc/index.rst deleted file mode 100644 index 6314b716513..00000000000 --- a/boards/phytec/mimx8mp_phyboard_pollux/doc/index.rst +++ /dev/null @@ -1,262 +0,0 @@ -.. _mimx8mp_phyboard_pollux: - -PhyBOARD Pollux (NXP i.MX8M Plus) -################################# - -Overview -******** - -The PhyBOARD Pollux is based upon the PhyCore-i.MX8M Plus SOM which is based on -the NXP i.MX8M Plus SoC. The SoC includes four Coretex-A53 cores and one -Coretex-M7 core for real time applications like Zephyr. The PhyBOARD Pollux -can be used for various applications like SmartHomes, Industry 4.0, IoT etc. -It features a lots of interfaces and computing capacity. It can be used as -a reference, to develop or in the final product too. - - -Board features: - -- Memory: - - - RAM: 256MB - 8GB LPDDR4 - - EEPROM: 4kB - 32kB - - eMMC: 4GB - 64GB (eMMC 5.1) - - SPI NOR Flash: 4MB - 256MB -- Interfaces: - - - Ethernet: 2x 10/100/1000BASE-T (1x TSN Support) - - USB: 2x 3.0 Host - - Serial: 1x RS232 / RS485 Full Duplex / Half Duplex - - CAN: 2x CAN FD - - Digital I/O: via Expansion Connector - - PCIe: 1x miniPCIe - - MMX/SD/SDIO: microSD slot - - Display: LVDS(1x4 or 1x8), MIPI DSI(1x4), HDMI - - Audio: SAI - - Camera: 2x MIPI CSI-2 (PhyCAM-M) - - Expansion Bus: I2C, SPI, SDIO, UART, USB - - JTAG: via PEB-EVAL-01 -- LEDs: - - - 1x Multicolor Status LED via I2C - - -.. image:: img/Phyboard_Pollux.jpg - :width: 720px - :align: center - :height: 405px - :alt: PhyBOARD Pollux - -More information about the board can be found at the `PHYTEC website`_. - -Supported Features -================== - -The Zephyr mimx8mp_phyboard_polis board configuration supports the following hardware -features: - -+-----------+------------+------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+------------------------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+------------------------------------+ -| GPIO | on-chip | GPIO output | -| | | GPIO input | -+-----------+------------+------------------------------------+ - -The default configuration can be found in the defconfig file: -:zephyr_file:`boards/phytec/mimx8mp_phyboard_pollux/mimx8mp_phyboard_pollux_mimx8ml8_m7_defconfig`. - -It's recommended to disable peripherals used by the M7-Core on the host running -on the Linux host. Other hardware features are not currently supported with -Zephyr on the M7-Core. - -Connections and IOs -=================== - -The following Compontens are tested and working correctly. - -UART ----- - -+-----------------+----------+----------------------------+ -| Board Name | SoM Name | Usage | -+=================+==========+============================+ -| Debug USB (A53) | UART1 | UART Debug Console via USB | -+-----------------+----------+----------------------------+ -| Wo WiFi Module | UART3 | UART to WiFi/BLE Module | -+-----------------+----------+----------------------------+ -| Debug USB (M7) | UART4 | UART Debug Console via USB | -+-----------------+----------+----------------------------+ - -.. note:: - The WiFi/BLE Module connected to UART3 isn't working with Zephyr yet. UART3 - can also be used through pin 31(RX) and 33(TX) of connector X6. - -GPIO ----- - -The pinmuxing for the GPIOs is the standard pinmuxing of the mimx8mp devicetree -created by NXP and can be found at -:zephyr_file:`dts/arm/nxp/nxp_imx8ml_m7.dtsi`. The Pinout of the PhyBOARD Polis -can be found at the `PHYTEC website`_. - -Programming and Debugging -************************* - -The i.MX8MP does not have a separate flash for the M7-Core. Because of this -the A53-Core has to load the program for the M7-Core to the right memory -address, set the PC and start the processor. - -The M7 can use up to 3 different RAMs (currently, only two configurations are -supported: ITCM and DDR). These are the memory mapping for A53 and M7: - -+---------+-----------------------+------------------------+-----------------------+-------+ -| Region | Cortex-A53 | Cortex-M7 (System Bus) | Cortex-M7 (Code Bus) | Size | -+=========+=======================+========================+=======================+=======+ -| OCRAM | 0x00900000-0x0098FFFF | 0x20200000-0x2028FFFF | 0x00900000-0x0098FFFF | 576KB | -+---------+-----------------------+------------------------+-----------------------+-------+ -| DTCM | 0x00800000-0x0081FFFF | 0x20000000-0x2001FFFF | | 128KB | -+---------+-----------------------+------------------------+-----------------------+-------+ -| ITCM | 0x007E0000-0x007FFFFF | | 0x00000000-0x0001FFFF | 128KB | -+---------+-----------------------+------------------------+-----------------------+-------+ -| OCRAM_S | 0x00180000-0x00188FFF | 0x20180000-0x20188FFF | 0x00180000-0x00188FFF | 36KB | -+---------+-----------------------+------------------------+-----------------------+-------+ -| DDR | 0x80000000-0x803FFFFF | 0x80200000-0x803FFFFF | 0x80000000-0x801FFFFF | 2MB | -+---------+-----------------------+------------------------+-----------------------+-------+ - -For more information about memory mapping see the -`i.MX 8M Plus Applications Processor Reference Manual`_ (section 2.1 to 2.3) - -At compilation time you have to choose which memory region will be used. This -configuration is done in the devicetree and the defconfig / the config of your -program. - -**By default Zephyr will use the TCM memory region.** You can configure it -to use the DDR region. In the devicetree overwrite you can select both options. - -.. code-block:: DTS - - chosen { - /* TCM */ - zephyr,flash = &itcm; - zephyr,sram = &dtcm; - }; - - -.. code-block:: DTS - - chosen { - /* DDR */ - zephyr,flash = &ddr_code; - zephyr,sram = &ddr_sys; - }; - - -And in the prj.conf the configuration to the **DDR** memory region: - -.. code-block:: cfg - - CONFIG_CODE_DDR=y - CONFIG_CODE_ITCM=n - -Connecting to the Serial Console -================================ - -A serial console for both the application CPU and the Cortex M7 coprocessor are -available via the onboard dual USB-to-UART converter. If you use Linux, create a -udev rule (as ``root``) to fix a permission issue when not using root for -flashing. - -.. code-block:: console - - # echo 'ATTR{idProduct}=="0a70", ATTR{idVendor}=="10c4", MODE="0666", GROUP="plugdev"' > /etc/udev/rules.d/50-usb-uart.rules - -Reload the rules and replug the device. - -.. code-block:: console - - $ sudo udevadm control --reload-rules - -Finally, unplug and plug the board again for the rules to take effect. - -Connect to the console via your favorite terminal program. For example: - -.. code-block:: console - - $ minicom -D /dev/ttyUSB1 -b 115200 - -Flashing and Debugging via JTAG -=============================== - -The PhyBOARD-Pollux can be debugged using a JTAG or SWD debug adapter. A Segger -JLink can be connected to the compatible JTAG connector on Phytec's -``PEB-EVAL-01`` shield. - -.. figure:: img/PEB-EVAL-01.jpg - :alt: PEB-EVAL-01 - :width: 350 - - PEB-EVAL-01 - -Before flashing or debugging via a JTAG debug adapter, -the M7 core has to be switched on: - -.. code-block:: console - - u-boot=> bootaux 0x7e0000 - -Here is an example for the :zephyr:code-sample:`hello_world` application: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: mimx8mp_phyboard_pollux/mimx8ml8/m7 - :goals: flash - -The console should now show the output of the application: - -.. code-block:: console - - *** Booting Zephyr OS build v3.7.0 *** - Hello World! mimx8mp_phyboard_pollux/mimx8ml8/m7 - -Starting a debug session is similar to flashing: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: mimx8mp_phyboard_pollux/mimx8ml8/m7 - :goals: debug - -Starting the M7-Core from U-Boot and Linux -========================================== - -Loading binaries and starting the M7-Core is supported from Linux via remoteproc -or from U-boot by directly copying the firmware binary. Please check the -`phyCORE-i.MX 8M Plus BSP Manual`_ for more information. - -References -========== - -- `i.MX 8M Plus Applications Processor Reference Manual`_ -- `phyCORE-i.MX 8M Plus BSP Manual`_ - -.. _PHYTEC website: - https://www.phytec.de/produkte/single-board-computer/phyboard-pollux/ - -.. _i.MX 8M Plus Applications Processor Reference Manual: - https://www.nxp.com/webapp/Download?colCode=IMX8MPRM - -.. _JLink Software: - https://www.segger.com/downloads/jlink/ - -.. _phyCORE-i.MX 8M Plus BSP Manual: - https://phytec.github.io/doc-bsp-yocto/bsp/imx8/imx8mp/imx8mp.html diff --git a/boards/phytec/mimx8mp_phyboard_pollux/mimx8mp_phyboard_pollux_mimx8ml8_m7.dts b/boards/phytec/mimx8mp_phyboard_pollux/mimx8mp_phyboard_pollux_mimx8ml8_m7.dts deleted file mode 100644 index b44577a4ee5..00000000000 --- a/boards/phytec/mimx8mp_phyboard_pollux/mimx8mp_phyboard_pollux_mimx8ml8_m7.dts +++ /dev/null @@ -1,68 +0,0 @@ -/* - * Copyright (c) 2022 PHYTEC Messtechnik GmbH - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include -#include "mimx8mp_phyboard_pollux-pinctrl.dtsi" - -/ { - model = "PhyBOARD Pollux (i.MX8MP)"; - compatible = "nxp,mimx8mp_phyboard_pollux"; - - chosen { - /* TCM */ - zephyr,flash = &itcm; - zephyr,sram = &dtcm; - - zephyr,console = &uart4; - zephyr,shell-uart = &uart4; - }; - - soc { - /* - * BSP-Linux standard output. Can cause problems if used with standard bsp - */ - uart1: uart@30860000 { - compatible = "nxp,imx-iuart"; - reg = <0x30860000 0x10000>; - interrupts = <26 3>; - clocks = <&ccm IMX_CCM_UART1_CLK 0x7c 24>; - pinctrl-0 = <&uart1_default>; - pinctrl-names = "default"; - status = "disabled"; - }; - - /* - * to Bluetooth module (currently not supported by zephyr) - * Expansion header Pin 31(RX) 33(TX) - */ - uart3: uart@30880000 { - compatible = "nxp,imx-iuart"; - reg = <0x30880000 0x10000>; - interrupts = <28 3>; - clocks = <&ccm IMX_CCM_UART3_CLK 0x68 12>; - pinctrl-0 = <&uart3_default>; - pinctrl-names = "default"; - hw-flow-control; - status = "disabled"; - }; - }; -}; - -/* - * Standard uart for the M7-Core - */ -&uart4 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart4_default>; - pinctrl-names = "default"; -}; - -&mailbox0 { - status = "okay"; -}; diff --git a/boards/phytec/mimx8mp_phyboard_pollux/mimx8mp_phyboard_pollux_mimx8ml8_m7.yaml b/boards/phytec/mimx8mp_phyboard_pollux/mimx8mp_phyboard_pollux_mimx8ml8_m7.yaml deleted file mode 100644 index aa2cc09a553..00000000000 --- a/boards/phytec/mimx8mp_phyboard_pollux/mimx8mp_phyboard_pollux_mimx8ml8_m7.yaml +++ /dev/null @@ -1,24 +0,0 @@ -# -# Copyright (c) 2022 PHYTEC Messtechnik GmbH -# -# SPDX-License-Identifier: Apache-2.0 -# - -identifier: mimx8mp_phyboard_pollux/mimx8ml8/m7 -name: PhyBOARD Pollux (i.MX8MP) -type: mcu -arch: arm -ram: 128 -flash: 128 -toolchain: - - zephyr - - gnuarmemb - - xtools -testing: - ignore_tags: - - net - - bluetooth -supported: - - uart - - gpio -vendor: nxp diff --git a/boards/phytec/mimx8mp_phyboard_pollux/mimx8mp_phyboard_pollux_mimx8ml8_m7_defconfig b/boards/phytec/mimx8mp_phyboard_pollux/mimx8mp_phyboard_pollux_mimx8ml8_m7_defconfig deleted file mode 100644 index 4926fdbe4e1..00000000000 --- a/boards/phytec/mimx8mp_phyboard_pollux/mimx8mp_phyboard_pollux_mimx8ml8_m7_defconfig +++ /dev/null @@ -1,20 +0,0 @@ -# -# Copyright (c) 2022 PHYTEC Messtechnik GmbH -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_CORTEX_M_SYSTICK=y -CONFIG_CLOCK_CONTROL=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_CONSOLE=y - -# y for TCM memory space -CONFIG_CODE_ITCM=y - -# y for DDR memory space -CONFIG_CODE_DDR=n - -CONFIG_PINCTRL=y diff --git a/boards/phytec/phyboard_electra/phyboard_electra_am6442_m4_defconfig b/boards/phytec/phyboard_electra/phyboard_electra_am6442_m4_defconfig index 1e4d69df6a0..fb0c6223e41 100644 --- a/boards/phytec/phyboard_electra/phyboard_electra_am6442_m4_defconfig +++ b/boards/phytec/phyboard_electra/phyboard_electra_am6442_m4_defconfig @@ -11,9 +11,6 @@ CONFIG_CORTEX_M_SYSTICK=y # Zephyr Kernel Configuration CONFIG_XIP=n -# Enable Pinctrl -CONFIG_PINCTRL=y - # Serial Driver CONFIG_SERIAL=y diff --git a/boards/phytec/phyboard_lyra/phyboard_lyra_am6234_m4_defconfig b/boards/phytec/phyboard_lyra/phyboard_lyra_am6234_m4_defconfig index a54f04a25e1..f309fdf6a80 100644 --- a/boards/phytec/phyboard_lyra/phyboard_lyra_am6234_m4_defconfig +++ b/boards/phytec/phyboard_lyra/phyboard_lyra_am6234_m4_defconfig @@ -11,9 +11,6 @@ CONFIG_CORTEX_M_SYSTICK=y # Zephyr Kernel Configuration CONFIG_XIP=n -# Enable Pinctrl -CONFIG_PINCTRL=y - # Serial Driver CONFIG_SERIAL=y diff --git a/boards/phytec/phyboard_nash/Kconfig.phyboard_nash b/boards/phytec/phyboard_nash/Kconfig.phyboard_nash new file mode 100644 index 00000000000..4640f4aaee0 --- /dev/null +++ b/boards/phytec/phyboard_nash/Kconfig.phyboard_nash @@ -0,0 +1,7 @@ +# Copyright 2024 PHYTEC Messtechnik GmbH +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_PHYBOARD_NASH + select SOC_MIMX9352_A55 if BOARD_PHYBOARD_NASH_MIMX9352_A55 + select SOC_MIMX9352_M33 if BOARD_PHYBOARD_NASH_MIMX9352_M33 + select SOC_PART_NUMBER_MIMX9352CVVXM diff --git a/boards/phytec/phyboard_nash/board.cmake b/boards/phytec/phyboard_nash/board.cmake new file mode 100644 index 00000000000..37a788d10d8 --- /dev/null +++ b/boards/phytec/phyboard_nash/board.cmake @@ -0,0 +1,8 @@ +# Copyright (c) 2024, PHYTEC Messtechnik GmbH +# SPDX-License-Identifier: Apache-2.0 + +board_set_debugger_ifnset(jlink) +board_set_flasher_ifnset(jlink) + +board_runner_args(jlink "--device=MIMX9352_M33") +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/phytec/phyboard_nash/board.yml b/boards/phytec/phyboard_nash/board.yml new file mode 100644 index 00000000000..3e4c15bc14d --- /dev/null +++ b/boards/phytec/phyboard_nash/board.yml @@ -0,0 +1,6 @@ +board: + name: phyboard_nash + full_name: phyBOARD-Nash i.MX93 + vendor: phytec + socs: + - name: mimx9352 diff --git a/boards/phytec/phyboard_nash/doc/img/phyboard_nash.webp b/boards/phytec/phyboard_nash/doc/img/phyboard_nash.webp new file mode 100644 index 00000000000..05d4e30c56a Binary files /dev/null and b/boards/phytec/phyboard_nash/doc/img/phyboard_nash.webp differ diff --git a/boards/phytec/phyboard_nash/doc/index.rst b/boards/phytec/phyboard_nash/doc/index.rst new file mode 100644 index 00000000000..16c281e9962 --- /dev/null +++ b/boards/phytec/phyboard_nash/doc/index.rst @@ -0,0 +1,178 @@ +.. _phyboard_nash: + +phyBOARD-Nash i.MX93 +#################### + +Overview +******** + +The phyBOARD-Nash is based on the phyCORE-i.MX93 SoM is based on the NXP i.MX93 +SoC. It features common industrial interfaces and can be used as a reference for +development or in the final product. It is an entry-level development board, +which helps developers to get familiar with the module before investing a large +amount of resources in more specific designs. + +i.MX93 MPU is composed of one cluster of 2x Cortex-A55 cores and a single +Cortex-M33 core. Zephyr OS is ported to run on one of the Cortex-A55 core as +well as the Cortex-M33 core. + +- Memory: + + - RAM: 512 MB - 2GB LPDDR4 + - EEPROM: 4 kB - 32 kB + - eMMC: 8 GB - 256 GB + +- Interfaces: + + - Ethernet: 2x 10/100BASE-T (1x TSN Support) + - USB: 2x 2.0 Host / OTG + - Serial: 1x RS232 / RS485 Full Duplex / Half Duplex + - CAN: 1x CAN FD + - Digital I/O: via Expansion Connector + - MMX/SD/SDIO: microSD slot + - Display: LVDS(1x4 or 1x8), MIPI DSI(1x4), HDMI + - Audio: SAI + - Camera: 1x MIPI CSI-2 (phyCAM-M), 1x Parallel + - Expansion Bus: I2C, SPI, SDIO, UART, USB + +- Debug: + + - JTAG 10-pin connector + - USB-C for UART debug, 2x serial ports for A55 and M33 + + +.. image:: img/phyboard_nash.webp + :width: 720px + :align: center + :height: 405px + :alt: phyBOARD-Nash + +More information about the board can be found at the `PHYTEC website`_. + +Supported Features +================== + +The ``phyboard_nash/mimx9352/a55`` board target supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| GIC-v4 | on-chip | interrupt controller | ++-----------+------------+-------------------------------------+ +| ARM TIMER | on-chip | system clock | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++-----------+------------+-------------------------------------+ +| TPM | on-chip | TPM Counter | ++-----------+------------+-------------------------------------+ + +The ``phyboard_nash/mimx9352/m33`` board target supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++-----------+------------+-------------------------------------+ + +Devices +======== +System Clock +------------ + +This board configuration uses a system clock frequency of 24 MHz. Cortex-A55 +Core runs up to 1.7 GHz. Cortex-M33 Core runs up to 200MHz in which SYSTICK runs +on same frequency. + +Serial Port +----------- + +This board configuration uses a single serial communication channel with the +CPU's UART2 for A55 core and M33 core. The u-boot bootloader or Linux use the +second serial port for debug output. + +Programming and Debugging (A55) +******************************* + +Copy the compiled ``zephyr.bin`` to the ``BOOT`` partition of the SD card and +plug the SD card into the board. Power it up and stop the u-boot execution at +prompt. + +Use U-Boot to load and execute zephyr.bin on Cortex-A55 Core0: + +.. code-block:: console + + fatload mmc 1:1 0xd0000000 zephyr.bin; dcache flush; icache flush; dcache off; icache off; go 0xd0000000 + + +Use this configuration to run basic Zephyr applications and kernel tests, +for example: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: phyboard_nash/mimx9352/a55 + :goals: build + +Use this configuration to run basic Zephyr applications, for example: + +.. code-block:: console + + *** Booting Zephyr OS build v3.7.0-848-gb4d99b124c6d *** + Hello World! phyboard_nash/mimx9352/a55 + +Programming and Debugging (M33) +******************************* + +Copy the compiled ``zephyr.bin`` to the ``BOOT`` partition of the SD card and +plug the SD card into the board. Power it up and stop the u-boot execution at +prompt. + +Use U-Boot to load and kick zephyr.bin to Cortex-M33 Core: + +.. code-block:: console + + load mmc 1:1 0x80000000 zephyr.bin;cp.b 0x80000000 0x201e0000 0x30000;bootaux 0x1ffe0000 0 + +Use this configuration to run basic Zephyr applications, for example: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: phyboard_nash/mimx9352/m33 + :goals: build + +This will build an image with the synchronization sample app, boot it and +display the following console output: + +.. code-block:: console + + *** Booting Zephyr OS build v3.7.0-848-gb4d99b124c6d *** + Hello World! phyboard_nash/mimx9352/m33 + +Starting the M7-Core from U-Boot and Linux +========================================== + +Loading binaries and starting the M33-Core is supported from Linux via +remoteproc. Please check the `phyCORE-i.MX93 BSP Manual`_ for more information. + +References +========== + +For more information refer to the `PHYTEC website`_. + +.. _PHYTEC website: + https://www.phytec.eu/en/produkte/development-kits/phyboard-nash/ +.. _phyCORE-i.MX93 BSP Manual: + https://phytec.github.io/doc-bsp-yocto/bsp/imx9/imx93/imx93.html diff --git a/boards/phytec/phyboard_nash/phyboard_nash-pinctrl.dtsi b/boards/phytec/phyboard_nash/phyboard_nash-pinctrl.dtsi new file mode 100644 index 00000000000..b9bfda29c04 --- /dev/null +++ b/boards/phytec/phyboard_nash/phyboard_nash-pinctrl.dtsi @@ -0,0 +1,19 @@ +/* + * Copyright 2024 PHYTEC Messtechnik GmbH + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + uart2_default: uart2_default { + group0 { + pinmux = <&iomuxc1_uart2_rxd_lpuart_rx_lpuart2_rx>, + <&iomuxc1_uart2_txd_lpuart_tx_lpuart2_tx>; + bias-pull-up; + slew-rate = "slightly_fast"; + drive-strength = "x5"; + }; + }; +}; diff --git a/boards/phytec/phyboard_nash/phyboard_nash_a55.dts b/boards/phytec/phyboard_nash/phyboard_nash_a55.dts new file mode 100644 index 00000000000..0c6c67ad7ac --- /dev/null +++ b/boards/phytec/phyboard_nash/phyboard_nash_a55.dts @@ -0,0 +1,40 @@ +/* + * Copyright 2022,2024 NXP + * Copyright 2024 PHYTEC Messtechnik GmbH + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "phyboard_nash-pinctrl.dtsi" + +/ { + model = "PHYTEC phyBOARD-Nash i.MX93"; + compatible = "phytec,phyboard_nash"; + + chosen { + zephyr,console = &lpuart2; + zephyr,shell-uart = &lpuart2; + zephyr,sram = &sram0; + }; + + cpus { + cpu@0 { + status = "disabled"; + }; + }; + + sram0: memory@d0000000 { + reg = <0xd0000000 DT_SIZE_M(1)>; + }; +}; + +&lpuart2 { + status = "okay"; + current-speed = <115200>; + /* clocks = <&ccm IMX_CCM_UART4_CLK 0x6c 24>; */ + pinctrl-0 = <&uart2_default>; + pinctrl-names = "default"; +}; diff --git a/boards/phytec/phyboard_nash/phyboard_nash_a55.yaml b/boards/phytec/phyboard_nash/phyboard_nash_a55.yaml new file mode 100644 index 00000000000..b48692ee9e7 --- /dev/null +++ b/boards/phytec/phyboard_nash/phyboard_nash_a55.yaml @@ -0,0 +1,18 @@ +# Copyright 2024 PHYTEC Messtechnik GmbH +# SPDX-License-Identifier: Apache-2.0 + +identifier: phyboard_nash/mimx9352/a55 +name: PHYTEC phyBOARD-Nash i.MX93 A55 +type: mcu +arch: arm64 +toolchain: + - zephyr + - cross-compile +ram: 1024 +supported: + - uart +testing: + ignore_tags: + - net + - bluetooth +vendor: phytec diff --git a/boards/phytec/phyboard_nash/phyboard_nash_a55_defconfig b/boards/phytec/phyboard_nash/phyboard_nash_a55_defconfig new file mode 100644 index 00000000000..c714bcaac77 --- /dev/null +++ b/boards/phytec/phyboard_nash/phyboard_nash_a55_defconfig @@ -0,0 +1,24 @@ +# Copyright 2024 PHYTEC Messtechnik GmbH +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_CLOCK_CONTROL=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_CONSOLE=y + +# ARM Options +CONFIG_AARCH64_IMAGE_HEADER=y +CONFIG_ARMV8_A_NS=y + +# MMU Options +CONFIG_MAX_XLAT_TABLES=64 + +# Cache Options +CONFIG_CACHE_MANAGEMENT=y +CONFIG_DCACHE_LINE_SIZE_DETECT=y +CONFIG_ICACHE_LINE_SIZE_DETECT=y + +# Zephyr Kernel Configuration +CONFIG_XIP=n +CONFIG_KERNEL_DIRECT_MAP=y diff --git a/boards/phytec/phyboard_nash/phyboard_nash_m33.dts b/boards/phytec/phyboard_nash/phyboard_nash_m33.dts new file mode 100644 index 00000000000..e1fcbe244b0 --- /dev/null +++ b/boards/phytec/phyboard_nash/phyboard_nash_m33.dts @@ -0,0 +1,31 @@ +/* + * Copyright 2024 PHYTEC Messtechnik GmbH + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "phyboard_nash-pinctrl.dtsi" + +/ { + model = "PHYTEC phyBOARD-Nash i.MX93"; + compatible = "phytec,phyboard_nash"; + + chosen { + /* TCM */ + zephyr,flash = &itcm; + zephyr,sram = &dtcm; + + zephyr,console = &lpuart2; + zephyr,shell-uart = &lpuart2; + }; +}; + +&lpuart2 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart2_default>; + pinctrl-names = "default"; +}; diff --git a/boards/phytec/phyboard_nash/phyboard_nash_m33.yaml b/boards/phytec/phyboard_nash/phyboard_nash_m33.yaml new file mode 100644 index 00000000000..3927ba8d1db --- /dev/null +++ b/boards/phytec/phyboard_nash/phyboard_nash_m33.yaml @@ -0,0 +1,15 @@ +# Copyright 2024 PHYTEC Messtechnik GmbH +# SPDX-License-Identifier: Apache-2.0 + +identifier: phyboard_nash/mimx9352/m33 +name: PHYTEC phyBOARD Nash (i.MX93) M33 +type: mcu +arch: arm +toolchain: + - zephyr + - cross-compile +ram: 128 +flash: 128 +supported: + - uart +vendor: phytec diff --git a/boards/phytec/phyboard_nash/phyboard_nash_m33_defconfig b/boards/phytec/phyboard_nash/phyboard_nash_m33_defconfig new file mode 100644 index 00000000000..5538854b599 --- /dev/null +++ b/boards/phytec/phyboard_nash/phyboard_nash_m33_defconfig @@ -0,0 +1,9 @@ +# Copyright 2024 PHYTEC Messtechnik GmbH +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_CLOCK_CONTROL=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_CONSOLE=y +CONFIG_XIP=y diff --git a/boards/phytec/phyboard_polis/Kconfig.phyboard_polis b/boards/phytec/phyboard_polis/Kconfig.phyboard_polis new file mode 100644 index 00000000000..e409b0f0fc4 --- /dev/null +++ b/boards/phytec/phyboard_polis/Kconfig.phyboard_polis @@ -0,0 +1,7 @@ +# Copyright (c) 2022 PHYTEC Messtechnik GmbH +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_PHYBOARD_POLIS + select SOC_PART_NUMBER_MIMX8MM6DVTLZ + select SOC_MIMX8MM6_M4 if BOARD_PHYBOARD_POLIS_MIMX8MM6_M4 diff --git a/boards/phytec/mimx8mm_phyboard_polis/board.cmake b/boards/phytec/phyboard_polis/board.cmake similarity index 100% rename from boards/phytec/mimx8mm_phyboard_polis/board.cmake rename to boards/phytec/phyboard_polis/board.cmake diff --git a/boards/phytec/phyboard_polis/board.yml b/boards/phytec/phyboard_polis/board.yml new file mode 100644 index 00000000000..2ca447ffb92 --- /dev/null +++ b/boards/phytec/phyboard_polis/board.yml @@ -0,0 +1,6 @@ +board: + name: phyboard_polis + full_name: phyBOARD-Polis i.MX8M Mini + vendor: phytec + socs: + - name: mimx8mm6 diff --git a/boards/phytec/mimx8mm_phyboard_polis/doc/img/PEB-EVAL-01.jpg b/boards/phytec/phyboard_polis/doc/img/PEB-EVAL-01.jpg similarity index 100% rename from boards/phytec/mimx8mm_phyboard_polis/doc/img/PEB-EVAL-01.jpg rename to boards/phytec/phyboard_polis/doc/img/PEB-EVAL-01.jpg diff --git a/boards/phytec/mimx8mm_phyboard_polis/doc/img/phyBOARD-Polis.jpg b/boards/phytec/phyboard_polis/doc/img/phyBOARD-Polis.jpg similarity index 100% rename from boards/phytec/mimx8mm_phyboard_polis/doc/img/phyBOARD-Polis.jpg rename to boards/phytec/phyboard_polis/doc/img/phyBOARD-Polis.jpg diff --git a/boards/phytec/phyboard_polis/doc/index.rst b/boards/phytec/phyboard_polis/doc/index.rst new file mode 100644 index 00000000000..f1229b4b17b --- /dev/null +++ b/boards/phytec/phyboard_polis/doc/index.rst @@ -0,0 +1,404 @@ +.. _phyboard_polis: + +phyBOARD-Polis i.MX8M Mini +########################## + +Overview +******** + +The phyBOARD-Polis, either a development platform for the +phyCORE-i.MX 8M Mini/Nano, or a powerful, industry-compatible single-board +computer for immediate implementation of your product idea. As a development +platform, the phyBOARD-Polis serves as reference design for your +customer-specific application and enables parallel development of the software +and carrier board for the phyCORE-i.MX 8M Mini/Nano. + + +As a powerful, industrial single-board computer (SBC), the phyBOARD-Polis is +equipped with a variety of standard interfaces which are available on standard +or socket/pin header connectors, while interesting extensions of the +phyCORE-i.MX 8M Mini/Nano features such as CAN FD, WLAN and an integrated +TPM chip further extend the range of applications that can be developed with +the phyCORE-i.MX 8M Mini/Nano. + +- Board features: + + - RAM: 512MB - 4GB (LPDDR4) + - Storage: + + - 4GB - 128GB eMMC + - 8MB - 128MB SPI NOR Flash + - microSD Interface + - 4kB EEPROM + - Wireless: + + - WiFi: 802.11 b/g/n (ac) 2.4 GHz / 5 GHz + - BLE 4.2 + - USB: + + - 1x USB2.0 OTG + - 1x USB2.0 + - Ethernet: 1x 10/100/1000BASE-T + - Interfaces: + - 1x RS232 / RS485 + - 2x UART + - 3x I²C + - 2x SPI + - Up to 4x PWM + - 4x SAI + - 1x MIPI CSI-2 + - 1x MIPI DSI-2 + - 2x MMC/SD/SDIO + - 1x PCIe (mini PCIE) + - LEDs: + + - 1x Status LED (3 Color LED) + - 1x Debug UART LED + - Debug + + - JTAG 20-pin connector + - MicroUSB for UART debug, two COM ports for A53 and M4 + +.. image:: img/phyBOARD-Polis.jpg + :align: center + :alt: phyBOARD-Polis + :width: 500 + +More information about the board can be found at the +`PHYTEC website`_. + +Supported Features +================== + +The Zephyr ``phyboard_polis/mimx8mm6/m4`` board target configuration supports +the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | GPIO output | +| | | GPIO input | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | ECSPI | ++-----------+------------+-------------------------------------+ +| CAN | MCP2518 | MCP2518 via ECSPI | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/phytec/phyboard_polis/phyboard_polis_mimx8mm6_m4_defconfig`. + +It is recommended to disable peripherals used by the M4 core on the Linux host. + +Other hardware features are not currently supported with Zephyr on the +M4-Core. + +Connections and IOs +=================== + +The following components are tested and working correctly. + +UART: +----- + +Zephyr is configured to use UART4 on the phyBOARD-Polis by default to minimize +problems with the A53-Core because UART4 is only accessible from the M4-Core. + ++---------------+-----------------+-----------------------------------+ +| Board Name | SoM Name | Usage | ++===============+=================+===================================+ +| RS232/485 | UART1 | RS232 / RS485 with flow-control | ++---------------+-----------------+-----------------------------------+ +| To WiFi Module| UART2 | UART to WiFi/BLE Module | ++---------------+-----------------+-----------------------------------+ +| Debug USB(A53)| UART3 | UART Debug Console via USB | ++---------------+-----------------+-----------------------------------+ +| Debug USB(M4) | UART4 | UART Debug Console via USB | ++---------------+-----------------+-----------------------------------+ + +.. note:: + Please note, that the to UART2 connected Wifi/BLE Module isn't working with + Zephyr yet. + +.. warning:: + On Boards with the version number 1532.1 UART4 isn't connected to the Debug + USB. UART4 connects to pin 10(RX) and 12(TX) on the X8 pinheader. + +SPI: +---- + +ECSPI is disabled by default. On phyBOARD-Polis, the SoC's ECSPI3 is not +usable. +ECSPI1 is connected to the MCP2518 CAN controller with a chip select. +Another device can be connected via the expansion header (X8): +PIN 5, 6, 7, 8 (CS, MOSI, MISO, SCLK). +ECSPI2 is connected to the TPM module. Currently the TPM module is not +supported by Zephyr. + +.. note:: + Please note, that it is necessary to disable ECSPI1 in the Linux devicetree + before you can use it on the M4-Core with Zephyr. + See section "Disabling Interfaces in Linux" for more information. + +LEDs: +----- + +Zephyr has the 3-color status LED configured. The led0 alias (the standard +Zephyr LED) is configured to be the blue LED. The LED can also light up in red +and green. + +GPIO: +----- + +The pinmuxing for the GPIOs is the standard pinmuxing of the mimx8mm devicetree +created by NXP. You can find it here: + +CAN: +---- + +The MCP2518 is connected via ECSPI1. The CAN interface is disabled by default +to not interfere with Linux on the A53-Core. +If you want to use the CAN interface you need to disable ECSPI in the Linux +devicetree. + +.. warning:: + There is a bug in the MCP2518 driver that causes the enable pin of the + transceiver to be not set. This causes a ENETDOWN error when trying to send + a CAN frame. Receiving CAN frames in *listen-only* mode is possible. + +The Pinout of the phyBOARD-Polis can be found here: + +`PHYTEC website`_ + +System Clock +============ + +The M4 Core is configured to run at a 400 MHz clock speed. + + +Programming and Debugging +************************* + +The i.MX8MM does not have a separate flash for the M4-Core. Because of this +the A53-Core has to load the program for the M4-Core to the right memory +address, set the PC and start the processor. +This can be done with U-Boot or Phytec's Linux BSP via remoteproc. + +Because remoteproc in Phytec's BSP only writes to the TCM memory area, +everything was tested in this memory area. + +You can read more about remoteproc in Phytec's BSP here: `Remoteproc BSP`_ + +These are the memory mapping for A53 and M4: + ++------------+-------------------------+------------------------+-----------------------+----------------------+ +| Region | Cortex-A53 | Cortex-M4 (System Bus) | Cortex-M4 (Code Bus) | Size | ++============+=========================+========================+=======================+======================+ +| OCRAM | 0x00900000-0x0093FFFF | 0x20200000-0x2023FFFF | 0x00900000-0x0093FFFF | 256KB | ++------------+-------------------------+------------------------+-----------------------+----------------------+ +| TCMU | 0x00800000-0x0081FFFF | 0x20000000-0x2001FFFF | | 128KB | ++------------+-------------------------+------------------------+-----------------------+----------------------+ +| TCML | 0x007E0000-0x007FFFFF | | 0x1FFE0000-0x1FFFFFFF | 128KB | ++------------+-------------------------+------------------------+-----------------------+----------------------+ +| OCRAM_S | 0x00180000-0x00187FFF | 0x20180000-0x20187FFF | 0x00180000-0x00187FFF | 32KB | ++------------+-------------------------+------------------------+-----------------------+----------------------+ + +For more information about memory mapping see the +`i.MX 8M Applications Processor Reference Manual`_ (section 2.1.2 and 2.1.3) + +At compilation time you have to choose which RAM will be used. This +configuration is done in +:zephyr_file:`boards/phytec/phyboard_polis/phyboard_polis_mimx8mm6_m4.dts` +with "zephyr,flash" and "zephyr,sram" properties. + +The following configurations are possible for the flash and sram chosen nodes +to change the used memory area: + +.. code-block:: none + + "zephyr,flash" + - &tcml_code + - &ocram_code + - &ocram_s_code + + "zephyr,sram" + - &tcmu_sys + - &ocram_sys + - &ocram_s_sys + +By default Zephyr is configured to use the TCM memory area and CONFIG_XIP is +disabled. If you want to use the OCRAM memory area you have to enable +CONFIG_XIP. + +Starting the M4-Core via U-Boot +=============================== + +Load the compiled zephyr.bin to memory address 0x4800000. +This should output something like this: + +.. code-block:: console + + u-boot=> tftp 0x48000000 192.168.3.10:zephyr.bin + Using ethernet@30be0000 device + TFTP from server 192.168.3.10; our IP address is 192.168.3.11 + Filename 'zephyr.bin'. + Load address: 0x48000000 + Loading: ## + 2 KiB/s + done + Bytes transferred = 27240 (6a68 hex) + +Because it's not possible to load directly to the TCM memory area you have to +copy the binaries. The last argument given is the size of the file in bytes, +you can copy it from the output of the last command. + +.. code-block:: console + + u-boot=> cp.b 0x48000000 0x7e0000 27240 + +And finaly starting the M4-Core at the right memory address: + +.. code-block:: console + + u-boot=> bootaux 0x7e0000 + ## Starting auxiliary core stack = 0x20003A58, pc = 0x1FFE1905... + + +Starting the M4-Core via remoteproc +=================================== + +Copy the zephyr.elf to ``/lib/firmware`` on the target. Maybe a Zephyr sample +will be included in a future BSP release. + +.. note:: + In order to use remoteproc you have to add ``imx8mm-phycore-rpmsg.dtbo`` at + the end of the line in the ``/boot/bootenv.txt``, then reboot the target. + +.. warning:: + Remoteproc only reads firmware files from the ``/lib/firmware`` directory! + If you try to load a binary from another location unexpected errors will + occur! + +To load and start a firmware use this commands: + +.. code-block:: console + + target$ echo /lib/firmware/zephyr.elf > /sys/class/remoteproc/remoteproc0/firmware + target$ echo start > /sys/class/remoteproc/remoteproc0/state + [ 90.700611] remoteproc remoteproc0: powering up imx-rproc + [ 90.706114] remoteproc remoteproc0: Direct firmware load for /lib/firmware/zephyr.elf failed w2 + [ 90.716571] remoteproc remoteproc0: Falling back to sysfs fallback for: /lib/firmware/zephyr.elf + [ 90.739280] remoteproc remoteproc0: Booting fw image /lib/firmware/zephyr.elf, size 599356 + [ 90.804448] remoteproc remoteproc0: remote processor imx-rproc is now up + + +The M4-Core is now started up and running. You can see the output from Zephyr +on UART4. + +Debugging +========= + +The phyBOARD-Polis can be debugged using a JTAG Debugger. +The easiest way to do that is to use a SEGGER JLink Debugger and Phytec's +``PEB-EVAL-01`` Shield, which can be directly connected to the JLink. +You can find the JLink Software package here: `JLink Software`_ + +.. figure:: img/PEB-EVAL-01.jpg + :alt: PEB-EVAL-01 + :width: 350 + + PEB-EVAL-01 + +To debug efficiently you should use multiple terminals: + +(But its also possible to use ``west debug``) + +After connecting everything and building with west use this command while in +the directory of the program you built earlier to start a debug server: + +.. code-block:: console + + host$ west debugserver + +West automatically connects via the JLink to the Target. And keeps open a +debug server. + +Use another terminal, start gdb, connect to target and load Zephyr on the +target: + +.. code-block:: console + + host$ gdb-multiarch build/zephyr/zephyr.elf -tui + (gdb) targ rem :2331 + Remote debugging using :2331 + 0x1ffe0008 in _vector_table () + (gdb) mon halt + (gdb) mon reset + (gdb) c + Continuing. + +The program can be debugged using standard gdb techniques. + +Disabling Interfaces in Linux +============================= + +If Zephyr is used on the M4-Core while Linux runs on the A53-Core, it is +recommended to disable the Interfaces used by the M4-Core to avoid conflicts. +More simple interfaces can be enabled on both cores at the same time, for +example GPIO. If you do that, keep in mind that conflicts can still arise. + +For more complex interfaces like SPI it is necessary to disable them in the +Linux devicetree, otherwise Linux will probably crash in a panic, resetting +the SoC. +For example: disabling ECSPI1 in Linux to use it on the M4-Core with Zephyr: + +1. Create a new file called ``disable_spi.dts`` with the following content: + + .. code:: dts + + /dts-v1/; + /plugin/; + + / { + fragment@0 { + target = <&ecspi1>; + __overlay__ { + status = "disabled"; + }; + }; + }; + +2. Compile the file with the dtc compiler to a devicetree blob: + + .. code:: console + + $ dtc -@ -I dts -O dtb -o imx8mm-phyboard-polis-disable-spi.dtbo disable_spi.dts; + +3. Copy the compiled file to the boot partition of the target. +4. Add the filename to the ``/boot/bootenv.txt`` file at the end of the line. +5. Reboot the target, the SPI interface is now disabled in Linux. + +.. _PHYTEC website: + https://www.phytec.de/produkte/single-board-computer/phyboard-polis-imx8m-mini/ + +.. _phyBOARD-Polis pinout: + https://download.phytec.de/Products/phyBOARD-Polis-iMX8M_Mini/TechData/phyCORE-i.MX8M_MINI_Pin_Muxing_Table.A1.xlsx?_ga=2.237582016.1177557183.1660563641-1900651135.1634193918 + +.. _Remoteproc BSP: + https://wiki.phytec.com/pages/releaseview.action?pageId=472257137#L1002e.A3i.MX8MMini/NanoBSPManual-RunningExamplesfromLinuxusingRemoteproc + +.. _i.MX 8M Applications Processor Reference Manual: + https://www.nxp.com/webapp/Download?colCode=IMX8MMRM + +.. _JLink Software: + https://www.segger.com/downloads/jlink/ diff --git a/boards/phytec/phyboard_polis/phyboard_polis-pinctrl.dtsi b/boards/phytec/phyboard_polis/phyboard_polis-pinctrl.dtsi new file mode 100644 index 00000000000..9ff9ed6936c --- /dev/null +++ b/boards/phytec/phyboard_polis/phyboard_polis-pinctrl.dtsi @@ -0,0 +1,88 @@ +/* + * Copyright (c) 2022-2024 PHYTEC Messtechnik GmbH + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + uart4_default: uart4_default { + group0 { + pinmux = <&iomuxc_uart4_rxd_uart_rx_uart4_rx>, + <&iomuxc_uart4_txd_uart_tx_uart4_tx>; + slew-rate = "fast"; + drive-strength = "x6"; + }; + }; + + uart3_default: uart3_default { + group0 { + pinmux = <&iomuxc_uart3_rxd_uart_rx_uart3_rx>, + <&iomuxc_uart3_txd_uart_tx_uart3_tx>; + slew-rate = "fast"; + drive-strength = "x6"; + }; + }; + + uart2_default: uart2_default { + group0 { + pinmux = <&iomuxc_sai3_rxd_uart_cts_b_uart2_rts_b>, + <&iomuxc_sai3_rxd_uart_rts_b_uart2_rts_b>, + <&iomuxc_sai3_txfs_uart_tx_uart2_rx>, + <&iomuxc_sai3_txc_uart_rx_uart2_tx>; + slew-rate = "fast"; + drive-strength = "x6"; + }; + }; + + uart1_default: uart1_default { + group0 { + pinmux = <&iomuxc_sai2_rxfs_uart_rx_uart1_tx>, + <&iomuxc_sai2_rxc_uart_rx_uart1_rx>, + <&iomuxc_sai2_rxd0_uart_rts_b_uart1_rts_b>, + <&iomuxc_sai2_txfs_uart_cts_b_uart1_cts_b>; + slew-rate = "fast"; + drive-strength = "x6"; + }; + }; + + ecspi1_default: ecspi1_default { + group1 { + pinmux = <&iomuxc_ecspi1_miso_ecspi_miso_ecspi1_miso>, + <&iomuxc_ecspi1_mosi_ecspi_mosi_ecspi1_mosi>, + <&iomuxc_ecspi1_sclk_ecspi_sclk_ecspi1_sclk>; + slew-rate = "fast"; + drive-strength = "x6"; + }; + group2 { + pinmux = <&iomuxc_ecspi1_ss0_gpio_io_gpio5_io09>; + slew-rate = "fast"; + drive-strength = "x6"; + bias-pull-up; + }; + group3 { + pinmux = <&iomuxc_sd2_wp_gpio_io_gpio2_io20>; + slew-rate = "fast"; + drive-strength = "x6"; + bias-pull-up; + }; + }; + + ecspi2_default: ecspi2_default { + group1 { + pinmux = <&iomuxc_ecspi2_miso_ecspi_miso_ecspi2_miso>, + <&iomuxc_ecspi2_mosi_ecspi_mosi_ecspi2_mosi>, + <&iomuxc_ecspi2_sclk_ecspi_sclk_ecspi2_sclk>; + slew-rate = "fast"; + drive-strength = "x6"; + bias-pull-up; + }; + group2 { + pinmux = <&iomuxc_ecspi2_ss0_gpio_io_gpio5_io13>; + slew-rate = "fast"; + drive-strength = "x6"; + bias-pull-up; + }; + }; +}; diff --git a/boards/phytec/phyboard_polis/phyboard_polis_mimx8mm6_m4.dts b/boards/phytec/phyboard_polis/phyboard_polis_mimx8mm6_m4.dts new file mode 100644 index 00000000000..76f43a91fe3 --- /dev/null +++ b/boards/phytec/phyboard_polis/phyboard_polis_mimx8mm6_m4.dts @@ -0,0 +1,125 @@ +/* + * Copyright (c) 2022-2024 PHYTEC Messtechnik GmbH + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "phyboard_polis-pinctrl.dtsi" + +/ { + model = "phyBOARD-Polis i.MX8M Mini"; + compatible = "nxp,phyboard_polis"; + + aliases { + uart-4 = &uart4; + uart-3 = &uart3; + uart-2 = &uart2; + uart-1 = &uart1; + led0 = &led_blue; + }; + + chosen { + zephyr,flash = &tcml_code; + zephyr,sram = &tcmu_sys; + zephyr,console = &uart4; + zephyr,shell-uart = &uart4; + zephyr,canbus = &mcp2518; + }; + + leds { + compatible = "gpio-leds"; + + led_red: led_red { + gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; + }; + + led_blue: led_blue { + gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; + }; + + led_green: led_green { + gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; + }; + }; + +}; + +&ecspi1 { + status = "disabled"; + pinctrl-0 = <&ecspi1_default>; + pinctrl-names = "default"; + /* first cs is for on board MCP2518, the second for SPI on expansion header */ + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>, + <&gpio2 20 GPIO_ACTIVE_LOW>; + + /* CAN FD */ + mcp2518: mcp2518@0 { + compatible = "microchip,mcp251xfd"; + reg = <0>; + spi-max-frequency = <20000000>; + int-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; + supply-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; + osc-freq = <40000000>; + status = "disabled"; + }; +}; + +/* + * TPM Module TI SLB9670 + * Currently there is no driver for the used module + */ +&ecspi2 { + status = "disabled"; + pinctrl-0 = <&ecspi2_default>; + pinctrl-names = "default"; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; +}; + +/* RS232 / RS485 pinheader on the board */ +&uart1 { + status = "disabled"; + pinctrl-0 = <&uart1_default>; + pinctrl-names = "default"; + hw-flow-control; +}; + +/* + * UART to bluetooth module / X18 header + * Currently there is no driver for the used module + */ +&uart2 { + status = "disabled"; + pinctrl-0 = <&uart2_default>; + pinctrl-names = "default"; + hw-flow-control; +}; + +/* UART usually used from A53 Core (1st tty on Debug USB connector */ +&uart3 { + status = "disabled"; + pinctrl-0 = <&uart3_default>; + pinctrl-names = "default"; +}; + +/* UART of the M4 Core (2nd tty on Debug USB connector) */ +&uart4 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart4_default>; + pinctrl-names = "default"; +}; + +/* + * needs to be configured, so the leds don't generate an error, + * but does not interfer with the A53-Core + */ +&gpio1 { + status = "okay"; +}; + +&mailbox0 { + status = "okay"; +}; diff --git a/boards/phytec/phyboard_polis/phyboard_polis_mimx8mm6_m4.yaml b/boards/phytec/phyboard_polis/phyboard_polis_mimx8mm6_m4.yaml new file mode 100644 index 00000000000..5167e4d0aec --- /dev/null +++ b/boards/phytec/phyboard_polis/phyboard_polis_mimx8mm6_m4.yaml @@ -0,0 +1,26 @@ +# +# Copyright (c) 2020-2024 PHYTEC Messtechnik GmbH +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: phyboard_polis/mimx8mm6/m4 +name: phyBOARD-Polis i.MX8M Mini +type: mcu +arch: arm +ram: 128 +flash: 128 +toolchain: + - zephyr + - gnuarmemb + - xtools +testing: + ignore_tags: + - net + - bluetooth +supported: + - uart + - spi + - gpio + - can +vendor: nxp diff --git a/boards/phytec/phyboard_polis/phyboard_polis_mimx8mm6_m4_defconfig b/boards/phytec/phyboard_polis/phyboard_polis_mimx8mm6_m4_defconfig new file mode 100644 index 00000000000..533730db043 --- /dev/null +++ b/boards/phytec/phyboard_polis/phyboard_polis_mimx8mm6_m4_defconfig @@ -0,0 +1,13 @@ +# +# Copyright (c) 2022 PHYTEC Messtechnik GmbH +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_CORTEX_M_SYSTICK=y +CONFIG_CLOCK_CONTROL=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_CONSOLE=y +CONFIG_GPIO=y diff --git a/boards/phytec/phyboard_pollux/Kconfig.phyboard_pollux b/boards/phytec/phyboard_pollux/Kconfig.phyboard_pollux new file mode 100644 index 00000000000..3d09a55b2aa --- /dev/null +++ b/boards/phytec/phyboard_pollux/Kconfig.phyboard_pollux @@ -0,0 +1,6 @@ +# Copyright (c) 2022 PHYTEC Messtechnik GmbH +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_PHYBOARD_POLLUX + select SOC_MIMX8ML8_M7 if BOARD_PHYBOARD_POLLUX_MIMX8ML8_M7 + select SOC_PART_NUMBER_MIMX8ML8DVNLZ diff --git a/boards/phytec/mimx8mp_phyboard_pollux/board.cmake b/boards/phytec/phyboard_pollux/board.cmake similarity index 100% rename from boards/phytec/mimx8mp_phyboard_pollux/board.cmake rename to boards/phytec/phyboard_pollux/board.cmake diff --git a/boards/phytec/phyboard_pollux/board.yml b/boards/phytec/phyboard_pollux/board.yml new file mode 100644 index 00000000000..a636af4d8aa --- /dev/null +++ b/boards/phytec/phyboard_pollux/board.yml @@ -0,0 +1,6 @@ +board: + name: phyboard_pollux + full_name: phyBOARD-Pollux i.MX8M Plus + vendor: phytec + socs: + - name: mimx8ml8 diff --git a/boards/phytec/mimx8mp_phyboard_pollux/doc/img/PEB-EVAL-01.jpg b/boards/phytec/phyboard_pollux/doc/img/PEB-EVAL-01.jpg similarity index 100% rename from boards/phytec/mimx8mp_phyboard_pollux/doc/img/PEB-EVAL-01.jpg rename to boards/phytec/phyboard_pollux/doc/img/PEB-EVAL-01.jpg diff --git a/boards/phytec/mimx8mp_phyboard_pollux/doc/img/Phyboard_Pollux.jpg b/boards/phytec/phyboard_pollux/doc/img/Phyboard_Pollux.jpg similarity index 100% rename from boards/phytec/mimx8mp_phyboard_pollux/doc/img/Phyboard_Pollux.jpg rename to boards/phytec/phyboard_pollux/doc/img/Phyboard_Pollux.jpg diff --git a/boards/phytec/phyboard_pollux/doc/index.rst b/boards/phytec/phyboard_pollux/doc/index.rst new file mode 100644 index 00000000000..73fa347b783 --- /dev/null +++ b/boards/phytec/phyboard_pollux/doc/index.rst @@ -0,0 +1,262 @@ +.. _phyboard_pollux: + +phyBOARD-Pollux i.MX8M Plus +########################### + +Overview +******** + +The phyBOARD-Pollux is based upon the phyCORE-i.MX8M Plus SOM which is based on +the NXP i.MX8M Plus SoC. The SoC includes four Coretex-A53 cores and one +Coretex-M7 core for real time applications like Zephyr. The phyBOARD-Pollux +can be used for various applications like SmartHomes, Industry 4.0, IoT etc. +It features a lots of interfaces and computing capacity. It can be used as +a reference, to develop or in the final product too. + + +Board features: + +- Memory: + + - RAM: 256MB - 8GB LPDDR4 + - EEPROM: 4kB - 32kB + - eMMC: 4GB - 64GB (eMMC 5.1) + - SPI NOR Flash: 4MB - 256MB +- Interfaces: + + - Ethernet: 2x 10/100/1000BASE-T (1x TSN Support) + - USB: 2x 3.0 Host + - Serial: 1x RS232 / RS485 Full Duplex / Half Duplex + - CAN: 2x CAN FD + - Digital I/O: via Expansion Connector + - PCIe: 1x miniPCIe + - MMX/SD/SDIO: microSD slot + - Display: LVDS(1x4 or 1x8), MIPI DSI(1x4), HDMI + - Audio: SAI + - Camera: 2x MIPI CSI-2 (phyCAM-M) + - Expansion Bus: I2C, SPI, SDIO, UART, USB + - JTAG: via PEB-EVAL-01 +- LEDs: + + - 1x Multicolor Status LED via I2C + + +.. image:: img/Phyboard_Pollux.jpg + :width: 720px + :align: center + :height: 405px + :alt: phyBOARD-Pollux + +More information about the board can be found at the `PHYTEC website`_. + +Supported Features +================== + +The Zephyr phyboard_polis board configuration supports the following hardware +features: + ++-----------+------------+------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+------------------------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+------------------------------------+ +| GPIO | on-chip | GPIO output | +| | | GPIO input | ++-----------+------------+------------------------------------+ + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/phytec/phyboard_pollux/phyboard_pollux_mimx8ml8_m7_defconfig`. + +It's recommended to disable peripherals used by the M7-Core on the host running +on the Linux host. Other hardware features are not currently supported with +Zephyr on the M7-Core. + +Connections and IOs +=================== + +The following Compontens are tested and working correctly. + +UART +---- + ++-----------------+----------+----------------------------+ +| Board Name | SoM Name | Usage | ++=================+==========+============================+ +| Debug USB (A53) | UART1 | UART Debug Console via USB | ++-----------------+----------+----------------------------+ +| Wo WiFi Module | UART3 | UART to WiFi/BLE Module | ++-----------------+----------+----------------------------+ +| Debug USB (M7) | UART4 | UART Debug Console via USB | ++-----------------+----------+----------------------------+ + +.. note:: + The WiFi/BLE Module connected to UART3 isn't working with Zephyr yet. UART3 + can also be used through pin 31(RX) and 33(TX) of connector X6. + +GPIO +---- + +The pinmuxing for the GPIOs is the standard pinmuxing of the mimx8mp devicetree +created by NXP and can be found at +:zephyr_file:`dts/arm/nxp/nxp_imx8ml_m7.dtsi`. The Pinout of the phyBOARD-Polis +can be found at the `PHYTEC website`_. + +Programming and Debugging +************************* + +The i.MX8MP does not have a separate flash for the M7-Core. Because of this +the A53-Core has to load the program for the M7-Core to the right memory +address, set the PC and start the processor. + +The M7 can use up to 3 different RAMs (currently, only two configurations are +supported: ITCM and DDR). These are the memory mapping for A53 and M7: + ++---------+-----------------------+------------------------+-----------------------+-------+ +| Region | Cortex-A53 | Cortex-M7 (System Bus) | Cortex-M7 (Code Bus) | Size | ++=========+=======================+========================+=======================+=======+ +| OCRAM | 0x00900000-0x0098FFFF | 0x20200000-0x2028FFFF | 0x00900000-0x0098FFFF | 576KB | ++---------+-----------------------+------------------------+-----------------------+-------+ +| DTCM | 0x00800000-0x0081FFFF | 0x20000000-0x2001FFFF | | 128KB | ++---------+-----------------------+------------------------+-----------------------+-------+ +| ITCM | 0x007E0000-0x007FFFFF | | 0x00000000-0x0001FFFF | 128KB | ++---------+-----------------------+------------------------+-----------------------+-------+ +| OCRAM_S | 0x00180000-0x00188FFF | 0x20180000-0x20188FFF | 0x00180000-0x00188FFF | 36KB | ++---------+-----------------------+------------------------+-----------------------+-------+ +| DDR | 0x80000000-0x803FFFFF | 0x80200000-0x803FFFFF | 0x80000000-0x801FFFFF | 2MB | ++---------+-----------------------+------------------------+-----------------------+-------+ + +For more information about memory mapping see the +`i.MX 8M Plus Applications Processor Reference Manual`_ (section 2.1 to 2.3) + +At compilation time you have to choose which memory region will be used. This +configuration is done in the devicetree and the defconfig / the config of your +program. + +**By default Zephyr will use the TCM memory region.** You can configure it +to use the DDR region. In the devicetree overwrite you can select both options. + +.. code-block:: DTS + + chosen { + /* TCM */ + zephyr,flash = &itcm; + zephyr,sram = &dtcm; + }; + + +.. code-block:: DTS + + chosen { + /* DDR */ + zephyr,flash = &ddr_code; + zephyr,sram = &ddr_sys; + }; + + +And in the prj.conf the configuration to the **DDR** memory region: + +.. code-block:: cfg + + CONFIG_CODE_DDR=y + CONFIG_CODE_ITCM=n + +Connecting to the Serial Console +================================ + +A serial console for both the application CPU and the Cortex M7 coprocessor are +available via the onboard dual USB-to-UART converter. If you use Linux, create a +udev rule (as ``root``) to fix a permission issue when not using root for +flashing. + +.. code-block:: console + + # echo 'ATTR{idProduct}=="0a70", ATTR{idVendor}=="10c4", MODE="0666", GROUP="plugdev"' > /etc/udev/rules.d/50-usb-uart.rules + +Reload the rules and replug the device. + +.. code-block:: console + + $ sudo udevadm control --reload-rules + +Finally, unplug and plug the board again for the rules to take effect. + +Connect to the console via your favorite terminal program. For example: + +.. code-block:: console + + $ minicom -D /dev/ttyUSB1 -b 115200 + +Flashing and Debugging via JTAG +=============================== + +The phyBOARD-Pollux can be debugged using a JTAG or SWD debug adapter. A Segger +JLink can be connected to the compatible JTAG connector on Phytec's +``PEB-EVAL-01`` shield. + +.. figure:: img/PEB-EVAL-01.jpg + :alt: PEB-EVAL-01 + :width: 350 + + PEB-EVAL-01 + +Before flashing or debugging via a JTAG debug adapter, +the M7 core has to be switched on: + +.. code-block:: console + + u-boot=> bootaux 0x7e0000 + +Here is an example for the :zephyr:code-sample:`hello_world` application: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: phyboard_pollux/mimx8ml8/m7 + :goals: flash + +The console should now show the output of the application: + +.. code-block:: console + + *** Booting Zephyr OS build v3.7.0 *** + Hello World! phyboard_pollux/mimx8ml8/m7 + +Starting a debug session is similar to flashing: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: phyboard_pollux/mimx8ml8/m7 + :goals: debug + +Starting the M7-Core from U-Boot and Linux +========================================== + +Loading binaries and starting the M7-Core is supported from Linux via remoteproc +or from U-boot by directly copying the firmware binary. Please check the +`phyCORE-i.MX 8M Plus BSP Manual`_ for more information. + +References +========== + +- `i.MX 8M Plus Applications Processor Reference Manual`_ +- `phyCORE-i.MX 8M Plus BSP Manual`_ + +.. _PHYTEC website: + https://www.phytec.de/produkte/single-board-computer/phyboard-pollux/ + +.. _i.MX 8M Plus Applications Processor Reference Manual: + https://www.nxp.com/webapp/Download?colCode=IMX8MPRM + +.. _JLink Software: + https://www.segger.com/downloads/jlink/ + +.. _phyCORE-i.MX 8M Plus BSP Manual: + https://phytec.github.io/doc-bsp-yocto/bsp/imx8/imx8mp/imx8mp.html diff --git a/boards/phytec/mimx8mp_phyboard_pollux/mimx8mp_phyboard_pollux-pinctrl.dtsi b/boards/phytec/phyboard_pollux/phyboard_pollux-pinctrl.dtsi similarity index 100% rename from boards/phytec/mimx8mp_phyboard_pollux/mimx8mp_phyboard_pollux-pinctrl.dtsi rename to boards/phytec/phyboard_pollux/phyboard_pollux-pinctrl.dtsi diff --git a/boards/phytec/phyboard_pollux/phyboard_pollux_mimx8ml8_m7.dts b/boards/phytec/phyboard_pollux/phyboard_pollux_mimx8ml8_m7.dts new file mode 100644 index 00000000000..9376bfb1df7 --- /dev/null +++ b/boards/phytec/phyboard_pollux/phyboard_pollux_mimx8ml8_m7.dts @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2022 PHYTEC Messtechnik GmbH + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "phyboard_pollux-pinctrl.dtsi" + +/ { + model = "phyBOARD-Pollux i.MX8MP"; + compatible = "nxp,phyboard_pollux"; + + chosen { + /* TCM */ + zephyr,flash = &itcm; + zephyr,sram = &dtcm; + + zephyr,console = &uart4; + zephyr,shell-uart = &uart4; + }; + + soc { + /* + * BSP-Linux standard output. Can cause problems if used with standard bsp + */ + uart1: uart@30860000 { + compatible = "nxp,imx-iuart"; + reg = <0x30860000 0x10000>; + interrupts = <26 3>; + clocks = <&ccm IMX_CCM_UART1_CLK 0x7c 24>; + pinctrl-0 = <&uart1_default>; + pinctrl-names = "default"; + status = "disabled"; + }; + + /* + * to Bluetooth module (currently not supported by zephyr) + * Expansion header Pin 31(RX) 33(TX) + */ + uart3: uart@30880000 { + compatible = "nxp,imx-iuart"; + reg = <0x30880000 0x10000>; + interrupts = <28 3>; + clocks = <&ccm IMX_CCM_UART3_CLK 0x68 12>; + pinctrl-0 = <&uart3_default>; + pinctrl-names = "default"; + hw-flow-control; + status = "disabled"; + }; + }; +}; + +/* + * Standard uart for the M7-Core + */ +&uart4 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart4_default>; + pinctrl-names = "default"; +}; + +&mailbox0 { + status = "okay"; +}; diff --git a/boards/phytec/phyboard_pollux/phyboard_pollux_mimx8ml8_m7.yaml b/boards/phytec/phyboard_pollux/phyboard_pollux_mimx8ml8_m7.yaml new file mode 100644 index 00000000000..01084520792 --- /dev/null +++ b/boards/phytec/phyboard_pollux/phyboard_pollux_mimx8ml8_m7.yaml @@ -0,0 +1,24 @@ +# +# Copyright (c) 2022 PHYTEC Messtechnik GmbH +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: phyboard_pollux/mimx8ml8/m7 +name: phyBOARD-Pollux i.MX8MP +type: mcu +arch: arm +ram: 128 +flash: 128 +toolchain: + - zephyr + - gnuarmemb + - xtools +testing: + ignore_tags: + - net + - bluetooth +supported: + - uart + - gpio +vendor: nxp diff --git a/boards/phytec/phyboard_pollux/phyboard_pollux_mimx8ml8_m7_defconfig b/boards/phytec/phyboard_pollux/phyboard_pollux_mimx8ml8_m7_defconfig new file mode 100644 index 00000000000..23f5e9cd9a1 --- /dev/null +++ b/boards/phytec/phyboard_pollux/phyboard_pollux_mimx8ml8_m7_defconfig @@ -0,0 +1,18 @@ +# +# Copyright (c) 2022 PHYTEC Messtechnik GmbH +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_CORTEX_M_SYSTICK=y +CONFIG_CLOCK_CONTROL=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_CONSOLE=y + +# y for TCM memory space +CONFIG_CODE_ITCM=y + +# y for DDR memory space +CONFIG_CODE_DDR=n diff --git a/boards/phytec/reel_board/Kconfig.defconfig b/boards/phytec/reel_board/Kconfig.defconfig index 68061a3ef3b..0436c7b1d7a 100644 --- a/boards/phytec/reel_board/Kconfig.defconfig +++ b/boards/phytec/reel_board/Kconfig.defconfig @@ -8,10 +8,6 @@ if BOARD_REEL_BOARD config I2C default y -config BT_CTLR - default y - depends on BT - if FXOS8700 choice FXOS8700_MODE diff --git a/boards/phytec/reel_board/doc/index.rst b/boards/phytec/reel_board/doc/index.rst index d468a6c559a..7e588bebf86 100644 --- a/boards/phytec/reel_board/doc/index.rst +++ b/boards/phytec/reel_board/doc/index.rst @@ -552,6 +552,8 @@ your board. References ********** +.. target-notes:: + .. _reel board Website: https://www.phytec.de/reelboard/ diff --git a/boards/pine64/pinetime_devkit0/Kconfig.defconfig b/boards/pine64/pinetime_devkit0/Kconfig.defconfig index adfebb274d9..e83a778e2b6 100644 --- a/boards/pine64/pinetime_devkit0/Kconfig.defconfig +++ b/boards/pine64/pinetime_devkit0/Kconfig.defconfig @@ -5,9 +5,6 @@ if BOARD_PINETIME_DEVKIT0 -config BT_CTLR - default BT - config INPUT default y if LVGL diff --git a/boards/pine64/pinetime_devkit0/doc/img/PineTime_leaflet.jpg b/boards/pine64/pinetime_devkit0/doc/img/PineTime_leaflet.jpg deleted file mode 100644 index 8077093ac83..00000000000 Binary files a/boards/pine64/pinetime_devkit0/doc/img/PineTime_leaflet.jpg and /dev/null differ diff --git a/boards/pine64/pinetime_devkit0/doc/img/PineTime_DevKit0.jpg b/boards/pine64/pinetime_devkit0/doc/img/pinetime_devkit0.jpg similarity index 100% rename from boards/pine64/pinetime_devkit0/doc/img/PineTime_DevKit0.jpg rename to boards/pine64/pinetime_devkit0/doc/img/pinetime_devkit0.jpg diff --git a/boards/pine64/pinetime_devkit0/doc/index.rst b/boards/pine64/pinetime_devkit0/doc/index.rst index 16a04cd329c..097bbcf4a11 100644 --- a/boards/pine64/pinetime_devkit0/doc/index.rst +++ b/boards/pine64/pinetime_devkit0/doc/index.rst @@ -1,28 +1,12 @@ -.. _pinetime_devkit0: - -Pine64 PineTime DevKit0 -####################### +.. zephyr:board:: pinetime_devkit0 Overview ******** -.. figure:: img/PineTime_leaflet.jpg - :align: center - :alt: Pine64 PineTime - - PineTime leaflet (Credit: Pine64) - - The Pine64 smartwatch, dubbed "PineTime", is a product of a community effort for an open source smartwatch in collaboration with wearable RTOS and Linux app developers/communities. -.. figure:: img/PineTime_DevKit0.jpg - :align: center - :alt: Pine64 PineTime - - PineTime Dev Kit (Credit: Pine64) - Hardware ******** diff --git a/boards/pine64/pinetime_devkit0/pinetime_devkit0.dts b/boards/pine64/pinetime_devkit0/pinetime_devkit0.dts index 7bdf52d79e4..a93b91dfc65 100644 --- a/boards/pine64/pinetime_devkit0/pinetime_devkit0.dts +++ b/boards/pine64/pinetime_devkit0/pinetime_devkit0.dts @@ -27,6 +27,7 @@ zephyr,flash = &flash0; zephyr,code-partition = &slot0_partition; zephyr,display = &st7789v; + zephyr,touch = &cst816s; }; aliases { @@ -111,7 +112,7 @@ nvgam-param = [D0 04 0C 11 13 2C 3F 44 51 2F 1F 1F 20 23]; ram-param = [00 F0]; rgb-param = [CD 08 14]; - mipi-mode = ; + mipi-mode = "MIPI_DBI_MODE_SPI_4WIRE"; }; }; }; diff --git a/boards/pjrc/teensy4/Kconfig.defconfig b/boards/pjrc/teensy4/Kconfig.defconfig index 4bdd626e94a..2af9d12ef9f 100644 --- a/boards/pjrc/teensy4/Kconfig.defconfig +++ b/boards/pjrc/teensy4/Kconfig.defconfig @@ -13,4 +13,12 @@ config BUILD_OUTPUT_HEX config DISK_DRIVER_SDMMC default y if DISK_DRIVERS +if NETWORKING + +config NET_L2_ETHERNET + default n if BOARD_TEENSY40 + default y if BOARD_TEENSY41 + +endif # NETWORKING + endif # BOARD_TEENSY40 || BOARD_TEENSY41 diff --git a/boards/pjrc/teensy4/doc/index.rst b/boards/pjrc/teensy4/doc/index.rst index f9644699d68..66aefe952c0 100644 --- a/boards/pjrc/teensy4/doc/index.rst +++ b/boards/pjrc/teensy4/doc/index.rst @@ -225,6 +225,8 @@ etc.): References ********** +.. target-notes:: + .. _Teensy 4.0 Website: https://www.pjrc.com/store/teensy40.html diff --git a/boards/pjrc/teensy4/teensy4-pinctrl.dtsi b/boards/pjrc/teensy4/teensy4-pinctrl.dtsi index 430020f5098..c12573cb6b3 100644 --- a/boards/pjrc/teensy4/teensy4-pinctrl.dtsi +++ b/boards/pjrc/teensy4/teensy4-pinctrl.dtsi @@ -1,5 +1,6 @@ /* * Copyright (c) 2022, NXP + * Copyright (c) 2024, Bernhard Kraemer * SPDX-License-Identifier: Apache-2.0 * * Note: File generated by gen_board_pinctrl.py @@ -12,41 +13,40 @@ /* Mode Straps configuration DP83825 */ pinmux_enet: pinmux_enet { group0 { + pinmux = <&iomuxc_gpio_b1_10_enet_ref_clk>; + bias-disable; + drive-strength = "r0-6"; + slew-rate = "slow"; + nxp,speed = "100-mhz"; + input-enable; + }; + group1 { pinmux = <&iomuxc_gpio_b1_04_enet_rx_data0>, + <&iomuxc_gpio_b1_05_enet_rx_data1>, <&iomuxc_gpio_b1_06_enet_rx_en>, + <&iomuxc_gpio_b1_07_enet_tx_data0>, + <&iomuxc_gpio_b1_08_enet_tx_data1>, + <&iomuxc_gpio_b1_09_enet_tx_en>, <&iomuxc_gpio_b1_11_enet_rx_er>; drive-strength = "r0-5"; - bias-pull-down; - bias-pull-down-value = "100k"; - slew-rate = "fast"; - nxp,speed = "200-mhz"; - }; - group1 { - pinmux = <&iomuxc_gpio_b1_05_enet_rx_data1>; - drive-strength = "r0-5"; bias-pull-up; - bias-pull-up-value = "22k"; + bias-pull-up-value = "100k"; slew-rate = "fast"; nxp,speed = "200-mhz"; }; - group2 { - pinmux = <&iomuxc_gpio_b1_07_enet_tx_data0>, - <&iomuxc_gpio_b1_08_enet_tx_data1>, - <&iomuxc_gpio_b1_09_enet_tx_en>, - <&iomuxc_gpio_b1_14_enet_mdc>, + }; + + pinmux_enet_mdio: pinmux_enet_mdio { + group0 { + pinmux = <&iomuxc_gpio_b1_14_enet_mdc>, <&iomuxc_gpio_b1_15_enet_mdio>, <&iomuxc_gpio_b0_15_gpio2_io15>, <&iomuxc_gpio_b0_14_gpio2_io14>; - drive-strength = "r0-6"; - slew-rate = "slow"; - nxp,speed = "100-mhz"; - }; - group3 { - pinmux = <&iomuxc_gpio_b1_10_enet_ref_clk>; - drive-strength = "r0-6"; - slew-rate = "slow"; - nxp,speed = "100-mhz"; - input-enable; + drive-strength = "r0-5"; + bias-pull-up; + bias-pull-up-value = "100k"; + slew-rate = "fast"; + nxp,speed = "200-mhz"; }; }; diff --git a/boards/pjrc/teensy4/teensy40.dts b/boards/pjrc/teensy4/teensy40.dts index 63775c3d1c6..ddbefe8d8c9 100644 --- a/boards/pjrc/teensy4/teensy40.dts +++ b/boards/pjrc/teensy4/teensy40.dts @@ -70,24 +70,8 @@ zephyr_udc0: &usb1 { status = "okay"; }; -/* Pinmux settings */ -&enet_mac { - pinctrl-0 = <&pinmux_enet>; - pinctrl-names = "default"; - zephyr,random-mac-address; - phy-connection-type = "rmii"; - phy-handle = <&phy>; -}; - -&enet_mdio { +&edma0 { status = "okay"; - pinctrl-0 = <&pinmux_enet>; - pinctrl-names = "default"; - phy: phy@0 { - compatible = "ethernet-phy"; - reg = <0>; - status = "okay"; - }; }; &flexcan1 { diff --git a/boards/pjrc/teensy4/teensy40_defconfig b/boards/pjrc/teensy4/teensy40_defconfig index 1d186d986c4..e73b48be0a3 100644 --- a/boards/pjrc/teensy4/teensy40_defconfig +++ b/boards/pjrc/teensy4/teensy40_defconfig @@ -12,4 +12,3 @@ CONFIG_GPIO=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=600000000 CONFIG_ARM_MPU=y CONFIG_HW_STACK_PROTECTION=y -CONFIG_PINCTRL=y diff --git a/boards/pjrc/teensy4/teensy41.dts b/boards/pjrc/teensy4/teensy41.dts index e113183c66f..98fc9aa4f4c 100644 --- a/boards/pjrc/teensy4/teensy41.dts +++ b/boards/pjrc/teensy4/teensy41.dts @@ -34,6 +34,29 @@ }; }; +&enet_mac { + status = "okay"; + pinctrl-0 = <&pinmux_enet>; + pinctrl-names = "default"; + nxp,unique-mac; + phy-connection-type = "rmii"; + phy-handle = <&phy>; +}; + +&enet_mdio { + status = "okay"; + pinctrl-0 = <&pinmux_enet_mdio>; + pinctrl-names = "default"; + phy: phy@0 { + status = "okay"; + compatible = "ti,dp83825"; + reg = <0>; + reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>; + int-gpios = <&gpio2 15 GPIO_ACTIVE_LOW>; + ti,interface-type = "rmii"; + }; +}; + &lpspi3 { status = "okay"; }; @@ -48,6 +71,7 @@ pinctrl-names = "default", "slow", "med", "fast"; mmc { compatible = "zephyr,sdmmc-disk"; + disk-name = "SD"; status = "okay"; }; }; diff --git a/boards/pjrc/teensy4/teensy41.yaml b/boards/pjrc/teensy4/teensy41.yaml index b2ad1e303ca..18f320a2df6 100644 --- a/boards/pjrc/teensy4/teensy41.yaml +++ b/boards/pjrc/teensy4/teensy41.yaml @@ -19,6 +19,7 @@ supported: - gpio - sdhc - usb_device + - netif:eth testing: ignore_tags: - net diff --git a/boards/pjrc/teensy4/teensy41_defconfig b/boards/pjrc/teensy4/teensy41_defconfig index 1d186d986c4..e73b48be0a3 100644 --- a/boards/pjrc/teensy4/teensy41_defconfig +++ b/boards/pjrc/teensy4/teensy41_defconfig @@ -12,4 +12,3 @@ CONFIG_GPIO=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=600000000 CONFIG_ARM_MPU=y CONFIG_HW_STACK_PROTECTION=y -CONFIG_PINCTRL=y diff --git a/boards/qemu/arc/doc/index.rst b/boards/qemu/arc/doc/index.rst index 0aef5d8dc39..1c38701b22e 100644 --- a/boards/qemu/arc/doc/index.rst +++ b/boards/qemu/arc/doc/index.rst @@ -1,7 +1,4 @@ -.. _qemu_arc: - -ARCv2 & ARCv3 Emulation (QEMU) -############################### +.. zephyr:board:: qemu_arc Overview ******** diff --git a/boards/qemu/arc/qemu_arc_qemu_arc_em.yaml b/boards/qemu/arc/qemu_arc_qemu_arc_em.yaml index 15adaf6b25a..d409cbf34b7 100644 --- a/boards/qemu/arc/qemu_arc_qemu_arc_em.yaml +++ b/boards/qemu/arc/qemu_arc_qemu_arc_em.yaml @@ -1,7 +1,8 @@ identifier: qemu_arc/qemu_arc_em name: QEMU Emulation for ARC EM type: qemu -simulation: qemu +simulation: + - name: qemu arch: arc toolchain: - zephyr diff --git a/boards/qemu/arc/qemu_arc_qemu_arc_hs.yaml b/boards/qemu/arc/qemu_arc_qemu_arc_hs.yaml index 92ea09d4ee8..0e568f34a79 100644 --- a/boards/qemu/arc/qemu_arc_qemu_arc_hs.yaml +++ b/boards/qemu/arc/qemu_arc_qemu_arc_hs.yaml @@ -1,7 +1,8 @@ identifier: qemu_arc/qemu_arc_hs name: QEMU Emulation for ARC HS type: qemu -simulation: qemu +simulation: + - name: qemu arch: arc toolchain: - zephyr diff --git a/boards/qemu/arc/qemu_arc_qemu_arc_hs5x.yaml b/boards/qemu/arc/qemu_arc_qemu_arc_hs5x.yaml index 152fbf0b5c0..819a8cf9249 100644 --- a/boards/qemu/arc/qemu_arc_qemu_arc_hs5x.yaml +++ b/boards/qemu/arc/qemu_arc_qemu_arc_hs5x.yaml @@ -1,7 +1,8 @@ identifier: qemu_arc/qemu_arc_hs5x name: QEMU Emulation for ARC HS5x type: qemu -simulation: qemu +simulation: + - name: qemu arch: arc toolchain: - zephyr diff --git a/boards/qemu/arc/qemu_arc_qemu_arc_hs6x.yaml b/boards/qemu/arc/qemu_arc_qemu_arc_hs6x.yaml index 94b4342a40a..901d15dd34f 100644 --- a/boards/qemu/arc/qemu_arc_qemu_arc_hs6x.yaml +++ b/boards/qemu/arc/qemu_arc_qemu_arc_hs6x.yaml @@ -1,7 +1,8 @@ identifier: qemu_arc/qemu_arc_hs6x name: QEMU Emulation for ARC HS6x type: qemu -simulation: qemu +simulation: + - name: qemu arch: arc toolchain: - cross-compile diff --git a/boards/qemu/arc/qemu_arc_qemu_arc_hs_xip.yaml b/boards/qemu/arc/qemu_arc_qemu_arc_hs_xip.yaml index dec824ec6b0..928ec24190e 100644 --- a/boards/qemu/arc/qemu_arc_qemu_arc_hs_xip.yaml +++ b/boards/qemu/arc/qemu_arc_qemu_arc_hs_xip.yaml @@ -1,7 +1,8 @@ identifier: qemu_arc/qemu_arc_hs/xip name: QEMU Emulation for ARC HS (XIP) type: qemu -simulation: qemu +simulation: + - name: qemu arch: arc toolchain: - zephyr diff --git a/boards/qemu/cortex_a53/doc/index.rst b/boards/qemu/cortex_a53/doc/index.rst index 930671bb927..d6e2e307b09 100644 --- a/boards/qemu/cortex_a53/doc/index.rst +++ b/boards/qemu/cortex_a53/doc/index.rst @@ -1,7 +1,4 @@ -.. _qemu_cortex_a53: - -ARM Cortex-A53 Emulation (QEMU) -############################### +.. zephyr:board:: qemu_cortex_a53 Overview ******** @@ -103,6 +100,8 @@ and shell would need to be disabled, therefore this is not directly supported. References ********** +.. target-notes:: + 1. (ID050815) ARM® Cortex®-A Series - Programmer’s Guide for ARMv8-A 2. (ID070919) Arm® Architecture Reference Manual - Armv8, for Armv8-A architecture profile 3. (ARM DAI 0527A) Application Note Bare-metal Boot Code for ARMv8-A Processors diff --git a/boards/qemu/cortex_a53/qemu_cortex_a53.yaml b/boards/qemu/cortex_a53/qemu_cortex_a53.yaml index b447db17f67..509a461422f 100644 --- a/boards/qemu/cortex_a53/qemu_cortex_a53.yaml +++ b/boards/qemu/cortex_a53/qemu_cortex_a53.yaml @@ -1,7 +1,8 @@ identifier: qemu_cortex_a53 name: QEMU Emulation for Cortex-A53 type: qemu -simulation: qemu +simulation: + - name: qemu arch: arm64 toolchain: - zephyr diff --git a/boards/qemu/cortex_a53/qemu_cortex_a53_qemu_cortex_a53_smp.yaml b/boards/qemu/cortex_a53/qemu_cortex_a53_qemu_cortex_a53_smp.yaml index 4804d064564..2a7e489a559 100644 --- a/boards/qemu/cortex_a53/qemu_cortex_a53_qemu_cortex_a53_smp.yaml +++ b/boards/qemu/cortex_a53/qemu_cortex_a53_qemu_cortex_a53_smp.yaml @@ -1,7 +1,8 @@ identifier: qemu_cortex_a53/qemu_cortex_a53/smp name: QEMU Emulation for Cortex-A53 SMP type: qemu -simulation: qemu +simulation: + - name: qemu arch: arm64 toolchain: - zephyr diff --git a/boards/qemu/cortex_a53/qemu_cortex_a53_qemu_cortex_a53_xip.yaml b/boards/qemu/cortex_a53/qemu_cortex_a53_qemu_cortex_a53_xip.yaml index 5805780ee33..e00d8611b14 100644 --- a/boards/qemu/cortex_a53/qemu_cortex_a53_qemu_cortex_a53_xip.yaml +++ b/boards/qemu/cortex_a53/qemu_cortex_a53_qemu_cortex_a53_xip.yaml @@ -1,7 +1,8 @@ identifier: qemu_cortex_a53/qemu_cortex_a53/xip name: QEMU Emulation for Cortex-A53 (XIP) type: qemu -simulation: qemu +simulation: + - name: qemu arch: arm64 toolchain: - zephyr diff --git a/boards/qemu/cortex_a9/qemu_cortex_a9.yaml b/boards/qemu/cortex_a9/qemu_cortex_a9.yaml index cf8853c3d5f..eb3e9ccc2c2 100644 --- a/boards/qemu/cortex_a9/qemu_cortex_a9.yaml +++ b/boards/qemu/cortex_a9/qemu_cortex_a9.yaml @@ -8,7 +8,8 @@ identifier: qemu_cortex_a9 name: QEMU Emulation for Cortex-A9 type: qemu -simulation: qemu +simulation: + - name: qemu arch: arm toolchain: - zephyr diff --git a/boards/qemu/cortex_m0/doc/index.rst b/boards/qemu/cortex_m0/doc/index.rst index 7035f57b07f..e091ace42a7 100644 --- a/boards/qemu/cortex_m0/doc/index.rst +++ b/boards/qemu/cortex_m0/doc/index.rst @@ -1,7 +1,4 @@ -.. _qemu_cortex_m0: - -ARM Cortex-M0 Emulation (QEMU) -############################## +.. zephyr:board:: qemu_cortex_m0 Overview ******** diff --git a/boards/qemu/cortex_m0/qemu_cortex_m0.yaml b/boards/qemu/cortex_m0/qemu_cortex_m0.yaml index a0605830d5e..5d6f166eeb7 100644 --- a/boards/qemu/cortex_m0/qemu_cortex_m0.yaml +++ b/boards/qemu/cortex_m0/qemu_cortex_m0.yaml @@ -1,7 +1,8 @@ identifier: qemu_cortex_m0 name: QEMU Emulation for Cortex-M0 type: qemu -simulation: qemu +simulation: + - name: qemu arch: arm toolchain: - zephyr diff --git a/boards/qemu/cortex_m3/Kconfig.defconfig b/boards/qemu/cortex_m3/Kconfig.defconfig index 07f168ce414..13b7fc07a9b 100644 --- a/boards/qemu/cortex_m3/Kconfig.defconfig +++ b/boards/qemu/cortex_m3/Kconfig.defconfig @@ -12,4 +12,12 @@ choice NULL_POINTER_EXCEPTION_DETECTION default NULL_POINTER_EXCEPTION_DETECTION_NONE endchoice +# BT relies on PSA Crypto API to perform crypto operations and, on this platform, +# these APIs are provided thougth Mbed TLS. Unfortunately this platform is not +# provided with a true random number generator which is required to properly +# initialize the PSA Crypto core, so we need to enable the fake TEST_RANDOM_GENERATOR. +config TEST_RANDOM_GENERATOR + bool + default y if BT + endif # BOARD_QEMU_CORTEX_M3 diff --git a/boards/qemu/cortex_m3/doc/index.rst b/boards/qemu/cortex_m3/doc/index.rst index f07f6bf2166..96eb19bc375 100644 --- a/boards/qemu/cortex_m3/doc/index.rst +++ b/boards/qemu/cortex_m3/doc/index.rst @@ -1,7 +1,4 @@ -.. _qemu_cortex_m3: - -ARM Cortex-M3 Emulation (QEMU) -############################## +.. zephyr:board:: qemu_cortex_m3 Overview ******** diff --git a/boards/qemu/cortex_m3/qemu_cortex_m3.yaml b/boards/qemu/cortex_m3/qemu_cortex_m3.yaml index cceafa8942e..70f17485495 100644 --- a/boards/qemu/cortex_m3/qemu_cortex_m3.yaml +++ b/boards/qemu/cortex_m3/qemu_cortex_m3.yaml @@ -1,7 +1,8 @@ identifier: qemu_cortex_m3 name: QEMU Emulation for Cortex-M3 type: qemu -simulation: qemu +simulation: + - name: qemu arch: arm toolchain: - zephyr diff --git a/boards/qemu/cortex_r5/doc/index.rst b/boards/qemu/cortex_r5/doc/index.rst index 9fd59d117ac..9d385b5a578 100644 --- a/boards/qemu/cortex_r5/doc/index.rst +++ b/boards/qemu/cortex_r5/doc/index.rst @@ -1,7 +1,4 @@ -.. _qemu_cortex_r5: - -ARM Cortex-R5 Emulation (QEMU) -############################## +.. zephyr:board:: qemu_cortex_r5 Overview ******** @@ -99,6 +96,8 @@ Refer to the detailed overview about :ref:`application_debugging`. References ********** +.. target-notes:: + 1. ARMv7-A and ARMv7-R Architecture Reference Manual (ARM DDI 0406C ID051414) 2. Cortex-R5 and Cortex-R5F Technical Reference Manual (ARM DDI 0460C ID021511) 3. Zynq UltraScale+ Device Technical Reference Manual (UG1085) diff --git a/boards/qemu/cortex_r5/qemu_cortex_r5.yaml b/boards/qemu/cortex_r5/qemu_cortex_r5.yaml index 17fbb1c8d94..120c983fec2 100644 --- a/boards/qemu/cortex_r5/qemu_cortex_r5.yaml +++ b/boards/qemu/cortex_r5/qemu_cortex_r5.yaml @@ -1,7 +1,8 @@ identifier: qemu_cortex_r5 name: QEMU Emulation for Cortex-R5 type: qemu -simulation: qemu +simulation: + - name: qemu arch: arm toolchain: - zephyr diff --git a/boards/qemu/kvm_arm64/doc/index.rst b/boards/qemu/kvm_arm64/doc/index.rst index 79eabb5c50f..e1341211e46 100644 --- a/boards/qemu/kvm_arm64/doc/index.rst +++ b/boards/qemu/kvm_arm64/doc/index.rst @@ -1,7 +1,4 @@ -.. _qemu_kvm_arm64: - -ARM AArch64 Virt KVM Emulation (QEMU) -##################################### +.. zephyr:board:: qemu_kvm_arm64 Overview ******** diff --git a/boards/qemu/leon3/doc/index.rst b/boards/qemu/leon3/doc/index.rst index 4e0599697fd..32a85ebbc5a 100644 --- a/boards/qemu/leon3/doc/index.rst +++ b/boards/qemu/leon3/doc/index.rst @@ -1,7 +1,4 @@ -.. _qemu_leon3: - -LEON3 Emulation (QEMU) -###################### +.. zephyr:board:: qemu_leon3 Overview ******** diff --git a/boards/qemu/leon3/qemu_leon3.yaml b/boards/qemu/leon3/qemu_leon3.yaml index 1db6f50a8cb..9e21ec42bbb 100644 --- a/boards/qemu/leon3/qemu_leon3.yaml +++ b/boards/qemu/leon3/qemu_leon3.yaml @@ -1,7 +1,8 @@ identifier: qemu_leon3 name: QEMU Emulation for LEON3 type: qemu -simulation: qemu +simulation: + - name: qemu arch: sparc ram: 1048576 flash: 524288 diff --git a/boards/qemu/malta/doc/index.rst b/boards/qemu/malta/doc/index.rst index 014d2ae9c78..f10dcc8c8df 100644 --- a/boards/qemu/malta/doc/index.rst +++ b/boards/qemu/malta/doc/index.rst @@ -1,7 +1,4 @@ -.. _qemu_malta: - -MIPS Malta Emulation (QEMU) -########################### +.. zephyr:board:: qemu_malta Overview ******** diff --git a/boards/qemu/malta/qemu_malta.yaml b/boards/qemu/malta/qemu_malta.yaml index 083fb0e93b1..836d037aabb 100644 --- a/boards/qemu/malta/qemu_malta.yaml +++ b/boards/qemu/malta/qemu_malta.yaml @@ -1,7 +1,8 @@ identifier: qemu_malta name: QEMU emulation for MIPS (little endian) type: qemu -simulation: qemu +simulation: + - name: qemu arch: mips toolchain: - zephyr diff --git a/boards/qemu/malta/qemu_malta_qemu_malta_be.yaml b/boards/qemu/malta/qemu_malta_qemu_malta_be.yaml index 3bdbe8fa5c8..a20cc223e85 100644 --- a/boards/qemu/malta/qemu_malta_qemu_malta_be.yaml +++ b/boards/qemu/malta/qemu_malta_qemu_malta_be.yaml @@ -1,7 +1,8 @@ identifier: qemu_malta/qemu_malta/be name: QEMU emulation for MIPS (big endian) type: qemu -simulation: qemu +simulation: + - name: qemu arch: mips toolchain: - zephyr diff --git a/boards/qemu/nios2/doc/index.rst b/boards/qemu/nios2/doc/index.rst index 9dcef10a451..81717ab91b4 100644 --- a/boards/qemu/nios2/doc/index.rst +++ b/boards/qemu/nios2/doc/index.rst @@ -1,7 +1,4 @@ -.. _qemu_nios2: - -Altera Nios-II Emulation (QEMU) -############################### +.. zephyr:board:: qemu_nios2 Overview ******** diff --git a/boards/qemu/nios2/qemu_nios2.yaml b/boards/qemu/nios2/qemu_nios2.yaml index 6f170873486..c0a3cf21644 100644 --- a/boards/qemu/nios2/qemu_nios2.yaml +++ b/boards/qemu/nios2/qemu_nios2.yaml @@ -1,7 +1,8 @@ identifier: qemu_nios2 name: QEMU Emulation for NIOS II type: qemu -simulation: qemu +simulation: + - name: qemu arch: nios2 ram: 128 flash: 128 diff --git a/boards/qemu/riscv32/doc/index.rst b/boards/qemu/riscv32/doc/index.rst index cf33745e198..ef2e3f91623 100644 --- a/boards/qemu/riscv32/doc/index.rst +++ b/boards/qemu/riscv32/doc/index.rst @@ -1,7 +1,4 @@ -.. _qemu_riscv32: - -RISCV32 Emulation (QEMU) -######################## +.. zephyr:board:: qemu_riscv32 Overview ******** diff --git a/boards/qemu/riscv32/qemu_riscv32.yaml b/boards/qemu/riscv32/qemu_riscv32.yaml index f01b63c2e41..6421fe744bd 100644 --- a/boards/qemu/riscv32/qemu_riscv32.yaml +++ b/boards/qemu/riscv32/qemu_riscv32.yaml @@ -1,7 +1,8 @@ identifier: qemu_riscv32 name: QEMU Emulation for RISC-V 32-bit type: qemu -simulation: qemu +simulation: + - name: qemu arch: riscv toolchain: - zephyr diff --git a/boards/qemu/riscv32/qemu_riscv32_qemu_virt_riscv32_smp.yaml b/boards/qemu/riscv32/qemu_riscv32_qemu_virt_riscv32_smp.yaml index ee9af4a3083..368fa750090 100644 --- a/boards/qemu/riscv32/qemu_riscv32_qemu_virt_riscv32_smp.yaml +++ b/boards/qemu/riscv32/qemu_riscv32_qemu_virt_riscv32_smp.yaml @@ -1,7 +1,8 @@ identifier: qemu_riscv32/qemu_virt_riscv32/smp name: QEMU Emulation for RISC-V 32-bit SMP type: qemu -simulation: qemu +simulation: + - name: qemu arch: riscv toolchain: - zephyr diff --git a/boards/qemu/riscv32_xip/doc/index.rst b/boards/qemu/riscv32_xip/doc/index.rst index 4cc4f30522f..aea547ff75d 100644 --- a/boards/qemu/riscv32_xip/doc/index.rst +++ b/boards/qemu/riscv32_xip/doc/index.rst @@ -1,7 +1,4 @@ -.. _qemu_riscv32_xip: - -RISCV32 XIP Emulation (QEMU) -############################ +.. zephyr:board:: qemu_riscv32_xip Overview ******** diff --git a/boards/qemu/riscv32_xip/qemu_riscv32_xip.yaml b/boards/qemu/riscv32_xip/qemu_riscv32_xip.yaml index 8111ffda678..2e21c4acd2f 100644 --- a/boards/qemu/riscv32_xip/qemu_riscv32_xip.yaml +++ b/boards/qemu/riscv32_xip/qemu_riscv32_xip.yaml @@ -1,7 +1,8 @@ identifier: qemu_riscv32_xip name: QEMU Emulation for RISC-V 32-bit in XIP mode type: qemu -simulation: qemu +simulation: + - name: qemu arch: riscv ram: 16 toolchain: diff --git a/boards/qemu/riscv32_xip/qemu_riscv32_xip_defconfig b/boards/qemu/riscv32_xip/qemu_riscv32_xip_defconfig index 578726a799f..b356602b0a0 100644 --- a/boards/qemu/riscv32_xip/qemu_riscv32_xip_defconfig +++ b/boards/qemu/riscv32_xip/qemu_riscv32_xip_defconfig @@ -4,7 +4,6 @@ CONFIG_CONSOLE=y CONFIG_SERIAL=y CONFIG_UART_SIFIVE_PORT_0=y CONFIG_UART_CONSOLE=y -CONFIG_PINCTRL=y CONFIG_GPIO=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=10000000 CONFIG_QEMU_ICOUNT_SHIFT=6 diff --git a/boards/qemu/riscv32e/board.yml b/boards/qemu/riscv32e/board.yml index e4b41d79f3e..e720485ff43 100644 --- a/boards/qemu/riscv32e/board.yml +++ b/boards/qemu/riscv32e/board.yml @@ -1,6 +1,6 @@ board: name: qemu_riscv32e - full_name: QEMU Emulation for RISCV32E Emulation + full_name: QEMU Emulation for RISCV32E vendor: qemu socs: - name: qemu_virt_riscv32e diff --git a/boards/qemu/riscv32e/doc/index.rst b/boards/qemu/riscv32e/doc/index.rst index 15981f00c8e..6b47c3a3639 100644 --- a/boards/qemu/riscv32e/doc/index.rst +++ b/boards/qemu/riscv32e/doc/index.rst @@ -1,7 +1,4 @@ -.. _qemu_riscv32e: - -RISCV32E Emulation (QEMU) -######################### +.. zephyr:board:: qemu_riscv32e Overview ******** diff --git a/boards/qemu/riscv32e/qemu_riscv32e.yaml b/boards/qemu/riscv32e/qemu_riscv32e.yaml index 1d9d4d588e6..8159d8c6292 100644 --- a/boards/qemu/riscv32e/qemu_riscv32e.yaml +++ b/boards/qemu/riscv32e/qemu_riscv32e.yaml @@ -1,7 +1,8 @@ identifier: qemu_riscv32e name: QEMU Emulation for RISC-V (RV32E) 32-bit type: qemu -simulation: qemu +simulation: + - name: qemu arch: riscv toolchain: - zephyr diff --git a/boards/qemu/riscv64/doc/index.rst b/boards/qemu/riscv64/doc/index.rst index e58df91f679..79d4f6d155f 100644 --- a/boards/qemu/riscv64/doc/index.rst +++ b/boards/qemu/riscv64/doc/index.rst @@ -1,7 +1,4 @@ -.. _qemu_riscv64: - -RISCV64 Emulation (QEMU) -######################## +.. zephyr:board:: qemu_riscv64 Overview ******** diff --git a/boards/qemu/riscv64/qemu_riscv64.yaml b/boards/qemu/riscv64/qemu_riscv64.yaml index 82bf68f3b1d..fc840e29886 100644 --- a/boards/qemu/riscv64/qemu_riscv64.yaml +++ b/boards/qemu/riscv64/qemu_riscv64.yaml @@ -1,7 +1,8 @@ identifier: qemu_riscv64 name: QEMU Emulation for RISC-V 64-bit type: qemu -simulation: qemu +simulation: + - name: qemu arch: riscv toolchain: - zephyr diff --git a/boards/qemu/riscv64/qemu_riscv64_qemu_virt_riscv64_smp.yaml b/boards/qemu/riscv64/qemu_riscv64_qemu_virt_riscv64_smp.yaml index 3b39ef7499d..914aec92c1a 100644 --- a/boards/qemu/riscv64/qemu_riscv64_qemu_virt_riscv64_smp.yaml +++ b/boards/qemu/riscv64/qemu_riscv64_qemu_virt_riscv64_smp.yaml @@ -1,7 +1,8 @@ identifier: qemu_riscv64/qemu_virt_riscv64/smp name: QEMU Emulation for RISC-V 64-bit SMP type: qemu -simulation: qemu +simulation: + - name: qemu arch: riscv toolchain: - zephyr diff --git a/boards/qemu/x86/doc/index.rst b/boards/qemu/x86/doc/index.rst index 2fdba13bc09..98e0098d39a 100644 --- a/boards/qemu/x86/doc/index.rst +++ b/boards/qemu/x86/doc/index.rst @@ -1,7 +1,4 @@ -.. _qemu_x86: - -X86 Emulation (QEMU) -#################### +.. zephyr:board:: qemu_x86 Overview ******** diff --git a/boards/qemu/x86/qemu_x86.dts b/boards/qemu/x86/qemu_x86.dts index 907e8a1ec1c..e26bf00057f 100644 --- a/boards/qemu/x86/qemu_x86.dts +++ b/boards/qemu/x86/qemu_x86.dts @@ -166,3 +166,7 @@ }; }; }; + +&cpu { + compatible = "intel,x86"; +}; diff --git a/boards/qemu/x86/qemu_x86.yaml b/boards/qemu/x86/qemu_x86.yaml index ae8bd13f9ca..09ed538e457 100644 --- a/boards/qemu/x86/qemu_x86.yaml +++ b/boards/qemu/x86/qemu_x86.yaml @@ -1,7 +1,8 @@ identifier: qemu_x86 name: QEMU Emulation for X86 type: qemu -simulation: qemu +simulation: + - name: qemu arch: x86 ram: 3000 toolchain: diff --git a/boards/qemu/x86/qemu_x86_64.dts b/boards/qemu/x86/qemu_x86_64.dts index fc252104773..64d33dca69a 100644 --- a/boards/qemu/x86/qemu_x86_64.dts +++ b/boards/qemu/x86/qemu_x86_64.dts @@ -9,7 +9,7 @@ cpus { cpu@1 { device_type = "cpu"; - compatible = "intel,x86"; + compatible = "intel,x86_64"; d-cache-line-size = <64>; reg = <1>; }; @@ -29,3 +29,7 @@ status = "okay"; }; }; + +&cpu { + compatible = "intel,x86_64"; +}; diff --git a/boards/qemu/x86/qemu_x86_64.yaml b/boards/qemu/x86/qemu_x86_64.yaml index b5c77de4c0e..5811211385b 100644 --- a/boards/qemu/x86/qemu_x86_64.yaml +++ b/boards/qemu/x86/qemu_x86_64.yaml @@ -5,7 +5,8 @@ arch: x86 toolchain: - zephyr - xtools -simulation: qemu +simulation: + - name: qemu supported: - acpi - can diff --git a/boards/qemu/x86/qemu_x86_64_atom_nokpti.dts b/boards/qemu/x86/qemu_x86_64_atom_nokpti.dts index 8a5f2d51154..692f9f1e880 100644 --- a/boards/qemu/x86/qemu_x86_64_atom_nokpti.dts +++ b/boards/qemu/x86/qemu_x86_64_atom_nokpti.dts @@ -9,9 +9,13 @@ cpus { cpu@1 { device_type = "cpu"; - compatible = "intel,x86"; + compatible = "intel,x86_64"; d-cache-line-size = <64>; reg = <1>; }; }; }; + +&cpu { + compatible = "intel,x86_64"; +}; diff --git a/boards/qemu/x86/qemu_x86_64_atom_nokpti.yaml b/boards/qemu/x86/qemu_x86_64_atom_nokpti.yaml index 22033bdc24d..943ee9ae0b6 100644 --- a/boards/qemu/x86/qemu_x86_64_atom_nokpti.yaml +++ b/boards/qemu/x86/qemu_x86_64_atom_nokpti.yaml @@ -7,7 +7,8 @@ toolchain: - xtools supported: - smp -simulation: qemu +simulation: + - name: qemu testing: default: true only_tags: diff --git a/boards/qemu/x86/qemu_x86_atom_nokpti.yaml b/boards/qemu/x86/qemu_x86_atom_nokpti.yaml index 54b8d1857d9..9620cfc0724 100644 --- a/boards/qemu/x86/qemu_x86_atom_nokpti.yaml +++ b/boards/qemu/x86/qemu_x86_atom_nokpti.yaml @@ -2,7 +2,8 @@ identifier: qemu_x86/atom/nokpti name: QEMU Emulation for X86 (KPTI disabled) type: qemu arch: x86 -simulation: qemu +simulation: + - name: qemu toolchain: - zephyr - xtools diff --git a/boards/qemu/x86/qemu_x86_atom_nommu.yaml b/boards/qemu/x86/qemu_x86_atom_nommu.yaml index 1076c2f3f87..e8fac2e2f57 100644 --- a/boards/qemu/x86/qemu_x86_atom_nommu.yaml +++ b/boards/qemu/x86/qemu_x86_atom_nommu.yaml @@ -2,7 +2,8 @@ identifier: qemu_x86/atom/nommu name: QEMU Emulation for X86 (MMU disabled) type: qemu arch: x86 -simulation: qemu +simulation: + - name: qemu toolchain: - zephyr - xtools diff --git a/boards/qemu/x86/qemu_x86_atom_nopae.yaml b/boards/qemu/x86/qemu_x86_atom_nopae.yaml index 2d3b46acc3f..5809fec52fa 100644 --- a/boards/qemu/x86/qemu_x86_atom_nopae.yaml +++ b/boards/qemu/x86/qemu_x86_atom_nopae.yaml @@ -2,7 +2,8 @@ identifier: qemu_x86/atom/nopae name: QEMU Emulation for X86 (32-bit page tables) type: qemu arch: x86 -simulation: qemu +simulation: + - name: qemu toolchain: - zephyr - xtools diff --git a/boards/qemu/x86/qemu_x86_atom_virt.yaml b/boards/qemu/x86/qemu_x86_atom_virt.yaml index ac656ad922d..782a28ac688 100644 --- a/boards/qemu/x86/qemu_x86_atom_virt.yaml +++ b/boards/qemu/x86/qemu_x86_atom_virt.yaml @@ -2,7 +2,8 @@ identifier: qemu_x86/atom/virt name: QEMU Emulation for X86 (Run in Virtual Address Space) type: qemu arch: x86 -simulation: qemu +simulation: + - name: qemu toolchain: - zephyr - xtools diff --git a/boards/qemu/x86/qemu_x86_atom_xip.yaml b/boards/qemu/x86/qemu_x86_atom_xip.yaml index f55d0b2097a..ec2cfb9104e 100644 --- a/boards/qemu/x86/qemu_x86_atom_xip.yaml +++ b/boards/qemu/x86/qemu_x86_atom_xip.yaml @@ -2,7 +2,8 @@ identifier: qemu_x86/atom/xip name: QEMU Emulation for X86 (XIP enabled) type: qemu arch: x86 -simulation: qemu +simulation: + - name: qemu toolchain: - zephyr - xtools diff --git a/boards/qemu/x86/qemu_x86_lakemont.dts b/boards/qemu/x86/qemu_x86_lakemont.dts index 87056f9cf65..b0793772631 100644 --- a/boards/qemu/x86/qemu_x86_lakemont.dts +++ b/boards/qemu/x86/qemu_x86_lakemont.dts @@ -31,9 +31,9 @@ zephyr,shell-uart = &uart0; }; - dram0: memory@0 { + dram0: memory@DT_DRAM_BASE { device_type = "memory"; - reg = ; + reg = ; }; soc { diff --git a/boards/qemu/x86/qemu_x86_lakemont.yaml b/boards/qemu/x86/qemu_x86_lakemont.yaml index 1f1d7bb83c9..7f153643b9e 100644 --- a/boards/qemu/x86/qemu_x86_lakemont.yaml +++ b/boards/qemu/x86/qemu_x86_lakemont.yaml @@ -1,7 +1,8 @@ identifier: qemu_x86_lakemont name: QEMU Emulation for X86 (Lakemont) type: qemu -simulation: qemu +simulation: + - name: qemu arch: x86 toolchain: - zephyr diff --git a/boards/qemu/x86/qemu_x86_tiny.dts b/boards/qemu/x86/qemu_x86_tiny.dts index 9ce52b60d88..54d30c2188c 100644 --- a/boards/qemu/x86/qemu_x86_tiny.dts +++ b/boards/qemu/x86/qemu_x86_tiny.dts @@ -4,6 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -#define DT_DRAM_BASE 0x100000 +/* Note: this is the unit-address (in hex) of the node */ +#define DT_DRAM_BASE 100000 #define DT_DRAM_SIZE DT_SIZE_K(256) #include "qemu_x86.dts" diff --git a/boards/qemu/x86/qemu_x86_tiny.ld b/boards/qemu/x86/qemu_x86_tiny.ld index 548e5fbdcb0..607b096e9d7 100644 --- a/boards/qemu/x86/qemu_x86_tiny.ld +++ b/boards/qemu/x86/qemu_x86_tiny.ld @@ -144,10 +144,10 @@ MEMORY #endif /* CONFIG_NEWLIB_LIBC */ #ifdef CONFIG_PICOLIBC -/* For Picolibc libc-hook.c. */ +/* For Picolibc, all files under lib/libc/picolibc */ #define LIB_C_IN_SECT(lsect) \ - *liblib__libc__picolibc.a:libc-hooks.c.obj(.##lsect) \ - *liblib__libc__picolibc.a:libc-hooks.c.obj(.##lsect##.*) + *liblib__libc__picolibc.a:(.##lsect) \ + *liblib__libc__picolibc.a:(.##lsect##.*) #endif /* CONFIG_PICOLIBC */ diff --git a/boards/qemu/x86/qemu_x86_tiny.yaml b/boards/qemu/x86/qemu_x86_tiny.yaml index 8807d57d8d0..c09f5b51379 100644 --- a/boards/qemu/x86/qemu_x86_tiny.yaml +++ b/boards/qemu/x86/qemu_x86_tiny.yaml @@ -2,7 +2,8 @@ identifier: qemu_x86_tiny name: QEMU Emulation for X86 (small VM) type: qemu arch: x86 -simulation: qemu +simulation: + - name: qemu toolchain: - zephyr - xtools diff --git a/boards/qemu/xtensa/Kconfig b/boards/qemu/xtensa/Kconfig index 8cdc6ec28ff..9ec79f85c1e 100644 --- a/boards/qemu/xtensa/Kconfig +++ b/boards/qemu/xtensa/Kconfig @@ -7,3 +7,4 @@ config BOARD_QEMU_XTENSA select QEMU_TARGET select ARCH_SUPPORTS_COREDUMP select XTENSA_MMU if BOARD_QEMU_XTENSA_DC233C_MMU + select XTENSA_MPU if BOARD_QEMU_XTENSA_SAMPLE_CONTROLLER32_MPU diff --git a/boards/qemu/xtensa/Kconfig.defconfig b/boards/qemu/xtensa/Kconfig.defconfig index 081971b5e81..c94da322385 100644 --- a/boards/qemu/xtensa/Kconfig.defconfig +++ b/boards/qemu/xtensa/Kconfig.defconfig @@ -9,4 +9,8 @@ config BUILD_OUTPUT_BIN config IPM_CONSOLE_STACK_SIZE default 2048 if IPM_CONSOLE_RECEIVER +# Must match XCHAL_DCACHE_LINESIZE form core-isa.h +config DCACHE_LINE_SIZE + default 32 + endif # BOARD_QEMU_XTENSA diff --git a/boards/qemu/xtensa/Kconfig.qemu_xtensa b/boards/qemu/xtensa/Kconfig.qemu_xtensa index f0aa1c8010c..6d1a9f9ce97 100644 --- a/boards/qemu/xtensa/Kconfig.qemu_xtensa +++ b/boards/qemu/xtensa/Kconfig.qemu_xtensa @@ -4,4 +4,5 @@ # SPDX-License-Identifier: Apache-2.0 config BOARD_QEMU_XTENSA - select SOC_XTENSA_DC233C + select SOC_XTENSA_SAMPLE_CONTROLLER32 if BOARD_QEMU_XTENSA_SAMPLE_CONTROLLER32_MPU + select SOC_XTENSA_DC233C if !BOARD_QEMU_XTENSA_SAMPLE_CONTROLLER32_MPU diff --git a/boards/qemu/xtensa/board.cmake b/boards/qemu/xtensa/board.cmake index 40818845da6..a11c7e8c158 100644 --- a/boards/qemu/xtensa/board.cmake +++ b/boards/qemu/xtensa/board.cmake @@ -3,10 +3,10 @@ set(SUPPORTED_EMU_PLATFORMS qemu) if(CONFIG_BOARD_QEMU_XTENSA) - set(QEMU_CPU_TYPE_${ARCH} dc233c) + set(QEMU_CPU_TYPE_${ARCH} ${CONFIG_SOC}) set(QEMU_FLAGS_${ARCH} - -machine sim -semihosting -nographic -cpu dc233c + -machine sim -semihosting -nographic -cpu ${CONFIG_SOC} ) endif() diff --git a/boards/qemu/xtensa/board.yml b/boards/qemu/xtensa/board.yml index 116a53db80b..285fab05121 100644 --- a/boards/qemu/xtensa/board.yml +++ b/boards/qemu/xtensa/board.yml @@ -6,3 +6,6 @@ board: - name: dc233c variants: - name: mmu + - name: sample_controller32 + variants: + - name: mpu diff --git a/boards/qemu/xtensa/doc/index.rst b/boards/qemu/xtensa/doc/index.rst index 1bc8b2b2ace..741e0569b7f 100644 --- a/boards/qemu/xtensa/doc/index.rst +++ b/boards/qemu/xtensa/doc/index.rst @@ -1,7 +1,4 @@ -.. _qemu_xtensa: - -Xtensa Emulation (QEMU) -####################### +.. zephyr:board:: qemu_xtensa Overview ******** @@ -18,7 +15,7 @@ emulated environment, for example, with the :zephyr:code-sample:`synchronization .. zephyr-app-commands:: :zephyr-app: samples/synchronization :host-os: unix - :board: qemu_xtensa + :board: qemu_xtensa/dc233c :goals: run This will build an image with the synchronization sample app, boot it using diff --git a/boards/qemu/xtensa/qemu_xtensa.yaml b/boards/qemu/xtensa/qemu_xtensa.yaml deleted file mode 100644 index 1190d0d3f8e..00000000000 --- a/boards/qemu/xtensa/qemu_xtensa.yaml +++ /dev/null @@ -1,14 +0,0 @@ -identifier: qemu_xtensa -name: QEMU Emulation for Xtensa -type: qemu -simulation: qemu -arch: xtensa -toolchain: - - zephyr - - xtools -testing: - default: true - ignore_tags: - - net - - bluetooth -vendor: cdns diff --git a/boards/qemu/xtensa/qemu_xtensa.dts b/boards/qemu/xtensa/qemu_xtensa_dc233c.dts similarity index 100% rename from boards/qemu/xtensa/qemu_xtensa.dts rename to boards/qemu/xtensa/qemu_xtensa_dc233c.dts diff --git a/boards/qemu/xtensa/qemu_xtensa_dc233c.yaml b/boards/qemu/xtensa/qemu_xtensa_dc233c.yaml new file mode 100644 index 00000000000..c0fd17ab84c --- /dev/null +++ b/boards/qemu/xtensa/qemu_xtensa_dc233c.yaml @@ -0,0 +1,15 @@ +identifier: qemu_xtensa/dc233c +name: QEMU Emulation for Xtensa +type: qemu +simulation: + - name: qemu +arch: xtensa +toolchain: + - zephyr + - xtools +testing: + default: true + ignore_tags: + - net + - bluetooth +vendor: cdns diff --git a/boards/qemu/xtensa/qemu_xtensa_defconfig b/boards/qemu/xtensa/qemu_xtensa_dc233c_defconfig similarity index 100% rename from boards/qemu/xtensa/qemu_xtensa_defconfig rename to boards/qemu/xtensa/qemu_xtensa_dc233c_defconfig diff --git a/boards/qemu/xtensa/qemu_xtensa_dc233c_mmu.yaml b/boards/qemu/xtensa/qemu_xtensa_dc233c_mmu.yaml index 61ab14c9130..b9bbbd89698 100644 --- a/boards/qemu/xtensa/qemu_xtensa_dc233c_mmu.yaml +++ b/boards/qemu/xtensa/qemu_xtensa_dc233c_mmu.yaml @@ -1,7 +1,8 @@ identifier: qemu_xtensa/dc233c/mmu name: QEMU Emulation for Xtensa with MMU type: qemu -simulation: qemu +simulation: + - name: qemu arch: xtensa toolchain: - zephyr diff --git a/boards/qemu/xtensa/qemu_xtensa_sample_controller32_mpu.dts b/boards/qemu/xtensa/qemu_xtensa_sample_controller32_mpu.dts new file mode 100644 index 00000000000..4fba5a197f0 --- /dev/null +++ b/boards/qemu/xtensa/qemu_xtensa_sample_controller32_mpu.dts @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2019, 2023 Intel Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include "sample_controller32.dtsi" + +/ { + model = "qemu_xtensa_mpu"; + compatible = "cdns,xtensa-sample-controller32"; + + chosen { + zephyr,sram = &sram0; + }; +}; + +&cpu0 { + clock-frequency = <10000000>; +}; diff --git a/boards/qemu/xtensa/qemu_xtensa_sample_controller32_mpu.yaml b/boards/qemu/xtensa/qemu_xtensa_sample_controller32_mpu.yaml new file mode 100644 index 00000000000..9285fa04e9e --- /dev/null +++ b/boards/qemu/xtensa/qemu_xtensa_sample_controller32_mpu.yaml @@ -0,0 +1,11 @@ +identifier: qemu_xtensa/sample_controller32/mpu +name: QEMU Emulation for Xtensa with MPU +type: qemu +simulation: + - name: qemu +arch: xtensa +testing: + default: true + ignore_tags: + - net + - bluetooth diff --git a/boards/qemu/xtensa/qemu_xtensa_sample_controller32_mpu_defconfig b/boards/qemu/xtensa/qemu_xtensa_sample_controller32_mpu_defconfig new file mode 100644 index 00000000000..8e34107fe3d --- /dev/null +++ b/boards/qemu/xtensa/qemu_xtensa_sample_controller32_mpu_defconfig @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 +CONFIG_CONSOLE=y +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=10000000 +CONFIG_STACK_SENTINEL=y +CONFIG_GEN_ISR_TABLES=y +CONFIG_GEN_IRQ_VECTOR_TABLE=n +CONFIG_SIMULATOR_XTENSA=y +CONFIG_QEMU_ICOUNT_SHIFT=6 +CONFIG_PRIVILEGED_STACK_SIZE=4096 diff --git a/boards/qorvo/decawave_dwm1001_dev/Kconfig.defconfig b/boards/qorvo/decawave_dwm1001_dev/Kconfig.defconfig index cd2a985b1eb..e29eec91cb3 100644 --- a/boards/qorvo/decawave_dwm1001_dev/Kconfig.defconfig +++ b/boards/qorvo/decawave_dwm1001_dev/Kconfig.defconfig @@ -5,9 +5,6 @@ if BOARD_DECAWAVE_DWM1001_DEV -config BT_CTLR - default BT - config I2C default SENSOR diff --git a/boards/qorvo/decawave_dwm1001_dev/doc/index.rst b/boards/qorvo/decawave_dwm1001_dev/doc/index.rst index 93966edb739..491851f3075 100644 --- a/boards/qorvo/decawave_dwm1001_dev/doc/index.rst +++ b/boards/qorvo/decawave_dwm1001_dev/doc/index.rst @@ -1,7 +1,4 @@ -.. _decawave_dwm1001_dev: - -Decawave DWM1001 -################# +.. zephyr:board:: decawave_dwm1001_dev Overview ******** diff --git a/boards/qorvo/decawave_dwm3001cdk/Kconfig.decawave_dwm3001cdk b/boards/qorvo/decawave_dwm3001cdk/Kconfig.decawave_dwm3001cdk new file mode 100644 index 00000000000..b731a794bef --- /dev/null +++ b/boards/qorvo/decawave_dwm3001cdk/Kconfig.decawave_dwm3001cdk @@ -0,0 +1,7 @@ +# DecaWave DWM3001CDK board configuration + +# Copyright (c) 2019 Stéphane D'Alu +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_DECAWAVE_DWM3001CDK + select SOC_NRF52833_QDAA diff --git a/boards/qorvo/decawave_dwm3001cdk/Kconfig.defconfig b/boards/qorvo/decawave_dwm3001cdk/Kconfig.defconfig new file mode 100644 index 00000000000..c814a6c8994 --- /dev/null +++ b/boards/qorvo/decawave_dwm3001cdk/Kconfig.defconfig @@ -0,0 +1,11 @@ +# DecaWave DWM3001CDK board configuration + +# Copyright (c) 2019 Stéphane D'Alu +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_DECAWAVE_DWM3001CDK + +config I2C + default SENSOR + +endif # BOARD_DECAWAVE_DWM3001CDK diff --git a/boards/qorvo/decawave_dwm3001cdk/board.cmake b/boards/qorvo/decawave_dwm3001cdk/board.cmake new file mode 100644 index 00000000000..f8c71dc5694 --- /dev/null +++ b/boards/qorvo/decawave_dwm3001cdk/board.cmake @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=nRF52833_xxAA" "--speed=4000") +board_runner_args(pyocd "--target=nrf52833" "--frequency=4000000") +include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) +include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd-nrf5.board.cmake) diff --git a/boards/qorvo/decawave_dwm3001cdk/board.yml b/boards/qorvo/decawave_dwm3001cdk/board.yml new file mode 100644 index 00000000000..e62aeef1789 --- /dev/null +++ b/boards/qorvo/decawave_dwm3001cdk/board.yml @@ -0,0 +1,5 @@ +board: + name: decawave_dwm3001cdk + vendor: qorvo + socs: + - name: nrf52833 diff --git a/boards/qorvo/decawave_dwm3001cdk/decawave_dwm3001cdk-pinctrl.dtsi b/boards/qorvo/decawave_dwm3001cdk/decawave_dwm3001cdk-pinctrl.dtsi new file mode 100644 index 00000000000..b68c634870a --- /dev/null +++ b/boards/qorvo/decawave_dwm3001cdk/decawave_dwm3001cdk-pinctrl.dtsi @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2022 Nordic Semiconductor + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + uart0_default: uart0_default { + group1 { + psels = , + ; + }; + }; + + uart0_sleep: uart0_sleep { + group1 { + psels = , + ; + low-power-enable; + }; + }; + + i2c0_default: i2c0_default { + group1 { + psels = , + ; + bias-pull-up; + }; + }; + + i2c0_sleep: i2c0_sleep { + group1 { + psels = , + ; + low-power-enable; + }; + }; + + spi3_default: spi3_default { + group1 { + psels = , + , + ; + }; + }; + + spi3_sleep: spi3_sleep { + group1 { + psels = , + , + ; + low-power-enable; + }; + }; +}; diff --git a/boards/qorvo/decawave_dwm3001cdk/decawave_dwm3001cdk.dts b/boards/qorvo/decawave_dwm3001cdk/decawave_dwm3001cdk.dts new file mode 100644 index 00000000000..88f85efbde5 --- /dev/null +++ b/boards/qorvo/decawave_dwm3001cdk/decawave_dwm3001cdk.dts @@ -0,0 +1,165 @@ +/* + * Copyright (c) 2019 Stéphane D'Alu + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "decawave_dwm3001cdk-pinctrl.dtsi" +#include + +/ { + model = "Decawave DWM3001CDK"; + compatible = "decawave,dwm3001"; + + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,uart-mcumgr = &uart0; + zephyr,bt-mon-uart = &uart0; + zephyr,bt-c2h-uart = &uart0; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + zephyr,ieee802154 = &ieee802154; + }; + + leds { + compatible = "gpio-leds"; + // led from top of board down + // D20: something related to jlink, red + // D13: DW3000 tx(red)/rx(green) + led0: led_0 { + gpios = <&gpio0 04 GPIO_ACTIVE_LOW>; + label = "D9 green LED"; + }; + led1: led_1 { + gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; + label = "D12 red LED"; + }; + led2: led_2 { + gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; + label = "D11 red LED"; + }; + led3: led_3 { + gpios = <&gpio0 05 GPIO_ACTIVE_LOW>; + label = "D10 blue LED"; + }; + }; + + buttons { + compatible = "gpio-keys"; + // SW1 is connected to P0.18, which by default is nRESET and + // will reset the board + button2: button_2 { + gpios = <&gpio0 2 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button switch 2"; + zephyr,code = ; + }; + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + sw0 = &button2; + led0 = &led0; + led1 = &led1; + led2 = &led2; + led3 = &led3; + watchdog0 = &wdt0; + accel0 = &lis2dh12; + }; + +}; + +&uicr { + gpio-as-nreset; +}; + +&gpiote { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&uart0 { + status = "okay"; + compatible = "nordic,nrf-uart"; + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-1 = <&uart0_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&gpio1 { + status = "okay"; +}; + +&i2c0 { + compatible = "nordic,nrf-twim"; + status = "okay"; + clock-frequency = ; + + pinctrl-0 = <&i2c0_default>; + pinctrl-1 = <&i2c0_sleep>; + pinctrl-names = "default", "sleep"; + lis2dh12: lis2dh12@19 { + compatible = "st,lis2dh12", "st,lis2dh"; + reg = <0x19>; + irq-gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; + }; +}; + +&spi3 { + compatible = "nordic,nrf-spim"; + status = "okay"; + cs-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&spi3_default>; + pinctrl-1 = <&spi3_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&ieee802154 { + status = "okay"; +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 0xC000>; + }; + slot0_partition: partition@c000 { + label = "image-0"; + reg = <0x0000C000 0x38000>; + }; + slot1_partition: partition@44000 { + label = "image-1"; + reg = <0x00044000 0x36000>; + }; + storage_partition: partition@7a000 { + label = "storage"; + reg = <0x0007A000 0x00006000>; + }; + }; +}; + +zephyr_udc0: &usbd { + compatible = "nordic,nrf-usbd"; + status = "okay"; +}; + +®1 { + regulator-initial-mode = ; +}; + +&adc { + status = "okay"; +}; diff --git a/boards/qorvo/decawave_dwm3001cdk/decawave_dwm3001cdk.yaml b/boards/qorvo/decawave_dwm3001cdk/decawave_dwm3001cdk.yaml new file mode 100644 index 00000000000..50fdad0ba87 --- /dev/null +++ b/boards/qorvo/decawave_dwm3001cdk/decawave_dwm3001cdk.yaml @@ -0,0 +1,20 @@ +identifier: decawave_dwm3001cdk +name: Decawave-DWM3001CDK +type: mcu +arch: arm +ram: 128 +flash: 512 +vendor: decawave +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - adc + - usb_device + - ble + - gpio + - pwm + - watchdog + - counter + - netif:openthread diff --git a/boards/qorvo/decawave_dwm3001cdk/decawave_dwm3001cdk_defconfig b/boards/qorvo/decawave_dwm3001cdk/decawave_dwm3001cdk_defconfig new file mode 100644 index 00000000000..7b06dae9085 --- /dev/null +++ b/boards/qorvo/decawave_dwm3001cdk/decawave_dwm3001cdk_defconfig @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART controller +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/qorvo/decawave_dwm3001cdk/doc/index.rst b/boards/qorvo/decawave_dwm3001cdk/doc/index.rst new file mode 100644 index 00000000000..ada232518fe --- /dev/null +++ b/boards/qorvo/decawave_dwm3001cdk/doc/index.rst @@ -0,0 +1,59 @@ +.. _decawave_dwm3001cdk: + +Decawave DWM3001CDK +################### + +Overview +******** + +The DWM3001CDK development board includes the DWM3001C module, battery connector +and charging circuit, LEDs, buttons, Raspberry Pi connector, and USB connector. +In addition, the board comes with J-Link OB adding debugging and Virtual COM +Port capabilities. + +See `Qorvo (Decawave) DWM3001CDK website`_ for more information about the +development board, `Qorvo (Decawave) DWM3001C website`_ about the module +itself, and `nRF52833 website`_ for the official reference on the IC itself. + +Programming and Debugging +************************* + +Applications for the ``decawave_dwm3001cdk`` board target can be built, flashed, +and debugged in the usual way. See :ref:`build_an_application` and +:ref:`application_run` for more details on building and running. + +Flashing +======== + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. Then build and flash +applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +Connect to the bottom micro-USB port labeled as J-Link and run your favorite +terminal program to listen for console output. + +.. code-block:: console + + $ minicom -D -b 115200 + +Replace :code:`` with the port where the DWM3001CDK board can be +found. For example, under Linux, :code:`/dev/ttyACM0`. + +Then build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: decawave_dwm3001cdk + :goals: build flash + +References +********** +.. target-notes:: + +.. _nRF52833 website: https://www.nordicsemi.com/products/nrf52833 +.. _Qorvo (Decawave) DWM3001C website: https://www.qorvo.com/products/p/DWM3001C +.. _Qorvo (Decawave) DWM3001CDK website: https://www.qorvo.com/products/p/DWM3001CDK diff --git a/boards/rak/rak5010/pre_dt_board.cmake b/boards/qorvo/decawave_dwm3001cdk/pre_dt_board.cmake similarity index 100% rename from boards/rak/rak5010/pre_dt_board.cmake rename to boards/qorvo/decawave_dwm3001cdk/pre_dt_board.cmake diff --git a/boards/quicklogic/qomu/doc/index.rst b/boards/quicklogic/qomu/doc/index.rst index 57505aebe91..7406e9896b5 100644 --- a/boards/quicklogic/qomu/doc/index.rst +++ b/boards/quicklogic/qomu/doc/index.rst @@ -1,20 +1,10 @@ -.. _qomu: - -Qomu -#### +.. zephyr:board:: qomu Overview ******** The Qomu board is a platform with an on-board QuickLogic EOS S3 Sensor Processing Platform. - -.. figure:: img/qomu-board.png - :align: center - :alt: Qomu - - Qomu (Credit: QuickLogic) - Hardware ******** diff --git a/boards/quicklogic/quick_feather/doc/index.rst b/boards/quicklogic/quick_feather/doc/index.rst index d5bf1e7026d..11394643956 100644 --- a/boards/quicklogic/quick_feather/doc/index.rst +++ b/boards/quicklogic/quick_feather/doc/index.rst @@ -1,7 +1,4 @@ -.. _quickfeather: - -QuickFeather -############ +.. zephyr:board:: quick_feather Overview ******** @@ -9,13 +6,6 @@ Overview The QuickFeather development board is a platform with an on-board QuickLogic EOS S3 Sensor Processing Platform. - -.. figure:: img/feather-board.jpg - :align: center - :alt: QuickFeather - - QuickFeather (Credit: QuickLogic) - Hardware ******** diff --git a/boards/rak/rak11720/doc/index.rst b/boards/rak/rak11720/doc/index.rst deleted file mode 100644 index 238ba6d8303..00000000000 --- a/boards/rak/rak11720/doc/index.rst +++ /dev/null @@ -1,122 +0,0 @@ -.. _rak11720: - -RAK11720 -######## - -The RAK11720 is a WisBlock Core module for RAK WisBlock. -It is based on the powerful ultra-low power Apollo3 Blue SoC (AMA3B1KK-KBR-B0) -from Ambiq together with a Semtech SX1262 LoRa® transceiver. - -The AMA3B1KK-KBR-B0 has an integrated Bluetooth Low Energy transceiver -that enhances the communication capabilities. The RAK11720 stamp module -comes in the same size and footprint as our RAK3172 module which gives -you the opportunity to enhance your existing designs -with BLE without designing a new PCB. - -.. image:: img/rak11720.webp - :align: center - :alt: RAK11720 - -Hardware -******** - -The easiset way to use a RAK11720, is the WisBlock Modular system. -A WisBlock Base board (RAK19007) which provides the power -supply and programming/debug interface is the base to plug a -RAK11722 (WisBlock Core module with the RAK11720) in. - -- Apollo3 Blue SoC with up to 96 MHz operating frequency -- ARM® Cortex® M4F core -- 16 kB 2-way Associative/Direct-Mapped Cache per core -- Up to 1 MB of flash memory for code/data -- Up to 384 KB of low leakage / low power RAM for code/data -- Integrated Bluetooth 5 Low-energy controller -- Semtech SX1262 low power high range LoRa transceiver -- iPEX connectors for the LORA antenna and BLE antenna. -- 2 user LEDs on RAK19007 WisBlock Base board -- Powered by either Micro USB, 3.7V rechargeable battery or a 5V Solar Panel Port - -For more information about the RAK11720 stamp module: - -- `WisDuo RAK11720 Website`_ -- `WisBlock RAK11722 Website`_ - -Supported Features -================== - -The RAK11720 module configuration supports the following hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+----------------------+ -| STIMER | on-chip | stimer | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ -| RADIO | on-chip | bluetooth | -+-----------+------------+----------------------+ -| RADIO | on-board | LoRa (SX1262) | -+-----------+------------+----------------------+ - -The default configuration can be found in the defconfig file: -``boards/rak/rak11720/rak11720_defconfig``. - -Programming and Debugging -========================= - -The RAK11720 board shall be connected to a Segger Embedded Debugger Unit -`J-Link OB `_. This provides a debug -interface to the Apollo3 Blue chip. You can use JLink to communicate with -the Apollo3 Blue. - -Flashing an application ------------------------ - -Connect your device to your host computer using the JLINK USB port. -The sample application :zephyr:code-sample:`hello_world` is used for this example. -Build the Zephyr kernel and application, then flash it to the device: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: rak11720 - :goals: flash - -.. note:: - ``west flash`` requires `SEGGER J-Link software`_ and `pylink`_ Python module - to be installed on you host computer. - -Open a serial terminal (minicom, putty, etc.) with the following settings: - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Reset the board and you should be able to see on the corresponding Serial Port -the following message: - -.. code-block:: console - - Hello World! rak11720/apollo3_blue - -.. _WisDuo RAK11720 Website: - https://docs.rakwireless.com/Product-Categories/WisDuo/RAK11720-Module/Overview/#product-description - -.. _WisBlock RAK11722 Website: - https://docs.rakwireless.com/Product-Categories/WisBlock/RAK11722/Overview/#product-description - -.. _SEGGER J-Link software: - https://www.segger.com/downloads/jlink - -.. _pylink: - https://github.com/Square/pylink diff --git a/boards/rak/rak4631/Kconfig.defconfig b/boards/rak/rak4631/Kconfig.defconfig deleted file mode 100644 index bf7cf003b29..00000000000 --- a/boards/rak/rak4631/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# RAKWIRELESS RAK4631 Board configuration - -# Copyright (c) 2021 Guillaume Paquet -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_RAK4631 - -config BT_CTLR - default BT - -endif # BOARD_RAK4631 diff --git a/boards/rak/rak4631/doc/index.rst b/boards/rak/rak4631/doc/index.rst deleted file mode 100644 index 14c6c912976..00000000000 --- a/boards/rak/rak4631/doc/index.rst +++ /dev/null @@ -1,154 +0,0 @@ -.. _rak4631_nrf52840: - -RAK4631 -####### - -Overview -******** - -RAK4631 is a WisBlock Core module for RAK WisBlock. -It extends the WisBlock series with a powerful -Nordic nRF52840 MCU that supports Bluetooth 5.0 -(Bluetooth Low Energy) and the newest LoRa transceiver -from Semtech, the SX1262. The Semtech SX1262 has compared -to the older SX127x series a lower power consumption at -the same TX power. This makes the RAK4631 an ultra-low -power communication solution. RAK4631 can be comfortably -programmed with ZephyrRTOS. - -.. image:: img/rak4631-front-parts.jpg - :align: center - :alt: RAK4631-NRF52840 - -Hardware -******** - -To use a RAK4631, you need at least a WisBlock Base -to plug the module in. WisBlock Base is the power -supply for the RAK4631 module and has the -programming/debug interface. - -- nRF52840 ARM Cortex-M4F Processor -- 64 MHz CPU clock -- 1 Micro-AB USB OTG host/device -- Semtech SX1262 low power high range LoRa transceiver -- iPEX connectors for the LORA antenna and BLE antenna. -- Multiple interfaces, I2C, UART, GPIO, ADC -- 2 user LEDs on RAK5005 mother Board -- Powered by either Micro USB, 3.7V rechargeable battery or a 5V Solar Panel Port - -Supported Features -================== - -The ``rak4631/nrf52840`` board configuration supports the following hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth, | -| | | ieee802154 | -+-----------+------------+----------------------+ -| RADIO | on-board | LoRa (SX1262) | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| USB | on-chip | usb | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -The default board configuration can be found in -:zephyr_file:`boards/rak/rak4631/rak4631_nrf52840_defconfig` - -Connections and IOs -=================== - -LED ---- - -* LED1 (green) = P1.3 -* LED2 (blue) = P1.4 - -Programming and Debugging -************************* - -The RAK4631 board shall be connected to a Segger Embedded Debugger Unit -`J-Link OB `_. This provides a debug -interface to the NRF52840 chip. You can use JLink to communicate with -the NRF52840. - -Flashing -======== - -#. Download JLink from the Segger `JLink Downloads Page`_. Go to the section - "J-Link Software and Documentation Pack" and install the "J-Link Software - and Documentation pack for Linux". The application JLinkExe needs to be - accessible from your path. - -#. Run your favorite terminal program to listen for output. Under Linux the - terminal should be :code:`/dev/ttyACM0`. For example: - - .. code-block:: console - - $ minicom -D /dev/ttyACM0 -o - - The -o option tells minicom not to send the modem initialization string. - Connection should be configured as follows: - - - Speed: 115200 - - Data: 8 bits - - Parity: None - - Stop bits: 1 - -#. Connect the RAK4631 board to your host computer using the USB debug port. - Then build and flash the :zephyr:code-sample:`hello_world` application. - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: rak4631/nrf52840 - :goals: build flash - - You should see "Hello World! rak4631_nrf52840" in your terminal. - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:zephyr:code-sample:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: rak4631/nrf52840 - :maybe-skip-config: - :goals: debug - -References -********** - -.. target-notes:: - -.. _RAK4631 Product Description: - https://docs.rakwireless.com/Product-Categories/WisBlock/RAK4631/Datasheet/#overview - -.. _JLink Downloads Page: - https://www.segger.com/downloads/jlink diff --git a/boards/rak/rak5010/Kconfig.defconfig b/boards/rak/rak5010/Kconfig.defconfig deleted file mode 100644 index 302f7fecd07..00000000000 --- a/boards/rak/rak5010/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# RAKWIRELESS RAK5010 Board configuration - -# Copyright (c) 2020 Guillaume Paquet -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_RAK5010 - -config BT_CTLR - default BT - -endif # BOARD_RAK5010 diff --git a/boards/rak/rak5010/doc/index.rst b/boards/rak/rak5010/doc/index.rst deleted file mode 100644 index 851d8924842..00000000000 --- a/boards/rak/rak5010/doc/index.rst +++ /dev/null @@ -1,159 +0,0 @@ -.. _rak5010_nrf52840: - -RAK5010 -####### - -Overview -******** - -WisTrio NB-IoT Tracker Pro (RAK5010) is a tracker -with integrated LTE CAT M1 & NB1, GPS, BLE, and sensors. -It is built on the Quectel BG96 LTE CAT M1 & NB1 module, -which has an integrated GPS receiver. The MCU running -the board is a Nordic nRF52840 controller. - -As it has both GPS and BLE it can be used for outdoor -and indoor scenarios, where location-based services need be present. - -The built-in sensors for RAK5010 are temperature and -humidity sensor, motion sensor, pressure sensor, and light sensor. -The extension IOs allow adding more sensors in addition to the on-board ones. - -This board is particularly suitable to be used as a -quick testing and prototyping tool for applications -requiring NB-IoT connectivity. Application development -supports the GCC environment. - -.. image:: img/rak5010-front-parts.jpg - :align: center - :alt: RAK5010-NRF52840 - -Hardware -******** - -- nRF52840 ARM Cortex-M4F Processor -- 32.768 kHz crystal oscillator -- 1 Micro-AB USB OTG host/device -- Quectel BG96, with LTE CAT M1, LTE NB1, and GNSS -- iPEX connectors for the LTE and GPS antenna and an on-board ceramic antenna for the BLE. -- nano-SIM and ESIM options. -- Multiple interfaces, I2C, UART, GPIO, ADC -- 1 user LED -- 1 SHTC3 Humidity and Temperature Sensor -- 1 OPT3001DNPR Ambient Light Sensor -- 1 LPS22HB Pressure Sensor -- 1 LIS3DH Motion Sensor -- Powered by either Micro USB, 3.7V rechargeable battery or a 5V Solar Panel Port - -Supported Features -================== - -The ``rak5010/nrf52840`` board configuration supports the following hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth, | -| | | ieee802154 | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| USB | on-chip | usb | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Other hardware features have not been enabled yet for this board. - -Connections and IOs -=================== - -LED ---- - -* LED0 (green) = P0.12 - - -Programming and Debugging -************************* - -The RAK5010 board shall be connected to a Segger Embedded Debugger Unit -`J-Link OB `_. This provides a debug -interface to the NRF52840 chip. You can use JLink to communicate with -the NRF52840. - -Flashing -======== - -#. Download JLink from the Segger `JLink Downloads Page`_. Go to the section - "J-Link Software and Documentation Pack" and install the "J-Link Software - and Documentation pack for Linux". The application JLinkExe needs to be - accessible from your path. - -#. Run your favorite terminal program to listen for output. Under Linux the - terminal should be :code:`/dev/ttyACM0`. For example: - - .. code-block:: console - - $ minicom -D /dev/ttyACM0 -o - - The -o option tells minicom not to send the modem initialization string. - Connection should be configured as follows: - - - Speed: 115200 - - Data: 8 bits - - Parity: None - - Stop bits: 1 - -#. Connect the RAK5010 board to your host computer using the USB debug port. - Then build and flash the :zephyr:code-sample:`hello_world` application. - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: rak5010/nrf52840 - :goals: build flash - - You should see "Hello World! rak5010_nrf52840" in your terminal. - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:zephyr:code-sample:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: rak5010/nrf52840 - :maybe-skip-config: - :goals: debug - -References -********** - -.. target-notes:: - -.. _RAK5010 Product Description: - https://doc.rakwireless.com/datasheet/rakproducts/rak5010-wistrio-nb-iot-tracker-datasheet - -.. _JLink Downloads Page: - https://www.segger.com/downloads/jlink diff --git a/boards/rak/index.rst b/boards/rakwireless/index.rst similarity index 100% rename from boards/rak/index.rst rename to boards/rakwireless/index.rst diff --git a/boards/rakwireless/rak11720/Kconfig.defconfig b/boards/rakwireless/rak11720/Kconfig.defconfig new file mode 100644 index 00000000000..ae6e8ff2bf8 --- /dev/null +++ b/boards/rakwireless/rak11720/Kconfig.defconfig @@ -0,0 +1,11 @@ +# RAKWIRELESS RAK11720 Board configuration +# Copyright (c) 2024 RAKwireless Technology Co., Ltd. +# Sercan Erat +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_RAK11720 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 32768 if AMBIQ_STIMER_TIMER + +endif # BOARD_RAK11720 diff --git a/boards/rak/rak11720/Kconfig.rak11720 b/boards/rakwireless/rak11720/Kconfig.rak11720 similarity index 100% rename from boards/rak/rak11720/Kconfig.rak11720 rename to boards/rakwireless/rak11720/Kconfig.rak11720 diff --git a/boards/rak/rak11720/board.cmake b/boards/rakwireless/rak11720/board.cmake similarity index 100% rename from boards/rak/rak11720/board.cmake rename to boards/rakwireless/rak11720/board.cmake diff --git a/boards/rak/rak11720/board.yml b/boards/rakwireless/rak11720/board.yml similarity index 100% rename from boards/rak/rak11720/board.yml rename to boards/rakwireless/rak11720/board.yml diff --git a/boards/rak/rak11720/doc/img/rak11720.webp b/boards/rakwireless/rak11720/doc/img/rak11720.webp similarity index 100% rename from boards/rak/rak11720/doc/img/rak11720.webp rename to boards/rakwireless/rak11720/doc/img/rak11720.webp diff --git a/boards/rakwireless/rak11720/doc/index.rst b/boards/rakwireless/rak11720/doc/index.rst new file mode 100644 index 00000000000..cae97f57c14 --- /dev/null +++ b/boards/rakwireless/rak11720/doc/index.rst @@ -0,0 +1,115 @@ +.. zephyr:board:: rak11720 + +The RAK11720 is a WisBlock Core module for RAK WisBlock. +It is based on the powerful ultra-low power Apollo3 Blue SoC (AMA3B1KK-KBR-B0) +from Ambiq together with a Semtech SX1262 LoRa® transceiver. + +The AMA3B1KK-KBR-B0 has an integrated Bluetooth Low Energy transceiver +that enhances the communication capabilities. The RAK11720 stamp module +comes in the same size and footprint as our RAK3172 module which gives +you the opportunity to enhance your existing designs +with BLE without designing a new PCB. + +Hardware +******** + +The easiset way to use a RAK11720, is the WisBlock Modular system. +A WisBlock Base board (RAK19007) which provides the power +supply and programming/debug interface is the base to plug a +RAK11722 (WisBlock Core module with the RAK11720) in. + +- Apollo3 Blue SoC with up to 96 MHz operating frequency +- ARM® Cortex® M4F core +- 16 kB 2-way Associative/Direct-Mapped Cache per core +- Up to 1 MB of flash memory for code/data +- Up to 384 KB of low leakage / low power RAM for code/data +- Integrated Bluetooth 5 Low-energy controller +- Semtech SX1262 low power high range LoRa transceiver +- iPEX connectors for the LORA antenna and BLE antenna. +- 2 user LEDs on RAK19007 WisBlock Base board +- Powered by either Micro USB, 3.7V rechargeable battery or a 5V Solar Panel Port + +For more information about the RAK11720 stamp module: + +- `WisDuo RAK11720 Website`_ +- `WisBlock RAK11722 Website`_ + +Supported Features +================== + +The RAK11720 module configuration supports the following hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+----------------------+ +| STIMER | on-chip | stimer | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ +| RADIO | on-chip | bluetooth | ++-----------+------------+----------------------+ +| RADIO | on-board | LoRa (SX1262) | ++-----------+------------+----------------------+ + +The default configuration can be found in the defconfig file: +``boards/rak/rak11720/rak11720_defconfig``. + +Programming and Debugging +========================= + +The RAK11720 board shall be connected to a Segger Embedded Debugger Unit +`J-Link OB `_. This provides a debug +interface to the Apollo3 Blue chip. You can use JLink to communicate with +the Apollo3 Blue. + +Flashing an application +----------------------- + +Connect your device to your host computer using the JLINK USB port. +The sample application :zephyr:code-sample:`hello_world` is used for this example. +Build the Zephyr kernel and application, then flash it to the device: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: rak11720 + :goals: flash + +.. note:: + ``west flash`` requires `SEGGER J-Link software`_ and `pylink`_ Python module + to be installed on you host computer. + +Open a serial terminal (minicom, putty, etc.) with the following settings: + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Reset the board and you should be able to see on the corresponding Serial Port +the following message: + +.. code-block:: console + + Hello World! rak11720/apollo3_blue + +.. _WisDuo RAK11720 Website: + https://docs.rakwireless.com/Product-Categories/WisDuo/RAK11720-Module/Overview/#product-description + +.. _WisBlock RAK11722 Website: + https://docs.rakwireless.com/Product-Categories/WisBlock/RAK11722/Overview/#product-description + +.. _SEGGER J-Link software: + https://www.segger.com/downloads/jlink + +.. _pylink: + https://github.com/Square/pylink diff --git a/boards/rak/rak11720/rak11720.dts b/boards/rakwireless/rak11720/rak11720.dts similarity index 78% rename from boards/rak/rak11720/rak11720.dts rename to boards/rakwireless/rak11720/rak11720.dts index 4f4f75d7ff2..828c676f0dd 100644 --- a/boards/rak/rak11720/rak11720.dts +++ b/boards/rakwireless/rak11720/rak11720.dts @@ -8,6 +8,7 @@ #include #include #include "rak11720_apollo3-pinctrl.dtsi" +#include / { model = "RAKwireless RAK11720 WisBlock LPWAN Module"; @@ -19,9 +20,11 @@ zephyr,flash = &flash0; zephyr,console = &uart0; zephyr,shell-uart = &uart0; + zephyr,uart-mcumgr = &uart0; zephyr,uart-pipe = &uart0; zephyr,flash-controller = &flash; zephyr,bt_hci = &bt_hci_apollo; + zephyr,code-partition = &slot0_partition; }; aliases { @@ -29,6 +32,8 @@ led0 = &blue_led; led1 = &green_led; lora0 = &lora; + bootloader-led0 = &blue_led; + mcuboot-led0 = &blue_led; }; leds { @@ -53,14 +58,36 @@ #address-cells = <1>; #size-cells = <1>; - /* Set 16KB of storage at the end of the 976KB of flash */ - storage_partition: partition@f0000 { + internal_boot_partition: partition@0 { + label = "internal_bootloader"; + reg = <0x00000000 0xc000>; + }; + + boot_partition: partition@c000 { + label = "mcuboot"; + reg = <0x0000c000 0xc000>; + }; + slot0_partition: partition@18000 { + label = "image-0"; + reg = <0x00018000 0x72000>; + }; + slot1_partition: partition@8a000 { + label = "image-1"; + reg = <0x0008a000 0x72000>; + }; + + /* Set 16KB of storage at the end of the 1024KB of flash */ + storage_partition: partition@fc000 { label = "storage"; - reg = <0x000f0000 0x4000>; + reg = <0x000fc000 0x4000>; }; }; }; +&stimer0 { + clk-source = <3>; +}; + &bleif { pinctrl-0 = <&bleif_default>; pinctrl-names = "default"; diff --git a/boards/rak/rak11720/rak11720.yaml b/boards/rakwireless/rak11720/rak11720.yaml similarity index 100% rename from boards/rak/rak11720/rak11720.yaml rename to boards/rakwireless/rak11720/rak11720.yaml diff --git a/boards/rak/rak11720/rak11720_apollo3-pinctrl.dtsi b/boards/rakwireless/rak11720/rak11720_apollo3-pinctrl.dtsi similarity index 100% rename from boards/rak/rak11720/rak11720_apollo3-pinctrl.dtsi rename to boards/rakwireless/rak11720/rak11720_apollo3-pinctrl.dtsi diff --git a/boards/rak/rak11720/rak11720_defconfig b/boards/rakwireless/rak11720/rak11720_defconfig similarity index 100% rename from boards/rak/rak11720/rak11720_defconfig rename to boards/rakwireless/rak11720/rak11720_defconfig diff --git a/boards/rakwireless/rak4631/Kconfig.defconfig b/boards/rakwireless/rak4631/Kconfig.defconfig new file mode 100644 index 00000000000..906754a1eb0 --- /dev/null +++ b/boards/rakwireless/rak4631/Kconfig.defconfig @@ -0,0 +1,8 @@ +# RAKWIRELESS RAK4631 Board configuration + +# Copyright (c) 2021 Guillaume Paquet +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_RAK4631 + +endif # BOARD_RAK4631 diff --git a/boards/rak/rak4631/Kconfig.rak4631 b/boards/rakwireless/rak4631/Kconfig.rak4631 similarity index 100% rename from boards/rak/rak4631/Kconfig.rak4631 rename to boards/rakwireless/rak4631/Kconfig.rak4631 diff --git a/boards/rak/rak4631/board.cmake b/boards/rakwireless/rak4631/board.cmake similarity index 100% rename from boards/rak/rak4631/board.cmake rename to boards/rakwireless/rak4631/board.cmake diff --git a/boards/rak/rak4631/board.yml b/boards/rakwireless/rak4631/board.yml similarity index 100% rename from boards/rak/rak4631/board.yml rename to boards/rakwireless/rak4631/board.yml diff --git a/boards/rak/rak4631/doc/img/rak4631-front-parts.jpg b/boards/rakwireless/rak4631/doc/img/rak4631-front-parts.jpg similarity index 100% rename from boards/rak/rak4631/doc/img/rak4631-front-parts.jpg rename to boards/rakwireless/rak4631/doc/img/rak4631-front-parts.jpg diff --git a/boards/rakwireless/rak4631/doc/index.rst b/boards/rakwireless/rak4631/doc/index.rst new file mode 100644 index 00000000000..5d237f7bf71 --- /dev/null +++ b/boards/rakwireless/rak4631/doc/index.rst @@ -0,0 +1,147 @@ +.. zephyr:board:: rak4631 + +Overview +******** + +RAK4631 is a WisBlock Core module for RAK WisBlock. +It extends the WisBlock series with a powerful +Nordic nRF52840 MCU that supports Bluetooth 5.0 +(Bluetooth Low Energy) and the newest LoRa transceiver +from Semtech, the SX1262. The Semtech SX1262 has compared +to the older SX127x series a lower power consumption at +the same TX power. This makes the RAK4631 an ultra-low +power communication solution. RAK4631 can be comfortably +programmed with ZephyrRTOS. + +Hardware +******** + +To use a RAK4631, you need at least a WisBlock Base +to plug the module in. WisBlock Base is the power +supply for the RAK4631 module and has the +programming/debug interface. + +- nRF52840 ARM Cortex-M4F Processor +- 64 MHz CPU clock +- 1 Micro-AB USB OTG host/device +- Semtech SX1262 low power high range LoRa transceiver +- iPEX connectors for the LORA antenna and BLE antenna. +- Multiple interfaces, I2C, UART, GPIO, ADC +- 2 user LEDs on RAK5005 mother Board +- Powered by either Micro USB, 3.7V rechargeable battery or a 5V Solar Panel Port + +Supported Features +================== + +The ``rak4631/nrf52840`` board configuration supports the following hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth, | +| | | ieee802154 | ++-----------+------------+----------------------+ +| RADIO | on-board | LoRa (SX1262) | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| USB | on-chip | usb | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +The default board configuration can be found in +:zephyr_file:`boards/rakwireless/rak4631/rak4631_nrf52840_defconfig` + +Connections and IOs +=================== + +LED +--- + +* LED1 (green) = P1.3 +* LED2 (blue) = P1.4 + +Programming and Debugging +************************* + +The RAK4631 board shall be connected to a Segger Embedded Debugger Unit +`J-Link OB `_. This provides a debug +interface to the NRF52840 chip. You can use JLink to communicate with +the NRF52840. + +Flashing +======== + +#. Download JLink from the Segger `JLink Downloads Page`_. Go to the section + "J-Link Software and Documentation Pack" and install the "J-Link Software + and Documentation pack for Linux". The application JLinkExe needs to be + accessible from your path. + +#. Run your favorite terminal program to listen for output. Under Linux the + terminal should be :code:`/dev/ttyACM0`. For example: + + .. code-block:: console + + $ minicom -D /dev/ttyACM0 -o + + The -o option tells minicom not to send the modem initialization string. + Connection should be configured as follows: + + - Speed: 115200 + - Data: 8 bits + - Parity: None + - Stop bits: 1 + +#. Connect the RAK4631 board to your host computer using the USB debug port. + Then build and flash the :zephyr:code-sample:`hello_world` application. + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: rak4631/nrf52840 + :goals: build flash + + You should see "Hello World! rak4631_nrf52840" in your terminal. + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: rak4631/nrf52840 + :maybe-skip-config: + :goals: debug + +References +********** + +.. target-notes:: + +.. _RAK4631 Product Description: + https://docs.rakwireless.com/Product-Categories/WisBlock/RAK4631/Datasheet/#overview + +.. _JLink Downloads Page: + https://www.segger.com/downloads/jlink diff --git a/boards/rakwireless/rak4631/pre_dt_board.cmake b/boards/rakwireless/rak4631/pre_dt_board.cmake new file mode 100644 index 00000000000..3369c21d3af --- /dev/null +++ b/boards/rakwireless/rak4631/pre_dt_board.cmake @@ -0,0 +1,7 @@ +# Copyright (c) 2022 Nordic Semiconductor +# SPDX-License-Identifier: Apache-2.0 + +# Suppress "unique_unit_address_if_enabled" to handle the following overlaps: +# - power@40000000 & clock@40000000 & bprot@40000000 +# - acl@4001e000 & flash-controller@4001e000 +list(APPEND EXTRA_DTC_FLAGS "-Wno-unique_unit_address_if_enabled") diff --git a/boards/rak/rak4631/rak4631_nrf52840-pinctrl.dtsi b/boards/rakwireless/rak4631/rak4631_nrf52840-pinctrl.dtsi similarity index 100% rename from boards/rak/rak4631/rak4631_nrf52840-pinctrl.dtsi rename to boards/rakwireless/rak4631/rak4631_nrf52840-pinctrl.dtsi diff --git a/boards/rak/rak4631/rak4631_nrf52840.dts b/boards/rakwireless/rak4631/rak4631_nrf52840.dts similarity index 100% rename from boards/rak/rak4631/rak4631_nrf52840.dts rename to boards/rakwireless/rak4631/rak4631_nrf52840.dts diff --git a/boards/rak/rak4631/rak4631_nrf52840.yaml b/boards/rakwireless/rak4631/rak4631_nrf52840.yaml similarity index 100% rename from boards/rak/rak4631/rak4631_nrf52840.yaml rename to boards/rakwireless/rak4631/rak4631_nrf52840.yaml diff --git a/boards/rak/rak4631/rak4631_nrf52840_defconfig b/boards/rakwireless/rak4631/rak4631_nrf52840_defconfig similarity index 100% rename from boards/rak/rak4631/rak4631_nrf52840_defconfig rename to boards/rakwireless/rak4631/rak4631_nrf52840_defconfig diff --git a/boards/rakwireless/rak5010/Kconfig.defconfig b/boards/rakwireless/rak5010/Kconfig.defconfig new file mode 100644 index 00000000000..5d71cbdc1f4 --- /dev/null +++ b/boards/rakwireless/rak5010/Kconfig.defconfig @@ -0,0 +1,8 @@ +# RAKWIRELESS RAK5010 Board configuration + +# Copyright (c) 2020 Guillaume Paquet +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_RAK5010 + +endif # BOARD_RAK5010 diff --git a/boards/rak/rak5010/Kconfig.rak5010 b/boards/rakwireless/rak5010/Kconfig.rak5010 similarity index 100% rename from boards/rak/rak5010/Kconfig.rak5010 rename to boards/rakwireless/rak5010/Kconfig.rak5010 diff --git a/boards/rak/rak5010/board.cmake b/boards/rakwireless/rak5010/board.cmake similarity index 100% rename from boards/rak/rak5010/board.cmake rename to boards/rakwireless/rak5010/board.cmake diff --git a/boards/rak/rak5010/board.yml b/boards/rakwireless/rak5010/board.yml similarity index 100% rename from boards/rak/rak5010/board.yml rename to boards/rakwireless/rak5010/board.yml diff --git a/boards/rak/rak5010/doc/img/rak5010-front-parts.jpg b/boards/rakwireless/rak5010/doc/img/rak5010-front-parts.jpg similarity index 100% rename from boards/rak/rak5010/doc/img/rak5010-front-parts.jpg rename to boards/rakwireless/rak5010/doc/img/rak5010-front-parts.jpg diff --git a/boards/rakwireless/rak5010/doc/index.rst b/boards/rakwireless/rak5010/doc/index.rst new file mode 100644 index 00000000000..3ffc2b7f712 --- /dev/null +++ b/boards/rakwireless/rak5010/doc/index.rst @@ -0,0 +1,155 @@ +.. zephyr:board:: rak5010 + +RAK5010 +####### + +Overview +******** + +WisTrio NB-IoT Tracker Pro (RAK5010) is a tracker +with integrated LTE CAT M1 & NB1, GPS, BLE, and sensors. +It is built on the Quectel BG96 LTE CAT M1 & NB1 module, +which has an integrated GPS receiver. The MCU running +the board is a Nordic nRF52840 controller. + +As it has both GPS and BLE it can be used for outdoor +and indoor scenarios, where location-based services need be present. + +The built-in sensors for RAK5010 are temperature and +humidity sensor, motion sensor, pressure sensor, and light sensor. +The extension IOs allow adding more sensors in addition to the on-board ones. + +This board is particularly suitable to be used as a +quick testing and prototyping tool for applications +requiring NB-IoT connectivity. Application development +supports the GCC environment. + +Hardware +******** + +- nRF52840 ARM Cortex-M4F Processor +- 32.768 kHz crystal oscillator +- 1 Micro-AB USB OTG host/device +- Quectel BG96, with LTE CAT M1, LTE NB1, and GNSS +- iPEX connectors for the LTE and GPS antenna and an on-board ceramic antenna for the BLE. +- nano-SIM and ESIM options. +- Multiple interfaces, I2C, UART, GPIO, ADC +- 1 user LED +- 1 SHTC3 Humidity and Temperature Sensor +- 1 OPT3001DNPR Ambient Light Sensor +- 1 LPS22HB Pressure Sensor +- 1 LIS3DH Motion Sensor +- Powered by either Micro USB, 3.7V rechargeable battery or a 5V Solar Panel Port + +Supported Features +================== + +The ``rak5010/nrf52840`` board configuration supports the following hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth, | +| | | ieee802154 | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| USB | on-chip | usb | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +Other hardware features have not been enabled yet for this board. + +Connections and IOs +=================== + +LED +--- + +* LED0 (green) = P0.12 + + +Programming and Debugging +************************* + +The RAK5010 board shall be connected to a Segger Embedded Debugger Unit +`J-Link OB `_. This provides a debug +interface to the NRF52840 chip. You can use JLink to communicate with +the NRF52840. + +Flashing +======== + +#. Download JLink from the Segger `JLink Downloads Page`_. Go to the section + "J-Link Software and Documentation Pack" and install the "J-Link Software + and Documentation pack for Linux". The application JLinkExe needs to be + accessible from your path. + +#. Run your favorite terminal program to listen for output. Under Linux the + terminal should be :code:`/dev/ttyACM0`. For example: + + .. code-block:: console + + $ minicom -D /dev/ttyACM0 -o + + The -o option tells minicom not to send the modem initialization string. + Connection should be configured as follows: + + - Speed: 115200 + - Data: 8 bits + - Parity: None + - Stop bits: 1 + +#. Connect the RAK5010 board to your host computer using the USB debug port. + Then build and flash the :zephyr:code-sample:`hello_world` application. + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: rak5010/nrf52840 + :goals: build flash + + You should see "Hello World! rak5010_nrf52840" in your terminal. + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: rak5010/nrf52840 + :maybe-skip-config: + :goals: debug + +References +********** + +.. target-notes:: + +.. _RAK5010 Product Description: + https://doc.rakwireless.com/datasheet/rakproducts/rak5010-wistrio-nb-iot-tracker-datasheet + +.. _JLink Downloads Page: + https://www.segger.com/downloads/jlink diff --git a/boards/rakwireless/rak5010/pre_dt_board.cmake b/boards/rakwireless/rak5010/pre_dt_board.cmake new file mode 100644 index 00000000000..3369c21d3af --- /dev/null +++ b/boards/rakwireless/rak5010/pre_dt_board.cmake @@ -0,0 +1,7 @@ +# Copyright (c) 2022 Nordic Semiconductor +# SPDX-License-Identifier: Apache-2.0 + +# Suppress "unique_unit_address_if_enabled" to handle the following overlaps: +# - power@40000000 & clock@40000000 & bprot@40000000 +# - acl@4001e000 & flash-controller@4001e000 +list(APPEND EXTRA_DTC_FLAGS "-Wno-unique_unit_address_if_enabled") diff --git a/boards/rak/rak5010/rak5010_nrf52840-pinctrl.dtsi b/boards/rakwireless/rak5010/rak5010_nrf52840-pinctrl.dtsi similarity index 100% rename from boards/rak/rak5010/rak5010_nrf52840-pinctrl.dtsi rename to boards/rakwireless/rak5010/rak5010_nrf52840-pinctrl.dtsi diff --git a/boards/rak/rak5010/rak5010_nrf52840.dts b/boards/rakwireless/rak5010/rak5010_nrf52840.dts similarity index 100% rename from boards/rak/rak5010/rak5010_nrf52840.dts rename to boards/rakwireless/rak5010/rak5010_nrf52840.dts diff --git a/boards/rak/rak5010/rak5010_nrf52840.yaml b/boards/rakwireless/rak5010/rak5010_nrf52840.yaml similarity index 100% rename from boards/rak/rak5010/rak5010_nrf52840.yaml rename to boards/rakwireless/rak5010/rak5010_nrf52840.yaml diff --git a/boards/rak/rak5010/rak5010_nrf52840_defconfig b/boards/rakwireless/rak5010/rak5010_nrf52840_defconfig similarity index 100% rename from boards/rak/rak5010/rak5010_nrf52840_defconfig rename to boards/rakwireless/rak5010/rak5010_nrf52840_defconfig diff --git a/boards/raspberrypi/common/rpi_pico-led.dtsi b/boards/raspberrypi/common/rpi_pico-led.dtsi new file mode 100644 index 00000000000..951e36260f2 --- /dev/null +++ b/boards/raspberrypi/common/rpi_pico-led.dtsi @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2021 Yonatan Schachter + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Pico and Pico 2 boards (but not Pico W) have a common LED placement. */ +/ { + leds { + compatible = "gpio-leds"; + led0: led_0 { + gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>; + label = "LED"; + }; + }; + + pwm_leds { + compatible = "pwm-leds"; + status = "disabled"; + pwm_led0: pwm_led_0 { + pwms = <&pwm 9 PWM_MSEC(20) PWM_POLARITY_NORMAL>; + label = "PWM_LED"; + }; + }; + + aliases { + led0 = &led0; + pwm-led0 = &pwm_led0; + }; +}; diff --git a/boards/raspberrypi/common/rpi_pico-pinctrl-common.dtsi b/boards/raspberrypi/common/rpi_pico-pinctrl-common.dtsi new file mode 100644 index 00000000000..66ccfd20895 --- /dev/null +++ b/boards/raspberrypi/common/rpi_pico-pinctrl-common.dtsi @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2021, Yonatan Schachter + * SPDX-License-Identifier: Apache-2.0 + */ + +/* The Pico and Pico 2 are pin compatible. */ +&pinctrl { + uart0_default: uart0_default { + group1 { + pinmux = ; + }; + group2 { + pinmux = ; + input-enable; + }; + }; + + i2c0_default: i2c0_default { + group1 { + pinmux = , ; + input-enable; + input-schmitt-enable; + }; + }; + + i2c1_default: i2c1_default { + group1 { + pinmux = , ; + input-enable; + input-schmitt-enable; + }; + }; + + spi0_default: spi0_default { + group1 { + pinmux = , , ; + }; + group2 { + pinmux = ; + input-enable; + }; + }; + + pwm_ch4b_default: pwm_ch4b_default { + group1 { + pinmux = ; + }; + }; + + adc_default: adc_default { + group1 { + pinmux = , , , ; + input-enable; + }; + }; +}; diff --git a/boards/raspberrypi/rpi_4b/doc/index.rst b/boards/raspberrypi/rpi_4b/doc/index.rst index 6f840ec55e5..88862cf7f9f 100644 --- a/boards/raspberrypi/rpi_4b/doc/index.rst +++ b/boards/raspberrypi/rpi_4b/doc/index.rst @@ -1,7 +1,4 @@ -.. rpi_4b: - -Raspberry Pi 4 Model B (Cortex-A72) -################################### +.. zephyr:board:: rpi_4b Overview ******** diff --git a/boards/raspberrypi/rpi_5/doc/index.rst b/boards/raspberrypi/rpi_5/doc/index.rst index fd0ad27df0a..d503f573df3 100644 --- a/boards/raspberrypi/rpi_5/doc/index.rst +++ b/boards/raspberrypi/rpi_5/doc/index.rst @@ -1,7 +1,4 @@ -.. _rpi_5: - -Raspberry Pi 5 (Cortex-A76) -########################### +.. zephyr:board:: rpi_5 Overview ******** @@ -44,6 +41,9 @@ The Raspberry Pi 5 board configuration supports the following hardware features: - N/A - :dtcompatible:`arm,gic-v2` * - GPIO + - :kconfig:option:`CONFIG_GPIO` + - :dtcompatible:`raspberrypi,rp1-gpio` + * - GPIO (Internal) - :kconfig:option:`CONFIG_GPIO` - :dtcompatible:`brcm,brcmstb-gpio` * - UART diff --git a/boards/raspberrypi/rpi_5/rpi_5.dts b/boards/raspberrypi/rpi_5/rpi_5.dts index 6fca0efd3d0..adba94d9474 100644 --- a/boards/raspberrypi/rpi_5/rpi_5.dts +++ b/boards/raspberrypi/rpi_5/rpi_5.dts @@ -43,3 +43,7 @@ status = "okay"; current-speed = <115200>; }; + +&gpio0_0 { + status = "okay"; +}; diff --git a/boards/raspberrypi/rpi_pico/Kconfig b/boards/raspberrypi/rpi_pico/Kconfig new file mode 100644 index 00000000000..475fe09d2a7 --- /dev/null +++ b/boards/raspberrypi/rpi_pico/Kconfig @@ -0,0 +1,5 @@ +# Copyright (c) 2021 Yonatan Schachter +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_RPI_PICO + select RP2_FLASH_W25Q080 diff --git a/boards/raspberrypi/rpi_pico/Kconfig.defconfig b/boards/raspberrypi/rpi_pico/Kconfig.defconfig index 1b4c3175a51..71c4fd9c43f 100644 --- a/boards/raspberrypi/rpi_pico/Kconfig.defconfig +++ b/boards/raspberrypi/rpi_pico/Kconfig.defconfig @@ -3,9 +3,6 @@ if BOARD_RPI_PICO -config RP2_FLASH_W25Q080 - default y - if I2C_DW config I2C_DW_CLOCK_SPEED @@ -16,4 +13,15 @@ endif # I2C_DW config USB_SELF_POWERED default n +if BOARD_RPI_PICO_RP2040_W && WIFI_AIROC + +config MAIN_STACK_SIZE + default 4096 + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 16384 + +endif # BOARD_RPI_PICO_RP2040_W && WIFI_AIROC + endif # BOARD_RPI_PICO diff --git a/boards/raspberrypi/rpi_pico/board.cmake b/boards/raspberrypi/rpi_pico/board.cmake index e9cd4edc18f..8d09fe3ab05 100644 --- a/boards/raspberrypi/rpi_pico/board.cmake +++ b/boards/raspberrypi/rpi_pico/board.cmake @@ -13,7 +13,7 @@ # The value must be the 'stem' part of the name of one of the files # in the openocd interface configuration file. # The setting is store to CMakeCache.txt. -if ("${RPI_PICO_DEBUG_ADAPTER}" STREQUAL "") +if("${RPI_PICO_DEBUG_ADAPTER}" STREQUAL "") set(RPI_PICO_DEBUG_ADAPTER "cmsis-dap") endif() diff --git a/boards/raspberrypi/rpi_pico/doc/index.rst b/boards/raspberrypi/rpi_pico/doc/index.rst index b2af4693b01..71f5b42003e 100644 --- a/boards/raspberrypi/rpi_pico/doc/index.rst +++ b/boards/raspberrypi/rpi_pico/doc/index.rst @@ -1,7 +1,4 @@ -.. _rpi_pico: - -Raspberry Pi Pico -################# +.. zephyr:board:: rpi_pico Overview ******** @@ -99,6 +96,8 @@ hardware features: - :kconfig:option:`CONFIG_SPI` - :dtcompatible:`raspberrypi,pico-spi-pio` +.. _rpi_pico_pin_mapping: + Pin Mapping =========== @@ -156,6 +155,23 @@ devices as well as both PIO devices). Programming and Debugging ************************* +System requirements +=================== + +Prerequisites for the Pico W +---------------------------- + +Building for the Raspberry Pi Pico W requires the AIROC binary blobs +provided by Infineon. Run the command below to retrieve those files: + +.. code-block:: console + + west blobs fetch hal_infineon + +.. note:: + + It is recommended running the command above after :file:`west update`. + Flashing ======== diff --git a/boards/raspberrypi/rpi_pico/rpi_pico-common.dtsi b/boards/raspberrypi/rpi_pico/rpi_pico-common.dtsi index 36058ef6483..811dafcdf77 100644 --- a/boards/raspberrypi/rpi_pico/rpi_pico-common.dtsi +++ b/boards/raspberrypi/rpi_pico/rpi_pico-common.dtsi @@ -6,7 +6,7 @@ #include -#include +#include #include "rpi_pico-pinctrl.dtsi" #include @@ -89,11 +89,6 @@ }; }; -&clocks { - pinctrl-0 = <&clocks_default>; - pinctrl-names = "default"; -}; - &uart0 { current-speed = <115200>; status = "okay"; @@ -152,7 +147,6 @@ zephyr_udc0: &usbd { &pwm { pinctrl-0 = <&pwm_ch4b_default>; pinctrl-names = "default"; - divider-int-0 = <255>; }; &vreg { diff --git a/boards/raspberrypi/rpi_pico/rpi_pico-pinctrl.dtsi b/boards/raspberrypi/rpi_pico/rpi_pico-pinctrl.dtsi index 761354420c6..5556638daa6 100644 --- a/boards/raspberrypi/rpi_pico/rpi_pico-pinctrl.dtsi +++ b/boards/raspberrypi/rpi_pico/rpi_pico-pinctrl.dtsi @@ -5,56 +5,4 @@ #include -&pinctrl { - uart0_default: uart0_default { - group1 { - pinmux = ; - }; - group2 { - pinmux = ; - input-enable; - }; - }; - - i2c0_default: i2c0_default { - group1 { - pinmux = , ; - input-enable; - input-schmitt-enable; - }; - }; - - i2c1_default: i2c1_default { - group1 { - pinmux = , ; - input-enable; - input-schmitt-enable; - }; - }; - - spi0_default: spi0_default { - group1 { - pinmux = , , ; - }; - group2 { - pinmux = ; - input-enable; - }; - }; - - pwm_ch4b_default: pwm_ch4b_default { - group1 { - pinmux = ; - }; - }; - - adc_default: adc_default { - group1 { - pinmux = , , , ; - input-enable; - }; - }; - - clocks_default: clocks_default { - }; -}; +#include "../common/rpi_pico-pinctrl-common.dtsi" diff --git a/boards/raspberrypi/rpi_pico/rpi_pico.dts b/boards/raspberrypi/rpi_pico/rpi_pico.dts index 97d721024d7..807dc8e7800 100644 --- a/boards/raspberrypi/rpi_pico/rpi_pico.dts +++ b/boards/raspberrypi/rpi_pico/rpi_pico.dts @@ -7,27 +7,4 @@ /dts-v1/; #include "rpi_pico-common.dtsi" - -/ { - leds { - compatible = "gpio-leds"; - led0: led_0 { - gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>; - label = "LED"; - }; - }; - - pwm_leds { - compatible = "pwm-leds"; - status = "disabled"; - pwm_led0: pwm_led_0 { - pwms = <&pwm 9 PWM_MSEC(20) PWM_POLARITY_NORMAL>; - label = "PWM_LED"; - }; - }; - - aliases { - led0 = &led0; - pwm-led0 = &pwm_led0; - }; -}; +#include "../common/rpi_pico-led.dtsi" diff --git a/boards/raspberrypi/rpi_pico/rpi_pico_rp2040_w.dts b/boards/raspberrypi/rpi_pico/rpi_pico_rp2040_w.dts index ae01f15d697..cba2142f7b5 100644 --- a/boards/raspberrypi/rpi_pico/rpi_pico_rp2040_w.dts +++ b/boards/raspberrypi/rpi_pico/rpi_pico_rp2040_w.dts @@ -1,5 +1,6 @@ /* * Copyright (c) 2023 Dave Rensberger - Beechwoods Software + * Copyright (c) 2024 Steve Boylan * * SPDX-License-Identifier: Apache-2.0 */ @@ -7,3 +8,60 @@ /dts-v1/; #include "rpi_pico-common.dtsi" + +&pinctrl { + pio0_spi0_default: pio0_spi0_default { + /* gpio 25 is used for chip select, not assigned to the PIO */ + group1 { + pinmux = ; + }; + }; + + airoc_wifi_default: airoc_wifi_default { + /* Control of GPIO24 is done through the WiFi driver */ + group1 { + pinmux = ; + input-enable; + }; + }; + + airoc_wifi_host_wake: airoc_wifi_host_wake { + /* Assign GPIO24 to SIO (GPIO) for use as an interrupt source */ + group1 { + /* Lacking a specific SIO pin definition, use the RP2040_PINMUX macro */ + pinmux = ; + input-enable; + }; + }; +}; + +&pio0 { + status = "okay"; + + pio0_spi0: pio0_spi0 { + compatible = "raspberrypi,pico-spi-pio"; + clocks = < &clocks RPI_PICO_CLKID_CLK_SYS >; + #address-cells = <1>; + #size-cells = <0>; + cs-gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; + clk-gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; + sio-gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&pio0_spi0_default>; + pinctrl-names = "default"; + status = "okay"; + airoc-wifi@0 { + compatible = "infineon,airoc-wifi"; + reg = < 0 >; + wifi-reg-on-gpios = < &gpio0 23 GPIO_ACTIVE_HIGH >; + bus-select-gpios = < &gpio0 24 GPIO_ACTIVE_HIGH >; + wifi-host-wake-gpios = < &gpio0 24 GPIO_ACTIVE_HIGH >; + spi-max-frequency = < 10000000 >; + spi-half-duplex; + spi-data-irq-shared; + pinctrl-0 = <&airoc_wifi_default>; + pinctrl-1 = <&airoc_wifi_host_wake>; + pinctrl-names = "default", "host_wake"; + status = "okay"; + }; + }; +}; diff --git a/boards/raspberrypi/rpi_pico/rpi_pico_rp2040_w_defconfig b/boards/raspberrypi/rpi_pico/rpi_pico_rp2040_w_defconfig index df003531af9..d1e96b968c5 100644 --- a/boards/raspberrypi/rpi_pico/rpi_pico_rp2040_w_defconfig +++ b/boards/raspberrypi/rpi_pico/rpi_pico_rp2040_w_defconfig @@ -9,3 +9,6 @@ CONFIG_BUILD_OUTPUT_HEX=y CONFIG_UART_INTERRUPT_DRIVEN=y CONFIG_RESET=y CONFIG_CLOCK_CONTROL=y + +# Default networking configuration +CONFIG_CYW43439=y diff --git a/boards/raspberrypi/rpi_pico2/Kconfig.defconfig b/boards/raspberrypi/rpi_pico2/Kconfig.defconfig new file mode 100644 index 00000000000..d122f3e4918 --- /dev/null +++ b/boards/raspberrypi/rpi_pico2/Kconfig.defconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2024 Andrew Featherstone +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_RPI_PICO2 + +config USB_SELF_POWERED + default n + +endif # BOARD_RPI_PICO2 diff --git a/boards/raspberrypi/rpi_pico2/Kconfig.rpi_pico2 b/boards/raspberrypi/rpi_pico2/Kconfig.rpi_pico2 new file mode 100644 index 00000000000..bcce97758fb --- /dev/null +++ b/boards/raspberrypi/rpi_pico2/Kconfig.rpi_pico2 @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Andrew Featherstone +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_RPI_PICO2 + select SOC_RP2350A_M33 if BOARD_RPI_PICO2_RP2350A_M33 diff --git a/boards/raspberrypi/rpi_pico2/board.cmake b/boards/raspberrypi/rpi_pico2/board.cmake new file mode 100644 index 00000000000..feae063129a --- /dev/null +++ b/boards/raspberrypi/rpi_pico2/board.cmake @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: Apache-2.0 + +if("${RPI_PICO_DEBUG_ADAPTER}" STREQUAL "") + set(RPI_PICO_DEBUG_ADAPTER "cmsis-dap") +endif() + +board_runner_args(openocd --cmd-pre-init "source [find interface/${RPI_PICO_DEBUG_ADAPTER}.cfg]") +board_runner_args(openocd --cmd-pre-init "source [find target/rp2350.cfg]") + +# The adapter speed is expected to be set by interface configuration. +# The Raspberry Pi's OpenOCD fork doesn't, so match their documentation at +# https://www.raspberrypi.com/documentation/microcontrollers/debug-probe.html#debugging-with-swd +board_runner_args(openocd --cmd-pre-init "set_adapter_speed_if_not_set 5000") + +board_runner_args(uf2 "--board-id=RP2350") + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/uf2.board.cmake) diff --git a/boards/raspberrypi/rpi_pico2/board.yml b/boards/raspberrypi/rpi_pico2/board.yml new file mode 100644 index 00000000000..2ab8ee59989 --- /dev/null +++ b/boards/raspberrypi/rpi_pico2/board.yml @@ -0,0 +1,6 @@ +board: + name: rpi_pico2 + full_name: Raspberry Pi Pico 2 + vendor: raspberrypi + socs: + - name: rp2350a diff --git a/boards/raspberrypi/rpi_pico2/doc/img/rpi_pico2.webp b/boards/raspberrypi/rpi_pico2/doc/img/rpi_pico2.webp new file mode 100644 index 00000000000..6a4895ba7b2 Binary files /dev/null and b/boards/raspberrypi/rpi_pico2/doc/img/rpi_pico2.webp differ diff --git a/boards/raspberrypi/rpi_pico2/doc/index.rst b/boards/raspberrypi/rpi_pico2/doc/index.rst new file mode 100644 index 00000000000..1457a8b849e --- /dev/null +++ b/boards/raspberrypi/rpi_pico2/doc/index.rst @@ -0,0 +1,93 @@ +.. zephyr:board:: rpi_pico2 + +Overview +******** + +The Raspberry Pi Pico 2 is the second-generation product in the Raspberry Pi +Pico family. From the `Raspberry Pi website `_ is referred to as Pico 2. + +There are many limitations of the board currently. Including but not limited to: +- The Zephyr build only supports configuring the RP2350A with the Cortex-M33 cores. +- As with the Pico 1, there's no support for running any code on the second core. + +Hardware +******** + +- Dual Cortex-M33 or Hazard3 processors at up to 150MHz +- 520KB of SRAM, and 4MB of on-board flash memory +- USB 1.1 with device and host support +- Low-power sleep and dormant modes +- Drag-and-drop programming using mass storage over USB +- 26 multi-function GPIO pins including 3 that can be used for ADC +- 2 SPI, 2 I2C, 2 UART, 3 12-bit 500ksps Analogue to Digital - Converter (ADC), 24 controllable PWM channels +- 2 Timer with 4 alarms, 1 AON Timer +- Temperature sensor +- 3 Programmable IO (PIO) blocks, 12 state machines total for custom peripheral support + + - Flexible, user-programmable high-speed IO + - Can emulate interfaces such as SD Card and VGA + +Supported Features +================== + +The ``rpi_pico2/rp2350a/m33`` board target supports the following +hardware features: + +.. list-table:: + :header-rows: 1 + + * - Peripheral + - Kconfig option + - Devicetree compatible + * - NVIC + - N/A + - :dtcompatible:`arm,v8m-nvic` + * - ADC + - :kconfig:option:`CONFIG_ADC` + - :dtcompatible:`raspberrypi,pico-adc` + * - Clock controller + - :kconfig:option:`CONFIG_CLOCK_CONTROL` + - :dtcompatible:`raspberrypi,pico-clock-controller` + * - Counter + - :kconfig:option:`CONFIG_COUNTER` + - :dtcompatible:`raspberrypi,pico-timer` + * - DMA + - :kconfig:option:`CONFIG_DMA` + - :dtcompatible:`raspberrypi,pico-dma` + * - GPIO + - :kconfig:option:`CONFIG_GPIO` + - :dtcompatible:`raspberrypi,pico-gpio` + * - HWINFO + - :kconfig:option:`CONFIG_HWINFO` + - N/A + * - I2C + - :kconfig:option:`CONFIG_I2C` + - :dtcompatible:`snps,designware-i2c` + * - PWM + - :kconfig:option:`CONFIG_PWM` + - :dtcompatible:`raspberrypi,pico-pwm` + * - SPI + - :kconfig:option:`CONFIG_SPI` + - :dtcompatible:`raspberrypi,pico-spi` + * - UART + - :kconfig:option:`CONFIG_SERIAL` + - :dtcompatible:`raspberrypi,pico-uart` + * - UART (PIO) + - :kconfig:option:`CONFIG_SERIAL` + - :dtcompatible:`raspberrypi,pico-uart-pio` + +Connections and IOs +=================== + +The default pin mapping is unchanged from the Pico 1 (see :ref:`rpi_pico_pin_mapping`). + +Programming and Debugging +************************* + +As with the Pico 1, the SWD interface can be used to program and debug the +device, e.g. using OpenOCD with the `Raspberry Pi Debug Probe `_ . + +References +********** + +.. target-notes:: diff --git a/boards/raspberrypi/rpi_pico2/rpi_pico2-pinctrl.dtsi b/boards/raspberrypi/rpi_pico2/rpi_pico2-pinctrl.dtsi new file mode 100644 index 00000000000..a7841dc2da6 --- /dev/null +++ b/boards/raspberrypi/rpi_pico2/rpi_pico2-pinctrl.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2024, Andrew Featherstone + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#include "../common/rpi_pico-pinctrl-common.dtsi" diff --git a/boards/raspberrypi/rpi_pico2/rpi_pico2.dtsi b/boards/raspberrypi/rpi_pico2/rpi_pico2.dtsi new file mode 100644 index 00000000000..85cdb97e845 --- /dev/null +++ b/boards/raspberrypi/rpi_pico2/rpi_pico2.dtsi @@ -0,0 +1,144 @@ +/* + * Copyright (c) 2024 Andrew Featherstone + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#include +#include + +#include "rpi_pico2-pinctrl.dtsi" +#include "../common/rpi_pico-led.dtsi" + +/ { + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,code-partition = &code_partition; + }; + + aliases { + watchdog0 = &wdt0; + }; + + pico_header: connector { + compatible = "raspberrypi,pico-header"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpio0 0 0>, /* GP0 */ + <1 0 &gpio0 1 0>, /* GP1 */ + <2 0 &gpio0 2 0>, /* GP2 */ + <3 0 &gpio0 3 0>, /* GP3 */ + <4 0 &gpio0 4 0>, /* GP4 */ + <5 0 &gpio0 5 0>, /* GP5 */ + <6 0 &gpio0 6 0>, /* GP6 */ + <7 0 &gpio0 7 0>, /* GP7 */ + <8 0 &gpio0 8 0>, /* GP8 */ + <9 0 &gpio0 9 0>, /* GP9 */ + <10 0 &gpio0 10 0>, /* GP10 */ + <11 0 &gpio0 11 0>, /* GP11 */ + <12 0 &gpio0 12 0>, /* GP12 */ + <13 0 &gpio0 13 0>, /* GP13 */ + <14 0 &gpio0 14 0>, /* GP14 */ + <15 0 &gpio0 15 0>, /* GP15 */ + <16 0 &gpio0 16 0>, /* GP16 */ + <17 0 &gpio0 17 0>, /* GP17 */ + <18 0 &gpio0 18 0>, /* GP18 */ + <19 0 &gpio0 19 0>, /* GP19 */ + <20 0 &gpio0 20 0>, /* GP20 */ + <21 0 &gpio0 21 0>, /* GP21 */ + <22 0 &gpio0 22 0>, /* GP22 */ + <26 0 &gpio0 26 0>, /* GP26 */ + <27 0 &gpio0 27 0>, /* GP27 */ + <28 0 &gpio0 28 0>; /* GP28 */ + }; +}; + +&flash0 { + reg = <0x10000000 DT_SIZE_M(4)>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserved memory for an image definition block. The block is much + * smaller than 256 bytes, but in practice the linker places the vector + * table at a much larger alignment offset. + */ + image_def: partition@0 { + label = "image_def"; + reg = <0x00000000 0x100>; + read-only; + }; + + /* + * Usable flash. Starts at 0x100, after the image definition block. + * The partition size is 4MB minus the 0x100 bytes taken by the + * image definition. + */ + code_partition: partition@100 { + label = "code-partition"; + reg = <0x100 (DT_SIZE_M(4) - 0x100)>; + read-only; + }; + }; +}; + +&uart0 { + current-speed = <115200>; + status = "okay"; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; +}; + +&gpio0 { + status = "okay"; +}; + +&spi0 { + clock-frequency = ; + pinctrl-0 = <&spi0_default>; + pinctrl-names = "default"; +}; + +&i2c0 { + clock-frequency = ; + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&i2c1 { + clock-frequency = ; + pinctrl-0 = <&i2c1_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&adc { + pinctrl-0 = <&adc_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&pwm { + pinctrl-0 = <&pwm_ch4b_default>; + pinctrl-names = "default"; + divider-int-0 = <255>; +}; + +&timer0 { + status = "okay"; +}; + +zephyr_udc0: &usbd { + status = "okay"; +}; + +pico_serial: &uart0 {}; diff --git a/boards/raspberrypi/rpi_pico2/rpi_pico2_rp2350a_m33.dts b/boards/raspberrypi/rpi_pico2/rpi_pico2_rp2350a_m33.dts new file mode 100644 index 00000000000..f96491f44e2 --- /dev/null +++ b/boards/raspberrypi/rpi_pico2/rpi_pico2_rp2350a_m33.dts @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2024 Andrew Featherstone + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +/* The build system assumes that there's a cpucluster-specific file. + * + * This file provides composition of the device tree: + * 1. The common features of the SoC + * 2. Core-specific configuration. + * 3. Board-specific configuration. + */ +#include +#include + +/* there's nothing specific to the Cortex-M33 cores vs the (not yet + * implemented) Hazard3 cores. + */ +#include "rpi_pico2.dtsi" diff --git a/boards/raspberrypi/rpi_pico2/rpi_pico2_rp2350a_m33.yaml b/boards/raspberrypi/rpi_pico2/rpi_pico2_rp2350a_m33.yaml new file mode 100644 index 00000000000..d3c340d88b1 --- /dev/null +++ b/boards/raspberrypi/rpi_pico2/rpi_pico2_rp2350a_m33.yaml @@ -0,0 +1,21 @@ +identifier: rpi_pico2/rp2350a/m33 +name: Raspberry Pi Pico 2 (Cortex-M33) +type: mcu +arch: arm +flash: 4096 +ram: 520 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - adc + - clock + - counter + - dma + - gpio + - hwinfo + - i2c + - pwm + - spi + - uart diff --git a/boards/raspberrypi/rpi_pico2/rpi_pico2_rp2350a_m33_defconfig b/boards/raspberrypi/rpi_pico2/rpi_pico2_rp2350a_m33_defconfig new file mode 100644 index 00000000000..8bd68e35113 --- /dev/null +++ b/boards/raspberrypi/rpi_pico2/rpi_pico2_rp2350a_m33_defconfig @@ -0,0 +1,14 @@ +# This configuration is orthogonal to whether the Cortex-M33 or Hazard3 cores +# are in use, but Zephyr does not support providing a qualifier-agnostic +# _defconfig file. +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_BUILD_OUTPUT_UF2=y +CONFIG_CLOCK_CONTROL=y +CONFIG_CONSOLE=y +CONFIG_GPIO=y +CONFIG_RESET=y +CONFIG_SERIAL=y +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=150000000 +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_USE_DT_CODE_PARTITION=y diff --git a/boards/raspberrypi/rpi_pico2/support/openocd.cfg b/boards/raspberrypi/rpi_pico2/support/openocd.cfg new file mode 100644 index 00000000000..82666bb5331 --- /dev/null +++ b/boards/raspberrypi/rpi_pico2/support/openocd.cfg @@ -0,0 +1,11 @@ +# Copyright (c) 2024 TOKITA Hiroshi +# SPDX-License-Identifier: Apache-2.0 + +# Checking and set 'adapter speed'. +# Set the adaptor speed, if unset, and given as an argument. +proc set_adapter_speed_if_not_set { speed } { + puts "checking adapter speed..." + if { [catch {adapter speed} ret] } { + adapter speed $speed + } +} diff --git a/boards/raytac/mdbt50q_db_33/Kconfig.defconfig b/boards/raytac/mdbt50q_db_33/Kconfig.defconfig index bb5e7c4a14d..4b8c325c77d 100644 --- a/boards/raytac/mdbt50q_db_33/Kconfig.defconfig +++ b/boards/raytac/mdbt50q_db_33/Kconfig.defconfig @@ -5,7 +5,4 @@ if BOARD_RAYTAC_MDBT50Q_DB_33 -config BT_CTLR - default BT - endif # BOARD_RAYTAC_MDBT50Q_DB_33 diff --git a/boards/raytac/mdbt50q_db_33/doc/index.rst b/boards/raytac/mdbt50q_db_33/doc/index.rst index 8089b7b5e48..fe10186965e 100644 --- a/boards/raytac/mdbt50q_db_33/doc/index.rst +++ b/boards/raytac/mdbt50q_db_33/doc/index.rst @@ -1,7 +1,4 @@ -.. _raytac_mdbt50q_db_33_nrf52833: - -Raytac MDBT50Q-DB-33 -#################### +.. zephyr:board:: raytac_mdbt50q_db_33 Overview ******** @@ -25,11 +22,6 @@ Nordic Semiconductor nRF52833 ARM Cortex-M4F CPU and the following devices: * :abbr:`USB (Universal Serial Bus)` * :abbr:`WDT (Watchdog Timer)` -.. figure:: img/mdbt50q_db_33.jpg - :width: 442px - :align: center - :alt: MDBT50Q-DB-33 - More information about the board can be found at the `MDBT50Q-DB-33 website`_. The `MDBT50Q-DB-33 Specification`_ contains the demo board's datasheet. The `MDBT50Q-DB-33 Schematic`_ contains the demo board's schematic. diff --git a/boards/raytac/mdbt50q_db_40/Kconfig.defconfig b/boards/raytac/mdbt50q_db_40/Kconfig.defconfig index 2919530e87c..b88aa0342fe 100644 --- a/boards/raytac/mdbt50q_db_40/Kconfig.defconfig +++ b/boards/raytac/mdbt50q_db_40/Kconfig.defconfig @@ -5,7 +5,4 @@ if BOARD_RAYTAC_MDBT50Q_DB_40 -config BT_CTLR - default BT - endif # BOARD_RAYTAC_MDBT50Q_DB_40 diff --git a/boards/raytac/mdbt50q_db_40/doc/index.rst b/boards/raytac/mdbt50q_db_40/doc/index.rst index 269b42bb9d5..5655d41e229 100644 --- a/boards/raytac/mdbt50q_db_40/doc/index.rst +++ b/boards/raytac/mdbt50q_db_40/doc/index.rst @@ -1,7 +1,4 @@ -.. _raytac_mdbt50q_db_40_nrf52840: - -Raytac MDBT50Q-DB-40 -#################### +.. zephyr:board:: raytac_mdbt50q_db_40 Overview ******** @@ -25,11 +22,6 @@ Nordic Semiconductor nRF52840 ARM Cortex-M4F CPU and the following devices: * :abbr:`USB (Universal Serial Bus)` * :abbr:`WDT (Watchdog Timer)` -.. figure:: img/mdbt50q_db_40.jpg - :width: 442px - :align: center - :alt: MDBT50Q-DB-40 - More information about the board can be found at the `MDBT50Q-DB-40 website`_. The `MDBT50Q-DB-40 Specification`_ contains the demo board's datasheet. The `MDBT50Q-DB-40 Schematic`_ contains the demo board's schematic. diff --git a/boards/raytac/mdbt53_db_40/Kconfig.defconfig b/boards/raytac/mdbt53_db_40/Kconfig.defconfig index dbbe13da493..40ae18ba31b 100644 --- a/boards/raytac/mdbt53_db_40/Kconfig.defconfig +++ b/boards/raytac/mdbt53_db_40/Kconfig.defconfig @@ -64,7 +64,4 @@ endif # BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP || BOARD_RAYTAC_MDBT53_DB_40_NR if BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUNET -config BT_CTLR - default y if BT - endif # BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUNET diff --git a/boards/raytac/mdbt53_db_40/doc/index.rst b/boards/raytac/mdbt53_db_40/doc/index.rst index 9ddb5b77c5d..a429f7b1881 100644 --- a/boards/raytac/mdbt53_db_40/doc/index.rst +++ b/boards/raytac/mdbt53_db_40/doc/index.rst @@ -1,7 +1,4 @@ -.. _raytac_mdbt53_db_40_nrf5340: - -Raytac MDBT53-DB-40 -################### +.. zephyr:board:: raytac_mdbt53_db_40 Overview ******** @@ -43,13 +40,6 @@ nRF5340 SoC provides support for the following devices: * :abbr:`UARTE (Universal asynchronous receiver-transmitter)` * :abbr:`WDT (Watchdog Timer)` -.. figure:: img/MDBT53-DB-40.jpg - :width: 442px - :align: center - :alt: MDBT53-DB-40 - - MDBT53-DB-40 (Credit: Raytac Corporation) - More information about the board can be found at the `MDBT53-DB-40 website`_. The `MDBT53-DB-40 Specification`_ contains the demo board's datasheet. The `MDBT53-DB-40 Schematic`_ contains the demo board's schematic. @@ -259,6 +249,8 @@ boards with a Segger IC. References ********** +.. target-notes:: + .. _IDAU: https://developer.arm.com/docs/100690/latest/attribution-units-sau-and-idau .. _MDBT53-DB-40 website: diff --git a/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp_common.dts b/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp_common.dts index bd89fa1664f..0db7bc0f933 100644 --- a/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp_common.dts +++ b/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp_common.dts @@ -108,6 +108,11 @@ status = "okay"; }; +&lfxo { + load-capacitors = "internal"; + load-capacitance-picofarad = <7>; +}; + &adc { status = "okay"; }; diff --git a/boards/raytac/mdbt53v_db_40/Kconfig.defconfig b/boards/raytac/mdbt53v_db_40/Kconfig.defconfig index b3f4fb77c5b..61e7592cc66 100644 --- a/boards/raytac/mdbt53v_db_40/Kconfig.defconfig +++ b/boards/raytac/mdbt53v_db_40/Kconfig.defconfig @@ -64,7 +64,4 @@ endif # BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP || BOARD_RAYTAC_MDBT53V_DB_40_ if BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUNET -config BT_CTLR - default y if BT - endif # BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUNET diff --git a/boards/raytac/mdbt53v_db_40/doc/index.rst b/boards/raytac/mdbt53v_db_40/doc/index.rst index 27a2aeee345..834971e7c7d 100644 --- a/boards/raytac/mdbt53v_db_40/doc/index.rst +++ b/boards/raytac/mdbt53v_db_40/doc/index.rst @@ -1,7 +1,4 @@ -.. _raytac_mdbt53v_db_40_nrf5340: - -Raytac MDBT53V-DB-40 -#################### +.. zephyr:board:: raytac_mdbt53v_db_40 Overview ******** @@ -42,13 +39,6 @@ nRF5340 SoC provides support for the following devices: * :abbr:`UARTE (Universal asynchronous receiver-transmitter)` * :abbr:`WDT (Watchdog Timer)` -.. figure:: img/MDBT53V-DB-40.jpg - :width: 442px - :align: center - :alt: MDBT53V-DB-40 - - MDBT53V-DB-40 (Credit: Raytac Corporation) - More information about the board can be found at the `MDBT53V-DB-40 website`_. The `MDBT53V-DB-40 Specification`_ contains the demo board's datasheet. The `MDBT53V-DB-40 Schematic`_ contains the demo board's schematic. @@ -249,6 +239,8 @@ J-Link OB IF to debug. References ********** +.. target-notes:: + .. _IDAU: https://developer.arm.com/docs/100690/latest/attribution-units-sau-and-idau .. _MDBT53V-DB-40 website: diff --git a/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp_common.dts b/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp_common.dts index 71811564df1..add880e3518 100644 --- a/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp_common.dts +++ b/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp_common.dts @@ -87,6 +87,11 @@ status = "okay"; }; +&lfxo { + load-capacitors = "internal"; + load-capacitance-picofarad = <7>; +}; + &adc { status = "okay"; }; diff --git a/boards/renesas/da14695_dk_usb/da14695_dk_usb-pinctrl.dtsi b/boards/renesas/da14695_dk_usb/da14695_dk_usb-pinctrl.dtsi index fbdf787a88e..521c90da0df 100644 --- a/boards/renesas/da14695_dk_usb/da14695_dk_usb-pinctrl.dtsi +++ b/boards/renesas/da14695_dk_usb/da14695_dk_usb-pinctrl.dtsi @@ -18,20 +18,20 @@ uart2_default: uart2_default { group1 { - pinmux = ; + pinmux = ; }; group2 { - pinmux = ; + pinmux = ; bias-pull-up; }; }; uart3_default: uart3_default { group1 { - pinmux = ; + pinmux = ; }; group2 { - pinmux = ; + pinmux = ; bias-pull-up; }; }; @@ -63,8 +63,8 @@ /omit-if-no-ref/ i2c2_sleep: i2c2_sleep { group1 { - pinmux = , - ; + pinmux = , + ; bias-pull-up; }; }; diff --git a/boards/renesas/da14695_dk_usb/da14695_dk_usb.dts b/boards/renesas/da14695_dk_usb/da14695_dk_usb.dts index 0c38c829db1..96c241aa9d1 100644 --- a/boards/renesas/da14695_dk_usb/da14695_dk_usb.dts +++ b/boards/renesas/da14695_dk_usb/da14695_dk_usb.dts @@ -38,51 +38,50 @@ }; }; - mikrobus_header{ - mikrobus-connector-1 { - compatible = "mikro-bus"; - #gpio-cells = <2>; - gpio-map-mask = <0xffffffff 0xffffffc0>; - gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpio0 25 0>, /* AN */ - /* Not a GPIO*/ /* RST */ - <2 0 &gpio1 2 0>, /* CS */ - <3 0 &gpio1 3 0>, /* SCK */ - <4 0 &gpio1 4 0>, /* MISO */ - <5 0 &gpio1 5 0>, /* MOSI */ - /* +3.3V */ - /* GND */ - <6 0 &gpio1 6 0>, /* PWM */ - <7 0 &gpio1 7 0>, /* INT */ - <8 0 &gpio1 8 0>, /* RX */ - <9 0 &gpio0 17 0>, /* TX */ - <10 0 &gpio0 18 0>, /* SCL */ - <11 0 &gpio0 19 0>; /* SDA */ - /* +5V */ - /* GND */ - }; - mikrobus-connector-2 { - compatible = "mikro-bus"; - #gpio-cells = <2>; - gpio-map-mask = <0xffffffff 0xffffffc0>; - gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpio1 9 0>, /* AN */ - /* Not a GPIO*/ /* RST */ - <2 0 &gpio0 20 0>, /* CS */ - <3 0 &gpio0 21 0>, /* SCK */ - <4 0 &gpio0 24 0>, /* MISO */ - <5 0 &gpio0 26 0>, /* MOSI */ - /* +3.3V */ - /* GND */ - <6 0 &gpio1 1 0>, /* PWM */ - <7 0 &gpio0 27 0>, /* INT */ - <8 0 &gpio0 28 0>, /* RX */ - <9 0 &gpio0 29 0>, /* TX */ - <10 0 &gpio0 30 0>, /* SCL */ - <11 0 &gpio0 31 0>; /* SDA */ - /* +5V */ - /* GND */ - }; + mikrobus_1_header: mikrobus-connector-1 { + compatible = "mikro-bus"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpio1 9 0>, /* AN */ + <1 0 &gpio0 12 0>, /* RST */ + <2 0 &gpio0 20 0>, /* CS */ + <3 0 &gpio0 21 0>, /* SCK */ + <4 0 &gpio0 24 0>, /* MISO */ + <5 0 &gpio0 26 0>, /* MOSI */ + /* +3.3V */ + /* GND */ + <6 0 &gpio1 1 0>, /* PWM */ + <7 0 &gpio0 27 0>, /* INT */ + <8 0 &gpio0 28 0>, /* RX */ + <9 0 &gpio0 29 0>, /* TX */ + <10 0 &gpio0 30 0>, /* SCL */ + <11 0 &gpio0 31 0>; /* SDA */ + /* +5V */ + /* GND */ + }; + + mikrobus_2_header: mikrobus-connector-2 { + compatible = "mikro-bus"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpio0 25 0>, /* AN */ + <1 0 &gpio0 12 0>, /* RST */ + <2 0 &gpio1 2 0>, /* CS */ + <3 0 &gpio1 3 0>, /* SCK */ + <4 0 &gpio1 4 0>, /* MISO */ + <5 0 &gpio1 5 0>, /* MOSI */ + /* +3.3V */ + /* GND */ + <6 0 &gpio1 6 0>, /* PWM */ + <7 0 &gpio1 7 0>, /* INT */ + <8 0 &gpio1 8 0>, /* RX */ + <9 0 &gpio0 17 0>, /* TX */ + <10 0 &gpio0 18 0>, /* SCL */ + <11 0 &gpio0 19 0>; /* SDA */ + /* +5V */ + /* GND */ }; aliases { @@ -118,7 +117,7 @@ label = "image-0"; reg = <0x0000c000 0x00076000>; }; - slot1_partition: partition@80000 { + slot1_partition: partition@82000 { label = "image-1"; reg = <0x00082000 0x00076000>; }; @@ -186,6 +185,7 @@ zephyr_udc0: &usbd { &pll { status = "okay"; }; + &i2c { status = "okay"; pinctrl-0 = <&i2c_default>; @@ -218,10 +218,18 @@ mikrobus_1_i2c: &i2c {}; mikrobus_1_spi: &spi {}; -mikrobus_1_uart: &uart2 {}; +mikrobus_1_uart: &uart3 {}; mikrobus_2_i2c: &i2c2 {}; mikrobus_2_spi: &spi2 {}; -mikrobus_2_uart: &uart3 {}; +mikrobus_2_uart: &uart2 {}; + +mikrobus_i2c: &mikrobus_1_i2c {}; + +mikrobus_spi: &mikrobus_1_spi {}; + +mikrobus_serial: &mikrobus_1_uart {}; + +mikrobus_header: &mikrobus_1_header {}; diff --git a/boards/renesas/da14695_dk_usb/da14695_dk_usb.yaml b/boards/renesas/da14695_dk_usb/da14695_dk_usb.yaml index bc55d5ada4d..b85aee119b6 100644 --- a/boards/renesas/da14695_dk_usb/da14695_dk_usb.yaml +++ b/boards/renesas/da14695_dk_usb/da14695_dk_usb.yaml @@ -8,10 +8,10 @@ toolchain: - gnuarmemb - xtools supported: - - arduino_gpio - gpio - hwinfo - watchdog - i2c - spi - usb_device + - usbd diff --git a/boards/renesas/da1469x_dk_pro/da1469x_dk_pro.dts b/boards/renesas/da1469x_dk_pro/da1469x_dk_pro.dts index f866df49a85..a5c4aa39c4d 100644 --- a/boards/renesas/da1469x_dk_pro/da1469x_dk_pro.dts +++ b/boards/renesas/da1469x_dk_pro/da1469x_dk_pro.dts @@ -6,6 +6,7 @@ /dts-v1/; #include #include "da1469x_dk_pro-pinctrl.dtsi" +#include / { model = "DA1469x series Development Kit Pro"; @@ -33,6 +34,15 @@ }; }; + gpio_keys { + compatible = "gpio-keys"; + user_button: button { + label = "User (K1)"; + gpios = <&gpio0 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + zephyr,code = ; + }; + }; + arduino_header: connector { compatible = "arduino-header-r3"; #gpio-cells = <2>; @@ -66,6 +76,7 @@ aliases { led0 = &red_led; watchdog0 = &wdog; + sw0 = &user_button; }; sysclk: system-clock { @@ -96,7 +107,7 @@ label = "image-0"; reg = <0x0000c000 0x00076000>; }; - slot1_partition: partition@80000 { + slot1_partition: partition@82000 { label = "image-1"; reg = <0x00082000 0x00076000>; }; diff --git a/boards/renesas/da1469x_dk_pro/da1469x_dk_pro.yaml b/boards/renesas/da1469x_dk_pro/da1469x_dk_pro.yaml index 942bfe3e07e..1d988ecbf57 100644 --- a/boards/renesas/da1469x_dk_pro/da1469x_dk_pro.yaml +++ b/boards/renesas/da1469x_dk_pro/da1469x_dk_pro.yaml @@ -22,4 +22,5 @@ supported: - mipi_dbi - display - memc + - usbd vendor: renesas diff --git a/boards/renesas/da1469x_dk_pro/dts/da1469x_dk_pro_lcdc.overlay b/boards/renesas/da1469x_dk_pro/dts/da1469x_dk_pro_lcdc.overlay index 94346ea39e7..61078f2bcca 100644 --- a/boards/renesas/da1469x_dk_pro/dts/da1469x_dk_pro_lcdc.overlay +++ b/boards/renesas/da1469x_dk_pro/dts/da1469x_dk_pro_lcdc.overlay @@ -10,6 +10,7 @@ / { chosen { zephyr,display = &lcdc; + zephyr,touch = &display_touch; }; lvgl_pointer { diff --git a/boards/renesas/da1469x_dk_pro/dts/da1469x_dk_pro_mipi_dbi.overlay b/boards/renesas/da1469x_dk_pro/dts/da1469x_dk_pro_mipi_dbi.overlay index 6612d290f5d..8a2a558fc59 100644 --- a/boards/renesas/da1469x_dk_pro/dts/da1469x_dk_pro_mipi_dbi.overlay +++ b/boards/renesas/da1469x_dk_pro/dts/da1469x_dk_pro_mipi_dbi.overlay @@ -10,6 +10,7 @@ / { chosen { zephyr,display = &ili9340; + zephyr,touch = &display_touch; }; lvgl_pointer { diff --git a/boards/renesas/ek_ra2a1/doc/ek_ra2a1.webp b/boards/renesas/ek_ra2a1/doc/ek_ra2a1.webp new file mode 100644 index 00000000000..6b7e94faafa Binary files /dev/null and b/boards/renesas/ek_ra2a1/doc/ek_ra2a1.webp differ diff --git a/boards/renesas/ek_ra2a1/doc/index.rst b/boards/renesas/ek_ra2a1/doc/index.rst index 060f1627d2c..fd8ebc5e26d 100644 --- a/boards/renesas/ek_ra2a1/doc/index.rst +++ b/boards/renesas/ek_ra2a1/doc/index.rst @@ -31,9 +31,26 @@ Renesas RA2A1 Microcontroller Group has following features - Watchdog Timer - 49 Input/Output pins +.. figure:: ek_ra2a1.webp + :align: center + :alt: RA2A1 Evaluation Kit + + EK-RA2A1 Board Functional Area Definitions (Credit: Renesas Electronics Corporation) + Hardware ******** +Detail Hardware feature for the RA2A1 MCU group can be found at `RA2A1 Group User's Manual Hardware`_ + +.. figure:: ra2a1_block_diagram.webp + :width: 442px + :align: center + :alt: RA2A1 MCU group feature + + RA2A1 Block diagram (Credit: Renesas Electronics Corporation) + +Detail Hardware feature for the EK-RA2A1 MCU can be found at `EK-RA2A1 - User's Manual`_ + EK-RA2A1 has following features. - Native pin access through 4x 40-pin male headers @@ -61,6 +78,16 @@ hardware features: +-----------+------------+-------------------------------+ | UART | on-chip | uart | +-----------+------------+-------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------+ +| COUNTER | on-chip | counter | ++-----------+------------+-------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------+ +| ENTROPY | on-chip | entropy | ++-----------+------------+-------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------+ The default configuration can be found in :zephyr_file:`boards/renesas/ek_ra2a1/ek_ra2a1_defconfig` @@ -74,7 +101,7 @@ Building & Flashing You can build and flash an application with onboard J-Link debug adapter. :ref:`build_an_application` and -:ref:`application_run` for more details). +:ref:`application_run` for more details. Here is an example for building and flashing the :zephyr:code-sample:`blinky` application. @@ -101,5 +128,13 @@ Also, see the instructions specific to the debug server that you use. References ********** +.. target-notes:: + .. EK-RA2A1 Web site: https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ek-ra2a1-evaluation-kit-ra2a1-mcu-group + +.. _RA2A1 Group User's Manual Hardware: + https://www.renesas.com/en/document/mah/renesas-ra2a1-group-users-manual-hardware + +.. _EK-RA2A1 - User's Manual: + https://www.renesas.com/en/document/mah/renesas-ra2a1-group-users-manual-hardware diff --git a/boards/renesas/ek_ra2a1/doc/ra2a1_block_diagram.webp b/boards/renesas/ek_ra2a1/doc/ra2a1_block_diagram.webp new file mode 100644 index 00000000000..9dc118cb5fb Binary files /dev/null and b/boards/renesas/ek_ra2a1/doc/ra2a1_block_diagram.webp differ diff --git a/boards/renesas/ek_ra2a1/ek_ra2a1-pinctrl.dtsi b/boards/renesas/ek_ra2a1/ek_ra2a1-pinctrl.dtsi index cded3e5f655..26835a70ea5 100644 --- a/boards/renesas/ek_ra2a1/ek_ra2a1-pinctrl.dtsi +++ b/boards/renesas/ek_ra2a1/ek_ra2a1-pinctrl.dtsi @@ -16,4 +16,31 @@ drive-strength = "medium"; }; }; + + spi1_default: spi1_default { + group1 { + /* MISO MOSI RSPCK SSL */ + psels = , + , + , + ; + }; + }; + + pwm0_default: pwm0_default { + group1 { + /* GTIOC0A GTIOC0B */ + psels = , + ; + }; + }; + + iic0_default: iic0_default { + group1 { + /* SCL0 SDA0 */ + psels = , + ; + drive-strength = "medium"; + }; + }; }; diff --git a/boards/renesas/ek_ra2a1/ek_ra2a1.dts b/boards/renesas/ek_ra2a1/ek_ra2a1.dts index eb14660f8ac..f0040a3fd6d 100644 --- a/boards/renesas/ek_ra2a1/ek_ra2a1.dts +++ b/boards/renesas/ek_ra2a1/ek_ra2a1.dts @@ -7,6 +7,7 @@ #include #include +#include #include "ek_ra2a1-pinctrl.dtsi" @@ -19,6 +20,7 @@ zephyr,flash = &flash0; zephyr,console = &uart0; zephyr,shell-uart = &uart0; + zephyr,entropy = &trng; }; leds { @@ -29,8 +31,18 @@ }; }; + buttons { + compatible = "gpio-keys"; + button0: s1 { + gpios = <&ioport2 6 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button switch 1"; + zephyr,code = ; + }; + }; + aliases { led0 = &led1; + sw0 = &button0; }; }; @@ -58,3 +70,42 @@ status = "okay"; }; }; + +&spi1 { + pinctrl-0 = <&spi1_default>; + pinctrl-names = "default"; + cs-gpios = <&ioport1 2 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&ioport1 { + status = "okay"; +}; + +&port_irq6 { + interrupts = <29 3>; + status = "okay"; +}; + +&pwm0 { + pinctrl-0 = <&pwm0_default>; + pinctrl-names = "default"; + interrupts = <28 1>, <31 1>; + interrupt-names = "gtioca", "overflow"; + status = "okay"; +}; + +&trng { + status = "okay"; +}; + +&iic0 { + pinctrl-0 = <&iic0_default>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = ; + interrupts = <0 1>, <1 1>, <2 1>, <3 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + status = "okay"; +}; diff --git a/boards/renesas/ek_ra2a1/ek_ra2a1_defconfig b/boards/renesas/ek_ra2a1/ek_ra2a1_defconfig index 6058aa5eb98..85bd6dcd455 100644 --- a/boards/renesas/ek_ra2a1/ek_ra2a1_defconfig +++ b/boards/renesas/ek_ra2a1/ek_ra2a1_defconfig @@ -5,7 +5,6 @@ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=48000000 # Enable GPIO CONFIG_GPIO=y -CONFIG_PINCTRL=y # Enable Console CONFIG_SERIAL=y @@ -14,5 +13,4 @@ CONFIG_UART_INTERRUPT_DRIVEN=y CONFIG_CONSOLE=y CONFIG_BUILD_OUTPUT_HEX=y -CONFIG_BUILD_NO_GAP_FILL=y CONFIG_CLOCK_CONTROL=y diff --git a/boards/renesas/ek_ra4e2/doc/ek-ra4e2-board.webp b/boards/renesas/ek_ra4e2/doc/ek_ra4e2.webp similarity index 100% rename from boards/renesas/ek_ra4e2/doc/ek-ra4e2-board.webp rename to boards/renesas/ek_ra4e2/doc/ek_ra4e2.webp diff --git a/boards/renesas/ek_ra4e2/doc/index.rst b/boards/renesas/ek_ra4e2/doc/index.rst index 0bf90ed5464..8b2c7312140 100644 --- a/boards/renesas/ek_ra4e2/doc/index.rst +++ b/boards/renesas/ek_ra4e2/doc/index.rst @@ -61,7 +61,7 @@ RA MCU - CAN FD (3-pin header) -.. figure:: ek-ra4e2-board.webp +.. figure:: ek_ra4e2.webp :align: center :alt: RA4E2 Evaluation Kit @@ -71,7 +71,7 @@ Hardware ******** Detail Hardware feature for the RA4E2 MCU group can be found at `RA4E2 Group User's Manual Hardware`_ -.. figure:: ra4e2-block-diagram.webp +.. figure:: ra4e2_block_diagram.webp :width: 442px :align: center :alt: RA4E2 MCU group feature @@ -98,6 +98,16 @@ The below features are currently supported on Zephyr OS for EK-RA4E2 board: +-----------+------------+----------------------+ | CLOCK | on-chip | clock control | +-----------+------------+----------------------+ +| SPI | on-chip | spi | ++-----------+------------+----------------------+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| ENTROPY | on-chip | entropy | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ Other hardware features are currently not supported by the port. diff --git a/boards/renesas/ek_ra4e2/doc/ra4e2-block-diagram.webp b/boards/renesas/ek_ra4e2/doc/ra4e2_block_diagram.webp similarity index 100% rename from boards/renesas/ek_ra4e2/doc/ra4e2-block-diagram.webp rename to boards/renesas/ek_ra4e2/doc/ra4e2_block_diagram.webp diff --git a/boards/renesas/ek_ra4e2/ek_ra4e2-pinctrl.dtsi b/boards/renesas/ek_ra4e2/ek_ra4e2-pinctrl.dtsi index 851d8543bee..4fa94b5c08d 100644 --- a/boards/renesas/ek_ra4e2/ek_ra4e2-pinctrl.dtsi +++ b/boards/renesas/ek_ra4e2/ek_ra4e2-pinctrl.dtsi @@ -11,4 +11,39 @@ ; }; }; + + spi0_default: spi0_default { + group1 { + /* MISO MOSI RSPCK SSL */ + psels = , + , + , + ; + }; + }; + + canfd0_default: canfd0_default { + group1 { + /* CRX0 CTX0 */ + psels = , + ; + drive-strength = "high"; + }; + }; + + adc0_default: adc0_default { + group1 { + /* input */ + psels = ; + renesas,analog-enable; + }; + }; + + pwm1_default: pwm1_default { + group1 { + /* GTIOC1A GTIOC1B */ + psels = , + ; + }; + }; }; diff --git a/boards/renesas/ek_ra4e2/ek_ra4e2.dts b/boards/renesas/ek_ra4e2/ek_ra4e2.dts index e371198e6ed..c5065f16f76 100644 --- a/boards/renesas/ek_ra4e2/ek_ra4e2.dts +++ b/boards/renesas/ek_ra4e2/ek_ra4e2.dts @@ -7,6 +7,8 @@ #include #include +#include +#include #include "ek_ra4e2-pinctrl.dtsi" / { @@ -15,9 +17,12 @@ chosen { zephyr,sram = &sram0; + zephyr,flash-controller = &flash1; zephyr,flash = &flash0; zephyr,console = &uart0; zephyr,shell-uart = &uart0; + zephyr,canbus = &canfd0; + zephyr,entropy = &trng; }; leds { @@ -36,8 +41,31 @@ }; }; + buttons { + compatible = "gpio-keys"; + button0: s1 { + gpios = <&ioport0 5 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button switch 1"; + zephyr,code = ; + }; + button1: s2 { + gpios = <&ioport3 4 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button switch 2"; + zephyr,code = ; + }; + }; + aliases { led0 = &led1; + sw0 = &button0; + sw1 = &button1; + }; + + transceiver0: can-phy0 { + compatible = "nxp,tja1043t", "can-transceiver-gpio"; + standby-gpios = <&ioport4 0 GPIO_ACTIVE_LOW>; + max-bitrate = <5000000>; + #phy-cells = <0>; }; }; @@ -53,8 +81,8 @@ }; &pll { - source = ; - div = ; + clocks = <&xtal>; + div = <1>; mul = <10 0>; status = "okay"; }; @@ -69,6 +97,10 @@ }; }; +&ioport0 { + status = "okay"; +}; + &ioport1 { status = "okay"; }; @@ -76,3 +108,76 @@ &ioport2 { status = "okay"; }; + +&spi0 { + pinctrl-0 = <&spi0_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&ioport4 { + status = "okay"; +}; + +&canfdclk { + clocks = <&pll>; + div = <8>; + status = "okay"; +}; + +&canfd_global { + status = "okay"; + canfd0 { + pinctrl-0 = <&canfd0_default>; + pinctrl-names = "default"; + phys = <&transceiver0>; + rx-max-filters = <16>; + status = "okay"; + }; +}; + +&adc0 { + status = "okay"; + pinctrl-0 = <&adc0_default>; + pinctrl-names = "default"; +}; + +&ioport3 { + status = "okay"; +}; + +&port_irq9 { + interrupts = <4 12>; + status = "okay"; +}; + +&port_irq10 { + interrupts = <5 12>; + status = "okay"; +}; + +&pwm1 { + pinctrl-0 = <&pwm1_default>; + pinctrl-names = "default"; + interrupts = <63 1>, <64 1>; + interrupt-names = "gtioca", "overflow"; + divider = ; + status = "okay"; +}; + +&trng { + status = "okay"; +}; + +&flash1 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + storage_partition: partition@0 { + label = "storage"; + reg = <0X0 DT_SIZE_K(4)>; + }; + }; +}; diff --git a/boards/renesas/ek_ra4e2/ek_ra4e2_defconfig b/boards/renesas/ek_ra4e2/ek_ra4e2_defconfig index ceaa9b32580..93569c968fc 100644 --- a/boards/renesas/ek_ra4e2/ek_ra4e2_defconfig +++ b/boards/renesas/ek_ra4e2/ek_ra4e2_defconfig @@ -5,7 +5,6 @@ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=100000000 # Enable GPIO CONFIG_GPIO=y -CONFIG_PINCTRL=y # Enable Console CONFIG_SERIAL=y @@ -14,5 +13,4 @@ CONFIG_UART_CONSOLE=y CONFIG_CONSOLE=y CONFIG_BUILD_OUTPUT_HEX=y -CONFIG_BUILD_NO_GAP_FILL=y CONFIG_CLOCK_CONTROL=y diff --git a/boards/renesas/ek_ra4m2/doc/ek-ra4m2-board.webp b/boards/renesas/ek_ra4m2/doc/ek_ra4m2.webp similarity index 100% rename from boards/renesas/ek_ra4m2/doc/ek-ra4m2-board.webp rename to boards/renesas/ek_ra4m2/doc/ek_ra4m2.webp diff --git a/boards/renesas/ek_ra4m2/doc/index.rst b/boards/renesas/ek_ra4m2/doc/index.rst index 833768d6d16..08025a1836f 100644 --- a/boards/renesas/ek_ra4m2/doc/index.rst +++ b/boards/renesas/ek_ra4m2/doc/index.rst @@ -61,7 +61,7 @@ available internal to the RA MCU **Special Feature Access** - 32 MB (256 Mb) External Quad-SPI Flash -.. figure:: ek-ra4m2-board.webp +.. figure:: ek_ra4m2.webp :align: center :alt: RA4M2 Evaluation Kit @@ -71,7 +71,7 @@ Hardware ******** Detail Hardware feature for the RA4M2 MCU group can be found at `RA4M2 Group User's Manual Hardware`_ -.. figure:: ra4m2-block-diagram.webp +.. figure:: ra4m2_block_diagram.webp :width: 442px :align: center :alt: RA4M2 MCU group feature @@ -98,6 +98,18 @@ The below features are currently supported on Zephyr OS for EK-RA4M2 board: +-----------+------------+----------------------+ | CLOCK | on-chip | clock control | +-----------+------------+----------------------+ +| SPI | on-chip | spi | ++-----------+------------+----------------------+ +| COUNTER | on-chip | counter | ++-----------+------------+----------------------+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| I2C | on-chip | i2c | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ Other hardware features are currently not supported by the port. diff --git a/boards/renesas/ek_ra4m2/doc/ra4m2-block-diagram.webp b/boards/renesas/ek_ra4m2/doc/ra4m2_block_diagram.webp similarity index 100% rename from boards/renesas/ek_ra4m2/doc/ra4m2-block-diagram.webp rename to boards/renesas/ek_ra4m2/doc/ra4m2_block_diagram.webp diff --git a/boards/renesas/ek_ra4m2/ek_ra4m2-pinctrl.dtsi b/boards/renesas/ek_ra4m2/ek_ra4m2-pinctrl.dtsi index 851d8543bee..cd65bed269b 100644 --- a/boards/renesas/ek_ra4m2/ek_ra4m2-pinctrl.dtsi +++ b/boards/renesas/ek_ra4m2/ek_ra4m2-pinctrl.dtsi @@ -11,4 +11,39 @@ ; }; }; + + spi0_default: spi0_default { + group1 { + /* MISO MOSI RSPCK SSL */ + psels = , + , + , + ; + }; + }; + + adc0_default: adc0_default { + group1 { + /* input */ + psels = ; + renesas,analog-enable; + }; + }; + + pwm1_default: pwm1_default { + group1 { + /* GTIOC1A GTIOC1B */ + psels = , + ; + }; + }; + + iic0_default: iic0_default { + group1 { + /* SCL0 SDA0 */ + psels = , + ; + drive-strength = "medium"; + }; + }; }; diff --git a/boards/renesas/ek_ra4m2/ek_ra4m2.dts b/boards/renesas/ek_ra4m2/ek_ra4m2.dts index 49f35db2e83..23e7c573ad1 100644 --- a/boards/renesas/ek_ra4m2/ek_ra4m2.dts +++ b/boards/renesas/ek_ra4m2/ek_ra4m2.dts @@ -7,6 +7,8 @@ #include #include +#include +#include #include "ek_ra4m2-pinctrl.dtsi" / { @@ -15,6 +17,7 @@ chosen { zephyr,sram = &sram0; + zephyr,flash-controller = &flash1; zephyr,flash = &flash0; zephyr,console = &uart0; zephyr,shell-uart = &uart0; @@ -36,8 +39,24 @@ }; }; + buttons { + compatible = "gpio-keys"; + button0: s1 { + gpios = <&ioport0 5 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button switch 1"; + zephyr,code = ; + }; + button1: s2 { + gpios = <&ioport0 6 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button switch 2"; + zephyr,code = ; + }; + }; + aliases { led0 = &led1; + sw0 = &button0; + sw1 = &button1; }; }; @@ -53,8 +72,8 @@ }; &pll { - source = ; - div = ; + clocks = <&xtal>; + div = <3>; mul = <25 0>; status = "okay"; }; @@ -69,6 +88,64 @@ }; }; +&ioport0 { + status = "okay"; +}; + &ioport4 { status = "okay"; }; + +&spi0 { + pinctrl-0 = <&spi0_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&adc0 { + status = "okay"; + pinctrl-0 = <&adc0_default>; + pinctrl-names = "default"; +}; + +&port_irq10 { + interrupts = <41 12>; + status = "okay"; +}; + +&port_irq11 { + interrupts = <42 12>; + status = "okay"; +}; + +&pwm1 { + pinctrl-0 = <&pwm1_default>; + pinctrl-names = "default"; + interrupts = <63 1>, <64 1>; + interrupt-names = "gtioca", "overflow"; + status = "okay"; +}; + +&iic0 { + pinctrl-0 = <&iic0_default>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = ; + interrupts = <87 1>, <88 1>, <89 1>, <90 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + status = "okay"; +}; + +&flash1 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + storage_partition: partition@0 { + label = "storage"; + reg = <0X0 DT_SIZE_K(8)>; + }; + }; +}; diff --git a/boards/renesas/ek_ra4m2/ek_ra4m2_defconfig b/boards/renesas/ek_ra4m2/ek_ra4m2_defconfig index ceaa9b32580..93569c968fc 100644 --- a/boards/renesas/ek_ra4m2/ek_ra4m2_defconfig +++ b/boards/renesas/ek_ra4m2/ek_ra4m2_defconfig @@ -5,7 +5,6 @@ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=100000000 # Enable GPIO CONFIG_GPIO=y -CONFIG_PINCTRL=y # Enable Console CONFIG_SERIAL=y @@ -14,5 +13,4 @@ CONFIG_UART_CONSOLE=y CONFIG_CONSOLE=y CONFIG_BUILD_OUTPUT_HEX=y -CONFIG_BUILD_NO_GAP_FILL=y CONFIG_CLOCK_CONTROL=y diff --git a/boards/renesas/ek_ra4m3/doc/ek-ra4m3-board.webp b/boards/renesas/ek_ra4m3/doc/ek_ra4m3.webp similarity index 100% rename from boards/renesas/ek_ra4m3/doc/ek-ra4m3-board.webp rename to boards/renesas/ek_ra4m3/doc/ek_ra4m3.webp diff --git a/boards/renesas/ek_ra4m3/doc/index.rst b/boards/renesas/ek_ra4m3/doc/index.rst index 07db2061617..fc96aade862 100644 --- a/boards/renesas/ek_ra4m3/doc/index.rst +++ b/boards/renesas/ek_ra4m3/doc/index.rst @@ -63,7 +63,7 @@ RA MCU **Special Feature Access** - 32 MB (256 Mb) External Quad-SPI Flash -.. figure:: ek-ra4m3-board.webp +.. figure:: ek_ra4m3.webp :align: center :alt: RA4M3 Evaluation Kit @@ -73,7 +73,7 @@ Hardware ******** Detail Hardware feature for the RA4M3 MCU group can be found at `RA4M3 Group User's Manual Hardware`_ -.. figure:: ra4m3-block-diagram.webp +.. figure:: ra4m3_block_diagram.webp :width: 442px :align: center :alt: RA4M3 MCU group feature @@ -100,6 +100,18 @@ The below features are currently supported on Zephyr OS for EK-RA4M3 board: +-----------+------------+----------------------+ | CLOCK | on-chip | clock control | +-----------+------------+----------------------+ +| SPI | on-chip | spi | ++-----------+------------+----------------------+ +| COUNTER | on-chip | counter | ++-----------+------------+----------------------+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| I2C | on-chip | i2c | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ Other hardware features are currently not supported by the port. diff --git a/boards/renesas/ek_ra4m3/doc/ra4m3-block-diagram.webp b/boards/renesas/ek_ra4m3/doc/ra4m3_block_diagram.webp similarity index 100% rename from boards/renesas/ek_ra4m3/doc/ra4m3-block-diagram.webp rename to boards/renesas/ek_ra4m3/doc/ra4m3_block_diagram.webp diff --git a/boards/renesas/ek_ra4m3/ek_ra4m3-pinctrl.dtsi b/boards/renesas/ek_ra4m3/ek_ra4m3-pinctrl.dtsi index 851d8543bee..93f63b5a56a 100644 --- a/boards/renesas/ek_ra4m3/ek_ra4m3-pinctrl.dtsi +++ b/boards/renesas/ek_ra4m3/ek_ra4m3-pinctrl.dtsi @@ -11,4 +11,39 @@ ; }; }; + + spi0_default: spi0_default { + group1 { + /* MISO MOSI RSPCK SSL */ + psels = , + , + , + ; + }; + }; + + adc0_default: adc0_default { + group1 { + /* input */ + psels = ; + renesas,analog-enable; + }; + }; + + pwm1_default: pwm1_default { + group1 { + /* GTIOC1A GTIOC1B */ + psels = , + ; + }; + }; + + iic0_default: iic0_default { + group1 { + /* SCL0 SDA0 */ + psels = , + ; + drive-strength = "medium"; + }; + }; }; diff --git a/boards/renesas/ek_ra4m3/ek_ra4m3.dts b/boards/renesas/ek_ra4m3/ek_ra4m3.dts index f076510018e..05b258b3652 100644 --- a/boards/renesas/ek_ra4m3/ek_ra4m3.dts +++ b/boards/renesas/ek_ra4m3/ek_ra4m3.dts @@ -7,6 +7,8 @@ #include #include +#include +#include #include "ek_ra4m3-pinctrl.dtsi" / { @@ -15,6 +17,7 @@ chosen { zephyr,sram = &sram0; + zephyr,flash-controller = &flash1; zephyr,flash = &flash0; zephyr,console = &uart0; zephyr,shell-uart = &uart0; @@ -36,8 +39,24 @@ }; }; + buttons { + compatible = "gpio-keys"; + button0: s1 { + gpios = <&ioport0 5 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button switch 1"; + zephyr,code = ; + }; + button1: s2 { + gpios = <&ioport0 6 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button switch 2"; + zephyr,code = ; + }; + }; + aliases { led0 = &led1; + sw0 = &button0; + sw1 = &button1; }; }; @@ -53,8 +72,8 @@ }; &pll { - source = ; - div = ; + clocks = <&xtal>; + div = <3>; mul = <25 0>; status = "okay"; }; @@ -69,6 +88,64 @@ }; }; +&ioport0 { + status = "okay"; +}; + &ioport4 { status = "okay"; }; + +&spi0 { + pinctrl-0 = <&spi0_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&adc0 { + status = "okay"; + pinctrl-0 = <&adc0_default>; + pinctrl-names = "default"; +}; + +&port_irq10 { + interrupts = <41 12>; + status = "okay"; +}; + +&port_irq11 { + interrupts = <42 12>; + status = "okay"; +}; + +&pwm1 { + pinctrl-0 = <&pwm1_default>; + pinctrl-names = "default"; + interrupts = <63 1>, <64 1>; + interrupt-names = "gtioca", "overflow"; + status = "okay"; +}; + +&iic0 { + pinctrl-0 = <&iic0_default>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = ; + interrupts = <87 1>, <88 1>, <89 1>, <90 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + status = "okay"; +}; + +&flash1 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + storage_partition: partition@0 { + label = "storage"; + reg = <0X0 DT_SIZE_K(8)>; + }; + }; +}; diff --git a/boards/renesas/ek_ra4m3/ek_ra4m3_defconfig b/boards/renesas/ek_ra4m3/ek_ra4m3_defconfig index ceaa9b32580..93569c968fc 100644 --- a/boards/renesas/ek_ra4m3/ek_ra4m3_defconfig +++ b/boards/renesas/ek_ra4m3/ek_ra4m3_defconfig @@ -5,7 +5,6 @@ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=100000000 # Enable GPIO CONFIG_GPIO=y -CONFIG_PINCTRL=y # Enable Console CONFIG_SERIAL=y @@ -14,5 +13,4 @@ CONFIG_UART_CONSOLE=y CONFIG_CONSOLE=y CONFIG_BUILD_OUTPUT_HEX=y -CONFIG_BUILD_NO_GAP_FILL=y CONFIG_CLOCK_CONTROL=y diff --git a/boards/renesas/ek_ra4w1/doc/ek-ra4w1-board.webp b/boards/renesas/ek_ra4w1/doc/ek_ra4w1.webp similarity index 100% rename from boards/renesas/ek_ra4w1/doc/ek-ra4w1-board.webp rename to boards/renesas/ek_ra4w1/doc/ek_ra4w1.webp diff --git a/boards/renesas/ek_ra4w1/doc/index.rst b/boards/renesas/ek_ra4w1/doc/index.rst index d20c5c27390..c9501e3dc1d 100644 --- a/boards/renesas/ek_ra4w1/doc/index.rst +++ b/boards/renesas/ek_ra4w1/doc/index.rst @@ -53,7 +53,7 @@ embedded RAM and low power consumption. - Emulator reset switch -.. figure:: ek-ra4w1-board.webp +.. figure:: ek_ra4w1.webp :align: center :alt: RA4W1 Evaluation Kit @@ -63,7 +63,7 @@ Hardware ******** Detail Hardware feature for the RA4W1 MCU group can be found at `RA4W1 Group User's Manual Hardware`_ -.. figure:: ra4w1-block-diagram.webp +.. figure:: ra4w1_block_diagram.webp :width: 442px :align: center :alt: RA4W1 MCU group feature @@ -90,6 +90,18 @@ The below features are currently supported on Zephyr OS for EK-RA4W1 board: +-----------+------------+----------------------+ | CLOCK | on-chip | clock control | +-----------+------------+----------------------+ +| SPI | on-chip | spi | ++-----------+------------+----------------------+ +| COUNTER | on-chip | counter | ++-----------+------------+----------------------+ +| ENTROPY | on-chip | entropy | ++-----------+------------+----------------------+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| I2C | on-chip | i2c | ++-----------+------------+----------------------+ Other hardware features are currently not supported by the port. diff --git a/boards/renesas/ek_ra4w1/doc/ra4w1-block-diagram.webp b/boards/renesas/ek_ra4w1/doc/ra4w1_block_diagram.webp similarity index 100% rename from boards/renesas/ek_ra4w1/doc/ra4w1-block-diagram.webp rename to boards/renesas/ek_ra4w1/doc/ra4w1_block_diagram.webp diff --git a/boards/renesas/ek_ra4w1/ek_ra4w1-pinctrl.dtsi b/boards/renesas/ek_ra4w1/ek_ra4w1-pinctrl.dtsi index 3c01cb6bec4..f0b48f12f95 100644 --- a/boards/renesas/ek_ra4w1/ek_ra4w1-pinctrl.dtsi +++ b/boards/renesas/ek_ra4w1/ek_ra4w1-pinctrl.dtsi @@ -11,4 +11,39 @@ ; }; }; + + spi1_default: spi1_default { + group1 { + /* MISO MOSI RSPCK SSL */ + psels = , + , + , + ; + }; + }; + + adc0_default: adc0_default { + group1 { + /* input */ + psels = ; + renesas,analog-enable; + }; + }; + + pwm1_default: pwm1_default { + group1 { + /* GTIOC1A GTIOC1B */ + psels = , + ; + }; + }; + + iic0_default: iic0_default { + group1 { + /* SCL0 SDA0 */ + psels = , + ; + drive-strength = "medium"; + }; + }; }; diff --git a/boards/renesas/ek_ra4w1/ek_ra4w1.dts b/boards/renesas/ek_ra4w1/ek_ra4w1.dts index 7d764631e03..a8adbfd99a1 100644 --- a/boards/renesas/ek_ra4w1/ek_ra4w1.dts +++ b/boards/renesas/ek_ra4w1/ek_ra4w1.dts @@ -7,6 +7,8 @@ #include #include +#include +#include #include "ek_ra4w1-pinctrl.dtsi" / { @@ -18,6 +20,7 @@ zephyr,flash = &flash0; zephyr,console = &uart0; zephyr,shell-uart = &uart0; + zephyr,entropy = &trng; }; leds { @@ -33,8 +36,18 @@ }; }; + buttons { + compatible = "gpio-keys"; + button0: s1 { + gpios = <&ioport4 2 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button switch 1"; + zephyr,code = ; + }; + }; + aliases { led0 = &led1; + sw0 = &button0; }; }; @@ -59,3 +72,43 @@ &ioport4 { status = "okay"; }; + +&spi1 { + pinctrl-0 = <&spi1_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&trng { + status = "okay"; +}; + +&adc0 { + status = "okay"; + pinctrl-0 = <&adc0_default>; + pinctrl-names = "default"; +}; + +&port_irq4 { + interrupts = <31 12>; + status = "okay"; +}; + +&pwm1 { + pinctrl-0 = <&pwm1_default>; + pinctrl-names = "default"; + interrupts = <8 1>, <9 1>; + interrupt-names = "gtioca", "overflow"; + status = "okay"; +}; + +&iic0 { + pinctrl-0 = <&iic0_default>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = ; + interrupts = <10 1>, <11 1>, <12 1>, <13 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + status = "okay"; +}; diff --git a/boards/renesas/ek_ra4w1/ek_ra4w1_defconfig b/boards/renesas/ek_ra4w1/ek_ra4w1_defconfig index 92542b8ab9c..631c90786a6 100644 --- a/boards/renesas/ek_ra4w1/ek_ra4w1_defconfig +++ b/boards/renesas/ek_ra4w1/ek_ra4w1_defconfig @@ -5,7 +5,6 @@ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=32000000 # Enable GPIO CONFIG_GPIO=y -CONFIG_PINCTRL=y # Enable Console CONFIG_SERIAL=y @@ -14,5 +13,4 @@ CONFIG_UART_CONSOLE=y CONFIG_CONSOLE=y CONFIG_BUILD_OUTPUT_HEX=y -CONFIG_BUILD_NO_GAP_FILL=y CONFIG_CLOCK_CONTROL=y diff --git a/boards/renesas/ek_ra6e2/doc/ek-ra6e2-board.webp b/boards/renesas/ek_ra6e2/doc/ek_ra6e2.webp similarity index 100% rename from boards/renesas/ek_ra6e2/doc/ek-ra6e2-board.webp rename to boards/renesas/ek_ra6e2/doc/ek_ra6e2.webp diff --git a/boards/renesas/ek_ra6e2/doc/index.rst b/boards/renesas/ek_ra6e2/doc/index.rst index aad21a93ea4..46fb121cc82 100644 --- a/boards/renesas/ek_ra6e2/doc/index.rst +++ b/boards/renesas/ek_ra6e2/doc/index.rst @@ -61,7 +61,7 @@ The key features of the EK-RA6E2 board are categorized in three groups as follow - 16 Mb (128 Mb) External Quad-SPI Flash - CAN (3-pin header) -.. figure:: ek-ra6e2-board.webp +.. figure:: ek_ra6e2.webp :align: center :alt: RA6E2 Evaluation Kit @@ -71,7 +71,7 @@ Hardware ******** Detailed hardware feature for the RA6E2 MCU group can be found at `RA6E2 Group User's Manual Hardware`_ -.. figure:: ra6e2-block-diagram.webp +.. figure:: ra6e2_block_diagram.webp :width: 442px :align: center :alt: RA6E2 MCU group feature @@ -98,6 +98,16 @@ The below features are currently supported on Zephyr OS for EK-RA6E2 board: +-----------+------------+----------------------+ | CLOCK | on-chip | clock control | +-----------+------------+----------------------+ +| SPI | on-chip | spi | ++-----------+------------+----------------------+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| ENTROPY | on-chip | entropy | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ Other hardware features are currently not supported by the port. diff --git a/boards/renesas/ek_ra6e2/doc/ra6e2-block-diagram.webp b/boards/renesas/ek_ra6e2/doc/ra6e2_block_diagram.webp similarity index 100% rename from boards/renesas/ek_ra6e2/doc/ra6e2-block-diagram.webp rename to boards/renesas/ek_ra6e2/doc/ra6e2_block_diagram.webp diff --git a/boards/renesas/ek_ra6e2/ek_ra6e2-pinctrl.dtsi b/boards/renesas/ek_ra6e2/ek_ra6e2-pinctrl.dtsi index 851d8543bee..f947ec6eba7 100644 --- a/boards/renesas/ek_ra6e2/ek_ra6e2-pinctrl.dtsi +++ b/boards/renesas/ek_ra6e2/ek_ra6e2-pinctrl.dtsi @@ -11,4 +11,39 @@ ; }; }; + + spi0_default: spi0_default { + group1 { + /* MISO MOSI RSPCK SSL */ + psels = , + , + , + ; + }; + }; + + canfd0_default: canfd0_default { + group1 { + /* CRX0 CTX0 */ + psels = , + ; + drive-strength = "high"; + }; + }; + + adc0_default: adc0_default { + group1 { + /* input */ + psels = ; + renesas,analog-enable; + }; + }; + + pwm1_default: pwm1_default { + group1 { + /* GTIOC1A GTIOC1B */ + psels = , + ; + }; + }; }; diff --git a/boards/renesas/ek_ra6e2/ek_ra6e2.dts b/boards/renesas/ek_ra6e2/ek_ra6e2.dts index 682aafcd006..a2ef88dba3e 100644 --- a/boards/renesas/ek_ra6e2/ek_ra6e2.dts +++ b/boards/renesas/ek_ra6e2/ek_ra6e2.dts @@ -7,6 +7,8 @@ #include #include +#include +#include #include "ek_ra6e2-pinctrl.dtsi" @@ -16,9 +18,12 @@ chosen { zephyr,sram = &sram0; + zephyr,flash-controller = &flash1; zephyr,flash = &flash0; zephyr,console = &uart0; zephyr,shell-uart = &uart0; + zephyr,canbus = &canfd0; + zephyr,entropy = &trng; }; leds { @@ -37,8 +42,24 @@ }; }; + buttons { + compatible = "gpio-keys"; + button0: s1 { + gpios = <&ioport0 5 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button switch 1"; + zephyr,code = ; + }; + button1: s2 { + gpios = <&ioport3 4 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button switch 2"; + zephyr,code = ; + }; + }; + aliases { led0 = &led1; + sw0 = &button0; + sw1 = &button1; }; }; @@ -52,34 +73,30 @@ }; }; -&ioport1 { +&ioport0 { status = "okay"; }; -&ioport2 { +&ioport1 { status = "okay"; }; -&ioport4 { +&spi0 { + pinctrl-0 = <&spi0_default>; + pinctrl-names = "default"; status = "okay"; }; -&flash0 { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; +&ioport2 { + status = "okay"; +}; - boot_partition: partition@0 { - label = "application"; - reg = <0x00000000 DT_SIZE_K(128)>; - }; +&ioport3 { + status = "okay"; +}; - storage_partition: partition@20000 { - label = "storage"; - reg = <0x20000 DT_SIZE_K(128)>; - }; - }; +&ioport4 { + status = "okay"; }; &xtal { @@ -94,8 +111,70 @@ }; &pll { - source = ; - div = ; + clocks = <&xtal>; + div = <1>; mul = <10 0>; status = "okay"; }; + +&canfdclk { + clocks = <&pll>; + div = <8>; + status = "okay"; +}; + +&canfd_global { + status = "okay"; + canfd0 { + pinctrl-0 = <&canfd0_default>; + pinctrl-names = "default"; + rx-max-filters = <16>; + status = "okay"; + + can-transceiver { + max-bitrate = <5000000>; + }; + }; +}; + +&adc0 { + status = "okay"; + pinctrl-0 = <&adc0_default>; + pinctrl-names = "default"; +}; + +&port_irq9 { + interrupts = <4 12>; + status = "okay"; +}; + +&port_irq10 { + interrupts = <5 12>; + status = "okay"; +}; + +&pwm1 { + pinctrl-0 = <&pwm1_default>; + pinctrl-names = "default"; + interrupts = <63 1>, <64 1>; + interrupt-names = "gtioca", "overflow"; + divider = ; + status = "okay"; +}; + +&trng { + status ="okay"; +}; + +&flash1 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + storage_partition: partition@0 { + label = "storage"; + reg = <0X0 DT_SIZE_K(4)>; + }; + }; +}; diff --git a/boards/renesas/ek_ra6e2/ek_ra6e2_defconfig b/boards/renesas/ek_ra6e2/ek_ra6e2_defconfig index 92bb425cfa8..882cf699d98 100644 --- a/boards/renesas/ek_ra6e2/ek_ra6e2_defconfig +++ b/boards/renesas/ek_ra6e2/ek_ra6e2_defconfig @@ -5,7 +5,6 @@ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=200000000 # Enable GPIO CONFIG_GPIO=y -CONFIG_PINCTRL=y # Enable Console CONFIG_SERIAL=y @@ -14,5 +13,4 @@ CONFIG_UART_CONSOLE=y CONFIG_CONSOLE=y CONFIG_BUILD_OUTPUT_HEX=y -CONFIG_BUILD_NO_GAP_FILL=y CONFIG_CLOCK_CONTROL=y diff --git a/boards/renesas/ek_ra6m1/doc/ek-ra6m1-board.webp b/boards/renesas/ek_ra6m1/doc/ek_ra6m1.webp similarity index 100% rename from boards/renesas/ek_ra6m1/doc/ek-ra6m1-board.webp rename to boards/renesas/ek_ra6m1/doc/ek_ra6m1.webp diff --git a/boards/renesas/ek_ra6m1/doc/index.rst b/boards/renesas/ek_ra6m1/doc/index.rst index 955c87ac32b..88aa944e3c1 100644 --- a/boards/renesas/ek_ra6m1/doc/index.rst +++ b/boards/renesas/ek_ra6m1/doc/index.rst @@ -57,7 +57,7 @@ all of which are controlled by the Main MCU firmware - USB Full Speed Debug and Device (micro-AB connector) -.. figure:: ek-ra6m1-board.webp +.. figure:: ek_ra6m1.webp :align: center :alt: RA6M1 Evaluation Kit @@ -67,7 +67,7 @@ Hardware ******** Detailed hardware feature for the RA6M1 MCU group can be found at `RA6M1 Group User's Manual Hardware`_ -.. figure:: ra6m1-block-diagram.webp +.. figure:: ra6m1_block_diagram.webp :width: 442px :align: center :alt: RA6M1 MCU group feature @@ -94,6 +94,18 @@ The below features are currently supported on Zephyr OS for EK-RA6M1 board: +-----------+------------+----------------------+ | CLOCK | on-chip | clock control | +-----------+------------+----------------------+ +| I2C | on-chip | i2c | ++-----------+------------+----------------------+ +| SPI | on-chip | spi | ++-----------+------------+----------------------+ +| COUNTER | on-chip | counter | ++-----------+------------+----------------------+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ Other hardware features are currently not supported by the port. diff --git a/boards/renesas/ek_ra6m1/doc/ra6m1-block-diagram.webp b/boards/renesas/ek_ra6m1/doc/ra6m1_block_diagram.webp similarity index 100% rename from boards/renesas/ek_ra6m1/doc/ra6m1-block-diagram.webp rename to boards/renesas/ek_ra6m1/doc/ra6m1_block_diagram.webp diff --git a/boards/renesas/ek_ra6m1/ek_ra6m1-pinctrl.dtsi b/boards/renesas/ek_ra6m1/ek_ra6m1-pinctrl.dtsi index 56fa3e26b6a..667e6dcd5c8 100644 --- a/boards/renesas/ek_ra6m1/ek_ra6m1-pinctrl.dtsi +++ b/boards/renesas/ek_ra6m1/ek_ra6m1-pinctrl.dtsi @@ -11,4 +11,39 @@ ; }; }; + + iic0_default: iic0_default { + group1 { + /* SCL0 SDA0 */ + psels = , + ; + drive-strength = "medium"; + }; + }; + + spi0_default: spi0_default { + group1 { + /* MISO MOSI RSPCK SSL */ + psels = , + , + , + ; + }; + }; + + adc0_default: adc0_default { + group1 { + /* input */ + psels = ; + renesas,analog-enable; + }; + }; + + pwm1_default: pwm1_default { + group1 { + /* GTIOC1A GTIOC1B */ + psels = , + ; + }; + }; }; diff --git a/boards/renesas/ek_ra6m1/ek_ra6m1.dts b/boards/renesas/ek_ra6m1/ek_ra6m1.dts index f82d0659112..a6df950b29e 100644 --- a/boards/renesas/ek_ra6m1/ek_ra6m1.dts +++ b/boards/renesas/ek_ra6m1/ek_ra6m1.dts @@ -7,6 +7,8 @@ #include #include +#include +#include #include "ek_ra6m1-pinctrl.dtsi" @@ -16,9 +18,11 @@ chosen { zephyr,sram = &sram0; + zephyr,flash-controller = &flash1; zephyr,flash = &flash0; zephyr,console = &uart8; zephyr,shell-uart = &uart8; + zephyr,entropy = &trng; }; leds { @@ -29,8 +33,18 @@ }; }; + buttons { + compatible = "gpio-keys"; + button0: s1 { + gpios = <&ioport4 15 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button switch 1"; + zephyr,code = ; + }; + }; + aliases { led0 = &led1; + sw0 = &button0; }; }; @@ -44,10 +58,31 @@ }; }; +&iic0 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <91 1>, <92 1>, <93 1>, <94 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + clock-frequency = ; + pinctrl-0 = <&iic0_default>; + pinctrl-names = "default"; +}; + +&spi0 { + pinctrl-0 = <&spi0_default>; + pinctrl-names = "default"; + status = "okay"; +}; + &ioport1 { status = "okay"; }; +&ioport4 { + status = "okay"; +}; + &xtal { clock-frequency = ; mosel = <0>; @@ -60,8 +95,44 @@ }; &pll { - source = ; - div = ; + clocks = <&xtal>; + div = <1>; mul = <20 0>; status = "okay"; }; + +&trng { + status ="okay"; +}; + +&adc0 { + status = "okay"; + pinctrl-0 = <&adc0_default>; + pinctrl-names = "default"; +}; + +&port_irq8 { + interrupts = <41 12>; + status = "okay"; +}; + +&pwm1 { + pinctrl-0 = <&pwm1_default>; + pinctrl-names = "default"; + interrupts = <63 1>, <64 1>; + interrupt-names = "gtioca", "overflow"; + status = "okay"; +}; + +&flash1 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + storage_partition: partition@0 { + label = "storage"; + reg = <0X0 DT_SIZE_K(8)>; + }; + }; +}; diff --git a/boards/renesas/ek_ra6m1/ek_ra6m1_defconfig b/boards/renesas/ek_ra6m1/ek_ra6m1_defconfig index 00adc77146e..fb0bf97d888 100644 --- a/boards/renesas/ek_ra6m1/ek_ra6m1_defconfig +++ b/boards/renesas/ek_ra6m1/ek_ra6m1_defconfig @@ -5,10 +5,8 @@ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=120000000 # Enable GPIO CONFIG_GPIO=y -CONFIG_PINCTRL=y CONFIG_BUILD_OUTPUT_HEX=y -CONFIG_BUILD_NO_GAP_FILL=y CONFIG_CLOCK_CONTROL=y # Enable Console diff --git a/boards/renesas/ek_ra6m2/doc/ek-ra6m2-board.webp b/boards/renesas/ek_ra6m2/doc/ek_ra6m2.webp similarity index 100% rename from boards/renesas/ek_ra6m2/doc/ek-ra6m2-board.webp rename to boards/renesas/ek_ra6m2/doc/ek_ra6m2.webp diff --git a/boards/renesas/ek_ra6m2/doc/index.rst b/boards/renesas/ek_ra6m2/doc/index.rst index 2a5cb68d16b..7ef4dc9589d 100644 --- a/boards/renesas/ek_ra6m2/doc/index.rst +++ b/boards/renesas/ek_ra6m2/doc/index.rst @@ -51,7 +51,7 @@ The key features of the EK-RA6M2 board are categorized in three groups as follow - USB Full Speed Host and Device (micro-AB connector) -.. figure:: ek-ra6m2-board.webp +.. figure:: ek_ra6m2.webp :align: center :alt: RA6M2 Evaluation Kit @@ -61,7 +61,7 @@ Hardware ******** Detailed hardware feature for the RA6M2 MCU group can be found at `RA6M2 Group User's Manual Hardware`_ -.. figure:: ra6m2-block-diagram.webp +.. figure:: ra6m2_block_diagram.webp :width: 871px :align: center :alt: RA6M2 MCU group feature @@ -88,6 +88,18 @@ The below features are currently supported on Zephyr OS for EK-RA6M2 board: +-----------+------------+----------------------+ | CLOCK | on-chip | clock control | +-----------+------------+----------------------+ +| I2C | on-chip | i2c | ++-----------+------------+----------------------+ +| SPI | on-chip | spi | ++-----------+------------+----------------------+ +| COUNTER | on-chip | counter | ++-----------+------------+----------------------+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ Other hardware features are currently not supported by the port. diff --git a/boards/renesas/ek_ra6m2/doc/ra6m2-block-diagram.webp b/boards/renesas/ek_ra6m2/doc/ra6m2_block_diagram.webp similarity index 100% rename from boards/renesas/ek_ra6m2/doc/ra6m2-block-diagram.webp rename to boards/renesas/ek_ra6m2/doc/ra6m2_block_diagram.webp diff --git a/boards/renesas/ek_ra6m2/ek_ra6m2-pinctrl.dtsi b/boards/renesas/ek_ra6m2/ek_ra6m2-pinctrl.dtsi index 69d920e7eda..bfccf28bc96 100644 --- a/boards/renesas/ek_ra6m2/ek_ra6m2-pinctrl.dtsi +++ b/boards/renesas/ek_ra6m2/ek_ra6m2-pinctrl.dtsi @@ -11,4 +11,39 @@ ; }; }; + + iic2_default: iic2_default { + group1 { + /* SCL2 SDA2 */ + psels = , + ; + drive-strength = "medium"; + }; + }; + + spi0_default: spi0_default { + group1 { + /* MISO MOSI RSPCK SSL */ + psels = , + , + , + ; + }; + }; + + adc0_default: adc0_default { + group1 { + /* input */ + psels = ; + renesas,analog-enable; + }; + }; + + pwm1_default: pwm1_default { + group1 { + /* GTIOC1A GTIOC1B */ + psels = , + ; + }; + }; }; diff --git a/boards/renesas/ek_ra6m2/ek_ra6m2.dts b/boards/renesas/ek_ra6m2/ek_ra6m2.dts index 78407352e72..46ea01ac4c6 100644 --- a/boards/renesas/ek_ra6m2/ek_ra6m2.dts +++ b/boards/renesas/ek_ra6m2/ek_ra6m2.dts @@ -7,6 +7,8 @@ #include #include +#include +#include #include "ek_ra6m2-pinctrl.dtsi" @@ -16,9 +18,11 @@ chosen { zephyr,sram = &sram0; + zephyr,flash-controller = &flash1; zephyr,flash = &flash0; zephyr,console = &uart7; zephyr,shell-uart = &uart7; + zephyr,entropy = &trng; }; leds { @@ -29,8 +33,18 @@ }; }; + buttons { + compatible = "gpio-keys"; + button0: s1 { + gpios = <&ioport1 5 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button switch 1"; + zephyr,code = ; + }; + }; + aliases { led0 = &led1; + sw0 = &button0; }; }; @@ -44,6 +58,23 @@ }; }; +&iic2 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <91 1>, <92 1>, <93 1>, <94 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + clock-frequency = ; + pinctrl-0 = <&iic2_default>; + pinctrl-names = "default"; +}; + +&spi0 { + pinctrl-0 = <&spi0_default>; + pinctrl-names = "default"; + status = "okay"; +}; + &ioport1 { status = "okay"; }; @@ -60,8 +91,44 @@ }; &pll { - source = ; - div = ; + clocks = <&xtal>; + div = <1>; mul = <20 0>; status = "okay"; }; + +&trng { + status ="okay"; +}; + +&adc0 { + status = "okay"; + pinctrl-0 = <&adc0_default>; + pinctrl-names = "default"; +}; + +&port_irq0 { + interrupts = <41 12>; + status = "okay"; +}; + +&pwm1 { + pinctrl-0 = <&pwm1_default>; + pinctrl-names = "default"; + interrupts = <63 1>, <64 1>; + interrupt-names = "gtioca", "overflow"; + status = "okay"; +}; + +&flash1 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + storage_partition: partition@0 { + label = "storage"; + reg = <0X0 DT_SIZE_K(32)>; + }; + }; +}; diff --git a/boards/renesas/ek_ra6m2/ek_ra6m2_defconfig b/boards/renesas/ek_ra6m2/ek_ra6m2_defconfig index 00adc77146e..fb0bf97d888 100644 --- a/boards/renesas/ek_ra6m2/ek_ra6m2_defconfig +++ b/boards/renesas/ek_ra6m2/ek_ra6m2_defconfig @@ -5,10 +5,8 @@ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=120000000 # Enable GPIO CONFIG_GPIO=y -CONFIG_PINCTRL=y CONFIG_BUILD_OUTPUT_HEX=y -CONFIG_BUILD_NO_GAP_FILL=y CONFIG_CLOCK_CONTROL=y # Enable Console diff --git a/boards/renesas/ek_ra6m3/doc/ek-ra6m3-board.webp b/boards/renesas/ek_ra6m3/doc/ek_ra6m3.webp similarity index 100% rename from boards/renesas/ek_ra6m3/doc/ek-ra6m3-board.webp rename to boards/renesas/ek_ra6m3/doc/ek_ra6m3.webp diff --git a/boards/renesas/ek_ra6m3/doc/index.rst b/boards/renesas/ek_ra6m3/doc/index.rst index bb468d9d1f5..1421fbaac1b 100644 --- a/boards/renesas/ek_ra6m3/doc/index.rst +++ b/boards/renesas/ek_ra6m3/doc/index.rst @@ -59,7 +59,7 @@ The key features of the EK-RA6M3 board are categorized in three groups as follow - USB High Speed Host and Device (micro-AB connector) - 32 Mb (256 Mb) External Quad-SPI Flash -.. figure:: ek-ra6m3-board.webp +.. figure:: ek_ra6m3.webp :align: center :alt: RA6M3 Evaluation Kit @@ -69,7 +69,7 @@ Hardware ******** Detailed hardware feature for the RA6M3 MCU group can be found at `RA6M3 Group User's Manual Hardware`_ -.. figure:: ra6m3-block-diagram.webp +.. figure:: ra6m3_block_diagram.webp :width: 442px :align: center :alt: RA6M3 MCU group feature @@ -96,6 +96,20 @@ The below features are currently supported on Zephyr OS for EK-RA6M3 board: +-----------+------------+----------------------+ | CLOCK | on-chip | clock control | +-----------+------------+----------------------+ +| I2C | on-chip | i2c | ++-----------+------------+----------------------+ +| SPI | on-chip | spi | ++-----------+------------+----------------------+ +| COUNTER | on-chip | counter | ++-----------+------------+----------------------+ +| USBHS | on-chip | udc | ++-----------+------------+----------------------+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ Other hardware features are currently not supported by the port. diff --git a/boards/renesas/ek_ra6m3/doc/ra6m3-block-diagram.webp b/boards/renesas/ek_ra6m3/doc/ra6m3_block_diagram.webp similarity index 100% rename from boards/renesas/ek_ra6m3/doc/ra6m3-block-diagram.webp rename to boards/renesas/ek_ra6m3/doc/ra6m3_block_diagram.webp diff --git a/boards/renesas/ek_ra6m3/ek_ra6m3-pinctrl.dtsi b/boards/renesas/ek_ra6m3/ek_ra6m3-pinctrl.dtsi index 56fa3e26b6a..6c3d7f285fd 100644 --- a/boards/renesas/ek_ra6m3/ek_ra6m3-pinctrl.dtsi +++ b/boards/renesas/ek_ra6m3/ek_ra6m3-pinctrl.dtsi @@ -11,4 +11,46 @@ ; }; }; + + iic2_default: iic2_default { + group1 { + /* SCL2 SDA2 */ + psels = , + ; + drive-strength = "medium"; + }; + }; + + spi0_default: spi0_default { + group1 { + /* MISO MOSI RSPCK SSL */ + psels = , + , + , + ; + }; + }; + + usbhs_default: usbhs_default { + group1 { + psels = ; /* VBUS */ + drive-strength = "high"; + }; + }; + + adc0_default: adc0_default { + group1 { + /* input */ + psels = ; + renesas,analog-enable; + }; + }; + + pwm1_default: pwm1_default { + group1 { + /* GTIOC1A GTIOC1B */ + psels = , + ; + }; + }; }; diff --git a/boards/renesas/ek_ra6m3/ek_ra6m3.dts b/boards/renesas/ek_ra6m3/ek_ra6m3.dts index 0cd4de22aa1..5ef2fd4b8b5 100644 --- a/boards/renesas/ek_ra6m3/ek_ra6m3.dts +++ b/boards/renesas/ek_ra6m3/ek_ra6m3.dts @@ -7,6 +7,8 @@ #include #include +#include +#include #include "ek_ra6m3-pinctrl.dtsi" @@ -18,7 +20,9 @@ zephyr,sram = &sram0; zephyr,console = &uart8; zephyr,shell-uart = &uart8; + zephyr,flash-controller = &flash1; zephyr,flash = &flash0; + zephyr,entropy = &trng; }; leds { @@ -37,11 +41,37 @@ }; }; + buttons { + compatible = "gpio-keys"; + button0: s1 { + gpios = <&ioport0 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button switch 1"; + zephyr,code = ; + }; + button1: s2 { + gpios = <&ioport0 8 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button switch 2"; + zephyr,code = ; + }; + }; + aliases { led0 = &led1; + sw0 = &button0; + sw1 = &button1; }; }; +&spi0 { + pinctrl-0 = <&spi0_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&ioport0 { + status = "okay"; +}; + &ioport1 { status = "okay"; }; @@ -60,6 +90,17 @@ }; }; +&iic2 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <91 1>, <92 1>, <93 1>, <94 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + clock-frequency = ; + pinctrl-0 = <&iic2_default>; + pinctrl-names = "default"; +}; + &xtal { clock-frequency = ; mosel = <0>; @@ -72,8 +113,63 @@ }; &pll { - source = ; - div = ; + clocks = <&xtal>; + div = <2>; mul = <20 0>; status = "okay"; }; + +&trng { + status ="okay"; +}; + +&usbhs { + pinctrl-0 = <&usbhs_default>; + pinctrl-names = "default"; + maximum-speed = "high-speed"; + status = "okay"; + zephyr_udc0: udc { + status = "okay"; + }; +}; + +&usbhs_phy { + phys-clock-src = "xtal"; +}; + +&adc0 { + status = "okay"; + pinctrl-0 = <&adc0_default>; + pinctrl-names = "default"; +}; + +&port_irq12 { + interrupts = <41 12>; + status = "okay"; +}; + +&port_irq13 { + interrupts = <42 12>; + status = "okay"; +}; + +&pwm1 { + pinctrl-0 = <&pwm1_default>; + pinctrl-names = "default"; + interrupts = <63 1>, <64 1>; + interrupt-names = "gtioca", "overflow"; + status = "okay"; +}; + +&flash1 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + storage_partition: partition@0 { + label = "storage"; + reg = <0X0 DT_SIZE_K(64)>; + }; + }; +}; diff --git a/boards/renesas/ek_ra6m3/ek_ra6m3_defconfig b/boards/renesas/ek_ra6m3/ek_ra6m3_defconfig index 31c2fa759e4..914980bc08c 100644 --- a/boards/renesas/ek_ra6m3/ek_ra6m3_defconfig +++ b/boards/renesas/ek_ra6m3/ek_ra6m3_defconfig @@ -5,7 +5,6 @@ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=120000000 # Enable GPIO CONFIG_GPIO=y -CONFIG_PINCTRL=y # Enable Console CONFIG_SERIAL=y @@ -14,5 +13,4 @@ CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_BUILD_OUTPUT_HEX=y -CONFIG_BUILD_NO_GAP_FILL=y CONFIG_CLOCK_CONTROL=y diff --git a/boards/renesas/ek_ra6m4/doc/ek-ra6m4-board.webp b/boards/renesas/ek_ra6m4/doc/ek_ra6m4.webp similarity index 100% rename from boards/renesas/ek_ra6m4/doc/ek-ra6m4-board.webp rename to boards/renesas/ek_ra6m4/doc/ek_ra6m4.webp diff --git a/boards/renesas/ek_ra6m4/doc/index.rst b/boards/renesas/ek_ra6m4/doc/index.rst index 82549000d63..1945197d633 100644 --- a/boards/renesas/ek_ra6m4/doc/index.rst +++ b/boards/renesas/ek_ra6m4/doc/index.rst @@ -64,7 +64,7 @@ The key features of the EK-RA6M4 board are categorized in three groups as follow - 32 Mb (256 Mb) External Quad-SPI Flash - 64 Mb (512 Mb) External Octo-SPI Flash -.. figure:: ek-ra6m4-board.webp +.. figure:: ek_ra6m4.webp :align: center :alt: RA6M4 Evaluation Kit @@ -74,7 +74,7 @@ Hardware ******** Detailed hardware feature for the RA6M4 MCU group can be found at `RA6M4 Group User's Manual Hardware`_ -.. figure:: ra6m4-block-diagram.webp +.. figure:: ra6m4_block_diagram.webp :width: 442px :align: center :alt: RA6M4 MCU group feature @@ -101,6 +101,18 @@ The below features are currently supported on Zephyr OS for EK-RA6M4 board: +-----------+------------+----------------------+ | CLOCK | on-chip | clock control | +-----------+------------+----------------------+ +| I2C | on-chip | i2c | ++-----------+------------+----------------------+ +| SPI | on-chip | spi | ++-----------+------------+----------------------+ +| COUNTER | on-chip | counter | ++-----------+------------+----------------------+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ Other hardware features are currently not supported by the port. diff --git a/boards/renesas/ek_ra6m4/doc/ra6m4-block-diagram.webp b/boards/renesas/ek_ra6m4/doc/ra6m4_block_diagram.webp similarity index 100% rename from boards/renesas/ek_ra6m4/doc/ra6m4-block-diagram.webp rename to boards/renesas/ek_ra6m4/doc/ra6m4_block_diagram.webp diff --git a/boards/renesas/ek_ra6m4/ek_ra6m4-pinctrl.dtsi b/boards/renesas/ek_ra6m4/ek_ra6m4-pinctrl.dtsi index 851d8543bee..29ef6ff2382 100644 --- a/boards/renesas/ek_ra6m4/ek_ra6m4-pinctrl.dtsi +++ b/boards/renesas/ek_ra6m4/ek_ra6m4-pinctrl.dtsi @@ -11,4 +11,39 @@ ; }; }; + + iic1_default: iic1_default { + group1 { + /* SCL1 SDA1 */ + psels = , + ; + drive-strength = "medium"; + }; + }; + + spi0_default: spi0_default { + group1 { + /* MISO MOSI RSPCK SSL */ + psels = , + , + , + ; + }; + }; + + adc0_default: adc0_default { + group1 { + /* input */ + psels = ; + renesas,analog-enable; + }; + }; + + pwm1_default: pwm1_default { + group1 { + /* GTIOC1A GTIOC1B */ + psels = , + ; + }; + }; }; diff --git a/boards/renesas/ek_ra6m4/ek_ra6m4.dts b/boards/renesas/ek_ra6m4/ek_ra6m4.dts index f0f447eede7..dbfd41347fb 100644 --- a/boards/renesas/ek_ra6m4/ek_ra6m4.dts +++ b/boards/renesas/ek_ra6m4/ek_ra6m4.dts @@ -7,6 +7,8 @@ #include #include +#include +#include #include "ek_ra6m4-pinctrl.dtsi" @@ -16,6 +18,7 @@ chosen { zephyr,sram = &sram0; + zephyr,flash-controller = &flash1; zephyr,flash = &flash0; zephyr,console = &uart0; zephyr,shell-uart = &uart0; @@ -37,8 +40,24 @@ }; }; + buttons { + compatible = "gpio-keys"; + button0: s1 { + gpios = <&ioport0 5 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button switch 1"; + zephyr,code = ; + }; + button1: s2 { + gpios = <&ioport0 6 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button switch 2"; + zephyr,code = ; + }; + }; + aliases { led0 = &led1; + sw0 = &button0; + sw1 = &button1; }; }; @@ -52,6 +71,27 @@ }; }; +&iic1 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <91 1>, <92 1>, <93 1>, <94 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + clock-frequency = ; + pinctrl-0 = <&iic1_default>; + pinctrl-names = "default"; +}; + +&spi0 { + pinctrl-0 = <&spi0_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&ioport0 { + status = "okay"; +}; + &ioport4 { status = "okay"; }; @@ -68,14 +108,51 @@ }; &pll { - source = ; - div = ; + clocks = <&xtal>; + div = <3>; mul = <25 0>; status = "okay"; }; &pclka { - clk-src = ; - clk-div = ; + clocks = <&pll>; + div = <2>; + status = "okay"; +}; + +&adc0 { + status = "okay"; + pinctrl-0 = <&adc0_default>; + pinctrl-names = "default"; +}; + +&port_irq10 { + interrupts = <41 12>; status = "okay"; }; + +&port_irq11 { + interrupts = <42 12>; + status = "okay"; +}; + +&pwm1 { + pinctrl-0 = <&pwm1_default>; + pinctrl-names = "default"; + interrupts = <63 1>, <64 1>; + interrupt-names = "gtioca", "overflow"; + status = "okay"; +}; + +&flash1 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + storage_partition: partition@0 { + label = "storage"; + reg = <0X0 DT_SIZE_K(8)>; + }; + }; +}; diff --git a/boards/renesas/ek_ra6m4/ek_ra6m4_defconfig b/boards/renesas/ek_ra6m4/ek_ra6m4_defconfig index 45a5a73366a..7d9405d6204 100644 --- a/boards/renesas/ek_ra6m4/ek_ra6m4_defconfig +++ b/boards/renesas/ek_ra6m4/ek_ra6m4_defconfig @@ -5,7 +5,6 @@ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=200000000 # Enable GPIO CONFIG_GPIO=y -CONFIG_PINCTRL=y # Enable Console CONFIG_SERIAL=y @@ -14,5 +13,4 @@ CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_BUILD_OUTPUT_HEX=y -CONFIG_BUILD_NO_GAP_FILL=y CONFIG_CLOCK_CONTROL=y diff --git a/boards/renesas/ek_ra6m5/doc/ek-ra6m5-board.webp b/boards/renesas/ek_ra6m5/doc/ek_ra6m5.webp similarity index 100% rename from boards/renesas/ek_ra6m5/doc/ek-ra6m5-board.webp rename to boards/renesas/ek_ra6m5/doc/ek_ra6m5.webp diff --git a/boards/renesas/ek_ra6m5/doc/index.rst b/boards/renesas/ek_ra6m5/doc/index.rst index bc94a155e11..5ab8b3bc49d 100644 --- a/boards/renesas/ek_ra6m5/doc/index.rst +++ b/boards/renesas/ek_ra6m5/doc/index.rst @@ -62,7 +62,7 @@ The key features of the EK-RA6M5 board are categorized in three groups as follow - 64 Mb (512 Mb) External Octo-SPI Flash - CAN (3-pin header) -.. figure:: ek-ra6m5-board.webp +.. figure:: ek_ra6m5.webp :align: center :alt: RA6M5 Evaluation Kit @@ -72,7 +72,7 @@ Hardware ******** Detailed hardware feature for the RA6M5 MCU group can be found at `RA6M5 Group User's Manual Hardware`_ -.. figure:: ra6m5-block-diagram.webp +.. figure:: ra6m5_block_diagram.webp :width: 442px :align: center :alt: RA6M5 MCU group feature @@ -99,6 +99,20 @@ The below features are currently supported on Zephyr OS for EK-RA6M5 board: +-----------+------------+----------------------+ | CLOCK | on-chip | clock control | +-----------+------------+----------------------+ +| I2C | on-chip | i2c | ++-----------+------------+----------------------+ +| SPI | on-chip | spi | ++-----------+------------+----------------------+ +| COUNTER | on-chip | counter | ++-----------+------------+----------------------+ +| USBHS | on-chip | udc | ++-----------+------------+----------------------+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ Other hardware features are currently not supported by the port. diff --git a/boards/renesas/ek_ra6m5/doc/ra6m5-block-diagram.webp b/boards/renesas/ek_ra6m5/doc/ra6m5_block_diagram.webp similarity index 100% rename from boards/renesas/ek_ra6m5/doc/ra6m5-block-diagram.webp rename to boards/renesas/ek_ra6m5/doc/ra6m5_block_diagram.webp diff --git a/boards/renesas/ek_ra6m5/ek_ra6m5-pinctrl.dtsi b/boards/renesas/ek_ra6m5/ek_ra6m5-pinctrl.dtsi index 851d8543bee..709f6168898 100644 --- a/boards/renesas/ek_ra6m5/ek_ra6m5-pinctrl.dtsi +++ b/boards/renesas/ek_ra6m5/ek_ra6m5-pinctrl.dtsi @@ -11,4 +11,46 @@ ; }; }; + + iic1_default: iic1_default { + group1 { + /* SCL1 SDA1 */ + psels = , + ; + drive-strength = "medium"; + }; + }; + + spi0_default: spi0_default { + group1 { + /* MISO MOSI RSPCK SSL */ + psels = , + , + , + ; + }; + }; + + usbhs_default: usbhs_default { + group1 { + psels = ; /* USBHS-VBUS */ + drive-strength = "high"; + }; + }; + + adc0_default: adc0_default { + group1 { + /* input */ + psels = ; + renesas,analog-enable; + }; + }; + + pwm1_default: pwm1_default { + group1 { + /* GTIOC1A GTIOC1B */ + psels = , + ; + }; + }; }; diff --git a/boards/renesas/ek_ra6m5/ek_ra6m5.dts b/boards/renesas/ek_ra6m5/ek_ra6m5.dts index ad84e26a167..9f5d1a5c276 100644 --- a/boards/renesas/ek_ra6m5/ek_ra6m5.dts +++ b/boards/renesas/ek_ra6m5/ek_ra6m5.dts @@ -7,6 +7,8 @@ #include #include +#include +#include #include "ek_ra6m5-pinctrl.dtsi" @@ -16,6 +18,7 @@ chosen { zephyr,sram = &sram0; + zephyr,flash-controller = &flash1; zephyr,flash = &flash0; zephyr,console = &uart0; zephyr,shell-uart = &uart0; @@ -37,8 +40,24 @@ }; }; + buttons { + compatible = "gpio-keys"; + button0: s1 { + gpios = <&ioport0 5 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button switch 1"; + zephyr,code = ; + }; + button1: s2 { + gpios = <&ioport0 4 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button switch 2"; + zephyr,code = ; + }; + }; + aliases { led0 = &led1; + sw0 = &button0; + sw1 = &button1; }; }; @@ -52,6 +71,23 @@ }; }; +&iic1 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <91 1>, <92 1>, <93 1>, <94 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + clock-frequency = ; + pinctrl-0 = <&iic1_default>; + pinctrl-names = "default"; +}; + +&spi0 { + pinctrl-0 = <&spi0_default>; + pinctrl-names = "default"; + status = "okay"; +}; + &ioport0 { status = "okay"; }; @@ -68,8 +104,59 @@ }; &pll { - source = ; - div = ; + clocks = <&xtal>; + div = <3>; mul = <25 0>; status = "okay"; }; + +&usbhs { + pinctrl-0 = <&usbhs_default>; + pinctrl-names = "default"; + maximum-speed = "high-speed"; + status = "okay"; + zephyr_udc0: udc { + status = "okay"; + }; +}; + +&usbhs_phy { + phys-clock-src = "xtal"; +}; + +&adc0 { + status = "okay"; + pinctrl-0 = <&adc0_default>; + pinctrl-names = "default"; +}; + +&port_irq9 { + interrupts = <41 12>; + status = "okay"; +}; + +&port_irq10 { + interrupts = <42 12>; + status = "okay"; +}; + +&pwm1 { + pinctrl-0 = <&pwm1_default>; + pinctrl-names = "default"; + interrupts = <63 1>, <64 1>; + interrupt-names = "gtioca", "overflow"; + status = "okay"; +}; + +&flash1 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + storage_partition: partition@0 { + label = "storage"; + reg = <0X0 DT_SIZE_K(8)>; + }; + }; +}; diff --git a/boards/renesas/ek_ra6m5/ek_ra6m5_defconfig b/boards/renesas/ek_ra6m5/ek_ra6m5_defconfig index 4b5534eb1ff..6a9a032666e 100644 --- a/boards/renesas/ek_ra6m5/ek_ra6m5_defconfig +++ b/boards/renesas/ek_ra6m5/ek_ra6m5_defconfig @@ -5,10 +5,8 @@ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=200000000 # Enable GPIO CONFIG_GPIO=y -CONFIG_PINCTRL=y CONFIG_BUILD_OUTPUT_HEX=y -CONFIG_BUILD_NO_GAP_FILL=y CONFIG_CLOCK_CONTROL=y # Enable Console diff --git a/boards/renesas/ek_ra8d1/CMakeLists.txt b/boards/renesas/ek_ra8d1/CMakeLists.txt new file mode 100644 index 00000000000..86d1cedc6f4 --- /dev/null +++ b/boards/renesas/ek_ra8d1/CMakeLists.txt @@ -0,0 +1,7 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) + +zephyr_linker_sources_ifdef(CONFIG_MEMC + SECTIONS sdram.ld) diff --git a/boards/renesas/ek_ra8d1/Kconfig.defconfig b/boards/renesas/ek_ra8d1/Kconfig.defconfig new file mode 100644 index 00000000000..db92a2bd461 --- /dev/null +++ b/boards/renesas/ek_ra8d1/Kconfig.defconfig @@ -0,0 +1,27 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_EK_RA8D1 + +if NETWORKING + +config NET_L2_ETHERNET + default y + +endif # NETWORKING + +if SHIELD_RTKMIPILCDB00000BE + +config MEMC + default y + +if LVGL + +config LV_Z_VDB_CUSTOM_SECTION + default y + +endif # LVGL + +endif # SHIELD_RTKMIPILCDB00000BE + +endif # BOARD_EK_RA8D1 diff --git a/boards/renesas/ek_ra8d1/doc/ek-ra8d1-board.jpg b/boards/renesas/ek_ra8d1/doc/ek_ra8d1.jpg similarity index 100% rename from boards/renesas/ek_ra8d1/doc/ek-ra8d1-board.jpg rename to boards/renesas/ek_ra8d1/doc/ek_ra8d1.jpg diff --git a/boards/renesas/ek_ra8d1/doc/index.rst b/boards/renesas/ek_ra8d1/doc/index.rst index 79a5dde2d90..183ed37acbd 100644 --- a/boards/renesas/ek_ra8d1/doc/index.rst +++ b/boards/renesas/ek_ra8d1/doc/index.rst @@ -61,7 +61,7 @@ The key features of the EK-RA8D1 board are categorized in three groups as follow - 512 Mb (64 MB) External Octo-SPI Flash (present in the MCU Native Pin Access area of the EK-RA8D1 board) - CAN FD (3-pin header) -.. figure:: ek-ra8d1-board.jpg +.. figure:: ek_ra8d1.jpg :align: center :alt: RA8D1 Evaluation Kit @@ -71,7 +71,7 @@ Hardware ******** Detail Hardware feature for the RA8D1 MCU group can be found at `RA8D1 Group User's Manual Hardware`_ -.. figure:: ra8d1-block-diagram.png +.. figure:: ra8d1_block_diagram.png :width: 442px :align: center :alt: RA8D1 MCU group feature @@ -85,25 +85,64 @@ Supported Features The below features are currently supported on Zephyr OS for EK-RA8D1 board: -+--------------+------------+------------------+ -| Interface | Controller | Driver/Component | -+==============+============+==================+ -| GPIO | on-chip | gpio | -+--------------+------------+------------------+ -| MPU | on-chip | arch/arm | -+--------------+------------+------------------+ -| NVIC | on-chip | arch/arm | -+--------------+------------+------------------+ -| UART | on-chip | serial | -+--------------+------------+------------------+ -| CLOCK | on-chip | clock control | -+--------------+------------+------------------+ -| ENTROPY | on-chip | entropy | -+--------------+------------+------------------+ -| SPI | on-chip | spi | -+--------------+------------+------------------+ -| FLASH | on-chip | flash | -+--------------+------------+------------------+ ++--------------+------------+-----------------------------------+ +| Interface | Controller | Driver/Component | ++==============+============+===================================+ +| GPIO | on-chip | gpio | ++--------------+------------+-----------------------------------+ +| MPU | on-chip | arch/arm | ++--------------+------------+-----------------------------------+ +| NVIC | on-chip | arch/arm | ++--------------+------------+-----------------------------------+ +| UART | on-chip | serial | ++--------------+------------+-----------------------------------+ +| CLOCK | on-chip | clock control | ++--------------+------------+-----------------------------------+ +| ENTROPY | on-chip | entropy | ++--------------+------------+-----------------------------------+ +| SPI | on-chip | spi | ++--------------+------------+-----------------------------------+ +| FLASH | on-chip | flash | ++--------------+------------+-----------------------------------+ +| PWM | on-chip | pwm | ++--------------+------------+-----------------------------------+ +| COUNTER | on-chip | counter | ++--------------+------------+-----------------------------------+ +| CAN | on-chip | canfd | ++--------------+------------+-----------------------------------+ +| I2C | on-chip | i2c | ++--------------+------------+-----------------------------------+ +| USBHS | on-chip | udc | ++--------------+------------+-----------------------------------+ +| DISPLAY | on-chip | LCDIF; MIPI-DSI. Tested with | +| | | :ref:`rtkmipilcdb00000be` shields | ++--------------+------------+-----------------------------------+ +| ETHERNET | on-chip | ethernet | ++--------------+------------+-----------------------------------+ +| ADC | on-chip | adc | ++--------------+------------+-----------------------------------+ +| SDHC | on-chip | sdhc | ++--------------+------------+-----------------------------------+ + +**Note:** + +- For using Ethernet on RA8D1 board please set switch SW1 as following configuration: + ++-------------+-------------+--------------+------------+------------+------------+-------------+-----------+ +| SW1-1 PMOD1 | SW1-2 TRACE | SW1-3 CAMERA | SW1-4 ETHA | SW1-5 ETHB | SW1-6 GLCD | SW1-7 SDRAM | SW1-8 I3C | ++-------------+-------------+--------------+------------+------------+------------+-------------+-----------+ +| OFF | OFF | OFF | OFF | ON | OFF | OFF | OFF | ++-------------+-------------+--------------+------------+------------+------------+-------------+-----------+ + +- For using SDHC channel 1 on RA8D1 board please set switch SW1 as following configuration: + ++-------------+-------------+--------------+------------+------------+------------+-------------+-----------+ +| SW1-1 PMOD1 | SW1-2 TRACE | SW1-3 CAMERA | SW1-4 ETHA | SW1-5 ETHB | SW1-6 GLCD | SW1-7 SDRAM | SW1-8 I3C | ++-------------+-------------+--------------+------------+------------+------------+-------------+-----------+ +| OFF | OFF | OFF | OFF | OFF | OFF | OFF | OFF | ++-------------+-------------+--------------+------------+------------+------------+-------------+-----------+ + +**CAUTION:** Do not enable SW1-4 and SW1-5 together Other hardware features are currently not supported by the port. diff --git a/boards/renesas/ek_ra8d1/doc/ra8d1-block-diagram.png b/boards/renesas/ek_ra8d1/doc/ra8d1_block_diagram.png similarity index 100% rename from boards/renesas/ek_ra8d1/doc/ra8d1-block-diagram.png rename to boards/renesas/ek_ra8d1/doc/ra8d1_block_diagram.png diff --git a/boards/renesas/ek_ra8d1/ek_ra8d1-pinctrl.dtsi b/boards/renesas/ek_ra8d1/ek_ra8d1-pinctrl.dtsi index 57a0e064fba..b4d3168b903 100644 --- a/boards/renesas/ek_ra8d1/ek_ra8d1-pinctrl.dtsi +++ b/boards/renesas/ek_ra8d1/ek_ra8d1-pinctrl.dtsi @@ -19,10 +19,246 @@ spi0_default: spi0_default { group1 { /* MISO MOSI RSPCK SSL */ - psels = , - , - , - ; + psels = , + , + , + ; + }; + }; + + pwm7_default: pwm7_default { + group1 { + /* GTIOC7A */ + psels = ; + }; + group2 { + /* GTIOC7B */ + psels = ; + }; + }; + + canfd0_default: canfd0_default { + group1 { + /* CRX0 CTX0 */ + psels = , + ; + drive-strength = "high"; + }; + }; + + iic1_default: iic1_default { + group1 { + /* SCL1 SDA1*/ + psels = ,; + drive-strength = "medium"; + }; + }; + + ether_default: ether_default { + group1 { + psels = , /* ET0_MDC */ + , /* ET0_MDIO */ + , /* ET0_LINKSTA */ + , /* RMII0_TXD_EN_B */ + , /* RMII0_TXD1_BR */ + , /* RMII0_TXD0_B */ + , /* REF50CK0_B */ + , /* RMII0_RXD0_B */ + , /* RMII0_RXD1_B */ + , /* RMII0_RX_ER_B */ + ; /* RMII0_CRS_DV_B */ + drive-strength = "high"; + }; + }; + + usbhs_default: usbhs_default { + group1 { + psels = ; /* USBHS-VBUS */ + drive-strength = "high"; + }; + }; + + adc0_default: adc0_default { + group1 { + /* input */ + psels = ; + renesas,analog-enable; + }; + }; + + sdram_default: sdram_default{ + group1 { + /* SDRAM_DQM1 */ + psels = , + /* SDRAM_CKE */ + , + /* SDRAM_WE */ + , + /* SDRAM_CS */ + , + /* SDRAM_A0 */ + , + /* SDRAM_A1 */ + , + /* SDRAM_A2 */ + , + /* SDRAM_A3 */ + , + /* SDRAM_A4 */ + , + /* SDRAM_A5 */ + , + /* SDRAM_A6 */ + , + /* SDRAM_A7 */ + , + /* SDRAM_A8 */ + , + /* SDRAM_A9 */ + , + /* SDRAM_A10 */ + , + /* SDRAM_A11 */ + , + /* SDRAM_A12 */ + , + /* SDRAM_D0 */ + , + /* SDRAM_D1 */ + , + /* SDRAM_D2 */ + , + /* SDRAM_D3 */ + , + /* SDRAM_D4 */ + , + /* SDRAM_D5 */ + , + /* SDRAM_D6 */ + , + /* SDRAM_D8 */ + , + /* SDRAM_D9 */ + , + /* SDRAM_D10 */ + , + /* SDRAM_D11 */ + , + /* SDRAM_D12 */ + , + /* SDRAM_D13 */ + , + /* SDRAM_D14 */ + , + /* SDRAM_BA0 */ + , + /* SDRAM_BA1 */ + , + /* SDRAM_RAS */ + , + /* SDRAM_CAS */ + , + /* SDRAM_SDCLK */ + ; + drive-strength = "high"; + }; + + group2 { + /* SDRAM_SDCLK */ + psels = ; + drive-strength = "highspeed-high"; + }; + + group3 { + /* SDRAM_D7 */ + psels = , + /* SDRAM_D15 */ + , + /* SDRAM_DQM0 */ + ; + }; + }; + + glcdc_default: glcdc_default { + group1 { + /* LCDC_TCON0 */ + psels = , + /* LCDC_TCON1 */ + , + /* LCDC_TCON2 */ + , + /* LCDC_TCON3 */ + , + /* LCDC_DATA00 */ + , + /* LCDC_DATA01 */ + , + /* LCDC_DATA02 */ + , + /* LCDC_DATA03 */ + , + /* LCDC_DATA04 */ + , + /* LCDC_DATA05 */ + , + /* LCDC_DATA06 */ + , + /* LCDC_DATA07 */ + , + /* LCDC_DATA08 */ + , + /* LCDC_DATA09 */ + , + /* LCDC_DATA10 */ + , + /* LCDC_DATA11 */ + , + /* LCDC_DATA12 */ + , + /* LCDC_DATA13 */ + , + /* LCDC_DATA14 */ + , + /* LCDC_DATA15 */ + , + /* LCDC_DATA16 */ + , + /* LCDC_DATA17 */ + , + /* LCDC_DATA18 */ + , + /* LCDC_DATA19 */ + , + /* LCDC_DATA20 */ + , + /* LCDC_DATA21 */ + , + /* LCDC_DATA22 */ + , + /* LCDC_DATA23 */ + , + /* LCDC_CLK */ + , + /* LCDC_EXTCLK */ + ; + }; + }; + + /* NOTE: pins conflict with ether_default */ + sdhc1_default: sdhc1_default { + group1 { + psels = , /* SDCD */ + , /* SDCMD */ + , /* SDDATA0 */ + , /* SDDATA1 */ + , /* SDDATA2 */ + , /* SDDATA3 */ + ; /* SDWP */ + drive-strength = "high"; + }; + group2 { + psels = ; /* SDCLK */ + drive-strength = "highspeed-high"; }; }; }; diff --git a/boards/renesas/ek_ra8d1/ek_ra8d1.dts b/boards/renesas/ek_ra8d1/ek_ra8d1.dts index 698e90e631c..a89c31f0940 100644 --- a/boards/renesas/ek_ra8d1/ek_ra8d1.dts +++ b/boards/renesas/ek_ra8d1/ek_ra8d1.dts @@ -7,7 +7,10 @@ #include #include - +#include +#include +#include +#include #include "ek_ra8d1-pinctrl.dtsi" / { @@ -21,6 +24,7 @@ zephyr,shell-uart = &uart9; zephyr,entropy = &trng; zephyr,flash-controller = &flash1; + zephyr,canbus = &canfd0; }; leds { @@ -39,8 +43,45 @@ }; }; + buttons { + compatible = "gpio-keys"; + button0: s1 { + gpios = <&ioport0 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button switch 1"; + zephyr,code = ; + }; + button1: s2 { + gpios = <&ioport0 8 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button switch 2"; + zephyr,code = ; + }; + }; + + sdram1: sdram@68000000 { + compatible = "zephyr,memory-region", "mmio-sram"; + device_type = "memory"; + reg = <0x68000000 DT_SIZE_M(64)>; /* 512 Mbits */ + zephyr,memory-region = "SDRAM"; + status = "okay"; + }; + + renesas_mipi_connector: mipi-connector { + compatible = "renesas,ra-gpio-mipi-header"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <14 0 &ioport5 11 0>, /* IIC_SDA */ + <15 0 &ioport4 4 0>, /* DISP_BLEN */ + <16 0 &ioport5 12 0>, /* IIC_SCL */ + <17 0 &ioport5 10 0>, /* DISP_INT */ + <18 0 &ioporta 1 0>; /* DISP_RST */ + }; + aliases { led0 = &led1; + sw0 = &button0; + sw1 = &button1; + mipi-dsi = &mipi_dsi; }; }; @@ -56,21 +97,40 @@ }; &pll { - source = ; - div = ; - mul = <96 0>; - divp = ; - freqp = ; - divq = ; - freqq = ; - divr = ; - freqr = ; status = "okay"; + pllp { + status = "okay"; + }; + + pllq { + status = "okay"; + }; + + pllr { + status = "okay"; + }; }; + &sciclk { - clk-src = ; - clk-div = ; + clocks = <&pllp>; + div = <4>; + status = "okay"; +}; + +&canfdclk { + clocks = <&pll>; + div = <5>; + status = "okay"; +}; + +&lcdclk { + clocks = <&pll>; + div = <2>; + status = "okay"; +}; + +&ioport0 { status = "okay"; }; @@ -82,10 +142,18 @@ status = "okay"; }; +&ioport5 { + status = "okay"; +}; + &ioport6 { status = "okay"; }; +&ioporta { + status = "okay"; +}; + &sci0 { /* sci0 and spi0 cannot be enabled together */ pinctrl-0 = <&sci9_default>; @@ -124,3 +192,111 @@ }; }; }; + +&pwm7 { + pinctrl-0 = <&pwm7_default>; + interrupts = <40 1>, <41 1>; + interrupt-names = "gtioca", "overflow"; + pinctrl-names = "default"; + status = "okay"; +}; + +&canfd_global { + status = "okay"; + canfd0 { + pinctrl-0 = <&canfd0_default>; + pinctrl-names = "default"; + rx-max-filters = <16>; + status = "okay"; + }; +}; + +&iic1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = ; + pinctrl-0 = <&iic1_default>; + pinctrl-names = "default"; +}; + +ð { + local-mac-address = [74 90 50 B0 5D E9]; + status = "okay"; + phy-handle = <&phy>; +}; + +&mdio { + pinctrl-0 = <ðer_default>; + pinctrl-names = "default"; + status = "okay"; + + phy: ethernet-phy@5 { + compatible = "ethernet-phy"; + reg = <5>; + status = "okay"; + }; +}; + +&usbhs { + pinctrl-0 = <&usbhs_default>; + pinctrl-names = "default"; + maximum-speed = "high-speed"; + status = "okay"; + zephyr_udc0: udc { + status = "okay"; + }; +}; + +&usbhs_phy { + phys-clock-src = "xtal"; +}; + +&adc0 { + status = "okay"; + pinctrl-0 = <&adc0_default>; + pinctrl-names = "default"; +}; + +&port_irq12 { + interrupts = <88 12>; + status = "okay"; +}; + +&port_irq13 { + interrupts = <89 12>; + status = "okay"; +}; + +&sdram { + pinctrl-0 = <&sdram_default>; + pinctrl-names = "default"; + status = "okay"; + auto-refresh-interval = ; + auto-refresh-count = ; + precharge-cycle-count = ; + multiplex-addr-shift = "10-bit"; + edian-mode = "little-endian"; + continuous-access; + bus-width = "16-bit"; + bank@0 { + reg = <0>; + renesas,ra-sdram-timing = ; + }; +}; + +zephyr_lcdif: &lcdif { + pinctrl-0 = <&glcdc_default>; + pinctrl-names = "default"; +}; + +zephyr_mipi_dsi: &mipi_dsi {}; + +renesas_mipi_i2c: &iic1{}; + +pmod_sd_shield: &sdhc1 {}; diff --git a/boards/renesas/ek_ra8d1/ek_ra8d1_defconfig b/boards/renesas/ek_ra8d1/ek_ra8d1_defconfig index daa9e38c77b..1f67b94e7c1 100644 --- a/boards/renesas/ek_ra8d1/ek_ra8d1_defconfig +++ b/boards/renesas/ek_ra8d1/ek_ra8d1_defconfig @@ -5,7 +5,6 @@ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=480000000 # Enable GPIO CONFIG_GPIO=y -CONFIG_PINCTRL=y # Enable Console CONFIG_SERIAL=y @@ -15,6 +14,3 @@ CONFIG_CONSOLE=y CONFIG_CLOCK_CONTROL=y CONFIG_BUILD_OUTPUT_HEX=y -CONFIG_BUILD_NO_GAP_FILL=y - -CONFIG_FLASH=y diff --git a/boards/renesas/ek_ra8d1/sdram.ld b/boards/renesas/ek_ra8d1/sdram.ld new file mode 100644 index 00000000000..5855e663d09 --- /dev/null +++ b/boards/renesas/ek_ra8d1/sdram.ld @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(sdram1), okay) + +SECTION_DATA_PROLOGUE(.sdram,(NOLOAD),) +{ + __SDRAM_Start = .; + KEEP(*(.sdram*)) +#ifdef CONFIG_LVGL + KEEP(*(.lvgl_buf*)) +#endif + __SDRAM_End = .; +} GROUP_LINK_IN(SDRAM) + +#endif diff --git a/boards/renesas/ek_ra8m1/Kconfig.defconfig b/boards/renesas/ek_ra8m1/Kconfig.defconfig new file mode 100644 index 00000000000..7f10ef8232f --- /dev/null +++ b/boards/renesas/ek_ra8m1/Kconfig.defconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_EK_RA8M1 + +if NETWORKING + +config NET_L2_ETHERNET + default y + +endif # NETWORKING + +endif # BOARD_EK_RA8M1 diff --git a/boards/renesas/ek_ra8m1/doc/ek-ra8m1-board.jpg b/boards/renesas/ek_ra8m1/doc/ek_ra8m1.jpg similarity index 100% rename from boards/renesas/ek_ra8m1/doc/ek-ra8m1-board.jpg rename to boards/renesas/ek_ra8m1/doc/ek_ra8m1.jpg diff --git a/boards/renesas/ek_ra8m1/doc/index.rst b/boards/renesas/ek_ra8m1/doc/index.rst index 84b168eb23e..55890ac3fcc 100644 --- a/boards/renesas/ek_ra8m1/doc/index.rst +++ b/boards/renesas/ek_ra8m1/doc/index.rst @@ -61,7 +61,7 @@ The key features of the EK-RA8M1 board are categorized in three groups as follow - 512 Mb (64 MB) External Octo-SPI Flash (present in the MCU Native Pin Access area of the EK-RA8M1 board) - CAN FD (3-pin header) -.. figure:: ek-ra8m1-board.jpg +.. figure:: ek_ra8m1.jpg :align: center :alt: RA8M1 Evaluation Kit @@ -71,7 +71,7 @@ Hardware ******** Detail Hardware feature for the RA8M1 MCU group can be found at `RA8M1 Group User's Manual Hardware`_ -.. figure:: ra8m1-block-diagram.jpg +.. figure:: ra8m1_block_diagram.jpg :width: 442px :align: center :alt: RA8M1 MCU group feature @@ -106,6 +106,25 @@ The below features are currently supported on Zephyr OS for EK-RA8M1 board: +-----------+------------+----------------------+ | FLASH | on-chip | flash | +-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| COUNTER | on-chip | counter | ++-----------+------------+----------------------+ +| CAN | on-chip | canfd | ++-----------+------------+----------------------+ +| USBHS | on-chip | udc | ++-----------+------------+----------------------+ +| ETHERNET | on-chip | ethernet | ++-----------+------------+----------------------+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| SDHC | on-chip | sdhc | ++-----------+------------+----------------------+ + +**Note:** + +- For using Ethernet module on EK-RA8M1, remove jumper J61 to enable Ethernet B +- For using SDHC driver on EK-RA8M1, remove jumper J61 to use with channel 0 Other hardware features are currently not supported by the port. diff --git a/boards/renesas/ek_ra8m1/doc/ra8m1-block-diagram.jpg b/boards/renesas/ek_ra8m1/doc/ra8m1_block_diagram.jpg similarity index 100% rename from boards/renesas/ek_ra8m1/doc/ra8m1-block-diagram.jpg rename to boards/renesas/ek_ra8m1/doc/ra8m1_block_diagram.jpg diff --git a/boards/renesas/ek_ra8m1/ek_ra8m1-pinctrl.dtsi b/boards/renesas/ek_ra8m1/ek_ra8m1-pinctrl.dtsi index b43c4be60ab..f3c3ec3ebd9 100644 --- a/boards/renesas/ek_ra8m1/ek_ra8m1-pinctrl.dtsi +++ b/boards/renesas/ek_ra8m1/ek_ra8m1-pinctrl.dtsi @@ -4,6 +4,30 @@ */ &pinctrl { + sci0_default: sci0_default { + group1 { + /* tx */ + psels = ; + drive-strength = "medium"; + }; + group2 { + /* rx */ + psels = ; + }; + }; + + sci2_default: sci2_default { + group1 { + /* tx */ + psels = ; + drive-strength = "medium"; + }; + group2 { + /* rx */ + psels = ; + }; + }; + sci3_default: sci3_default { group1 { /* tx */ @@ -53,4 +77,65 @@ ; }; }; + + pwm7_default: pwm7_default { + group1 { + /* GTIOC7A */ + psels = ; + }; + group2 { + /* GTIOC7B */ + psels = ; + }; + }; + + canfd0_default: canfd0_default { + group1 { + /* CRX0 CTX0 */ + psels = , + ; + drive-strength = "high"; + }; + }; + + ether_default: ether_default { + group1 { + psels = , /* ET0_MDC */ + , /* ET0_MDIO */ + , /* ET0_LINKSTA */ + , /* RMII0_TXD_EN_B */ + , /* RMII0_TXD1_BR */ + , /* RMII0_TXD0_B */ + , /* REF50CK0_B */ + , /* RMII0_RXD0_B */ + , /* RMII0_RXD1_B */ + , /* RMII0_RX_ER_B */ + ; /* RMII0_CRS_DV_B */ + drive-strength = "high"; + }; + }; + + usbhs_default: usbhs_default { + group1 { + psels = ; /* VBUS */ + drive-strength = "high"; + }; + }; + + sdhc0_default: sdhc0_default { + group1 { + psels = , /* SDCD */ + , /* SDCMD */ + , /* SDDATA0 */ + , /* SDDATA1 */ + , /* SDDATA2 */ + , /* SDDATA3 */ + ; /* SDWP */ + drive-strength = "high"; + }; + group2 { + psels = ; /* SDCLK */ + drive-strength = "highspeed-high"; + }; + }; }; diff --git a/boards/renesas/ek_ra8m1/ek_ra8m1.dts b/boards/renesas/ek_ra8m1/ek_ra8m1.dts index de64b9ecf25..96e952cd099 100644 --- a/boards/renesas/ek_ra8m1/ek_ra8m1.dts +++ b/boards/renesas/ek_ra8m1/ek_ra8m1.dts @@ -8,6 +8,7 @@ #include #include #include +#include #include "ek_ra8m1-pinctrl.dtsi" / { @@ -21,6 +22,7 @@ zephyr,console = &uart9; zephyr,shell-uart = &uart9; zephyr,entropy = &trng; + zephyr,canbus = &canfd0; }; leds { @@ -62,8 +64,61 @@ /* GND */ }; + pmod1_header: pmod-connector-1 { + compatible = "digilent,pmod"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &ioport6 12 0>, /* IO1 */ + <1 0 &ioport6 9 0>, /* IO2 */ + <2 0 &ioport6 10 0>, /* IO3 */ + <3 0 &ioport6 11 0>, /* IO4 */ + <4 0 &ioport0 6 0>, /* IO5 */ + <5 0 &ioporta 8 0>, /* IO6 */ + <6 0 &ioport6 14 0>, /* IO7 */ + <7 0 &ioport6 15 0>; /* IO8 */ + }; + + pmod2_header: pmod-connector-2 { + compatible = "digilent,pmod"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &ioporta 5 0>, /* IO1 */ + <1 0 &ioporta 3 0>, /* IO2 */ + <2 0 &ioporta 2 0>, /* IO3 */ + <3 0 &ioporta 4 0>, /* IO4 */ + <4 0 &ioport5 8 0>, /* IO5 */ + <5 0 &ioport8 9 0>, /* IO6 */ + <6 0 &ioport8 10 0>, /* IO7 */ + <7 0 &ioport8 11 0>; /* IO8 */ + }; + + buttons { + compatible = "gpio-keys"; + button0: s1 { + gpios = <&ioport0 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button switch 1"; + zephyr,code = ; + }; + button1: s2 { + gpios = <&ioport0 8 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button switch 2"; + zephyr,code = ; + }; + }; + aliases { led0 = &led1; + sw0 = &button0; + sw1 = &button1; + }; + + transceiver0: can-phy0 { + compatible = "nxp,tja1040t", "can-transceiver-gpio"; + standby-gpios = <&ioport2 7 GPIO_ACTIVE_HIGH>; + max-bitrate = <5000000>; + #phy-cells = <0>; }; }; @@ -79,21 +134,30 @@ }; &pll { - source = ; - div = ; - mul = <96 0>; - divp = ; - freqp = ; - divq = ; - freqq = ; - divr = ; - freqr = ; status = "okay"; + pllp { + status = "okay"; + }; + + pllq { + status = "okay"; + }; + + pllr { + status = "okay"; + }; }; + &sciclk { - clk-src = ; - clk-div = ; + clocks = <&pllp>; + div = <4>; + status = "okay"; +}; + +&canfdclk { + clocks = <&pll>; + div = <5>; status = "okay"; }; @@ -105,6 +169,10 @@ status = "okay"; }; +&ioport2 { + status = "okay"; +}; + &ioport3 { status = "okay"; }; @@ -121,10 +189,38 @@ status = "okay"; }; +&ioport8 { + status = "okay"; +}; + &ioport9 { status = "okay"; }; +&ioporta { + status = "okay"; +}; + +&sci0 { + pinctrl-0 = <&sci0_default>; + pinctrl-names = "default"; + status = "okay"; + uart0: uart { + current-speed = <115200>; + status = "okay"; + }; +}; + +&sci2 { + pinctrl-0 = <&sci2_default>; + pinctrl-names = "default"; + status = "okay"; + uart2: uart { + current-speed = <115200>; + status = "okay"; + }; +}; + &sci3 { pinctrl-0 = <&sci3_default>; pinctrl-names = "default"; @@ -159,6 +255,7 @@ mikrobus_serial: &uart3 {}; status = "okay"; pinctrl-0 = <&adc0_default>; pinctrl-names = "default"; + average-count = <4>; }; &trng { @@ -171,6 +268,14 @@ mikrobus_serial: &uart3 {}; status = "okay"; }; +&pwm7 { + pinctrl-0 = <&pwm7_default>; + interrupts = <40 1>, <41 1>; + interrupt-names = "gtioca", "overflow"; + pinctrl-names = "default"; + status = "okay"; +}; + &flash1 { partitions { compatible = "fixed-partitions"; @@ -183,3 +288,64 @@ mikrobus_serial: &uart3 {}; }; }; }; + +&canfd_global { + status = "okay"; + canfd0 { + pinctrl-0 = <&canfd0_default>; + pinctrl-names = "default"; + phys = <&transceiver0>; + rx-max-filters = <16>; + status = "okay"; + }; +}; + +pmod1_serial: &uart0 {}; +pmod2_serial: &uart2 {}; + +pmod_serial: &pmod1_serial {}; +pmod_header: &pmod1_header {}; + +ð { + local-mac-address = [74 90 50 B0 6D 5A]; + status = "okay"; + phy-handle = <&phy>; +}; + +&mdio { + pinctrl-0 = <ðer_default>; + pinctrl-names = "default"; + status = "okay"; + + phy: ethernet-phy@5 { + compatible = "ethernet-phy"; + reg = <5>; + status = "okay"; + }; +}; + +&usbhs { + pinctrl-0 = <&usbhs_default>; + pinctrl-names = "default"; + maximum-speed = "high-speed"; + status = "okay"; + zephyr_udc0: udc { + status = "okay"; + }; +}; + +&usbhs_phy { + phys-clock-src = "xtal"; +}; + +&port_irq12 { + interrupts = <88 12>; + status = "okay"; +}; + +&port_irq13 { + interrupts = <89 12>; + status = "okay"; +}; + +pmod_sd_shield: &sdhc0 {}; diff --git a/boards/renesas/ek_ra8m1/ek_ra8m1_defconfig b/boards/renesas/ek_ra8m1/ek_ra8m1_defconfig index dca93f2b9e0..d20f5032468 100644 --- a/boards/renesas/ek_ra8m1/ek_ra8m1_defconfig +++ b/boards/renesas/ek_ra8m1/ek_ra8m1_defconfig @@ -5,7 +5,6 @@ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=480000000 # Enable GPIO CONFIG_GPIO=y -CONFIG_PINCTRL=y # Enable Console CONFIG_SERIAL=y @@ -14,7 +13,4 @@ CONFIG_UART_INTERRUPT_DRIVEN=y CONFIG_CONSOLE=y CONFIG_BUILD_OUTPUT_HEX=y -CONFIG_BUILD_NO_GAP_FILL=y CONFIG_CLOCK_CONTROL=y - -CONFIG_FLASH=y diff --git a/boards/renesas/fpb_ra6e1/doc/fpb-ra6e1-board.webp b/boards/renesas/fpb_ra6e1/doc/fpb_ra6e1.webp similarity index 100% rename from boards/renesas/fpb_ra6e1/doc/fpb-ra6e1-board.webp rename to boards/renesas/fpb_ra6e1/doc/fpb_ra6e1.webp diff --git a/boards/renesas/fpb_ra6e1/doc/index.rst b/boards/renesas/fpb_ra6e1/doc/index.rst index 17332f0c5e2..b9df0e22f36 100644 --- a/boards/renesas/fpb_ra6e1/doc/index.rst +++ b/boards/renesas/fpb_ra6e1/doc/index.rst @@ -46,9 +46,9 @@ The key features of the FPB-RA6E1 board are categorized in three groups as follo - MCU boot configuration jumper -.. figure:: fpb-ra6e1-board.webp +.. figure:: fpb_ra6e1.webp :align: center - :alt: RA6E1 Evaluation Kit + :alt: RA6E1 Fast Prototyping Board FPB-RA6E1 Board Functional Area Definitions (Credit: Renesas Electronics Corporation) @@ -56,7 +56,7 @@ Hardware ******** Detailed hardware feature for the RA6E1 MCU group can be found at `RA6E1 Group User's Manual Hardware`_ -.. figure:: ra6e1-block-diagram.webp +.. figure:: ra6e1_block_diagram.webp :width: 442px :align: center :alt: RA6E1 MCU group feature @@ -83,6 +83,16 @@ The below features are currently supported on Zephyr OS for FPB-RA6E1 board: +-----------+------------+----------------------+ | FLASH | on-chip | flash | +-----------+------------+----------------------+ +| I2C | on-chip | i2c | ++-----------+------------+----------------------+ +| SPI | on-chip | spi | ++-----------+------------+----------------------+ +| COUNTER | on-chip | counter | ++-----------+------------+----------------------+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ Other hardware features are currently not supported by the port. diff --git a/boards/renesas/fpb_ra6e1/doc/ra6e1-block-diagram.webp b/boards/renesas/fpb_ra6e1/doc/ra6e1_block_diagram.webp similarity index 100% rename from boards/renesas/fpb_ra6e1/doc/ra6e1-block-diagram.webp rename to boards/renesas/fpb_ra6e1/doc/ra6e1_block_diagram.webp diff --git a/boards/renesas/fpb_ra6e1/fpb_ra6e1-pinctrl.dtsi b/boards/renesas/fpb_ra6e1/fpb_ra6e1-pinctrl.dtsi index 3c01cb6bec4..89628ad68be 100644 --- a/boards/renesas/fpb_ra6e1/fpb_ra6e1-pinctrl.dtsi +++ b/boards/renesas/fpb_ra6e1/fpb_ra6e1-pinctrl.dtsi @@ -11,4 +11,39 @@ ; }; }; + + iic0_default: iic0_default { + group1 { + /* SCL0 SDA0 */ + psels = , + ; + drive-strength = "medium"; + }; + }; + + spi1_default: spi1_default { + group1 { + /* MISO MOSI RSPCK SSL */ + psels = , + , + , + ; + }; + }; + + adc0_default: adc0_default { + group1 { + /* input */ + psels = ; + renesas,analog-enable; + }; + }; + + pwm1_default: pwm1_default { + group1 { + /* GTIOC1A GTIOC1B */ + psels = , + ; + }; + }; }; diff --git a/boards/renesas/fpb_ra6e1/fpb_ra6e1.dts b/boards/renesas/fpb_ra6e1/fpb_ra6e1.dts index 6f734989539..776df2f4b25 100644 --- a/boards/renesas/fpb_ra6e1/fpb_ra6e1.dts +++ b/boards/renesas/fpb_ra6e1/fpb_ra6e1.dts @@ -7,6 +7,8 @@ #include #include +#include +#include #include "fpb_ra6e1-pinctrl.dtsi" @@ -16,6 +18,7 @@ chosen { zephyr,sram = &sram0; + zephyr,flash-controller = &flash1; zephyr,flash = &flash0; zephyr,console = &uart0; zephyr,shell-uart = &uart0; @@ -33,8 +36,18 @@ }; }; + buttons { + compatible = "gpio-keys"; + button0: s1 { + gpios = <&ioport2 5 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button switch 1"; + zephyr,code = ; + }; + }; + aliases { led0 = &led1; + sw0 = &button0; }; }; @@ -48,6 +61,27 @@ }; }; +&iic0 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <91 1>, <92 1>, <93 1>, <94 1>; + interrupt-names = "rxi", "txi", "tei", "eri"; + clock-frequency = ; + pinctrl-0 = <&iic0_default>; + pinctrl-names = "default"; +}; + +&spi1 { + pinctrl-0 = <&spi1_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&ioport2 { + status = "okay"; +}; + &ioport4 { status = "okay"; }; @@ -57,26 +91,40 @@ }; &pll { - source = ; - div = ; + clocks = <&hoco>; + div = <2>; mul = <20 0>; status = "okay"; }; -&flash0 { +&flash1 { partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; - boot_partition: partition@0 { - label = "application"; - reg = <0x00000000 DT_SIZE_K(512)>; - }; - - storage_partition: partition@80000 { + storage_partition: partition@0 { label = "storage"; - reg = <0x80000 DT_SIZE_K(512)>; + reg = <0X0 DT_SIZE_K(8)>; }; }; }; + +&adc0 { + status = "okay"; + pinctrl-0 = <&adc0_default>; + pinctrl-names = "default"; +}; + +&port_irq1 { + interrupts = <41 12>; + status = "okay"; +}; + +&pwm1 { + pinctrl-0 = <&pwm1_default>; + pinctrl-names = "default"; + interrupts = <63 1>, <64 1>; + interrupt-names = "gtioca", "overflow"; + status = "okay"; +}; diff --git a/boards/renesas/fpb_ra6e1/fpb_ra6e1_defconfig b/boards/renesas/fpb_ra6e1/fpb_ra6e1_defconfig index fa7ef716d3f..4fd3e749468 100644 --- a/boards/renesas/fpb_ra6e1/fpb_ra6e1_defconfig +++ b/boards/renesas/fpb_ra6e1/fpb_ra6e1_defconfig @@ -5,10 +5,8 @@ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=200000000 # Enable GPIO CONFIG_GPIO=y -CONFIG_PINCTRL=y CONFIG_BUILD_OUTPUT_HEX=y -CONFIG_BUILD_NO_GAP_FILL=y # Enable Console CONFIG_SERIAL=y diff --git a/boards/renesas/fpb_ra6e2/doc/fpb-ra6e2-board.webp b/boards/renesas/fpb_ra6e2/doc/fpb_ra6e2.webp similarity index 100% rename from boards/renesas/fpb_ra6e2/doc/fpb-ra6e2-board.webp rename to boards/renesas/fpb_ra6e2/doc/fpb_ra6e2.webp diff --git a/boards/renesas/fpb_ra6e2/doc/index.rst b/boards/renesas/fpb_ra6e2/doc/index.rst index 21acb93f869..76e04dba216 100644 --- a/boards/renesas/fpb_ra6e2/doc/index.rst +++ b/boards/renesas/fpb_ra6e2/doc/index.rst @@ -50,7 +50,7 @@ The key features of the FPB-RA6E2 board are categorized in three groups as follo - MCU boot configuration jumper -.. figure:: fpb-ra6e2-board.webp +.. figure:: fpb_ra6e2.webp :align: center :alt: RA6E2 Fast Prototyping Board @@ -60,7 +60,7 @@ Hardware ******** Detailed hardware feature for the RA6E2 MCU group can be found at `RA6E2 Group User's Manual Hardware`_ -.. figure:: ra6e2-block-diagram.webp +.. figure:: ra6e2_block_diagram.webp :width: 442px :align: center :alt: RA6E2 MCU group feature @@ -85,6 +85,16 @@ The below features are currently supported on Zephyr OS for FPB-RA6E2 board: +-----------+------------+----------------------+ | UART | on-chip | serial | +-----------+------------+----------------------+ +| SPI | on-chip | spi | ++-----------+------------+----------------------+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| ENTROPY | on-chip | entropy | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ Other hardware features are currently not supported by the port. diff --git a/boards/renesas/fpb_ra6e2/doc/ra6e2-block-diagram.webp b/boards/renesas/fpb_ra6e2/doc/ra6e2_block_diagram.webp similarity index 100% rename from boards/renesas/fpb_ra6e2/doc/ra6e2-block-diagram.webp rename to boards/renesas/fpb_ra6e2/doc/ra6e2_block_diagram.webp diff --git a/boards/renesas/fpb_ra6e2/fpb_ra6e2-pinctrl.dtsi b/boards/renesas/fpb_ra6e2/fpb_ra6e2-pinctrl.dtsi index 851d8543bee..8d7e96e99b1 100644 --- a/boards/renesas/fpb_ra6e2/fpb_ra6e2-pinctrl.dtsi +++ b/boards/renesas/fpb_ra6e2/fpb_ra6e2-pinctrl.dtsi @@ -11,4 +11,30 @@ ; }; }; + + spi0_default: spi0_default { + group1 { + /* MISO MOSI RSPCK SSL */ + psels = , + , + , + ; + }; + }; + + adc0_default: adc0_default { + group1 { + /* input */ + psels = ; + renesas,analog-enable; + }; + }; + + pwm1_default: pwm1_default { + group1 { + /* GTIOC1A GTIOC1B */ + psels = , + ; + }; + }; }; diff --git a/boards/renesas/fpb_ra6e2/fpb_ra6e2.dts b/boards/renesas/fpb_ra6e2/fpb_ra6e2.dts index bc7baa6c5ce..6175be7aaa0 100644 --- a/boards/renesas/fpb_ra6e2/fpb_ra6e2.dts +++ b/boards/renesas/fpb_ra6e2/fpb_ra6e2.dts @@ -7,6 +7,8 @@ #include #include +#include +#include #include "fpb_ra6e2-pinctrl.dtsi" @@ -19,6 +21,7 @@ zephyr,flash = &flash0; zephyr,console = &uart0; zephyr,shell-uart = &uart0; + zephyr,entropy = &trng; }; leds { @@ -33,9 +36,19 @@ }; }; + buttons { + compatible = "gpio-keys"; + button0: s1 { + gpios = <&ioport3 4 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button switch 1"; + zephyr,code = ; + }; + }; + aliases { led0 = &led1; led1 = &led2; + sw0 = &button0; }; }; @@ -49,24 +62,29 @@ }; }; +&spi0 { + pinctrl-0 = <&spi0_default>; + pinctrl-names = "default"; + status = "okay"; +}; + &ioport2 { status = "okay"; }; +&ioport3 { + status = "okay"; +}; + &flash0 { partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; - boot_partition: partition@0 { - label = "application"; - reg = <0x00000000 DT_SIZE_K(128)>; - }; - - storage_partition: partition@20000 { + storage_partition: partition@0 { label = "storage"; - reg = <0x20000 DT_SIZE_K(128)>; + reg = <0X0 DT_SIZE_K(4)>; }; }; }; @@ -76,8 +94,32 @@ }; &pll { - source = ; - div = ; + clocks = <&hoco>; + div = <1>; mul = <10 0>; status = "okay"; }; + +&adc0 { + status = "okay"; + pinctrl-0 = <&adc0_default>; + pinctrl-names = "default"; +}; + +&port_irq9 { + interrupts = <41 12>; + status = "okay"; +}; + +&pwm1 { + pinctrl-0 = <&pwm1_default>; + pinctrl-names = "default"; + interrupts = <63 1>, <64 1>; + interrupt-names = "gtioca", "overflow"; + divider = ; + status = "okay"; +}; + +&trng { + status ="okay"; +}; diff --git a/boards/renesas/fpb_ra6e2/fpb_ra6e2_defconfig b/boards/renesas/fpb_ra6e2/fpb_ra6e2_defconfig index 92bb425cfa8..882cf699d98 100644 --- a/boards/renesas/fpb_ra6e2/fpb_ra6e2_defconfig +++ b/boards/renesas/fpb_ra6e2/fpb_ra6e2_defconfig @@ -5,7 +5,6 @@ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=200000000 # Enable GPIO CONFIG_GPIO=y -CONFIG_PINCTRL=y # Enable Console CONFIG_SERIAL=y @@ -14,5 +13,4 @@ CONFIG_UART_CONSOLE=y CONFIG_CONSOLE=y CONFIG_BUILD_OUTPUT_HEX=y -CONFIG_BUILD_NO_GAP_FILL=y CONFIG_CLOCK_CONTROL=y diff --git a/boards/renesas/mck_ra8t1/Kconfig.defconfig b/boards/renesas/mck_ra8t1/Kconfig.defconfig new file mode 100644 index 00000000000..37c1586dbb1 --- /dev/null +++ b/boards/renesas/mck_ra8t1/Kconfig.defconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_MCK_RA8T1 + +if NETWORKING + +config NET_L2_ETHERNET + default y + +endif # NETWORKING + +endif # BOARD_MCK_RA8T1 diff --git a/boards/renesas/mck_ra8t1/doc/index.rst b/boards/renesas/mck_ra8t1/doc/index.rst index f223004c969..e80028da83b 100644 --- a/boards/renesas/mck_ra8t1/doc/index.rst +++ b/boards/renesas/mck_ra8t1/doc/index.rst @@ -18,7 +18,7 @@ MCK-RA8T1 kit includes the items below: - Permanent magnet synchronous motors - Accessories (cables, standoffs, etc.) -.. figure:: mck-ra8t1-product-contents.jpg +.. figure:: mck_ra8t1_product_contents.jpg :align: center :alt: RA8T1 Evaluation Kit @@ -54,7 +54,7 @@ The specifications of the CPU board are shown below: - Ethrnet connector - microSD card connector -.. figure:: ra8t1-cpu-board-block-diagram.jpg +.. figure:: mck_ra8t1.jpg :align: center :alt: RA8T1 Evaluation Kit @@ -69,7 +69,7 @@ Hardware ******** Detail Hardware feature for the RA8T1 MCU group can be found at `RA8T1 Group User's Manual Hardware`_ -.. figure:: ra8t1-block-diagram.png +.. figure:: ra8t1_block_diagram.png :width: 442px :align: center :alt: RA8T1 MCU group feature @@ -102,6 +102,22 @@ The below features are currently supported on Zephyr OS for MCB-RA8T1 board: +--------------+------------+----------------------+ | FLASH | on-chip | flash | +--------------+------------+----------------------+ +| PWM | on-chip | pwm | ++--------------+------------+----------------------+ +| COUNTER | on-chip | counter | ++--------------+------------+----------------------+ +| CAN | on-chip | canfd | ++--------------+------------+----------------------+ +| I2C | on-chip | i2c | ++--------------+------------+----------------------+ +| ETHERNET | on-chip | ethernet | ++--------------+------------+----------------------+ +| ADC | on-chip | adc | ++--------------+------------+----------------------+ +| SDHC | on-chip | sdhc | ++--------------+------------+----------------------+ + +**Note:** For using SDHC module on EK-RA8M1, Connect microSD Card to microSD Socket (CN12) Other hardware features are currently not supported by the port. diff --git a/boards/renesas/mck_ra8t1/doc/ra8t1-cpu-board-block-diagram.jpg b/boards/renesas/mck_ra8t1/doc/mck_ra8t1.jpg similarity index 100% rename from boards/renesas/mck_ra8t1/doc/ra8t1-cpu-board-block-diagram.jpg rename to boards/renesas/mck_ra8t1/doc/mck_ra8t1.jpg diff --git a/boards/renesas/mck_ra8t1/doc/mck-ra8t1-product-contents.jpg b/boards/renesas/mck_ra8t1/doc/mck_ra8t1_product_contents.jpg similarity index 100% rename from boards/renesas/mck_ra8t1/doc/mck-ra8t1-product-contents.jpg rename to boards/renesas/mck_ra8t1/doc/mck_ra8t1_product_contents.jpg diff --git a/boards/renesas/mck_ra8t1/doc/ra8t1-block-diagram.png b/boards/renesas/mck_ra8t1/doc/ra8t1_block_diagram.png similarity index 100% rename from boards/renesas/mck_ra8t1/doc/ra8t1-block-diagram.png rename to boards/renesas/mck_ra8t1/doc/ra8t1_block_diagram.png diff --git a/boards/renesas/mck_ra8t1/mck_ra8t1-pinctrl.dtsi b/boards/renesas/mck_ra8t1/mck_ra8t1-pinctrl.dtsi index c8183975f37..5bb55bb8a0d 100644 --- a/boards/renesas/mck_ra8t1/mck_ra8t1-pinctrl.dtsi +++ b/boards/renesas/mck_ra8t1/mck_ra8t1-pinctrl.dtsi @@ -25,4 +25,74 @@ ; }; }; + + pwm2_default: pwm2_default { + group1 { + /* GTIOC2A */ + psels = ; + }; + group2 { + /* GTIOC2B */ + psels = ; + }; + }; + + canfd1_default: canfd1_default { + group1 { + /* CRX1 CTX1 */ + psels = , + ; + drive-strength = "high"; + }; + }; + + iic1_default: iic1_default { + group1 { + /* SCL1 SDA1*/ + psels = ,; + drive-strength = "medium"; + }; + }; + + ether_default: ether_default { + group1 { + psels = , /* ET0_MDC */ + , /* ET0_MDIO */ + , /* ET0_LINKSTA */ + , /* RMII0_TXD_EN_B */ + , /* RMII0_TXD1_BR */ + , /* RMII0_TXD0_B */ + , /* REF50CK0_B */ + , /* RMII0_RXD0_B */ + , /* RMII0_RXD1_B */ + , /* RMII0_RX_ER_B */ + ; /* RMII0_CRS_DV_B */ + drive-strength = "high"; + }; + }; + + adc0_default: adc0_default { + group1 { + /* input */ + psels = ; + renesas,analog-enable; + }; + }; + + sdhc0_default: sdhc0_default { + group1 { + psels = , /* SDCD */ + , /* SDCMD */ + , /* SDDATA0 */ + , /* SDDATA1 */ + , /* SDDATA2 */ + , /* SDDATA3 */ + ; /* SDWP */ + drive-strength = "high"; + }; + group2 { + psels = ; /* SDCLK */ + drive-strength = "highspeed-high"; + }; + }; }; diff --git a/boards/renesas/mck_ra8t1/mck_ra8t1.dts b/boards/renesas/mck_ra8t1/mck_ra8t1.dts index f7046d49149..d20ad5ecc4e 100644 --- a/boards/renesas/mck_ra8t1/mck_ra8t1.dts +++ b/boards/renesas/mck_ra8t1/mck_ra8t1.dts @@ -7,7 +7,7 @@ #include #include - +#include #include "mck_ra8t1-pinctrl.dtsi" / { @@ -21,6 +21,7 @@ zephyr,shell-uart = &uart3; zephyr,entropy = &trng; zephyr,flash-controller = &flash1; + zephyr,canbus = &canfd1; }; leds { @@ -45,6 +46,7 @@ aliases { led0 = &led1; + sdhc0 = &sdhc0; }; }; @@ -60,21 +62,33 @@ }; &pll { - source = ; - div = ; - mul = <80 0>; - divp = ; - freqp = ; - divq = ; - freqq = ; - divr = ; - freqr = ; status = "okay"; + pllp { + status = "okay"; + }; + + pllq { + status = "okay"; + }; + + pllr { + status = "okay"; + }; }; &sciclk { - clk-src = ; - clk-div = ; + clocks = <&pllp>; + div = <4>; + status = "okay"; +}; + +&canfdclk { + clocks = <&pll>; + div = <5>; + status = "okay"; +}; + +&ioport3 { status = "okay"; }; @@ -118,3 +132,67 @@ }; }; }; + +&pwm2 { + pinctrl-0 = <&pwm2_default>; + interrupts = <40 1>, <41 1>; + interrupt-names = "gtioca", "overflow"; + pinctrl-names = "default"; + status = "okay"; +}; + +&canfd_global { + status = "okay"; + canfd1 { + pinctrl-0 = <&canfd1_default>; + pinctrl-names = "default"; + rx-max-filters = <16>; + status = "okay"; + }; +}; + +&iic1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = ; + pinctrl-0 = <&iic1_default>; + pinctrl-names = "default"; +}; + +ð { + local-mac-address = [74 90 50 6D 81 75]; + status = "okay"; + phy-handle = <&phy>; +}; + +&mdio { + pinctrl-0 = <ðer_default>; + pinctrl-names = "default"; + status = "okay"; + + phy: ethernet-phy@5 { + compatible = "ethernet-phy"; + reg = <5>; + status = "okay"; + }; +}; + +&adc0 { + status = "okay"; + pinctrl-0 = <&adc0_default>; + pinctrl-names = "default"; + average-count = <4>; +}; + +&sdhc0 { + compatible = "renesas,ra-sdhc"; + pinctrl-0 = <&sdhc0_default>; + enable-gpios = <&ioport3 11 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + status = "okay"; + sdmmc { + compatible = "zephyr,sdmmc-disk"; + disk-name = "SD"; + status = "okay"; + }; +}; diff --git a/boards/renesas/mck_ra8t1/mck_ra8t1_defconfig b/boards/renesas/mck_ra8t1/mck_ra8t1_defconfig index 29889ab9ae6..07c0ee5f1ca 100644 --- a/boards/renesas/mck_ra8t1/mck_ra8t1_defconfig +++ b/boards/renesas/mck_ra8t1/mck_ra8t1_defconfig @@ -5,7 +5,6 @@ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=480000000 # Enable GPIO CONFIG_GPIO=y -CONFIG_PINCTRL=y # Enable Console CONFIG_SERIAL=y @@ -16,6 +15,3 @@ CONFIG_CONSOLE=y CONFIG_CLOCK_CONTROL=y CONFIG_BUILD_OUTPUT_HEX=y -CONFIG_BUILD_NO_GAP_FILL=y - -CONFIG_FLASH=y diff --git a/boards/renesas/rcar_h3ulcb/rcar_h3ulcb_r8a77951_a57.dts b/boards/renesas/rcar_h3ulcb/rcar_h3ulcb_r8a77951_a57.dts index 117b6bb4e74..fd814bc977e 100644 --- a/boards/renesas/rcar_h3ulcb/rcar_h3ulcb_r8a77951_a57.dts +++ b/boards/renesas/rcar_h3ulcb/rcar_h3ulcb_r8a77951_a57.dts @@ -66,6 +66,7 @@ pinctrl-names = "default", "uhs"; disk { compatible = "zephyr,sdmmc-disk"; + disk-name = "SD"; status = "okay"; }; @@ -93,6 +94,7 @@ pinctrl-names = "default", "uhs"; disk { compatible = "zephyr,mmc-disk"; + disk-name = "SD2"; status = "disabled"; }; bus-width = <8>; diff --git a/boards/renesas/rcar_salvator_xs/rcar_salvator_xs.dts b/boards/renesas/rcar_salvator_xs/rcar_salvator_xs.dts index bc926dfddd4..33f836f5924 100644 --- a/boards/renesas/rcar_salvator_xs/rcar_salvator_xs.dts +++ b/boards/renesas/rcar_salvator_xs/rcar_salvator_xs.dts @@ -46,6 +46,7 @@ pinctrl-names = "default", "uhs"; disk { compatible = "zephyr,mmc-disk"; + disk-name = "SD2"; status = "disabled"; }; bus-width = <8>; diff --git a/boards/renesas/rcar_spider_s4/rcar_spider_s4_r8a779f0_a55.dts b/boards/renesas/rcar_spider_s4/rcar_spider_s4_r8a779f0_a55.dts index 3a7b5c4eb82..c512a13f04b 100644 --- a/boards/renesas/rcar_spider_s4/rcar_spider_s4_r8a779f0_a55.dts +++ b/boards/renesas/rcar_spider_s4/rcar_spider_s4_r8a779f0_a55.dts @@ -41,6 +41,7 @@ pinctrl-names = "default", "uhs"; disk { compatible = "zephyr,mmc-disk"; + disk-name = "SD2"; status = "okay"; }; bus-width = <8>; diff --git a/boards/renesas/rzg3s_smarc/Kconfig.rzg3s_smarc b/boards/renesas/rzg3s_smarc/Kconfig.rzg3s_smarc new file mode 100644 index 00000000000..3a0abcb410b --- /dev/null +++ b/boards/renesas/rzg3s_smarc/Kconfig.rzg3s_smarc @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_RZG3S_SMARC + select SOC_R9A08G045S33GBG diff --git a/boards/renesas/rzg3s_smarc/board.cmake b/boards/renesas/rzg3s_smarc/board.cmake new file mode 100644 index 00000000000..1dbf0782ab0 --- /dev/null +++ b/boards/renesas/rzg3s_smarc/board.cmake @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=R9A08G045S33_M33_0" "--speed=15000") +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/renesas/rzg3s_smarc/board.yml b/boards/renesas/rzg3s_smarc/board.yml new file mode 100644 index 00000000000..97f7d9ba24f --- /dev/null +++ b/boards/renesas/rzg3s_smarc/board.yml @@ -0,0 +1,6 @@ +board: + name: rzg3s_smarc + full_name: RZ/G3S SMARC Evaluation Board Kit + vendor: renesas + socs: + - name: r9a08g045s33gbg diff --git a/boards/renesas/rzg3s_smarc/doc/index.rst b/boards/renesas/rzg3s_smarc/doc/index.rst new file mode 100644 index 00000000000..e442a836ee4 --- /dev/null +++ b/boards/renesas/rzg3s_smarc/doc/index.rst @@ -0,0 +1,234 @@ +.. zephyr:board:: rzg3s_smarc + +Overview +******** + +The Renesas RZ/G3S SMARC Evaluation Board Kit (RZ/G3S-EVKIT) consists of a SMARC v2.1 module board and a carrier board. + +* Device: RZ/G3S R9A08G045S33GBG + + * Cortex-A55 Single, Cortex-M33 x 2 + * BGA 359-pin, 14mmSq body, 0.5mm pitch + +* SMARC v2.1 Module Board Functions + + * LPDDR4 SDRAM: 1GB x 1pc + * QSPI flash memory: 128Mb x 1pc + * eMMC memory: 64GB x 1pc + * PMIC power supply RAA215300A2GNP#HA3 implemented + * microSD card x2 + * I3C connector + * JTAG connector + * ADC x8 channels + * Current monitor (USB Micro B) + +* Carrier Board Functions + + * Gigabit Ethernet x2 + * USB2.0 x2ch (OTG x1ch, Host x1ch) + * CAN-FD x2 + * microSD card x1 + * Mono speaker, Stereo headphone, Mic., and Aux.. + * PMOD x2 + * USB-Type C for power input + * PCIe Gen2 4-lane slot (G3S supports only 1-lane) + * M.2 Key E + * M.2 Key B and SIM card + * Coin cell battery holder (3.0V support) + +Hardware +******** + +The Renesas RZ/G3S MPU documentation can be found at `RZ/G3S Group Website`_ + +.. figure:: rzg3s_block_diagram.webp + :width: 600px + :align: center + :alt: RZ/G3S group feature + + RZ/G3S block diagram (Credit: Renesas Electronics Corporation) + +Supported Features +================== + +The ``rzg3s_smarc/r9a08g045s33gbg/cm33`` board target supports the ARM Cortex-M33 System Core without FPU +and the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | arch/arm | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | arch/arm | ++-----------+------------+-------------------------------------+ +| PINCTRL | on-chip | pinctrl | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial | ++-----------+------------+-------------------------------------+ + +Other hardware features are currently not supported by the port. + +Programming and Debugging +************************* + +RZ/G3S-EVKIT is designed to start different systems on different cores. +It uses Yocto as the build system to build Linux system and boot loaders +to run BL2 TF-A on Cortex-A55 System Core before starting Zephyr. The minimal steps are described below. + + 1. Follow ''2.2 Building Images'' of `SMARC EVK of RZ/G3S Linux Start-up Guide`_ to prepare the build environment. + + 2. Before build, add ``PLAT_M33_BOOT_SUPPORT=1`` to meta-renesas/meta-rzg3s/recipes-bsp/trusted-firmware-a/trusted-firmware-a.bbappend. + + .. code-block:: bash + :emphasize-lines: 6 + + require trusted-firmware-a.inc + COMPATIBLE_MACHINE_rzg3s = "(rzg3s-dev|smarc-rzg3s)" + PLATFORM_rzg3s-dev = "g3s" + EXTRA_FLAGS_rzg3s-dev = "BOARD=dev14_1_lpddr PLAT_SYSTEM_SUSPEND=vbat" + PLATFORM_smarc-rzg3s = "g3s" + EXTRA_FLAGS_smarc-rzg3s = "BOARD=smarc PLAT_SYSTEM_SUSPEND=vbat PLAT_M33_BOOT_SUPPORT=1" + + 3. Start the build: + + .. code-block:: bash + + MACHINE=smarc-rzg3s bitbake core-image-minimal + + The below necessary artifacts will be located in the build/tmp/deploy/images + + +---------------+-----------------------------+ + | Artifacts | File name | + +===============+=============================+ + | Boot loader | bl2_bp_spi-smarc-rzg3s.srec | + | | | + | | fip-smarc-rzg3s.srec | + +---------------+-----------------------------+ + | Flash Writer | FlashWriter-smarc-rzg3s.mot | + +---------------+-----------------------------+ + + 4. Follow ''4.2 Startup Procedure'' of `SMARC EVK of RZ/G3S Linux Start-up Guide`_ for power supply and board setting + at SCIF download (SW_MODE[1:4] = OFF, ON, OFF, ON) and Cortex-A55 cold boot (SW_CONFIG[1:6] = OFF, OFF, ON, OFF, OFF, OFF) + + 5. Follow ''4.3 Download Flash Writer to RAM'' of `SMARC EVK of RZ/G3S Linux Start-up Guide`_ to download Flash Writer to RAM + + 6. Follow ''4.4 Write the Bootloader'' of `SMARC EVK of RZ/G3S Linux Start-up Guide`_ to write the boot loader + to the target board by using Flash Writer. + +Applications for the ``rzg3s_smarc`` board can be built in the usual way as +documented in :ref:`build_an_application`. + +Console +======= + +The UART port for Cortex-M33 System Core can be accessed by connecting `Pmod USBUART `_ +to the upper side of ``PMOD1_3A``. + +Debugging +========= + +It is possible to load and execute a Zephyr application binary on +this board on the Cortex-M33 System Core from +the internal SRAM, using ``JLink`` debugger (:ref:`jlink-debug-host-tools`). + +.. note:: + + Currently it's required Renesas BL2 TF-A to be started on Cortex-A55 System Core + before starting Zephyr as it configures clocks and the Cortex-M33 System Core before starting it. + +Here is an example for building and debugging with the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: rzg3s_smarc/r9a08g045s33gbg/cm33 + :goals: build debug + +Flashing +======== + +Zephyr application can be flashed to QSPI storage and then loaded by +Renesas BL2 TF-A running on the Cortex-A55 System Core and starting binary on the Cortex-M33 System Core. + +The Zephyr application binary has to be converted to Motorolla S-record `SREC`_ format +which is generated automatically in Zephyr application build directory with the extension ``s19``. + +.. _SREC: https://en.wikipedia.org/wiki/SREC_(file_format) + +.. _Flashing on QSPI: + +Flashing on QSPI using Flash Writer +--------------------------------------- + +Zephyr binary has to be converted to **srec** format. + +* Download and start **Flash Writer** as described in ''4.3 Download Flash Writer to RAM'' of `SMARC EVK of RZ/G3S Linux Start-up Guide`_ +* Use **XLS2** command to flash Zephyr binary +* Input when asked: + +.. code-block:: console + + ===== Please Input Program Top Address ============ + Please Input : H'23000 + ===== Please Input Qspi Save Address === + Please Input : H'200000 + +* Then send Zephyr **s19** file from terminal (use ''ascii'' mode) +* Reboot the board in the **QSPI Boot Mode** + +.. code-block:: console + + -- Load Program to SRAM --------------- + + Flash writer for RZ/G3S Series V0.60 Jan.26,2023 + Product Code : RZ/G3S + >XLS2 + ===== Qspi writing of RZ/G2 Board Command ============= + Load Program to Spiflash + Writes to any of SPI address. + Program size & Qspi Save Address + ===== Please Input Program Top Address ============ + Please Input : H'23000 + + ===== Please Input Qspi Save Address === + Please Input : H'200000 + please send ! ('.' & CR stop load) + I Flash memory... + Erase Completed + Write to SPI Flash memory. + ======= Qspi Save Information ================= + SpiFlashMemory Stat Address : H'00200000 + SpiFlashMemory End Address : H'002098E6 + =========================================================== + +Flashing on QSPI using west +--------------------------- + +Before using ``flash`` command, the board must be set to Cortex-M33 cold boot (SW_CONFIG[1:6] = OFF, OFF, ON, OFF, OFF, ON). +After flashing, it must be set back to Cortex-A55 cold boot to run. + +The minimal version of SEGGER JLink SW which can perform flashing of QSPI memory is v7.96. + +**Note:** It's verified that we can perform flashing successfully with SEGGER JLink SW v7.98g so please use this or later +version. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: rzg3s_smarc/r9a08g045s33gbg/cm33 + :goals: build flash + :compact: + +References +********** + +.. target-notes:: + +.. _RZ/G3S Group Website: + https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/rzg3s-general-purpose-microprocessors-single-core-arm-cortex-a55-11-ghz-cpu-and-dual-core-cortex-m33-250 + +.. _RZG3S-EVKIT Website: + https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/rzg3s-evkit-evaluation-board-kit-rzg3s-mpu + +.. _SMARC EVK of RZ/G3S Linux Start-up Guide: + https://www.renesas.com/us/en/document/gde/smarc-evk-rzg3s-linux-start-guide-rev104 diff --git a/boards/renesas/rzg3s_smarc/doc/rzg3s_block_diagram.webp b/boards/renesas/rzg3s_smarc/doc/rzg3s_block_diagram.webp new file mode 100644 index 00000000000..ae3022760bc Binary files /dev/null and b/boards/renesas/rzg3s_smarc/doc/rzg3s_block_diagram.webp differ diff --git a/boards/renesas/rzg3s_smarc/doc/rzg3s_smarc.webp b/boards/renesas/rzg3s_smarc/doc/rzg3s_smarc.webp new file mode 100644 index 00000000000..1d81bb7a615 Binary files /dev/null and b/boards/renesas/rzg3s_smarc/doc/rzg3s_smarc.webp differ diff --git a/boards/renesas/rzg3s_smarc/rzg3s_smarc-pinctrl.dtsi b/boards/renesas/rzg3s_smarc/rzg3s_smarc-pinctrl.dtsi new file mode 100644 index 00000000000..aa8ae25d057 --- /dev/null +++ b/boards/renesas/rzg3s_smarc/rzg3s_smarc-pinctrl.dtsi @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2024 EPAM Systems + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +&pinctrl { + /omit-if-no-ref/ scif0_pins: scif0 { + scif0-pinmux { + pinmux = , /* TXD */ + ; /* RXD */ + }; + }; + + /omit-if-no-ref/ scif1_pins: scif1 { + scif1-pinmux { + pinmux = , /* TXD */ + ; /* RXD */ + }; + }; + + /omit-if-no-ref/ scif3_pins: scif3 { + scif3-pinmux { + pinmux = , /* TXD */ + ; /* RXD */ + }; + }; + + /omit-if-no-ref/ scif5_pins: scif5 { + scif5-pinmux { + pinmux = , /* RXD */ + ; /* TXD */ + }; + }; +}; diff --git a/boards/renesas/rzg3s_smarc/rzg3s_smarc_r9a08g045s33gbg_cm33.dts b/boards/renesas/rzg3s_smarc/rzg3s_smarc_r9a08g045s33gbg_cm33.dts new file mode 100644 index 00000000000..81210407ae4 --- /dev/null +++ b/boards/renesas/rzg3s_smarc/rzg3s_smarc_r9a08g045s33gbg_cm33.dts @@ -0,0 +1,92 @@ +/* + * Copyright (c) 2024 EPAM Systems + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include "rzg3s_smarc-pinctrl.dtsi" + +/ { + model = "Renesas RZ/G3S SMARC"; + compatible = "renesas,rzg3s-smarc"; + + chosen { + zephyr,sram = &sram_mcpu0; + zephyr,flash = &spi_flash; + zephyr,console = &scif1; + zephyr,shell-uart = &scif1; + }; + + aliases { + sw0 = &sw_1; + sw1 = &sw_2; + sw2 = &sw_3; + }; + + buttons { + compatible = "gpio-keys"; + + sw_1: button_1 { + gpios = <&gpio18 0 GPIO_ACTIVE_LOW>; + label = "SW1"; + zephyr,code = ; + }; + + sw_2: button_2 { + gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; + label = "SW2"; + zephyr,code = ; + }; + + sw_3: button_3 { + gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; + label = "SW3"; + zephyr,code = ; + }; + }; + + ddr: memory@60000000 { + compatible ="zephyr,memory-region", "mmio-sram"; + reg = <0x60000000 DT_SIZE_M(16)>; + zephyr,memory-region = "DDR"; + zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>; + }; + + sram_mcpu0: memory@23000 { + compatible = "mmio-sram"; + reg = <0x23000 DT_SIZE_K(243)>; + }; + + /* + * This node is defined to enable west flash support. + * The base addr and size depends on ATF-F configuration, which is running on Cortex-A55 and + * loading Zephyr app from xSPI flash. + */ + spi_flash: memory@80200000 { + compatible = "mmio-sram"; + reg = <0x80200000 DT_SIZE_K(256)>; + }; + +}; + +&scif1 { + current-speed = <115200>; + pinctrl-0 = <&scif1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&gpio0{ + status = "okay"; +}; + +&gpio18{ + status = "okay"; +}; diff --git a/boards/renesas/rzg3s_smarc/rzg3s_smarc_r9a08g045s33gbg_cm33.yaml b/boards/renesas/rzg3s_smarc/rzg3s_smarc_r9a08g045s33gbg_cm33.yaml new file mode 100644 index 00000000000..06285a945de --- /dev/null +++ b/boards/renesas/rzg3s_smarc/rzg3s_smarc_r9a08g045s33gbg_cm33.yaml @@ -0,0 +1,10 @@ +identifier: rzg3s_smarc/r9a08g045s33gbg/cm33 +name: Cortex-M33 for Renesas RZ/G3S SMARC +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb +supported: + - uart + - gpio diff --git a/boards/renesas/rzg3s_smarc/rzg3s_smarc_r9a08g045s33gbg_cm33_defconfig b/boards/renesas/rzg3s_smarc/rzg3s_smarc_r9a08g045s33gbg_cm33_defconfig new file mode 100644 index 00000000000..b06a719875e --- /dev/null +++ b/boards/renesas/rzg3s_smarc/rzg3s_smarc_r9a08g045s33gbg_cm33_defconfig @@ -0,0 +1,12 @@ +# Copyright (c) 2024 EPAM Systems +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_XIP=n + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=ys +CONFIG_UART_CONSOLE=y diff --git a/boards/renesas/rzt2m_starterkit/doc/index.rst b/boards/renesas/rzt2m_starterkit/doc/index.rst index eecaa1bc3c6..69f6c532700 100644 --- a/boards/renesas/rzt2m_starterkit/doc/index.rst +++ b/boards/renesas/rzt2m_starterkit/doc/index.rst @@ -95,4 +95,6 @@ Connect GDB to the server and load an application: References ********** +.. target-notes:: + .. _RZT2M Product page: https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/rzt2m-high-performance-multi-function-mpu-realizing-high-speed-processing-and-high-precision-control diff --git a/boards/renesas/rzt2m_starterkit/rzt2m_starter_kit_renesas_rzt2m.dts b/boards/renesas/rzt2m_starterkit/rzt2m_starter_kit_renesas_rzt2m.dts index a34558ec014..717c21c0cda 100644 --- a/boards/renesas/rzt2m_starterkit/rzt2m_starter_kit_renesas_rzt2m.dts +++ b/boards/renesas/rzt2m_starterkit/rzt2m_starter_kit_renesas_rzt2m.dts @@ -7,6 +7,7 @@ /dts-v1/; #include #include +#include / { model = "RZT/2M Starter Kit"; @@ -48,10 +49,12 @@ sw1: sw1 { label = "sw1"; gpios = <&gpio10 5 0>; + zephyr,code = ; }; sw2: sw2 { label = "sw2"; gpios = <&gpio16 3 0>; + zephyr,code = ; }; }; }; diff --git a/boards/renode/cortex_r8_virtual/cortex_r8_virtual.yaml b/boards/renode/cortex_r8_virtual/cortex_r8_virtual.yaml index 8d888e8806c..36a60b9ff9a 100644 --- a/boards/renode/cortex_r8_virtual/cortex_r8_virtual.yaml +++ b/boards/renode/cortex_r8_virtual/cortex_r8_virtual.yaml @@ -5,8 +5,9 @@ arch: arm toolchain: - zephyr ram: 131072 -simulation: renode -simulation_exec: renode +simulation: + - name: renode + exec: renode testing: ignore_tags: - net diff --git a/boards/renode/cortex_r8_virtual/doc/index.rst b/boards/renode/cortex_r8_virtual/doc/index.rst index 07a18a77650..8691724fcea 100644 --- a/boards/renode/cortex_r8_virtual/doc/index.rst +++ b/boards/renode/cortex_r8_virtual/doc/index.rst @@ -1,7 +1,4 @@ -.. _cortex_r8_virtual: - -Cortex-R8 Virtual -################# +.. zephyr:board:: cortex_r8_virtual Overview ******** diff --git a/boards/renode/riscv32_virtual/doc/index.rst b/boards/renode/riscv32_virtual/doc/index.rst index a53384f5331..478260d2689 100644 --- a/boards/renode/riscv32_virtual/doc/index.rst +++ b/boards/renode/riscv32_virtual/doc/index.rst @@ -1,7 +1,4 @@ -.. _riscv32-virtual: - -RISCV32 Virtual -############### +.. zephyr:board:: riscv32_virtual Overview ******** diff --git a/boards/renode/riscv32_virtual/riscv32_virtual.yaml b/boards/renode/riscv32_virtual/riscv32_virtual.yaml index 64cab1f32ba..6b2f85d5f88 100644 --- a/boards/renode/riscv32_virtual/riscv32_virtual.yaml +++ b/boards/renode/riscv32_virtual/riscv32_virtual.yaml @@ -6,8 +6,9 @@ toolchain: - zephyr ram: 4096 flash: 4096 -simulation: renode -simulation_exec: renode +simulation: + - name: renode + exec: renode testing: ignore_tags: - net diff --git a/boards/ronoth/lodev/doc/img/lodev.jpg b/boards/ronoth/lodev/doc/img/ronoth_lodev.jpg similarity index 100% rename from boards/ronoth/lodev/doc/img/lodev.jpg rename to boards/ronoth/lodev/doc/img/ronoth_lodev.jpg diff --git a/boards/ronoth/lodev/doc/index.rst b/boards/ronoth/lodev/doc/index.rst index 58f0756ecb3..bce64d4faa1 100644 --- a/boards/ronoth/lodev/doc/index.rst +++ b/boards/ronoth/lodev/doc/index.rst @@ -1,7 +1,4 @@ -.. _ronoth_lodev: - -Ronoth LoDev -############ +.. zephyr:board:: ronoth_lodev ======== Overview @@ -16,12 +13,6 @@ and a +20 dBm power amplifier. Refer to `AcSIP S76S Product Information Brief`_ Zephyr applications may use the **ronoth_lodev** configuration to run on this board. -.. figure:: img/lodev.jpg - :align: center - :alt: Image of Ronoth LoDev open source development board containing S76S system on a chip - - Ronoth LoDev - `Board design files`_ are available on GitHub. ================ diff --git a/boards/ronoth/lodev/ronoth_lodev.dts b/boards/ronoth/lodev/ronoth_lodev.dts index 024e71a7210..315f58fa2c6 100644 --- a/boards/ronoth/lodev/ronoth_lodev.dts +++ b/boards/ronoth/lodev/ronoth_lodev.dts @@ -163,7 +163,7 @@ &adc1 { pinctrl-0 = <&adc_in0_pa0>; pinctrl-names = "default"; - st,adc-clock-source = ; + st,adc-clock-source = "SYNC"; st,adc-prescaler = <4>; status = "okay"; }; diff --git a/boards/ruuvi/ruuvitag/Kconfig.defconfig b/boards/ruuvi/ruuvitag/Kconfig.defconfig index 237d564c746..4b9d1f8360f 100644 --- a/boards/ruuvi/ruuvitag/Kconfig.defconfig +++ b/boards/ruuvi/ruuvitag/Kconfig.defconfig @@ -8,7 +8,4 @@ if BOARD_RUUVI_RUUVITAG config SPI default y -config BT_CTLR - default BT - endif # BOARD_RUUVI_RUUVITAG diff --git a/boards/ruuvi/ruuvitag/doc/index.rst b/boards/ruuvi/ruuvitag/doc/index.rst index 42348b8a387..946b9549468 100644 --- a/boards/ruuvi/ruuvitag/doc/index.rst +++ b/boards/ruuvi/ruuvitag/doc/index.rst @@ -1,7 +1,4 @@ -.. _ruuvi_ruuvitag: - -Ruuvi RuuviTag -############## +.. zephyr:board:: ruuvi_ruuvitag Overview ******** @@ -10,12 +7,6 @@ RuuviTag is an advanced battery-operated open-source Bluetooth enabled sensor beacon platform capable of sending temperature, humidity, pressure, and motion information over Bluetooth Low Energy. -.. figure:: img/ruuvitag.jpg - :align: center - :alt: RUUVI RuuviTag - - RUUVI RuuviTag (Credit: https://ruuvi.com/) - More information about the board can be found at the `ruuvitag website`_. diff --git a/boards/ruuvi/ruuvitag/ruuvi_ruuvitag_defconfig b/boards/ruuvi/ruuvitag/ruuvi_ruuvitag_defconfig index 9ece16276d2..9e5e8d4d914 100644 --- a/boards/ruuvi/ruuvitag/ruuvi_ruuvitag_defconfig +++ b/boards/ruuvi/ruuvitag/ruuvi_ruuvitag_defconfig @@ -14,5 +14,3 @@ CONFIG_USE_SEGGER_RTT=y # Enable GPIO CONFIG_GPIO=y - -CONFIG_PINCTRL=y diff --git a/boards/sc/scobc_module1/doc/index.rst b/boards/sc/scobc_module1/doc/index.rst index 260a062692f..52e8000b1b8 100644 --- a/boards/sc/scobc_module1/doc/index.rst +++ b/boards/sc/scobc_module1/doc/index.rst @@ -1,7 +1,4 @@ -.. _scobc_module1: - -Space Cubics OBC module 1 -######################### +.. zephyr:board:: scobc_module1 Overview ******** @@ -10,12 +7,6 @@ Overview especially for 3U CubeSats. The board is based on Xilinx Artix-7 FPGA and implements ARM Cortex M3 as the main CPU. -.. figure:: scobc.jpg - :align: center - :alt: Space Cubics OBC module 1 - - Space Cubics OBC module 1 - It is designed to survive in the severe space environment, extreme temperature, vacuum, and space radiation. diff --git a/boards/seagate/legend/legend.dts b/boards/seagate/legend/legend.dts index d230345dd07..cb576ed09dd 100644 --- a/boards/seagate/legend/legend.dts +++ b/boards/seagate/legend/legend.dts @@ -137,7 +137,7 @@ label = "product-info"; reg = <0x00000000 DT_SIZE_K(4)>; }; - led_das: partition@10000 { + led_das: partition@1000 { label = "led-das"; reg = <0x00001000 DT_SIZE_K(60)>; }; diff --git a/boards/seco/stm32f3_seco_d23/doc/index.rst b/boards/seco/stm32f3_seco_d23/doc/index.rst index bc2626767f0..03e0bf82586 100644 --- a/boards/seco/stm32f3_seco_d23/doc/index.rst +++ b/boards/seco/stm32f3_seco_d23/doc/index.rst @@ -1,7 +1,4 @@ -.. _stm32f3_seco_d23_board: - -SECO SBC-3.5-PX30 (JUNO - D23) (STM32F302) -########################################## +.. zephyr:board:: stm32f3_seco_d23 Overview ******** @@ -21,13 +18,6 @@ The audio functionalities are managed by the AudioCodec embedded in the RK-809 PMIC. SBC-3.5-PX30 board is completed by a series of connectors with various interfaces (UART, SPI, I2C) managed by the microcontroller STM32F302VCT6. -.. image:: img/stm32f3_seco_d23.jpg - :align: center - :alt: SECO SBC-3.5-PX30 - -More information about the board can be found at the -`SECO SBC-3.5-PX30 website`_. - Hardware ******** diff --git a/boards/seeed/lora_e5_dev_board/doc/lora_e5_dev_board.rst b/boards/seeed/lora_e5_dev_board/doc/lora_e5_dev_board.rst index ca234210734..9c2071abd4f 100644 --- a/boards/seeed/lora_e5_dev_board/doc/lora_e5_dev_board.rst +++ b/boards/seeed/lora_e5_dev_board/doc/lora_e5_dev_board.rst @@ -1,7 +1,4 @@ -.. _lora_e5_dev_board: - -Seeed Studio LoRa-E5 Dev Board -############################## +.. zephyr:board:: lora_e5_dev_board Overview ******** @@ -13,10 +10,6 @@ The LoRa-E5-HF STM32WLE5JC Module supports multiple LPWAN protocols on the All GPIOs of the LoRa-E5 Module are laid out supporting various data protocols and interfaces including RS-485 and Grove. -.. image:: img/lora_e5_dev_board.jpg - :align: center - :alt: LoRa-E5 Dev board - Hardware ******** diff --git a/boards/seeed/lora_e5_dev_board/lora_e5_dev_board.dts b/boards/seeed/lora_e5_dev_board/lora_e5_dev_board.dts index 64ea2f84726..f3df8911ee8 100644 --- a/boards/seeed/lora_e5_dev_board/lora_e5_dev_board.dts +++ b/boards/seeed/lora_e5_dev_board/lora_e5_dev_board.dts @@ -157,7 +157,7 @@ stm32_lp_tick_source: &lptim1 { &adc1 { pinctrl-0 = <&adc_in2_pb3>; pinctrl-names = "default"; - st,adc-clock-source = ; + st,adc-clock-source = "SYNC"; st,adc-prescaler = <4>; status = "okay"; }; diff --git a/boards/seeed/lora_e5_mini/doc/index.rst b/boards/seeed/lora_e5_mini/doc/index.rst index 78227fcb62b..05e94cdaf3a 100644 --- a/boards/seeed/lora_e5_mini/doc/index.rst +++ b/boards/seeed/lora_e5_mini/doc/index.rst @@ -1,7 +1,4 @@ -.. _lora_e5_mini: - -Seeed Studio LoRa-E5 mini -######################### +.. zephyr:board:: lora_e5_mini Overview ******** @@ -10,10 +7,6 @@ LoRa-E5 mini is a compacted-sized development board suitable for the rapid testing and building of small-sized LoRa device, exposing all capabilities of Seeed Studio LoRa-E5 STM32WLE5JC module. -.. image:: img/lora_e5_mini.jpg - :align: center - :alt: LoRa-E5 mini - Hardware ******** diff --git a/boards/seeed/seeeduino_xiao/doc/index.rst b/boards/seeed/seeeduino_xiao/doc/index.rst index 48003fdb63c..7dc905e39b3 100644 --- a/boards/seeed/seeeduino_xiao/doc/index.rst +++ b/boards/seeed/seeeduino_xiao/doc/index.rst @@ -1,7 +1,4 @@ -.. _seeeduino_xiao: - -Seeeduino XIAO -############## +.. zephyr:board:: seeeduino_xiao Overview ******** @@ -10,10 +7,6 @@ The Seeeduino XIAO is a tiny (20 mm x 17.5 mm) ARM development board with onboard LEDs, USB port, and range of I/O broken out onto 14 pins. -.. image:: img/seeeduino_xiao.jpg - :align: center - :alt: Seeeduino XIAO - Hardware ******** diff --git a/boards/seeed/seeeduino_xiao/seeeduino_xiao.yaml b/boards/seeed/seeeduino_xiao/seeeduino_xiao.yaml index b3532949edd..4330f0a754a 100644 --- a/boards/seeed/seeeduino_xiao/seeeduino_xiao.yaml +++ b/boards/seeed/seeeduino_xiao/seeeduino_xiao.yaml @@ -16,7 +16,6 @@ supported: - i2c - spi - uart - - usb - usb_device - watchdog vendor: seeed diff --git a/boards/seeed/wio_terminal/Kconfig.defconfig b/boards/seeed/wio_terminal/Kconfig.defconfig index 4b742f1a228..3ff8b296015 100644 --- a/boards/seeed/wio_terminal/Kconfig.defconfig +++ b/boards/seeed/wio_terminal/Kconfig.defconfig @@ -3,5 +3,7 @@ # SPDX-License-Identifier: Apache-2.0 -config LV_COLOR_16_SWAP +configdefault LV_COLOR_16_SWAP default y if LVGL + +source "boards/common/usb/Kconfig.cdc_acm_serial.defconfig" diff --git a/boards/seeed/wio_terminal/doc/index.rst b/boards/seeed/wio_terminal/doc/index.rst index f640f11b445..736d3cb6984 100644 --- a/boards/seeed/wio_terminal/doc/index.rst +++ b/boards/seeed/wio_terminal/doc/index.rst @@ -1,7 +1,4 @@ -.. _wio_terminal: - -Wio Terminal -############ +.. zephyr:board:: wio_terminal Overview ******** @@ -11,11 +8,6 @@ wireless connectivity (2.4G/5G dual-band Wi-Fi and BLE 5.0), LCD display, USB C port, FPC connector, microSD card slot, Raspberry Pi compatible 40-pins header and 2 Grove connectors. -.. image:: img/wio_terminal.png - :width: 500px - :align: center - :alt: Seeed Studio Wio Terminal - Hardware ******** diff --git a/boards/seeed/wio_terminal/wio_terminal.dts b/boards/seeed/wio_terminal/wio_terminal.dts index 42df242515a..c04feb0b14a 100644 --- a/boards/seeed/wio_terminal/wio_terminal.dts +++ b/boards/seeed/wio_terminal/wio_terminal.dts @@ -18,8 +18,6 @@ chosen { zephyr,sram = &sram0; zephyr,flash = &flash0; - zephyr,console = &wio_terminal_console; - zephyr,shell-uart = &wio_terminal_console; zephyr,code-partition = &code_partition; zephyr,display = &ili9341; }; @@ -277,6 +275,7 @@ spi-max-frequency = <24000000>; mmc { compatible = "zephyr,sdmmc-disk"; + disk-name = "SD"; }; }; }; @@ -299,8 +298,6 @@ zephyr_udc0: &usb0 { status = "okay"; pinctrl-0 = <&usb_dc_default>; pinctrl-names = "default"; - - wio_terminal_console: wio_terminal_console { - compatible = "zephyr,cdc-acm-uart"; - }; }; + +#include <../boards/common/usb/cdc_acm_serial.dtsi> diff --git a/boards/seeed/wio_terminal/wio_terminal_defconfig b/boards/seeed/wio_terminal/wio_terminal_defconfig index 20852ef411e..e44adbcbb67 100644 --- a/boards/seeed/wio_terminal/wio_terminal_defconfig +++ b/boards/seeed/wio_terminal/wio_terminal_defconfig @@ -14,16 +14,3 @@ CONFIG_REGULATOR=y CONFIG_BOOTLOADER_BOSSA=y CONFIG_BOOTLOADER_BOSSA_ADAFRUIT_UF2=y CONFIG_BUILD_OUTPUT_UF2=y - -# Console over USB CDC-ACM -CONFIG_SERIAL=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_USB_DEVICE_STACK=y -CONFIG_USB_DEVICE_INITIALIZE_AT_BOOT=y -CONFIG_USB_DEVICE_VID=0x2886 -CONFIG_USB_DEVICE_PID=0x802D -CONFIG_USB_DEVICE_MANUFACTURER="Seeed Studio" -CONFIG_USB_DEVICE_PRODUCT="Wio Terminal" -CONFIG_USB_CDC_ACM_LOG_LEVEL_OFF=y diff --git a/boards/seeed/xiao_ble/Kconfig.defconfig b/boards/seeed/xiao_ble/Kconfig.defconfig index d02785ec152..3bc7ae6721f 100644 --- a/boards/seeed/xiao_ble/Kconfig.defconfig +++ b/boards/seeed/xiao_ble/Kconfig.defconfig @@ -5,17 +5,6 @@ if BOARD_XIAO_BLE -config BT_CTLR - default BT - -if USB_DEVICE_STACK - -config UART_CONSOLE - default CONSOLE - -config USB_DEVICE_INITIALIZE_AT_BOOT - default y - -endif # USB_DEVICE_STACK +source "boards/common/usb/Kconfig.cdc_acm_serial.defconfig" endif # BOARD_XIAO_BLE diff --git a/boards/seeed/xiao_ble/doc/index.rst b/boards/seeed/xiao_ble/doc/index.rst index c33d786e024..831eb872a9d 100644 --- a/boards/seeed/xiao_ble/doc/index.rst +++ b/boards/seeed/xiao_ble/doc/index.rst @@ -1,7 +1,4 @@ -.. _xiao_ble: - -XIAO BLE (Sense) -################ +.. zephyr:board:: xiao_ble Overview ******** @@ -10,10 +7,6 @@ The Seeed XIAO BLE (Sense) is a tiny (21 mm x 17.5 mm) Nordic Semiconductor nRF52840 ARM Cortex-M4F development board with onboard LEDs, USB port, QSPI flash, battery charger, and range of I/O broken out into 14 pins. -.. figure:: img/xiao_ble.jpg - :align: center - :alt: XIAO BLE - Hardware ******** diff --git a/boards/seeed/xiao_ble/xiao_ble_common.dtsi b/boards/seeed/xiao_ble/xiao_ble_common.dtsi index db00fbf1368..7b87b6db76f 100644 --- a/boards/seeed/xiao_ble/xiao_ble_common.dtsi +++ b/boards/seeed/xiao_ble/xiao_ble_common.dtsi @@ -6,19 +6,12 @@ */ #include +#include #include "xiao_ble-pinctrl.dtsi" #include "seeed_xiao_connector.dtsi" / { chosen { - zephyr,console = &usb_cdc_acm_uart; - zephyr,shell-uart = &usb_cdc_acm_uart; - zephyr,uart-mcumgr = &usb_cdc_acm_uart; - zephyr,bt-mon-uart = &usb_cdc_acm_uart; - zephyr,bt-c2h-uart = &usb_cdc_acm_uart; - zephyr,sram = &sram0; - zephyr,flash = &flash0; - zephyr,code-partition = &code_partition; zephyr,ieee802154 = &ieee802154; }; @@ -145,46 +138,9 @@ status = "okay"; }; -&flash0 { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - sd_partition: partition@0 { - label = "softdevice"; - reg = <0x00000000 0x00027000>; - }; - - code_partition: partition@27000 { - label = "code_partition"; - reg = <0x00027000 0x000c5000>; - }; - - /* - * The flash starting at 0x000ec000 and ending at - * 0x000f3fff is reserved for use by the application. - * - * Storage partition will be used by FCB/LittleFS/NVS - * if enabled. - */ - storage_partition: partition@ec000 { - label = "storage"; - reg = <0x000ec000 0x00008000>; - }; - - boot_partition: partition@f4000 { - label = "adafruit_boot"; - reg = <0x000f4000 0x0000c000>; - }; - }; -}; - zephyr_udc0: &usbd { compatible = "nordic,nrf-usbd"; status = "okay"; - - usb_cdc_acm_uart: cdc-acm-uart { - compatible = "zephyr,cdc-acm-uart"; - }; }; + +#include <../boards/common/usb/cdc_acm_serial.dtsi> diff --git a/boards/seeed/xiao_ble/xiao_ble_defconfig b/boards/seeed/xiao_ble/xiao_ble_defconfig index 84eb3e97f22..725c581b364 100644 --- a/boards/seeed/xiao_ble/xiao_ble_defconfig +++ b/boards/seeed/xiao_ble/xiao_ble_defconfig @@ -15,12 +15,6 @@ CONFIG_SERIAL=y # Enable console CONFIG_CONSOLE=y -# Logger cannot use itself to log -CONFIG_USB_CDC_ACM_LOG_LEVEL_OFF=y - -# Enable USB -CONFIG_USB_DEVICE_STACK=y - # Build UF2 by default, supported by the Adafruit nRF52 Bootloader CONFIG_BUILD_OUTPUT_UF2=y CONFIG_USE_DT_CODE_PARTITION=y diff --git a/boards/seeed/xiao_ble/xiao_ble_nrf52840_sense_defconfig b/boards/seeed/xiao_ble/xiao_ble_nrf52840_sense_defconfig index 027dd93e73b..37b63403a6d 100644 --- a/boards/seeed/xiao_ble/xiao_ble_nrf52840_sense_defconfig +++ b/boards/seeed/xiao_ble/xiao_ble_nrf52840_sense_defconfig @@ -15,12 +15,6 @@ CONFIG_SERIAL=y # Enable console CONFIG_CONSOLE=y -# Logger cannot use itself to log -CONFIG_USB_CDC_ACM_LOG_LEVEL_OFF=y - -# Enable USB -CONFIG_USB_DEVICE_STACK=y - # Build UF2 by default, supported by the Adafruit nRF52 Bootloader CONFIG_BUILD_OUTPUT_UF2=y CONFIG_USE_DT_CODE_PARTITION=y diff --git a/boards/seeed/xiao_esp32c3/Kconfig b/boards/seeed/xiao_esp32c3/Kconfig new file mode 100644 index 00000000000..c6a99b1032d --- /dev/null +++ b/boards/seeed/xiao_esp32c3/Kconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 4096 diff --git a/boards/seeed/xiao_esp32c3/Kconfig.defconfig b/boards/seeed/xiao_esp32c3/Kconfig.defconfig deleted file mode 100644 index 4171bb04bc2..00000000000 --- a/boards/seeed/xiao_esp32c3/Kconfig.defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright 2022 Google LLC -# SPDX-License-Identifier: Apache-2.0 - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 65535 if WIFI && BT - default 51200 if WIFI - default 40960 if BT - default 4096 diff --git a/boards/seeed/xiao_esp32c3/Kconfig.xiao_esp32c3 b/boards/seeed/xiao_esp32c3/Kconfig.xiao_esp32c3 index e4db49fc4a6..7a31aa29252 100644 --- a/boards/seeed/xiao_esp32c3/Kconfig.xiao_esp32c3 +++ b/boards/seeed/xiao_esp32c3/Kconfig.xiao_esp32c3 @@ -2,4 +2,4 @@ # SPDX-License-Identifier: Apache-2.0 config BOARD_XIAO_ESP32C3 - select SOC_ESP32C3_FX4 + select SOC_ESP32C3_FN4 diff --git a/boards/seeed/xiao_esp32c3/doc/index.rst b/boards/seeed/xiao_esp32c3/doc/index.rst index 48ce9ddae0d..fa9811661a4 100644 --- a/boards/seeed/xiao_esp32c3/doc/index.rst +++ b/boards/seeed/xiao_esp32c3/doc/index.rst @@ -1,7 +1,4 @@ -.. _xiao_esp32c3: - -XIAO ESP32C3 -############ +.. zephyr:board:: xiao_esp32c3 Overview ******** @@ -11,12 +8,6 @@ Espressif ESP32-C3 WiFi/Bluetooth dual-mode chip. For more details see the `Seeed Studio XIAO ESP32C3`_ wiki page. -.. figure:: img/xiao_esp32c.jpg - :align: center - :alt: XIAO ESP32C3 - - XIAO ESP32C3 - Hardware ******** diff --git a/boards/seeed/xiao_esp32c3/xiao_esp32c3.dts b/boards/seeed/xiao_esp32c3/xiao_esp32c3.dts index 68687958b8a..606ec381f82 100644 --- a/boards/seeed/xiao_esp32c3/xiao_esp32c3.dts +++ b/boards/seeed/xiao_esp32c3/xiao_esp32c3.dts @@ -9,13 +9,14 @@ #include #include "xiao_esp32c3-pinctrl.dtsi" #include "seeed_xiao_connector.dtsi" +#include / { model = "Seeed XIAO ESP32C3"; compatible = "seeed,xiao-esp32c3"; chosen { - zephyr,sram = &sram0; + zephyr,sram = &sram1; zephyr,console = &usb_serial; zephyr,shell-uart = &usb_serial; zephyr,flash = &flash0; @@ -86,40 +87,6 @@ status = "okay"; }; -&flash0 { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x0000F000>; - read-only; - }; - - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 0x00100000>; - }; - - slot1_partition: partition@110000 { - label = "image-1"; - reg = <0x00110000 0x00100000>; - }; - - scratch_partition: partition@210000 { - label = "image-scratch"; - reg = <0x00210000 0x00040000>; - }; - - storage_partition: partition@250000 { - label = "storage"; - reg = <0x00250000 0x00006000>; - }; - }; -}; - &esp32_bt_hci { status = "okay"; }; diff --git a/boards/seeed/xiao_esp32c3/xiao_esp32c3.yaml b/boards/seeed/xiao_esp32c3/xiao_esp32c3.yaml index 1d762f6f2b2..bacf2a681bd 100644 --- a/boards/seeed/xiao_esp32c3/xiao_esp32c3.yaml +++ b/boards/seeed/xiao_esp32c3/xiao_esp32c3.yaml @@ -11,8 +11,4 @@ supported: - uart - watchdog - can -testing: - ignore_tags: - - net - - bluetooth vendor: seeed diff --git a/boards/seeed/xiao_esp32c6/Kconfig b/boards/seeed/xiao_esp32c6/Kconfig new file mode 100644 index 00000000000..bc76c90de06 --- /dev/null +++ b/boards/seeed/xiao_esp32c6/Kconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Mario Paja +# SPDX-License-Identifier: Apache-2.0 + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 4096 diff --git a/boards/seeed/xiao_esp32c6/Kconfig.sysbuild b/boards/seeed/xiao_esp32c6/Kconfig.sysbuild new file mode 100644 index 00000000000..543becaa4f6 --- /dev/null +++ b/boards/seeed/xiao_esp32c6/Kconfig.sysbuild @@ -0,0 +1,10 @@ +# Copyright (c) 2024 Mario Paja +# SPDX-License-Identifier: Apache-2.0 + +choice BOOTLOADER + default BOOTLOADER_MCUBOOT +endchoice + +choice BOOT_SIGNATURE_TYPE + default BOOT_SIGNATURE_TYPE_NONE +endchoice diff --git a/boards/seeed/xiao_esp32c6/Kconfig.xiao_esp32c6 b/boards/seeed/xiao_esp32c6/Kconfig.xiao_esp32c6 new file mode 100644 index 00000000000..34fc9fe1b5e --- /dev/null +++ b/boards/seeed/xiao_esp32c6/Kconfig.xiao_esp32c6 @@ -0,0 +1,7 @@ +# XIAO ESP32C6 board configuration + +# Copyright (c) 2024 Mario Paja +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_XIAO_ESP32C6 + select SOC_ESP32_C6_WROOM_1U_N4 diff --git a/boards/seeed/xiao_esp32c6/board.cmake b/boards/seeed/xiao_esp32c6/board.cmake new file mode 100644 index 00000000000..2f04d1fe886 --- /dev/null +++ b/boards/seeed/xiao_esp32c6/board.cmake @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +if(NOT "${OPENOCD}" MATCHES "^${ESPRESSIF_TOOLCHAIN_PATH}/.*") + set(OPENOCD OPENOCD-NOTFOUND) +endif() +find_program(OPENOCD openocd PATHS ${ESPRESSIF_TOOLCHAIN_PATH}/openocd-esp32/bin NO_DEFAULT_PATH) + +include(${ZEPHYR_BASE}/boards/common/esp32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/seeed/xiao_esp32c6/board.yml b/boards/seeed/xiao_esp32c6/board.yml new file mode 100644 index 00000000000..f7d65e65a43 --- /dev/null +++ b/boards/seeed/xiao_esp32c6/board.yml @@ -0,0 +1,6 @@ +board: + name: xiao_esp32c6 + full_name: XIAO ESP32C6 + vendor: seeed + socs: + - name: esp32c6 diff --git a/boards/seeed/xiao_esp32c6/doc/img/xiao_esp32c6.webp b/boards/seeed/xiao_esp32c6/doc/img/xiao_esp32c6.webp new file mode 100644 index 00000000000..739123ba9f5 Binary files /dev/null and b/boards/seeed/xiao_esp32c6/doc/img/xiao_esp32c6.webp differ diff --git a/boards/seeed/xiao_esp32c6/doc/img/xiao_esp32c6_pinout.webp b/boards/seeed/xiao_esp32c6/doc/img/xiao_esp32c6_pinout.webp new file mode 100644 index 00000000000..3cc7232f27c Binary files /dev/null and b/boards/seeed/xiao_esp32c6/doc/img/xiao_esp32c6_pinout.webp differ diff --git a/boards/seeed/xiao_esp32c6/doc/index.rst b/boards/seeed/xiao_esp32c6/doc/index.rst new file mode 100644 index 00000000000..5e6865c5b02 --- /dev/null +++ b/boards/seeed/xiao_esp32c6/doc/index.rst @@ -0,0 +1,235 @@ +.. zephyr:board:: xiao_esp32c6 + +Overview +******** + +Seeed Studio XIAO ESP32C6 is powered by the highly-integrated ESP32-C6 SoC. +It consists of a high-performance (HP) 32-bit RISC-V processor, which can be clocked up to 160 MHz, +and a low-power (LP) 32-bit RISC-V processor, which can be clocked up to 20 MHz. +It has a 320KB ROM, a 512KB SRAM, and works with external flash. +This board integrates complete Wi-Fi, Bluetooth LE, Zigbee, and Thread functions. +For more information, check `Seeed Studio XIAO ESP32C6`_ . + +Hardware +******** + +This board is based on the ESP32-C6 with 4MB of flash, integrating 2.4 GHz Wi-Fi 6, +Bluetooth 5.3 (LE) and the 802.15.4 protocol. It has an USB-C port for programming +and debugging, integrated battery charging and an U.FL external antenna connector. +It is based on a standard XIAO 14 pin pinout. + +Supported Features +================== + +The Zephyr ``xiao_esp32c6`` board target supports the following hardware features: + ++------------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++============+============+=====================================+ +| UART | on-chip | serial port | ++------------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++------------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++------------+------------+-------------------------------------+ +| USB-JTAG | on-chip | hardware interface | ++------------+------------+-------------------------------------+ +| SPI Master | on-chip | spi | ++------------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++------------+------------+-------------------------------------+ +| Watchdog | on-chip | watchdog | ++------------+------------+-------------------------------------+ +| LEDC | on-chip | pwm | ++------------+------------+-------------------------------------+ +| SPI DMA | on-chip | spi | ++------------+------------+-------------------------------------+ +| GDMA | on-chip | dma | ++------------+------------+-------------------------------------+ +| TRNG | on-chip | entropy | ++------------+------------+-------------------------------------+ +| USB-CDC | on-chip | serial | ++------------+------------+-------------------------------------+ +| Wi-Fi | on-chip | | ++------------+------------+-------------------------------------+ + +The board uses a standard XIAO pinout, the default pin mapping is the following: + +.. figure:: img/xiao_esp32c6_pinout.webp + :align: center + :alt: XIAO ESP32C6 Pinout + + XIAO ESP32C6 Pinout + +System requirements +******************* + +Prerequisites +============= + +Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command +below to retrieve those files. + +.. code-block:: console + + west blobs fetch hal_espressif + +.. note:: + + It is recommended running the command above after :file:`west update`. + +Building & Flashing +******************* + +Simple boot +=========== + +The board could be loaded using the single binary image, without 2nd stage bootloader. +It is the default option when building the application without additional configuration. + +.. note:: + + Simple boot does not provide any security features nor OTA updates. + +MCUboot bootloader +================== + +User may choose to use MCUboot bootloader instead. In that case the bootloader +must be built (and flashed) at least once. + +There are two options to be used when building an application: + +1. Sysbuild +2. Manual build + +.. note:: + + User can select the MCUboot bootloader by adding the following line + to the board default configuration file. + + .. code:: cfg + + CONFIG_BOOTLOADER_MCUBOOT=y + +Sysbuild +======== + +The sysbuild makes possible to build and flash all necessary images needed to +bootstrap the board with the EPS32 SoC. + +To build the sample application using sysbuild use the command: + +.. zephyr-app-commands:: + :tool: west + :zephyr-app: samples/hello_world + :board: xiao_esp32c6 + :goals: build + :west-args: --sysbuild + :compact: + +By default, the ESP32 sysbuild creates bootloader (MCUboot) and application +images. But it can be configured to create other kind of images. + +Build directory structure created by sysbuild is different from traditional +Zephyr build. Output is structured by the domain subdirectories: + +.. code-block:: + + build/ + ├── hello_world + │   └── zephyr + │   ├── zephyr.elf + │   └── zephyr.bin + ├── mcuboot + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + └── domains.yaml + +.. note:: + + With ``--sysbuild`` option the bootloader will be re-build and re-flash + every time the pristine build is used. + +For more information about the system build please read the :ref:`sysbuild` documentation. + +Manual build +============ + +During the development cycle, it is intended to build & flash as quickly possible. +For that reason, images can be built one at a time using traditional build. + +The instructions following are relevant for both manual build and sysbuild. +The only difference is the structure of the build directory. + +.. note:: + + Remember that bootloader (MCUboot) needs to be flash at least once. + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: xiao_esp32c6 + :goals: build + +The usual ``flash`` target will work with the ``xiao_esp32c6`` board +configuration. Here is an example for the :zephyr:code-sample:`hello_world` +application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: xiao_esp32c6 + :goals: flash + +Since the Zephyr console is by default on the ``usb_serial`` device, we use +the espressif monitor to view. + +.. code-block:: console + + $ west espressif monitor + +After the board has automatically reset and booted, you should see the following +message in the monitor: + +.. code-block:: console + + ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** + Hello World! xiao_esp32c6/esp32c6 + +Debugging +********* + +As with much custom hardware, the ESP32-C6 modules require patches to +OpenOCD that are not upstreamed yet. Espressif maintains their own fork of +the project. The custom OpenOCD can be obtained at `OpenOCD ESP32`_. + +The Zephyr SDK uses a bundled version of OpenOCD by default. You can overwrite that behavior by adding the +``-DOPENOCD= -DOPENOCD_DEFAULT_PATH=`` +parameter when building. + +Here is an example for building the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: xiao_esp32c6 + :goals: build flash + :gen-args: -DOPENOCD= -DOPENOCD_DEFAULT_PATH= + +You can debug an application in the usual way. Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: xiao_esp32c6 + :goals: debug + +References +********** + +.. target-notes:: + +.. _`Seeed Studio XIAO ESP32C6`: https://wiki.seeedstudio.com/xiao_esp32c6_getting_started/ +.. _`ESP32-C6 Datasheet`: https://www.espressif.com/sites/default/files/documentation/esp32-c6_datasheet_en.pdf +.. _`ESP32-C6 Technical Reference Manual`: https://espressif.com/sites/default/files/documentation/esp32-c6_technical_reference_manual_en.pdf +.. _`OpenOCD ESP32`: https://github.com/espressif/openocd-esp32/releases diff --git a/boards/seeed/xiao_esp32c6/seeed_xiao_connector.dtsi b/boards/seeed/xiao_esp32c6/seeed_xiao_connector.dtsi new file mode 100644 index 00000000000..cf4b71f8734 --- /dev/null +++ b/boards/seeed/xiao_esp32c6/seeed_xiao_connector.dtsi @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2024 Mario Paja + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + xiao_d: connector { + compatible = "seeed,xiao-gpio"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpio0 0 0>, /* D0 */ + <1 0 &gpio0 1 0>, /* D1 */ + <2 0 &gpio0 2 0>, /* D2 */ + <3 0 &gpio0 21 0>, /* D3 */ + <4 0 &gpio0 22 0>, /* D4 */ + <5 0 &gpio0 23 0>, /* D5 */ + <6 0 &gpio0 16 0>, /* D6 */ + <7 0 &gpio0 17 0>, /* D7 */ + <8 0 &gpio0 19 0>, /* D8 */ + <9 0 &gpio0 20 0>, /* D9 */ + <10 0 &gpio0 18 0>; /* D10 */ + }; +}; + +xiao_i2c: &i2c0 {}; +xiao_spi: &spi2 {}; +xiao_serial: &uart0 {}; diff --git a/boards/seeed/xiao_esp32c6/support/openocd.cfg b/boards/seeed/xiao_esp32c6/support/openocd.cfg new file mode 100644 index 00000000000..d86a5517a4c --- /dev/null +++ b/boards/seeed/xiao_esp32c6/support/openocd.cfg @@ -0,0 +1,4 @@ +# ESP32C6 has built-in JTAG interface over USB port in pins GPIO13/GPIO12 (D-/D+). +set ESP_RTOS none + +source [find board/esp32c6-builtin.cfg] diff --git a/boards/seeed/xiao_esp32c6/xiao_esp32c6-pinctrl.dtsi b/boards/seeed/xiao_esp32c6/xiao_esp32c6-pinctrl.dtsi new file mode 100644 index 00000000000..424a4051578 --- /dev/null +++ b/boards/seeed/xiao_esp32c6/xiao_esp32c6-pinctrl.dtsi @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2024 Mario Paja + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +&pinctrl { + + uart0_default: uart0_default { + group1 { + pinmux = ; + output-high; + }; + group2 { + pinmux = ; + bias-pull-up; + }; + }; + + spim2_default: spim2_default { + group1 { + pinmux = , + ; + }; + group2 { + pinmux = ; + output-low; + }; + }; + + i2c0_default: i2c0_default { + group1 { + pinmux = , + ; + bias-pull-up; + drive-open-drain; + output-high; + }; + }; +}; diff --git a/boards/seeed/xiao_esp32c6/xiao_esp32c6.dts b/boards/seeed/xiao_esp32c6/xiao_esp32c6.dts new file mode 100644 index 00000000000..d155f5aa201 --- /dev/null +++ b/boards/seeed/xiao_esp32c6/xiao_esp32c6.dts @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2024 Mario Paja + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "xiao_esp32c6-pinctrl.dtsi" +#include +#include +#include "seeed_xiao_connector.dtsi" + +/ { + model = "Seeed XIAO ESP32C6"; + compatible = "seeed,xiao-esp32c6"; + + chosen { + zephyr,sram = &sramhp; + zephyr,console = &usb_serial; + zephyr,shell-uart = &usb_serial; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + }; + + leds: leds { + compatible = "gpio-leds"; + yellow_led: led_0 { + gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; + label = "User LED1"; + }; + }; + + aliases { + led0 = &yellow_led; + watchdog0 = &wdt0; + }; + +}; + +&trng0 { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&wdt0 { + status = "okay"; +}; + +&usb_serial { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = ; + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; +}; + +&spi2 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim2_default>; + pinctrl-names = "default"; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; +}; diff --git a/boards/seeed/xiao_esp32c6/xiao_esp32c6.yaml b/boards/seeed/xiao_esp32c6/xiao_esp32c6.yaml new file mode 100644 index 00000000000..50a8f099a3e --- /dev/null +++ b/boards/seeed/xiao_esp32c6/xiao_esp32c6.yaml @@ -0,0 +1,18 @@ +identifier: xiao_esp32c6 +name: XIAO ESP32C6 +type: mcu +arch: riscv +toolchain: + - zephyr +supported: + - gpio + - watchdog + - uart + - dma + - spi + - entropy + - i2c +testing: + ignore_tags: + - tracing +vendor: seeed diff --git a/boards/seeed/xiao_esp32c6/xiao_esp32c6_defconfig b/boards/seeed/xiao_esp32c6/xiao_esp32c6_defconfig new file mode 100644 index 00000000000..6539bd42e59 --- /dev/null +++ b/boards/seeed/xiao_esp32c6/xiao_esp32c6_defconfig @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_GPIO=y diff --git a/boards/seeed/xiao_esp32s3/Kconfig b/boards/seeed/xiao_esp32s3/Kconfig new file mode 100644 index 00000000000..361a4f5fc84 --- /dev/null +++ b/boards/seeed/xiao_esp32s3/Kconfig @@ -0,0 +1,7 @@ +# Copyright (c) 2023 Seeed Studio inc. +# SPDX-License-Identifier: Apache-2.0 + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 4096 if BOARD_XIAO_ESP32S3_ESP32S3_PROCPU || BOARD_XIAO_ESP32S3_ESP32S3_PROCPU_SENSE + default 256 if BOARD_XIAO_ESP32S3_ESP32S3_APPCPU diff --git a/boards/seeed/xiao_esp32s3/Kconfig.defconfig b/boards/seeed/xiao_esp32s3/Kconfig.defconfig deleted file mode 100644 index b9222985d8d..00000000000 --- a/boards/seeed/xiao_esp32s3/Kconfig.defconfig +++ /dev/null @@ -1,20 +0,0 @@ -# Copyright (c) 2023 Seeed Studio inc. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_XIAO_ESP32S3_ESP32S3_PROCPU - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 65535 if WIFI && BT - default 51200 if WIFI - default 40960 if BT - default 4096 - -endif # BOARD_XIAO_ESP32S3_ESP32S3_PROCPU - -if BOARD_XIAO_ESP32S3_ESP32S3_APPCPU - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - default 256 - -endif # BOARD_XIAO_ESP32S3_ESP32S3_APPCPU diff --git a/boards/seeed/xiao_esp32s3/Kconfig.xiao_esp32s3 b/boards/seeed/xiao_esp32s3/Kconfig.xiao_esp32s3 index cbe07014750..212d510c344 100644 --- a/boards/seeed/xiao_esp32s3/Kconfig.xiao_esp32s3 +++ b/boards/seeed/xiao_esp32s3/Kconfig.xiao_esp32s3 @@ -5,5 +5,5 @@ config BOARD_XIAO_ESP32S3 select SOC_ESP32S3_WROOM_N8R8 - select SOC_ESP32S3_PROCPU if BOARD_XIAO_ESP32S3_ESP32S3_PROCPU + select SOC_ESP32S3_PROCPU if BOARD_XIAO_ESP32S3_ESP32S3_PROCPU || BOARD_XIAO_ESP32S3_ESP32S3_PROCPU_SENSE select SOC_ESP32S3_APPCPU if BOARD_XIAO_ESP32S3_ESP32S3_APPCPU diff --git a/boards/seeed/xiao_esp32s3/board.yml b/boards/seeed/xiao_esp32s3/board.yml index c3eb3a0204d..1d3c200f657 100644 --- a/boards/seeed/xiao_esp32s3/board.yml +++ b/boards/seeed/xiao_esp32s3/board.yml @@ -4,3 +4,6 @@ board: vendor: seeed socs: - name: esp32s3 + variants: + - name: 'sense' + cpucluster: 'procpu' diff --git a/boards/seeed/xiao_esp32s3/doc/img/xiao-esp32s3-sense.png b/boards/seeed/xiao_esp32s3/doc/img/xiao-esp32s3-sense.png new file mode 100644 index 00000000000..90e0824a13e Binary files /dev/null and b/boards/seeed/xiao_esp32s3/doc/img/xiao-esp32s3-sense.png differ diff --git a/boards/seeed/xiao_esp32s3/doc/index.rst b/boards/seeed/xiao_esp32s3/doc/index.rst index 4c029bd5d64..afc3a7e231c 100644 --- a/boards/seeed/xiao_esp32s3/doc/index.rst +++ b/boards/seeed/xiao_esp32s3/doc/index.rst @@ -1,12 +1,9 @@ -.. _xiao_esp32s3: - -XIAO ESP32S3 -############ +.. zephyr:board:: xiao_esp32s3 Overview ******** -Seeed Studio XIAO ESP32S3 is an IoT mini development board based on the +Seeed Studio XIAO ESP32S3 and XIAO ESP32S3 Sense are IoT mini development boards based on the Espressif ESP32-S3 WiFi/Bluetooth dual-mode chip. For more details see the `Seeed Studio XIAO ESP32S3`_ wiki page. @@ -17,6 +14,12 @@ For more details see the `Seeed Studio XIAO ESP32S3`_ wiki page. XIAO ESP32S3 +.. figure:: img/xiao-esp32s3-sense.png + :align: center + :alt: XIAO ESP32S3 Sense + + XIAO ESP32S3 Sense + Hardware ******** @@ -30,6 +33,8 @@ and Bluetooth® Low Energy (Bluetooth LE). It consists of high-performance dual- (Xtensa® 32-bit LX7), a low power coprocessor, a Wi-Fi baseband, a Bluetooth LE baseband, RF module, and numerous peripherals. +Additionally, Sense variant integrates a OV2640 camera sensor, microphone and sdcard slot. + Supported Features ================== @@ -66,6 +71,8 @@ Current Zephyr's XIAO ESP32S3 board supports the following features: +------------+------------+-------------------------------------+ | GDMA | on-chip | dma | +------------+------------+-------------------------------------+ +| LCD_CAM | on-chip | lcd_cam | ++------------+------------+-------------------------------------+ Connections and IOs =================== @@ -76,7 +83,7 @@ The board uses a standard XIAO pinout, the default pin mapping is the following: :align: center :alt: XIAO ESP32S3 Pinout - XIAO ESP32S3 Pinout + XIAO ESP32S3 and XIAO ESP32S3 Sense Pinout Prerequisites ------------- @@ -183,19 +190,41 @@ The only difference is the structure of the build directory. Build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: xiao_esp32s3/esp32s3/procpu - :goals: build +.. tabs:: + + .. group-tab:: XIAO ESP32S3 + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: xiao_esp32s3/esp32s3/procpu + :goals: build + + .. group-tab:: XIAO ESP32S3 Sense + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: xiao_esp32s3/esp32s3/procpu/sense + :goals: build The usual ``flash`` target will work with the ``xiao_esp32s3`` board configuration. Here is an example for the :zephyr:code-sample:`hello_world` application. -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: xiao_esp32s3/esp32s3/procpu - :goals: flash +.. tabs:: + + .. group-tab:: XIAO ESP32S3 + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: xiao_esp32s3/esp32s3/procpu + :goals: flash + + .. group-tab:: XIAO ESP32S3 Sense + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: xiao_esp32s3/esp32s3/procpu/sense + :goals: flash Open the serial monitor using the following command: @@ -222,21 +251,45 @@ Further documentation can be obtained from the SoC vendor in `JTAG debugging for Here is an example for building the :zephyr:code-sample:`hello_world` application. -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: xiao_esp32s3/esp32/procpu - :goals: build flash +.. tabs:: + + .. group-tab:: XIAO ESP32S3 + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: xiao_esp32s3/esp32s3/procpu + :goals: debug + + .. group-tab:: XIAO ESP32S3 Sense + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: xiao_esp32s3/esp32s3/procpu/sense + :goals: debug You can debug an application in the usual way. Here is an example for the :zephyr:code-sample:`hello_world` application. -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: xiao_esp32s3/esp32/procpu - :goals: debug +.. tabs:: + + .. group-tab:: XIAO ESP32S3 + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: xiao_esp32s3/esp32s3/procpu + :goals: debug + + .. group-tab:: XIAO ESP32S3 Sense + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: xiao_esp32s3/esp32s3/procpu/sense + :goals: debug References ********** +.. target-notes:: + .. _`Seeed Studio XIAO ESP32S3`: https://wiki.seeedstudio.com/xiao_esp32s3_getting_started/ .. _`JTAG debugging for ESP32-S3`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32s3/api-guides/jtag-debugging/ .. _`OpenOCD ESP32`: https://github.com/espressif/openocd-esp32/releases diff --git a/boards/seeed/xiao_esp32s3/xiao_esp32s3-pinctrl.dtsi b/boards/seeed/xiao_esp32s3/xiao_esp32s3-pinctrl.dtsi index 27097b6bb26..3159a39611b 100644 --- a/boards/seeed/xiao_esp32s3/xiao_esp32s3-pinctrl.dtsi +++ b/boards/seeed/xiao_esp32s3/xiao_esp32s3-pinctrl.dtsi @@ -41,6 +41,38 @@ }; }; + i2c1_default: i2c1_default { + group1 { + pinmux = , + ; + bias-pull-up; + drive-open-drain; + output-high; + }; + }; + + lcd_cam_default: lcd_cam_default { + group1 { + pinmux = ; + output-enable; + }; + group2 { + pinmux = , + , + , + , + , + , + , + , + , + , + ; + input-enable; + bias-disable; + }; + }; + twai_default: twai_default { group1 { pinmux = , diff --git a/boards/seeed/xiao_esp32s3/xiao_esp32s3_appcpu.dts b/boards/seeed/xiao_esp32s3/xiao_esp32s3_appcpu.dts index f2cf95742ac..42962e9f0df 100644 --- a/boards/seeed/xiao_esp32s3/xiao_esp32s3_appcpu.dts +++ b/boards/seeed/xiao_esp32s3/xiao_esp32s3_appcpu.dts @@ -5,15 +5,19 @@ */ /dts-v1/; -#include +#include +#include + / { model = "Seeed Xiao ESP32S3 APPCPU"; compatible = "espressif,esp32s3"; chosen { - zephyr,sram = &sram0; + zephyr,sram = &sram1; zephyr,ipc_shm = &shm0; zephyr,ipc = &ipm0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_appcpu_partition; }; }; @@ -24,42 +28,3 @@ &ipm0 { status = "okay"; }; - -&flash0 { - status = "okay"; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Reserve 64kB for the bootloader */ - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x00010000>; - read-only; - }; - - /* Reserve 1024kB for the application in slot 0 */ - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 0x00100000>; - }; - - /* Reserve 1024kB for the application in slot 1 */ - slot1_partition: partition@110000 { - label = "image-1"; - reg = <0x00110000 0x00100000>; - }; - - /* Reserve 256kB for the scratch partition */ - scratch_partition: partition@210000 { - label = "image-scratch"; - reg = <0x00210000 0x00040000>; - }; - - storage_partition: partition@250000 { - label = "storage"; - reg = <0x00250000 0x00006000>; - }; - }; -}; diff --git a/boards/seeed/xiao_esp32s3/xiao_esp32s3_procpu.dts b/boards/seeed/xiao_esp32s3/xiao_esp32s3_procpu.dts index 2c1349b735c..ca5d919e4fd 100644 --- a/boards/seeed/xiao_esp32s3/xiao_esp32s3_procpu.dts +++ b/boards/seeed/xiao_esp32s3/xiao_esp32s3_procpu.dts @@ -6,129 +6,12 @@ /dts-v1/; -#include +#include "xiao_esp32s3_procpu_common.dtsi" #include "xiao_esp32s3-pinctrl.dtsi" #include "seeed_xiao_connector.dtsi" +#include / { model = "Seeed Xiao ESP32S3 PROCPU"; compatible = "seeed,xiao-esp32s3"; - - chosen { - zephyr,sram = &sram0; - zephyr,console = &usb_serial; - zephyr,shell-uart = &usb_serial; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; - zephyr,bt-hci = &esp32_bt_hci; - }; - - aliases { - i2c-0 = &i2c0; - watchdog0 = &wdt0; - led0 = &led0; - }; - - leds { - compatible = "gpio-leds"; - led0: led_0 { - gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; - label = "BUILTIN LED"; - }; - }; - -}; - -&usb_serial { - status = "okay"; -}; - -&uart0 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart0_default>; - pinctrl-names = "default"; -}; - -&i2c0 { - status = "okay"; - clock-frequency = ; - pinctrl-0 = <&i2c0_default>; - pinctrl-names = "default"; -}; - -&trng0 { - status = "okay"; -}; - -&spi2 { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - pinctrl-0 = <&spim2_default>; - pinctrl-names = "default"; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&wdt0 { - status = "okay"; -}; - -&twai { - pinctrl-0 = <&twai_default>; - pinctrl-names = "default"; -}; - -&timer0 { - status = "okay"; -}; - -&timer1 { - status = "okay"; -}; - -&flash0 { - status = "okay"; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x0000F000>; - read-only; - }; - - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 0x00100000>; - }; - - slot1_partition: partition@110000 { - label = "image-1"; - reg = <0x00110000 0x00100000>; - }; - - scratch_partition: partition@210000 { - label = "image-scratch"; - reg = <0x00210000 0x00040000>; - }; - - storage_partition: partition@250000 { - label = "storage"; - reg = <0x00250000 0x00006000>; - }; - }; -}; - -&esp32_bt_hci { - status = "okay"; }; diff --git a/boards/seeed/xiao_esp32s3/xiao_esp32s3_procpu.yaml b/boards/seeed/xiao_esp32s3/xiao_esp32s3_procpu.yaml index d438611cb33..dea06b25bb5 100644 --- a/boards/seeed/xiao_esp32s3/xiao_esp32s3_procpu.yaml +++ b/boards/seeed/xiao_esp32s3/xiao_esp32s3_procpu.yaml @@ -15,8 +15,4 @@ supported: - entropy - pwm - dma -testing: - ignore_tags: - - net - - bluetooth vendor: seeed diff --git a/boards/seeed/xiao_esp32s3/xiao_esp32s3_procpu_common.dtsi b/boards/seeed/xiao_esp32s3/xiao_esp32s3_procpu_common.dtsi new file mode 100644 index 00000000000..79860b26447 --- /dev/null +++ b/boards/seeed/xiao_esp32s3/xiao_esp32s3_procpu_common.dtsi @@ -0,0 +1,96 @@ +/* + * Copyright (c) 2023 Seeed Studio inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "xiao_esp32s3-pinctrl.dtsi" +#include "seeed_xiao_connector.dtsi" + +/ { + chosen { + zephyr,sram = &sram1; + zephyr,console = &usb_serial; + zephyr,shell-uart = &usb_serial; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + zephyr,bt-hci = &esp32_bt_hci; + }; + + aliases { + i2c-0 = &i2c0; + watchdog0 = &wdt0; + led0 = &led0; + }; + + leds { + compatible = "gpio-leds"; + led0: led_0 { + gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; + label = "BUILTIN LED"; + }; + }; + +}; + +&usb_serial { + status = "okay"; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = ; + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; +}; + +&trng0 { + status = "okay"; +}; + +&spi2 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim2_default>; + pinctrl-names = "default"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&wdt0 { + status = "okay"; +}; + +&twai { + pinctrl-0 = <&twai_default>; + pinctrl-names = "default"; +}; + +&timer0 { + status = "okay"; +}; + +&timer1 { + status = "okay"; +}; + +&esp32_bt_hci { + status = "okay"; +}; diff --git a/boards/seeed/xiao_esp32s3/xiao_esp32s3_procpu_sense.dts b/boards/seeed/xiao_esp32s3/xiao_esp32s3_procpu_sense.dts new file mode 100644 index 00000000000..f8f7ed4a316 --- /dev/null +++ b/boards/seeed/xiao_esp32s3/xiao_esp32s3_procpu_sense.dts @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2023 Seeed Studio inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include "xiao_esp32s3_procpu_common.dtsi" +#include + +/ { + model = "Seeed Xiao ESP32S3 PROCPU Sense"; + compatible = "seeed,xiao-esp32s3"; + + chosen { + zephyr,camera = &lcd_cam; + }; +}; + +&i2c1 { + status = "okay"; + clock-frequency = ; + pinctrl-0 = <&i2c1_default>; + pinctrl-names = "default"; + + ov2640: ov2640@30 { + compatible = "ovti,ov2640"; + reg = <0x30>; + status = "okay"; + clock-rate-control = <0x80>; + port { + ov2640_ep_out: endpoint { + remote-endpoint-label = "dvp_ep_in"; + }; + }; + }; +}; + +&dma { + status = "okay"; +}; + +&lcd_cam { + status = "okay"; + cam-clk = <10000000>; + pinctrl-0 = <&lcd_cam_default>; + pinctrl-names = "default"; + source = <&ov2640>; + dmas = <&dma 2>; + dma-names = "rx"; + port { + dvp_ep_in: endpoint { + remote-endpoint-label = "ov2640_ep_out"; + }; + }; +}; + +&spi2 { + status = "okay"; + cs-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; + + sdcard: sdcard@0 { + compatible = "zephyr,sdhc-spi-slot"; + reg = <0>; + status = "okay"; + mmc { + compatible = "zephyr,sdmmc-disk"; + disk-name = "SD"; + status = "okay"; + }; + spi-max-frequency = <20000000>; + }; +}; diff --git a/boards/seeed/xiao_esp32s3/xiao_esp32s3_procpu_sense.yaml b/boards/seeed/xiao_esp32s3/xiao_esp32s3_procpu_sense.yaml new file mode 100644 index 00000000000..f617abbb697 --- /dev/null +++ b/boards/seeed/xiao_esp32s3/xiao_esp32s3_procpu_sense.yaml @@ -0,0 +1,18 @@ +identifier: xiao_esp32s3/esp32s3/procpu/sense +name: XIAO ESP32S3 Sense PROCPU +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - gpio + - uart + - i2c + - spi + - can + - counter + - watchdog + - entropy + - pwm + - dma +vendor: seeed diff --git a/boards/seeed/xiao_esp32s3/xiao_esp32s3_procpu_sense_defconfig b/boards/seeed/xiao_esp32s3/xiao_esp32s3_procpu_sense_defconfig new file mode 100644 index 00000000000..6539bd42e59 --- /dev/null +++ b/boards/seeed/xiao_esp32s3/xiao_esp32s3_procpu_sense_defconfig @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_GPIO=y diff --git a/boards/seeed/xiao_rp2040/Kconfig b/boards/seeed/xiao_rp2040/Kconfig new file mode 100644 index 00000000000..8afc66f408f --- /dev/null +++ b/boards/seeed/xiao_rp2040/Kconfig @@ -0,0 +1,5 @@ +# Copyright (c) 2023 Seeed Studio inc. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_XIAO_RP2040 + select RP2_FLASH_W25Q080 diff --git a/boards/seeed/xiao_rp2040/Kconfig.defconfig b/boards/seeed/xiao_rp2040/Kconfig.defconfig index e2af832cdca..bc729ed2b36 100644 --- a/boards/seeed/xiao_rp2040/Kconfig.defconfig +++ b/boards/seeed/xiao_rp2040/Kconfig.defconfig @@ -3,9 +3,6 @@ if BOARD_XIAO_RP2040 -config RP2_FLASH_W25Q080 - default y - if I2C_DW config I2C_DW_CLOCK_SPEED diff --git a/boards/seeed/xiao_rp2040/doc/index.rst b/boards/seeed/xiao_rp2040/doc/index.rst index 7206e9be07f..0cf39c014c7 100644 --- a/boards/seeed/xiao_rp2040/doc/index.rst +++ b/boards/seeed/xiao_rp2040/doc/index.rst @@ -1,7 +1,4 @@ -.. _xiao_rp2040: - -XIAO RP2040 -########### +.. zephyr:board:: xiao_rp2040 Overview ******** @@ -13,12 +10,6 @@ to be flashed without any adapter, in a drag-and-drop manner. For more details see the `Seeed Studio XIAO RP2040`_ wiki page. -.. figure:: img/xiao_rp2040.webp - :align: center - :alt: XIAO RP2040 - - XIAO RP2040 - Hardware ******** diff --git a/boards/seeed/xiao_rp2040/xiao_rp2040-pinctrl.dtsi b/boards/seeed/xiao_rp2040/xiao_rp2040-pinctrl.dtsi index 0e235884bf2..eb72fe503c0 100644 --- a/boards/seeed/xiao_rp2040/xiao_rp2040-pinctrl.dtsi +++ b/boards/seeed/xiao_rp2040/xiao_rp2040-pinctrl.dtsi @@ -57,9 +57,6 @@ }; }; - clocks_default: clocks_default { - }; - ws2812_pio0_default: ws2812_pio0_default { ws2812 { pinmux = ; diff --git a/boards/seeed/xiao_rp2040/xiao_rp2040.dts b/boards/seeed/xiao_rp2040/xiao_rp2040.dts index 0a52f47d672..98a700f242f 100644 --- a/boards/seeed/xiao_rp2040/xiao_rp2040.dts +++ b/boards/seeed/xiao_rp2040/xiao_rp2040.dts @@ -7,7 +7,7 @@ /dts-v1/; -#include +#include #include "xiao_rp2040-pinctrl.dtsi" #include "seeed_xiao_connector.dtsi" #include @@ -86,11 +86,6 @@ }; }; -&clocks { - pinctrl-0 = <&clocks_default>; - pinctrl-names = "default"; -}; - &timer { status = "okay"; }; @@ -172,3 +167,7 @@ zephyr_udc0: &usbd { regulator-always-on; regulator-allowed-modes = ; }; + +&xosc { + startup-delay-multiplier = <64>; +}; diff --git a/boards/segger/ip_k66f/doc/index.rst b/boards/segger/ip_k66f/doc/index.rst index 1d081835cc8..902802eb6d3 100644 --- a/boards/segger/ip_k66f/doc/index.rst +++ b/boards/segger/ip_k66f/doc/index.rst @@ -1,7 +1,4 @@ -.. _ip_k66f: - -SEGGER IP Switch Board -###################### +.. zephyr:board:: ip_k66f Overview ******** @@ -13,10 +10,6 @@ Ethernet switch with Gigabit RGMII/MII/RMII interface. - KSZ8794CNX enables evaluation for switch functions - On-board debug probe J-Link-OB for programming -.. image:: ip_k66f.jpg - :align: center - :alt: IP-K66F - Hardware ******** diff --git a/boards/segger/ip_k66f/ip_k66f_defconfig b/boards/segger/ip_k66f/ip_k66f_defconfig index 3a283228faf..873d457d15b 100644 --- a/boards/segger/ip_k66f/ip_k66f_defconfig +++ b/boards/segger/ip_k66f/ip_k66f_defconfig @@ -1,7 +1,6 @@ # SPDX-License-Identifier: Apache-2.0 CONFIG_GPIO=y -CONFIG_PINCTRL=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=180000000 CONFIG_OSC_LOW_POWER=y CONFIG_USE_SEGGER_RTT=y diff --git a/boards/segger/trb_stm32f407/doc/index.rst b/boards/segger/trb_stm32f407/doc/index.rst index 24c8f8df6d8..0b90123c411 100644 --- a/boards/segger/trb_stm32f407/doc/index.rst +++ b/boards/segger/trb_stm32f407/doc/index.rst @@ -1,7 +1,4 @@ -.. _segger_trb_stm32f407: - -Cortex-M Trace Reference Board V1.2 -################################### +.. zephyr:board:: segger_trb_stm32f407 Overview ******** @@ -12,12 +9,6 @@ ARM Cortex-M4 CPU, to test hardware tracing with the SEGGER Trace-Pro debuggers. It is not meant for general prototype development because it is extremely limited when it comes to IO, and only has 3 LEDs. -.. figure:: img/segger_trb_stm32f407.jpg - :align: center - :alt: SEGGER-TRB-STM32F407 - - SEGGER-TRB-STM32F407 - Hardware ******** diff --git a/boards/shields/adafruit_2_8_tft_touch_v2/boards/rd_rw612_bga.overlay b/boards/shields/adafruit_2_8_tft_touch_v2/boards/rd_rw612_bga.overlay index 8c44347e63f..2e193a00d4f 100644 --- a/boards/shields/adafruit_2_8_tft_touch_v2/boards/rd_rw612_bga.overlay +++ b/boards/shields/adafruit_2_8_tft_touch_v2/boards/rd_rw612_bga.overlay @@ -22,6 +22,8 @@ &lcdic { /* Byte swapping not supported for this display */ /delete-property/ nxp,swap-bytes; + /* Set timer0 ratio to enable longer resets */ + nxp,timer0-ratio = <15>; /* * Settings to connect this display: diff --git a/boards/shields/adafruit_2_8_tft_touch_v2/dts/adafruit_2_8_tft_touch_v2.dtsi b/boards/shields/adafruit_2_8_tft_touch_v2/dts/adafruit_2_8_tft_touch_v2.dtsi index 9a8d5069c37..b2df10395b1 100644 --- a/boards/shields/adafruit_2_8_tft_touch_v2/dts/adafruit_2_8_tft_touch_v2.dtsi +++ b/boards/shields/adafruit_2_8_tft_touch_v2/dts/adafruit_2_8_tft_touch_v2.dtsi @@ -9,6 +9,7 @@ / { chosen { zephyr,display = &adafruit_2_8_tft_touch_v2_ili9340; + zephyr,touch = &ft5336_adafruit_2_8_tft_touch_v2; }; lvgl_pointer { @@ -57,6 +58,7 @@ spi-max-frequency = <24000000>; mmc { compatible = "zephyr,sdmmc-disk"; + disk-name = "SD"; status = "okay"; }; }; diff --git a/boards/shields/adafruit_adalogger_featherwing/Kconfig.shield b/boards/shields/adafruit_adalogger_featherwing/Kconfig.shield new file mode 100644 index 00000000000..eb5446a4746 --- /dev/null +++ b/boards/shields/adafruit_adalogger_featherwing/Kconfig.shield @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Philip-Dylan Gleonec +# SPDX-License-Identifier: Apache-2.0 + +config SHIELD_ADAFRUIT_DATA_LOGGER + def_bool $(shields_list_contains,adafruit_adalogger_featherwing) diff --git a/boards/shields/adafruit_adalogger_featherwing/adafruit_adalogger_featherwing.overlay b/boards/shields/adafruit_adalogger_featherwing/adafruit_adalogger_featherwing.overlay new file mode 100644 index 00000000000..3576ff838b0 --- /dev/null +++ b/boards/shields/adafruit_adalogger_featherwing/adafruit_adalogger_featherwing.overlay @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2024 Philip-Dylan Gleonec + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + aliases { + rtc = &rtc0_adafruit_adalogger_featherwing; + sdhc0 = &sdhc0_adafruit_adalogger_featherwing; + }; +}; + +&feather_spi { + status = "okay"; + cs-gpios = <&feather_header 17 GPIO_ACTIVE_LOW>; /* D10 */ + + sdhc0_adafruit_adalogger_featherwing: sdhc@0 { + compatible = "zephyr,sdhc-spi-slot"; + reg = <0>; + spi-max-frequency = <12000000>; + status = "okay"; + + sdmmc { + compatible = "zephyr,sdmmc-disk"; + status = "okay"; + }; + }; +}; + +&feather_i2c { + status = "okay"; + + rtc0_adafruit_adalogger_featherwing: rtc@68 { + compatible = "nxp,pcf8523"; + reg = <0x68>; + alarms-count = <1>; + battery-switch-over = "standard"; + status = "okay"; + }; +}; diff --git a/boards/shields/adafruit_adalogger_featherwing/doc/adafruit_adalogger_featherwing.webp b/boards/shields/adafruit_adalogger_featherwing/doc/adafruit_adalogger_featherwing.webp new file mode 100644 index 00000000000..1e8e5960c04 Binary files /dev/null and b/boards/shields/adafruit_adalogger_featherwing/doc/adafruit_adalogger_featherwing.webp differ diff --git a/boards/shields/adafruit_adalogger_featherwing/doc/index.rst b/boards/shields/adafruit_adalogger_featherwing/doc/index.rst new file mode 100644 index 00000000000..bc11d86bf51 --- /dev/null +++ b/boards/shields/adafruit_adalogger_featherwing/doc/index.rst @@ -0,0 +1,58 @@ +.. _adafruit_adalogger_featherwing_shield: + +Adafruit Adalogger Featherwing Shield +##################################### + +Overview +******** + +The `Adafruit Adalogger Featherwing Shield`_ features an `NXP PCF8523 Real-Time +Clock/Calendar with Battery Backup`_, and an SD card interface. + +.. figure:: adafruit_adalogger_featherwing.webp + :align: center + :alt: Adafruit Adalogger Featherwing Shield + + Adafruit Adalogger Featherwing Shield (Credit: Adafruit) + +Pin Assignments +=============== + ++-----------------------+---------------------------------------------+ +| Shield Connector Pin | Function | ++=======================+=============================================+ +| D10 | SD card SPI CS | ++-----------------------+---------------------------------------------+ +| MOSI | SD card SPI MOSI | ++-----------------------+---------------------------------------------+ +| MISO | SD card SPI MISO | ++-----------------------+---------------------------------------------+ +| SCK | SD card SPI SCK | ++-----------------------+---------------------------------------------+ +| SDA | PCF8523 RTC I2C SDA | ++-----------------------+---------------------------------------------+ +| SCL | PCF8523 RTC I2C SCL | ++-----------------------+---------------------------------------------+ + +Requirements +************ + +This shield can only be used with a board which provides a configuration for Feather connectors and +defines node aliases for SPI, I2C and GPIO interfaces (see :ref:`shields` for more details). + +Programming +*********** + +Set ``--shield adafruit_adalogger_featherwing`` when you invoke ``west build``. For example: + +.. zephyr-app-commands:: + :zephyr-app: tests/drivers/rtc/rtc_api + :board: adafruit_feather_m0_basic_proto + :shield: adafruit_adalogger_featherwing + :goals: build + +.. _Adafruit Adalogger Featherwing Shield: + https://learn.adafruit.com/adafruit-adalogger-featherwing + +.. _NXP PCF8523 Real-Time Clock/Calendar with Battery Backup: + https://www.nxp.com/docs/en/data-sheet/PCF8523.pdf diff --git a/boards/shields/adafruit_aw9523/Kconfig.shield b/boards/shields/adafruit_aw9523/Kconfig.shield new file mode 100644 index 00000000000..9d853a9c67e --- /dev/null +++ b/boards/shields/adafruit_aw9523/Kconfig.shield @@ -0,0 +1,5 @@ +# Copyright (c) 2024 TOKITA Hiroshi +# SPDX-License-Identifier: Apache-2.0 + +config SHIELD_ADAFRUIT_AW9523 + def_bool $(shields_list_contains,adafruit_aw9523) diff --git a/boards/shields/adafruit_aw9523/adafruit_aw9523.overlay b/boards/shields/adafruit_aw9523/adafruit_aw9523.overlay new file mode 100644 index 00000000000..1b3ea5550e3 --- /dev/null +++ b/boards/shields/adafruit_aw9523/adafruit_aw9523.overlay @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2024 TOKITA Hiroshi + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&stemma_qt_i2c { + status = "okay"; + + adafruit_aw9523: aw9523b@58 { + status = "okay"; + reg = <0x58>; + compatible = "awinic,aw9523b"; + + adafruit_aw9523_gpio: aw9523b-gpio { + status = "okay"; + compatible = "awinic,aw9523b-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + }; +}; diff --git a/boards/shields/adafruit_aw9523/doc/adafruit_aw9523.webp b/boards/shields/adafruit_aw9523/doc/adafruit_aw9523.webp new file mode 100644 index 00000000000..7a3cf48fda9 Binary files /dev/null and b/boards/shields/adafruit_aw9523/doc/adafruit_aw9523.webp differ diff --git a/boards/shields/adafruit_aw9523/doc/index.rst b/boards/shields/adafruit_aw9523/doc/index.rst new file mode 100644 index 00000000000..5f27d89f002 --- /dev/null +++ b/boards/shields/adafruit_aw9523/doc/index.rst @@ -0,0 +1,49 @@ +.. _adafruit_aw9523: + +Adafruit AW9523 GPIO Expander and LED Driver +############################################ + +Overview +******** + +The `Adafruit AW9523 GPIO Expander and LED Driver`_ provides +16-channel GPIO/LED controller function. + +.. figure:: adafruit_aw9523.webp + :align: center + :alt: Adafruit AW9523 + + Adafruit AW9523 (Credit: Adafruit) + +Pin Assignments +=============== + ++--------------------------+------------------------------------------+ +| Shield Pin | Function | ++==========================+==========================================+ +| SDA | AW9523B I2C SDA | ++--------------------------+------------------------------------------+ +| SCL | AW9523B I2C SCL | ++--------------------------+------------------------------------------+ +| INT (Pad on board) | AW9523B Interrupt output [1]_ | ++--------------------------+------------------------------------------+ +| RST (Pad on board) | AW9523B Reset pin [2]_ | ++--------------------------+------------------------------------------+ + +.. [1] To receive interrupts, connect the INT pin to the SoC's GPIO and set the connected + GPIO in the ``int-gpios`` property in an additional overlay. The INT terminal must be + pulled up. + +.. [2] If you want to control the reset pin from the SoC, connect it to a GPIO on the SoC + and define the ``reset-gpios`` property in an additional overlay. + +Programming +*********** + +Set ``--shield adafruit_aw9523`` when you invoke ``west build``. + +.. _Adafruit AW9523 GPIO Expander and LED Driver: + https://learn.adafruit.com/adafruit-aw9523-gpio-expander-and-led-driver + +.. _Awinic AW9523B 16 MULTI-FUNCTION LED DRIVER AND GPIO CONTROLLER WITH I2C INTERFACE: + https://doc.awinic.com/doc/202403/deffbf3b-7e7b-4ff6-8e91-fd85e2d845d5.pdf diff --git a/boards/shields/adafruit_data_logger/adafruit_data_logger.overlay b/boards/shields/adafruit_data_logger/adafruit_data_logger.overlay index 00d4876736d..1d3ffb8fc75 100644 --- a/boards/shields/adafruit_data_logger/adafruit_data_logger.overlay +++ b/boards/shields/adafruit_data_logger/adafruit_data_logger.overlay @@ -43,6 +43,7 @@ sdmmc { compatible = "zephyr,sdmmc-disk"; + disk-name = "SD"; status = "okay"; }; }; diff --git a/boards/shields/arduino_uno_click/doc/index.rst b/boards/shields/arduino_uno_click/doc/index.rst index 6c3ec052bbe..02a8ac576c6 100644 --- a/boards/shields/arduino_uno_click/doc/index.rst +++ b/boards/shields/arduino_uno_click/doc/index.rst @@ -45,7 +45,7 @@ other mikroBUS shields. For example: :zephyr-app: samples/net/sockets/echo_server :host-os: unix :board: sam_v71_xult/samv71q21 - :gen-args: -DOVERLAY_CONFIG=overlay-802154.conf + :gen-args: -DEXTRA_CONF_FILE=overlay-802154.conf :shield: arduino_uno_click,atmel_rf2xx_mikrobus :goals: build diff --git a/boards/shields/atmel_rf2xx/doc/index.rst b/boards/shields/atmel_rf2xx/doc/index.rst index 14c389e4701..d33a66a09b3 100644 --- a/boards/shields/atmel_rf2xx/doc/index.rst +++ b/boards/shields/atmel_rf2xx/doc/index.rst @@ -295,7 +295,7 @@ Set ``--shield `` when you invoke ``west build``. :zephyr-app: samples/net/sockets/echo_server :host-os: unix :board: sam4s_xplained - :gen-args: -DOVERLAY_CONFIG=overlay-802154.conf + :gen-args: -DEXTRA_CONF_FILE=overlay-802154.conf :shield: atmel_rf2xx_xplained :goals: build flash :compact: @@ -304,7 +304,7 @@ Set ``--shield `` when you invoke ``west build``. :zephyr-app: samples/net/sockets/echo_server :host-os: unix :board: [sam4e_xpro | sam_v71_xult/samv71q21] - :gen-args: -DOVERLAY_CONFIG=overlay-802154.conf + :gen-args: -DEXTRA_CONF_FILE=overlay-802154.conf :shield: [atmel_rf2xx_xpro | atmel_rf2xx_legacy] :goals: build flash :compact: @@ -313,7 +313,7 @@ Set ``--shield `` when you invoke ``west build``. :zephyr-app: samples/net/sockets/echo_server :host-os: unix :board: [sam_v71_xult/samv71q21 | frdm_k64f | nucleo_f767zi] - :gen-args: -DOVERLAY_CONFIG=overlay-802154.conf + :gen-args: -DEXTRA_CONF_FILE=overlay-802154.conf :shield: atmel_rf2xx_arduino :goals: build flash :compact: @@ -322,7 +322,7 @@ Set ``--shield `` when you invoke ``west build``. :zephyr-app: samples/net/sockets/echo_server :host-os: unix :board: lpcxpresso55s69_ns - :gen-args: -DOVERLAY_CONFIG=overlay-802154.conf + :gen-args: -DEXTRA_CONF_FILE=overlay-802154.conf :shield: atmel_rf2xx_microbus :goals: build flash :compact: diff --git a/boards/shields/buydisplay_2_8_tft_touch_arduino/Kconfig.defconfig b/boards/shields/buydisplay_2_8_tft_touch_arduino/Kconfig.defconfig index 2e9c0a6ed8a..38e54dbec88 100644 --- a/boards/shields/buydisplay_2_8_tft_touch_arduino/Kconfig.defconfig +++ b/boards/shields/buydisplay_2_8_tft_touch_arduino/Kconfig.defconfig @@ -25,7 +25,7 @@ choice LV_COLOR_DEPTH default LV_COLOR_DEPTH_16 endchoice -config LV_COLOR_16_SWAP +configdefault LV_COLOR_16_SWAP default y config INPUT diff --git a/boards/shields/buydisplay_2_8_tft_touch_arduino/buydisplay_2_8_tft_touch_arduino.overlay b/boards/shields/buydisplay_2_8_tft_touch_arduino/buydisplay_2_8_tft_touch_arduino.overlay index dcc87b2c628..48261f8b920 100644 --- a/boards/shields/buydisplay_2_8_tft_touch_arduino/buydisplay_2_8_tft_touch_arduino.overlay +++ b/boards/shields/buydisplay_2_8_tft_touch_arduino/buydisplay_2_8_tft_touch_arduino.overlay @@ -9,6 +9,7 @@ / { chosen { zephyr,display = &ili9340_buydisplay_2_8_tft_touch_arduino; + zephyr,touch = &ft5336_buydisplay_2_8_tft_touch_arduino; }; lvgl_pointer { diff --git a/boards/shields/buydisplay_3_5_tft_touch_arduino/buydisplay_3_5_tft_touch_arduino.overlay b/boards/shields/buydisplay_3_5_tft_touch_arduino/buydisplay_3_5_tft_touch_arduino.overlay index 67b679f124c..a5ca0696974 100644 --- a/boards/shields/buydisplay_3_5_tft_touch_arduino/buydisplay_3_5_tft_touch_arduino.overlay +++ b/boards/shields/buydisplay_3_5_tft_touch_arduino/buydisplay_3_5_tft_touch_arduino.overlay @@ -9,6 +9,7 @@ / { chosen { zephyr,display = &ili9488_buydisplay_3_5_tft_touch_arduino; + zephyr,touch = &ft5336_buydisplay_3_5_tft_touch_arduino; }; lvgl_pointer { diff --git a/boards/shields/dvp_fpc24_mt9m114/boards/mimxrt1060_evkb.overlay b/boards/shields/dvp_fpc24_mt9m114/boards/mimxrt1060_evkb.overlay deleted file mode 100644 index a4aa7a27308..00000000000 --- a/boards/shields/dvp_fpc24_mt9m114/boards/mimxrt1060_evkb.overlay +++ /dev/null @@ -1,9 +0,0 @@ -/* - * Copyright 2024 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -&dvp_fpc24_interface { - source = <&mt9m114>; -}; diff --git a/boards/shields/dvp_fpc24_mt9m114/boards/mimxrt1064_evk.overlay b/boards/shields/dvp_fpc24_mt9m114/boards/mimxrt1064_evk.overlay deleted file mode 100644 index a4aa7a27308..00000000000 --- a/boards/shields/dvp_fpc24_mt9m114/boards/mimxrt1064_evk.overlay +++ /dev/null @@ -1,9 +0,0 @@ -/* - * Copyright 2024 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -&dvp_fpc24_interface { - source = <&mt9m114>; -}; diff --git a/boards/shields/dvp_fpc24_mt9m114/dvp_fpc24_mt9m114.overlay b/boards/shields/dvp_fpc24_mt9m114/dvp_fpc24_mt9m114.overlay index 52988535182..49bc018779a 100644 --- a/boards/shields/dvp_fpc24_mt9m114/dvp_fpc24_mt9m114.overlay +++ b/boards/shields/dvp_fpc24_mt9m114/dvp_fpc24_mt9m114.overlay @@ -17,7 +17,7 @@ port { mt9m114_ep_out: endpoint { - remote-endpoint = <&dfi_ep_in>; + remote-endpoint-label = "dfi_ep_in"; }; }; }; @@ -28,7 +28,7 @@ port { dfi_ep_in: endpoint { - remote-endpoint = <&mt9m114_ep_out>; + remote-endpoint-label = "mt9m114_ep_out"; }; }; }; diff --git a/boards/shields/eval_adxl362_ardz/Kconfig.shield b/boards/shields/eval_adxl362_ardz/Kconfig.shield new file mode 100644 index 00000000000..031c345841e --- /dev/null +++ b/boards/shields/eval_adxl362_ardz/Kconfig.shield @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +config SHIELD_EVAL_ADXL362_ARDZ + def_bool $(shields_list_contains,eval_adxl362_ardz) diff --git a/boards/shields/eval_adxl362_ardz/boards/apard32690_max32690_m4.overlay b/boards/shields/eval_adxl362_ardz/boards/apard32690_max32690_m4.overlay new file mode 100644 index 00000000000..384cb5ecb6d --- /dev/null +++ b/boards/shields/eval_adxl362_ardz/boards/apard32690_max32690_m4.overlay @@ -0,0 +1,11 @@ +/* + * Copyright (c) 2024 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + aliases { + accel0 = &adxl362_eval_adxl362_ardz; + }; +}; diff --git a/boards/shields/eval_adxl362_ardz/doc/index.rst b/boards/shields/eval_adxl362_ardz/doc/index.rst new file mode 100644 index 00000000000..e14f708f3f1 --- /dev/null +++ b/boards/shields/eval_adxl362_ardz/doc/index.rst @@ -0,0 +1,52 @@ +.. _eval_adxl362_ardz: + +EVAL-ADXL362-ARDZ +################# + +Overview +******** + +The EVAL-ADXL362-ARDZ is a 3-axis digital accelerometer Arduino shield powered +by the Analog Devices ADXL362. + +Programming +*********** + +Set ``--shield eval_adxl362_ardz`` when you invoke ``west build``. For example: + +.. zephyr-app-commands:: + :zephyr-app: samples/sensor/sensor_shell + :board: apard32690/max32690/m4 + :shield: eval_adxl362_ardz + :goals: build + +Requirements +************ + +This shield can only be used with a board which provides a configuration for +Arduino connectors and defines node aliases for SPI and GPIO interfaces (see +:ref:`shields` for more details). + +References +********** + +- `EVAL-ADXL362-ARDZ product page`_ +- `EVAL-ADXL362-ARDZ user guide`_ +- `EVAL-ADXL362-ARDZ schematic`_ +- `ADXL362 product page`_ +- `ADXL362 data sheet`_ + +.. _EVAL-ADXL362-ARDZ product page: + https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/eval-adxl362-ardz.html + +.. _EVAL-ADXL362-ARDZ user guide: + https://wiki.analog.com/resources/eval/user-guides/eval-adicup360/hardware/adxl362 + +.. _EVAL-ADXL362-ARDZ schematic: + https://www.analog.com/media/en/reference-design-documentation/design-integration-files/eval-adxl362-ardz-designsupport.zip + +.. _ADXL362 product page: + https://www.analog.com/en/products/adxl362.html + +.. _ADXL362 data sheet: + https://www.analog.com/media/en/technical-documentation/data-sheets/adxl362.pdf diff --git a/boards/shields/eval_adxl362_ardz/eval_adxl362_ardz.overlay b/boards/shields/eval_adxl362_ardz/eval_adxl362_ardz.overlay new file mode 100644 index 00000000000..d5b63252656 --- /dev/null +++ b/boards/shields/eval_adxl362_ardz/eval_adxl362_ardz.overlay @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2024 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&arduino_spi { + status = "okay"; + + adxl362_eval_adxl362_ardz: adxl362@0 { + compatible = "adi,adxl362"; + reg = <0x0>; + spi-max-frequency = ; + int1-gpios = <&arduino_header 8 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; diff --git a/boards/shields/eval_adxl372_ardz/Kconfig.shield b/boards/shields/eval_adxl372_ardz/Kconfig.shield new file mode 100644 index 00000000000..20b61c3b528 --- /dev/null +++ b/boards/shields/eval_adxl372_ardz/Kconfig.shield @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +config SHIELD_EVAL_ADXL372_ARDZ + def_bool $(shields_list_contains,eval_adxl372_ardz) diff --git a/boards/shields/eval_adxl372_ardz/boards/apard32690_max32690_m4.overlay b/boards/shields/eval_adxl372_ardz/boards/apard32690_max32690_m4.overlay new file mode 100644 index 00000000000..0abd52f0bfa --- /dev/null +++ b/boards/shields/eval_adxl372_ardz/boards/apard32690_max32690_m4.overlay @@ -0,0 +1,11 @@ +/* + * Copyright (c) 2024 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + aliases { + accel0 = &adxl372_eval_adxl372_ardz; + }; +}; diff --git a/boards/shields/eval_adxl372_ardz/doc/index.rst b/boards/shields/eval_adxl372_ardz/doc/index.rst new file mode 100644 index 00000000000..b4210d2d9ca --- /dev/null +++ b/boards/shields/eval_adxl372_ardz/doc/index.rst @@ -0,0 +1,52 @@ +.. _eval_adxl372_ardz: + +EVAL-ADXL372-ARDZ +################# + +Overview +******** + +The EVAL-ADXL372-ARDZ is a 3-axis digital accelerometer Arduino shield powered +by the Analog Devices ADXL372. + +Programming +*********** + +Set ``--shield eval_adxl372_ardz`` when you invoke ``west build``. For example: + +.. zephyr-app-commands:: + :zephyr-app: samples/sensor/sensor_shell + :board: apard32690/max32690/m4 + :shield: eval_adxl372_ardz + :goals: build + +Requirements +************ + +This shield can only be used with a board which provides a configuration for +Arduino connectors and defines node aliases for SPI and GPIO interfaces (see +:ref:`shields` for more details). + +References +********** + +- `EVAL-ADXL372-ARDZ product page`_ +- `EVAL-ADXL372-ARDZ user guide`_ +- `EVAL-ADXL372-ARDZ schematic`_ +- `ADXL372 product page`_ +- `ADXL372 data sheet`_ + +.. _EVAL-ADXL372-ARDZ product page: + https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/eval-adxl372-ardz.html + +.. _EVAL-ADXL372-ARDZ user guide: + https://wiki.analog.com/resources/eval/user-guides/eval-adicup3029/hardware/adxl372 + +.. _EVAL-ADXL372-ARDZ schematic: + https://www.analog.com/media/en/evaluation-documentation/evaluation-design-files/eval-adxl372-ardz-designsupport.zip + +.. _ADXL372 product page: + https://www.analog.com/en/products/adxl372.html + +.. _ADXL372 data sheet: + https://www.analog.com/media/en/technical-documentation/data-sheets/adxl372.pdf diff --git a/boards/shields/eval_adxl372_ardz/eval_adxl372_ardz.overlay b/boards/shields/eval_adxl372_ardz/eval_adxl372_ardz.overlay new file mode 100644 index 00000000000..349374a7c7a --- /dev/null +++ b/boards/shields/eval_adxl372_ardz/eval_adxl372_ardz.overlay @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2024 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&arduino_spi { + status = "okay"; + + adxl372_eval_adxl372_ardz: adxl372@0 { + compatible = "adi,adxl372"; + reg = <0x0>; + spi-max-frequency = ; + int1-gpios = <&arduino_header 13 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; diff --git a/boards/shields/frdm_cr20a/doc/index.rst b/boards/shields/frdm_cr20a/doc/index.rst index 1e24e6ed2c2..244d34df0bc 100644 --- a/boards/shields/frdm_cr20a/doc/index.rst +++ b/boards/shields/frdm_cr20a/doc/index.rst @@ -10,7 +10,7 @@ The Freedom development board platform supports the MCR20A 2.4GHZ wireless transceiver. The FRDM-CR20A evaluation board is a small, low-power, cost-effective reference design for the MCR20A transceiver in a shield form factor, compatible with existing Freedom development platforms, such as -:ref:`frdm_k64f`. +:zephyr:board:`frdm_k64f`. .. image:: frdm_cr20a.jpg :align: center diff --git a/boards/shields/frdm_kw41z/doc/index.rst b/boards/shields/frdm_kw41z/doc/index.rst index ad9f784bcae..6f471295e62 100644 --- a/boards/shields/frdm_kw41z/doc/index.rst +++ b/boards/shields/frdm_kw41z/doc/index.rst @@ -13,7 +13,7 @@ integrated 2.4 GHz transceiver supporting Bluetooth |reg| Smart/Bluetooth (BLE) v4.2, Generic FSK, IEEE |reg| 802.15.4 and Thread. The FRDM-KW41Z can be used as a standalone board or as an Arduino shield. This -document covers usage as a shield; see :ref:`frdm_kw41z` for usage as a +document covers usage as a shield; see :zephyr:board:`frdm_kw41z` for usage as a standalone board. Bluetooth Controller @@ -53,7 +53,7 @@ host controller interface (HCI): OpenSDA circuit. #. Attach the FRDM-KW41Z to the Arduino header on your selected main board, - such as :ref:`mimxrt1050_evk` or :ref:`frdm_k64f`. + such as :zephyr:board:`mimxrt1050_evk` or :zephyr:board:`frdm_k64f`. #. Set ``--shield frdm_kw41z`` when you invoke ``west build`` in your Zephyr bluetooth application. For example, diff --git a/boards/shields/frdm_stbc_agm01/doc/index.rst b/boards/shields/frdm_stbc_agm01/doc/index.rst index 7879c169061..e477ba85e64 100644 --- a/boards/shields/frdm_stbc_agm01/doc/index.rst +++ b/boards/shields/frdm_stbc_agm01/doc/index.rst @@ -43,8 +43,8 @@ Pin Assignment of the FRDM-STBC-AGM01 Shield For more information about the FXOS8700, FXAS21002, and FRDM-STBC-AGM01 board: -- :zephyr:code-sample:`fxos8700` - :zephyr:code-sample:`fxas21002` +- `FXOS8700 Website`_ - `FRDM-STBC-AGM01 Website`_ - `FRDM-STBC-AGM01 Quick Reference Card`_ - `FRDM-STBC-AGM01 Schematics`_ @@ -68,3 +68,6 @@ Set ``--shield frdm_stbc_agm01`` when you invoke ``west build``. For example: .. _FRDM-STBC-AGM01 Schematics: https://www.nxp.com/downloads/en/schematics/FRDM-STBC-AGM01-SCH.pdf + +.. _FXOS8700 Website: + https://www.nxp.com/products/sensors/accelerometers/digital-motion-sensor-3d-accelerometer-2g-4g-8g-plus-3d-magnetometer:FXOS8700CQ diff --git a/boards/shields/g1120b0mipi/Kconfig.defconfig b/boards/shields/g1120b0mipi/Kconfig.defconfig index 64b784035e7..5a6971aeef3 100644 --- a/boards/shields/g1120b0mipi/Kconfig.defconfig +++ b/boards/shields/g1120b0mipi/Kconfig.defconfig @@ -20,7 +20,7 @@ config MIPI_DSI_MCUX_2L_SWAP16 endif # MIPI_DSI_MCUX_2L # Swap 16 bit color setting for LVGL, to send high byte first -config LV_COLOR_16_SWAP +configdefault LV_COLOR_16_SWAP default y if !MIPI_DSI_MCUX_2L_SWAP16 config LV_Z_VDB_SIZE diff --git a/boards/shields/g1120b0mipi/g1120b0mipi.overlay b/boards/shields/g1120b0mipi/g1120b0mipi.overlay index 7fec77ee3d7..48b724ea588 100644 --- a/boards/shields/g1120b0mipi/g1120b0mipi.overlay +++ b/boards/shields/g1120b0mipi/g1120b0mipi.overlay @@ -7,6 +7,7 @@ /{ chosen { zephyr,display = &rm67162_g1120b0mipi; + zephyr,touch = &ft3267_g1120b0mipi; }; en_mipi_display_g1120b0mipi: enable-mipi-display { diff --git a/boards/shields/lcd_par_s035/Kconfig.defconfig b/boards/shields/lcd_par_s035/Kconfig.defconfig index 8e375f8b1a8..a536a16f534 100644 --- a/boards/shields/lcd_par_s035/Kconfig.defconfig +++ b/boards/shields/lcd_par_s035/Kconfig.defconfig @@ -28,4 +28,13 @@ config INPUT_GT911_INTERRUPT endif # LVGL +if INPUT + +# GT911 driver drives reset pin low, so it needs to initialize before +# the display driver but after the MIPI DBI driver +config INPUT_INIT_PRIORITY + default 82 + +endif # INPUT + endif # SHIELD_LCD_PAR_S035 diff --git a/boards/shields/lcd_par_s035/boards/rd_rw612_bga.overlay b/boards/shields/lcd_par_s035/boards/rd_rw612_bga.overlay new file mode 100644 index 00000000000..d8d217460b4 --- /dev/null +++ b/boards/shields/lcd_par_s035/boards/rd_rw612_bga.overlay @@ -0,0 +1,101 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/* + * To use this board with this display, perform the following modifications: + * - Depopulate resistors R78, R604, R598, R15, R245, R243, R11, R20, R237, + * R235, R431, R447, R420, R459, R485, and R486 + * - Populate resistors R286, R19, R246, R242, R123, R239, R124, R125, R236, + * R233, and R12 + * - Remove jumper JP30 + * - Set jumper JP40 to postion 1-2, JP38 to 1-2, and JP16 to position 2-3 + */ + +/* + * To connect the display configure SW1 on the display to + * ON-ON-OFF (8 bit 8080 mode), and connect the following pins + * | Board Pin | Display Pin | Function | + * |-----------|-------------|----------| + * | HD2.8 | D0 | D[0] | + * | HD2.16 | D1 | D[1] | + * | J5.2 | TE | TE | + * | J5.4 | D2 | D[2] | + * | J5.1 | D3 | D[3] | + * | J5.6 | RD | RDX | + * | J5.3 | D4 | D[4] | + * | HD2.7 | D5 | D[5] | + * | HD2.6 | D6 | D[6] | + * | HD2.1 | D7 | D[7] | + * | HD2.2 | WR | WR | + * | HD8.1 | CS | CS | + * | HD8.2 | D/C | DC | + * | J13.8 | GND | GND | + * | J13.7 | VDD | 3V3 | + * | J5.10 | SCL | IC2_SCL | + * | J5.9 | SDA | IC2_SDA | + * | HD2.4 | INT | INT | + * | HD2.5 | RST | RESET | + */ + +/* Expand the LCDIC pinmux to cover all 8080 mode pins */ +&pinmux_lcdic { + group0 { + pinmux = , + , + , + , + , + , + , + , + , + , + , + , + , + ; + slew-rate = "ultra"; + }; +}; + +&st7796s { + mipi-mode = "MIPI_DBI_MODE_8080_BUS_8_BIT"; + /* + * Display supports minimum write cycle time of 66ns. This + * means we can clock the LCDIC module at 30MHz, as + * the minimum write duration will be 2x the module + * clock. Note that this frequency is too fast for reading + * from the display module + */ + mipi-max-frequency = <30000000>; + /* + * Note that this display is *not* buggy- we use rgb-is-inverted + * as a workaround here to get the display to report an inverted + * color format. This is because the "nxp,swap-bytes" setting + * on the LCDIC will apply byte swapping in hardware, so the + * display should report an inverted color format to account + * for this. This results in better performance for applications + * like LVGL, which would otherwise have to swap RGB565 data in + * software + */ + rgb-is-inverted; + /* Enable TE synchronization, using the rising edge */ + te-mode = "MIPI_DBI_TE_RISING_EDGE"; +}; + +&lcdic { + /* Enable byte swapping */ + nxp,swap-bytes; + /* Set pulse width for write active and write inactive to min value */ + nxp,write-active-cycles = <1>; + nxp,write-inactive-cycles = <1>; + /* Raise the timer0 ratio to enable longer reset delay */ + nxp,timer0-ratio = <15>; + /* Lower timer1 ratio to enable shorter TE delay */ + nxp,timer1-ratio = <0>; +}; diff --git a/boards/shields/lcd_par_s035/lcd_par_s035_8080.overlay b/boards/shields/lcd_par_s035/lcd_par_s035_8080.overlay index 9306610bc1f..f47a66042f3 100644 --- a/boards/shields/lcd_par_s035/lcd_par_s035_8080.overlay +++ b/boards/shields/lcd_par_s035/lcd_par_s035_8080.overlay @@ -9,6 +9,7 @@ /{ chosen { zephyr,display = &st7796s; + zephyr,touch = >911_lcd_par_s035; }; lvgl_pointer { @@ -24,12 +25,12 @@ gt911_lcd_par_s035: gt911-lcd_par_s035@5d { compatible = "goodix,gt911"; reg = <0x5d>; - alt-addr = <0x14>; irq-gpios = <&nxp_lcd_8080_connector 9 GPIO_ACTIVE_HIGH>; + reset-gpios = <&nxp_lcd_8080_connector 11 GPIO_ACTIVE_LOW>; }; }; -&nxp_flexio_lcd { +&zephyr_mipi_dbi_parallel { status = "okay"; #address-cells = <1>; #size-cells = <0>; @@ -38,7 +39,7 @@ reg = <0>; /* Baud rate on each pin is 1MHz */ mipi-max-frequency = <10000000>; - mipi-mode = ; + mipi-mode = "MIPI_DBI_MODE_8080_BUS_16_BIT"; height = <320>; width = <480>; invert-mode = "1-dot"; diff --git a/boards/shields/mikroe_ble_tiny_click/Kconfig.defconfig b/boards/shields/mikroe_ble_tiny_click/Kconfig.defconfig index db63d94f3c5..d6711f11874 100644 --- a/boards/shields/mikroe_ble_tiny_click/Kconfig.defconfig +++ b/boards/shields/mikroe_ble_tiny_click/Kconfig.defconfig @@ -3,4 +3,4 @@ CONFIG_BT_HCI=y CONFIG_BT_HCI_ACL_FLOW_CONTROL=n -CONFIG_BT_CTLR=n +CONFIG_BT_LL_SW_SPLIT=n diff --git a/boards/shields/mikroe_ble_tiny_click/mikroe_ble_tiny_click.overlay b/boards/shields/mikroe_ble_tiny_click/mikroe_ble_tiny_click.overlay index 6f3e7b53f42..4dedd179a98 100644 --- a/boards/shields/mikroe_ble_tiny_click/mikroe_ble_tiny_click.overlay +++ b/boards/shields/mikroe_ble_tiny_click/mikroe_ble_tiny_click.overlay @@ -15,5 +15,12 @@ bt_hci_uart: bt_hci_uart { compatible = "zephyr,bt-hci-uart"; + status = "okay"; + + da1453x { + compatible = "renesas,bt-hci-da1453x"; + reset-gpios = <&mikrobus_header 1 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; }; }; diff --git a/boards/shields/mikroe_eth3_click/Kconfig.defconfig b/boards/shields/mikroe_eth3_click/Kconfig.defconfig new file mode 100644 index 00000000000..970f0fc910a --- /dev/null +++ b/boards/shields/mikroe_eth3_click/Kconfig.defconfig @@ -0,0 +1,14 @@ +# Copyright (c) 2024 Mario Paja +# SPDX-License-Identifier: Apache-2.0 + +if SHIELD_MIKROE_ETH3_CLICK + +if NETWORKING + +# LAN9250 is L2 chip slave on SPI +config NET_L2_ETHERNET + default y + +endif # NETWORKING + +endif # SHIELD_MIKROE_ETH3_CLICK diff --git a/boards/shields/mikroe_eth3_click/Kconfig.shield b/boards/shields/mikroe_eth3_click/Kconfig.shield new file mode 100644 index 00000000000..56f8d6893aa --- /dev/null +++ b/boards/shields/mikroe_eth3_click/Kconfig.shield @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Mario Paja +# SPDX-License-Identifier: Apache-2.0 + +config SHIELD_MIKROE_ETH3_CLICK + def_bool $(shields_list_contains,mikroe_eth3_click) diff --git a/boards/shields/mikroe_eth3_click/doc/eth3_click.webp b/boards/shields/mikroe_eth3_click/doc/eth3_click.webp new file mode 100644 index 00000000000..243ec81fec3 Binary files /dev/null and b/boards/shields/mikroe_eth3_click/doc/eth3_click.webp differ diff --git a/boards/shields/mikroe_eth3_click/doc/index.rst b/boards/shields/mikroe_eth3_click/doc/index.rst new file mode 100644 index 00000000000..10f9669762f --- /dev/null +++ b/boards/shields/mikroe_eth3_click/doc/index.rst @@ -0,0 +1,67 @@ +.. _mikroe_eth3_click: + +MikroElektronika ETH 3 Click +############################ + +Overview +******** + +ETH 3 Click is an accessory board in mikroBus™ form factor. It features `LAN9250`_, +a 10/100Mbps BASE-T stand alone Ethernet Controller with an on-board MAC & PHY, +16Kbyte FIFO Buffer and SPI serial interface. +More information at `ETH 3 Click Shield website`_. + +.. figure:: eth3_click.webp + :align: center + :alt: MikroElektronika ETH 3 Click + + MikroElektronika ETH 3 Click (Credit: MikroElektronika) + +Pins Assignment of the Eth Click Shield +======================================= + ++-----------------------+---------------------------------------------+ +| Shield Connector Pin | Function | ++=======================+=============================================+ +| RST# | Ethernet Controller's Reset | ++-----------------------+---------------------------------------------+ +| CS# | SPI's Chip Select | ++-----------------------+---------------------------------------------+ +| SCK | SPI's ClocK | ++-----------------------+---------------------------------------------+ +| SDO | SPI's Slave Data Output (MISO) | ++-----------------------+---------------------------------------------+ +| SDI | SPI's Slave Data Input (MISO) | ++-----------------------+---------------------------------------------+ +| INT | Ethernet Controller's Interrupt Output | ++-----------------------+---------------------------------------------+ + + +Requirements +************ + +This shield can only be used with a board which provides a configuration +for Mikro-BUS connectors and defines node aliases for SPI and GPIO interfaces +(see :ref:`shields` for more details). + +Programming +*********** + +Set ``--shield mikroe_eth3_click`` when you invoke ``west build``. For example: + +.. zephyr-app-commands:: + :zephyr-app: samples/net/dhcpv4_client + :board: mikroe_stm32_m4_clicker + :shield: mikroe_eth3_click + :goals: build + +References +********** + +.. target-notes:: + +.. _ETH 3 Click Shield website: + https://www.mikroe.com/eth-3-click + +.. _LAN9250: + https://www.microchip.com/en-us/product/lan9250 diff --git a/boards/shields/mikroe_eth3_click/mikroe_eth3_click.overlay b/boards/shields/mikroe_eth3_click/mikroe_eth3_click.overlay new file mode 100644 index 00000000000..6c1bc35cf83 --- /dev/null +++ b/boards/shields/mikroe_eth3_click/mikroe_eth3_click.overlay @@ -0,0 +1,15 @@ +/* Copyright (c) 2024 Mario Paja + * SPDX-License-Identifier: Apache-2.0 + */ + +&mikrobus_spi { + status = "okay"; + + eth3_click_mikroe_eth3_click: eth3_click@0 { + compatible = "microchip,lan9250"; + reg = <0x0>; + local-mac-address = [00 00 00 01 02 03]; + spi-max-frequency = <30000000>; + int-gpios = <&mikrobus_header 7 GPIO_ACTIVE_LOW>; /* INT */ + }; +}; diff --git a/boards/shields/mikroe_weather_click/Kconfig.shield b/boards/shields/mikroe_weather_click/Kconfig.shield index 9c73ce779a2..be548a7ce8c 100644 --- a/boards/shields/mikroe_weather_click/Kconfig.shield +++ b/boards/shields/mikroe_weather_click/Kconfig.shield @@ -1,5 +1,8 @@ # Copyright (c) 2024 Common Ground Electronics # SPDX-License-Identifier: Apache-2.0 -config SHIELD_MIKROE_WEATHER_CLICK - def_bool $(shields_list_contains,mikroe_weather_click) +config SHIELD_MIKROE_WEATHER_CLICK_I2C + def_bool $(shields_list_contains,mikroe_weather_click_i2c) + +config SHIELD_MIKROE_WEATHER_CLICK_SPI + def_bool $(shields_list_contains,mikroe_weather_click_spi) diff --git a/boards/shields/mikroe_weather_click/doc/index.rst b/boards/shields/mikroe_weather_click/doc/index.rst index 3042ff87521..80143d80117 100644 --- a/boards/shields/mikroe_weather_click/doc/index.rst +++ b/boards/shields/mikroe_weather_click/doc/index.rst @@ -21,8 +21,15 @@ Requirements This shield can only be used with a board that provides a mikroBUS |trade| socket and defines a ``mikrobus_i2c`` node label for the mikroBUS |trade| I2C +interface or a ``mikrobus_spi`` node label for the mikroBUS |trade| SPI interface (see :ref:`shields` for more details). +.. note:: + + By default the Weather Click is configured to use the I2C interface. In + order to use the SPI interface the jumper settings must be changed. See + the `Weather Click Schematic`_ for further details. + For more information about the BME280 and the Weather Click, see the following documentation: @@ -34,13 +41,14 @@ documentation: Programming *********** -Set ``--shield mikroe_weather_click`` when you invoke ``west build``. For +Set ``--shield mikroe_weather_click_i2c`` or +``--shield mikroe_weather_click_spi`` when you invoke ``west build``. For example: .. zephyr-app-commands:: :zephyr-app: samples/sensor/bme280 :board: lpcxpresso55s16 - :shield: mikroe_weather_click + :shield: [mikroe_weather_click_i2c | mikroe_weather_click_spi] :goals: build .. _Weather Click: diff --git a/boards/shields/mikroe_weather_click/mikroe_weather_click.overlay b/boards/shields/mikroe_weather_click/mikroe_weather_click_i2c.overlay similarity index 100% rename from boards/shields/mikroe_weather_click/mikroe_weather_click.overlay rename to boards/shields/mikroe_weather_click/mikroe_weather_click_i2c.overlay diff --git a/boards/shields/mikroe_weather_click/mikroe_weather_click_spi.overlay b/boards/shields/mikroe_weather_click/mikroe_weather_click_spi.overlay new file mode 100644 index 00000000000..7cf667244f4 --- /dev/null +++ b/boards/shields/mikroe_weather_click/mikroe_weather_click_spi.overlay @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2024 Ian Morris + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&mikrobus_spi { + status = "okay"; + cs-gpios = <&mikrobus_header 2 GPIO_ACTIVE_LOW>; + + bme280_mikroe_weather_click: bme280@0 { + status = "okay"; + compatible = "bosch,bme280"; + spi-max-frequency = <1000000>; + reg = <0>; + }; +}; diff --git a/boards/shields/nrf7002eb/doc/index.rst b/boards/shields/nrf7002eb/doc/index.rst index e93c778f87c..06f9f4d828d 100644 --- a/boards/shields/nrf7002eb/doc/index.rst +++ b/boards/shields/nrf7002eb/doc/index.rst @@ -46,16 +46,16 @@ The shield can be used in any application by setting ``--shield nrf7002eb`` when Shield Variants ############### -The nRF7002 EK has a variant which includes the COEX pins. These pins are not be routed to the +The nRF7002 EB has a variant which includes the COEX pins. These pins are not be routed to the edge-connector on some boards, like earlier revisions of the Thingy53 than v1.0.0. -- ``nrf7002ek``: The default variant. -- ``nrf7002ek_coex``: Variant which includes the COEX pins. +- ``nrf7002eb``: The default variant. +- ``nrf7002eb_coex``: Variant which includes the COEX pins. SR Co-existence ############### -The nRF7002 EK supports SR co-existence provided the host board supports it. The SR co-existence +The nRF7002 EB supports SR co-existence provided the host board supports it. The SR co-existence pins are connected to the host board's GPIO pins. Two Kconfig options are available to enable SR co-existence: diff --git a/boards/shields/nxp_btb44_ov5640/nxp_btb44_ov5640.overlay b/boards/shields/nxp_btb44_ov5640/nxp_btb44_ov5640.overlay index e7c179f5d23..9eca70c27cd 100644 --- a/boards/shields/nxp_btb44_ov5640/nxp_btb44_ov5640.overlay +++ b/boards/shields/nxp_btb44_ov5640/nxp_btb44_ov5640.overlay @@ -4,6 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include + /{ chosen { zephyr,camera = &nxp_csi; @@ -21,7 +23,9 @@ port { ov5640_ep_out: endpoint { - remote-endpoint = <&mipi_csi2rx_ep_in>; + remote-endpoint-label = "mipi_csi2rx_ep_in"; + bus-type = ; + data-lanes = <1 2>; }; }; }; @@ -30,14 +34,13 @@ &nxp_mipi_csi { status = "okay"; - sensor = <&ov5640>; - ports { port@1 { reg = <1>; mipi_csi2rx_ep_in: endpoint { - remote-endpoint = <&ov5640_ep_out>; + remote-endpoint-label = "ov5640_ep_out"; + data-lanes = <1 2>; }; }; }; diff --git a/boards/shields/p3t1755dp_ard_i2c/Kconfig.shield b/boards/shields/p3t1755dp_ard_i2c/Kconfig.shield new file mode 100644 index 00000000000..0cdc75a34be --- /dev/null +++ b/boards/shields/p3t1755dp_ard_i2c/Kconfig.shield @@ -0,0 +1,8 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +config SHIELD_P3T1755DP_ARD_I3C + def_bool $(shields_list_contains,p3t1755dp_ard_i3c) diff --git a/boards/shields/p3t1755dp_ard_i2c/boards/frdm_mcxn236.overlay b/boards/shields/p3t1755dp_ard_i2c/boards/frdm_mcxn236.overlay new file mode 100644 index 00000000000..22ec2f7453c --- /dev/null +++ b/boards/shields/p3t1755dp_ard_i2c/boards/frdm_mcxn236.overlay @@ -0,0 +1,14 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&i3c1 { + status = "disabled"; +}; + +&flexcomm5_lpi2c5 { + status = "okay"; + clock-frequency = ; +}; diff --git a/boards/shields/p3t1755dp_ard_i2c/boards/mimxrt1180_evk_mimxrt1189_cm33.overlay b/boards/shields/p3t1755dp_ard_i2c/boards/mimxrt1180_evk_mimxrt1189_cm33.overlay new file mode 100644 index 00000000000..5a997072e24 --- /dev/null +++ b/boards/shields/p3t1755dp_ard_i2c/boards/mimxrt1180_evk_mimxrt1189_cm33.overlay @@ -0,0 +1,14 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&i3c2 { + status = "disabled"; +}; + +&lpi2c2 { + status = "okay"; + clock-frequency = ; +}; diff --git a/boards/shields/p3t1755dp_ard_i2c/boards/mimxrt1180_evk_mimxrt1189_cm7.overlay b/boards/shields/p3t1755dp_ard_i2c/boards/mimxrt1180_evk_mimxrt1189_cm7.overlay new file mode 100644 index 00000000000..5a997072e24 --- /dev/null +++ b/boards/shields/p3t1755dp_ard_i2c/boards/mimxrt1180_evk_mimxrt1189_cm7.overlay @@ -0,0 +1,14 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&i3c2 { + status = "disabled"; +}; + +&lpi2c2 { + status = "okay"; + clock-frequency = ; +}; diff --git a/boards/shields/p3t1755dp_ard_i2c/doc/index.rst b/boards/shields/p3t1755dp_ard_i2c/doc/index.rst new file mode 100644 index 00000000000..866ecfd6dd5 --- /dev/null +++ b/boards/shields/p3t1755dp_ard_i2c/doc/index.rst @@ -0,0 +1,59 @@ +.. _p3t1755dp_ard_i2c_shield: + +P3T1755DP Arduino® Shield Evaluation Board +########################################## + +Overview +******** + +P3T1755DP is a ±0.5 °C accurate temperature-to-digital converter +with a -40 °C to 125 °C range. + +.. figure:: p3t1755dp_ard.webp + :align: center + :alt: P3T1755DP ARD + +Requirements +************ + +The temperature register always stores a 12 bit two's complement data, +giving a temperature resolution of 0.0625 °C. P3T1755DP can be configured +for different operation conditions: continuous conversion, one-shot mode +or shutdown mode. The device supports 2-wire serial I3C (up to 12.5 MHz) +and I²C (up to 3.4 MHz) as communication interface. + +For more information about P3T1755DP-ARD see these NXP documents: + +- `Getting Started with the P3T1755DP-ARD Evaluation Board`_ +- `P3T1755DP-ARD Evaluation Board User Manual`_ + +Hardware Connection +******************* +- Shield board p3t1755dp_ard in I3C mode + J10, J11, J12 3-5, the i3c addr is 0x4800000236152a0090 + JP2, Jp3 1-2 + I3C is from J13 + The VDD from arduino is 3v3 JP1 2-3 + +- Shield board p3t1755dp_ard in I2C mode + J10, J11, J12 3-5, the i2c addr is 0x48 + JP2, Jp3 2-3 + The I2C is from Arduino J5 pin9(SCL_ARD) pin10(SDA_ARD) + The VDD from arduino is 3v3 JP1 2-3 + +Programming +*********** + +Set ``--shield p3t1755dp_ard_i3c`` when you invoke ``west build``. For example: + +.. zephyr-app-commands:: + :zephyr-app: samples/sensor/thermometer + :board: mimxrt1180_evk/mimxrt1189/cm33 + :shield: p3t1755dp_ard_i3c + :goals: build + +.. _Getting Started with the P3T1755DP-ARD Evaluation Board: + https://www.nxp.com/document/guide/getting-started-with-the-p3t1755dp-ard-evaluation-board:GS-P3T1755DP-ARD + +.. _P3T1755DP-ARD Evaluation Board User Manual: + https://www.nxp.com/docs/en/user-manual/UM11834.pdf diff --git a/boards/shields/p3t1755dp_ard_i2c/doc/p3t1755dp_ard.webp b/boards/shields/p3t1755dp_ard_i2c/doc/p3t1755dp_ard.webp new file mode 100644 index 00000000000..3c8dd30c617 Binary files /dev/null and b/boards/shields/p3t1755dp_ard_i2c/doc/p3t1755dp_ard.webp differ diff --git a/boards/shields/p3t1755dp_ard_i2c/p3t1755dp_ard_i2c.overlay b/boards/shields/p3t1755dp_ard_i2c/p3t1755dp_ard_i2c.overlay new file mode 100644 index 00000000000..b4f74314dd9 --- /dev/null +++ b/boards/shields/p3t1755dp_ard_i2c/p3t1755dp_ard_i2c.overlay @@ -0,0 +1,21 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + aliases { + ambient-temp0 = &p3t1755_i2c; + }; +}; + +&p3t1755dp_ard_i2c_interface { + status = "okay"; + p3t1755_i2c: p3t1755@48 { + compatible = "nxp,p3t1755"; + reg = <0x48>; + oneshot-mode; + status = "okay"; + }; +}; diff --git a/boards/shields/p3t1755dp_ard_i3c/Kconfig.shield b/boards/shields/p3t1755dp_ard_i3c/Kconfig.shield new file mode 100644 index 00000000000..0cdc75a34be --- /dev/null +++ b/boards/shields/p3t1755dp_ard_i3c/Kconfig.shield @@ -0,0 +1,8 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +config SHIELD_P3T1755DP_ARD_I3C + def_bool $(shields_list_contains,p3t1755dp_ard_i3c) diff --git a/boards/shields/p3t1755dp_ard_i3c/boards/frdm_mcxn236.overlay b/boards/shields/p3t1755dp_ard_i3c/boards/frdm_mcxn236.overlay new file mode 100644 index 00000000000..115b33818b1 --- /dev/null +++ b/boards/shields/p3t1755dp_ard_i3c/boards/frdm_mcxn236.overlay @@ -0,0 +1,27 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* + * The p3t1755 shield board is plugged into the arduino interface on + * the FRDM-MCXN236 board, and the J13 on the shield board is connected + * to the J9 on the MCXN236 referred below. + * J13-1 -> J9-3; J13-2 -> J9-4; + * J13-3 -> J9-1; J13-4 -> J9-22; + */ + +#include + +&flexcomm5_lpi2c5 { + status = "disabled"; +}; + +&i3c1 { + status = "okay"; + + i2c-scl-hz = ; + i3c-scl-hz = ; + i3c-od-scl-hz = ; +}; diff --git a/boards/shields/p3t1755dp_ard_i3c/boards/mimxrt1180_evk_mimxrt1189_cm33.overlay b/boards/shields/p3t1755dp_ard_i3c/boards/mimxrt1180_evk_mimxrt1189_cm33.overlay new file mode 100644 index 00000000000..a0e26da50f4 --- /dev/null +++ b/boards/shields/p3t1755dp_ard_i3c/boards/mimxrt1180_evk_mimxrt1189_cm33.overlay @@ -0,0 +1,27 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* + * The p3t1755 shield board is plugged into the arduino interface on + * the MIMXRT1180-EVK board, and the J13 on the shield board is connected + * to the J50 on the RT1180 referred below. + * J13-1 -> J50-1; J13-2 -> J50-2; + * J13-3 -> J50-3; J13-4 -> J50-4; + */ + +#include + +&lpi2c2 { + status = "disabled"; +}; + +&i3c2 { + status = "okay"; + + i2c-scl-hz = ; + i3c-scl-hz = ; + i3c-od-scl-hz = ; +}; diff --git a/boards/shields/p3t1755dp_ard_i3c/boards/mimxrt1180_evk_mimxrt1189_cm7.overlay b/boards/shields/p3t1755dp_ard_i3c/boards/mimxrt1180_evk_mimxrt1189_cm7.overlay new file mode 100644 index 00000000000..a0e26da50f4 --- /dev/null +++ b/boards/shields/p3t1755dp_ard_i3c/boards/mimxrt1180_evk_mimxrt1189_cm7.overlay @@ -0,0 +1,27 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* + * The p3t1755 shield board is plugged into the arduino interface on + * the MIMXRT1180-EVK board, and the J13 on the shield board is connected + * to the J50 on the RT1180 referred below. + * J13-1 -> J50-1; J13-2 -> J50-2; + * J13-3 -> J50-3; J13-4 -> J50-4; + */ + +#include + +&lpi2c2 { + status = "disabled"; +}; + +&i3c2 { + status = "okay"; + + i2c-scl-hz = ; + i3c-scl-hz = ; + i3c-od-scl-hz = ; +}; diff --git a/boards/shields/p3t1755dp_ard_i3c/doc/index.rst b/boards/shields/p3t1755dp_ard_i3c/doc/index.rst new file mode 100644 index 00000000000..ff76ea33410 --- /dev/null +++ b/boards/shields/p3t1755dp_ard_i3c/doc/index.rst @@ -0,0 +1,59 @@ +.. _p3t1755dp_ard_i3c_shield: + +P3T1755DP Arduino® Shield Evaluation Board +########################################## + +Overview +******** + +P3T1755DP is a ±0.5 °C accurate temperature-to-digital converter +with a -40 °C to 125 °C range. + +.. figure:: p3t1755dp_ard.webp + :align: center + :alt: P3T1755DP ARD + +Requirements +************ + +The temperature register always stores a 12 bit two's complement data, +giving a temperature resolution of 0.0625 °C. P3T1755DP can be configured +for different operation conditions: continuous conversion, one-shot mode +or shutdown mode. The device supports 2-wire serial I3C (up to 12.5 MHz) +and I²C (up to 3.4 MHz) as communication interface. + +For more information about P3T1755DP-ARD see these NXP documents: + +- `Getting Started with the P3T1755DP-ARD Evaluation Board`_ +- `P3T1755DP-ARD Evaluation Board User Manual`_ + +Hardware Connection +******************* +- Shield board p3t1755dp_ard in I3C mode + J10, J11, J12 3-5, the i3c addr is 0x4800000236152a0090 + JP2, Jp3 1-2 + I3C is from J13 + The VDD from arduino is 3v3 JP1 2-3 + +- Shield board p3t1755dp_ard in I2C mode + J10, J11, J12 3-5, the i2c addr is 0x48 + JP2, Jp3 2-3 + The I2C is from Arduino J5 pin9(SCL_ARD) pin10(SDA_ARD) + The VDD from arduino is 3v3 JP1 2-3 + +Programming +*********** + +Set ``--shield p3t1755dp_ard_i3c`` when you invoke ``west build``. For example: + +.. zephyr-app-commands:: + :zephyr-app: samples/sensor/thermometer + :board: mimxrt1180_evk/mimxrt1189/cm33 + :shield: p3t1755dp_ard_i3c + :goals: build + +.. _Getting Started with the P3T1755DP-ARD Evaluation Board: + https://www.nxp.com/document/guide/getting-started-with-the-p3t1755dp-ard-evaluation-board:GS-P3T1755DP-ARD + +.. _P3T1755DP-ARD Evaluation Board User Manual: + https://www.nxp.com/docs/en/user-manual/UM11834.pdf diff --git a/boards/shields/p3t1755dp_ard_i3c/doc/p3t1755dp_ard.webp b/boards/shields/p3t1755dp_ard_i3c/doc/p3t1755dp_ard.webp new file mode 100644 index 00000000000..3c8dd30c617 Binary files /dev/null and b/boards/shields/p3t1755dp_ard_i3c/doc/p3t1755dp_ard.webp differ diff --git a/boards/shields/p3t1755dp_ard_i3c/p3t1755dp_ard_i3c.overlay b/boards/shields/p3t1755dp_ard_i3c/p3t1755dp_ard_i3c.overlay new file mode 100644 index 00000000000..572368f9523 --- /dev/null +++ b/boards/shields/p3t1755dp_ard_i3c/p3t1755dp_ard_i3c.overlay @@ -0,0 +1,20 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + aliases { + ambient-temp0 = &p3t1755_i3c; + }; +}; + +&p3t1755dp_ard_i3c_interface { + status = "okay"; + p3t1755_i3c: p3t1755@4800000236152a0090 { + compatible = "nxp,p3t1755"; + reg = <0x48 0x0236 0x152a0090>; + status = "okay"; + }; +}; diff --git a/boards/shields/pmod_acl/doc/index.rst b/boards/shields/pmod_acl/doc/index.rst index 7a635f435ad..19d2ee03867 100644 --- a/boards/shields/pmod_acl/doc/index.rst +++ b/boards/shields/pmod_acl/doc/index.rst @@ -1,4 +1,4 @@ -.. pmod_acl: +.. _pmod_acl: Digilent Pmod ACL ################# diff --git a/boards/shields/pmod_sd/Kconfig.shield b/boards/shields/pmod_sd/Kconfig.shield new file mode 100644 index 00000000000..8da50ac8224 --- /dev/null +++ b/boards/shields/pmod_sd/Kconfig.shield @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SHIELD_PMOD_SD + def_bool $(shields_list_contains,pmod_sd) diff --git a/boards/shields/pmod_sd/boards/ek_ra8d1.overlay b/boards/shields/pmod_sd/boards/ek_ra8d1.overlay new file mode 100644 index 00000000000..65f155cf28d --- /dev/null +++ b/boards/shields/pmod_sd/boards/ek_ra8d1.overlay @@ -0,0 +1,10 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +&pmod_sd_shield { + interrupt-names = "accs", "card", "dma-req"; + interrupts = <60 12>, <61 12>, <62 12>; + pinctrl-0 = <&sdhc1_default>; +}; diff --git a/boards/shields/pmod_sd/doc/index.rst b/boards/shields/pmod_sd/doc/index.rst new file mode 100644 index 00000000000..eaf051f4c08 --- /dev/null +++ b/boards/shields/pmod_sd/doc/index.rst @@ -0,0 +1,54 @@ +.. _pmod_sd: + +Digilent Pmod SD +################ + +Overview +******** + +The Digilent Pmod SD (Revision B) allows system boards to read from and write to SD cards. + +Features +******** + +- Full-sized SD card slot +- Store and access large amounts of date from your system board +- No limitation on file system or memory size of SD card used +- 1-bit and 4-bit communication +- 12-pin Pmod port with SPI interface + +Programming +*********** + +Set ``--shield pmod_sd`` when you invoke ``west build``. For example: + +.. zephyr-app-commands:: + :zephyr-app: tests/drivers/disk/disk_access + :board: ek_ra8m1 + :shield: pmod_sd + :goals: build + +Pinout +====== + +.. figure:: pmod_sd_pins.webp + :align: center + :alt: PMOD SD Pinout + + PMOD SD Pinout (Credit: Digilent) + +References +********** + +- `Pmod SD product page`_ +- `Pmod SD reference manual`_ +- `Pmod SD schematic`_ + +.. _Pmod SD product page: + https://digilent.com/shop/pmod-sd-full-sized-sd-card-slot/ + +.. _Pmod SD reference manual: + https://digilent.com/reference/pmod/pmodsd/reference-manual + +.. _Pmod SD schematic: + https://digilent.com/reference/_media/reference/pmod/pmodsd/pmodsd_sch.pdf diff --git a/boards/shields/pmod_sd/doc/pmod_sd_pins.webp b/boards/shields/pmod_sd/doc/pmod_sd_pins.webp new file mode 100644 index 00000000000..3be8baedb1e Binary files /dev/null and b/boards/shields/pmod_sd/doc/pmod_sd_pins.webp differ diff --git a/boards/shields/pmod_sd/pmod_sd.overlay b/boards/shields/pmod_sd/pmod_sd.overlay new file mode 100644 index 00000000000..6bf8d7675c0 --- /dev/null +++ b/boards/shields/pmod_sd/pmod_sd.overlay @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + aliases { + sdhc0 = &pmod_sd_shield; + }; +}; + +&pmod_sd_shield { + pinctrl-0 = <&sdhc0_default>; + pinctrl-names = "default"; + status = "okay"; + sdmmc { + compatible = "zephyr,sdmmc-disk"; + disk-name = "SD"; + status = "okay"; + }; +}; diff --git a/boards/shields/renesas_us159_da14531evz/Kconfig.shield b/boards/shields/renesas_us159_da14531evz/Kconfig.shield new file mode 100644 index 00000000000..85cea91bb85 --- /dev/null +++ b/boards/shields/renesas_us159_da14531evz/Kconfig.shield @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SHIELD_RENESAS_US159_DA14531EVZ + def_bool $(shields_list_contains,renesas_us159_da14531evz) diff --git a/boards/shields/renesas_us159_da14531evz/boards/ek_ra8m1.overlay b/boards/shields/renesas_us159_da14531evz/boards/ek_ra8m1.overlay new file mode 100644 index 00000000000..d17555e4f79 --- /dev/null +++ b/boards/shields/renesas_us159_da14531evz/boards/ek_ra8m1.overlay @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + sci0_default: sci0_default { + group1 { + /* tx */ + psels = ; + drive-strength = "medium"; + }; + group2 { + /* rx, rts, cts */ + psels = , + , + ; + }; + }; +}; + +&sci0 { + pinctrl-0 = <&sci0_default>; + pinctrl-names = "default"; + status = "okay"; + uart0: uart { + current-speed = <115200>; + hw-flow-control; + status = "okay"; + }; +}; diff --git a/boards/shields/renesas_us159_da14531evz/doc/da14531-hci-hw-flow-binary.webp b/boards/shields/renesas_us159_da14531evz/doc/da14531-hci-hw-flow-binary.webp new file mode 100644 index 00000000000..0bbf1335652 Binary files /dev/null and b/boards/shields/renesas_us159_da14531evz/doc/da14531-hci-hw-flow-binary.webp differ diff --git a/boards/shields/renesas_us159_da14531evz/doc/index.rst b/boards/shields/renesas_us159_da14531evz/doc/index.rst new file mode 100644 index 00000000000..1b302e4ac14 --- /dev/null +++ b/boards/shields/renesas_us159_da14531evz/doc/index.rst @@ -0,0 +1,79 @@ +.. _renesas_us159_da14531evz_shield: + +Renesas DA14531 Pmod Board +########################## + +Overview +******** + +The Renesas US159 DA14531EVZ carries a `DA14531MOD`_ Bluetooth LE module +in a `Digilent Pmod`_ |trade| form factor. + +.. figure:: us159-da14531evz-pmod.webp + :align: center + :alt: Renesas US159 DA14531EVZ Pmod + + Renesas US159 DA14531EVZ Pmod (Credit: Renesas Electronics) + +Requirements +************ + +This shield can only be used with a board that provides a Pmod |trade| +socket and defines the ``pmod_serial`` node label (see :ref:`shields` for +more details). + +The DA14531 Module contained on the shield must be programmed with a binary +file that supports the HCI interface over UART, with hardware flow control +enabled. + +The `Renesas SmartBond Flash Programmer`_ tool can be used to download a +suitable binary and then program it into the DA14531 via the SWD header +present on the Pmod board. Once the tool has been installed, open it and +press the "Search Online" button. The required binary file can be selected +for download as follows: + +.. figure:: da14531-hci-hw-flow-binary.webp + :align: center + :alt: DA14531 HCI Binary File Selection + + Selecting the DA14531 HCI Binary File for Download + +Press the "Program" button to program the binary file into the DA14531 Module. + +For more information about interfacing to the DA14531 and the US159 DA14531EVZ +Pmod, see the following documentation: + +- `DA14531MOD Datasheet`_ +- `US159 DA14531EVZ Pmod`_ + +Programming +*********** + +Set ``--shield renesas_us159_da14531evz`` when you invoke ``west build``. For +example: + +.. zephyr-app-commands:: + :zephyr-app: samples/bluetooth/beacon + :board: ek_ra8m1 + :shield: renesas_us159_da14531evz + :goals: build + +References +********** + +.. target-notes:: + +.. _DA14531MOD: + https://www.renesas.com/us/en/products/wireless-connectivity/bluetooth-low-energy/da14531mod-smartbond-tiny-bluetooth-low-energy-module + +.. _Digilent Pmod: + https://digilent.com/reference/pmod/start + +.. _Renesas SmartBond Flash Programmer: + https://www.renesas.com/us/en/software-tool/smartbond-flash-programmer + +.. _DA14531MOD Datasheet: + https://www.renesas.com/us/en/document/dst/da14531-module-datasheet?r=1601921 + +.. _US159 DA14531EVZ Pmod: + https://www.renesas.com/en/products/wireless-connectivity/bluetooth-low-energy/us159-da14531evz-low-power-bluetooth-pmod-board-renesas-quickconnect-iot diff --git a/boards/shields/renesas_us159_da14531evz/doc/us159-da14531evz-pmod.webp b/boards/shields/renesas_us159_da14531evz/doc/us159-da14531evz-pmod.webp new file mode 100644 index 00000000000..cb3cb2f42d6 Binary files /dev/null and b/boards/shields/renesas_us159_da14531evz/doc/us159-da14531evz-pmod.webp differ diff --git a/boards/shields/renesas_us159_da14531evz/renesas_us159_da14531evz.overlay b/boards/shields/renesas_us159_da14531evz/renesas_us159_da14531evz.overlay new file mode 100644 index 00000000000..e943e75dc03 --- /dev/null +++ b/boards/shields/renesas_us159_da14531evz/renesas_us159_da14531evz.overlay @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + chosen { + zephyr,bt-hci = &bt_hci_uart; + }; +}; + +&pmod_serial { + status = "okay"; + + bt_hci_uart: bt_hci_uart { + compatible = "zephyr,bt-hci-uart"; + status = "okay"; + + da1453x { + compatible = "renesas,bt-hci-da1453x"; + status = "okay"; + reset-gpios = <&pmod_header 5 GPIO_ACTIVE_LOW>; + }; + }; +}; diff --git a/boards/shields/rk043fn02h_ct/rk043fn02h_ct.overlay b/boards/shields/rk043fn02h_ct/rk043fn02h_ct.overlay index ab0b10d70af..ee76848b220 100644 --- a/boards/shields/rk043fn02h_ct/rk043fn02h_ct.overlay +++ b/boards/shields/rk043fn02h_ct/rk043fn02h_ct.overlay @@ -9,6 +9,7 @@ /{ chosen { zephyr,display = &zephyr_lcdif; + zephyr,touch = &ft5336_rk043fn02h_ct; }; lvgl_pointer { diff --git a/boards/shields/rk043fn66hs_ctg/rk043fn66hs_ctg.overlay b/boards/shields/rk043fn66hs_ctg/rk043fn66hs_ctg.overlay index b992ec932b8..6231bd51db3 100644 --- a/boards/shields/rk043fn66hs_ctg/rk043fn66hs_ctg.overlay +++ b/boards/shields/rk043fn66hs_ctg/rk043fn66hs_ctg.overlay @@ -9,6 +9,7 @@ /{ chosen { zephyr,display = &zephyr_lcdif; + zephyr,touch = >911_rk043fn66hs_ctg; }; lvgl_pointer { diff --git a/boards/shields/rk055hdmipi4m/boards/mimxrt595_evk_mimxrt595s_cm33.conf b/boards/shields/rk055hdmipi4m/boards/mimxrt595_evk_mimxrt595s_cm33.conf index bf60c87c693..000b59e0b43 100644 --- a/boards/shields/rk055hdmipi4m/boards/mimxrt595_evk_mimxrt595s_cm33.conf +++ b/boards/shields/rk055hdmipi4m/boards/mimxrt595_evk_mimxrt595s_cm33.conf @@ -6,7 +6,7 @@ # Use external framebuffer memory CONFIG_MCUX_DCNANO_LCDIF_EXTERNAL_FB_MEM=y -CONFIG_LV_Z_VBD_CUSTOM_SECTION=y +CONFIG_LV_Z_VDB_CUSTOM_SECTION=y # Use FlexSPI2 for framebuffer (pSRAM is present on this bus) CONFIG_MCUX_DCNANO_LCDIF_EXTERNAL_FB_ADDR=0x38400000 # M33 core and LCDIF both access FlexSPI2 through the same cache, diff --git a/boards/shields/rk055hdmipi4m/rk055hdmipi4m.overlay b/boards/shields/rk055hdmipi4m/rk055hdmipi4m.overlay index 58e610fc59e..a7526a3353a 100644 --- a/boards/shields/rk055hdmipi4m/rk055hdmipi4m.overlay +++ b/boards/shields/rk055hdmipi4m/rk055hdmipi4m.overlay @@ -9,6 +9,7 @@ /{ chosen { zephyr,display = &lcdif; + zephyr,touch = >911_rk055hdmipi4m; }; en_mipi_display: enable-mipi-display { diff --git a/boards/shields/rk055hdmipi4ma0/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay b/boards/shields/rk055hdmipi4ma0/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay new file mode 100644 index 00000000000..7578cac75c2 --- /dev/null +++ b/boards/shields/rk055hdmipi4ma0/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay @@ -0,0 +1,10 @@ +/* + * Copyright 2024, NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&zephyr_mipi_dsi { + /* Raise the DSI clock frequency */ + phy-clock = <792000000>; +}; diff --git a/boards/shields/rk055hdmipi4ma0/boards/mimxrt1170_evk_mimxrt1176_cm7.overlay b/boards/shields/rk055hdmipi4ma0/boards/mimxrt1170_evk_mimxrt1176_cm7.overlay new file mode 100644 index 00000000000..7578cac75c2 --- /dev/null +++ b/boards/shields/rk055hdmipi4ma0/boards/mimxrt1170_evk_mimxrt1176_cm7.overlay @@ -0,0 +1,10 @@ +/* + * Copyright 2024, NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&zephyr_mipi_dsi { + /* Raise the DSI clock frequency */ + phy-clock = <792000000>; +}; diff --git a/boards/shields/rk055hdmipi4ma0/boards/mimxrt595_evk_mimxrt595s_cm33.conf b/boards/shields/rk055hdmipi4ma0/boards/mimxrt595_evk_mimxrt595s_cm33.conf index bf60c87c693..000b59e0b43 100644 --- a/boards/shields/rk055hdmipi4ma0/boards/mimxrt595_evk_mimxrt595s_cm33.conf +++ b/boards/shields/rk055hdmipi4ma0/boards/mimxrt595_evk_mimxrt595s_cm33.conf @@ -6,7 +6,7 @@ # Use external framebuffer memory CONFIG_MCUX_DCNANO_LCDIF_EXTERNAL_FB_MEM=y -CONFIG_LV_Z_VBD_CUSTOM_SECTION=y +CONFIG_LV_Z_VDB_CUSTOM_SECTION=y # Use FlexSPI2 for framebuffer (pSRAM is present on this bus) CONFIG_MCUX_DCNANO_LCDIF_EXTERNAL_FB_ADDR=0x38400000 # M33 core and LCDIF both access FlexSPI2 through the same cache, diff --git a/boards/shields/rk055hdmipi4ma0/rk055hdmipi4ma0.overlay b/boards/shields/rk055hdmipi4ma0/rk055hdmipi4ma0.overlay index 7df9f53b6a3..6c353d09372 100644 --- a/boards/shields/rk055hdmipi4ma0/rk055hdmipi4ma0.overlay +++ b/boards/shields/rk055hdmipi4ma0/rk055hdmipi4ma0.overlay @@ -9,6 +9,7 @@ /{ chosen { zephyr,display = &lcdif; + zephyr,touch = >911_rk055hdmipi4ma0; }; en_mipi_display_rk055hdmipi4ma0: enable-mipi-display-rk055hdmipi4ma0 { diff --git a/boards/shields/rtkmipilcdb00000be/Kconfig.defconfig b/boards/shields/rtkmipilcdb00000be/Kconfig.defconfig new file mode 100644 index 00000000000..749284f97fb --- /dev/null +++ b/boards/shields/rtkmipilcdb00000be/Kconfig.defconfig @@ -0,0 +1,57 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +if SHIELD_RTKMIPILCDB00000BE +if DISPLAY + +# Enable MIPI DSI, as this display controller requires it. + +config MIPI_DSI + default y + +endif # DISPLAY + +if LVGL + +# Configure LVGL to use touchscreen with input API + +config INPUT + default y + +if INPUT + +# GT911 driver drives reset pin low, GT911 and ILI9806E_DSI driver share a reset line, +# so it needs to initialize before the display_ili9806e_dsi driver but after the MIPI DSI driver + +config INPUT_INIT_PRIORITY + default 89 + +endif # INPUT + +# LVGL should allocate buffers equal to size of display +config LV_Z_VDB_SIZE + default 100 + +# Enable double buffering +config LV_Z_DOUBLE_VDB + default y + +# Force full refresh. This prevents memory copy associated with partial +# display refreshes, which is not necessary for the GLCDC driver +config LV_Z_FULL_REFRESH + default y + +config LV_Z_BITS_PER_PIXEL + default 32 + +# Use offloaded render thread +config LV_Z_FLUSH_THREAD + default y + +choice LV_COLOR_DEPTH + default LV_COLOR_DEPTH_32 +endchoice + +endif # LVGL + +endif # SHIELD_RTKMIPILCDB00000BE diff --git a/boards/shields/rtkmipilcdb00000be/Kconfig.shield b/boards/shields/rtkmipilcdb00000be/Kconfig.shield new file mode 100644 index 00000000000..0081d3f9819 --- /dev/null +++ b/boards/shields/rtkmipilcdb00000be/Kconfig.shield @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SHIELD_RTKMIPILCDB00000BE + def_bool $(shields_list_contains,rtkmipilcdb00000be) diff --git a/boards/shields/rtkmipilcdb00000be/boards/ek_ra8d1.overlay b/boards/shields/rtkmipilcdb00000be/boards/ek_ra8d1.overlay new file mode 100644 index 00000000000..30399bc741f --- /dev/null +++ b/boards/shields/rtkmipilcdb00000be/boards/ek_ra8d1.overlay @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + iic1_default: iic1_default { + group1 { + /* SCL1 SDA1 */ + psels = , + ; + drive-strength = "medium"; + }; + }; +}; + +&iic1 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = ; + pinctrl-0 = <&iic1_default>; + pinctrl-names = "default"; +}; diff --git a/boards/shields/rtkmipilcdb00000be/doc/index.rst b/boards/shields/rtkmipilcdb00000be/doc/index.rst new file mode 100644 index 00000000000..4e77512e6d5 --- /dev/null +++ b/boards/shields/rtkmipilcdb00000be/doc/index.rst @@ -0,0 +1,61 @@ +.. _rtkmipilcdb00000be: + +RTKMIPILCDB00000BE MIPI Display +############################### + +Overview +******** + +The Focus LCDs RTKMIPILCDB00000BE MIPI Display is a 4.5 inch TFT 480x854 pixels +capacitive touch panel, and a backlight unit. + +This display uses a 26 pin connector header. + +Pins Assignment of the Renesas RTKMIPILCDB00000BE MIPI Display +============================================================== + ++-----------------------+------------------------+ +| Connector Pin | Function | ++=======================+========================+ +| 14 | Touch ctrl I2C SDA | ++-----------------------+------------------------+ +| 15 | Display backlight enable| ++-----------------------+------------------------+ +| 16 | Touch ctrl I2C SCL | ++-----------------------+------------------------+ +| 17 | External interrupt | ++-----------------------+------------------------+ +| 18 | Display reset | ++-----------------------+------------------------+ + +Hardware Requirements: +********************** + +Supported Renesas RA boards: EK-RA8D1 +- 1 x RA Board +- 1 x Micro USB cable + +Hardware Configuration: +*********************** + +The MIPI Graphics Expansion Port (J58) connects the EK-RA8D1 board to the MIPI Graphics Expansion Board +supplied as part of the kit. + +Set the configuration switches (SW1) as below to avoid potential failures. + +-------------+-------------+--------------+------------+------------+------------+-------------+-----------+ + | SW1-1 PMOD1 | SW1-2 TRACE | SW1-3 CAMERA | SW1-4 ETHA | SW1-5 ETHB | SW1-6 GLCD | SW1-7 SDRAM | SW1-8 I3C | + +-------------+-------------+--------------+------------+------------+------------+-------------+-----------+ + | OFF | OFF | OFF | OFF | OFF | ON | ON | OFF | + +-------------+-------------+--------------+------------+------------+------------+-------------+-----------+ + +Programming +*********** + +Set ``--shield=rtkmipilcdb00000be`` when you invoke ``west build``. For +example: + +.. zephyr-app-commands:: + :zephyr-app: tests/drivers/display/display_read_write + :board: ek_ra8d1 + :shield: rtkmipilcdb00000be + :goals: build diff --git a/boards/shields/rtkmipilcdb00000be/rtkmipilcdb00000be.overlay b/boards/shields/rtkmipilcdb00000be/rtkmipilcdb00000be.overlay new file mode 100644 index 00000000000..1902a9cb55b --- /dev/null +++ b/boards/shields/rtkmipilcdb00000be/rtkmipilcdb00000be.overlay @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/{ + chosen { + zephyr,display = &zephyr_lcdif; + }; + + lvgl_pointer { + compatible = "zephyr,lvgl-pointer-input"; + input = <>911_rtkmipilcdb00000be>; + }; +}; + +&renesas_mipi_i2c { + status = "okay"; + gt911_rtkmipilcdb00000be: gt911-rtkmipilcdb00000be@5d { + compatible = "goodix,gt911"; + reg = <0x5d>; + irq-gpios = <&renesas_mipi_connector 17 GPIO_ACTIVE_HIGH>; + reset-gpios = <&renesas_mipi_connector 18 GPIO_ACTIVE_LOW>; + }; +}; + +&zephyr_mipi_dsi { + status = "okay"; + ili9806e: ili9806e@0 { + status = "okay"; + compatible = "ilitek,ili9806e-dsi"; + reg = <0x0>; + height = <854>; + width = <480>; + data-lanes = <2>; + pixel-format = ; + }; +}; + +&zephyr_lcdif { + status = "okay"; + width = <480>; + height = <854>; + input-pixel-format = ; + output-pixel-format = ; + display-timings { + compatible = "zephyr,panel-timing"; + hsync-len = <2>; + hback-porch = <5>; + vsync-len = <3>; + vback-porch = <20>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + hfront-porch = <72>; + vfront-porch = <17>; + }; + backlight-gpios = <&renesas_mipi_connector 15 GPIO_ACTIVE_HIGH>; +}; diff --git a/boards/shields/seeed_w5500/Kconfig.defconfig b/boards/shields/seeed_w5500/Kconfig.defconfig new file mode 100644 index 00000000000..72924f7ec8d --- /dev/null +++ b/boards/shields/seeed_w5500/Kconfig.defconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2024 Marcin Niestroj +# SPDX-License-Identifier: Apache-2.0 + +if SHIELD_SEEED_W5500 + +if NETWORKING + +config NET_L2_ETHERNET + default y + +endif # NETWORKING + +endif # SHIELD_SEEED_W5500 diff --git a/boards/shields/seeed_w5500/Kconfig.shield b/boards/shields/seeed_w5500/Kconfig.shield new file mode 100644 index 00000000000..cb5de82d457 --- /dev/null +++ b/boards/shields/seeed_w5500/Kconfig.shield @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Marcin Niestroj +# SPDX-License-Identifier: Apache-2.0 + +config SHIELD_SEEED_W5500 + def_bool $(shields_list_contains,seeed_w5500) diff --git a/boards/shields/seeed_w5500/doc/index.rst b/boards/shields/seeed_w5500/doc/index.rst new file mode 100644 index 00000000000..3ba095ce0f7 --- /dev/null +++ b/boards/shields/seeed_w5500/doc/index.rst @@ -0,0 +1,70 @@ +.. _seeed_w5500: + +Seeed W5500 Ethernet Shield +########################### + +Overview +******** + +Seeed `W5500 Ethernet Shield`_ is an Arduino connector shield with: + +- `W5500`_ 10/100 MBPS stand alone Ethernet controller with on-board MAC & PHY + and 16 KiloBytes for FIFO buffer, +- SPI serial interface, +- Grove UART connector, +- Grove I2C connector, +- SD card slot. + +.. figure:: seeed_w5500.webp + :align: center + :alt: Seeed W5500 Ethernet Shield + + Seeed W5500 Ethernet Shield + +Pins Assignment of the W5500 Shield +=================================== + ++-----------------------+---------------------------------------------+ +| Shield Connector Pin | Function | ++=======================+=============================================+ +| RST | Ethernet Controller's Reset | ++-----------------------+---------------------------------------------+ +| D2 | Ethernet Controller's Interrupt Output | ++-----------------------+---------------------------------------------+ +| D10 | SPI's Chip Select | ++-----------------------+---------------------------------------------+ +| D11 | SPI's Master Output Slave Input (MOSI) | ++-----------------------+---------------------------------------------+ +| D12 | SPI's Master Input Slave Output (MISO) | ++-----------------------+---------------------------------------------+ +| D13 | SPI's Clock | ++-----------------------+---------------------------------------------+ + +Requirements +************ + +This shield can only be used with a board that provides a configuration +for Arduino connectors and defines node aliases for SPI and GPIO interfaces +(see :ref:`shields` for more details). + +Programming +*********** + +Set ``--shield seeed_w5500`` when you invoke ``west build``. For example: + +.. zephyr-app-commands:: + :zephyr-app: samples/net/dhcpv4_client + :board: nrf52840dk/nrf52840 + :shield: seeed_w5500 + :goals: build + +References +********** + +.. target-notes:: + +.. _W5500: + https://wiznet.io/products/iethernet-chips/w5500 + +.. _W5500 Ethernet Shield: + https://wiki.seeedstudio.com/W5500_Ethernet_Shield_v1.0 diff --git a/boards/shields/seeed_w5500/doc/seeed_w5500.webp b/boards/shields/seeed_w5500/doc/seeed_w5500.webp new file mode 100644 index 00000000000..83477d34fc0 Binary files /dev/null and b/boards/shields/seeed_w5500/doc/seeed_w5500.webp differ diff --git a/boards/shields/seeed_w5500/seeed_w5500.overlay b/boards/shields/seeed_w5500/seeed_w5500.overlay new file mode 100644 index 00000000000..9551c0f0e3a --- /dev/null +++ b/boards/shields/seeed_w5500/seeed_w5500.overlay @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2024 Marcin Niestroj + * SPDX-License-Identifier: Apache-2.0 + */ + +&arduino_spi { + status = "okay"; + + eth_w5500: eth-w5500@0 { + compatible = "wiznet,w5500"; + reg = <0x0>; + spi-max-frequency = ; + int-gpios = <&arduino_header 8 GPIO_ACTIVE_LOW>; /* D2 */ + }; +}; diff --git a/boards/shields/seeed_xiao_expansion_board/seeed_xiao_expansion_board.overlay b/boards/shields/seeed_xiao_expansion_board/seeed_xiao_expansion_board.overlay index b61e2c85fc5..54405f39d73 100644 --- a/boards/shields/seeed_xiao_expansion_board/seeed_xiao_expansion_board.overlay +++ b/boards/shields/seeed_xiao_expansion_board/seeed_xiao_expansion_board.overlay @@ -60,6 +60,7 @@ status = "okay"; mmc { compatible = "zephyr,sdmmc-disk"; + disk-name = "SD"; status = "okay"; }; spi-max-frequency = <24000000>; diff --git a/boards/shields/seeed_xiao_round_display/Kconfig.defconfig b/boards/shields/seeed_xiao_round_display/Kconfig.defconfig index 81cbf380745..443d5ba03b9 100644 --- a/boards/shields/seeed_xiao_round_display/Kconfig.defconfig +++ b/boards/shields/seeed_xiao_round_display/Kconfig.defconfig @@ -14,7 +14,7 @@ choice LV_COLOR_DEPTH default LV_COLOR_DEPTH_16 endchoice -config LV_COLOR_16_SWAP +configdefault LV_COLOR_16_SWAP default y endif # LVGL diff --git a/boards/shields/seeed_xiao_round_display/seeed_xiao_round_display.overlay b/boards/shields/seeed_xiao_round_display/seeed_xiao_round_display.overlay index d4a3ad1329e..9e0540d8231 100644 --- a/boards/shields/seeed_xiao_round_display/seeed_xiao_round_display.overlay +++ b/boards/shields/seeed_xiao_round_display/seeed_xiao_round_display.overlay @@ -10,6 +10,7 @@ / { chosen { zephyr,display = &gc9a01_xiao_round_display; + zephyr,touch = &chsc6x_xiao_round_display; }; vbatt { @@ -88,6 +89,7 @@ status = "okay"; mmc { compatible = "zephyr,sdmmc-disk"; + disk-name = "SD"; status = "okay"; }; spi-max-frequency = ; diff --git a/boards/shields/semtech_sx1276mb1mas/doc/index.rst b/boards/shields/semtech_sx1276mb1mas/doc/index.rst index d4b7d07c454..ef72a16d324 100644 --- a/boards/shields/semtech_sx1276mb1mas/doc/index.rst +++ b/boards/shields/semtech_sx1276mb1mas/doc/index.rst @@ -58,7 +58,7 @@ Arduino connectors and defines node aliases for SPI and GPIO interfaces (see Programming *********** -Set ``--shield semtech_sx1271mb1mas`` when you invoke ``west build``. For +Set ``--shield semtech_sx1276mb1mas`` when you invoke ``west build``. For example: .. zephyr-app-commands:: diff --git a/boards/shields/sparkfun_carrier_asset_tracker/Kconfig.defconfig b/boards/shields/sparkfun_carrier_asset_tracker/Kconfig.defconfig deleted file mode 100644 index da44e62a05f..00000000000 --- a/boards/shields/sparkfun_carrier_asset_tracker/Kconfig.defconfig +++ /dev/null @@ -1,21 +0,0 @@ -# Copyright (c) 2024 Jerónimo Agulló -# SPDX-License-Identifier: Apache-2.0 - -if SHIELD_SPARKFUN_CARRIER_ASSET_TRACKER - -config SERIAL - default y - -config UART_INTERRUPT_DRIVEN - default y - -config UART_ASYNC_API - default y - -config I2C - default y - -config SPI - default y - -endif # SHIELD_SPARKFUN_CARRIER_ASSET_TRACKER diff --git a/boards/shields/sparkfun_carrier_asset_tracker/sparkfun_carrier_asset_tracker.overlay b/boards/shields/sparkfun_carrier_asset_tracker/sparkfun_carrier_asset_tracker.overlay index 6c7a9383c27..83416900763 100644 --- a/boards/shields/sparkfun_carrier_asset_tracker/sparkfun_carrier_asset_tracker.overlay +++ b/boards/shields/sparkfun_carrier_asset_tracker/sparkfun_carrier_asset_tracker.overlay @@ -35,6 +35,7 @@ status = "okay"; mmc { compatible = "zephyr,sdmmc-disk"; + disk-name = "SD"; status = "okay"; }; spi-max-frequency = ; diff --git a/boards/shields/st7735r/st7735r_ada_160x128.overlay b/boards/shields/st7735r/st7735r_ada_160x128.overlay index d769b9a1a4d..1547c6fa281 100644 --- a/boards/shields/st7735r/st7735r_ada_160x128.overlay +++ b/boards/shields/st7735r/st7735r_ada_160x128.overlay @@ -22,7 +22,7 @@ st7735r_st7735r_ada_160x128: st7735r@0 { compatible = "sitronix,st7735r"; mipi-max-frequency = <20000000>; - mipi-mode = ; + mipi-mode = "MIPI_DBI_MODE_SPI_4WIRE"; reg = <0>; width = <160>; height = <128>; diff --git a/boards/shields/st7789v_generic/Kconfig.defconfig b/boards/shields/st7789v_generic/Kconfig.defconfig index e0057a2e9d7..b28cf38f78c 100644 --- a/boards/shields/st7789v_generic/Kconfig.defconfig +++ b/boards/shields/st7789v_generic/Kconfig.defconfig @@ -20,7 +20,7 @@ choice LV_COLOR_DEPTH default LV_COLOR_DEPTH_16 if SHIELD_ST7789V_WAVESHARE_240X240 endchoice -config LV_COLOR_16_SWAP +configdefault LV_COLOR_16_SWAP default y if SHIELD_ST7789V_WAVESHARE_240X240 endif # LVGL diff --git a/boards/shields/st7789v_generic/st7789v_tl019fqv01.overlay b/boards/shields/st7789v_generic/st7789v_tl019fqv01.overlay index 46c863b5ac8..059f9d565b6 100644 --- a/boards/shields/st7789v_generic/st7789v_tl019fqv01.overlay +++ b/boards/shields/st7789v_generic/st7789v_tl019fqv01.overlay @@ -42,7 +42,7 @@ nvgam-param = [D0 00 02 07 05 15 2D 44 44 1C 18 16 1C 1D]; ram-param = [00 F8]; rgb-param = [CD 08 14]; - mipi-mode = ; + mipi-mode = "MIPI_DBI_MODE_SPI_4WIRE"; }; }; }; diff --git a/boards/shields/st7789v_generic/st7789v_waveshare_240x240.overlay b/boards/shields/st7789v_generic/st7789v_waveshare_240x240.overlay index 0a92937a982..e4128572b44 100644 --- a/boards/shields/st7789v_generic/st7789v_waveshare_240x240.overlay +++ b/boards/shields/st7789v_generic/st7789v_waveshare_240x240.overlay @@ -44,7 +44,7 @@ nvgam-param = [D0 04 0C 11 13 2C 3F 44 51 2F 1F 1F 20 23]; ram-param = [00 F0]; rgb-param = [CD 08 14]; - mipi-mode = ; + mipi-mode = "MIPI_DBI_MODE_SPI_4WIRE"; }; }; }; diff --git a/boards/shields/st_b_lcd40_dsi1_mb1166/Kconfig.defconfig b/boards/shields/st_b_lcd40_dsi1_mb1166/Kconfig.defconfig index 2fe69bcea06..5c734b992f3 100644 --- a/boards/shields/st_b_lcd40_dsi1_mb1166/Kconfig.defconfig +++ b/boards/shields/st_b_lcd40_dsi1_mb1166/Kconfig.defconfig @@ -4,27 +4,13 @@ if SHIELD_ST_B_LCD40_DSI1_MB1166 || SHIELD_ST_B_LCD40_DSI1_MB1166_A09 -# Double frame buffer maintained by lvgl. -if LVGL +orsource "boards/*.defconfig" -config STM32_LTDC_FB_NUM - default 0 +if LVGL config INPUT default y -config LV_Z_VDB_SIZE - default 100 - -config LV_Z_DOUBLE_VDB - default y - -config LV_Z_VBD_CUSTOM_SECTION - default y - -config LV_Z_FULL_REFRESH - default y - config LV_Z_BITS_PER_PIXEL default 32 diff --git a/boards/shields/st_b_lcd40_dsi1_mb1166/boards/st_b_lcd40_dsi1_mb1166/stm32h747i_disco_stm32h747xx_m7.overlay b/boards/shields/st_b_lcd40_dsi1_mb1166/boards/st_b_lcd40_dsi1_mb1166/stm32h747i_disco_stm32h747xx_m7.overlay deleted file mode 100644 index 554e9777f1c..00000000000 --- a/boards/shields/st_b_lcd40_dsi1_mb1166/boards/st_b_lcd40_dsi1_mb1166/stm32h747i_disco_stm32h747xx_m7.overlay +++ /dev/null @@ -1,21 +0,0 @@ -/* - * Copyright (c) 2023 bytes at work AG - * - * SPDX-License-Identifier: Apache-2.0 - */ -<dc { - /* orisetech, otm8009a */ - display-timings { - compatible = "zephyr,panel-timing"; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - hsync-len = <2>; - vsync-len = <1>; - hback-porch = <34>; - vback-porch = <15>; - hfront-porch = <34>; - vfront-porch = <16>; - }; -}; diff --git a/boards/shields/st_b_lcd40_dsi1_mb1166/boards/st_b_lcd40_dsi1_mb1166_a09/stm32h747i_disco_stm32h747xx_m7.overlay b/boards/shields/st_b_lcd40_dsi1_mb1166/boards/st_b_lcd40_dsi1_mb1166_a09/stm32h747i_disco_stm32h747xx_m7.overlay index 90ddb549d7a..3710329ee9a 100644 --- a/boards/shields/st_b_lcd40_dsi1_mb1166/boards/st_b_lcd40_dsi1_mb1166_a09/stm32h747i_disco_stm32h747xx_m7.overlay +++ b/boards/shields/st_b_lcd40_dsi1_mb1166/boards/st_b_lcd40_dsi1_mb1166_a09/stm32h747i_disco_stm32h747xx_m7.overlay @@ -4,27 +4,9 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include - -&mipi_dsi { +&zephyr_mipi_dsi { + status = "okay"; loosely-packed; largest-packet-size = <64>; bta-ack-disable; }; - -<dc { - /* frida, nt35510 */ - display-timings { - compatible = "zephyr,panel-timing"; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - hsync-len = <2>; - vsync-len = <120>; - hback-porch = <34>; - vback-porch = <150>; - hfront-porch = <34>; - vfront-porch = <150>; - }; -}; diff --git a/boards/shields/st_b_lcd40_dsi1_mb1166/boards/stm32h747i_disco_stm32h747xx_m7.defconfig b/boards/shields/st_b_lcd40_dsi1_mb1166/boards/stm32h747i_disco_stm32h747xx_m7.defconfig new file mode 100644 index 00000000000..f7cdddf0944 --- /dev/null +++ b/boards/shields/st_b_lcd40_dsi1_mb1166/boards/stm32h747i_disco_stm32h747xx_m7.defconfig @@ -0,0 +1,21 @@ +# Copyright (c) 2024 Linumiz +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_STM32H747I_DISCO_STM32H747XX_M7 +if LVGL + +# Double frame buffer maintained by lvgl. +config STM32_LTDC_FB_NUM + default 0 + +config LV_Z_DOUBLE_VDB + default y + +config LV_Z_VDB_CUSTOM_SECTION + default y + +config LV_Z_FULL_REFRESH + default y + +endif #LVGL +endif # BOARD_STM32H747I_DISCO_STM32H747XX_M7 diff --git a/boards/shields/st_b_lcd40_dsi1_mb1166/boards/stm32h747i_disco_stm32h747xx_m7.overlay b/boards/shields/st_b_lcd40_dsi1_mb1166/boards/stm32h747i_disco_stm32h747xx_m7.overlay index 7a80559b8c9..7d96dd56e8d 100644 --- a/boards/shields/st_b_lcd40_dsi1_mb1166/boards/stm32h747i_disco_stm32h747xx_m7.overlay +++ b/boards/shields/st_b_lcd40_dsi1_mb1166/boards/stm32h747i_disco_stm32h747xx_m7.overlay @@ -4,34 +4,17 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include - -/ { - lvgl_pointer { - compatible = "zephyr,lvgl-pointer-input"; - input = <&ft5336>; - invert-y; - }; - - chosen { - zephyr,display = <dc; - }; -}; - &sdram2 { - /* Frame buffer memory cache will cause screen flickering. */ + /* Frame buffer memory when cached causes screen flickering. */ zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>; }; -<dc { +&zephyr_lcd_controller { status = "okay"; ext-sdram = <&sdram2>; - width = <800>; - height = <480>; def-back-color-red = <0>; def-back-color-green = <0>; def-back-color-blue = <0>; - pixel-format = ; }; /* ltdc uses pll3_r as pixel clock */ @@ -45,7 +28,7 @@ div-r = <24>; /* 27.5 MHz */ }; -&mipi_dsi { +&zephyr_mipi_dsi { status = "okay"; /* DSI HOST dedicated PLL @@ -61,15 +44,3 @@ hs-active-high; de-active-high; }; - -&i2c4 { - pinctrl-0 = <&i2c4_scl_pd12 &i2c4_sda_pd13>; - pinctrl-names = "default"; - clock-frequency = ; - status = "okay"; - - ft5336: ft5336@38 { - compatible = "focaltech,ft5336"; - reg = <0x38>; - }; -}; diff --git a/boards/shields/st_b_lcd40_dsi1_mb1166/st_b_lcd40_dsi1_mb1166.overlay b/boards/shields/st_b_lcd40_dsi1_mb1166/st_b_lcd40_dsi1_mb1166.overlay index f351cae9cdb..5e577214d27 100644 --- a/boards/shields/st_b_lcd40_dsi1_mb1166/st_b_lcd40_dsi1_mb1166.overlay +++ b/boards/shields/st_b_lcd40_dsi1_mb1166/st_b_lcd40_dsi1_mb1166.overlay @@ -4,7 +4,22 @@ * SPDX-License-Identifier: Apache-2.0 */ -&mipi_dsi { +#include + +/ { + lvgl_pointer { + compatible = "zephyr,lvgl-pointer-input"; + input = <&ft5336>; + invert-y; + }; + + chosen { + zephyr,display = &zephyr_lcd_controller; + }; +}; + +&zephyr_mipi_dsi { + status = "okay"; otm8009a: otm8009a@0 { status = "okay"; compatible = "orisetech,otm8009a"; @@ -18,3 +33,33 @@ rotation = <90>; }; }; + +&zephyr_lcd_controller { + status = "okay"; + width = <800>; + height = <480>; + pixel-format = ; + /* orisetech, otm8009a */ + display-timings { + compatible = "zephyr,panel-timing"; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + hsync-len = <2>; + vsync-len = <1>; + hback-porch = <34>; + vback-porch = <15>; + hfront-porch = <34>; + vfront-porch = <16>; + }; +}; + +&qsh_030_i2c { + ft5336: ft5336@38 { + compatible = "focaltech,ft5336"; + reg = <0x38>; + int-gpios = <&dsi_lcd_qsh_030 4 0>; + status = "okay"; + }; +}; diff --git a/boards/shields/st_b_lcd40_dsi1_mb1166/st_b_lcd40_dsi1_mb1166_a09.overlay b/boards/shields/st_b_lcd40_dsi1_mb1166/st_b_lcd40_dsi1_mb1166_a09.overlay index 0201678d4d0..ddef9b74e02 100644 --- a/boards/shields/st_b_lcd40_dsi1_mb1166/st_b_lcd40_dsi1_mb1166_a09.overlay +++ b/boards/shields/st_b_lcd40_dsi1_mb1166/st_b_lcd40_dsi1_mb1166_a09.overlay @@ -4,7 +4,22 @@ * SPDX-License-Identifier: Apache-2.0 */ -&mipi_dsi { +#include + +/ { + lvgl_pointer { + compatible = "zephyr,lvgl-pointer-input"; + input = <&ft5336>; + invert-y; + }; + + chosen { + zephyr,display = &zephyr_lcd_controller; + }; +}; + +&zephyr_mipi_dsi { + status = "okay"; nt35510: nt35510@0 { status = "okay"; compatible = "frida,nt35510"; @@ -18,3 +33,33 @@ rotation = <90>; }; }; + +&zephyr_lcd_controller { + status = "okay"; + width = <800>; + height = <480>; + pixel-format = ; + /* frida, nt35510 */ + display-timings { + compatible = "zephyr,panel-timing"; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + hsync-len = <2>; + vsync-len = <120>; + hback-porch = <34>; + vback-porch = <150>; + hfront-porch = <34>; + vfront-porch = <150>; + }; +}; + +&qsh_030_i2c { + ft5336: ft5336@38 { + compatible = "focaltech,ft5336"; + reg = <0x38>; + int-gpios = <&dsi_lcd_qsh_030 4 0>; + status = "okay"; + }; +}; diff --git a/boards/shields/v2c_daplink/v2c_daplink.overlay b/boards/shields/v2c_daplink/v2c_daplink.overlay index 2ecc1feeb00..110971cafbb 100644 --- a/boards/shields/v2c_daplink/v2c_daplink.overlay +++ b/boards/shields/v2c_daplink/v2c_daplink.overlay @@ -41,6 +41,7 @@ spi-max-frequency = <25000000>; mmc { compatible = "zephyr,sdmmc-disk"; + disk-name = "SD"; status = "okay"; }; }; diff --git a/boards/shields/v2c_daplink/v2c_daplink_cfg.overlay b/boards/shields/v2c_daplink/v2c_daplink_cfg.overlay index 0a00a2792bb..1a4c31d7199 100644 --- a/boards/shields/v2c_daplink/v2c_daplink_cfg.overlay +++ b/boards/shields/v2c_daplink/v2c_daplink_cfg.overlay @@ -33,6 +33,7 @@ spi-max-frequency = <25000000>; mmc { compatible = "zephyr,sdmmc-disk"; + disk-name = "SD"; status = "okay"; }; }; diff --git a/boards/shields/waveshare_epaper/dts/waveshare_epaper_common.dtsi b/boards/shields/waveshare_epaper/dts/waveshare_epaper_common.dtsi index 9e62469af64..80480cf5787 100644 --- a/boards/shields/waveshare_epaper/dts/waveshare_epaper_common.dtsi +++ b/boards/shields/waveshare_epaper/dts/waveshare_epaper_common.dtsi @@ -16,6 +16,7 @@ spi-max-frequency = <24000000>; mmc { compatible = "zephyr,sdmmc-disk"; + disk-name = "SD"; status = "okay"; }; }; diff --git a/boards/shields/weact_ov2640_cam_module/Kconfig.shield b/boards/shields/weact_ov2640_cam_module/Kconfig.shield new file mode 100644 index 00000000000..a00d675d780 --- /dev/null +++ b/boards/shields/weact_ov2640_cam_module/Kconfig.shield @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Charles Dias +# SPDX-License-Identifier: Apache-2.0 + +config SHIELD_WEACT_OV2640_CAM_MODULE + def_bool $(shields_list_contains,weact_ov2640_cam_module) diff --git a/boards/shields/weact_ov2640_cam_module/boards/mini_stm32h743.conf b/boards/shields/weact_ov2640_cam_module/boards/mini_stm32h743.conf new file mode 100644 index 00000000000..48b3a8db88d --- /dev/null +++ b/boards/shields/weact_ov2640_cam_module/boards/mini_stm32h743.conf @@ -0,0 +1,8 @@ +# +# Copyright (c) 2024 Charles Dias +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_VIDEO_HFLIP=y +CONFIG_VIDEO_VFLIP=y diff --git a/boards/shields/weact_ov2640_cam_module/boards/mini_stm32h743.overlay b/boards/shields/weact_ov2640_cam_module/boards/mini_stm32h743.overlay new file mode 100644 index 00000000000..e9923727607 --- /dev/null +++ b/boards/shields/weact_ov2640_cam_module/boards/mini_stm32h743.overlay @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2024 Charles Dias + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* AHB clocks must respect the minimum ratio AHB / DCMI_PIXCLK of 2.5 (AN5020 - Rev 3). + * The OV2640 PCLK is around 72 MHz for QQVGA resolution (160x120) with MCO1_SEL_HSI48 + * and MCO1_PRE_DIV_4. + */ +&rcc { + clocks = <&pll>; + clock-frequency = ; + d1cpre = <1>; + hpre = <1>; + d1ppre = <2>; + d2ppre1 = <2>; + d2ppre2 = <2>; + d3ppre = <2>; +}; + +/* See reference manual (RM0433 Rev 8) page 390: + * 100: HSI48 clock selected (hsi48_ck) + */ +#define MCO1_SEL_HSI48 4 + + /* See reference manual (RM0433 Rev 8) page 391: + * 0100: division by 4 + */ +#define MCO1_PRE_DIV_4 4 + +&mco1 { + status = "okay"; + clocks = <&rcc STM32_SRC_HSI48 MCO1_SEL(MCO1_SEL_HSI48)>; + prescaler = ; + pinctrl-0 = <&rcc_mco_1_pa8>; + pinctrl-names = "default"; +}; + +&zephyr_camera_i2c { + ov2640: ov2640@30 { + supply-gpios = <&dcmi_camera_connector 8 GPIO_ACTIVE_HIGH>; + clock-rate-control = <0x80>; + }; +}; + +&zephyr_camera_dvp { + dmas = <&dma1 0 75 (STM32_DMA_PERIPH_TO_MEMORY | STM32_DMA_PERIPH_NO_INC | + STM32_DMA_MEM_INC | STM32_DMA_PERIPH_8BITS | STM32_DMA_MEM_32BITS | + STM32_DMA_PRIORITY_HIGH) STM32_DMA_FIFO_1_4>; +}; + +&dma1 { + status = "okay"; +}; + +&dmamux1 { + status = "okay"; +}; diff --git a/boards/shields/weact_ov2640_cam_module/doc/index.rst b/boards/shields/weact_ov2640_cam_module/doc/index.rst new file mode 100644 index 00000000000..1609fc5a23d --- /dev/null +++ b/boards/shields/weact_ov2640_cam_module/doc/index.rst @@ -0,0 +1,82 @@ +.. _weact_ov2640_cam_module: + +WeAct Studio MiniSTM32H7xx OV2640 Camera Sensor +############################################### + +Overview +******** + +The OV2640 camera sensor is designed to interface with the WeAct Studio +MiniSTM32H7xx boards, providing camera sensor capabilities. This shield +integrates the OV2640 camera module, which is capable of capturing images +and video with a resolution of up to 2 megapixels. + +.. figure:: ov2640.webp + :align: center + :alt: OV2640 Camera Sensor + +More information about the OV2640 camera sensor can be found on the +`MiniSTM32H7xx GitHub`_ and in the `OV2640 datasheet`_. + +Requirements +************ + +Your board needs to have a ``zephyr_camera_dvp`` device tree label to work with this shield. + +Pin Assignments +=============== + +The shield connects to the WeAct Studio MiniSTM32H7xx board via the +following pins: + ++--------------+-----------+-----------------------------+ +| Shield Pin | Board Pin | Function | ++==============+===========+=============================+ +| DCMI_D0 | PC6 | DCMI Data Line 0 | ++--------------+-----------+-----------------------------+ +| DCMI_D1 | PC7 | DCMI Data Line 1 | ++--------------+-----------+-----------------------------+ +| DCMI_D2 | PE0 | DCMI Data Line 2 | ++--------------+-----------+-----------------------------+ +| DCMI_D3 | PE1 | DCMI Data Line 3 | ++--------------+-----------+-----------------------------+ +| DCMI_D4 | PE4 | DCMI Data Line 4 | ++--------------+-----------+-----------------------------+ +| DCMI_D5 | PD3 | DCMI Data Line 5 | ++--------------+-----------+-----------------------------+ +| DCMI_D6 | PE5 | DCMI Data Line 6 | ++--------------+-----------+-----------------------------+ +| DCMI_D7 | PE6 | DCMI Data Line 7 | ++--------------+-----------+-----------------------------+ +| DCMI_HSYNC | PA4 | DCMI HSYNC | ++--------------+-----------+-----------------------------+ +| DCMI_VSYNC | PB7 | DCMI VSYNC | ++--------------+-----------+-----------------------------+ +| DCMI_PIXCLK | PA6 | DCMI Pixel Clock | ++--------------+-----------+-----------------------------+ +| I2C_SDA | PB9 | I2C Data Line | ++--------------+-----------+-----------------------------+ +| I2C_SCL | PB8 | I2C Clock Line | ++--------------+-----------+-----------------------------+ +| RCC_MCO1 | PA8 | Clock Output | ++--------------+-----------+-----------------------------+ +| SUPPLY | PA7 | Power Supply Control (GPIO) | ++--------------+-----------+-----------------------------+ + +Programming +*********** + +Set ``--shield weact_ov2640_cam_module`` when you invoke ``west build``. For example: + +.. zephyr-app-commands:: + :zephyr-app: samples/drivers/video/capture_to_lvgl/ + :board: mini_stm32h743 + :shield: weact_ov2640_cam_module + :gen-args: -DCONFIG_BOOT_DELAY=2000 + :goals: build + +.. _MiniSTM32H7xx GitHub: + https://github.com/WeActStudio/MiniSTM32H7xx + +.. _OV2640 datasheet: + https://www.uctronics.com/download/cam_module/OV2640DS.pdf diff --git a/boards/shields/weact_ov2640_cam_module/doc/ov2640.webp b/boards/shields/weact_ov2640_cam_module/doc/ov2640.webp new file mode 100644 index 00000000000..8043befcf75 Binary files /dev/null and b/boards/shields/weact_ov2640_cam_module/doc/ov2640.webp differ diff --git a/boards/shields/weact_ov2640_cam_module/weact_ov2640_cam_module.overlay b/boards/shields/weact_ov2640_cam_module/weact_ov2640_cam_module.overlay new file mode 100644 index 00000000000..bc8c6ebddb2 --- /dev/null +++ b/boards/shields/weact_ov2640_cam_module/weact_ov2640_cam_module.overlay @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2024 Charles Dias + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + chosen { + zephyr,camera = &zephyr_camera_dvp; + }; +}; + +&zephyr_camera_i2c { + status = "okay"; + clock-frequency = ; + + ov2640: ov2640@30 { + compatible = "ovti,ov2640"; + reg = <0x30>; + status = "okay"; + + port { + ov2640_ep_out: endpoint { + remote-endpoint = <&zephyr_camera_dvp_in>; + }; + }; + }; +}; + +&zephyr_camera_dvp { + status = "okay"; + sensor = <&ov2640>; + bus-width = <8>; + hsync-active = <0>; + vsync-active = <0>; + pixelclk-active = <1>; + capture-rate = <1>; + + port { + zephyr_camera_dvp_in: endpoint { + remote-endpoint = <&ov2640_ep_out>; + }; + }; +}; diff --git a/boards/shields/x_nucleo_bnrg2a1/Kconfig.defconfig b/boards/shields/x_nucleo_bnrg2a1/Kconfig.defconfig index 94ace9e3849..0c42f5dcb40 100644 --- a/boards/shields/x_nucleo_bnrg2a1/Kconfig.defconfig +++ b/boards/shields/x_nucleo_bnrg2a1/Kconfig.defconfig @@ -5,12 +5,6 @@ if SHIELD_X_NUCLEO_BNRG2A1 if BT -config SPI - default y - -config BT_SPI - default y - config BT_BLUENRG_ACI default y diff --git a/boards/shields/x_nucleo_idb05a1/Kconfig.defconfig b/boards/shields/x_nucleo_idb05a1/Kconfig.defconfig index 276ee664679..4e346ea3e64 100644 --- a/boards/shields/x_nucleo_idb05a1/Kconfig.defconfig +++ b/boards/shields/x_nucleo_idb05a1/Kconfig.defconfig @@ -5,12 +5,6 @@ if SHIELD_X_NUCLEO_IDB05A1 if BT -config SPI - default y - -config BT_SPI - default y - config BT_BLUENRG_ACI default y # Disable Flow control diff --git a/boards/shields/x_nucleo_iks02a1/boards/nucleo_f411re.overlay b/boards/shields/x_nucleo_iks02a1/boards/nucleo_f411re.overlay index 1591debc937..e57bf8cafd9 100644 --- a/boards/shields/x_nucleo_iks02a1/boards/nucleo_f411re.overlay +++ b/boards/shields/x_nucleo_iks02a1/boards/nucleo_f411re.overlay @@ -5,9 +5,12 @@ */ &plli2s { + div-m = <8>; mul-n = <192>; div-r = <3>; - status = "okay"; + div-q = <4>; + clocks = <&clk_hse>; + status = "okay"; /* 48MHz on PLLI2SQ */ }; &dma2 { diff --git a/boards/shields/x_nucleo_iks4a1/x_nucleo_iks4a1.overlay b/boards/shields/x_nucleo_iks4a1/x_nucleo_iks4a1.overlay index 3cda8324777..eaa60be0f4d 100644 --- a/boards/shields/x_nucleo_iks4a1/x_nucleo_iks4a1.overlay +++ b/boards/shields/x_nucleo_iks4a1/x_nucleo_iks4a1.overlay @@ -9,6 +9,7 @@ magn0 = &lis2mdl_1e_x_nucleo_iks4a1; accel0 = &lsm6dso16is_6a_x_nucleo_iks4a1; accel1 = &lsm6dsv16x_6b_x_nucleo_iks4a1; + accel2 = &lis2duxs12_1e_x_nucleo_iks4a1; press0 = &lps22df_5d_x_nucleo_iks4a1; }; }; @@ -45,4 +46,11 @@ drdy-pulsed; drdy-gpios = <&arduino_header 12 GPIO_ACTIVE_HIGH>; /* D6 (PB10) */ }; + + lis2duxs12_1e_x_nucleo_iks4a1: lis2duxs12@19 { + compatible = "st,lis2duxs12"; + reg = <0x19>; + int1-gpios = <&arduino_header 3 GPIO_ACTIVE_HIGH>; /* A3 */ + }; + }; diff --git a/boards/shields/x_nucleo_wb05kn1/Kconfig.defconfig b/boards/shields/x_nucleo_wb05kn1/Kconfig.defconfig index 9ca34477181..dae0d61a9b0 100644 --- a/boards/shields/x_nucleo_wb05kn1/Kconfig.defconfig +++ b/boards/shields/x_nucleo_wb05kn1/Kconfig.defconfig @@ -5,22 +5,10 @@ if SHIELD_X_NUCLEO_WB05KN1_UART || SHIELD_X_NUCLEO_WB05KN1_SPI if BT -config SPI - default y - depends on SHIELD_X_NUCLEO_WB05KN1_SPI - config SPI_STM32_INTERRUPT default y depends on SPI -config BT_SPI - default y - depends on DT_HAS_ST_HCI_SPI_V2_ENABLED - -config BT_H4 - default y - depends on DT_HAS_ZEPHYR_BT_HCI_UART_ENABLED - config BT_BLUENRG_ACI default y diff --git a/boards/sifive/hifive1/doc/index.rst b/boards/sifive/hifive1/doc/index.rst index 2c3d2ba1fb6..dcd9a2948ef 100644 --- a/boards/sifive/hifive1/doc/index.rst +++ b/boards/sifive/hifive1/doc/index.rst @@ -1,7 +1,4 @@ -.. _hifive1: - -SiFive HiFive1 -############## +.. zephyr:board:: hifive1 Overview ******** diff --git a/boards/sifive/hifive1/hifive1.yaml b/boards/sifive/hifive1/hifive1.yaml index 99463674324..bb575f695f3 100644 --- a/boards/sifive/hifive1/hifive1.yaml +++ b/boards/sifive/hifive1/hifive1.yaml @@ -5,8 +5,9 @@ arch: riscv toolchain: - zephyr ram: 16 -simulation: renode -simulation_exec: renode +simulation: + - name: renode + exec: renode supported: - pwm - gpio diff --git a/boards/sifive/hifive1/hifive1_defconfig b/boards/sifive/hifive1/hifive1_defconfig index 21c46be1caf..4a1d5391c78 100644 --- a/boards/sifive/hifive1/hifive1_defconfig +++ b/boards/sifive/hifive1/hifive1_defconfig @@ -5,5 +5,4 @@ CONFIG_CONSOLE=y CONFIG_SERIAL=y CONFIG_UART_SIFIVE_PORT_0=y CONFIG_UART_CONSOLE=y -CONFIG_PINCTRL=y CONFIG_GPIO=y diff --git a/boards/sifive/hifive_unleashed/Kconfig.hifive_unleashed b/boards/sifive/hifive_unleashed/Kconfig.hifive_unleashed index 2fc2f15d50f..da445a39155 100644 --- a/boards/sifive/hifive_unleashed/Kconfig.hifive_unleashed +++ b/boards/sifive/hifive_unleashed/Kconfig.hifive_unleashed @@ -2,4 +2,5 @@ # SPDX-License-Identifier: Apache-2.0 config BOARD_HIFIVE_UNLEASHED - select SOC_SIFIVE_FREEDOM_FU540 + select SOC_SIFIVE_FREEDOM_FU540_E51 if BOARD_HIFIVE_UNLEASHED_FU540_E51 + select SOC_SIFIVE_FREEDOM_FU540_U54 if BOARD_HIFIVE_UNLEASHED_FU540_U54 diff --git a/boards/sifive/hifive_unleashed/doc/index.rst b/boards/sifive/hifive_unleashed/doc/index.rst index f2dd987ff03..e6450ac1f6c 100644 --- a/boards/sifive/hifive_unleashed/doc/index.rst +++ b/boards/sifive/hifive_unleashed/doc/index.rst @@ -1,7 +1,4 @@ -.. _hifive_unleashed: - -SiFive HiFive Unleashed -####################### +.. zephyr:board:: hifive_unleashed Overview ******** @@ -9,10 +6,6 @@ Overview The HiFive Unleashed is a development board with a SiFive FU540-C000 multi-core 64bit RISC-V SoC. -.. image:: img/hifive_unleashed.jpg - :align: center - :alt: SiFive HiFive Unleashed board - Programming and debugging ************************* @@ -22,9 +15,21 @@ Building Applications for the ``hifive_unleashed`` board configuration can be built as usual (see :ref:`build_an_application`) using the corresponding board name: -.. zephyr-app-commands:: - :board: hifive_unleashed - :goals: build +.. tabs:: + + .. group-tab:: E51 + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: hifive_unleashed/fu540/e51 + :goals: build + + .. group-tab:: U54 + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: hifive_unleashed/fu540/u54 + :goals: build Flashing ======== diff --git a/boards/sifive/hifive_unleashed/hifive_unleashed.dts b/boards/sifive/hifive_unleashed/hifive_unleashed.dts deleted file mode 100644 index 321ca13a964..00000000000 --- a/boards/sifive/hifive_unleashed/hifive_unleashed.dts +++ /dev/null @@ -1,72 +0,0 @@ -/* - * Copyright (c) 2021 Katsuhiro Suzuki - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include - -/ { - chosen { - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - zephyr,sram = &ram0; - }; - - ram0: ram0@80000000 { - compatible = "memory"; - reg = <0x80000000 0xf0000000>; - reg-names = "mem"; - }; - - lscon_96b: connector { - compatible = "linaro,96b-lscon-1v8"; - #gpio-cells = <2>; - gpio-map-mask = <0xffffffff 0xffffffc0>; - gpio-map-pass-thru = <0 0x3f>; - gpio-map = <22 0 &gpio0 0 0>, /* GPIO-A */ - <23 0 &gpio0 1 0>, /* GPIO-B */ - <24 0 &gpio0 2 0>, /* GPIO-C */ - <25 0 &gpio0 3 0>, /* GPIO-D */ - <26 0 &gpio0 4 0>, /* GPIO-E */ - <27 0 &gpio0 5 0>, /* GPIO-F */ - <38 0 &gpio0 6 0>, /* GPIO-G */ - <39 0 &gpio0 7 0>, /* GPIO-H */ - <30 0 &gpio0 8 0>, /* GPIO-I */ - <31 0 &gpio0 9 0>, /* GPIO-J */ - <32 0 &gpio0 15 0>; /* GPIO-K */ - /* GPIO-L not connected */ - }; -}; - -&uart0 { - status = "okay"; - current-speed = <115200>; -}; - -/* disabled (used by Flash ROM by default) */ -&spi0 { - reg = <0x10040000 0x1000 0x20000000 0x2000000>; - flash0: flash@0 { - compatible = "issi,is25wp256d", "jedec,spi-nor"; - status = "disabled"; - size = <33554432>; - jedec-id = [96 60 18]; - reg = <0>; - spi-max-frequency = <133000000>; - }; -}; - -&spi1 { - status = "okay"; -}; - -&spi2 { - status = "okay"; -}; - -&gpio0 { - status = "okay"; -}; diff --git a/boards/sifive/hifive_unleashed/hifive_unleashed.dtsi b/boards/sifive/hifive_unleashed/hifive_unleashed.dtsi new file mode 100644 index 00000000000..8465265f388 --- /dev/null +++ b/boards/sifive/hifive_unleashed/hifive_unleashed.dtsi @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2021 Katsuhiro Suzuki + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include + +/ { + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,sram = &l2lim; + }; + + ram0: ram0@80000000 { + compatible = "memory"; + reg = <0x80000000 0xf0000000>; + reg-names = "mem"; + }; + + lscon_96b: connector { + compatible = "linaro,96b-lscon-1v8"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <22 0 &gpio0 0 0>, /* GPIO-A */ + <23 0 &gpio0 1 0>, /* GPIO-B */ + <24 0 &gpio0 2 0>, /* GPIO-C */ + <25 0 &gpio0 3 0>, /* GPIO-D */ + <26 0 &gpio0 4 0>, /* GPIO-E */ + <27 0 &gpio0 5 0>, /* GPIO-F */ + <38 0 &gpio0 6 0>, /* GPIO-G */ + <39 0 &gpio0 7 0>, /* GPIO-H */ + <30 0 &gpio0 8 0>, /* GPIO-I */ + <31 0 &gpio0 9 0>, /* GPIO-J */ + <32 0 &gpio0 15 0>; /* GPIO-K */ + /* GPIO-L not connected */ + }; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; +}; + +/* disabled (used by Flash ROM by default) */ +&spi0 { + reg = <0x10040000 0x1000 0x20000000 0x2000000>; + flash0: flash@0 { + compatible = "issi,is25wp256d", "jedec,spi-nor"; + status = "disabled"; + size = <33554432>; + jedec-id = [96 60 18]; + reg = <0>; + spi-max-frequency = <133000000>; + }; +}; + +&spi1 { + status = "okay"; +}; + +&spi2 { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; diff --git a/boards/sifive/hifive_unleashed/hifive_unleashed.yaml b/boards/sifive/hifive_unleashed/hifive_unleashed.yaml deleted file mode 100644 index 1fb91e4c2e0..00000000000 --- a/boards/sifive/hifive_unleashed/hifive_unleashed.yaml +++ /dev/null @@ -1,23 +0,0 @@ -identifier: hifive_unleashed -name: SiFive HiFive Unleashed -type: mcu -arch: riscv -toolchain: - - zephyr -ram: 3840 -simulation: renode -simulation_exec: renode -testing: - ignore_tags: - - net - - bluetooth - - flash - - newlib - - crypto - renode: - uart: sysbus.uart0 - resc: boards/sifive/hifive_unleashed/support/hifive_unleashed.resc -supported: - - gpio - - spi -vendor: sifive diff --git a/boards/sifive/hifive_unleashed/hifive_unleashed_e51.dts b/boards/sifive/hifive_unleashed/hifive_unleashed_e51.dts new file mode 100644 index 00000000000..567fb97e9ea --- /dev/null +++ b/boards/sifive/hifive_unleashed/hifive_unleashed_e51.dts @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2024 Antmicro + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include "hifive_unleashed.dtsi" + +/ { + + cpus { + cpu@1 { + status = "disabled"; + }; + + cpu@2 { + status = "disabled"; + }; + + cpu@3 { + status = "disabled"; + }; + + cpu@4 { + status = "disabled"; + }; + }; + +}; diff --git a/boards/sifive/hifive_unleashed/hifive_unleashed_e51.yaml b/boards/sifive/hifive_unleashed/hifive_unleashed_e51.yaml new file mode 100644 index 00000000000..28683410d52 --- /dev/null +++ b/boards/sifive/hifive_unleashed/hifive_unleashed_e51.yaml @@ -0,0 +1,24 @@ +identifier: hifive_unleashed/fu540/e51 +name: SiFive HiFive Unleashed (E51) +type: mcu +arch: riscv +toolchain: + - zephyr +ram: 3840 +simulation: + - name: renode + exec: renode +testing: + timeout_multiplier: 6 + ignore_tags: + - net + - bluetooth + - flash + - crypto + renode: + uart: sysbus.uart0 + resc: boards/sifive/hifive_unleashed/support/hifive_unleashed.resc +supported: + - gpio + - spi +vendor: sifive diff --git a/boards/sifive/hifive_unleashed/hifive_unleashed_defconfig b/boards/sifive/hifive_unleashed/hifive_unleashed_e51_defconfig similarity index 100% rename from boards/sifive/hifive_unleashed/hifive_unleashed_defconfig rename to boards/sifive/hifive_unleashed/hifive_unleashed_e51_defconfig diff --git a/boards/sifive/hifive_unleashed/hifive_unleashed_u54.dts b/boards/sifive/hifive_unleashed/hifive_unleashed_u54.dts new file mode 100644 index 00000000000..53af3e2e92e --- /dev/null +++ b/boards/sifive/hifive_unleashed/hifive_unleashed_u54.dts @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2024 Antmicro + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include "hifive_unleashed.dtsi" + +/ { + cpus { + cpu@0 { + status = "disabled"; + }; + }; +}; diff --git a/boards/sifive/hifive_unleashed/hifive_unleashed_u54.yaml b/boards/sifive/hifive_unleashed/hifive_unleashed_u54.yaml new file mode 100644 index 00000000000..b0be2aedfc3 --- /dev/null +++ b/boards/sifive/hifive_unleashed/hifive_unleashed_u54.yaml @@ -0,0 +1,24 @@ +identifier: hifive_unleashed/fu540/u54 +name: SiFive HiFive Unleashed (U54) +type: mcu +arch: riscv +toolchain: + - zephyr +ram: 3840 +simulation: + - name: renode + exec: renode +testing: + timeout_multiplier: 6 + ignore_tags: + - net + - bluetooth + - flash + - crypto + renode: + uart: sysbus.uart0 + resc: boards/sifive/hifive_unleashed/support/hifive_unleashed.resc +supported: + - gpio + - spi +vendor: sifive diff --git a/boards/sifive/hifive_unleashed/hifive_unleashed_u54_defconfig b/boards/sifive/hifive_unleashed/hifive_unleashed_u54_defconfig new file mode 100644 index 00000000000..21f7ae226ae --- /dev/null +++ b/boards/sifive/hifive_unleashed/hifive_unleashed_u54_defconfig @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_CONSOLE=y +CONFIG_GPIO=y +CONFIG_SERIAL=y +CONFIG_UART_SIFIVE_PORT_0=y +CONFIG_UART_CONSOLE=y +CONFIG_XIP=n +CONFIG_RV_BOOT_HART=1 +CONFIG_FLOAT_HARD=y diff --git a/boards/sifive/hifive_unleashed/support/hifive_unleashed.resc b/boards/sifive/hifive_unleashed/support/hifive_unleashed.resc index 4d06081c5c9..fbb0ddeb9a2 100644 --- a/boards/sifive/hifive_unleashed/support/hifive_unleashed.resc +++ b/boards/sifive/hifive_unleashed/support/hifive_unleashed.resc @@ -10,6 +10,9 @@ set platform """ using "platforms/cpus/sifive-fu540.repl" +l2lim: Memory.MappedMemory @ sysbus 0x08000000 + size: 0x2000000 + clint: frequency: 10000000 """ diff --git a/boards/sifive/hifive_unleashed/support/openocd_hifive_unleashed.cfg b/boards/sifive/hifive_unleashed/support/openocd_hifive_unleashed.cfg index 1620f6cbd39..f8092286163 100644 --- a/boards/sifive/hifive_unleashed/support/openocd_hifive_unleashed.cfg +++ b/boards/sifive/hifive_unleashed/support/openocd_hifive_unleashed.cfg @@ -18,5 +18,9 @@ target create $_TARGETNAME.3 riscv -chain-position $_TARGETNAME -coreid 3 target create $_TARGETNAME.4 riscv -chain-position $_TARGETNAME -coreid 4 target smp $_TARGETNAME.0 $_TARGETNAME.1 $_TARGETNAME.2 $_TARGETNAME.3 $_TARGETNAME.4 $_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 0x4000 -work-area-backup 1 +$_TARGETNAME.1 configure -work-area-phys 0x80000000 -work-area-size 0x4000 -work-area-backup 1 +$_TARGETNAME.2 configure -work-area-phys 0x80000000 -work-area-size 0x4000 -work-area-backup 1 +$_TARGETNAME.3 configure -work-area-phys 0x80000000 -work-area-size 0x4000 -work-area-backup 1 +$_TARGETNAME.4 configure -work-area-phys 0x80000000 -work-area-size 0x4000 -work-area-backup 1 flash bank onboard_spi_flash0 fespi 0x20000000 0 0 0 $_TARGETNAME.0 0x10040000 diff --git a/boards/sifive/hifive_unmatched/Kconfig.hifive_unmatched b/boards/sifive/hifive_unmatched/Kconfig.hifive_unmatched index 87911f3ccb3..77ea79eb29d 100644 --- a/boards/sifive/hifive_unmatched/Kconfig.hifive_unmatched +++ b/boards/sifive/hifive_unmatched/Kconfig.hifive_unmatched @@ -2,4 +2,5 @@ # SPDX-License-Identifier: Apache-2.0 config BOARD_HIFIVE_UNMATCHED - select SOC_SIFIVE_FREEDOM_FU740 + select SOC_SIFIVE_FREEDOM_FU740_S7 if BOARD_HIFIVE_UNMATCHED_FU740_S7 + select SOC_SIFIVE_FREEDOM_FU740_U74 if BOARD_HIFIVE_UNMATCHED_FU740_U74 diff --git a/boards/sifive/hifive_unmatched/doc/index.rst b/boards/sifive/hifive_unmatched/doc/index.rst index da374e37679..bc2447104b2 100644 --- a/boards/sifive/hifive_unmatched/doc/index.rst +++ b/boards/sifive/hifive_unmatched/doc/index.rst @@ -1,7 +1,4 @@ -.. _hifive_unmatched: - -SiFive HiFive Unmatched -####################### +.. zephyr:board:: hifive_unmatched Overview ******** @@ -9,10 +6,6 @@ Overview The HiFive Unmatched is a development board with a SiFive FU740-C000 multi-core 64bit RISC-V SoC. -.. image:: img/hifive_unmatched.jpg - :align: center - :alt: SiFive HiFive Unmatched board - Programming and debugging ************************* @@ -22,9 +15,21 @@ Building Applications for the ``hifive_unmatched`` board configuration can be built as usual (see :ref:`build_an_application`) using the corresponding board name: -.. zephyr-app-commands:: - :board: hifive_unmatched - :goals: build +.. tabs:: + + .. group-tab:: S7 + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: hifive_unmatched/fu740/s7 + :goals: build + + .. group-tab:: U74 + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: hifive_unmatched/fu740/u74 + :goals: build Flashing ======== diff --git a/boards/sifive/hifive_unmatched/hifive_unmatched.dts b/boards/sifive/hifive_unmatched/hifive_unmatched.dtsi similarity index 100% rename from boards/sifive/hifive_unmatched/hifive_unmatched.dts rename to boards/sifive/hifive_unmatched/hifive_unmatched.dtsi diff --git a/boards/sifive/hifive_unmatched/hifive_unmatched.yaml b/boards/sifive/hifive_unmatched/hifive_unmatched.yaml deleted file mode 100644 index 6fbfb696ce1..00000000000 --- a/boards/sifive/hifive_unmatched/hifive_unmatched.yaml +++ /dev/null @@ -1,20 +0,0 @@ -identifier: hifive_unmatched -name: SiFive HiFive Unmatched -type: mcu -arch: riscv -toolchain: - - zephyr -ram: 3840 -simulation: renode -simulation_exec: renode -testing: - ignore_tags: - - net - - bluetooth - renode: - uart: sysbus.uart0 - resc: boards/sifive/hifive_unmatched/support/hifive_unmatched.resc -supported: - - spi - - memc -vendor: sifive diff --git a/boards/sifive/hifive_unmatched/hifive_unmatched_s7.dts b/boards/sifive/hifive_unmatched/hifive_unmatched_s7.dts new file mode 100644 index 00000000000..a850910b368 --- /dev/null +++ b/boards/sifive/hifive_unmatched/hifive_unmatched_s7.dts @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2024 Antmicro + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include "hifive_unmatched.dtsi" + +/ { + cpus { + cpu@1 { + status = "disabled"; + }; + + cpu@2 { + status = "disabled"; + }; + + cpu@3 { + status = "disabled"; + }; + + cpu@4 { + status = "disabled"; + }; + }; +}; diff --git a/boards/sifive/hifive_unmatched/hifive_unmatched_s7.yaml b/boards/sifive/hifive_unmatched/hifive_unmatched_s7.yaml new file mode 100644 index 00000000000..18914290609 --- /dev/null +++ b/boards/sifive/hifive_unmatched/hifive_unmatched_s7.yaml @@ -0,0 +1,22 @@ +identifier: hifive_unmatched/fu740/s7 +name: SiFive HiFive Unmatched (S7) +type: mcu +arch: riscv +toolchain: + - zephyr +ram: 3840 +simulation: + - name: renode + exec: renode +testing: + timeout_multiplier: 6 + ignore_tags: + - net + - bluetooth + renode: + uart: sysbus.uart0 + resc: boards/sifive/hifive_unmatched/support/hifive_unmatched.resc +supported: + - spi + - memc +vendor: sifive diff --git a/boards/sifive/hifive_unmatched/hifive_unmatched_defconfig b/boards/sifive/hifive_unmatched/hifive_unmatched_s7_defconfig similarity index 100% rename from boards/sifive/hifive_unmatched/hifive_unmatched_defconfig rename to boards/sifive/hifive_unmatched/hifive_unmatched_s7_defconfig diff --git a/boards/sifive/hifive_unmatched/hifive_unmatched_u74.dts b/boards/sifive/hifive_unmatched/hifive_unmatched_u74.dts new file mode 100644 index 00000000000..e8adf2bd127 --- /dev/null +++ b/boards/sifive/hifive_unmatched/hifive_unmatched_u74.dts @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2024 Antmicro + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include "hifive_unmatched.dtsi" + +/ { + cpus { + cpu@0 { + status = "disabled"; + }; + }; +}; diff --git a/boards/sifive/hifive_unmatched/hifive_unmatched_u74.yaml b/boards/sifive/hifive_unmatched/hifive_unmatched_u74.yaml new file mode 100644 index 00000000000..9a7a5582b7e --- /dev/null +++ b/boards/sifive/hifive_unmatched/hifive_unmatched_u74.yaml @@ -0,0 +1,22 @@ +identifier: hifive_unmatched/fu740/u74 +name: SiFive HiFive Unmatched (U74) +type: mcu +arch: riscv +toolchain: + - zephyr +ram: 3840 +simulation: + - name: renode + exec: renode +testing: + timeout_multiplier: 6 + ignore_tags: + - net + - bluetooth + renode: + uart: sysbus.uart0 + resc: boards/sifive/hifive_unmatched/support/hifive_unmatched.resc +supported: + - spi + - memc +vendor: sifive diff --git a/boards/sifive/hifive_unmatched/hifive_unmatched_u74_defconfig b/boards/sifive/hifive_unmatched/hifive_unmatched_u74_defconfig new file mode 100644 index 00000000000..b63433284cb --- /dev/null +++ b/boards/sifive/hifive_unmatched/hifive_unmatched_u74_defconfig @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_SIFIVE_PORT_0=y +CONFIG_UART_CONSOLE=y +CONFIG_XIP=n +CONFIG_RV_BOOT_HART=1 +CONFIG_FLOAT_HARD=y diff --git a/boards/sifive/hifive_unmatched/support/openocd_hifive_unmatched.cfg b/boards/sifive/hifive_unmatched/support/openocd_hifive_unmatched.cfg index 1620f6cbd39..f8092286163 100644 --- a/boards/sifive/hifive_unmatched/support/openocd_hifive_unmatched.cfg +++ b/boards/sifive/hifive_unmatched/support/openocd_hifive_unmatched.cfg @@ -18,5 +18,9 @@ target create $_TARGETNAME.3 riscv -chain-position $_TARGETNAME -coreid 3 target create $_TARGETNAME.4 riscv -chain-position $_TARGETNAME -coreid 4 target smp $_TARGETNAME.0 $_TARGETNAME.1 $_TARGETNAME.2 $_TARGETNAME.3 $_TARGETNAME.4 $_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 0x4000 -work-area-backup 1 +$_TARGETNAME.1 configure -work-area-phys 0x80000000 -work-area-size 0x4000 -work-area-backup 1 +$_TARGETNAME.2 configure -work-area-phys 0x80000000 -work-area-size 0x4000 -work-area-backup 1 +$_TARGETNAME.3 configure -work-area-phys 0x80000000 -work-area-size 0x4000 -work-area-backup 1 +$_TARGETNAME.4 configure -work-area-phys 0x80000000 -work-area-size 0x4000 -work-area-backup 1 flash bank onboard_spi_flash0 fespi 0x20000000 0 0 0 $_TARGETNAME.0 0x10040000 diff --git a/boards/silabs/dev_kits/sim3u1xx_dk/doc/index.rst b/boards/silabs/dev_kits/sim3u1xx_dk/doc/index.rst index 67284c4b782..da8bb3cac5e 100644 --- a/boards/silabs/dev_kits/sim3u1xx_dk/doc/index.rst +++ b/boards/silabs/dev_kits/sim3u1xx_dk/doc/index.rst @@ -1,16 +1,10 @@ -.. _sim3u1xx_dk: - -Silicon Labs SiM3U1xx 32-bit MCU USB Development Kit -#################################################### +.. zephyr:board:: sim3u1xx_dk Overview ******** This is a `development kit`_ that is used to develop software for the SiM3U1xx MCUs. -.. figure:: sim3u1xx_dk.webp - :align: center - Hardware ******** @@ -55,6 +49,8 @@ The board configuration supports the following hardware features: +-----------+------------+-------------------------------------+ | SYSTICK | on-chip | systick | +-----------+------------+-------------------------------------+ +| AES | on-chip | crypto | ++-----------+------------+-------------------------------------+ | DMA | on-chip | dma | +-----------+------------+-------------------------------------+ | FLASH | on-chip | flash memory | diff --git a/boards/silabs/dev_kits/sim3u1xx_dk/sim3u1xx_dk.dts b/boards/silabs/dev_kits/sim3u1xx_dk/sim3u1xx_dk.dts index f55f5a667f9..4915747d934 100644 --- a/boards/silabs/dev_kits/sim3u1xx_dk/sim3u1xx_dk.dts +++ b/boards/silabs/dev_kits/sim3u1xx_dk/sim3u1xx_dk.dts @@ -24,6 +24,7 @@ zephyr,console = &usart0; zephyr,flash = &flash0; zephyr,shell-uart = &usart0; + zephyr,uart-pipe = &usart0; zephyr,sram = &sram0; }; @@ -109,3 +110,12 @@ }; }; }; + +&dma { + status = "okay"; + dma-channels = <8>; /* Crypto DMA channels have ID 5, 6, and 7 */ +}; + +&crypto { + status = "okay"; +}; diff --git a/boards/silabs/dev_kits/sim3u1xx_dk/sim3u1xx_dk.yaml b/boards/silabs/dev_kits/sim3u1xx_dk/sim3u1xx_dk.yaml index 3555255ae42..13a20e8a736 100644 --- a/boards/silabs/dev_kits/sim3u1xx_dk/sim3u1xx_dk.yaml +++ b/boards/silabs/dev_kits/sim3u1xx_dk/sim3u1xx_dk.yaml @@ -13,6 +13,7 @@ toolchain: - xtools - zephyr supported: + - crypto - dma - flash - gpio diff --git a/boards/silabs/dev_kits/sltb004a/Kconfig.defconfig b/boards/silabs/dev_kits/sltb004a/Kconfig.defconfig index 3a9256b44e1..77ed8bb3fa0 100644 --- a/boards/silabs/dev_kits/sltb004a/Kconfig.defconfig +++ b/boards/silabs/dev_kits/sltb004a/Kconfig.defconfig @@ -1,5 +1,3 @@ -# EFR32MG SLTB004A board - # Copyright (c) 2018, Diego Sueiro # SPDX-License-Identifier: Apache-2.0 diff --git a/boards/silabs/dev_kits/sltb004a/Kconfig.sltb004a b/boards/silabs/dev_kits/sltb004a/Kconfig.sltb004a index 58f4485dd4e..8cd573f4128 100644 --- a/boards/silabs/dev_kits/sltb004a/Kconfig.sltb004a +++ b/boards/silabs/dev_kits/sltb004a/Kconfig.sltb004a @@ -1,5 +1,3 @@ -# EFR32MG SLTB004A board - # Copyright (c) 2018, Diego Sueiro # SPDX-License-Identifier: Apache-2.0 diff --git a/boards/silabs/dev_kits/sltb004a/board.cmake b/boards/silabs/dev_kits/sltb004a/board.cmake index 94e24e1ee31..435c2dd75d6 100644 --- a/boards/silabs/dev_kits/sltb004a/board.cmake +++ b/boards/silabs/dev_kits/sltb004a/board.cmake @@ -1,6 +1,5 @@ # Copyright (c) 2018, Evry ASA -# # SPDX-License-Identifier: Apache-2.0 -# + board_runner_args(jlink "--device=EFR32MG12PxxxF1024") include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/silabs/dev_kits/sltb004a/doc/index.rst b/boards/silabs/dev_kits/sltb004a/doc/index.rst index e11145365fb..14795756afc 100644 --- a/boards/silabs/dev_kits/sltb004a/doc/index.rst +++ b/boards/silabs/dev_kits/sltb004a/doc/index.rst @@ -1,7 +1,4 @@ -.. _sltb004a: - -EFR32MG12 Thunderboard (SLTB004A) -################################# +.. zephyr:board:: sltb004a Overview ******** @@ -10,10 +7,6 @@ The EFR32MG12 Thunderboard (a.k.a Thunderboard Sense 2) contains an MCU from the EFR32MG12 family built on ARM® Cortex®-M4F processor with low power capabilities. -.. image:: sltb004a.jpg - :align: center - :alt: EFR32MG12 SLTB004A - Hardware ******** @@ -149,7 +142,7 @@ Programming and Debugging .. note:: Before using the kit the first time, you should update the J-Link firmware - from `J-Link-Downloads`_ + in Simplicity Studio. Flashing ======== @@ -206,6 +199,3 @@ the following message: .. _J-Link: https://www.segger.com/jlink-debug-probes.html - -.. _J-Link-Downloads: - https://www.segger.com/downloads/jlink diff --git a/boards/silabs/dev_kits/sltb004a/sltb004a.dts b/boards/silabs/dev_kits/sltb004a/sltb004a.dts index 033984be007..5252b0b6a48 100644 --- a/boards/silabs/dev_kits/sltb004a/sltb004a.dts +++ b/boards/silabs/dev_kits/sltb004a/sltb004a.dts @@ -27,6 +27,7 @@ chosen { zephyr,console = &usart0; zephyr,shell-uart = &usart0; + zephyr,uart-pipe = &usart0; zephyr,sram = &sram0; zephyr,flash = &flash0; }; diff --git a/boards/silabs/dev_kits/sltb004a/sltb004a.yaml b/boards/silabs/dev_kits/sltb004a/sltb004a.yaml index a610e85fdee..c1e842247f6 100644 --- a/boards/silabs/dev_kits/sltb004a/sltb004a.yaml +++ b/boards/silabs/dev_kits/sltb004a/sltb004a.yaml @@ -1,5 +1,5 @@ identifier: sltb004a -name: Thunderboard Sense 2 (SLTB004A, BRD4166A) +name: Thunderboard Sense 2 (SLTB004A, BRD4166A, EFR32MG12) type: mcu arch: arm ram: 256 diff --git a/boards/silabs/dev_kits/sltb009a/Kconfig.defconfig b/boards/silabs/dev_kits/sltb009a/Kconfig.defconfig index 6c21d423607..ef52b5824af 100644 --- a/boards/silabs/dev_kits/sltb009a/Kconfig.defconfig +++ b/boards/silabs/dev_kits/sltb009a/Kconfig.defconfig @@ -1,4 +1,3 @@ -# EFM32GG SLTB009A default board configuration # Copyright (c) 2023 Antmicro # SPDX-License-Identifier: Apache-2.0 diff --git a/boards/silabs/dev_kits/sltb009a/Kconfig.sltb009a b/boards/silabs/dev_kits/sltb009a/Kconfig.sltb009a index d486de84769..42ff41d0471 100644 --- a/boards/silabs/dev_kits/sltb009a/Kconfig.sltb009a +++ b/boards/silabs/dev_kits/sltb009a/Kconfig.sltb009a @@ -1,4 +1,3 @@ -# EFM32GG SLTB009A board configuration # Copyright (c) 2023 Antmicro # SPDX-License-Identifier: Apache-2.0 diff --git a/boards/silabs/dev_kits/sltb009a/doc/index.rst b/boards/silabs/dev_kits/sltb009a/doc/index.rst index 9366a7d2649..8be84aefc60 100644 --- a/boards/silabs/dev_kits/sltb009a/doc/index.rst +++ b/boards/silabs/dev_kits/sltb009a/doc/index.rst @@ -1,7 +1,4 @@ -.. _efm32gg_sltb009a: - -EFM32GG12 Thunderboard (SLTB009A) -################################# +.. zephyr:board:: sltb009a Overview ******** @@ -10,12 +7,6 @@ The EFM32GG12 Thunderboard Kit (SLTB009A) is an evaluation platform for the EFM32GG12 Giant Gecko Microcontroller, featuring an ARM Cortex-M4 with FPU, 1024kB flash, and 192kB RAM. -.. figure:: sltb009a.jpg - :align: center - :alt: SLTB009A - - SLTB009A (Credit: Silicon Labs) - Hardware ******** @@ -110,7 +101,7 @@ Programming and Debugging .. note:: Before using the kit the first time, you should update the J-Link firmware - from `J-Link-Downloads`_ + in Simplicity Studio. Flashing ======== @@ -161,6 +152,3 @@ terminal session: .. _J-Link: https://www.segger.com/jlink-debug-probes.html - -.. _J-Link-Downloads: - https://www.segger.com/downloads/jlink diff --git a/boards/silabs/dev_kits/sltb009a/sltb009a.dts b/boards/silabs/dev_kits/sltb009a/sltb009a.dts index 1c36fb59f21..901cc93bca9 100644 --- a/boards/silabs/dev_kits/sltb009a/sltb009a.dts +++ b/boards/silabs/dev_kits/sltb009a/sltb009a.dts @@ -16,6 +16,7 @@ chosen { zephyr,console = &usart0; zephyr,shell-uart = &usart0; + zephyr,uart-pipe = &usart0; zephyr,sram = &sram0; zephyr,flash = &flash0; }; diff --git a/boards/silabs/dev_kits/sltb010a/Kconfig.defconfig b/boards/silabs/dev_kits/sltb010a/Kconfig.defconfig index 9b45efccc90..fac4f17b12e 100644 --- a/boards/silabs/dev_kits/sltb010a/Kconfig.defconfig +++ b/boards/silabs/dev_kits/sltb010a/Kconfig.defconfig @@ -1,14 +1,6 @@ -# Thunderboard-style boards - # Copyright (c) 2023 Antmicro # SPDX-License-Identifier: Apache-2.0 -config CMU_HFXO_FREQ - default 38400000 - -config CMU_LFXO_FREQ - default 32768 - if SOC_GECKO_USE_RAIL config FPU diff --git a/boards/silabs/dev_kits/sltb010a/Kconfig.sltb010a b/boards/silabs/dev_kits/sltb010a/Kconfig.sltb010a index 43710c25408..21d7b680858 100644 --- a/boards/silabs/dev_kits/sltb010a/Kconfig.sltb010a +++ b/boards/silabs/dev_kits/sltb010a/Kconfig.sltb010a @@ -1,5 +1,3 @@ -# EFR32BG SLTB010A board - # Copyright (c) 2021, Sateesh Kotapati # SPDX-License-Identifier: Apache-2.0 diff --git a/boards/silabs/dev_kits/sltb010a/board.c b/boards/silabs/dev_kits/sltb010a/board.c index 7572f0fad39..ac43052e362 100644 --- a/boards/silabs/dev_kits/sltb010a/board.c +++ b/boards/silabs/dev_kits/sltb010a/board.c @@ -8,22 +8,12 @@ #include #include -#ifdef CONFIG_SOC_GECKO_DEV_INIT -#include "em_cmu.h" -#endif - - LOG_MODULE_REGISTER(thunderboard, CONFIG_BOARD_SLTB010A_LOG_LEVEL); -static int thunderboard_init_clocks(void); - static int thunderboard_init(void) { int ret; -#ifdef CONFIG_SOC_GECKO_DEV_INIT - thunderboard_init_clocks(); -#endif static struct gpio_dt_spec wake_up_gpio_dev = GPIO_DT_SPEC_GET(DT_NODELABEL(wake_up_trigger), gpios); @@ -40,25 +30,5 @@ static int thunderboard_init(void) return 0; } -#ifdef CONFIG_SOC_GECKO_DEV_INIT -static int thunderboard_init_clocks(void) -{ - CMU_ClockSelectSet(cmuClock_SYSCLK, cmuSelect_HFRCODPLL); -#if defined(_CMU_EM01GRPACLKCTRL_MASK) - CMU_ClockSelectSet(cmuClock_EM01GRPACLK, cmuSelect_HFRCODPLL); -#endif -#if defined(_CMU_EM01GRPBCLKCTRL_MASK) - CMU_ClockSelectSet(cmuClock_EM01GRPBCLK, cmuSelect_HFRCODPLL); -#endif - CMU_ClockSelectSet(cmuClock_EM23GRPACLK, cmuSelect_LFRCO); -#if defined(RTCC_PRESENT) - CMU_ClockSelectSet(cmuClock_RTCC, cmuSelect_LFRCO); -#endif - CMU_ClockSelectSet(cmuClock_WDOG0, cmuSelect_LFRCO); - - return 0; -} -#endif - /* needs to be done after GPIO driver init */ SYS_INIT(thunderboard_init, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE); diff --git a/boards/silabs/dev_kits/sltb010a/doc/index.rst b/boards/silabs/dev_kits/sltb010a/doc/index.rst index a335924359f..eb7dcfb24a0 100644 --- a/boards/silabs/dev_kits/sltb010a/doc/index.rst +++ b/boards/silabs/dev_kits/sltb010a/doc/index.rst @@ -1,16 +1,9 @@ -.. _sltb010a: - -EFR32BG22 Thunderboard (SLTB010A) -################################# +.. zephyr:board:: sltb010a SLTB010A is a development kit based on the EFR32BG22 SoC. Early revisions of the kit (A00 and A01) use a slightly different PCB (BRD4184A) from later revisions (BRD4184B). -.. image:: ./sltb010a.jpg - :align: center - :alt: SLTB010A board - Hardware ******** @@ -70,6 +63,8 @@ The sltb010a board configuration supports the following hardware features: +-----------+------------+-------------------------------------+ | UART | on-chip | serial | +-----------+------------+-------------------------------------+ +| DMA | on-chip | ldma | ++-----------+------------+-------------------------------------+ | WATCHDOG | on-chip | watchdog | +-----------+------------+-------------------------------------+ | TRNG | on-chip | true random number generator | diff --git a/boards/silabs/dev_kits/sltb010a/sltb010a-pinctrl.dtsi b/boards/silabs/dev_kits/sltb010a/sltb010a-pinctrl.dtsi new file mode 100644 index 00000000000..435ca5a0cf4 --- /dev/null +++ b/boards/silabs/dev_kits/sltb010a/sltb010a-pinctrl.dtsi @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2024 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + usart0_default: usart0_default { + group0 { + pins = , ; + drive-push-pull; + output-high; + }; + group1 { + pins = ; + input-enable; + }; + }; + + usart1_default: usart1_default { + group0 { + pins = ; + drive-push-pull; + output-high; + }; + group1 { + pins = ; + input-enable; + silabs,input-filter; + }; + }; + + i2c0_default: i2c0_default { + group0 { + pins = , ; + drive-open-drain; + bias-pull-up; + }; + }; +}; diff --git a/boards/silabs/dev_kits/sltb010a/sltb010a.dts b/boards/silabs/dev_kits/sltb010a/sltb010a.dts index 3f352ea6008..994a75007ee 100644 --- a/boards/silabs/dev_kits/sltb010a/sltb010a.dts +++ b/boards/silabs/dev_kits/sltb010a/sltb010a.dts @@ -6,8 +6,9 @@ /dts-v1/; #include -#include +#include "sltb010a-pinctrl.dtsi" #include "thunderboard.dtsi" +#include / { /* These aliases are provided for compatibility with samples */ @@ -27,6 +28,50 @@ }; }; +&hfxo { + status = "okay"; + ctune = <120>; + precision = <50>; +}; + +&lfxo { + status = "okay"; + ctune = <37>; + precision = <50>; +}; + +&hfrcodpll { + clock-frequency = ; + clocks = <&hfxo>; + dpll-n = <3839>; + dpll-m = <1919>; + dpll-edge = "fall"; + dpll-lock = "phase"; + dpll-autorecover; +}; + +&em23grpaclk { + clocks = <&lfxo>; +}; + +&em4grpaclk { + clocks = <&lfxo>; +}; + +&rtccclk { + clocks = <&lfxo>; +}; + +&wdog0clk { + clocks = <&lfxo>; +}; + +&dcdc { + status = "okay"; + regulator-boot-on; + regulator-initial-mode = ; +}; + &flash0 { partitions { /* Reserve 48 KiB for the bootloader */ @@ -57,7 +102,7 @@ }; &sw_imu_enable { - enable-gpios = <&gpiob GECKO_PIN(4) GPIO_ACTIVE_HIGH>; + enable-gpios = <&gpiob 4 GPIO_ACTIVE_HIGH>; }; &bt_hci_silabs { diff --git a/boards/silabs/dev_kits/sltb010a/sltb010a_0.overlay b/boards/silabs/dev_kits/sltb010a/sltb010a_0.overlay index c108c8e67db..3b3654f9c60 100644 --- a/boards/silabs/dev_kits/sltb010a/sltb010a_0.overlay +++ b/boards/silabs/dev_kits/sltb010a/sltb010a_0.overlay @@ -11,9 +11,9 @@ }; &sw_sensor_enable { - enable-gpios = <&gpioa GECKO_PIN(4) GPIO_ACTIVE_HIGH>; + enable-gpios = <&gpioa 4 GPIO_ACTIVE_HIGH>; }; &sw_mic_enable { - enable-gpios = <&gpioa GECKO_PIN(0) GPIO_ACTIVE_HIGH>; + enable-gpios = <&gpioa 0 GPIO_ACTIVE_HIGH>; }; diff --git a/boards/silabs/dev_kits/sltb010a/sltb010a_0.yaml b/boards/silabs/dev_kits/sltb010a/sltb010a_0.yaml index 8cbf1832eac..90a2ebc846a 100644 --- a/boards/silabs/dev_kits/sltb010a/sltb010a_0.yaml +++ b/boards/silabs/dev_kits/sltb010a/sltb010a_0.yaml @@ -14,5 +14,7 @@ supported: - gpio - uart - i2c + - dma - spi + - clock_control vendor: silabs diff --git a/boards/silabs/dev_kits/sltb010a/sltb010a_2.overlay b/boards/silabs/dev_kits/sltb010a/sltb010a_2.overlay index 224722da280..8365fd71ee0 100644 --- a/boards/silabs/dev_kits/sltb010a/sltb010a_2.overlay +++ b/boards/silabs/dev_kits/sltb010a/sltb010a_2.overlay @@ -12,17 +12,17 @@ }; &button0 { - gpios = <&gpiob GECKO_PIN(3) GPIO_ACTIVE_LOW>; + gpios = <&gpiob 3 GPIO_ACTIVE_LOW>; }; &led0 { - gpios = <&gpioa GECKO_PIN(4) GPIO_ACTIVE_HIGH>; + gpios = <&gpioa 4 GPIO_ACTIVE_HIGH>; }; &sw_sensor_enable { - enable-gpios = <&gpioc GECKO_PIN(6) GPIO_ACTIVE_HIGH>; + enable-gpios = <&gpioc 6 GPIO_ACTIVE_HIGH>; }; &sw_mic_enable { - enable-gpios = <&gpioc GECKO_PIN(7) GPIO_ACTIVE_HIGH>; + enable-gpios = <&gpioc 7 GPIO_ACTIVE_HIGH>; }; diff --git a/boards/silabs/dev_kits/sltb010a/sltb010a_2.yaml b/boards/silabs/dev_kits/sltb010a/sltb010a_2.yaml index 2024a279aeb..b0642de163e 100644 --- a/boards/silabs/dev_kits/sltb010a/sltb010a_2.yaml +++ b/boards/silabs/dev_kits/sltb010a/sltb010a_2.yaml @@ -14,5 +14,6 @@ supported: - gpio - uart - i2c + - dma - spi vendor: silabs diff --git a/boards/silabs/dev_kits/sltb010a/sltb010a_defconfig b/boards/silabs/dev_kits/sltb010a/sltb010a_defconfig index 50a14221ec9..b7da445368c 100644 --- a/boards/silabs/dev_kits/sltb010a/sltb010a_defconfig +++ b/boards/silabs/dev_kits/sltb010a/sltb010a_defconfig @@ -8,13 +8,3 @@ CONFIG_GPIO=y CONFIG_SOC_GECKO_EMU_DCDC=y CONFIG_SOC_GECKO_EMU_DCDC_MODE_ON=y CONFIG_HW_STACK_PROTECTION=y -CONFIG_PINCTRL=y - -# Used if SysTick is enabled, ignored for BURTC -# (BURTC uses TIMER_READS_ITS_FREQUENCY_AT_RUNTIME) -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=76800000 - -# Use BURTC as system clock source -CONFIG_GECKO_BURTC_TIMER=y -CONFIG_CMU_BURTCCLK_LFXO=y -CONFIG_SYS_CLOCK_TICKS_PER_SEC=1024 diff --git a/boards/silabs/dev_kits/sltb010a/thunderboard.dtsi b/boards/silabs/dev_kits/sltb010a/thunderboard.dtsi index 71979837476..0ec7c11aa15 100644 --- a/boards/silabs/dev_kits/sltb010a/thunderboard.dtsi +++ b/boards/silabs/dev_kits/sltb010a/thunderboard.dtsi @@ -5,13 +5,13 @@ */ #include -#include / { chosen { zephyr,bt-c2h-uart = &usart1; zephyr,console = &usart1; zephyr,shell-uart = &usart1; + zephyr,uart-pipe = &usart1; zephyr,sram = &sram0; zephyr,flash = &flash0; }; @@ -19,7 +19,7 @@ leds { compatible = "gpio-leds"; led0: led_0 { - gpios = <&gpiob GECKO_PIN(0) GPIO_ACTIVE_HIGH>; + gpios = <&gpiob 0 GPIO_ACTIVE_HIGH>; label = "LED 0"; }; }; @@ -27,7 +27,7 @@ buttons { compatible = "gpio-keys"; button0: button_0 { - gpios = <&gpiob GECKO_PIN(1) GPIO_ACTIVE_LOW>; + gpios = <&gpiob 1 GPIO_ACTIVE_LOW>; label = "User Push Button 0"; zephyr,code = ; }; @@ -35,7 +35,7 @@ wake_up_trigger: gpio-wake-up { compatible = "silabs,gecko-wake-up-trigger"; - gpios = <&gpioa GECKO_PIN(5) GPIO_ACTIVE_LOW>; + gpios = <&gpioa 5 GPIO_ACTIVE_LOW>; }; /* GPIOs that power up different sensors */ @@ -130,11 +130,7 @@ status = "okay"; }; -&burtc0 { - status = "okay"; -}; - -&stimer0 { +&rtcc0 { status = "okay"; }; @@ -142,17 +138,6 @@ status = "okay"; }; -&pinctrl { - i2c0_default: i2c0_default { - group1 { - psels = , - , - , - ; - }; - }; -}; - &i2c0 { pinctrl-0 = <&i2c0_default>; pinctrl-names = "default"; diff --git a/boards/silabs/dev_kits/xg24_dk2601b/Kconfig.defconfig b/boards/silabs/dev_kits/xg24_dk2601b/Kconfig.defconfig index 01e02d66d11..13cb5b0c77c 100644 --- a/boards/silabs/dev_kits/xg24_dk2601b/Kconfig.defconfig +++ b/boards/silabs/dev_kits/xg24_dk2601b/Kconfig.defconfig @@ -1,20 +1,8 @@ -# EFR32XG24 DK2601B board - # Copyright (c) 2021, Sateesh Kotapati # SPDX-License-Identifier: Apache-2.0 if BOARD_XG24_DK2601B -config CMU_HFXO_FREQ - default 40000000 - -config CMU_LFXO_FREQ - default 32768 - -config FLASH_BASE_ADDRESS - hex - default 0x08000000 - if SOC_GECKO_USE_RAIL config FPU diff --git a/boards/silabs/dev_kits/xg24_dk2601b/Kconfig.xg24_dk2601b b/boards/silabs/dev_kits/xg24_dk2601b/Kconfig.xg24_dk2601b index bf4ac3677f1..b4f862550c8 100644 --- a/boards/silabs/dev_kits/xg24_dk2601b/Kconfig.xg24_dk2601b +++ b/boards/silabs/dev_kits/xg24_dk2601b/Kconfig.xg24_dk2601b @@ -1,5 +1,3 @@ -# EFR32XG24 DK2601B board - # Copyright (c) 2021, Sateesh Kotapati # SPDX-License-Identifier: Apache-2.0 diff --git a/boards/silabs/dev_kits/xg24_dk2601b/board.c b/boards/silabs/dev_kits/xg24_dk2601b/board.c index 601b759b6ca..52c2e02e44a 100644 --- a/boards/silabs/dev_kits/xg24_dk2601b/board.c +++ b/boards/silabs/dev_kits/xg24_dk2601b/board.c @@ -9,21 +9,12 @@ #include #include -#ifdef CONFIG_SOC_GECKO_DEV_INIT -#include "em_cmu.h" -#endif - LOG_MODULE_REGISTER(efr32xg24_dk2601b, CONFIG_BOARD_EFR32MG24_LOG_LEVEL); -static int efr32xg24_dk2601b_init_clocks(void); - static int efr32xg24_dk2601b_init(void) { int ret; -#ifdef CONFIG_SOC_GECKO_DEV_INIT - efr32xg24_dk2601b_init_clocks(); -#endif static struct gpio_dt_spec wake_up_gpio_dev = GPIO_DT_SPEC_GET(DT_NODELABEL(wake_up_trigger), gpios); @@ -40,32 +31,5 @@ static int efr32xg24_dk2601b_init(void) return 0; } -#ifdef CONFIG_SOC_GECKO_DEV_INIT -static int efr32xg24_dk2601b_init_clocks(void) -{ - CMU_ClockSelectSet(cmuClock_SYSCLK, cmuSelect_HFRCODPLL); -#if defined(_CMU_EM01GRPACLKCTRL_MASK) - CMU_ClockSelectSet(cmuClock_EM01GRPACLK, cmuSelect_HFRCODPLL); -#endif -#if defined(_CMU_EM01GRPBCLKCTRL_MASK) - CMU_ClockSelectSet(cmuClock_EM01GRPBCLK, cmuSelect_HFRCODPLL); -#endif - CMU_ClockSelectSet(cmuClock_EM23GRPACLK, cmuSelect_LFRCO); - CMU_ClockSelectSet(cmuClock_EM4GRPACLK, cmuSelect_LFRCO); -#if defined(RTCC_PRESENT) - CMU_ClockSelectSet(cmuClock_RTCC, cmuSelect_LFRCO); -#endif -#if defined(SYSRTC_PRESENT) - CMU_ClockSelectSet(cmuClock_SYSRTC, cmuSelect_LFRCO); -#endif - CMU_ClockSelectSet(cmuClock_WDOG0, cmuSelect_LFRCO); -#if WDOG_COUNT > 1 - CMU_ClockSelectSet(cmuClock_WDOG1, cmuSelect_LFRCO); -#endif - - return 0; -} -#endif - /* needs to be done after GPIO driver init */ SYS_INIT(efr32xg24_dk2601b_init, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE); diff --git a/boards/silabs/dev_kits/xg24_dk2601b/board.cmake b/boards/silabs/dev_kits/xg24_dk2601b/board.cmake index a3f0cd9faea..8ea96e1cc62 100644 --- a/boards/silabs/dev_kits/xg24_dk2601b/board.cmake +++ b/boards/silabs/dev_kits/xg24_dk2601b/board.cmake @@ -1,7 +1,5 @@ # Copyright (c) 2021, Sateesh Kotapati -# # SPDX-License-Identifier: Apache-2.0 -# board_runner_args(jlink "--device=EFR32MG24BxxxF1536" "--reset-after-load") include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/silabs/dev_kits/xg24_dk2601b/doc/index.rst b/boards/silabs/dev_kits/xg24_dk2601b/doc/index.rst index 069b1d8923f..c2453e977c0 100644 --- a/boards/silabs/dev_kits/xg24_dk2601b/doc/index.rst +++ b/boards/silabs/dev_kits/xg24_dk2601b/doc/index.rst @@ -1,7 +1,4 @@ -.. _efr32mg24_dk2601b: - -EFR32xG24 Dev Kit (xG24-DK2601B) -################################ +.. zephyr:board:: xg24_dk2601b Overview ******** @@ -10,13 +7,6 @@ The EFR32MG24 Mighty Gecko Board dev kit contains a Wireless System-On-Chip from the EFR32MG24 family built on an ARM Cortex®-M33F processor with excellent low power capabilities. -.. figure:: ./img/xg24_dk2601b.jpg - :height: 260px - :align: center - :alt: xG24-DK2601B Dev Kit board - - xG24-DK2601B (image courtesy of Silicon Labs) - Hardware ******** @@ -66,6 +56,8 @@ The board configuration supports the following hardware features: +-----------+------------+-------------------------------------+ | UART | on-chip | serial | +-----------+------------+-------------------------------------+ +| DMA | on-chip | ldma | ++-----------+------------+-------------------------------------+ | TRNG | on-chip | semailbox | +-----------+------------+-------------------------------------+ | WATCHDOG | on-chip | watchdog | @@ -119,7 +111,7 @@ Programming and Debugging .. note:: Before using the kit the first time, you should update the J-Link firmware - from `J-Link-Downloads`_ + in Simplicity Studio. Flashing ======== @@ -179,6 +171,3 @@ this example. .. _BRD2601B User Guide: https://www.silabs.com/documents/public/user-guides/ug524-brd2601b-user-guide.pdf - -.. _J-Link-Downloads: - https://www.segger.com/downloads/jlink diff --git a/boards/silabs/dev_kits/xg24_dk2601b/xg24_dk2601b-pinctrl.dtsi b/boards/silabs/dev_kits/xg24_dk2601b/xg24_dk2601b-pinctrl.dtsi new file mode 100644 index 00000000000..30aaa4655ba --- /dev/null +++ b/boards/silabs/dev_kits/xg24_dk2601b/xg24_dk2601b-pinctrl.dtsi @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2024 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + usart0_default: usart0_default { + group0 { + pins = ; + drive-push-pull; + output-high; + }; + group1 { + pins = ; + input-enable; + silabs,input-filter; + }; + }; + + i2c0_default: i2c0_default { + group0 { + pins = , ; + drive-open-drain; + bias-pull-up; + }; + }; +}; diff --git a/boards/silabs/dev_kits/xg24_dk2601b/xg24_dk2601b.dts b/boards/silabs/dev_kits/xg24_dk2601b/xg24_dk2601b.dts index ac03b32ff37..0859df1b3d4 100644 --- a/boards/silabs/dev_kits/xg24_dk2601b/xg24_dk2601b.dts +++ b/boards/silabs/dev_kits/xg24_dk2601b/xg24_dk2601b.dts @@ -6,8 +6,9 @@ /dts-v1/; #include -#include #include +#include +#include "xg24_dk2601b-pinctrl.dtsi" / { model = "Silicon Labs BRD2601B (xG24 Dev Kit)"; @@ -16,6 +17,7 @@ chosen { zephyr,console = &usart0; zephyr,shell-uart = &usart0; + zephyr,uart-pipe = &usart0; zephyr,sram = &sram0; zephyr,flash = &flash0; zephyr,code-partition = &slot0_partition; @@ -34,37 +36,37 @@ leds { compatible = "gpio-leds"; red_led: led_2 { - gpios = <&gpiod GECKO_PIN(2) GPIO_ACTIVE_LOW>; + gpios = <&gpiod 2 GPIO_ACTIVE_LOW>; }; green_led: led_0 { - gpios = <&gpioa GECKO_PIN(4) GPIO_ACTIVE_LOW>; + gpios = <&gpioa 4 GPIO_ACTIVE_LOW>; }; blue_led: led_1 { - gpios = <&gpiob GECKO_PIN(0) GPIO_ACTIVE_LOW>; + gpios = <&gpiob 0 GPIO_ACTIVE_LOW>; }; }; buttons { compatible = "gpio-keys"; button0: button_0 { - gpios = <&gpiob GECKO_PIN(2) GPIO_ACTIVE_LOW>; + gpios = <&gpiob 2 GPIO_ACTIVE_LOW>; zephyr,code = ; }; button1: button_1 { - gpios = <&gpiob GECKO_PIN(3) GPIO_ACTIVE_LOW>; + gpios = <&gpiob 3 GPIO_ACTIVE_LOW>; zephyr,code = ; }; }; wake_up_trigger: gpio-wake-up { compatible = "silabs,gecko-wake-up-trigger"; - gpios = <&gpioa GECKO_PIN(5) GPIO_ACTIVE_LOW>; + gpios = <&gpioa 5 GPIO_ACTIVE_LOW>; }; sensor_enable: gpio_switch_0 { compatible = "regulator-fixed"; regulator-name = "sensor_enable"; - enable-gpios = <&gpioc GECKO_PIN(9) GPIO_ACTIVE_HIGH>; + enable-gpios = <&gpioc 9 GPIO_ACTIVE_HIGH>; regulator-boot-on; }; }; @@ -73,6 +75,48 @@ clock-frequency = <78000000>; }; +&hfxo { + status = "okay"; + ctune = <140>; + precision = <50>; +}; + +&lfxo { + status = "okay"; + ctune = <63>; + precision = <50>; +}; + +&hfrcodpll { + clock-frequency = ; + clocks = <&hfxo>; + dpll-n = <3839>; + dpll-m = <1919>; + dpll-edge = "fall"; + dpll-lock = "phase"; + dpll-autorecover; +}; + +&em23grpaclk { + clocks = <&lfxo>; +}; + +&em4grpaclk { + clocks = <&lfxo>; +}; + +&sysrtcclk { + clocks = <&lfxo>; +}; + +&wdog0clk { + clocks = <&lfxo>; +}; + +&wdog1clk { + clocks = <&lfxo>; +}; + &usart0 { current-speed = <115200>; pinctrl-0 = <&usart0_default>; @@ -132,6 +176,13 @@ status = "okay"; }; +&dcdc { + status = "okay"; + regulator-boot-on; + regulator-initial-mode = ; + silabs,pfmx-peak-current-milliamp = <120>; +}; + &flash0 { partitions { compatible = "fixed-partitions"; @@ -175,7 +226,7 @@ status = "okay"; }; -&stimer0 { +&sysrtc0 { status = "okay"; }; diff --git a/boards/silabs/dev_kits/xg24_dk2601b/xg24_dk2601b.yaml b/boards/silabs/dev_kits/xg24_dk2601b/xg24_dk2601b.yaml index ed39649abe6..599c5c6657e 100644 --- a/boards/silabs/dev_kits/xg24_dk2601b/xg24_dk2601b.yaml +++ b/boards/silabs/dev_kits/xg24_dk2601b/xg24_dk2601b.yaml @@ -12,7 +12,9 @@ supported: - counter - gpio - uart + - dma - watchdog + - clock_control testing: ignore_tags: - pm diff --git a/boards/silabs/dev_kits/xg24_dk2601b/xg24_dk2601b_defconfig b/boards/silabs/dev_kits/xg24_dk2601b/xg24_dk2601b_defconfig index caadb4bb35b..ea3fbea0c13 100644 --- a/boards/silabs/dev_kits/xg24_dk2601b/xg24_dk2601b_defconfig +++ b/boards/silabs/dev_kits/xg24_dk2601b/xg24_dk2601b_defconfig @@ -5,13 +5,8 @@ CONFIG_ARM_MPU=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y -CONFIG_CORTEX_M_SYSTICK=y CONFIG_GPIO=y -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=76800000 -CONFIG_CMU_HFCLK_HFXO=y -CONFIG_CMU_HFCLK_LFXO=y CONFIG_HW_STACK_PROTECTION=y -CONFIG_PINCTRL=y CONFIG_REGULATOR=y CONFIG_SOC_GECKO_EMU_DCDC=y CONFIG_SOC_GECKO_EMU_DCDC_MODE_ON=y diff --git a/boards/silabs/dev_kits/xg24_ek2703a/CMakeLists.txt b/boards/silabs/dev_kits/xg24_ek2703a/CMakeLists.txt new file mode 100644 index 00000000000..2e35c87b81d --- /dev/null +++ b/boards/silabs/dev_kits/xg24_ek2703a/CMakeLists.txt @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Norik Systems +# SPDX-License-Identifier: Apache-2.0 + +zephyr_library() +zephyr_library_sources(board.c) diff --git a/boards/silabs/dev_kits/xg24_ek2703a/Kconfig b/boards/silabs/dev_kits/xg24_ek2703a/Kconfig new file mode 100644 index 00000000000..bcc3f461f6e --- /dev/null +++ b/boards/silabs/dev_kits/xg24_ek2703a/Kconfig @@ -0,0 +1,16 @@ +# EFR32XG24 EK2703A board + +# Copyright (c) 2022, Silicon Labs +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_XG24_EK2703A + +config BOARD_XG24_EK2703A + select GPIO + select BOARD_LATE_INIT_HOOK + +module = BOARD_EFR32MG24 +module-str = Board Control +source "subsys/logging/Kconfig.template.log_config" + +endif # BOARD_XG24_EK2703A diff --git a/boards/silabs/dev_kits/xg24_ek2703a/Kconfig.defconfig b/boards/silabs/dev_kits/xg24_ek2703a/Kconfig.defconfig new file mode 100644 index 00000000000..53290acffd0 --- /dev/null +++ b/boards/silabs/dev_kits/xg24_ek2703a/Kconfig.defconfig @@ -0,0 +1,26 @@ +# Copyright (c) 2021, Sateesh Kotapati +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_XG24_EK2703A + +config CMU_HFXO_FREQ + default 39000000 + +config CMU_LFXO_FREQ + default 32768 + +if SOC_GECKO_USE_RAIL + +config FPU + default y + +endif # SOC_GECKO_USE_RAIL + +if BT + +config COMMON_LIBC_MALLOC_ARENA_SIZE + default 8192 + +endif # BT + +endif # BOARD_XG24_EK2703A diff --git a/boards/silabs/dev_kits/xg24_ek2703a/Kconfig.xg24_ek2703a b/boards/silabs/dev_kits/xg24_ek2703a/Kconfig.xg24_ek2703a new file mode 100644 index 00000000000..275ebeb1f6a --- /dev/null +++ b/boards/silabs/dev_kits/xg24_ek2703a/Kconfig.xg24_ek2703a @@ -0,0 +1,5 @@ +# Copyright (c) 2021, Sateesh Kotapati +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_XG24_EK2703A + select SOC_PART_NUMBER_EFR32MG24B210F1536IM48 diff --git a/boards/silabs/dev_kits/xg24_ek2703a/board.c b/boards/silabs/dev_kits/xg24_ek2703a/board.c new file mode 100644 index 00000000000..2ffc7aa210d --- /dev/null +++ b/boards/silabs/dev_kits/xg24_ek2703a/board.c @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2021 Sateesh Kotapati + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include + +LOG_MODULE_REGISTER(efr32xg24_ek2703a, CONFIG_BOARD_EFR32MG24_LOG_LEVEL); + +void board_late_init_hook(void) +{ + int ret; + + static struct gpio_dt_spec wake_up_gpio_dev = + GPIO_DT_SPEC_GET(DT_NODELABEL(wake_up_trigger), gpios); + + if (!gpio_is_ready_dt(&wake_up_gpio_dev)) { + LOG_ERR("Wake-up GPIO device was not found!\n"); + } + ret = gpio_pin_configure_dt(&wake_up_gpio_dev, GPIO_OUTPUT_ACTIVE); + if (ret < 0) { + LOG_ERR("Failed to configure wake-up GPIO!\n"); + } +} diff --git a/boards/silabs/dev_kits/xg24_ek2703a/board.cmake b/boards/silabs/dev_kits/xg24_ek2703a/board.cmake new file mode 100644 index 00000000000..a39d499a6c2 --- /dev/null +++ b/boards/silabs/dev_kits/xg24_ek2703a/board.cmake @@ -0,0 +1,8 @@ +# Copyright (c) 2021, Sateesh Kotapati +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=EFR32MG24BxxxF1536" "--reset-after-load") +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) + +board_runner_args(silabs_commander "--device=EFR32MG24B210F1536IM48") +include(${ZEPHYR_BASE}/boards/common/silabs_commander.board.cmake) diff --git a/boards/silabs/dev_kits/xg24_ek2703a/board.yml b/boards/silabs/dev_kits/xg24_ek2703a/board.yml new file mode 100644 index 00000000000..7327014ed54 --- /dev/null +++ b/boards/silabs/dev_kits/xg24_ek2703a/board.yml @@ -0,0 +1,6 @@ +board: + name: xg24_ek2703a + full_name: EFR32xG24 Explorer Kit (xG24-EK2703A) + vendor: silabs + socs: + - name: efr32mg24b210f1536im48 diff --git a/boards/silabs/dev_kits/xg24_ek2703a/doc/index.rst b/boards/silabs/dev_kits/xg24_ek2703a/doc/index.rst new file mode 100644 index 00000000000..e841838b1be --- /dev/null +++ b/boards/silabs/dev_kits/xg24_ek2703a/doc/index.rst @@ -0,0 +1,163 @@ +.. zephyr:board:: xg24_ek2703a + +Overview +******** + +The EFR32xG24 Explorer Kit (xG24-EK2703A) contains +a Wireless System-On-Chip from the EFR32MG24 family built on an +ARM Cortex®-M33 processor with excellent low power capabilities. + +Hardware +******** + +- EFR32MG24B210F1536IM48-B Mighty Gecko SoC +- CPU core: ARM Cortex®-M33 with FPU +- Flash memory: 1536 kB +- RAM: 256 kB +- Transmit power: up to +10 dBm +- Operation frequency: 2.4 GHz +- Crystals for LFXO (32.768 kHz) and HFXO (39 MHz). + +For more information about the EFR32MG24 SoC and BRD2703A board, refer to these +documents: + +- `EFR32MG24 Website`_ +- `EFR32MG24 Datasheet`_ +- `EFR32xG24 Reference Manual`_ +- `BRD2703A User Guide`_ + +Supported Features +================== + +The ``xg24_ek2703a`` board supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| MPU | on-chip | memory protection unit | ++-----------+------------+-------------------------------------+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| COUNTER | on-chip | stimer | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial | ++-----------+------------+-------------------------------------+ +| TRNG | on-chip | semailbox | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | watchdog | ++-----------+------------+-------------------------------------+ +| I2C(M/S) | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| RADIO | on-chip | bluetooth | ++-----------+------------+-------------------------------------+ + +Other hardware features are currently not supported by the port. + +Connections and IOs +=================== + +In the following table, the column **Name** contains Pin names. For example, PA2 +means Pin number 2 on PORTA, as used in the board's datasheets and manuals. + ++-------+-------------+-------------------------------------+ +| Name | Function | Usage | ++=======+=============+=====================================+ +| PA4 | GPIO | LED0 | ++-------+-------------+-------------------------------------+ +| PA7 | GPIO | LED1 | ++-------+-------------+-------------------------------------+ +| PB2 | GPIO | Push Button 0 | ++-------+-------------+-------------------------------------+ +| PB3 | GPIO | Push Button 1 | ++-------+-------------+-------------------------------------+ +| PA5 | USART0_TX | UART Console VCOM_TX US0_TX | ++-------+-------------+-------------------------------------+ +| PA6 | USART0_RX | UART Console VCOM_RX US0_RX | ++-------+-------------+-------------------------------------+ + +The default configuration can be found in +:zephyr_file:`boards/silabs/dev_kits/xg24_ek2703a/xg24_ek2703a_defconfig` + +System Clock +============ + +The EFR32MG24 SoC is configured to use the 39 MHz external oscillator on the +board. + +Serial Port +=========== + +The EFR32MG24 SoC has one USART and two EUSARTs. +USART0 is connected to the board controller and is used for the console. + +Programming and Debugging +************************* + +.. note:: + Before using the kit the first time, you should update the J-Link firmware + in Simplicity Studio. + +Flashing +======== + +The sample application :zephyr:code-sample:`hello_world` is used for this example. +Build the Zephyr kernel and application: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: xg24_ek2703a + :goals: build + +Connect the xg24_ek2703a to your host computer using the USB port and you +should see a USB connection. + +Open a serial terminal (minicom, putty, etc.) with the following settings: + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Reset the board and you'll see the following message on the corresponding serial port +terminal session: + +.. code-block:: console + + Hello World! xg24_ek2703a + +Bluetooth +========= + +To use the BLE function, run the command below to retrieve necessary binary +blobs from the SiLabs HAL repository. + +.. code-block:: console + + west blobs fetch hal_silabs + +Then build the Zephyr kernel and a Bluetooth sample with the following +command. The :zephyr:code-sample:`bluetooth_observer` sample application is used in +this example. + +.. zephyr-app-commands:: + :zephyr-app: samples/bluetooth/observer + :board: xg24_ek2703a + :goals: build + +.. _EFR32MG24 Website: + https://www.silabs.com/wireless/zigbee/efr32mg24-series-2-socs# + +.. _EFR32MG24 Datasheet: + https://www.silabs.com/documents/public/data-sheets/efr32mg24-datasheet.pdf + +.. _EFR32xG24 Reference Manual: + https://www.silabs.com/documents/public/reference-manuals/efr32xg24-rm.pdf + +.. _BRD2703A User Guide: + https://www.silabs.com/documents/public/user-guides/ug533-xg24-ek2703a.pdf diff --git a/boards/silabs/dev_kits/xg24_ek2703a/dts/bindings/silabs,gecko-wake-up-trigger.yaml b/boards/silabs/dev_kits/xg24_ek2703a/dts/bindings/silabs,gecko-wake-up-trigger.yaml new file mode 100644 index 00000000000..ba8892f2ce0 --- /dev/null +++ b/boards/silabs/dev_kits/xg24_ek2703a/dts/bindings/silabs,gecko-wake-up-trigger.yaml @@ -0,0 +1,15 @@ +# Copyright (c) 2022, Antmicro +# SPDX-License-Identifier: Apache-2.0 + +description: GPIO Wake Up Trigger for EFR32MG24 + +compatible: "silabs,gecko-wake-up-trigger" + +include: base.yaml + +properties: + gpios: + type: phandle-array + required: true + description: | + GPIO used as wake up trigger from EM4 sleep diff --git a/boards/silabs/dev_kits/xg24_ek2703a/pre_dt_board.cmake b/boards/silabs/dev_kits/xg24_ek2703a/pre_dt_board.cmake new file mode 100644 index 00000000000..beb76b85552 --- /dev/null +++ b/boards/silabs/dev_kits/xg24_ek2703a/pre_dt_board.cmake @@ -0,0 +1,5 @@ +# Copyright (c) 2021 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +# SPI is implemented via usart so node name isn't spi@... +list(APPEND EXTRA_DTC_FLAGS "-Wno-spi_bus_bridge") diff --git a/boards/silabs/dev_kits/xg24_ek2703a/xg24_ek2703a-pinctrl.dtsi b/boards/silabs/dev_kits/xg24_ek2703a/xg24_ek2703a-pinctrl.dtsi new file mode 100644 index 00000000000..30aaa4655ba --- /dev/null +++ b/boards/silabs/dev_kits/xg24_ek2703a/xg24_ek2703a-pinctrl.dtsi @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2024 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + usart0_default: usart0_default { + group0 { + pins = ; + drive-push-pull; + output-high; + }; + group1 { + pins = ; + input-enable; + silabs,input-filter; + }; + }; + + i2c0_default: i2c0_default { + group0 { + pins = , ; + drive-open-drain; + bias-pull-up; + }; + }; +}; diff --git a/boards/silabs/dev_kits/xg24_ek2703a/xg24_ek2703a.dts b/boards/silabs/dev_kits/xg24_ek2703a/xg24_ek2703a.dts new file mode 100644 index 00000000000..a4bf9f857e5 --- /dev/null +++ b/boards/silabs/dev_kits/xg24_ek2703a/xg24_ek2703a.dts @@ -0,0 +1,206 @@ +/* + * Copyright (c) 2020 TriaGnoSys GmbH + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include +#include "xg24_ek2703a-pinctrl.dtsi" + +/ { + model = "Silicon Labs BRD2703A (xG24 Explorer Kit)"; + compatible = "silabs,xg24_ek2703a", "silabs,efr32mg24"; + + chosen { + zephyr,console = &usart0; + zephyr,shell-uart = &usart0; + zephyr,uart-pipe = &usart0; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + zephyr,bt-hci = &bt_hci_silabs; + }; + + aliases { + led0 = &led0; + led1 = &led1; + sw0 = &button0; + sw1 = &button1; + watchdog0 = &wdog0; + }; + + leds { + compatible = "gpio-leds"; + led0: led_0 { + gpios = <&gpioa 4 GPIO_ACTIVE_LOW>; + }; + led1: led_1 { + gpios = <&gpioa 7 GPIO_ACTIVE_LOW>; + }; + }; + + buttons { + compatible = "gpio-keys"; + button0: button_0 { + gpios = <&gpiob 2 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + button1: button_1 { + gpios = <&gpiob 3 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + }; + + wake_up_trigger: gpio-wake-up { + compatible = "silabs,gecko-wake-up-trigger"; + gpios = <&gpioa 5 GPIO_ACTIVE_LOW>; + }; +}; + +&cpu0 { + clock-frequency = <78000000>; +}; + +&hfxo { + status = "okay"; + ctune = <140>; + precision = <50>; +}; + +&lfxo { + status = "okay"; + ctune = <63>; + precision = <50>; +}; + +&hfrcodpll { + clock-frequency = ; + clocks = <&hfxo>; + dpll-n = <3839>; + dpll-m = <1919>; + dpll-edge = "fall"; + dpll-lock = "phase"; + dpll-autorecover; +}; + +&em23grpaclk { + clocks = <&lfxo>; +}; + +&em4grpaclk { + clocks = <&lfxo>; +}; + +&sysrtcclk { + clocks = <&lfxo>; +}; + +&wdog0clk { + clocks = <&lfxo>; +}; + +&wdog1clk { + clocks = <&lfxo>; +}; + +&usart0 { + current-speed = <115200>; + pinctrl-0 = <&usart0_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&i2c0 { + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&gpio { + status = "okay"; +}; + +&gpioa { + status = "okay"; +}; + +&gpiob { + status = "okay"; +}; + +&gpioc { + status = "okay"; +}; + +&gpiod { + status = "okay"; +}; + +&wdog0 { + status = "okay"; +}; + +&se { + status = "okay"; +}; + +&dcdc { + status = "okay"; + regulator-boot-on; + regulator-initial-mode = ; + silabs,pfmx-peak-current-milliamp = <120>; +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 48 kB for the bootloader */ + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x0 0x0000c000>; + read-only; + }; + + /* Reserve 464 kB for the application in slot 0 */ + slot0_partition: partition@c000 { + label = "image-0"; + reg = <0x0000c000 0x00074000>; + }; + + /* Reserve 464 kB for the application in slot 1 */ + slot1_partition: partition@80000 { + label = "image-1"; + reg = <0x00080000 0x00074000>; + }; + + /* Reserve 32 kB for the scratch partition */ + scratch_partition: partition@f4000 { + label = "image-scratch"; + reg = <0x000f4000 0x00008000>; + }; + + /* Set 528Kb of storage at the end of the 1024Kb of flash */ + storage_partition: partition@fc000 { + label = "storage"; + reg = <0x000fc000 0x00084000>; + }; + }; +}; + +&adc0 { + status = "okay"; +}; + +&sysrtc0 { + status = "okay"; +}; + +&bt_hci_silabs { + status = "okay"; +}; diff --git a/boards/silabs/dev_kits/xg24_ek2703a/xg24_ek2703a.yaml b/boards/silabs/dev_kits/xg24_ek2703a/xg24_ek2703a.yaml new file mode 100644 index 00000000000..551f2754872 --- /dev/null +++ b/boards/silabs/dev_kits/xg24_ek2703a/xg24_ek2703a.yaml @@ -0,0 +1,21 @@ +identifier: xg24_ek2703a +name: EFR32xG24 Explorer Kit (xG24-EK2703A, BRD2703A) +type: mcu +arch: arm +ram: 256 +flash: 1536 +toolchain: + - zephyr + - gnuarmemb +supported: + - bluetooth + - counter + - gpio + - uart + - watchdog + - clock_control +testing: + ignore_tags: + - pm + - hwinfo +vendor: silabs diff --git a/boards/silabs/dev_kits/xg24_ek2703a/xg24_ek2703a_defconfig b/boards/silabs/dev_kits/xg24_ek2703a/xg24_ek2703a_defconfig new file mode 100644 index 00000000000..ea3fbea0c13 --- /dev/null +++ b/boards/silabs/dev_kits/xg24_ek2703a/xg24_ek2703a_defconfig @@ -0,0 +1,12 @@ +# Copyright (c) 2022 Silicon Labs +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARM_MPU=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_GPIO=y +CONFIG_HW_STACK_PROTECTION=y +CONFIG_REGULATOR=y +CONFIG_SOC_GECKO_EMU_DCDC=y +CONFIG_SOC_GECKO_EMU_DCDC_MODE_ON=y diff --git a/boards/silabs/dev_kits/xg27_dk2602a/Kconfig.defconfig b/boards/silabs/dev_kits/xg27_dk2602a/Kconfig.defconfig index 850f2cd8538..fac4f17b12e 100644 --- a/boards/silabs/dev_kits/xg27_dk2602a/Kconfig.defconfig +++ b/boards/silabs/dev_kits/xg27_dk2602a/Kconfig.defconfig @@ -1,12 +1,6 @@ # Copyright (c) 2023 Antmicro # SPDX-License-Identifier: Apache-2.0 -config CMU_HFXO_FREQ - default 38400000 - -config CMU_LFXO_FREQ - default 32768 - if SOC_GECKO_USE_RAIL config FPU diff --git a/boards/silabs/dev_kits/xg27_dk2602a/Kconfig.xg27_dk2602a b/boards/silabs/dev_kits/xg27_dk2602a/Kconfig.xg27_dk2602a index d5f2945cdfd..c766b128ff1 100644 --- a/boards/silabs/dev_kits/xg27_dk2602a/Kconfig.xg27_dk2602a +++ b/boards/silabs/dev_kits/xg27_dk2602a/Kconfig.xg27_dk2602a @@ -1,5 +1,3 @@ -# EFR32BG SLTB010A board - # Copyright (c) 2021, Sateesh Kotapati # SPDX-License-Identifier: Apache-2.0 diff --git a/boards/silabs/dev_kits/xg27_dk2602a/board.c b/boards/silabs/dev_kits/xg27_dk2602a/board.c index f26befcf508..7c466f6ee74 100644 --- a/boards/silabs/dev_kits/xg27_dk2602a/board.c +++ b/boards/silabs/dev_kits/xg27_dk2602a/board.c @@ -8,22 +8,12 @@ #include #include -#ifdef CONFIG_SOC_GECKO_DEV_INIT -#include "em_cmu.h" -#endif - - LOG_MODULE_REGISTER(dev_kit, CONFIG_BOARD_XG27_DK2602A_LOG_LEVEL); -static int dev_kit_init_clocks(void); - static int dev_kit_init(void) { int ret; -#ifdef CONFIG_SOC_GECKO_DEV_INIT - dev_kit_init_clocks(); -#endif static struct gpio_dt_spec wake_up_gpio_dev = GPIO_DT_SPEC_GET(DT_NODELABEL(wake_up_trigger), gpios); @@ -40,25 +30,5 @@ static int dev_kit_init(void) return 0; } -#ifdef CONFIG_SOC_GECKO_DEV_INIT -static int dev_kit_init_clocks(void) -{ - CMU_ClockSelectSet(cmuClock_SYSCLK, cmuSelect_HFRCODPLL); -#if defined(_CMU_EM01GRPACLKCTRL_MASK) - CMU_ClockSelectSet(cmuClock_EM01GRPACLK, cmuSelect_HFRCODPLL); -#endif -#if defined(_CMU_EM01GRPBCLKCTRL_MASK) - CMU_ClockSelectSet(cmuClock_EM01GRPBCLK, cmuSelect_HFRCODPLL); -#endif - CMU_ClockSelectSet(cmuClock_EM23GRPACLK, cmuSelect_LFRCO); -#if defined(RTCC_PRESENT) - CMU_ClockSelectSet(cmuClock_RTCC, cmuSelect_LFRCO); -#endif - CMU_ClockSelectSet(cmuClock_WDOG0, cmuSelect_LFRCO); - - return 0; -} -#endif - /* needs to be done after GPIO driver init */ SYS_INIT(dev_kit_init, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE); diff --git a/boards/silabs/dev_kits/xg27_dk2602a/board.cmake b/boards/silabs/dev_kits/xg27_dk2602a/board.cmake index a5086fdebd9..805a47d77e0 100644 --- a/boards/silabs/dev_kits/xg27_dk2602a/board.cmake +++ b/boards/silabs/dev_kits/xg27_dk2602a/board.cmake @@ -3,5 +3,6 @@ board_runner_args(jlink "--device=EFR32BG27CxxxF768" "--reset-after-load") include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) + board_runner_args(silabs_commander "--device=EFR32BG27C140F768IM40") include(${ZEPHYR_BASE}/boards/common/silabs_commander.board.cmake) diff --git a/boards/silabs/dev_kits/xg27_dk2602a/doc/index.rst b/boards/silabs/dev_kits/xg27_dk2602a/doc/index.rst index 273b78e60ba..c700e1cf9c0 100644 --- a/boards/silabs/dev_kits/xg27_dk2602a/doc/index.rst +++ b/boards/silabs/dev_kits/xg27_dk2602a/doc/index.rst @@ -1,18 +1,8 @@ -.. _xg27_dk2602a: - -EFR32xG27 Dev Kit (xG27-DK2602A) -################################ +.. zephyr:board:: xg27_dk2602a Silicon Labs xG27-DK2602A is a Dev Kit using the EFR32BG27 SoC. The kit consists of the EFR32BG27 +8 dBm Dev Kit Board (BRD2602A). -.. figure:: ./xg27_dk2602a.png - :height: 260px - :align: center - :alt: xG27-DK2602A - - xG27-DK2602A (image courtesy of Silicon Labs) - Hardware ******** @@ -57,6 +47,8 @@ The xg27_dk2602a board configuration supports the following hardware features: +-----------+------------+-------------------------------------+ | UART | on-chip | serial | +-----------+------------+-------------------------------------+ +| DMA | on-chip | ldma | ++-----------+------------+-------------------------------------+ Flashing ======== diff --git a/boards/silabs/dev_kits/xg27_dk2602a/thunderboard.dtsi b/boards/silabs/dev_kits/xg27_dk2602a/thunderboard.dtsi index 71979837476..0ec7c11aa15 100644 --- a/boards/silabs/dev_kits/xg27_dk2602a/thunderboard.dtsi +++ b/boards/silabs/dev_kits/xg27_dk2602a/thunderboard.dtsi @@ -5,13 +5,13 @@ */ #include -#include / { chosen { zephyr,bt-c2h-uart = &usart1; zephyr,console = &usart1; zephyr,shell-uart = &usart1; + zephyr,uart-pipe = &usart1; zephyr,sram = &sram0; zephyr,flash = &flash0; }; @@ -19,7 +19,7 @@ leds { compatible = "gpio-leds"; led0: led_0 { - gpios = <&gpiob GECKO_PIN(0) GPIO_ACTIVE_HIGH>; + gpios = <&gpiob 0 GPIO_ACTIVE_HIGH>; label = "LED 0"; }; }; @@ -27,7 +27,7 @@ buttons { compatible = "gpio-keys"; button0: button_0 { - gpios = <&gpiob GECKO_PIN(1) GPIO_ACTIVE_LOW>; + gpios = <&gpiob 1 GPIO_ACTIVE_LOW>; label = "User Push Button 0"; zephyr,code = ; }; @@ -35,7 +35,7 @@ wake_up_trigger: gpio-wake-up { compatible = "silabs,gecko-wake-up-trigger"; - gpios = <&gpioa GECKO_PIN(5) GPIO_ACTIVE_LOW>; + gpios = <&gpioa 5 GPIO_ACTIVE_LOW>; }; /* GPIOs that power up different sensors */ @@ -130,11 +130,7 @@ status = "okay"; }; -&burtc0 { - status = "okay"; -}; - -&stimer0 { +&rtcc0 { status = "okay"; }; @@ -142,17 +138,6 @@ status = "okay"; }; -&pinctrl { - i2c0_default: i2c0_default { - group1 { - psels = , - , - , - ; - }; - }; -}; - &i2c0 { pinctrl-0 = <&i2c0_default>; pinctrl-names = "default"; diff --git a/boards/silabs/dev_kits/xg27_dk2602a/xg27_dk2602a-pinctrl.dtsi b/boards/silabs/dev_kits/xg27_dk2602a/xg27_dk2602a-pinctrl.dtsi new file mode 100644 index 00000000000..915d9bfe209 --- /dev/null +++ b/boards/silabs/dev_kits/xg27_dk2602a/xg27_dk2602a-pinctrl.dtsi @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2024 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + usart0_default: usart0_default { + group0 { + pins = , ; + drive-push-pull; + output-high; + }; + group1 { + pins = ; + input-enable; + }; + }; + + usart1_default: usart1_default { + group0 { + pins = ; + drive-push-pull; + output-high; + }; + group1 { + pins = ; + input-enable; + silabs,input-filter; + }; + }; + + i2c0_default: i2c0_default { + group0 { + pins = , ; + drive-open-drain; + bias-pull-up; + }; + }; +}; diff --git a/boards/silabs/dev_kits/xg27_dk2602a/xg27_dk2602a.dts b/boards/silabs/dev_kits/xg27_dk2602a/xg27_dk2602a.dts index 6dba2bfa648..f201a09e86a 100644 --- a/boards/silabs/dev_kits/xg27_dk2602a/xg27_dk2602a.dts +++ b/boards/silabs/dev_kits/xg27_dk2602a/xg27_dk2602a.dts @@ -6,8 +6,9 @@ /dts-v1/; #include -#include +#include "xg27_dk2602a-pinctrl.dtsi" #include "thunderboard.dtsi" +#include / { model = "Silicon Labs xG27-DK2602A Dev Kit"; @@ -31,6 +32,50 @@ }; }; +&hfxo { + status = "okay"; + ctune = <140>; + precision = <50>; +}; + +&lfxo { + status = "okay"; + ctune = <63>; + precision = <50>; +}; + +&hfrcodpll { + clock-frequency = ; + clocks = <&hfxo>; + dpll-n = <3839>; + dpll-m = <1919>; + dpll-edge = "fall"; + dpll-lock = "phase"; + dpll-autorecover; +}; + +&em23grpaclk { + clocks = <&lfxo>; +}; + +&em4grpaclk { + clocks = <&lfxo>; +}; + +&rtccclk { + clocks = <&lfxo>; +}; + +&wdog0clk { + clocks = <&lfxo>; +}; + +&dcdc { + status = "okay"; + regulator-boot-on; + regulator-initial-mode = ; +}; + &flash0 { partitions { /* Reserve 48 KiB for the bootloader */ @@ -61,25 +106,25 @@ }; &led0 { - gpios = <&gpioa GECKO_PIN(4) GPIO_ACTIVE_HIGH>; + gpios = <&gpioa 4 GPIO_ACTIVE_HIGH>; }; &sw_sensor_enable { - enable-gpios = <&gpioc GECKO_PIN(6) GPIO_ACTIVE_HIGH>; + enable-gpios = <&gpioc 6 GPIO_ACTIVE_HIGH>; }; &sw_mic_enable { - enable-gpios = <&gpioc GECKO_PIN(7) GPIO_ACTIVE_HIGH>; + enable-gpios = <&gpioc 7 GPIO_ACTIVE_HIGH>; }; &sw_imu_enable { - enable-gpios = <&gpiob GECKO_PIN(4) GPIO_ACTIVE_HIGH>; + enable-gpios = <&gpiob 4 GPIO_ACTIVE_HIGH>; }; &button0 { - gpios = <&gpiob GECKO_PIN(3) GPIO_ACTIVE_LOW>; + gpios = <&gpiob 3 GPIO_ACTIVE_LOW>; }; &bt_hci_silabs { diff --git a/boards/silabs/dev_kits/xg27_dk2602a/xg27_dk2602a.yaml b/boards/silabs/dev_kits/xg27_dk2602a/xg27_dk2602a.yaml index bb6a214b786..519f9ce9a9e 100644 --- a/boards/silabs/dev_kits/xg27_dk2602a/xg27_dk2602a.yaml +++ b/boards/silabs/dev_kits/xg27_dk2602a/xg27_dk2602a.yaml @@ -13,4 +13,6 @@ supported: - counter - gpio - uart + - dma + - clock_control vendor: silabs diff --git a/boards/silabs/dev_kits/xg27_dk2602a/xg27_dk2602a_defconfig b/boards/silabs/dev_kits/xg27_dk2602a/xg27_dk2602a_defconfig index 50a14221ec9..b7da445368c 100644 --- a/boards/silabs/dev_kits/xg27_dk2602a/xg27_dk2602a_defconfig +++ b/boards/silabs/dev_kits/xg27_dk2602a/xg27_dk2602a_defconfig @@ -8,13 +8,3 @@ CONFIG_GPIO=y CONFIG_SOC_GECKO_EMU_DCDC=y CONFIG_SOC_GECKO_EMU_DCDC_MODE_ON=y CONFIG_HW_STACK_PROTECTION=y -CONFIG_PINCTRL=y - -# Used if SysTick is enabled, ignored for BURTC -# (BURTC uses TIMER_READS_ITS_FREQUENCY_AT_RUNTIME) -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=76800000 - -# Use BURTC as system clock source -CONFIG_GECKO_BURTC_TIMER=y -CONFIG_CMU_BURTCCLK_LFXO=y -CONFIG_SYS_CLOCK_TICKS_PER_SEC=1024 diff --git a/boards/silabs/radio_boards/common/efr32-series1-common.dtsi b/boards/silabs/radio_boards/common/efr32-series1-common.dtsi index 8ff361eccaa..72e771c1b28 100644 --- a/boards/silabs/radio_boards/common/efr32-series1-common.dtsi +++ b/boards/silabs/radio_boards/common/efr32-series1-common.dtsi @@ -11,6 +11,7 @@ chosen { zephyr,console = &usart0; zephyr,shell-uart = &usart0; + zephyr,uart-pipe = &usart0; zephyr,sram = &sram0; zephyr,flash = &flash0; zephyr,code-partition = &slot0_partition; diff --git a/boards/silabs/radio_boards/slwrb4104a/Kconfig.defconfig b/boards/silabs/radio_boards/slwrb4104a/Kconfig.defconfig index 09a4f9906ae..35290c1e564 100644 --- a/boards/silabs/radio_boards/slwrb4104a/Kconfig.defconfig +++ b/boards/silabs/radio_boards/slwrb4104a/Kconfig.defconfig @@ -1,5 +1,3 @@ -# EFR32 radio board - # Copyright (c) 2020 Piotr Mienkowski # Copyright (c) 2020 TriaGnoSys GmbH # SPDX-License-Identifier: Apache-2.0 @@ -12,10 +10,6 @@ config CMU_HFXO_FREQ config CMU_LFXO_FREQ default 32768 -config FLASH_BASE_ADDRESS - hex - default 0x0 - config LOG_BACKEND_SWO_FREQ_HZ default 875000 depends on LOG_BACKEND_SWO diff --git a/boards/silabs/radio_boards/slwrb4104a/Kconfig.slwrb4104a b/boards/silabs/radio_boards/slwrb4104a/Kconfig.slwrb4104a index 179b7f02c0a..a22a705668e 100644 --- a/boards/silabs/radio_boards/slwrb4104a/Kconfig.slwrb4104a +++ b/boards/silabs/radio_boards/slwrb4104a/Kconfig.slwrb4104a @@ -1,5 +1,3 @@ -# EFR32BG13 BRD4104A - # Copyright (c) 2020 Piotr Mienkowski # Copyright (c) 2020 TriaGnoSys GmbH # SPDX-License-Identifier: Apache-2.0 diff --git a/boards/silabs/radio_boards/slwrb4104a/board.cmake b/boards/silabs/radio_boards/slwrb4104a/board.cmake index cf1d8ee0e75..2dd6552983c 100644 --- a/boards/silabs/radio_boards/slwrb4104a/board.cmake +++ b/boards/silabs/radio_boards/slwrb4104a/board.cmake @@ -1,7 +1,7 @@ # SPDX-License-Identifier: Apache-2.0 -board_runner_args(openocd) board_runner_args(jlink "--device=EFR32BG13PxxxF512") +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +board_runner_args(openocd) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) -include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/silabs/radio_boards/slwrb4104a/board.yml b/boards/silabs/radio_boards/slwrb4104a/board.yml index d1122ace331..65e82240b97 100644 --- a/boards/silabs/radio_boards/slwrb4104a/board.yml +++ b/boards/silabs/radio_boards/slwrb4104a/board.yml @@ -1,5 +1,6 @@ -boards: - - name: slwrb4104a - full_name: EFR32BG13 2.4 GHz 10 dBm (SLWRB4104A) - socs: - - name: efr32bg13p632f512gm48 +board: + name: slwrb4104a + full_name: EFR32BG13 2.4 GHz 10 dBm (SLWRB4104A) + vendor: silabs + socs: + - name: efr32bg13p632f512gm48 diff --git a/boards/silabs/radio_boards/slwrb4104a/doc/index.rst b/boards/silabs/radio_boards/slwrb4104a/doc/index.rst index 3496421743c..1cee2ffd5ab 100644 --- a/boards/silabs/radio_boards/slwrb4104a/doc/index.rst +++ b/boards/silabs/radio_boards/slwrb4104a/doc/index.rst @@ -1,7 +1,4 @@ -.. _slwrb4104a: - -EFR32BG13 2.4 GHz 10 dBm (SLWRB4104A) -##################################### +.. zephyr:board:: slwrb4104a Overview ******** @@ -11,12 +8,6 @@ radio boards delivered with `SLWSTK6020B Bluetooth SoC Starter Kit`_. It contains a Wireless System-On-Chip from the EFR32BG13 family built on an ARM Cortex®-M4F processor with excellent low power capabilities. -.. figure:: efr32bg13-slwrb4104a.jpg - :align: center - :alt: SLWRB4104A Blue Gecko Bluetooth® Low Energy Radio Board - - SLWRB4104A (image courtesy of Silicon Labs) - The BRD4104A a.k.a. SLWRB4104A radio board plugs into the Wireless Starter Kit Mainboard BRD4001A and is supported as one of :ref:`silabs_radio_boards`. diff --git a/boards/silabs/radio_boards/slwrb4104a/slwrb4104a.yaml b/boards/silabs/radio_boards/slwrb4104a/slwrb4104a.yaml index 926a55f3150..a407f847f6f 100644 --- a/boards/silabs/radio_boards/slwrb4104a/slwrb4104a.yaml +++ b/boards/silabs/radio_boards/slwrb4104a/slwrb4104a.yaml @@ -1,5 +1,5 @@ identifier: slwrb4104a -name: EFR32BG13 2.4 GHz 10 dBm Radio Board (SLWRB4104A) +name: EFR32BG13 2.4 GHz 10 dBm Radio Board (SLWRB4104A, BRD4104A) type: mcu arch: arm ram: 64 diff --git a/boards/silabs/radio_boards/slwrb4161a/Kconfig.defconfig b/boards/silabs/radio_boards/slwrb4161a/Kconfig.defconfig index bf950b922f9..a9577b3eac5 100644 --- a/boards/silabs/radio_boards/slwrb4161a/Kconfig.defconfig +++ b/boards/silabs/radio_boards/slwrb4161a/Kconfig.defconfig @@ -1,5 +1,3 @@ -# EFR32 radio board - # Copyright (c) 2020 Piotr Mienkowski # Copyright (c) 2020 TriaGnoSys GmbH # SPDX-License-Identifier: Apache-2.0 @@ -12,10 +10,6 @@ config CMU_HFXO_FREQ config CMU_LFXO_FREQ default 32768 -config FLASH_BASE_ADDRESS - hex - default 0x0 - config LOG_BACKEND_SWO_FREQ_HZ default 875000 depends on LOG_BACKEND_SWO diff --git a/boards/silabs/radio_boards/slwrb4161a/Kconfig.slwrb4161a b/boards/silabs/radio_boards/slwrb4161a/Kconfig.slwrb4161a index 67291857e9f..246762ef071 100644 --- a/boards/silabs/radio_boards/slwrb4161a/Kconfig.slwrb4161a +++ b/boards/silabs/radio_boards/slwrb4161a/Kconfig.slwrb4161a @@ -1,5 +1,3 @@ -# EFR32MG12 BRD4161A - # Copyright (c) 2020 Piotr Mienkowski # Copyright (c) 2020 TriaGnoSys GmbH # SPDX-License-Identifier: Apache-2.0 diff --git a/boards/silabs/radio_boards/slwrb4161a/board.cmake b/boards/silabs/radio_boards/slwrb4161a/board.cmake index be43109892d..b24ae335204 100644 --- a/boards/silabs/radio_boards/slwrb4161a/board.cmake +++ b/boards/silabs/radio_boards/slwrb4161a/board.cmake @@ -1,7 +1,7 @@ # SPDX-License-Identifier: Apache-2.0 -board_runner_args(openocd) board_runner_args(jlink "--device=EFR32MG12PxxxF1024") +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +board_runner_args(openocd) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) -include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/silabs/radio_boards/slwrb4161a/board.yml b/boards/silabs/radio_boards/slwrb4161a/board.yml index fd0c68e48b2..4d5fa40b8be 100644 --- a/boards/silabs/radio_boards/slwrb4161a/board.yml +++ b/boards/silabs/radio_boards/slwrb4161a/board.yml @@ -1,5 +1,6 @@ -boards: - - name: slwrb4161a - full_name: EFR32MG12 2.4 GHz 19 dBm (SLWRB4161A) - socs: - - name: efr32mg12p432f1024gl125 +board: + name: slwrb4161a + full_name: EFR32MG12 2.4 GHz 19 dBm (SLWRB4161A) + vendor: silabs + socs: + - name: efr32mg12p432f1024gl125 diff --git a/boards/silabs/radio_boards/slwrb4161a/doc/index.rst b/boards/silabs/radio_boards/slwrb4161a/doc/index.rst index 927e27c20ae..134dbdb3af0 100644 --- a/boards/silabs/radio_boards/slwrb4161a/doc/index.rst +++ b/boards/silabs/radio_boards/slwrb4161a/doc/index.rst @@ -1,7 +1,4 @@ -.. _slwrb4161a: - -EFR32MG12 2.4 GHz 19 dBm (SLWRB4161A) -##################################### +.. zephyr:board:: slwrb4161a Overview ******** @@ -10,12 +7,6 @@ The EFR32MG12 Mighty Gecko Radio Board contains a Wireless System-On-Chip from the EFR32MG12 family built on an ARM Cortex®-M4F processor with excellent low power capabilities. -.. figure:: efr32mg12-slwrb4161a.jpeg - :align: center - :alt: SLWRB4161A Mighty Gecko Radio Board - - SLWRB4161A (image courtesy of Silicon Labs) - The BRD4161A a.k.a. SLWRB4161A radio board plugs into the Wireless Starter Kit Mainboard BRD4001A and is supported as one of :ref:`silabs_radio_boards`. diff --git a/boards/silabs/radio_boards/slwrb4161a/slwrb4161a.yaml b/boards/silabs/radio_boards/slwrb4161a/slwrb4161a.yaml index 6f46897683e..8890f1dcd98 100644 --- a/boards/silabs/radio_boards/slwrb4161a/slwrb4161a.yaml +++ b/boards/silabs/radio_boards/slwrb4161a/slwrb4161a.yaml @@ -1,5 +1,5 @@ identifier: slwrb4161a -name: EFR32MG12 2.4 GHz 19 dBm Radio Board (SLWRB4161A) +name: EFR32MG12 2.4 GHz 19 dBm Radio Board (SLWRB4161A, BRD4161A) type: mcu arch: arm ram: 256 diff --git a/boards/silabs/radio_boards/slwrb4170a/Kconfig.defconfig b/boards/silabs/radio_boards/slwrb4170a/Kconfig.defconfig index 35a05e59ea5..47f7d487a25 100644 --- a/boards/silabs/radio_boards/slwrb4170a/Kconfig.defconfig +++ b/boards/silabs/radio_boards/slwrb4170a/Kconfig.defconfig @@ -1,5 +1,3 @@ -# EFR32 radio board - # Copyright (c) 2020 Piotr Mienkowski # Copyright (c) 2020 TriaGnoSys GmbH # SPDX-License-Identifier: Apache-2.0 @@ -12,10 +10,6 @@ config CMU_HFXO_FREQ config CMU_LFXO_FREQ default 32768 -config FLASH_BASE_ADDRESS - hex - default 0x0 - config LOG_BACKEND_SWO_FREQ_HZ default 875000 depends on LOG_BACKEND_SWO diff --git a/boards/silabs/radio_boards/slwrb4170a/Kconfig.slwrb4170a b/boards/silabs/radio_boards/slwrb4170a/Kconfig.slwrb4170a index 6ae34218fc3..9934b2dfae6 100644 --- a/boards/silabs/radio_boards/slwrb4170a/Kconfig.slwrb4170a +++ b/boards/silabs/radio_boards/slwrb4170a/Kconfig.slwrb4170a @@ -1,5 +1,3 @@ -# EFR32MG12 BRD4170A - # Copyright (c) 2020 Piotr Mienkowski # Copyright (c) 2020 TriaGnoSys GmbH # SPDX-License-Identifier: Apache-2.0 diff --git a/boards/silabs/radio_boards/slwrb4170a/board.cmake b/boards/silabs/radio_boards/slwrb4170a/board.cmake index be43109892d..b24ae335204 100644 --- a/boards/silabs/radio_boards/slwrb4170a/board.cmake +++ b/boards/silabs/radio_boards/slwrb4170a/board.cmake @@ -1,7 +1,7 @@ # SPDX-License-Identifier: Apache-2.0 -board_runner_args(openocd) board_runner_args(jlink "--device=EFR32MG12PxxxF1024") +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +board_runner_args(openocd) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) -include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/silabs/radio_boards/slwrb4170a/board.yml b/boards/silabs/radio_boards/slwrb4170a/board.yml index 5d9fd340d3e..63a0445c9bb 100644 --- a/boards/silabs/radio_boards/slwrb4170a/board.yml +++ b/boards/silabs/radio_boards/slwrb4170a/board.yml @@ -1,5 +1,6 @@ -boards: - - name: slwrb4170a - full_name: EFR32MG12 2400/868-915 MHz 19 dBm Dual Band (SLWRB4170A) - socs: - - name: efr32mg12p433f1024gm68 +board: + name: slwrb4170a + full_name: EFR32MG12 2400/868-915 MHz 19 dBm Dual Band (SLWRB4170A) + vendor: silabs + socs: + - name: efr32mg12p433f1024gm68 diff --git a/boards/silabs/radio_boards/slwrb4170a/doc/index.rst b/boards/silabs/radio_boards/slwrb4170a/doc/index.rst index ccc2b7248ea..9c96d7ec31e 100644 --- a/boards/silabs/radio_boards/slwrb4170a/doc/index.rst +++ b/boards/silabs/radio_boards/slwrb4170a/doc/index.rst @@ -1,7 +1,4 @@ -.. _slwrb4170a: - -EFR32MG12 2400/868-915 MHz 19 dBm Dual Band (SLWRB4170A) -######################################################## +.. zephyr:board:: slwrb4170a Overview ******** @@ -10,12 +7,6 @@ The EFR32MG12 Mighty Gecko Radio Board contains a Wireless System-On-Chip from the EFR32MG12 family built on an ARM Cortex®-M4F processor with excellent low power capabilities. -.. figure:: efr32mg12-slwrb4170a.jpg - :align: center - :alt: SLWRB4170A Mighty Gecko Radio Board - - SLWRB4170A (image courtesy of Silicon Labs) - The BRD4170A a.k.a. SLWRB4170A radio board plugs into the Wireless Starter Kit Mainboard BRD4001A and is supported as one of :ref:`silabs_radio_boards`. diff --git a/boards/silabs/radio_boards/slwrb4170a/slwrb4170a.yaml b/boards/silabs/radio_boards/slwrb4170a/slwrb4170a.yaml index 754d40f8840..0acb1d782b8 100644 --- a/boards/silabs/radio_boards/slwrb4170a/slwrb4170a.yaml +++ b/boards/silabs/radio_boards/slwrb4170a/slwrb4170a.yaml @@ -1,5 +1,5 @@ identifier: slwrb4170a -name: EFR32MG12 2400/868-915 MHz 19 dBm Dual Band Radio Board (SLWRB4170A) +name: EFR32MG12 2400/868-915 MHz 19 dBm Dual Band Radio Board (SLWRB4170A, BRD4170A) type: mcu arch: arm ram: 256 diff --git a/boards/silabs/radio_boards/slwrb4180a/Kconfig.defconfig b/boards/silabs/radio_boards/slwrb4180a/Kconfig.defconfig index d02170404ff..859089bbdff 100644 --- a/boards/silabs/radio_boards/slwrb4180a/Kconfig.defconfig +++ b/boards/silabs/radio_boards/slwrb4180a/Kconfig.defconfig @@ -1,21 +1,9 @@ -# EFR32 radio board - # Copyright (c) 2020 Piotr Mienkowski # Copyright (c) 2020 TriaGnoSys GmbH # SPDX-License-Identifier: Apache-2.0 if BOARD_SLWRB4180A -config CMU_HFXO_FREQ - default 38400000 - -config CMU_LFXO_FREQ - default 32768 - -config FLASH_BASE_ADDRESS - hex - default 0x0 - config LOG_BACKEND_SWO_FREQ_HZ default 875000 depends on LOG_BACKEND_SWO diff --git a/boards/silabs/radio_boards/slwrb4180a/Kconfig.slwrb4180a b/boards/silabs/radio_boards/slwrb4180a/Kconfig.slwrb4180a index 2e1e6c0fd3e..fe405d5b9ef 100644 --- a/boards/silabs/radio_boards/slwrb4180a/Kconfig.slwrb4180a +++ b/boards/silabs/radio_boards/slwrb4180a/Kconfig.slwrb4180a @@ -1,5 +1,3 @@ -# EFR32MG21 BRD4180A - # Copyright (c) 2020 Piotr Mienkowski # Copyright (c) 2020 TriaGnoSys GmbH # SPDX-License-Identifier: Apache-2.0 diff --git a/boards/silabs/radio_boards/slwrb4180a/board.cmake b/boards/silabs/radio_boards/slwrb4180a/board.cmake index aa7247647d8..70f52255ee6 100644 --- a/boards/silabs/radio_boards/slwrb4180a/board.cmake +++ b/boards/silabs/radio_boards/slwrb4180a/board.cmake @@ -1,7 +1,7 @@ # SPDX-License-Identifier: Apache-2.0 -board_runner_args(openocd) board_runner_args(jlink "--device=EFR32MG21AxxxF1024") +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +board_runner_args(openocd) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) -include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/silabs/radio_boards/slwrb4180a/board.yml b/boards/silabs/radio_boards/slwrb4180a/board.yml index f77ecb3f65b..d5f3955ba86 100644 --- a/boards/silabs/radio_boards/slwrb4180a/board.yml +++ b/boards/silabs/radio_boards/slwrb4180a/board.yml @@ -1,5 +1,6 @@ -boards: - - name: slwrb4180a - full_name: EFR32xG21 2.4 GHz 20 dBm (SLWRB4180A) - socs: - - name: efr32mg21a020f1024im32 +board: + name: slwrb4180a + full_name: EFR32xG21 2.4 GHz 20 dBm (SLWRB4180A) + vendor: silabs + socs: + - name: efr32mg21a020f1024im32 diff --git a/boards/silabs/radio_boards/slwrb4180a/doc/index.rst b/boards/silabs/radio_boards/slwrb4180a/doc/index.rst index 057e8ec9b00..d49a5770e4c 100644 --- a/boards/silabs/radio_boards/slwrb4180a/doc/index.rst +++ b/boards/silabs/radio_boards/slwrb4180a/doc/index.rst @@ -1,7 +1,4 @@ -.. _slwrb4180a: - -EFR32xG21 2.4 GHz 20 dBm (SLWRB4180A) -##################################### +.. zephyr:board:: slwrb4180a Overview ******** @@ -11,12 +8,6 @@ radio boards delivered with `EFR32-SLWSTK6006A Website`_. It contains a Wireless System-On-Chip from the EFR32MG21 family built on an ARM Cortex®-M33F processor with excellent low power capabilities. -.. figure:: efr32mg21-slwrb4180a.jpg - :align: center - :alt: SLWRB4180A Mighty Gecko Radio Board - - SLWRB4180A (image courtesy of Silicon Labs) - The BRD4180A a.k.a. SLWRB4180A radio board plugs into the Wireless Starter Kit Mainboard BRD4001A and is supported as one of :ref:`silabs_radio_boards`. @@ -65,6 +56,8 @@ The board configuration supports the following hardware features: +-----------+------------+-------------------------------------+ | I2C | on-chip | i2c port-polling | +-----------+------------+-------------------------------------+ +| DMA | on-chip | ldma | ++-----------+------------+-------------------------------------+ | WATCHDOG | on-chip | watchdog | +-----------+------------+-------------------------------------+ diff --git a/boards/silabs/radio_boards/slwrb4180a/slwrb4180a-pinctrl.dtsi b/boards/silabs/radio_boards/slwrb4180a/slwrb4180a-pinctrl.dtsi index 74723695d86..146c0861858 100644 --- a/boards/silabs/radio_boards/slwrb4180a/slwrb4180a-pinctrl.dtsi +++ b/boards/silabs/radio_boards/slwrb4180a/slwrb4180a-pinctrl.dtsi @@ -1,18 +1,23 @@ /* * Copyright (c) 2023 Antmicro + * Copyright (c) 2024 Silicon Laboratories Inc. * * SPDX-License-Identifier: Apache-2.0 */ -#include -#include +#include &pinctrl { usart0_default: usart0_default { + group0 { + pins = ; + drive-push-pull; + output-high; + }; group1 { - psels = , - , - ; + pins = ; + input-enable; + silabs,input-filter; }; }; }; diff --git a/boards/silabs/radio_boards/slwrb4180a/slwrb4180a.dts b/boards/silabs/radio_boards/slwrb4180a/slwrb4180a.dts index 9d761504783..48154c0b879 100644 --- a/boards/silabs/radio_boards/slwrb4180a/slwrb4180a.dts +++ b/boards/silabs/radio_boards/slwrb4180a/slwrb4180a.dts @@ -16,6 +16,7 @@ chosen { zephyr,console = &usart0; zephyr,shell-uart = &usart0; + zephyr,uart-pipe = &usart0; zephyr,sram = &sram0; zephyr,flash = &flash0; zephyr,code-partition = &slot0_partition; @@ -61,7 +62,49 @@ }; &cpu0 { - clock-frequency = <38400000>; + clock-frequency = <76800000>; +}; + +&hfxo { + status = "okay"; + ctune = <129>; + precision = <50>; +}; + +&lfxo { + status = "okay"; + ctune = <79>; + precision = <50>; +}; + +&hfrcodpll { + clock-frequency = ; + clocks = <&hfxo>; + dpll-n = <3839>; + dpll-m = <1919>; + dpll-edge = "fall"; + dpll-lock = "phase"; + dpll-autorecover; +}; + +&em23grpaclk { + clocks = <&lfxo>; +}; + +&em4grpaclk { + clocks = <&lfxo>; +}; + +&rtccclk { + clocks = <&lfxo>; +}; + +&wdog0clk { + clocks = <&lfxo>; +}; + +&wdog1clk { + clocks = <&lfxo>; }; &usart0 { diff --git a/boards/silabs/radio_boards/slwrb4180a/slwrb4180a.yaml b/boards/silabs/radio_boards/slwrb4180a/slwrb4180a.yaml index ae9d5b7f2b8..580908453da 100644 --- a/boards/silabs/radio_boards/slwrb4180a/slwrb4180a.yaml +++ b/boards/silabs/radio_boards/slwrb4180a/slwrb4180a.yaml @@ -1,5 +1,5 @@ identifier: slwrb4180a -name: EFR32xG21 2.4 GHz 20 dBm Radio Board (SLWRB4180A) +name: EFR32xG21 2.4 GHz 20 dBm Radio Board (SLWRB4180A, BRD4180A) type: mcu arch: arm ram: 96 @@ -13,6 +13,7 @@ supported: - gpio - nvs - uart + - dma - watchdog testing: ignore_tags: diff --git a/boards/silabs/radio_boards/slwrb4180a/slwrb4180a_defconfig b/boards/silabs/radio_boards/slwrb4180a/slwrb4180a_defconfig index 053f12a36f4..e70f8f5c519 100644 --- a/boards/silabs/radio_boards/slwrb4180a/slwrb4180a_defconfig +++ b/boards/silabs/radio_boards/slwrb4180a/slwrb4180a_defconfig @@ -5,6 +5,3 @@ CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y CONFIG_GPIO=y -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=38400000 -CONFIG_CMU_HFCLK_HFXO=y -CONFIG_PINCTRL=y diff --git a/boards/silabs/radio_boards/slwrb4250b/Kconfig.defconfig b/boards/silabs/radio_boards/slwrb4250b/Kconfig.defconfig index 1fb66afb871..3ac04f0f671 100644 --- a/boards/silabs/radio_boards/slwrb4250b/Kconfig.defconfig +++ b/boards/silabs/radio_boards/slwrb4250b/Kconfig.defconfig @@ -1,5 +1,3 @@ -# EFR32 radio board - # Copyright (c) 2020 Piotr Mienkowski # Copyright (c) 2020 TriaGnoSys GmbH # SPDX-License-Identifier: Apache-2.0 @@ -12,10 +10,6 @@ config CMU_HFXO_FREQ config CMU_LFXO_FREQ default 32768 -config FLASH_BASE_ADDRESS - hex - default 0x0 - config LOG_BACKEND_SWO_FREQ_HZ default 875000 depends on LOG_BACKEND_SWO diff --git a/boards/silabs/radio_boards/slwrb4250b/Kconfig.slwrb4250b b/boards/silabs/radio_boards/slwrb4250b/Kconfig.slwrb4250b index bab71ba23c9..8b2b4d9dc7a 100644 --- a/boards/silabs/radio_boards/slwrb4250b/Kconfig.slwrb4250b +++ b/boards/silabs/radio_boards/slwrb4250b/Kconfig.slwrb4250b @@ -1,5 +1,3 @@ -# EFR32FG1P BRD4250B - # Copyright (c) 2020 Piotr Mienkowski # Copyright (c) 2020 TriaGnoSys GmbH # SPDX-License-Identifier: Apache-2.0 diff --git a/boards/silabs/radio_boards/slwrb4250b/board.cmake b/boards/silabs/radio_boards/slwrb4250b/board.cmake index a17aad7a895..7babe79c8c0 100644 --- a/boards/silabs/radio_boards/slwrb4250b/board.cmake +++ b/boards/silabs/radio_boards/slwrb4250b/board.cmake @@ -1,7 +1,7 @@ # SPDX-License-Identifier: Apache-2.0 board_runner_args(openocd) -board_runner_args(jlink "--device=EFR32FG1PxxxF256") - include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) + +board_runner_args(jlink "--device=EFR32FG1PxxxF256") include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/silabs/radio_boards/slwrb4250b/board.yml b/boards/silabs/radio_boards/slwrb4250b/board.yml index 052b39f83c3..63de8182fbd 100644 --- a/boards/silabs/radio_boards/slwrb4250b/board.yml +++ b/boards/silabs/radio_boards/slwrb4250b/board.yml @@ -1,5 +1,6 @@ -boards: - - name: slwrb4250b - full_name: EFR32FG1 2400/868 MHz 13 dBm Dual Band (SLWRB4250B) - socs: - - name: efr32fg1p133f256gm48 +board: + name: slwrb4250b + full_name: EFR32FG1 2400/868 MHz 13 dBm Dual Band (SLWRB4250B) + vendor: silabs + socs: + - name: efr32fg1p133f256gm48 diff --git a/boards/silabs/radio_boards/slwrb4250b/doc/index.rst b/boards/silabs/radio_boards/slwrb4250b/doc/index.rst index 7a865b5b573..57a26c65cbf 100644 --- a/boards/silabs/radio_boards/slwrb4250b/doc/index.rst +++ b/boards/silabs/radio_boards/slwrb4250b/doc/index.rst @@ -1,7 +1,4 @@ -.. _slwrb4250b: - -EFR32FG1 2400/868 MHz 13 dBm Dual Band (SLWRB4250B) -################################################### +.. zephyr:board:: slwrb4250b Overview ******** @@ -10,12 +7,6 @@ The EFR32FG1 Flex Gecko 2.4 GHz and 868 MHz Radio Board is delivered as part of `SLWSTK6061B Proprietary Wireless Starter Kit`_. It contains a EFR32FG1 Wireless SoC built on an ARM Cortex®-M4F processor with excellent low power capabilities. -.. figure:: efr32fg1-slwrb4250b.jpg - :align: center - :alt: SLWRB4250B Flex Gecko 2.4 GHz and 868 MHz Radio Board - - SLWRB4250B (image courtesy of Silicon Labs) - The BRD4250B a.k.a. SLWRB4250B radio board plugs into the Wireless Starter Kit Mainboard BRD4001A and is supported as one of :ref:`silabs_radio_boards`. diff --git a/boards/silabs/radio_boards/slwrb4250b/slwrb4250b.yaml b/boards/silabs/radio_boards/slwrb4250b/slwrb4250b.yaml index 8f54bc21752..699eaf13971 100644 --- a/boards/silabs/radio_boards/slwrb4250b/slwrb4250b.yaml +++ b/boards/silabs/radio_boards/slwrb4250b/slwrb4250b.yaml @@ -1,5 +1,5 @@ identifier: slwrb4250b -name: EFR32FG 2400/868 MHz 13 dBm Dual Band Radio Board (SLWRB4250B) +name: EFR32FG 2400/868 MHz 13 dBm Dual Band Radio Board (SLWRB4250B, BRD4250B) type: mcu arch: arm ram: 32 diff --git a/boards/silabs/radio_boards/slwrb4255a/Kconfig.defconfig b/boards/silabs/radio_boards/slwrb4255a/Kconfig.defconfig index 70528d489b4..ffc370954f5 100644 --- a/boards/silabs/radio_boards/slwrb4255a/Kconfig.defconfig +++ b/boards/silabs/radio_boards/slwrb4255a/Kconfig.defconfig @@ -1,5 +1,3 @@ -# EFR32 radio board - # Copyright (c) 2020 Piotr Mienkowski # Copyright (c) 2020 TriaGnoSys GmbH # SPDX-License-Identifier: Apache-2.0 @@ -12,10 +10,6 @@ config CMU_HFXO_FREQ config CMU_LFXO_FREQ default 32768 -config FLASH_BASE_ADDRESS - hex - default 0x0 - config LOG_BACKEND_SWO_FREQ_HZ default 875000 depends on LOG_BACKEND_SWO diff --git a/boards/silabs/radio_boards/slwrb4255a/Kconfig.slwrb4255a b/boards/silabs/radio_boards/slwrb4255a/Kconfig.slwrb4255a index 6f95623eb75..2890e54f940 100644 --- a/boards/silabs/radio_boards/slwrb4255a/Kconfig.slwrb4255a +++ b/boards/silabs/radio_boards/slwrb4255a/Kconfig.slwrb4255a @@ -1,5 +1,3 @@ -# EFR32FG13P BRD4255A board - # Copyright (c) 2020 Piotr Mienkowski # Copyright (c) 2020 TriaGnoSys GmbH # SPDX-License-Identifier: Apache-2.0 diff --git a/boards/silabs/radio_boards/slwrb4255a/board.cmake b/boards/silabs/radio_boards/slwrb4255a/board.cmake index 7e93e543d55..cff49d797c5 100644 --- a/boards/silabs/radio_boards/slwrb4255a/board.cmake +++ b/boards/silabs/radio_boards/slwrb4255a/board.cmake @@ -1,7 +1,7 @@ # SPDX-License-Identifier: Apache-2.0 -board_runner_args(openocd) board_runner_args(jlink "--device=EFR32FG13PxxxF512") +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +board_runner_args(openocd) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) -include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/silabs/radio_boards/slwrb4255a/board.yml b/boards/silabs/radio_boards/slwrb4255a/board.yml index 841a0858e13..b6740ec9685 100644 --- a/boards/silabs/radio_boards/slwrb4255a/board.yml +++ b/boards/silabs/radio_boards/slwrb4255a/board.yml @@ -1,5 +1,6 @@ -boards: - - name: slwrb4255a - full_name: EFR32FG13 2400/915 MHz 19 dBm Dual Band (SLWRB4255A) - socs: - - name: efr32fg13p233f512gm48 +board: + name: slwrb4255a + full_name: EFR32FG13 2400/915 MHz 19 dBm Dual Band (SLWRB4255A) + vendor: silabs + socs: + - name: efr32fg13p233f512gm48 diff --git a/boards/silabs/radio_boards/slwrb4255a/doc/index.rst b/boards/silabs/radio_boards/slwrb4255a/doc/index.rst index 43dd6e65aad..47cb5a15fbb 100644 --- a/boards/silabs/radio_boards/slwrb4255a/doc/index.rst +++ b/boards/silabs/radio_boards/slwrb4255a/doc/index.rst @@ -1,7 +1,4 @@ -.. _slwrb4255a: - -EFR32FG13 2400/915 MHz 19 dBm Dual Band (SLWRB4255A) -#################################################### +.. zephyr:board:: slwrb4255a Overview ******** @@ -10,12 +7,6 @@ The EFR32FG13P Flex Gecko 2.4 GHz and 915 MHz Radio Board is delivered as a `standalone Proprietary Wireless radio board`_. It contains a EFR32FG13P Wireless SoC built on an ARM Cortex®-M4F processor with excellent low power capabilities. -.. figure:: efr32fg13-slwrb4255a.jpg - :align: center - :alt: SLWRB4255A Flex Gecko 2.4 GHz and 915 MHz Radio Board - - SLWRB4255A (image courtesy of Silicon Labs) - The BRD4255A a.k.a. SLWRB4255A radio board plugs into the Wireless Starter Kit Mainboard BRD4001A and is supported as one of :ref:`silabs_radio_boards`. @@ -67,7 +58,7 @@ The board configuration supports the following hardware features: +-----------+------------+-------------------------------------+ The default configuration can be found in -:zephyr_file:`boards/silabs/radio_boards/slwrb4255/slwrb4255_defconfig` +:zephyr_file:`boards/silabs/radio_boards/slwrb4255a/slwrb4255a_defconfig` Connections and IOs =================== diff --git a/boards/silabs/radio_boards/slwrb4255a/slwrb4255a.yaml b/boards/silabs/radio_boards/slwrb4255a/slwrb4255a.yaml index e1d6718fbce..2e5a295ff8e 100644 --- a/boards/silabs/radio_boards/slwrb4255a/slwrb4255a.yaml +++ b/boards/silabs/radio_boards/slwrb4255a/slwrb4255a.yaml @@ -1,5 +1,5 @@ identifier: slwrb4255a -name: EFR32FG13 2400/915 MHz 19 dBm Dual Band Radio Board (SLWRB4255A) +name: EFR32FG13 2400/915 MHz 19 dBm Dual Band Radio Board (SLWRB4255A, BRD4255A) type: mcu arch: arm ram: 64 diff --git a/boards/silabs/radio_boards/slwrb4321a/Kconfig.defconfig b/boards/silabs/radio_boards/slwrb4321a/Kconfig.defconfig index 63ff16bbad6..f70d82cdd63 100644 --- a/boards/silabs/radio_boards/slwrb4321a/Kconfig.defconfig +++ b/boards/silabs/radio_boards/slwrb4321a/Kconfig.defconfig @@ -1,4 +1,3 @@ -# EFM32GG SLWSTK6121A default board configuration # Copyright (c) 2019 Interay Solutions B.V. # Copyright (c) 2019 Oane Kingma # Copyright (c) 2020 Thorvald Natvig diff --git a/boards/silabs/radio_boards/slwrb4321a/Kconfig.slwrb4321a b/boards/silabs/radio_boards/slwrb4321a/Kconfig.slwrb4321a index 1ce37ed6446..567135f6bce 100644 --- a/boards/silabs/radio_boards/slwrb4321a/Kconfig.slwrb4321a +++ b/boards/silabs/radio_boards/slwrb4321a/Kconfig.slwrb4321a @@ -1,4 +1,3 @@ -# EFM32GG11 SLWRB4321A board configuration # Copyright (c) 2019 Interay Solutions B.V. # Copyright (c) 2019 Oane Kingma # Copyright (c) 2020 Thorvald Natvig diff --git a/boards/silabs/radio_boards/slwrb4321a/board.cmake b/boards/silabs/radio_boards/slwrb4321a/board.cmake index 0f0250335b6..5a929fe6094 100644 --- a/boards/silabs/radio_boards/slwrb4321a/board.cmake +++ b/boards/silabs/radio_boards/slwrb4321a/board.cmake @@ -4,7 +4,7 @@ # SPDX-License-Identifier: Apache-2.0 board_runner_args(jlink "--device=EFM32GG11B820F2048") -board_runner_args(openocd) - include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) + +board_runner_args(openocd) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/silabs/radio_boards/slwrb4321a/doc/index.rst b/boards/silabs/radio_boards/slwrb4321a/doc/index.rst index 50ec07b7f79..ccd82c5387e 100644 --- a/boards/silabs/radio_boards/slwrb4321a/doc/index.rst +++ b/boards/silabs/radio_boards/slwrb4321a/doc/index.rst @@ -1,7 +1,4 @@ -.. _slwrb4321a: - -WGM160P Wi-Fi Module (SLWRB4321A) -################################# +.. zephyr:board:: slwrb4321a Overview ******** @@ -10,12 +7,6 @@ The WGM160P Starter Kit SLWSTK6121A comes with the BRD4321A radio board. This radio boards contains a WGM160P module, which combines the WF200 Wi-Fi transceiver with an EFM32GG11 microcontroller. -.. figure:: wgm160p-starter-kit.jpg - :align: center - :alt: SLWSTK6121A - - SLWSTK6121A (image courtesy of Silicon Labs) - Hardware ******** @@ -69,7 +60,7 @@ features: +-----------+------------+-------------------------------------+ The default configuration can be found in -:zephyr_file:`boards/silabs/slwrb4321a/slwrb4321a_defconfig` +:zephyr_file:`boards/silabs/radio_boards/slwrb4321a/slwrb4321a_defconfig` Other hardware features, including the WF200 WiFi transceiver, are currently not supported by the port. @@ -121,7 +112,7 @@ Programming and Debugging .. note:: Before using the kit the first time, you should update the J-Link firmware - from `J-Link-Downloads`_ + in Simplicity Studio. Flashing ======== @@ -181,6 +172,3 @@ terminal session: .. _J-Link: https://www.segger.com/jlink-debug-probes.html - -.. _J-Link-Downloads: - https://www.segger.com/downloads/jlink diff --git a/boards/silabs/radio_boards/slwrb4321a/slwrb4321a.dts b/boards/silabs/radio_boards/slwrb4321a/slwrb4321a.dts index 4dfff28a2dc..a778fbfb180 100644 --- a/boards/silabs/radio_boards/slwrb4321a/slwrb4321a.dts +++ b/boards/silabs/radio_boards/slwrb4321a/slwrb4321a.dts @@ -18,6 +18,7 @@ chosen { zephyr,console = &usart0; zephyr,shell-uart = &usart0; + zephyr,uart-pipe = &usart0; zephyr,sram = &sram0; zephyr,flash = &flash0; }; diff --git a/boards/silabs/radio_boards/slwrb4321a/slwrb4321a.yaml b/boards/silabs/radio_boards/slwrb4321a/slwrb4321a.yaml index 7b61761886f..b6f05256c98 100644 --- a/boards/silabs/radio_boards/slwrb4321a/slwrb4321a.yaml +++ b/boards/silabs/radio_boards/slwrb4321a/slwrb4321a.yaml @@ -1,5 +1,5 @@ identifier: slwrb4321a -name: WGM160P Wi-Fi Module Radio Board (SLWRB4321A) +name: WGM160P Wi-Fi Module Radio Board (SLWRB4321A, BRD4321A) type: mcu arch: arm ram: 512 diff --git a/boards/silabs/radio_boards/xg23_rb4210a/Kconfig.defconfig b/boards/silabs/radio_boards/xg23_rb4210a/Kconfig.defconfig new file mode 100644 index 00000000000..74411aa5622 --- /dev/null +++ b/boards/silabs/radio_boards/xg23_rb4210a/Kconfig.defconfig @@ -0,0 +1,17 @@ +# Copyright (c) 2024 Yishai Jaffe +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_XG23_RB4210A + +config LOG_BACKEND_SWO_FREQ_HZ + default 875000 + depends on LOG_BACKEND_SWO + +if SOC_GECKO_USE_RAIL + +config FPU + default y + +endif # SOC_GECKO_USE_RAIL + +endif # BOARD_XG23_RB4210A diff --git a/boards/silabs/radio_boards/xg23_rb4210a/Kconfig.xg23_rb4210a b/boards/silabs/radio_boards/xg23_rb4210a/Kconfig.xg23_rb4210a new file mode 100644 index 00000000000..cec62787ad5 --- /dev/null +++ b/boards/silabs/radio_boards/xg23_rb4210a/Kconfig.xg23_rb4210a @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Yishai Jaffe +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_XG23_RB4210A + select SOC_PART_NUMBER_EFR32ZG23B020F512IM48 diff --git a/boards/silabs/radio_boards/xg23_rb4210a/board.cmake b/boards/silabs/radio_boards/xg23_rb4210a/board.cmake new file mode 100644 index 00000000000..7cbad4e887b --- /dev/null +++ b/boards/silabs/radio_boards/xg23_rb4210a/board.cmake @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=EFR32ZG23BxxxF512") +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) + +board_runner_args(openocd) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) + +board_runner_args(silabs_commander "--device=EFR32ZG23B020F512IM48") +include(${ZEPHYR_BASE}/boards/common/silabs_commander.board.cmake) diff --git a/boards/silabs/radio_boards/xg23_rb4210a/board.yml b/boards/silabs/radio_boards/xg23_rb4210a/board.yml new file mode 100644 index 00000000000..42d6b9ff707 --- /dev/null +++ b/boards/silabs/radio_boards/xg23_rb4210a/board.yml @@ -0,0 +1,6 @@ +board: + name: xg23_rb4210a + full_name: EFR32xG23 868-915 MHz 20 dBm (xG23-RB4210A) + vendor: silabs + socs: + - name: efr32zg23b020f512im48 diff --git a/boards/silabs/radio_boards/xg23_rb4210a/doc/efr32zg23-xg23-rb4210a.jpg b/boards/silabs/radio_boards/xg23_rb4210a/doc/efr32zg23-xg23-rb4210a.jpg new file mode 100644 index 00000000000..904a9ae03ac Binary files /dev/null and b/boards/silabs/radio_boards/xg23_rb4210a/doc/efr32zg23-xg23-rb4210a.jpg differ diff --git a/boards/silabs/radio_boards/xg23_rb4210a/doc/index.rst b/boards/silabs/radio_boards/xg23_rb4210a/doc/index.rst new file mode 100644 index 00000000000..153ef502a7c --- /dev/null +++ b/boards/silabs/radio_boards/xg23_rb4210a/doc/index.rst @@ -0,0 +1,152 @@ +.. zephyr:board:: xg23_rb4210a + +Overview +******** + +The EFR32ZG23 Radio Board is the radio board delivered with +`xG23-PK6068A Website`_. It contains a Wireless System-On-Chip from the +EFR32ZG23 family built on an ARM Cortex®-M33 processor with excellent low +power capabilities. + +The BRD4210A a.k.a. xG23-RB4210A radio board plugs into the Wireless Pro Kit +Mainboard BRD4002A and is supported as one of :ref:`silabs_radio_boards`. + +Hardware +******** + +- EFR32ZG23B020F512IM48 SoC +- CPU core: ARM Cortex®-M33 with FPU +- Flash memory: 512 kB +- RAM: 64 kB +- Transmit power: up to +20 dBm +- Operation frequency: 868-915 MHz +- Crystals for LFXO (32.768 kHz) and HFXO (39 MHz). + +For more information about the EFR32ZG23 SoC and BRD4210A board, refer to these +documents: + +- `EFR32ZG23 Website`_ +- `EFR32ZG23 Datasheet`_ +- `EFR32xG23 Reference Manual`_ +- `xG23-PK6068A Website`_ +- `BRD4210A User Guide`_ + +Supported Features +================== + +The board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| MPU | on-chip | memory protection unit | ++-----------+------------+-------------------------------------+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| COUNTER | on-chip | stimer | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial | ++-----------+------------+-------------------------------------+ +| DMA | on-chip | ldma | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| TRNG | on-chip | semailbox | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | watchdog | ++-----------+------------+-------------------------------------+ + +Other hardware features are currently not supported by the port. + +Connections and IOs +=================== + +In the following table, the column **Name** contains Pin names. For example, PA2 +means Pin number 2 on PORTA, as used in the board's datasheets and manuals. + ++-------+-------------+-------------------------------------+ +| Name | Function | Usage | ++=======+=============+=====================================+ +| PB2 | GPIO | LED0 | ++-------+-------------+-------------------------------------+ +| PD3 | GPIO | LED1 | ++-------+-------------+-------------------------------------+ +| PB1 | GPIO | Push Button 0 | ++-------+-------------+-------------------------------------+ +| PB3 | GPIO | Push Button 1 | ++-------+-------------+-------------------------------------+ +| PB0 | GPIO | Board Controller Enable | +| | | VCOM_ENABLE | ++-------+-------------+-------------------------------------+ +| PA8 | USART0_TX | UART Console VCOM_TX US0_TX | ++-------+-------------+-------------------------------------+ +| PA9 | USART0_RX | UART Console VCOM_RX US0_RX | ++-------+-------------+-------------------------------------+ + +The default configuration can be found in +:zephyr_file:`boards/silabs/radio_boards/xg23_rb4210a/xg23_rb4210a_defconfig` + +System Clock +============ + +The EFR32ZG23 SoC is configured to use the 39 MHz external oscillator on the +board. + +Serial Port +=========== + +The EFR32ZG23 SoC has one USART and three EUSARTs. +USART0 is connected to the board controller and is used for the console. + +Programming and Debugging +************************* + +Flashing +======== + +Connect the BRD4002A board with a mounted BRD4210A radio module to your host +computer using the USB port. + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: xg23_rb4210a + :goals: flash + +Open a serial terminal (minicom, putty, etc.) with the following settings: + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Reset the board and you should see the following message in the terminal: + +.. code-block:: console + + Hello World! xg23_rb4210a/efr32zg23b020f512im48 + + +.. _xG23-PK6068A Website: + https://www.silabs.com/development-tools/wireless/efr32xg23-pro-kit-20-dbm + +.. _BRD4210A User Guide: + https://www.silabs.com/documents/public/user-guides/ug507-brd4210a-user-guide.pdf + +.. _EFR32ZG23 Website: + https://www.silabs.com/wireless/z-wave/800-series-modem-soc + +.. _EFR32ZG23 Datasheet: + https://www.silabs.com/documents/public/data-sheets/efr32zg23-datasheet.pdf + +.. _EFR32xG23 Reference Manual: + https://www.silabs.com/documents/public/reference-manuals/efr32xg23-rm.pdf diff --git a/boards/silabs/radio_boards/xg23_rb4210a/pre_dt_board.cmake b/boards/silabs/radio_boards/xg23_rb4210a/pre_dt_board.cmake new file mode 100644 index 00000000000..beb76b85552 --- /dev/null +++ b/boards/silabs/radio_boards/xg23_rb4210a/pre_dt_board.cmake @@ -0,0 +1,5 @@ +# Copyright (c) 2021 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +# SPI is implemented via usart so node name isn't spi@... +list(APPEND EXTRA_DTC_FLAGS "-Wno-spi_bus_bridge") diff --git a/boards/silabs/radio_boards/xg23_rb4210a/support/openocd.cfg b/boards/silabs/radio_boards/xg23_rb4210a/support/openocd.cfg new file mode 100644 index 00000000000..38409eb70ad --- /dev/null +++ b/boards/silabs/radio_boards/xg23_rb4210a/support/openocd.cfg @@ -0,0 +1,25 @@ +if {[info exists env(OPENOCD_INTERFACE)]} { + set INTERFACE $env(OPENOCD_INTERFACE) +} else { + # By default connect over Debug USB port using the J-Link interface + set INTERFACE "jlink" +} + +source [find interface/$INTERFACE.cfg] + +transport select swd + +set CHIPNAME efr32 + +source [find target/efm32.cfg] + +$_TARGETNAME configure -event gdb-attach { + echo "Debugger attaching: halting execution" + reset halt + gdb_breakpoint_override hard +} + +$_TARGETNAME configure -event gdb-detach { + echo "Debugger detaching: resuming execution" + resume +} diff --git a/boards/silabs/radio_boards/xg23_rb4210a/xg23_rb4210a-pinctrl.dtsi b/boards/silabs/radio_boards/xg23_rb4210a/xg23_rb4210a-pinctrl.dtsi new file mode 100644 index 00000000000..9b7f1b02c58 --- /dev/null +++ b/boards/silabs/radio_boards/xg23_rb4210a/xg23_rb4210a-pinctrl.dtsi @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2024 Yishai Jaffe + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + usart0_default: usart0_default { + group0 { + pins = ; + drive-push-pull; + output-high; + }; + group1 { + pins = ; + input-enable; + silabs,input-filter; + }; + }; +}; diff --git a/boards/silabs/radio_boards/xg23_rb4210a/xg23_rb4210a.dts b/boards/silabs/radio_boards/xg23_rb4210a/xg23_rb4210a.dts new file mode 100644 index 00000000000..c5800aeb520 --- /dev/null +++ b/boards/silabs/radio_boards/xg23_rb4210a/xg23_rb4210a.dts @@ -0,0 +1,201 @@ +/* + * Copyright (c) 2024 Yishai Jaffe + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include +#include "xg23_rb4210a-pinctrl.dtsi" + +/ { + model = "Silicon Labs BRD4210A"; + compatible = "silabs,xg23_rb4210a", "silabs,efr32zg23"; + + chosen { + zephyr,console = &usart0; + zephyr,shell-uart = &usart0; + zephyr,uart-pipe = &usart0; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + }; + + aliases { + led0 = &led0; + led1 = &led1; + sw0 = &button0; + sw1 = &button1; + watchdog0 = &wdog0; + }; + + leds { + compatible = "gpio-leds"; + led0: led_0 { + gpios = <&gpiob 2 GPIO_ACTIVE_HIGH>; + label = "LED 0"; + }; + led1: led_1 { + gpios = <&gpiod 3 GPIO_ACTIVE_HIGH>; + label = "LED 1"; + }; + }; + + buttons { + compatible = "gpio-keys"; + button0: button_0 { + gpios = <&gpiob 1 GPIO_ACTIVE_LOW>; + label = "User Push Button 0"; + zephyr,code = ; + }; + button1: button_1 { + gpios = <&gpiob 3 GPIO_ACTIVE_LOW>; + label = "User Push Button 1"; + zephyr,code = ; + }; + }; + +}; + +&cpu0 { + clock-frequency = <78000000>; +}; + +&pstate_em3 { + status = "disabled"; +}; + +&hfxo { + status = "okay"; + ctune = <106>; + precision = <50>; +}; + +&lfxo { + status = "okay"; + ctune = <38>; + precision = <50>; +}; + +&hfrcodpll { + clock-frequency = ; + clocks = <&hfxo>; + dpll-n = <3839>; + dpll-m = <1919>; + dpll-edge = "fall"; + dpll-lock = "phase"; + dpll-autorecover; +}; + +&em23grpaclk { + clocks = <&lfxo>; +}; + +&em4grpaclk { + clocks = <&lfxo>; +}; + +&sysrtcclk { + clocks = <&lfxo>; +}; + +&wdog0clk { + clocks = <&lfxo>; +}; + +&wdog1clk { + clocks = <&lfxo>; +}; + +&usart0 { + current-speed = <115200>; + pinctrl-0 = <&usart0_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&gpio { + status = "okay"; +}; + +&gpioa { + status = "okay"; +}; + +&gpiob { + status = "okay"; + + board-controller-enable { + gpio-hog; + gpios = <0 GPIO_ACTIVE_HIGH>; + output-high; + }; +}; + +&gpioc { + status = "okay"; +}; + +&gpiod { + status = "okay"; +}; + +&wdog0 { + status = "okay"; +}; + +&sysrtc0 { + status = "okay"; +}; + +&se { + status = "okay"; +}; + +&dcdc { + status = "okay"; + regulator-boot-on; + regulator-initial-mode = ; + silabs,pfmx-peak-current-milliamp = <80>; +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 48 kB for the bootloader */ + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x0 DT_SIZE_K(48)>; + read-only; + }; + + /* Reserve 208 kB for the application in slot 0 */ + slot0_partition: partition@c000 { + label = "image-0"; + reg = <0x0000c000 DT_SIZE_K(208)>; + }; + + /* Reserve 208 kB for the application in slot 1 */ + slot1_partition: partition@40000 { + label = "image-1"; + reg = <0x00040000 DT_SIZE_K(208)>; + }; + + /* Reserve 32 kB for the scratch partition */ + scratch_partition: partition@74000 { + label = "image-scratch"; + reg = <0x00074000 DT_SIZE_K(32)>; + }; + + /* Set 16 kB of storage at the end of the 1536 kB of flash */ + storage_partition: partition@7c000 { + label = "storage"; + reg = <0x0007c000 DT_SIZE_K(16)>; + }; + }; +}; diff --git a/boards/silabs/radio_boards/xg23_rb4210a/xg23_rb4210a.yaml b/boards/silabs/radio_boards/xg23_rb4210a/xg23_rb4210a.yaml new file mode 100644 index 00000000000..a9229ef60b1 --- /dev/null +++ b/boards/silabs/radio_boards/xg23_rb4210a/xg23_rb4210a.yaml @@ -0,0 +1,27 @@ +identifier: xg23_rb4210a +name: EFR32xG23 868-915 MHz 20 dBm Radio Board (xG23-RB4210A, BRD4210A) +type: mcu +arch: arm +ram: 64 +flash: 512 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - clock_control + - counter + - entropy + - flash + - gpio + - i2c + - led + - pinctrl + - spi + - uart + - dma + - watchdog +testing: + ignore_tags: + - pm +vendor: silabs diff --git a/boards/silabs/radio_boards/xg23_rb4210a/xg23_rb4210a_defconfig b/boards/silabs/radio_boards/xg23_rb4210a/xg23_rb4210a_defconfig new file mode 100644 index 00000000000..d937f7c3052 --- /dev/null +++ b/boards/silabs/radio_boards/xg23_rb4210a/xg23_rb4210a_defconfig @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARM_MPU=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_GPIO=y +CONFIG_SOC_GECKO_EMU_DCDC=y +CONFIG_SOC_GECKO_EMU_DCDC_MODE_ON=y diff --git a/boards/silabs/radio_boards/xg24_rb4187c/Kconfig.defconfig b/boards/silabs/radio_boards/xg24_rb4187c/Kconfig.defconfig index 05899cfebc2..da434eb55ed 100644 --- a/boards/silabs/radio_boards/xg24_rb4187c/Kconfig.defconfig +++ b/boards/silabs/radio_boards/xg24_rb4187c/Kconfig.defconfig @@ -1,21 +1,9 @@ -# EFR32 radio board - # Copyright (c) 2020 Piotr Mienkowski # Copyright (c) 2020 TriaGnoSys GmbH # SPDX-License-Identifier: Apache-2.0 if BOARD_XG24_RB4187C -config CMU_HFXO_FREQ - default 39000000 - -config CMU_LFXO_FREQ - default 32768 - -config FLASH_BASE_ADDRESS - hex - default 0x08000000 - config LOG_BACKEND_SWO_FREQ_HZ default 875000 depends on LOG_BACKEND_SWO diff --git a/boards/silabs/radio_boards/xg24_rb4187c/Kconfig.xg24_rb4187c b/boards/silabs/radio_boards/xg24_rb4187c/Kconfig.xg24_rb4187c index 7d51709ba49..df7ae2c6a4d 100644 --- a/boards/silabs/radio_boards/xg24_rb4187c/Kconfig.xg24_rb4187c +++ b/boards/silabs/radio_boards/xg24_rb4187c/Kconfig.xg24_rb4187c @@ -1,5 +1,3 @@ -# EFR32MG24 BRD4187C - # Copyright (c) 2020 Piotr Mienkowski # Copyright (c) 2020 TriaGnoSys GmbH # SPDX-License-Identifier: Apache-2.0 diff --git a/boards/silabs/radio_boards/xg24_rb4187c/board.cmake b/boards/silabs/radio_boards/xg24_rb4187c/board.cmake index a6187e28f0f..9daf13bb39a 100644 --- a/boards/silabs/radio_boards/xg24_rb4187c/board.cmake +++ b/boards/silabs/radio_boards/xg24_rb4187c/board.cmake @@ -1,7 +1,7 @@ # SPDX-License-Identifier: Apache-2.0 -board_runner_args(openocd) board_runner_args(jlink "--device=EFR32MG24BxxxF1536") +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +board_runner_args(openocd) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) -include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/silabs/radio_boards/xg24_rb4187c/board.yml b/boards/silabs/radio_boards/xg24_rb4187c/board.yml index 36457142237..d4254a0c42d 100644 --- a/boards/silabs/radio_boards/xg24_rb4187c/board.yml +++ b/boards/silabs/radio_boards/xg24_rb4187c/board.yml @@ -1,5 +1,6 @@ -boards: - - name: xg24_rb4187c - full_name: EFR32xG24 2.4 GHz 20 dBm (xG24-RB4187C) - socs: - - name: efr32mg24b220f1536im48 +board: + name: xg24_rb4187c + full_name: EFR32xG24 2.4 GHz 20 dBm (xG24-RB4187C) + vendor: silabs + socs: + - name: efr32mg24b220f1536im48 diff --git a/boards/silabs/radio_boards/xg24_rb4187c/doc/index.rst b/boards/silabs/radio_boards/xg24_rb4187c/doc/index.rst index 82da55861ce..f104714f2b3 100644 --- a/boards/silabs/radio_boards/xg24_rb4187c/doc/index.rst +++ b/boards/silabs/radio_boards/xg24_rb4187c/doc/index.rst @@ -1,7 +1,4 @@ -.. _xg24_rb4187c: - -EFR32xG24 2.4 GHz 20 dBm (xG24-RB4187C) -####################################### +.. zephyr:board:: xg24_rb4187c Overview ******** @@ -11,12 +8,6 @@ radio boards delivered with `xG24-PK6010A Website`_. It contains a Wireless System-On-Chip from the EFR32MG24 family built on an ARM Cortex®-M33F processor with excellent low power capabilities. -.. figure:: efr32mg24-xg24-rb4187c.jpg - :align: center - :alt: xG24-RB4187C Mighty Gecko Radio Board - - xG24-RB4187C (image courtesy of Silicon Labs) - The BRD4187C a.k.a. xG24-RB4187C radio board plugs into the Wireless Pro Kit Mainboard BRD4002A and is supported as one of :ref:`silabs_radio_boards`. @@ -62,6 +53,8 @@ The board configuration supports the following hardware features: +-----------+------------+-------------------------------------+ | UART | on-chip | serial | +-----------+------------+-------------------------------------+ +| DMA | on-chip | ldma | ++-----------+------------+-------------------------------------+ | I2C | on-chip | i2c | +-----------+------------+-------------------------------------+ | TRNG | on-chip | semailbox | diff --git a/boards/silabs/radio_boards/xg24_rb4187c/xg24_rb4187c-pinctrl.dtsi b/boards/silabs/radio_boards/xg24_rb4187c/xg24_rb4187c-pinctrl.dtsi index 0ea520ce13f..75e9112e69c 100644 --- a/boards/silabs/radio_boards/xg24_rb4187c/xg24_rb4187c-pinctrl.dtsi +++ b/boards/silabs/radio_boards/xg24_rb4187c/xg24_rb4187c-pinctrl.dtsi @@ -4,15 +4,19 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include -#include +#include &pinctrl { usart0_default: usart0_default { + group0 { + pins = ; + drive-push-pull; + output-high; + }; group1 { - psels = , - , - ; + pins = ; + input-enable; + silabs,input-filter; }; }; }; diff --git a/boards/silabs/radio_boards/xg24_rb4187c/xg24_rb4187c.dts b/boards/silabs/radio_boards/xg24_rb4187c/xg24_rb4187c.dts index 21a487e758f..819ed7cd800 100644 --- a/boards/silabs/radio_boards/xg24_rb4187c/xg24_rb4187c.dts +++ b/boards/silabs/radio_boards/xg24_rb4187c/xg24_rb4187c.dts @@ -7,6 +7,7 @@ /dts-v1/; #include #include +#include #include "xg24_rb4187c-pinctrl.dtsi" / { @@ -16,6 +17,7 @@ chosen { zephyr,console = &usart0; zephyr,shell-uart = &usart0; + zephyr,uart-pipe = &usart0; zephyr,sram = &sram0; zephyr,flash = &flash0; zephyr,code-partition = &slot0_partition; @@ -34,11 +36,11 @@ leds { compatible = "gpio-leds"; led0: led_0 { - gpios = <&gpiob GECKO_PIN(2) GPIO_ACTIVE_HIGH>; + gpios = <&gpiob 2 GPIO_ACTIVE_HIGH>; label = "LED 0"; }; led1: led_1 { - gpios = <&gpiob GECKO_PIN(4) GPIO_ACTIVE_HIGH>; + gpios = <&gpiob 4 GPIO_ACTIVE_HIGH>; label = "LED 1"; }; }; @@ -46,12 +48,12 @@ buttons { compatible = "gpio-keys"; button0: button_0 { - gpios = <&gpiob GECKO_PIN(1) GPIO_ACTIVE_LOW>; + gpios = <&gpiob 1 GPIO_ACTIVE_LOW>; label = "User Push Button 0"; zephyr,code = ; }; button1: button_1 { - gpios = <&gpiob GECKO_PIN(3) GPIO_ACTIVE_LOW>; + gpios = <&gpiob 3 GPIO_ACTIVE_LOW>; label = "User Push Button 1"; zephyr,code = ; }; @@ -60,13 +62,55 @@ }; &cpu0 { - clock-frequency = <39000000>; + clock-frequency = <78000000>; }; &pstate_em3 { status = "disabled"; }; +&hfxo { + status = "okay"; + ctune = <95>; + precision = <50>; +}; + +&lfxo { + status = "okay"; + ctune = <44>; + precision = <50>; +}; + +&hfrcodpll { + clock-frequency = ; + clocks = <&hfxo>; + dpll-n = <3839>; + dpll-m = <1919>; + dpll-edge = "fall"; + dpll-lock = "phase"; + dpll-autorecover; +}; + +&em23grpaclk { + clocks = <&lfxo>; +}; + +&em4grpaclk { + clocks = <&lfxo>; +}; + +&sysrtcclk { + clocks = <&lfxo>; +}; + +&wdog0clk { + clocks = <&lfxo>; +}; + +&wdog1clk { + clocks = <&lfxo>; +}; + &usart0 { current-speed = <115200>; pinctrl-0 = <&usart0_default>; @@ -105,16 +149,19 @@ status = "okay"; }; -&burtc0 { +&sysrtc0 { status = "okay"; }; -&stimer0 { +&se { status = "okay"; }; -&se { +&dcdc { status = "okay"; + regulator-boot-on; + regulator-initial-mode = ; + silabs,pfmx-peak-current-milliamp = <100>; }; &flash0 { diff --git a/boards/silabs/radio_boards/xg24_rb4187c/xg24_rb4187c.yaml b/boards/silabs/radio_boards/xg24_rb4187c/xg24_rb4187c.yaml index b0be89058ea..014021b5548 100644 --- a/boards/silabs/radio_boards/xg24_rb4187c/xg24_rb4187c.yaml +++ b/boards/silabs/radio_boards/xg24_rb4187c/xg24_rb4187c.yaml @@ -1,5 +1,5 @@ identifier: xg24_rb4187c -name: EFR32xG24 2.4 GHz 20 dBm Radio Board (xG24-RB4187C) +name: EFR32xG24 2.4 GHz 20 dBm Radio Board (xG24-RB4187C, BRD4187C) type: mcu arch: arm ram: 256 @@ -12,6 +12,7 @@ supported: - bluetooth - gpio - uart + - dma - watchdog testing: ignore_tags: diff --git a/boards/silabs/radio_boards/xg24_rb4187c/xg24_rb4187c_defconfig b/boards/silabs/radio_boards/xg24_rb4187c/xg24_rb4187c_defconfig index 7e41ebc6a13..d937f7c3052 100644 --- a/boards/silabs/radio_boards/xg24_rb4187c/xg24_rb4187c_defconfig +++ b/boards/silabs/radio_boards/xg24_rb4187c/xg24_rb4187c_defconfig @@ -5,12 +5,5 @@ CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y CONFIG_GPIO=y -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=78000000 CONFIG_SOC_GECKO_EMU_DCDC=y CONFIG_SOC_GECKO_EMU_DCDC_MODE_ON=y -CONFIG_PINCTRL=y - -# Use BURTC as system clock source -CONFIG_GECKO_BURTC_TIMER=y -CONFIG_CMU_BURTCCLK_LFXO=y -CONFIG_SYS_CLOCK_TICKS_PER_SEC=1024 diff --git a/boards/silabs/starter_kits/efm32wg_stk3800/Kconfig.defconfig b/boards/silabs/starter_kits/efm32wg_stk3800/Kconfig.defconfig index 12fb1b4f236..07d2f13e6a1 100644 --- a/boards/silabs/starter_kits/efm32wg_stk3800/Kconfig.defconfig +++ b/boards/silabs/starter_kits/efm32wg_stk3800/Kconfig.defconfig @@ -1,5 +1,3 @@ -# EFM32WG STK3800 board - # Copyright (c) 2017, Christian Taedcke # SPDX-License-Identifier: Apache-2.0 diff --git a/boards/silabs/starter_kits/efm32wg_stk3800/Kconfig.efm32wg_stk3800 b/boards/silabs/starter_kits/efm32wg_stk3800/Kconfig.efm32wg_stk3800 index 025ac1849f0..e0d4f8bde10 100644 --- a/boards/silabs/starter_kits/efm32wg_stk3800/Kconfig.efm32wg_stk3800 +++ b/boards/silabs/starter_kits/efm32wg_stk3800/Kconfig.efm32wg_stk3800 @@ -1,5 +1,3 @@ -# EFM32WG STK3800 board - # Copyright (c) 2017, Christian Taedcke # SPDX-License-Identifier: Apache-2.0 diff --git a/boards/silabs/starter_kits/efm32wg_stk3800/board.cmake b/boards/silabs/starter_kits/efm32wg_stk3800/board.cmake index 3e0929fbfda..80d94b9d4a2 100644 --- a/boards/silabs/starter_kits/efm32wg_stk3800/board.cmake +++ b/boards/silabs/starter_kits/efm32wg_stk3800/board.cmake @@ -1,5 +1,4 @@ # SPDX-License-Identifier: Apache-2.0 board_runner_args(jlink "--device=EFM32WG990F256") - include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/silabs/starter_kits/efm32wg_stk3800/doc/index.rst b/boards/silabs/starter_kits/efm32wg_stk3800/doc/index.rst index 0c04b7b21de..e8f4b9e432a 100644 --- a/boards/silabs/starter_kits/efm32wg_stk3800/doc/index.rst +++ b/boards/silabs/starter_kits/efm32wg_stk3800/doc/index.rst @@ -1,7 +1,4 @@ -.. _efm32wg_stk3800: - -EFM32 Wonder Gecko (EFM32WG-STK3800) -#################################### +.. zephyr:board:: efm32wg_stk3800 Overview ******** @@ -10,13 +7,6 @@ The EFM32 Wonder Gecko Starter Kit EFM32WG-STK3800 contains a MCU from the EFM32WG family built on ARM® Cortex®-M4F processor with excellent low power capabilities. -.. figure:: efm32wg_stk3800.jpg - :align: center - :alt: EFM32WG-STK3800 - - EFM32WG-STK3800 (image courtesy of Silicon Labs) - - Hardware ******** @@ -60,7 +50,7 @@ The efm32wg_stk3800 board configuration supports the following hardware features +-----------+------------+-------------------------------------+ The default configuration can be found in -:zephyr_file:`boards/silabs/starter_kit/efm32wg_stk3800/efm32wg_stk3800_defconfig` +:zephyr_file:`boards/silabs/starter_kits/efm32wg_stk3800/efm32wg_stk3800_defconfig` Other hardware features are currently not supported by the port. @@ -109,7 +99,7 @@ Programming and Debugging .. note:: Before using the kit the first time, you should update the J-Link firmware - from `J-Link-Downloads`_ + in Simplicity Studio. Flashing ======== @@ -172,6 +162,3 @@ the following message: .. _J-Link: https://www.segger.com/jlink-debug-probes.html - -.. _J-Link-Downloads: - https://www.segger.com/downloads/jlink diff --git a/boards/silabs/starter_kits/efm32wg_stk3800/efm32wg_stk3800.yaml b/boards/silabs/starter_kits/efm32wg_stk3800/efm32wg_stk3800.yaml index 35dbe24db1f..46f0a60822a 100644 --- a/boards/silabs/starter_kits/efm32wg_stk3800/efm32wg_stk3800.yaml +++ b/boards/silabs/starter_kits/efm32wg_stk3800/efm32wg_stk3800.yaml @@ -1,5 +1,5 @@ identifier: efm32wg_stk3800 -name: EFM32 Wonder Gecko Starter Kit (EFM32WG-STK3800) +name: EFM32 Wonder Gecko Starter Kit (EFM32WG-STK3800, BRD2400B) type: mcu arch: arm ram: 32 diff --git a/boards/silabs/starter_kits/slstk3400a/Kconfig.defconfig b/boards/silabs/starter_kits/slstk3400a/Kconfig.defconfig index 78d39acd21a..7c867fdd8e4 100644 --- a/boards/silabs/starter_kits/slstk3400a/Kconfig.defconfig +++ b/boards/silabs/starter_kits/slstk3400a/Kconfig.defconfig @@ -1,5 +1,3 @@ -# EFM32HG SLSTK3400A board - # Copyright (c) 2018, Marcio Montenegro # SPDX-License-Identifier: Apache-2.0 diff --git a/boards/silabs/starter_kits/slstk3400a/Kconfig.slstk3400a b/boards/silabs/starter_kits/slstk3400a/Kconfig.slstk3400a index bdbf1d82750..122db9571fb 100644 --- a/boards/silabs/starter_kits/slstk3400a/Kconfig.slstk3400a +++ b/boards/silabs/starter_kits/slstk3400a/Kconfig.slstk3400a @@ -1,5 +1,3 @@ -# EFM32HG SLSTK3400A board - # Copyright (c) 2018, Marcio Montenegro # SPDX-License-Identifier: Apache-2.0 diff --git a/boards/silabs/starter_kits/slstk3400a/doc/index.rst b/boards/silabs/starter_kits/slstk3400a/doc/index.rst index 7f3f919643b..91786515008 100644 --- a/boards/silabs/starter_kits/slstk3400a/doc/index.rst +++ b/boards/silabs/starter_kits/slstk3400a/doc/index.rst @@ -1,7 +1,4 @@ -.. _slstk3400a: - -EFM32 Happy Gecko (SLSTK3400A) -############################## +.. zephyr:board:: slstk3400a Overview ******** @@ -10,12 +7,6 @@ The EFM32 Happy Gecko Starter Kit SLSTK3400A contains a MCU from the EFM32HG family built on ARM® Cortex®-M0+ processor with excellent low power capabilities. -.. figure:: slstk3400a.jpg - :align: center - :alt: SLSTK3400A - - SLSTK3400A (image courtesy of Silicon Labs) - Hardware ******** @@ -60,7 +51,7 @@ The efm32hg_slstk3400 board configuration supports the following hardware featur +-----------+------------+-------------------------------------+ The default configuration can be found in -:zephyr_file:`boards/silabs/starter_kit/slstk3400a/slstk3400a_defconfig` +:zephyr_file:`boards/silabs/starter_kits/slstk3400a/slstk3400a_defconfig` Other hardware features are currently not supported by the port. @@ -109,7 +100,7 @@ Programming and Debugging .. note:: Before using the kit the first time, you should update the J-Link firmware - from `J-Link-Downloads`_ + in Simplicity Studio. Flashing ======== @@ -171,6 +162,3 @@ Reset the board and you will see this message written to the serial port: .. _J-Link: https://www.segger.com/jlink-debug-probes.html - -.. _J-Link-Downloads: - https://www.segger.com/downloads/jlink diff --git a/boards/silabs/starter_kits/slstk3400a/slstk3400a.yaml b/boards/silabs/starter_kits/slstk3400a/slstk3400a.yaml index 0739c38d858..e3bb4628be0 100644 --- a/boards/silabs/starter_kits/slstk3400a/slstk3400a.yaml +++ b/boards/silabs/starter_kits/slstk3400a/slstk3400a.yaml @@ -1,5 +1,5 @@ identifier: slstk3400a -name: EFM32 Happy Gecko Starter Kit (SLSTK3400A) +name: EFM32 Happy Gecko Starter Kit (SLSTK3400A, BRD2012B) type: mcu arch: arm ram: 8 diff --git a/boards/silabs/starter_kits/slstk3401a/Kconfig.defconfig b/boards/silabs/starter_kits/slstk3401a/Kconfig.defconfig index 992f7da89d4..dd79a970d84 100644 --- a/boards/silabs/starter_kits/slstk3401a/Kconfig.defconfig +++ b/boards/silabs/starter_kits/slstk3401a/Kconfig.defconfig @@ -1,5 +1,3 @@ -# EFM32PG SLSTK3401A board - # Copyright (c) 2020, Rafael Dias Menezes # SPDX-License-Identifier: Apache-2.0 diff --git a/boards/silabs/starter_kits/slstk3401a/Kconfig.slstk3401a b/boards/silabs/starter_kits/slstk3401a/Kconfig.slstk3401a index ef6df9553d6..d6875a11631 100644 --- a/boards/silabs/starter_kits/slstk3401a/Kconfig.slstk3401a +++ b/boards/silabs/starter_kits/slstk3401a/Kconfig.slstk3401a @@ -1,5 +1,3 @@ -# EFM32PG SLSTK3401A board - # Copyright (c) 2020, Rafael Dias Menezes # SPDX-License-Identifier: Apache-2.0 diff --git a/boards/silabs/starter_kits/slstk3401a/board.cmake b/boards/silabs/starter_kits/slstk3401a/board.cmake index 6cbb91515e4..1c46e4c1bfa 100644 --- a/boards/silabs/starter_kits/slstk3401a/board.cmake +++ b/boards/silabs/starter_kits/slstk3401a/board.cmake @@ -1,8 +1,5 @@ -# # Copyright (c) 2020, Rafael Dias Menezes -# # SPDX-License-Identifier: Apache-2.0 -# board_runner_args(jlink "--device=EFM32PG1BxxxF256") include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/silabs/starter_kits/slstk3401a/doc/index.rst b/boards/silabs/starter_kits/slstk3401a/doc/index.rst index d1e41ade626..8e5fa5fb1ee 100644 --- a/boards/silabs/starter_kits/slstk3401a/doc/index.rst +++ b/boards/silabs/starter_kits/slstk3401a/doc/index.rst @@ -1,7 +1,4 @@ -.. _slstk3401a: - -EFM32 Pearl Gecko (SLSTK3401A) -############################## +.. zephyr:board:: slstk3401a Overview ******** @@ -10,12 +7,6 @@ The EFM32 Pearl Gecko Starter Kit SLSTK3401A contains an MCU from the EFM32PG family built on an ARM® Cortex®-M4F processor with excellent low power capabilities. -.. figure:: slstk3401a.jpg - :align: center - :alt: EFM32PG-SLSTK3401A - - EFM32PG-SLSTK3401A (image courtesy of Silicon Labs) - Hardware ******** @@ -120,7 +111,7 @@ Programming and Debugging .. note:: Before using the kit the first time, you should update the J-Link firmware - from `J-Link-Downloads`_ + in Simplicity Studio. Flashing ======== @@ -183,6 +174,3 @@ terminal session: .. _J-Link: https://www.segger.com/jlink-debug-probes.html - -.. _J-Link-Downloads: - https://www.segger.com/downloads/jlink diff --git a/boards/silabs/starter_kits/slstk3401a/slstk3401a.yaml b/boards/silabs/starter_kits/slstk3401a/slstk3401a.yaml index c2eab5f1756..a7de8915c22 100644 --- a/boards/silabs/starter_kits/slstk3401a/slstk3401a.yaml +++ b/boards/silabs/starter_kits/slstk3401a/slstk3401a.yaml @@ -1,5 +1,5 @@ identifier: slstk3401a -name: EFM32 Pearl Gecko Starter Kit (SLSTK3401A) +name: EFM32 Pearl Gecko Starter Kit (SLSTK3401A, BRD2500B) type: mcu arch: arm ram: 32 diff --git a/boards/silabs/starter_kits/slstk3402a/Kconfig.defconfig b/boards/silabs/starter_kits/slstk3402a/Kconfig.defconfig index 87181e6b602..f3b2a8c77e0 100644 --- a/boards/silabs/starter_kits/slstk3402a/Kconfig.defconfig +++ b/boards/silabs/starter_kits/slstk3402a/Kconfig.defconfig @@ -1,5 +1,3 @@ -# EFM32PG12 SLSTK3402A board - # Copyright (c) 2018, Christian Taedcke # Copyright (c) 2019 Lemonbeat GmbH # SPDX-License-Identifier: Apache-2.0 diff --git a/boards/silabs/starter_kits/slstk3402a/Kconfig.slstk3402a b/boards/silabs/starter_kits/slstk3402a/Kconfig.slstk3402a index e4d6444823b..0a30a1daade 100644 --- a/boards/silabs/starter_kits/slstk3402a/Kconfig.slstk3402a +++ b/boards/silabs/starter_kits/slstk3402a/Kconfig.slstk3402a @@ -1,5 +1,3 @@ -# EFM32PG12 SLSTK3402A board - # Copyright (c) 2018, Christian Taedcke # Copyright (c) 2019 Lemonbeat GmbH # SPDX-License-Identifier: Apache-2.0 diff --git a/boards/silabs/starter_kits/slstk3402a/board.cmake b/boards/silabs/starter_kits/slstk3402a/board.cmake index b9925901bc8..9cd1b64e6e7 100644 --- a/boards/silabs/starter_kits/slstk3402a/board.cmake +++ b/boards/silabs/starter_kits/slstk3402a/board.cmake @@ -1,8 +1,5 @@ -# # Copyright (c) 2018, Christian Taedcke -# # SPDX-License-Identifier: Apache-2.0 -# board_runner_args(jlink "--device=EFM32PG12BxxxF1024") include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/silabs/starter_kits/slstk3402a/doc/index.rst b/boards/silabs/starter_kits/slstk3402a/doc/index.rst index 4e5293ee08f..3470e9e6701 100644 --- a/boards/silabs/starter_kits/slstk3402a/doc/index.rst +++ b/boards/silabs/starter_kits/slstk3402a/doc/index.rst @@ -1,7 +1,4 @@ -.. _slstk3402a: - -EFM32 Pearl Gecko 12 (SLSTK3402A) -################################# +.. zephyr:board:: slstk3402a Overview ******** @@ -10,12 +7,6 @@ The EFM32 Pearl Gecko 12 Starter Kit SLSTK3402A contains an MCU from the EFM32PG family built on an ARM® Cortex®-M4F processor with excellent low power capabilities. -.. figure:: slstk3402a.jpg - :align: center - :alt: SLSTK3402A - - EFM32PG12 SLSTK3402A (image courtesy of Silicon Labs) - Hardware ******** @@ -143,7 +134,7 @@ Programming and Debugging .. note:: Before using the kit the first time, you should update the J-Link firmware - from `J-Link-Downloads`_ + in Simplicity Studio. Flashing ======== @@ -209,6 +200,3 @@ terminal session: .. _J-Link: https://www.segger.com/jlink-debug-probes.html - -.. _J-Link-Downloads: - https://www.segger.com/downloads/jlink diff --git a/boards/silabs/starter_kits/slstk3402a/slstk3402a_efm32jg12b500f1024gl125.yaml b/boards/silabs/starter_kits/slstk3402a/slstk3402a_efm32jg12b500f1024gl125.yaml index f6981091500..552699ed84a 100644 --- a/boards/silabs/starter_kits/slstk3402a/slstk3402a_efm32jg12b500f1024gl125.yaml +++ b/boards/silabs/starter_kits/slstk3402a/slstk3402a_efm32jg12b500f1024gl125.yaml @@ -1,5 +1,5 @@ identifier: slstk3402a/efm32jg12b500f1024gl125 -name: EFM32JG12 SLSTK3402A +name: EFM32JG12 Pearl Gecko Starter Kit (SLSTK3402A, BRD2501B) type: mcu arch: arm ram: 256 diff --git a/boards/silabs/starter_kits/slstk3402a/slstk3402a_efm32pg12b500f1024gl125.yaml b/boards/silabs/starter_kits/slstk3402a/slstk3402a_efm32pg12b500f1024gl125.yaml index 1ce7433a7aa..8274823adfa 100644 --- a/boards/silabs/starter_kits/slstk3402a/slstk3402a_efm32pg12b500f1024gl125.yaml +++ b/boards/silabs/starter_kits/slstk3402a/slstk3402a_efm32pg12b500f1024gl125.yaml @@ -1,5 +1,5 @@ identifier: slstk3402a/efm32pg12b500f1024gl125 -name: EFM32PG12 SLSTK3402A +name: EFM32PG12 Pearl Gecko Starter Kit (SLSTK3402A, BRD2501B) type: mcu arch: arm ram: 256 diff --git a/boards/silabs/starter_kits/slstk3701a/Kconfig.defconfig b/boards/silabs/starter_kits/slstk3701a/Kconfig.defconfig index 24d55ad5a9b..f534e34ff83 100644 --- a/boards/silabs/starter_kits/slstk3701a/Kconfig.defconfig +++ b/boards/silabs/starter_kits/slstk3701a/Kconfig.defconfig @@ -1,4 +1,3 @@ -# EFM32GG STK3701A default board configuration # Copyright (c) 2019 Interay Solutions B.V. # Copyright (c) 2019 Oane Kingma # SPDX-License-Identifier: Apache-2.0 diff --git a/boards/silabs/starter_kits/slstk3701a/Kconfig.slstk3701a b/boards/silabs/starter_kits/slstk3701a/Kconfig.slstk3701a index e0fd2b5412e..e7b3b53b134 100644 --- a/boards/silabs/starter_kits/slstk3701a/Kconfig.slstk3701a +++ b/boards/silabs/starter_kits/slstk3701a/Kconfig.slstk3701a @@ -1,4 +1,3 @@ -# EFM32GG11 SLSTK3701A board configuration # Copyright (c) 2019 Interay Solutions B.V. # Copyright (c) 2019 Oane Kingma # SPDX-License-Identifier: Apache-2.0 diff --git a/boards/silabs/starter_kits/slstk3701a/board.cmake b/boards/silabs/starter_kits/slstk3701a/board.cmake index d56bbf2a97f..20bfe9f4821 100644 --- a/boards/silabs/starter_kits/slstk3701a/board.cmake +++ b/boards/silabs/starter_kits/slstk3701a/board.cmake @@ -3,6 +3,7 @@ # SPDX-License-Identifier: Apache-2.0 board_runner_args(jlink "--device=EFM32GG11B820F2048") -board_runner_args(openocd) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) + +board_runner_args(openocd) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/silabs/starter_kits/slstk3701a/doc/index.rst b/boards/silabs/starter_kits/slstk3701a/doc/index.rst index 6209984049e..d63c3f3844b 100644 --- a/boards/silabs/starter_kits/slstk3701a/doc/index.rst +++ b/boards/silabs/starter_kits/slstk3701a/doc/index.rst @@ -1,7 +1,4 @@ -.. _efm32gg_stk3701a: - -EFM32 Giant Gecko 11 (SLSTK3701A) -################################# +.. zephyr:board:: slstk3701a Overview ******** @@ -10,12 +7,6 @@ The EFM32 Giant Gecko Starter Kit SLSTK3701A contains an MCU from the EFM32GG Series 1 family built on an ARM® Cortex®-M4F processor with excellent low power capabilities. -.. figure:: slstk3701a.jpg - :align: center - :alt: EFM32GG11 SLSTK3701A - - EFM32GG11 SLSTK3701A (image courtesy of Silicon Labs) - Hardware ******** @@ -132,7 +123,7 @@ Programming and Debugging .. note:: Before using the kit the first time, you should update the J-Link firmware - from `J-Link-Downloads`_ + in Simplicity Studio. Flashing ======== @@ -195,6 +186,3 @@ terminal session: .. _J-Link: https://www.segger.com/jlink-debug-probes.html - -.. _J-Link-Downloads: - https://www.segger.com/downloads/jlink diff --git a/boards/silabs/starter_kits/slstk3701a/slstk3701a-pinctrl.dtsi b/boards/silabs/starter_kits/slstk3701a/slstk3701a-pinctrl.dtsi index 4540922dd2f..a8731a39368 100644 --- a/boards/silabs/starter_kits/slstk3701a/slstk3701a-pinctrl.dtsi +++ b/boards/silabs/starter_kits/slstk3701a/slstk3701a-pinctrl.dtsi @@ -43,4 +43,13 @@ ; }; }; + + i2c2_default: i2c2_default { + group1 { + psels = , + , + , + ; + }; + }; }; diff --git a/boards/silabs/starter_kits/slstk3701a/slstk3701a.dts b/boards/silabs/starter_kits/slstk3701a/slstk3701a.dts index 1e67f024d7f..331a2163718 100644 --- a/boards/silabs/starter_kits/slstk3701a/slstk3701a.dts +++ b/boards/silabs/starter_kits/slstk3701a/slstk3701a.dts @@ -92,6 +92,12 @@ status = "okay"; }; +&i2c2 { + pinctrl-0 = <&i2c2_default>; + pinctrl-names = "default"; + status = "okay"; +}; + &rtcc0 { prescaler = <1>; status = "okay"; diff --git a/boards/silabs/starter_kits/slstk3701a/slstk3701a.yaml b/boards/silabs/starter_kits/slstk3701a/slstk3701a.yaml index bfad741b918..2c9a0d812cd 100644 --- a/boards/silabs/starter_kits/slstk3701a/slstk3701a.yaml +++ b/boards/silabs/starter_kits/slstk3701a/slstk3701a.yaml @@ -1,5 +1,5 @@ identifier: slstk3701a -name: EFM32GG11 Giant Gecko Starter Kit (SLSTK3701A) +name: EFM32GG11 Giant Gecko Starter Kit (SLSTK3701A, BRD2204C) type: mcu arch: arm ram: 512 diff --git a/boards/sipeed/longan_nano/doc/index.rst b/boards/sipeed/longan_nano/doc/index.rst index 6150c2378cf..49a52c00d65 100644 --- a/boards/sipeed/longan_nano/doc/index.rst +++ b/boards/sipeed/longan_nano/doc/index.rst @@ -1,11 +1,4 @@ -.. _longan_nano: - -Sipeed Longan Nano -################## - -.. image:: img/longan_nano.jpg - :align: center - :alt: longan_nano +.. zephyr:board:: longan_nano Overview ******** diff --git a/boards/sipeed/longan_nano/longan_nano-common.dtsi b/boards/sipeed/longan_nano/longan_nano-common.dtsi index c5e9202e94f..e11ee37f8af 100644 --- a/boards/sipeed/longan_nano/longan_nano-common.dtsi +++ b/boards/sipeed/longan_nano/longan_nano-common.dtsi @@ -106,7 +106,7 @@ caset = [00 01 00 a0]; raset = [00 1a 00 69]; - mipi-mode = ; + mipi-mode = "MIPI_DBI_MODE_SPI_4WIRE"; mipi-max-frequency = <4000000>; }; }; @@ -170,6 +170,7 @@ spi-max-frequency = <24000000>; mmc { compatible = "zephyr,sdmmc-disk"; + disk-name = "SD"; status = "okay"; }; }; diff --git a/boards/snps/em_starterkit/doc/index.rst b/boards/snps/em_starterkit/doc/index.rst index e569031e378..9fc53692b66 100644 --- a/boards/snps/em_starterkit/doc/index.rst +++ b/boards/snps/em_starterkit/doc/index.rst @@ -1,7 +1,4 @@ -.. _em_starterkit: - -DesignWare(R) ARC(R) EM Starter Kit -################################### +.. zephyr:board:: em_starterkit Overview ******** @@ -12,10 +9,6 @@ for the ARC EM Family of processors. The EM Family includes the EM4, EM6, EM5D, EM7D, EM9D, and EM11D cores. The Zephyr RTOS can be used with the EM Starter Kit. -.. image:: em_starterkit.jpg - :align: center - :alt: DesignWare(R) ARC(R) EM Starter Kit (synopsys.com) - The ARC EM Starter Kit consists of a hardware platform, including pre-installed FPGA images of different ARC EM processor configurations with peripherals. Documentation for this board can be found at `embARC website`_. @@ -26,7 +19,7 @@ See also this URL for details about the board: The latest version of EM Starter Kit is 2.3, developer can upgrade from 2.0/2.1/2.2 to 2.3 using latest firmware. The default configuration for EM Starter Kit boards can be found in -:zephyr_file:`boards/snps/em_starterkit/em_starterkit_defconfig`. +:zephyr_file:`boards/snps/em_starterkit/`. The default SoC for this board supported in Zephyr is the EM9D. This configuration is a Harvard Architecture, with a separate @@ -307,6 +300,8 @@ The following is a list of TODO items: References ********** +.. target-notes:: + .. _embARC website: https://www.embarc.org .. _Designware ARC EM Starter Kit website: https://www.synopsys.com/dw/ipdir.php?ds=arc_em_starter_kit diff --git a/boards/snps/em_starterkit/em_starterkit_emsk_em11d_defconfig b/boards/snps/em_starterkit/em_starterkit_emsk_em11d_defconfig index 38979ec4912..132e072f56f 100644 --- a/boards/snps/em_starterkit/em_starterkit_emsk_em11d_defconfig +++ b/boards/snps/em_starterkit/em_starterkit_emsk_em11d_defconfig @@ -3,7 +3,6 @@ CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 CONFIG_XIP=n -CONFIG_BUILD_NO_GAP_FILL=y CONFIG_BUILD_OUTPUT_BIN=n CONFIG_ARCV2_INTERRUPT_UNIT=y CONFIG_ARCV2_TIMER=y diff --git a/boards/snps/em_starterkit/em_starterkit_emsk_em7d_2_3_defconfig b/boards/snps/em_starterkit/em_starterkit_emsk_em7d_2_3_defconfig index 42963436cbc..f3d598c4b10 100644 --- a/boards/snps/em_starterkit/em_starterkit_emsk_em7d_2_3_defconfig +++ b/boards/snps/em_starterkit/em_starterkit_emsk_em7d_2_3_defconfig @@ -3,7 +3,6 @@ CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 CONFIG_XIP=n -CONFIG_BUILD_NO_GAP_FILL=y CONFIG_BUILD_OUTPUT_BIN=n CONFIG_ARCV2_INTERRUPT_UNIT=y CONFIG_ARCV2_TIMER=y diff --git a/boards/snps/em_starterkit/em_starterkit_emsk_em7d_defconfig b/boards/snps/em_starterkit/em_starterkit_emsk_em7d_defconfig index d9fa27c036b..2649fc165c8 100644 --- a/boards/snps/em_starterkit/em_starterkit_emsk_em7d_defconfig +++ b/boards/snps/em_starterkit/em_starterkit_emsk_em7d_defconfig @@ -3,7 +3,6 @@ CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 CONFIG_XIP=n -CONFIG_BUILD_NO_GAP_FILL=y CONFIG_BUILD_OUTPUT_BIN=n CONFIG_ARCV2_INTERRUPT_UNIT=y CONFIG_ARCV2_TIMER=y diff --git a/boards/snps/em_starterkit/em_starterkit_emsk_em9d_defconfig b/boards/snps/em_starterkit/em_starterkit_emsk_em9d_defconfig index 38979ec4912..132e072f56f 100644 --- a/boards/snps/em_starterkit/em_starterkit_emsk_em9d_defconfig +++ b/boards/snps/em_starterkit/em_starterkit_emsk_em9d_defconfig @@ -3,7 +3,6 @@ CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 CONFIG_XIP=n -CONFIG_BUILD_NO_GAP_FILL=y CONFIG_BUILD_OUTPUT_BIN=n CONFIG_ARCV2_INTERRUPT_UNIT=y CONFIG_ARCV2_TIMER=y diff --git a/boards/snps/emsdp/doc/index.rst b/boards/snps/emsdp/doc/index.rst index bad8a48e4bb..f300d3723ce 100644 --- a/boards/snps/emsdp/doc/index.rst +++ b/boards/snps/emsdp/doc/index.rst @@ -1,7 +1,4 @@ -.. _emsdp: - -DesignWare(R) ARC(R) EM Software Development Platform -##################################################### +.. zephyr:board:: emsdp Overview ******** @@ -12,10 +9,6 @@ to accelerate software development and debug of ARC EM processors and subsystems a wide range of ultra-low power embedded applications such as IoT, sensor fusion, and voice applications. -.. image:: emsdp.jpg - :align: center - :alt: DesignWare(R) ARC(R) EM Software Development Platform (synopsys.com) - For details about the board, see: `DesignWare ARC EM Software Development Platform (EM SDP) `__ diff --git a/boards/snps/emsdp/emsdp_emsdp_em11d_defconfig b/boards/snps/emsdp/emsdp_emsdp_em11d_defconfig index 666e1cb41fb..1cbd8610dbb 100644 --- a/boards/snps/emsdp/emsdp_emsdp_em11d_defconfig +++ b/boards/snps/emsdp/emsdp_emsdp_em11d_defconfig @@ -2,7 +2,6 @@ CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 CONFIG_XIP=n -CONFIG_BUILD_NO_GAP_FILL=y CONFIG_BUILD_OUTPUT_BIN=n CONFIG_ARCV2_INTERRUPT_UNIT=y CONFIG_ARCV2_TIMER=y @@ -13,4 +12,3 @@ CONFIG_UART_INTERRUPT_DRIVEN=y CONFIG_ARC_MPU_ENABLE=y CONFIG_GPIO=y CONFIG_SPI=y -CONFIG_PINCTRL=y diff --git a/boards/snps/emsdp/emsdp_emsdp_em5d_defconfig b/boards/snps/emsdp/emsdp_emsdp_em5d_defconfig index 03f84b13a64..1cbd8610dbb 100644 --- a/boards/snps/emsdp/emsdp_emsdp_em5d_defconfig +++ b/boards/snps/emsdp/emsdp_emsdp_em5d_defconfig @@ -2,7 +2,6 @@ CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 CONFIG_XIP=n -CONFIG_BUILD_NO_GAP_FILL=y CONFIG_BUILD_OUTPUT_BIN=n CONFIG_ARCV2_INTERRUPT_UNIT=y CONFIG_ARCV2_TIMER=y diff --git a/boards/snps/emsdp/emsdp_emsdp_em6_defconfig b/boards/snps/emsdp/emsdp_emsdp_em6_defconfig index 03f84b13a64..1cbd8610dbb 100644 --- a/boards/snps/emsdp/emsdp_emsdp_em6_defconfig +++ b/boards/snps/emsdp/emsdp_emsdp_em6_defconfig @@ -2,7 +2,6 @@ CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 CONFIG_XIP=n -CONFIG_BUILD_NO_GAP_FILL=y CONFIG_BUILD_OUTPUT_BIN=n CONFIG_ARCV2_INTERRUPT_UNIT=y CONFIG_ARCV2_TIMER=y diff --git a/boards/snps/emsdp/emsdp_emsdp_em7d_defconfig b/boards/snps/emsdp/emsdp_emsdp_em7d_defconfig index d8581e40fab..1c5957e4386 100644 --- a/boards/snps/emsdp/emsdp_emsdp_em7d_defconfig +++ b/boards/snps/emsdp/emsdp_emsdp_em7d_defconfig @@ -2,7 +2,6 @@ CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 CONFIG_XIP=n -CONFIG_BUILD_NO_GAP_FILL=y CONFIG_BUILD_OUTPUT_BIN=n CONFIG_ARCV2_INTERRUPT_UNIT=y CONFIG_ARCV2_TIMER=y diff --git a/boards/snps/emsdp/emsdp_emsdp_em7d_esp_defconfig b/boards/snps/emsdp/emsdp_emsdp_em7d_esp_defconfig index d6de8dababf..d347468026c 100644 --- a/boards/snps/emsdp/emsdp_emsdp_em7d_esp_defconfig +++ b/boards/snps/emsdp/emsdp_emsdp_em7d_esp_defconfig @@ -2,7 +2,6 @@ CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 CONFIG_XIP=n -CONFIG_BUILD_NO_GAP_FILL=y CONFIG_BUILD_OUTPUT_BIN=n CONFIG_ARCV2_INTERRUPT_UNIT=y CONFIG_ARCV2_TIMER=y diff --git a/boards/snps/emsdp/emsdp_emsdp_em9d_defconfig b/boards/snps/emsdp/emsdp_emsdp_em9d_defconfig index 03f84b13a64..1cbd8610dbb 100644 --- a/boards/snps/emsdp/emsdp_emsdp_em9d_defconfig +++ b/boards/snps/emsdp/emsdp_emsdp_em9d_defconfig @@ -2,7 +2,6 @@ CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 CONFIG_XIP=n -CONFIG_BUILD_NO_GAP_FILL=y CONFIG_BUILD_OUTPUT_BIN=n CONFIG_ARCV2_INTERRUPT_UNIT=y CONFIG_ARCV2_TIMER=y diff --git a/boards/snps/hsdk/doc/index.rst b/boards/snps/hsdk/doc/index.rst index b79ecbca968..f7d82a9866f 100644 --- a/boards/snps/hsdk/doc/index.rst +++ b/boards/snps/hsdk/doc/index.rst @@ -1,7 +1,4 @@ -.. _hsdk: - -DesignWare(R) ARC(R) HS Development Kit -######################################## +.. zephyr:board:: hsdk Overview ******** @@ -14,10 +11,6 @@ UART, I2S, ADC, PWM and GPIO. A Vivante GPU is also contained in the ARC Development System SoC. This allows developers to build and debug complex software on a comprehensive hardware platform -.. image:: hsdk.jpg - :align: center - :alt: DesignWare(R) ARC(R) HS Development Kit (synopsys.com) - For details about the board, see: `ARC HS Development Kit (HSDK) `__ @@ -518,6 +511,8 @@ Release Notes References ********** +.. target-notes:: + .. _embARC website: https://www.embarc.org .. _Designware HS Development Kit website: https://www.synopsys.com/dw/ipdir.php?ds=arc-hs-development-kit diff --git a/boards/snps/hsdk/hsdk_arc_hsdk_2cores_defconfig b/boards/snps/hsdk/hsdk_arc_hsdk_2cores_defconfig index bc0a91f60be..449b4c2a8bd 100644 --- a/boards/snps/hsdk/hsdk_arc_hsdk_2cores_defconfig +++ b/boards/snps/hsdk/hsdk_arc_hsdk_2cores_defconfig @@ -2,7 +2,6 @@ CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 CONFIG_XIP=n -CONFIG_BUILD_NO_GAP_FILL=y CONFIG_BUILD_OUTPUT_BIN=n CONFIG_ARCV2_INTERRUPT_UNIT=y CONFIG_ARCV2_TIMER=y diff --git a/boards/snps/hsdk/hsdk_defconfig b/boards/snps/hsdk/hsdk_defconfig index 0d17f50041b..75f91c8c1a2 100644 --- a/boards/snps/hsdk/hsdk_defconfig +++ b/boards/snps/hsdk/hsdk_defconfig @@ -2,7 +2,6 @@ CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 CONFIG_XIP=n -CONFIG_BUILD_NO_GAP_FILL=y CONFIG_BUILD_OUTPUT_BIN=n CONFIG_ARCV2_INTERRUPT_UNIT=y CONFIG_ARCV2_TIMER=y diff --git a/boards/snps/hsdk4xd/doc/index.rst b/boards/snps/hsdk4xd/doc/index.rst index 04b30bcaf9b..0808b76ca6d 100644 --- a/boards/snps/hsdk4xd/doc/index.rst +++ b/boards/snps/hsdk4xd/doc/index.rst @@ -1,20 +1,13 @@ -.. _hsdk4xd: - -DesignWare(R) ARC(R) HS4x/HS4xD Development Kit -############################################### +.. zephyr:board:: hsdk4xd Overview ******** -The ARC HS4x/HS4xD Development Kit is the next revision of :ref:`Synopsys HSDK board `. +The ARC HS4x/HS4xD Development Kit is the next revision of :zephyr:board:`Synopsys HSDK board `. It includes a multicore ARC HS4xD-based chip that integrates a wide range of interfaces including Ethernet, HDMI, WiFi, Bluetooth, USB, SDIO, I2C, SPI, UART, I2S, ADC, PWM and GPIO, as well as a Think Silicon GPU. -.. image:: hsdk4xd.jpg - :align: center - :alt: DesignWare(R) ARC(R) HS4x/HS4xD Development Kit (synopsys.com) - For details about the board, see: `ARC HS4x/HS4xD Development Kit (HSDK4xD) `__ @@ -547,6 +540,8 @@ The following list indicates the state of HS4x/HS4xD Development Kit peripherals References ********** +.. target-notes:: + .. _embARC website: https://www.embarc.org .. _Designware HS Development Kit website: https://www.synopsys.com/dw/ipdir.php?ds=arc-hs-development-kit diff --git a/boards/snps/hsdk4xd/hsdk4xd_defconfig b/boards/snps/hsdk4xd/hsdk4xd_defconfig index 00d8ba6ff0d..52e7a63c63a 100644 --- a/boards/snps/hsdk4xd/hsdk4xd_defconfig +++ b/boards/snps/hsdk4xd/hsdk4xd_defconfig @@ -1,7 +1,6 @@ # SPDX-License-Identifier: Apache-2.0 CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 -CONFIG_BUILD_NO_GAP_FILL=y CONFIG_BUILD_OUTPUT_BIN=n CONFIG_ARCV2_INTERRUPT_UNIT=y CONFIG_ARCV2_TIMER=y diff --git a/boards/snps/iotdk/doc/index.rst b/boards/snps/iotdk/doc/index.rst index 5482bed17d9..8176f51618d 100644 --- a/boards/snps/iotdk/doc/index.rst +++ b/boards/snps/iotdk/doc/index.rst @@ -1,7 +1,4 @@ -.. _iotdk: - -DesignWare(R) ARC(R) IoT Development Kit -######################################## +.. zephyr:board:: iotdk Overview ******** @@ -14,10 +11,6 @@ implementation of the ARC Data Fusion IP Subsystem running at 144 MHz on SMIC's 55-nm ultra-low power process, and a rich set of peripherals commonly used in IoT designs such as USB, UART, SPI, I2C, PWM, SDIO, and ADCs. -.. image:: iotdk.jpg - :align: center - :alt: DesignWare(R) ARC(R)IoT Development Kit (synopsys.com) - For details about the board, see: `ARC IoT Development Kit (IoTDK) `__ @@ -189,6 +182,8 @@ Release Notes References ********** +.. target-notes:: + .. _embARC website: https://www.embarc.org .. _Designware ARC IoT Development Kit website: https://www.synopsys.com/dw/ipdir.php?ds=arc_iot_development_kit diff --git a/boards/snps/iotdk/iotdk_defconfig b/boards/snps/iotdk/iotdk_defconfig index d95ae777729..a12a0a63fb2 100644 --- a/boards/snps/iotdk/iotdk_defconfig +++ b/boards/snps/iotdk/iotdk_defconfig @@ -1,7 +1,6 @@ # SPDX-License-Identifier: Apache-2.0 CONFIG_XIP=n -CONFIG_BUILD_NO_GAP_FILL=y CONFIG_BUILD_OUTPUT_BIN=n CONFIG_ARCV2_INTERRUPT_UNIT=y CONFIG_ARCV2_TIMER=y diff --git a/boards/snps/nsim/arc_classic/doc/index.rst b/boards/snps/nsim/arc_classic/doc/index.rst index 24a35ac9544..c3839dfc893 100644 --- a/boards/snps/nsim/arc_classic/doc/index.rst +++ b/boards/snps/nsim/arc_classic/doc/index.rst @@ -1,7 +1,4 @@ -.. _nsim: - -DesignWare ARC nSIM and HAPS FPGA boards -######################################## +.. zephyr:board:: nsim Overview ******** @@ -39,7 +36,7 @@ available configurations are listed below: .. _board_arc_nsim_prop_args_files: It is recommended to look at precise description of a particular sub-configuration in either -``.props`` or ``.args`` files in :zephyr_file:`boards/snps/nsim/support/` directory to understand +``.props`` or ``.args`` files in :zephyr_file:`boards/snps/nsim/arc_classic/support/` directory to understand which options are configured and so will be used on invocation of the simulator. In case of single-core configurations it would be ``.props`` file which contains configuration @@ -55,14 +52,14 @@ simulation anyway). nSIM & MDB don't exactly match, so care should be taken). I.e. for the single-core ``nsim/nsim_hs5x`` platform there are -:zephyr_file:`boards/snps/nsim/support/nsim_hs5x.props` and -:zephyr_file:`boards/snps/nsim/support/mdb_hs5x.args`. +:zephyr_file:`boards/snps/nsim/arc_classic/support/nsim_hs5x.props` and +:zephyr_file:`boards/snps/nsim/arc_classic/support/mdb_hs5x.args`. For the multi-core configurations there is only ``.args`` file as the multi-core configuration can only be instantiated with help of MDB. I.e. for the multi-core ``nsim/nsim_hs5x/smp`` platform there is only -:zephyr_file:`boards/snps/nsim/support/mdb_hs5x_smp.args`. +:zephyr_file:`boards/snps/nsim/arc_classic/support/mdb_hs5x_smp.args`. .. warning:: All nSIM/MDB configurations are used for demo and testing purposes. They are not meant to @@ -90,7 +87,7 @@ Most board sub-configurations support building with both GNU and ARC MWDT toolch there might be exceptions from that, especially for newly added targets. You can check supported toolchains for the sub-configurations in the corresponding ``.yaml`` file. -I.e. for the ``nsim/nsim_hs5x`` board we can check :zephyr_file:`boards/snps/nsim/nsim_nsim_hs5x.yaml` +I.e. for the ``nsim/nsim_hs5x`` board we can check :zephyr_file:`boards/snps/nsim/arc_classic/nsim_nsim_hs5x.yaml` The supported toolchains are listed in ``toolchain:`` array in ``.yaml`` file, where we can find: @@ -316,7 +313,7 @@ GNU & MWDT toolchain compiler options ===================================== The hardware-specific compiler options are set in corresponding SoC cmake file. For ``nsim`` board -it is :zephyr_file:`soc/snps/nsim/CMakeLists.txt`. +it is :zephyr_file:`soc/snps/nsim/arc_classic/CMakeLists.txt`. For the GNU toolchain the basic configuration is set via ``-mcpu`` which is defined in generic code and based on the selected CPU model via Kconfig. It still can be forcefully set to required value @@ -333,6 +330,8 @@ For the MWDT toolchain all hardware-specific compiler options are set directly i References ********** +.. target-notes:: + .. _Designware ARC nSIM: https://www.synopsys.com/dw/ipdir.php?ds=sim_nsim .. _DesignWare ARC Free nSIM: https://www.synopsys.com/cgi-bin/dwarcnsim/req1.cgi .. _HAPS: https://www.synopsys.com/verification/prototyping/haps.html diff --git a/boards/snps/nsim/arc_classic/nsim_nsim_em.yaml b/boards/snps/nsim/arc_classic/nsim_nsim_em.yaml index 7fd973932eb..4ca8b66ab2c 100644 --- a/boards/snps/nsim/arc_classic/nsim_nsim_em.yaml +++ b/boards/snps/nsim/arc_classic/nsim_nsim_em.yaml @@ -1,8 +1,9 @@ identifier: nsim/nsim_em name: EM Nsim simulator type: sim -simulation: nsim -simulation_exec: nsimdrv +simulation: + - name: nsim + exec: nsimdrv arch: arc toolchain: - zephyr diff --git a/boards/snps/nsim/arc_classic/nsim_nsim_em11d.yaml b/boards/snps/nsim/arc_classic/nsim_nsim_em11d.yaml index e37aeb2f442..c69866d1752 100644 --- a/boards/snps/nsim/arc_classic/nsim_nsim_em11d.yaml +++ b/boards/snps/nsim/arc_classic/nsim_nsim_em11d.yaml @@ -1,8 +1,9 @@ identifier: nsim/nsim_em11d name: EM11D Nsim simulator type: sim -simulation: nsim -simulation_exec: nsimdrv +simulation: + - name: nsim + exec: nsimdrv arch: arc toolchain: - zephyr diff --git a/boards/snps/nsim/arc_classic/nsim_nsim_em7d_v22.dts b/boards/snps/nsim/arc_classic/nsim_nsim_em7d_v22.dts index 4b52355589a..ef9791ff0d7 100644 --- a/boards/snps/nsim/arc_classic/nsim_nsim_em7d_v22.dts +++ b/boards/snps/nsim/arc_classic/nsim_nsim_em7d_v22.dts @@ -6,6 +6,9 @@ /dts-v1/; +#define ICCM_SIZE DT_SIZE_K(256) +#define DCCM_SIZE DT_SIZE_K(128) + #include "nsim_em.dtsi" / { diff --git a/boards/snps/nsim/arc_classic/nsim_nsim_em7d_v22.yaml b/boards/snps/nsim/arc_classic/nsim_nsim_em7d_v22.yaml index c77c883ccc8..f23c4489749 100644 --- a/boards/snps/nsim/arc_classic/nsim_nsim_em7d_v22.yaml +++ b/boards/snps/nsim/arc_classic/nsim_nsim_em7d_v22.yaml @@ -1,8 +1,9 @@ identifier: nsim/nsim_em7d_v22 name: EM nSIM simulator (EM7D_v22) type: sim -simulation: nsim -simulation_exec: nsimdrv +simulation: + - name: nsim + exec: nsimdrv arch: arc toolchain: - zephyr diff --git a/boards/snps/nsim/arc_classic/nsim_nsim_hs.yaml b/boards/snps/nsim/arc_classic/nsim_nsim_hs.yaml index 2f02bf5c85a..2a77407839c 100644 --- a/boards/snps/nsim/arc_classic/nsim_nsim_hs.yaml +++ b/boards/snps/nsim/arc_classic/nsim_nsim_hs.yaml @@ -1,8 +1,9 @@ identifier: nsim/nsim_hs name: HS nSIM simulator type: sim -simulation: nsim -simulation_exec: nsimdrv +simulation: + - name: nsim + exec: nsimdrv arch: arc toolchain: - zephyr diff --git a/boards/snps/nsim/arc_classic/nsim_nsim_hs5x.yaml b/boards/snps/nsim/arc_classic/nsim_nsim_hs5x.yaml index a20ad79a34a..05c26d61f00 100644 --- a/boards/snps/nsim/arc_classic/nsim_nsim_hs5x.yaml +++ b/boards/snps/nsim/arc_classic/nsim_nsim_hs5x.yaml @@ -1,8 +1,9 @@ identifier: nsim/nsim_hs5x name: HS5x nSIM simulator type: sim -simulation: nsim -simulation_exec: nsimdrv +simulation: + - name: nsim + exec: nsimdrv arch: arc toolchain: - zephyr diff --git a/boards/snps/nsim/arc_classic/nsim_nsim_hs5x_smp.yaml b/boards/snps/nsim/arc_classic/nsim_nsim_hs5x_smp.yaml index 09dcfd014ef..1d0e71868a4 100644 --- a/boards/snps/nsim/arc_classic/nsim_nsim_hs5x_smp.yaml +++ b/boards/snps/nsim/arc_classic/nsim_nsim_hs5x_smp.yaml @@ -1,8 +1,9 @@ identifier: nsim/nsim_hs5x/smp name: Multi-core HS5x nSIM simulator type: sim -simulation: mdb-nsim -simulation_exec: mdb +simulation: + - name: mdb-nsim + exec: mdb arch: arc toolchain: - zephyr diff --git a/boards/snps/nsim/arc_classic/nsim_nsim_hs5x_smp_12cores.yaml b/boards/snps/nsim/arc_classic/nsim_nsim_hs5x_smp_12cores.yaml index 63a60a3423a..e73c2f9216e 100644 --- a/boards/snps/nsim/arc_classic/nsim_nsim_hs5x_smp_12cores.yaml +++ b/boards/snps/nsim/arc_classic/nsim_nsim_hs5x_smp_12cores.yaml @@ -1,8 +1,9 @@ identifier: nsim/nsim_hs5x/smp/12cores name: Multi-core HS5x nSIM simulator (12 cores) type: sim -simulation: mdb-nsim -simulation_exec: mdb +simulation: + - name: mdb-nsim + exec: mdb arch: arc toolchain: - zephyr diff --git a/boards/snps/nsim/arc_classic/nsim_nsim_hs6x.yaml b/boards/snps/nsim/arc_classic/nsim_nsim_hs6x.yaml index 08d1fecc9c2..b175b159509 100644 --- a/boards/snps/nsim/arc_classic/nsim_nsim_hs6x.yaml +++ b/boards/snps/nsim/arc_classic/nsim_nsim_hs6x.yaml @@ -1,8 +1,9 @@ identifier: nsim/nsim_hs6x name: HS6x nSIM simulator type: sim -simulation: nsim -simulation_exec: nsimdrv +simulation: + - name: nsim + exec: nsimdrv arch: arc toolchain: - arcmwdt diff --git a/boards/snps/nsim/arc_classic/nsim_nsim_hs6x_smp.yaml b/boards/snps/nsim/arc_classic/nsim_nsim_hs6x_smp.yaml index 5db80b6afa1..4efcbf70f0d 100644 --- a/boards/snps/nsim/arc_classic/nsim_nsim_hs6x_smp.yaml +++ b/boards/snps/nsim/arc_classic/nsim_nsim_hs6x_smp.yaml @@ -1,8 +1,9 @@ identifier: nsim/nsim_hs6x/smp name: Multi-core HS6x nSIM simulator type: sim -simulation: mdb-nsim -simulation_exec: mdb +simulation: + - name: mdb-nsim + exec: mdb arch: arc toolchain: - cross-compile diff --git a/boards/snps/nsim/arc_classic/nsim_nsim_hs6x_smp_12cores.yaml b/boards/snps/nsim/arc_classic/nsim_nsim_hs6x_smp_12cores.yaml index 085f4bb93d5..7b82325e648 100644 --- a/boards/snps/nsim/arc_classic/nsim_nsim_hs6x_smp_12cores.yaml +++ b/boards/snps/nsim/arc_classic/nsim_nsim_hs6x_smp_12cores.yaml @@ -1,8 +1,9 @@ identifier: nsim/nsim_hs6x/smp/12cores name: Multi-core HS6x nSIM simulator (12 cores) type: sim -simulation: mdb-nsim -simulation_exec: mdb +simulation: + - name: mdb-nsim + exec: mdb arch: arc toolchain: - cross-compile diff --git a/boards/snps/nsim/arc_classic/nsim_nsim_hs_flash_xip.yaml b/boards/snps/nsim/arc_classic/nsim_nsim_hs_flash_xip.yaml index e39cfe00f9a..9e54bba4b7a 100644 --- a/boards/snps/nsim/arc_classic/nsim_nsim_hs_flash_xip.yaml +++ b/boards/snps/nsim/arc_classic/nsim_nsim_hs_flash_xip.yaml @@ -1,8 +1,9 @@ identifier: nsim/nsim_hs/flash_xip name: HS nSIM simulator (FLASH XIP) type: sim -simulation: nsim -simulation_exec: nsimdrv +simulation: + - name: nsim + exec: nsimdrv arch: arc toolchain: - zephyr diff --git a/boards/snps/nsim/arc_classic/nsim_nsim_hs_hostlink.yaml b/boards/snps/nsim/arc_classic/nsim_nsim_hs_hostlink.yaml index 6a2a224d2e6..ccda2a5884f 100644 --- a/boards/snps/nsim/arc_classic/nsim_nsim_hs_hostlink.yaml +++ b/boards/snps/nsim/arc_classic/nsim_nsim_hs_hostlink.yaml @@ -1,8 +1,9 @@ identifier: nsim/nsim_hs/hostlink name: HS3x nSIM simulator type: sim -simulation: nsim -simulation_exec: nsimdrv +simulation: + - name: nsim + exec: nsimdrv arch: arc toolchain: - zephyr diff --git a/boards/snps/nsim/arc_classic/nsim_nsim_hs_mpuv6.yaml b/boards/snps/nsim/arc_classic/nsim_nsim_hs_mpuv6.yaml index 03e5609e703..e09e257cc32 100644 --- a/boards/snps/nsim/arc_classic/nsim_nsim_hs_mpuv6.yaml +++ b/boards/snps/nsim/arc_classic/nsim_nsim_hs_mpuv6.yaml @@ -1,8 +1,9 @@ identifier: nsim/nsim_hs/mpuv6 name: HS (with MPU v6) nSIM simulator type: sim -simulation: nsim -simulation_exec: nsimdrv +simulation: + - name: nsim + exec: nsimdrv arch: arc toolchain: - zephyr diff --git a/boards/snps/nsim/arc_classic/nsim_nsim_hs_smp.yaml b/boards/snps/nsim/arc_classic/nsim_nsim_hs_smp.yaml index 50f910e3f8c..977a13826d0 100644 --- a/boards/snps/nsim/arc_classic/nsim_nsim_hs_smp.yaml +++ b/boards/snps/nsim/arc_classic/nsim_nsim_hs_smp.yaml @@ -1,8 +1,9 @@ identifier: nsim/nsim_hs/smp name: Multi-core HS nSIM simulator type: sim -simulation: mdb-nsim -simulation_exec: mdb +simulation: + - name: mdb-nsim + exec: mdb arch: arc toolchain: - zephyr diff --git a/boards/snps/nsim/arc_classic/nsim_nsim_hs_sram.yaml b/boards/snps/nsim/arc_classic/nsim_nsim_hs_sram.yaml index f2d8a0e8bd9..10e7d6929a6 100644 --- a/boards/snps/nsim/arc_classic/nsim_nsim_hs_sram.yaml +++ b/boards/snps/nsim/arc_classic/nsim_nsim_hs_sram.yaml @@ -1,8 +1,9 @@ identifier: nsim/nsim_hs/sram name: HS nSIM simulator (SRAM) type: sim -simulation: nsim -simulation_exec: nsimdrv +simulation: + - name: nsim + exec: nsimdrv arch: arc toolchain: - zephyr diff --git a/boards/snps/nsim/arc_classic/nsim_nsim_sem.dts b/boards/snps/nsim/arc_classic/nsim_nsim_sem.dts index de118195e3e..807d54ba698 100644 --- a/boards/snps/nsim/arc_classic/nsim_nsim_sem.dts +++ b/boards/snps/nsim/arc_classic/nsim_nsim_sem.dts @@ -4,27 +4,14 @@ * SPDX-License-Identifier: Apache-2.0 */ - /dts-v1/; +#define ICCM_SIZE DT_SIZE_K(256) +#define DCCM_SIZE DT_SIZE_K(256) + #include "nsim_em-sec.dtsi" / { - - model = "nsim_sem"; + model = "snps,nsim_sem"; compatible = "snps,nsim_sem"; - - iccm0: iccm@0 { - compatible = "arc,iccm"; - reg = <0x0 0x40000>; - }; - - dccm0: dccm@80000000 { - compatible = "arc,dccm"; - reg = <0x80000000 0x40000>; - }; - - chosen { - zephyr,sram = &dccm0; - }; }; diff --git a/boards/snps/nsim/arc_classic/nsim_nsim_sem.yaml b/boards/snps/nsim/arc_classic/nsim_nsim_sem.yaml index fadc0783f72..cc114d849af 100644 --- a/boards/snps/nsim/arc_classic/nsim_nsim_sem.yaml +++ b/boards/snps/nsim/arc_classic/nsim_nsim_sem.yaml @@ -1,9 +1,10 @@ identifier: nsim/nsim_sem -name: SEM Nsim simulator +name: SEM nSIM simulator type: sim arch: arc -simulation: nsim -simulation_exec: nsimdrv +simulation: + - name: nsim + exec: nsimdrv toolchain: - zephyr - cross-compile diff --git a/boards/snps/nsim/arc_classic/nsim_nsim_sem_mpu_stack_guard.dts b/boards/snps/nsim/arc_classic/nsim_nsim_sem_mpu_stack_guard.dts index 4b1c02279c7..a5d01055853 100644 --- a/boards/snps/nsim/arc_classic/nsim_nsim_sem_mpu_stack_guard.dts +++ b/boards/snps/nsim/arc_classic/nsim_nsim_sem_mpu_stack_guard.dts @@ -6,9 +6,12 @@ /dts-v1/; +#define ICCM_SIZE DT_SIZE_K(512) +#define DCCM_SIZE DT_SIZE_K(512) + #include "nsim_em-sec.dtsi" / { - model = "snps,nsim_sem_mpu_stack_guard"; - compatible = "snps,nsim_sem_mpu_stack_guard.dts"; + model = "snps,nsim_sem"; + compatible = "snps,nsim_sem"; }; diff --git a/boards/snps/nsim/arc_classic/nsim_nsim_sem_mpu_stack_guard.yaml b/boards/snps/nsim/arc_classic/nsim_nsim_sem_mpu_stack_guard.yaml index 986345ab8e0..7eb893a505e 100644 --- a/boards/snps/nsim/arc_classic/nsim_nsim_sem_mpu_stack_guard.yaml +++ b/boards/snps/nsim/arc_classic/nsim_nsim_sem_mpu_stack_guard.yaml @@ -2,8 +2,9 @@ identifier: nsim/nsim_sem/mpu_stack_guard name: SEM nSIM simulator (stack guard) type: sim arch: arc -simulation: nsim -simulation_exec: nsimdrv +simulation: + - name: nsim + exec: nsimdrv toolchain: - zephyr - cross-compile diff --git a/boards/snps/nsim/arc_classic/nsim_nsim_vpx5.yaml b/boards/snps/nsim/arc_classic/nsim_nsim_vpx5.yaml index b1169acd111..894288daa34 100644 --- a/boards/snps/nsim/arc_classic/nsim_nsim_vpx5.yaml +++ b/boards/snps/nsim/arc_classic/nsim_nsim_vpx5.yaml @@ -1,8 +1,9 @@ identifier: nsim/nsim_vpx5 name: VPX5 nSIM simulator type: sim -simulation: nsim -simulation_exec: nsimdrv +simulation: + - name: nsim + exec: nsimdrv arch: arc toolchain: - arcmwdt diff --git a/boards/snps/nsim/arc_classic/support/mdb_em7d_v22.args b/boards/snps/nsim/arc_classic/support/mdb_em7d_v22.args index ea1fa9efbfe..e827823df82 100644 --- a/boards/snps/nsim/arc_classic/support/mdb_em7d_v22.args +++ b/boards/snps/nsim/arc_classic/support/mdb_em7d_v22.args @@ -38,10 +38,10 @@ -dcache_feature=2 -icache=16384,32,2,a -icache_feature=2 - -dccm_size=0x80000 + -dccm_size=0x20000 -dccm_base=0x80000000 -dccm_interleave - -iccm0_size=0x80000 + -iccm0_size=0x40000 -iccm0_base=0x00000000 -Xpct_counters=8 -dmac diff --git a/boards/snps/nsim/arc_classic/support/mdb_hs.args b/boards/snps/nsim/arc_classic/support/mdb_hs.args index b53cdd69221..9b513b6000e 100644 --- a/boards/snps/nsim/arc_classic/support/mdb_hs.args +++ b/boards/snps/nsim/arc_classic/support/mdb_hs.args @@ -34,11 +34,11 @@ -dcache_mem_cycles=2 -icache=65536,64,4,a -icache_feature=2 - -dccm_size=0x40000 + -dccm_size=0x100000 -dccm_base=0x80000000 -dccm_mem_cycles=2 - -iccm0_size=0x40000 - -iccm0_base=0x70000000 + -iccm0_size=0x100000 + -iccm0_base=0x00000000 -mpuv3 -mpu_regions=16 -prop=nsim_mem-dev=uart0,kind=dwuart,base=0xf0000000,irq=24 diff --git a/boards/snps/nsim/arc_classic/support/mdb_hs_hostlink.args b/boards/snps/nsim/arc_classic/support/mdb_hs_hostlink.args index 322ab33998a..2676357f3d0 100644 --- a/boards/snps/nsim/arc_classic/support/mdb_hs_hostlink.args +++ b/boards/snps/nsim/arc_classic/support/mdb_hs_hostlink.args @@ -34,11 +34,11 @@ -dcache_mem_cycles=2 -icache=65536,64,4,a -icache_feature=2 - -dccm_size=0x40000 + -dccm_size=0x100000 -dccm_base=0x80000000 -dccm_mem_cycles=2 - -iccm0_size=0x40000 - -iccm0_base=0x70000000 + -iccm0_size=0x100000 + -iccm0_base=0x00000000 -mpuv3 -mpu_regions=16 -noprofile diff --git a/boards/snps/nsim/arc_classic/support/mdb_hs_mpuv6.args b/boards/snps/nsim/arc_classic/support/mdb_hs_mpuv6.args index 5f7a5a98e69..64c68a917cd 100644 --- a/boards/snps/nsim/arc_classic/support/mdb_hs_mpuv6.args +++ b/boards/snps/nsim/arc_classic/support/mdb_hs_mpuv6.args @@ -39,7 +39,7 @@ -dccm_size=0x100000 -dccm_base=0x80000000 -dccm_mem_cycles=2 - -iccm0_size=0x40000 - -iccm0_base=0x70000000 + -iccm0_size=0x100000 + -iccm0_base=0x00000000 -prop=nsim_mem-dev=uart0,kind=dwuart,base=0xf0000000,irq=24 -noprofile diff --git a/boards/snps/nsim/arc_classic/support/nsim_hs.props b/boards/snps/nsim/arc_classic/support/nsim_hs.props index 56eb627e670..6482a379a0d 100644 --- a/boards/snps/nsim/arc_classic/support/nsim_hs.props +++ b/boards/snps/nsim/arc_classic/support/nsim_hs.props @@ -41,8 +41,8 @@ dccm_size=0x100000 dccm_base=0x80000000 nsim_isa_dccm_mem_cycles=2 - iccm0_size=0x40000 - iccm0_base=0x70000000 + iccm0_size=0x100000 + iccm0_base=0x00000000 mpu_regions=16 mpu_version=3 nsim_mem-dev=uart0,kind=dwuart,base=0xf0000000,irq=24 diff --git a/boards/snps/nsim/arc_classic/support/nsim_hs_hostlink.props b/boards/snps/nsim/arc_classic/support/nsim_hs_hostlink.props index 9c96ba18083..c1afff58cf2 100644 --- a/boards/snps/nsim/arc_classic/support/nsim_hs_hostlink.props +++ b/boards/snps/nsim/arc_classic/support/nsim_hs_hostlink.props @@ -41,7 +41,7 @@ dccm_size=0x100000 dccm_base=0x80000000 nsim_isa_dccm_mem_cycles=2 - iccm0_size=0x40000 - iccm0_base=0x70000000 + iccm0_size=0x100000 + iccm0_base=0x00000000 mpu_regions=16 mpu_version=3 diff --git a/boards/snps/nsim/arc_classic/support/nsim_hs_mpuv6.props b/boards/snps/nsim/arc_classic/support/nsim_hs_mpuv6.props index 9556ec1105e..faa3b7f4163 100644 --- a/boards/snps/nsim/arc_classic/support/nsim_hs_mpuv6.props +++ b/boards/snps/nsim/arc_classic/support/nsim_hs_mpuv6.props @@ -43,6 +43,6 @@ dccm_size=0x100000 dccm_base=0x80000000 nsim_isa_dccm_mem_cycles=2 - iccm0_size=0x40000 - iccm0_base=0x70000000 + iccm0_size=0x100000 + iccm0_base=0x00000000 nsim_mem-dev=uart0,kind=dwuart,base=0xf0000000,irq=24 diff --git a/boards/snps/nsim/arc_v/doc/index.rst b/boards/snps/nsim/arc_v/doc/index.rst index 22a0ecc23e9..a0bc41c2be7 100644 --- a/boards/snps/nsim/arc_v/doc/index.rst +++ b/boards/snps/nsim/arc_v/doc/index.rst @@ -1,7 +1,4 @@ -.. _nsim_arc_v: - -DesignWare RISC-V nSIM and HAPS FPGA boards -########################################### +.. zephyr:board:: nsim_arc_v Overview ******** @@ -20,7 +17,7 @@ Supported board targets for that platform are listed below: .. _board_nsim_arc_v_prop_files: It is recommended to look at precise description of a particular board target in ``.props`` -files in :zephyr_file:`boards/snps/nsim_arc_v/support/` directory to understand +files in :zephyr_file:`boards/snps/nsim/arc_v/support/` directory to understand which options are configured and so will be used on invocation of the simulator. .. warning:: @@ -43,7 +40,7 @@ Most board targets support building with both GNU and ARC MWDT toolchains, howev there might be exceptions from that, especially for newly added targets. You can check supported toolchains for the board targets in the corresponding ``.yaml`` file. -I.e. for the ``nsim_arc_v/rmx100`` board we can check :zephyr_file:`boards/snps/nsim_arc_v/nsim_arc_v_rmx100.yaml` +I.e. for the ``nsim_arc_v/rmx100`` board we can check :zephyr_file:`boards/snps/nsim/arc_v/nsim_arc_v_rmx100.yaml` The supported toolchains are listed in ``toolchain:`` array in ``.yaml`` file, where we can find: @@ -193,6 +190,8 @@ on SoC level. References ********** +.. target-notes:: + .. _Designware ARC nSIM: https://www.synopsys.com/dw/ipdir.php?ds=sim_nsim .. _DesignWare ARC Free nSIM: https://www.synopsys.com/cgi-bin/dwarcnsim/req1.cgi .. _HAPS: https://www.synopsys.com/verification/prototyping/haps.html diff --git a/boards/snps/nsim/arc_v/nsim_arc_v_rmx100.yaml b/boards/snps/nsim/arc_v/nsim_arc_v_rmx100.yaml index 3639ab453f8..6070498da81 100644 --- a/boards/snps/nsim/arc_v/nsim_arc_v_rmx100.yaml +++ b/boards/snps/nsim/arc_v/nsim_arc_v_rmx100.yaml @@ -1,7 +1,8 @@ identifier: nsim_arc_v/rmx100 name: Synopsys rmx100 -simulation: nsim -simulation_exec: nsimdrv +simulation: + - name: nsim + exec: nsimdrv type: sim arch: riscv toolchain: diff --git a/boards/sparkfun/micromod/Kconfig.defconfig b/boards/sparkfun/micromod/Kconfig.defconfig index 50f6c3f582a..41cda3e459a 100644 --- a/boards/sparkfun/micromod/Kconfig.defconfig +++ b/boards/sparkfun/micromod/Kconfig.defconfig @@ -5,7 +5,4 @@ if BOARD_MICROMOD_NRF52840 -config BT_CTLR - default BT - endif # BOARD_MICROMOD_NRF52840 diff --git a/boards/sparkfun/micromod/micromod_nrf52840.yaml b/boards/sparkfun/micromod/micromod_nrf52840.yaml index 3afd6269313..520d9607d5e 100644 --- a/boards/sparkfun/micromod/micromod_nrf52840.yaml +++ b/boards/sparkfun/micromod/micromod_nrf52840.yaml @@ -17,7 +17,6 @@ supported: - pwm - adc - usb_device - - usb_cdc - watchdog - micromod_gpio - micromod_uart diff --git a/boards/sparkfun/nrf52_sparkfun/Kconfig.defconfig b/boards/sparkfun/nrf52_sparkfun/Kconfig.defconfig index 47d8a99ceca..415fd0eb5b5 100644 --- a/boards/sparkfun/nrf52_sparkfun/Kconfig.defconfig +++ b/boards/sparkfun/nrf52_sparkfun/Kconfig.defconfig @@ -6,7 +6,4 @@ if BOARD_NRF52_SPARKFUN -config BT_CTLR - default BT - endif # BOARD_NRF52_SPARKFUN diff --git a/boards/sparkfun/pro_micro_rp2040/Kconfig b/boards/sparkfun/pro_micro_rp2040/Kconfig new file mode 100644 index 00000000000..08105807953 --- /dev/null +++ b/boards/sparkfun/pro_micro_rp2040/Kconfig @@ -0,0 +1,5 @@ +# Copyright (c) 2021 Pete Johanson +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_SPARKFUN_PRO_MICRO_RP2040 + select RP2_FLASH_W25Q080 diff --git a/boards/sparkfun/pro_micro_rp2040/Kconfig.defconfig b/boards/sparkfun/pro_micro_rp2040/Kconfig.defconfig index 57aecafff00..89f13a15cd5 100644 --- a/boards/sparkfun/pro_micro_rp2040/Kconfig.defconfig +++ b/boards/sparkfun/pro_micro_rp2040/Kconfig.defconfig @@ -3,9 +3,6 @@ if BOARD_SPARKFUN_PRO_MICRO_RP2040 -config RP2_FLASH_W25Q080 - default y - if I2C_DW config I2C_DW_CLOCK_SPEED diff --git a/boards/sparkfun/pro_micro_rp2040/board.cmake b/boards/sparkfun/pro_micro_rp2040/board.cmake index 7d557630b9b..9add174b565 100644 --- a/boards/sparkfun/pro_micro_rp2040/board.cmake +++ b/boards/sparkfun/pro_micro_rp2040/board.cmake @@ -16,7 +16,7 @@ # The value must be the 'stem' part of the name of one of the files # in the openocd interface configuration file. # The setting is store to CMakeCache.txt. -if ("${RPI_PICO_DEBUG_ADAPTER}" STREQUAL "") +if("${RPI_PICO_DEBUG_ADAPTER}" STREQUAL "") set(RPI_PICO_DEBUG_ADAPTER "cmsis-dap") endif() diff --git a/boards/sparkfun/pro_micro_rp2040/doc/index.rst b/boards/sparkfun/pro_micro_rp2040/doc/index.rst index f538a04b1ce..6932147e862 100644 --- a/boards/sparkfun/pro_micro_rp2040/doc/index.rst +++ b/boards/sparkfun/pro_micro_rp2040/doc/index.rst @@ -103,8 +103,8 @@ Default Zephyr Peripheral Mapping: - I2C1_SDA : P2 - I2C1_SCL : P3 - SPI0_RX : P20 -- SPI0_SCK : P18 -- SPI0_TX : P19 +- SPI0_SCK : P22 +- SPI0_TX : P23 Programming and Debugging ************************* diff --git a/boards/sparkfun/pro_micro_rp2040/sparkfun_pro_micro_rp2040-pinctrl.dtsi b/boards/sparkfun/pro_micro_rp2040/sparkfun_pro_micro_rp2040-pinctrl.dtsi index 5b9c353f802..072770e1339 100644 --- a/boards/sparkfun/pro_micro_rp2040/sparkfun_pro_micro_rp2040-pinctrl.dtsi +++ b/boards/sparkfun/pro_micro_rp2040/sparkfun_pro_micro_rp2040-pinctrl.dtsi @@ -29,14 +29,14 @@ spi0_default: spi0_default { group1 { - pinmux = ; + pinmux = ; }; group2 { pinmux = ; input-enable; }; group3 { - pinmux = ; + pinmux = ; }; }; @@ -47,9 +47,6 @@ }; }; - clocks_default: clocks_default { - }; - ws2812_pio0_default: ws2812_pio_default { ws2812 { pinmux = ; diff --git a/boards/sparkfun/pro_micro_rp2040/sparkfun_pro_micro_rp2040.dts b/boards/sparkfun/pro_micro_rp2040/sparkfun_pro_micro_rp2040.dts index 43761b85a14..999da056095 100644 --- a/boards/sparkfun/pro_micro_rp2040/sparkfun_pro_micro_rp2040.dts +++ b/boards/sparkfun/pro_micro_rp2040/sparkfun_pro_micro_rp2040.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include +#include #include "sparkfun_pro_micro_rp2040-pinctrl.dtsi" #include "sparkfun_pro_micro_connector.dtsi" #include @@ -58,11 +58,6 @@ }; }; -&clocks { - pinctrl-0 = <&clocks_default>; - pinctrl-names = "default"; -}; - &uart0 { current-speed = <115200>; status = "okay"; diff --git a/boards/sparkfun/red_v_things_plus/sparkfun_red_v_things_plus_defconfig b/boards/sparkfun/red_v_things_plus/sparkfun_red_v_things_plus_defconfig index 2085c58676a..db9df36022c 100644 --- a/boards/sparkfun/red_v_things_plus/sparkfun_red_v_things_plus_defconfig +++ b/boards/sparkfun/red_v_things_plus/sparkfun_red_v_things_plus_defconfig @@ -2,7 +2,6 @@ # SPDX-License-Identifier: Apache-2.0 CONFIG_GPIO=y -CONFIG_PINCTRL=y CONFIG_CONSOLE=y CONFIG_SERIAL=y CONFIG_UART_SIFIVE_PORT_0=y diff --git a/boards/sparkfun/thing_plus_matter_mgm240p/Kconfig.defconfig b/boards/sparkfun/thing_plus_matter_mgm240p/Kconfig.defconfig index 9c21ba54457..1f5a3c940df 100644 --- a/boards/sparkfun/thing_plus_matter_mgm240p/Kconfig.defconfig +++ b/boards/sparkfun/thing_plus_matter_mgm240p/Kconfig.defconfig @@ -12,10 +12,6 @@ config CMU_HFXO_FREQ config CMU_LFXO_FREQ default 32768 -config FLASH_BASE_ADDRESS - hex - default 0x08000000 - if SOC_GECKO_USE_RAIL config FPU diff --git a/boards/sparkfun/thing_plus_matter_mgm240p/board.c b/boards/sparkfun/thing_plus_matter_mgm240p/board.c index 6578e872700..beb2b540294 100644 --- a/boards/sparkfun/thing_plus_matter_mgm240p/board.c +++ b/boards/sparkfun/thing_plus_matter_mgm240p/board.c @@ -10,22 +10,13 @@ #include #include -#ifdef CONFIG_SOC_GECKO_DEV_INIT -#include "em_cmu.h" -#endif - LOG_MODULE_REGISTER(sparkfun_thing_plus_mgm240p, CONFIG_BOARD_SPARKFUN_THING_PLUS_MATTER_MGM240P_LOG_LEVEL); -static int sparkfun_thing_plus_mgm240p_init_clocks(void); - static int sparkfun_thing_plus_mgm240p_init(void) { int ret; -#ifdef CONFIG_SOC_GECKO_DEV_INIT - sparkfun_thing_plus_mgm240p_init_clocks(); -#endif static struct gpio_dt_spec wake_up_gpio_dev = GPIO_DT_SPEC_GET(DT_NODELABEL(wake_up_trigger), gpios); @@ -42,32 +33,5 @@ static int sparkfun_thing_plus_mgm240p_init(void) return 0; } -#ifdef CONFIG_SOC_GECKO_DEV_INIT -static int sparkfun_thing_plus_mgm240p_init_clocks(void) -{ - CMU_ClockSelectSet(cmuClock_SYSCLK, cmuSelect_HFRCODPLL); -#if defined(_CMU_EM01GRPACLKCTRL_MASK) - CMU_ClockSelectSet(cmuClock_EM01GRPACLK, cmuSelect_HFRCODPLL); -#endif -#if defined(_CMU_EM01GRPBCLKCTRL_MASK) - CMU_ClockSelectSet(cmuClock_EM01GRPBCLK, cmuSelect_HFRCODPLL); -#endif - CMU_ClockSelectSet(cmuClock_EM23GRPACLK, cmuSelect_LFRCO); - CMU_ClockSelectSet(cmuClock_EM4GRPACLK, cmuSelect_LFRCO); -#if defined(RTCC_PRESENT) - CMU_ClockSelectSet(cmuClock_RTCC, cmuSelect_LFRCO); -#endif -#if defined(SYSRTC_PRESENT) - CMU_ClockSelectSet(cmuClock_SYSRTC, cmuSelect_LFRCO); -#endif - CMU_ClockSelectSet(cmuClock_WDOG0, cmuSelect_LFRCO); -#if WDOG_COUNT > 1 - CMU_ClockSelectSet(cmuClock_WDOG1, cmuSelect_LFRCO); -#endif - - return 0; -} -#endif - /* needs to be done after GPIO driver init */ SYS_INIT(sparkfun_thing_plus_mgm240p_init, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE); diff --git a/boards/sparkfun/thing_plus_matter_mgm240p/doc/index.rst b/boards/sparkfun/thing_plus_matter_mgm240p/doc/index.rst index cdaed771bd8..bd91534fc79 100644 --- a/boards/sparkfun/thing_plus_matter_mgm240p/doc/index.rst +++ b/boards/sparkfun/thing_plus_matter_mgm240p/doc/index.rst @@ -1,6 +1,6 @@ .. _sparkfun_thing_plus_mgm240p: -SPARKFUN THING PLUS MATTER +SparkFun Thing Plus Matter ########################### Overview @@ -15,7 +15,7 @@ ARM Cortex®-M33F processor with excellent low power capabilities. :align: center :alt: MGM240P Sparkfun Think Plus Matter - xG24-MGM240P (image courtesy of Sparkfun) + MGM240P Sparkfun Think Plus Matter (image courtesy of Sparkfun) Hardware ******** @@ -81,7 +81,7 @@ means Pin number 2 on PORTA, as used in the board's datasheets and manuals. +-------+-------------+-------------------------------------+ The default configuration can be found in -:zephyr_file:`boards/silabs/sparkfun_thing_plus_mgm240p/sparkfun_thing_plus_mgm240p_defconfig` +:zephyr_file:`boards/sparkfun/thing_plus_matter_mgm240p/sparkfun_thing_plus_matter_mgm240p_defconfig` System Clock ============ @@ -100,7 +100,7 @@ Programming and Debugging .. note:: Before using the kit the first time, you should update the J-Link firmware - from `J-Link-Downloads`_ + in Simplicity Studio. Flashing ======== @@ -128,7 +128,7 @@ terminal session: .. code-block:: console - Hello World! _sparkfun_thing_plus_mgm240p + Hello World! _sparkfun_thing_plus_matter_mgm240p Bluetooth ========= @@ -146,7 +146,7 @@ this example. .. zephyr-app-commands:: :zephyr-app: samples/bluetooth/observer - :board: sparkfun_thing_plus_mgm240p + :board: sparkfun_thing_plus_matter_mgm240p :goals: build .. _EFR32MG24 Website: @@ -163,6 +163,3 @@ this example. .. _MGM240P Schematics: https://cdn.sparkfun.com/assets/0/f/8/4/9/Thing_Plus_MGM240P.pdf - -.. _J-Link-Downloads: - https://www.segger.com/downloads/jlink diff --git a/boards/sparkfun/thing_plus_matter_mgm240p/sparkfun_thing_plus_matter_mgm240p-pinctrl.dtsi b/boards/sparkfun/thing_plus_matter_mgm240p/sparkfun_thing_plus_matter_mgm240p-pinctrl.dtsi index 4e6cb746f80..2fd6fc8674c 100644 --- a/boards/sparkfun/thing_plus_matter_mgm240p/sparkfun_thing_plus_matter_mgm240p-pinctrl.dtsi +++ b/boards/sparkfun/thing_plus_matter_mgm240p/sparkfun_thing_plus_matter_mgm240p-pinctrl.dtsi @@ -5,25 +5,40 @@ */ #include -#include +#include &pinctrl { /* configuration for uart0 device, default state */ usart0_default: usart0_default { + group0 { + pins = ; + drive-push-pull; + output-high; + }; group1 { - /* configure PA.6 as UART_RX and PA.5 as UART_TX */ - psels = , - , - ; + pins = ; + input-enable; + silabs,input-filter; }; }; - i2c0_default: i2c0_default { + eusart1_default: eusart1_default { + group0 { + pins = , , ; + drive-push-pull; + output-high; + }; group1 { - psels = , - , - , - ; + pins = ; + input-enable; + }; + }; + + i2c0_default: i2c0_default { + group0 { + pins = , ; + drive-open-drain; + bias-pull-up; }; }; diff --git a/boards/sparkfun/thing_plus_matter_mgm240p/sparkfun_thing_plus_matter_mgm240p.dts b/boards/sparkfun/thing_plus_matter_mgm240p/sparkfun_thing_plus_matter_mgm240p.dts index e0352730d30..05db65eb187 100644 --- a/boards/sparkfun/thing_plus_matter_mgm240p/sparkfun_thing_plus_matter_mgm240p.dts +++ b/boards/sparkfun/thing_plus_matter_mgm240p/sparkfun_thing_plus_matter_mgm240p.dts @@ -9,6 +9,7 @@ #include #include "sparkfun_thing_plus_matter_mgm240p-pinctrl.dtsi" #include +#include / { model = "Sparkfun MGM240P (Sparkfun Thing Plus Matter)"; @@ -25,20 +26,21 @@ aliases { led0 = &blue_led; + spi0 = &eusart1; watchdog0 = &wdog0; }; leds { compatible = "gpio-leds"; blue_led: led_1 { - gpios = <&gpioa GECKO_PIN(8) GPIO_ACTIVE_LOW>; + gpios = <&gpioa 8 GPIO_ACTIVE_LOW>; }; }; wake_up_trigger: gpio-wake-up { compatible = "silabs,gecko-wake-up-trigger"; - gpios = <&gpioa GECKO_PIN(5) GPIO_ACTIVE_LOW>; + gpios = <&gpioa 5 GPIO_ACTIVE_LOW>; }; }; @@ -47,12 +49,40 @@ clock-frequency = <78000000>; }; +&hfxo { + status = "okay"; + ctune = <140>; + precision = <50>; +}; + +&hfrcodpll { + clock-frequency = ; + clocks = <&hfxo>; + dpll-n = <3839>; + dpll-m = <1919>; + dpll-edge = "fall"; + dpll-lock = "phase"; + dpll-autorecover; +}; + &usart0 { current-speed = <115200>; pinctrl-0 = <&usart0_default>; pinctrl-names = "default"; status = "okay"; }; + +&eusart1 { + compatible = "silabs,gecko-spi-eusart"; + + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&eusart1_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + &i2c0 { pinctrl-0 = <&i2c0_default>; pinctrl-names = "default"; @@ -88,6 +118,13 @@ status = "okay"; }; +&dcdc { + status = "okay"; + regulator-boot-on; + regulator-initial-mode = ; + silabs,pfmx-peak-current-milliamp = <50>; +}; + &flash0 { partitions { compatible = "fixed-partitions"; diff --git a/boards/sparkfun/thing_plus_matter_mgm240p/sparkfun_thing_plus_matter_mgm240p.yaml b/boards/sparkfun/thing_plus_matter_mgm240p/sparkfun_thing_plus_matter_mgm240p.yaml index 87bea1b9315..392fbb38fb9 100644 --- a/boards/sparkfun/thing_plus_matter_mgm240p/sparkfun_thing_plus_matter_mgm240p.yaml +++ b/boards/sparkfun/thing_plus_matter_mgm240p/sparkfun_thing_plus_matter_mgm240p.yaml @@ -14,6 +14,7 @@ supported: - uart - spi - watchdog + - clock_control testing: ignore_tags: - net diff --git a/boards/sparkfun/thing_plus_matter_mgm240p/sparkfun_thing_plus_matter_mgm240p_defconfig b/boards/sparkfun/thing_plus_matter_mgm240p/sparkfun_thing_plus_matter_mgm240p_defconfig index 6ab4ff4cdaa..fee02fbc812 100644 --- a/boards/sparkfun/thing_plus_matter_mgm240p/sparkfun_thing_plus_matter_mgm240p_defconfig +++ b/boards/sparkfun/thing_plus_matter_mgm240p/sparkfun_thing_plus_matter_mgm240p_defconfig @@ -6,13 +6,9 @@ CONFIG_ARM_MPU=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y -CONFIG_CORTEX_M_SYSTICK=y CONFIG_GPIO=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=76800000 -CONFIG_CMU_HFCLK_HFXO=y CONFIG_SOC_GECKO_EMU_DCDC=y CONFIG_SOC_GECKO_EMU_DCDC_MODE_ON=y -CONFIG_CMU_HFCLK_LFXO=y CONFIG_HW_STACK_PROTECTION=y -CONFIG_PINCTRL=y CONFIG_REGULATOR=y diff --git a/boards/st/b_g474e_dpow1/b_g474e_dpow1.dts b/boards/st/b_g474e_dpow1/b_g474e_dpow1.dts index 1eb84827718..3c20afabc64 100644 --- a/boards/st/b_g474e_dpow1/b_g474e_dpow1.dts +++ b/boards/st/b_g474e_dpow1/b_g474e_dpow1.dts @@ -134,7 +134,7 @@ stm32_lp_tick_source: &lptim1 { &adc2 { pinctrl-0 = <&adc2_in8_pc2>; pinctrl-names = "default"; - st,adc-clock-source = ; + st,adc-clock-source = "SYNC"; st,adc-prescaler = <4>; status = "okay"; diff --git a/boards/st/b_g474e_dpow1/b_g474e_dpow1.yaml b/boards/st/b_g474e_dpow1/b_g474e_dpow1.yaml index b27446b1beb..ff6b032e815 100644 --- a/boards/st/b_g474e_dpow1/b_g474e_dpow1.yaml +++ b/boards/st/b_g474e_dpow1/b_g474e_dpow1.yaml @@ -13,6 +13,5 @@ supported: - gpio - watchdog - tcpc - - usb - usbd vendor: st diff --git a/boards/st/b_g474e_dpow1/doc/index.rst b/boards/st/b_g474e_dpow1/doc/index.rst index 7e1f584b522..b130b728663 100644 --- a/boards/st/b_g474e_dpow1/doc/index.rst +++ b/boards/st/b_g474e_dpow1/doc/index.rst @@ -1,7 +1,4 @@ -.. _b_g474e_dpow1_board: - -ST B-G474E-DPOW1 Discovery -########################## +.. zephyr:board:: b_g474e_dpow1 Overview ******** @@ -34,10 +31,6 @@ the STLINK-V3E debugger and programmer. - On-board STLINK-V3E debugger/programmer with USB re-enumeration capability: mass storage, Virtual COM port, and debug port -.. image:: img/b_g474e_dpow1.jpg - :align: center - :alt: B-G474E-DPOW1 - More information about the board can be found at the `B-G474E-DPOW1 website`_. diff --git a/boards/st/b_l072z_lrwan1/doc/index.rst b/boards/st/b_l072z_lrwan1/doc/index.rst index 527461c24a4..06385429700 100644 --- a/boards/st/b_l072z_lrwan1/doc/index.rst +++ b/boards/st/b_l072z_lrwan1/doc/index.rst @@ -1,7 +1,4 @@ -.. _b_l072z_lrwan1_board: - -ST B-L072Z-LRWAN1 Discovery kit -############################### +.. zephyr:board:: b_l072z_lrwan1 Overview ******** @@ -53,10 +50,6 @@ This kit provides: - 2 push-buttons (user and reset) - Arduino* Uno V3 connectors -.. image:: img/b_l072z_lrwan1.jpg - :align: center - :alt: B-L072Z-LRWAN1 - More information about the board can be found at the `B-L072Z-LRWAN1 website`_. Hardware diff --git a/boards/st/b_l4s5i_iot01a/Kconfig.defconfig b/boards/st/b_l4s5i_iot01a/Kconfig.defconfig index 317d096e0ce..8e2d927cf94 100644 --- a/boards/st/b_l4s5i_iot01a/Kconfig.defconfig +++ b/boards/st/b_l4s5i_iot01a/Kconfig.defconfig @@ -24,12 +24,6 @@ endchoice if BT -config SPI - default y - -config BT_SPI - default y - config BT_BLUENRG_ACI default y # Disable Flow control diff --git a/boards/st/b_l4s5i_iot01a/b_l4s5i_iot01a.dts b/boards/st/b_l4s5i_iot01a/b_l4s5i_iot01a.dts index d41c75c44bf..d7f5adab5be 100644 --- a/boards/st/b_l4s5i_iot01a/b_l4s5i_iot01a.dts +++ b/boards/st/b_l4s5i_iot01a/b_l4s5i_iot01a.dts @@ -181,31 +181,23 @@ boot_partition: partition@0 { label = "mcuboot"; - reg = <0x00000000 DT_SIZE_K(64)>; + reg = <0x0 DT_SIZE_K(64)>; read-only; }; - /* - * The flash starting at offset 0x10000 and ending at - * offset 0x1ffff is reserved for use by the application. - */ - - slot0_partition: partition@20000 { + slot0_partition: partition@10000 { label = "image-0"; - reg = <0x00020000 DT_SIZE_K(432)>; + reg = <0x10000 DT_SIZE_K(976)>; }; - slot1_partition: partition@8c000 { + + slot1_partition: partition@104000 { label = "image-1"; - reg = <0x0008C000 DT_SIZE_K(432)>; - }; - scratch_partition: partition@f8000 { - label = "image-scratch"; - reg = <0x000F8000 DT_SIZE_K(16)>; + reg = <0x104000 DT_SIZE_K(976)>; }; - storage_partition: partition@fc000 { + storage_partition: partition@1f8000 { label = "storage"; - reg = <0x000fc000 DT_SIZE_K(16)>; + reg = <0x1f8000 DT_SIZE_K(32)>; }; }; }; diff --git a/boards/st/b_l4s5i_iot01a/b_l4s5i_iot01a.yaml b/boards/st/b_l4s5i_iot01a/b_l4s5i_iot01a.yaml index 63b445b8038..d0928a8aa1d 100644 --- a/boards/st/b_l4s5i_iot01a/b_l4s5i_iot01a.yaml +++ b/boards/st/b_l4s5i_iot01a/b_l4s5i_iot01a.yaml @@ -6,7 +6,7 @@ toolchain: - zephyr - gnuarmemb - xtools -ram: 640 +ram: 192 flash: 2048 supported: - arduino_gpio diff --git a/boards/st/b_l4s5i_iot01a/doc/index.rst b/boards/st/b_l4s5i_iot01a/doc/index.rst index fb1620c672d..83a6dcd1e8a 100644 --- a/boards/st/b_l4s5i_iot01a/doc/index.rst +++ b/boards/st/b_l4s5i_iot01a/doc/index.rst @@ -1,7 +1,4 @@ -.. _b_l4s5i_iot01a_board: - -ST B_L4S5I_IOT01A Discovery kit -############################### +.. zephyr:board:: b_l4s5i_iot01a Overview ******** @@ -40,10 +37,6 @@ some highlights of the B_L4S5I_IOT01A Discovery kit: - External 5 V -.. image:: img/b-l4s5i_iot01a.jpg - :align: center - :alt: B_L4S5I_IOT01A Discovery kit - More information about the board can be found at the `B L4S5I IOT01A Discovery kit website`_. Hardware diff --git a/boards/st/b_u585i_iot02a/b_u585i_iot02a-common.dtsi b/boards/st/b_u585i_iot02a/b_u585i_iot02a-common.dtsi index c8d5ca4b790..39a42c9934a 100644 --- a/boards/st/b_u585i_iot02a/b_u585i_iot02a-common.dtsi +++ b/boards/st/b_u585i_iot02a/b_u585i_iot02a-common.dtsi @@ -223,7 +223,7 @@ zephyr_udc0: &usbotg_fs { &adc1 { pinctrl-0 = <&adc1_in15_pb0>; pinctrl-names = "default"; - st,adc-clock-source = ; + st,adc-clock-source = "ASYNC"; st,adc-prescaler = <4>; status = "okay"; }; @@ -231,7 +231,7 @@ zephyr_udc0: &usbotg_fs { &adc4 { pinctrl-0 = <&adc4_in19_pb1>; pinctrl-names = "default"; - st,adc-clock-source = ; + st,adc-clock-source = "ASYNC"; st,adc-prescaler = <4>; status = "okay"; }; diff --git a/boards/st/b_u585i_iot02a/doc/index.rst b/boards/st/b_u585i_iot02a/doc/index.rst index 2400f75e3d1..c9d9378444a 100644 --- a/boards/st/b_u585i_iot02a/doc/index.rst +++ b/boards/st/b_u585i_iot02a/doc/index.rst @@ -1,7 +1,4 @@ -.. _b_u585i_iot02a_board: - -ST B_U585I_IOT02A Discovery kit -############################### +.. zephyr:board:: b_u585i_iot02a Overview ******** @@ -35,10 +32,6 @@ some highlights of the B_U585I_IOT02A Discovery kit: - External sources -.. image:: img/b-u585i-iot02a.jpg - :align: center - :alt: B_U585I_IOT02A Discovery kit - More information about the board can be found at the `B U585I IOT02A Discovery kit website`_. Hardware diff --git a/boards/st/disco_l475_iot1/Kconfig.defconfig b/boards/st/disco_l475_iot1/Kconfig.defconfig index 808425eae05..68ede55faae 100644 --- a/boards/st/disco_l475_iot1/Kconfig.defconfig +++ b/boards/st/disco_l475_iot1/Kconfig.defconfig @@ -24,12 +24,6 @@ endchoice if BT -config SPI - default y - -config BT_SPI - default y - config BT_BLUENRG_ACI default y # Disable Flow control diff --git a/boards/st/disco_l475_iot1/disco_l475_iot1.dts b/boards/st/disco_l475_iot1/disco_l475_iot1.dts index fbea236337d..6ffb6950124 100644 --- a/boards/st/disco_l475_iot1/disco_l475_iot1.dts +++ b/boards/st/disco_l475_iot1/disco_l475_iot1.dts @@ -224,23 +224,18 @@ boot_partition: partition@0 { label = "mcuboot"; - reg = <0x00000000 DT_SIZE_K(64)>; + reg = <0x0 DT_SIZE_K(64)>; read-only; }; - /* - * The flash starting at offset 0x10000 and ending at - * offset 0x1ffff is reserved for use by the application. - */ - - slot0_partition: partition@20000 { + slot0_partition: partition@1000 { label = "image-0"; - reg = <0x00020000 DT_SIZE_K(864)>; + reg = <0x1000 DT_SIZE_K(928)>; }; - scratch_partition: partition@f8000 { - label = "image-scratch"; - reg = <0x000F8000 DT_SIZE_K(16)>; + storage_partition: partition@f8000 { + label = "storage"; + reg = <0xf8000 DT_SIZE_K(32)>; }; }; }; @@ -298,7 +293,7 @@ zephyr_udc0: &usbotg_fs { pinctrl-0 = <&adc1_in3_pc2 &adc1_in4_pc3 &adc1_in13_pc4 &adc1_in14_pc5>; pinctrl-names = "default"; - st,adc-clock-source = ; + st,adc-clock-source = "SYNC"; st,adc-prescaler = <4>; status = "okay"; }; @@ -343,8 +338,8 @@ zephyr_udc0: &usbotg_fs { reg = <0x00000000 DT_SIZE_K(864)>; }; - storage_partition: partition@d8000 { - label = "storage"; + slot2_partition: partition@d8000 { + label = "image-3"; reg = <0x000d8000 DT_SIZE_M(7)>; }; }; diff --git a/boards/st/disco_l475_iot1/doc/index.rst b/boards/st/disco_l475_iot1/doc/index.rst index 197881078a3..b301979a163 100644 --- a/boards/st/disco_l475_iot1/doc/index.rst +++ b/boards/st/disco_l475_iot1/doc/index.rst @@ -1,7 +1,4 @@ -.. _disco_l475_iot1_board: - -ST Disco L475 IOT01 (B-L475E-IOT01A) -#################################### +.. zephyr:board:: disco_l475_iot1 Overview ******** @@ -36,10 +33,6 @@ This kit provides: - mass storage, virtual COM port and debug port -.. image:: img/disco_l475_iot1.jpg - :align: center - :alt: Disco L475 IoT1 - More information about the board can be found at the `Disco L475 IoT1 website`_. Hardware diff --git a/boards/st/nucleo_c031c6/doc/index.rst b/boards/st/nucleo_c031c6/doc/index.rst index 997b60e47e6..7de1e597fac 100644 --- a/boards/st/nucleo_c031c6/doc/index.rst +++ b/boards/st/nucleo_c031c6/doc/index.rst @@ -1,7 +1,4 @@ -.. _nucleo_c031c6_board: - -ST Nucleo C031C6 -################ +.. zephyr:board:: nucleo_c031c6 Overview ******** @@ -16,10 +13,6 @@ The STM32 Nucleo board integrates the ST-LINK/V2-1 debugger and programmer. The STM32 Nucleo board comes with the STM32 comprehensive software HAL library together with various packaged software examples. -.. image:: img/nucleo_c031c6.jpg - :align: center - :alt: Nucleo C031C6 - More information about the board can be found at the `Nucleo C031C6 website`_. Hardware diff --git a/boards/st/nucleo_c031c6/nucleo_c031c6.dts b/boards/st/nucleo_c031c6/nucleo_c031c6.dts index 404c1cb2962..e14cf235121 100644 --- a/boards/st/nucleo_c031c6/nucleo_c031c6.dts +++ b/boards/st/nucleo_c031c6/nucleo_c031c6.dts @@ -117,7 +117,7 @@ &adc1 { pinctrl-0 = <&adc1_in0_pa0 &adc1_in1_pa1 &adc1_in4_pa4>; pinctrl-names = "default"; - st,adc-clock-source = ; + st,adc-clock-source = "SYNC"; st,adc-prescaler = <4>; status = "okay"; }; diff --git a/boards/st/nucleo_c071rb/Kconfig.nucleo_c071rb b/boards/st/nucleo_c071rb/Kconfig.nucleo_c071rb new file mode 100644 index 00000000000..b0c7abff956 --- /dev/null +++ b/boards/st/nucleo_c071rb/Kconfig.nucleo_c071rb @@ -0,0 +1,5 @@ +# Copyright (c) 2024 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_C071RB + select SOC_STM32C071XX diff --git a/boards/st/nucleo_c071rb/arduino_r3_connector.dtsi b/boards/st/nucleo_c071rb/arduino_r3_connector.dtsi new file mode 100644 index 00000000000..5d62471e418 --- /dev/null +++ b/boards/st/nucleo_c071rb/arduino_r3_connector.dtsi @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2024 STMicroelectronics + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + arduino_header: connector { + compatible = "arduino-header-r3"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpioa 0 0>, /* A0 */ + <1 0 &gpioa 1 0>, /* A1 */ + <2 0 &gpioa 4 0>, /* A2 */ + <3 0 &gpiob 0 0>, /* A3 */ + <4 0 &gpioc 4 0>, /* A4 */ + <5 0 &gpioc 5 0>, /* A5 */ + <6 0 &gpiob 7 0>, /* D0 */ + <7 0 &gpiob 6 0>, /* D1 */ + <8 0 &gpioa 10 0>, /* D2 */ + <9 0 &gpioc 7 0>, /* D3 */ + <10 0 &gpiob 5 0>, /* D4 */ + <11 0 &gpiob 4 0>, /* D5 */ + <12 0 &gpioc 8 0>, /* D6 */ + <13 0 &gpioa 8 0>, /* D7 */ + <14 0 &gpioa 9 0>, /* D8 */ + <15 0 &gpiob 3 0>, /* D9 */ + <16 0 &gpioa 15 0>, /* D10 */ + <17 0 &gpioa 7 0>, /* D11 */ + <18 0 &gpioa 6 0>, /* D12 */ + <19 0 &gpioa 5 0>, /* D13 */ + <20 0 &gpiob 9 0>, /* D14 */ + <21 0 &gpiob 8 0>; /* D15 */ + }; +}; + +arduino_i2c: &i2c1 {}; +arduino_spi: &spi1 {}; +arduino_serial: &usart1 {}; diff --git a/boards/st/nucleo_c071rb/board.cmake b/boards/st/nucleo_c071rb/board.cmake new file mode 100644 index 00000000000..716846e4923 --- /dev/null +++ b/boards/st/nucleo_c071rb/board.cmake @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: Apache-2.0 + +# keep first +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") + +# keep first +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/st/nucleo_c071rb/board.yml b/boards/st/nucleo_c071rb/board.yml new file mode 100644 index 00000000000..af125dd1154 --- /dev/null +++ b/boards/st/nucleo_c071rb/board.yml @@ -0,0 +1,6 @@ +board: + name: nucleo_c071rb + full_name: Nucleo C071RB + vendor: st + socs: + - name: stm32c071xx diff --git a/boards/st/nucleo_c071rb/doc/img/nucleo_c071rb.webp b/boards/st/nucleo_c071rb/doc/img/nucleo_c071rb.webp new file mode 100644 index 00000000000..2cd802b7a59 Binary files /dev/null and b/boards/st/nucleo_c071rb/doc/img/nucleo_c071rb.webp differ diff --git a/boards/st/nucleo_c071rb/doc/index.rst b/boards/st/nucleo_c071rb/doc/index.rst new file mode 100644 index 00000000000..7d4637c82a5 --- /dev/null +++ b/boards/st/nucleo_c071rb/doc/index.rst @@ -0,0 +1,163 @@ +.. zephyr:board:: nucleo_c071rb + +Overview +******** +The STM32 Nucleo-64 development board with STM32C071RB MCU, supports Arduino and ST morpho connectivity. + +The STM32 Nucleo board provides an affordable, and flexible way for users to try out new concepts, +and build prototypes with the STM32 microcontroller, choosing from the various +combinations of performance, power consumption and features. + +The STM32 Nucleo board integrates the ST-LINK/V2-1 debugger and programmer. + +The STM32 Nucleo board comes with the STM32 comprehensive software HAL library together +with various packaged software examples. + +.. image:: img/nucleo_c071rb.webp + :align: center + :alt: Nucleo C071RB + +More information about the board can be found at the `Nucleo C071RB website`_. + +Hardware +******** +Nucleo C071RB provides the following hardware components: + +- STM32 microcontroller in 64-pin package featuring 128 Kbytes of Flash memory + and 24 Kbytes of SRAM. +- Extension resource: + + - Arduino* Uno V3 connectivity + +- On-board ST-LINK/V2-1 debugger/programmer with SWD connector: + +- Flexible board power supply: + + - USB VBUS or external source (3.3V, 5V, 7 - 12V) + - Current consumption measurement (IDD) + +- Four LEDs: + + - USB communication (LD1), USB power fault LED (LD2), power LED (LD3), + user LED (LD4) + +- Two push-button: USER and RESET + +- USB re-enumeration capability. Three different interfaces supported on USB: + + - Virtual COM port + - Mass storage + - Debug port + +More information about STM32C071RB can be found here: +`STM32C0x1 reference manual`_ + +Supported Features +================== + +The Zephyr ``nucleo_c071rb`` board supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | reset and clock control | ++-----------+------------+-------------------------------------+ +| RTC | on-chip | counter | ++-----------+------------+-------------------------------------+ +| IWDG | on-chip | independent watchdog | ++-----------+------------+-------------------------------------+ +| WWDG | on-chip | window watchdog | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | ADC Controller | ++-----------+------------+-------------------------------------+ +| die-temp | on-chip | die temperature sensor | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| DMA | on-chip | Direct Memory Access | ++-----------+------------+-------------------------------------+ +| RTC | on-chip | rtc | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported in this Zephyr port. + +The default configuration can be found in +:zephyr_file:`boards/st/nucleo_c071rb/nucleo_c071rb_defconfig` + +Connections and IOs +=================== + +Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as +input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the +GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current +capable except for analog inputs. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) +- LD1 : PA5 +- LD2 : PC9 +- SPI1 NSS/SCK/MISO/MOSI : PA4/PA5/PA11/PA12 (Arduino SPI) +- UART_2 TX/RX : PA2/PA3 (ST-Link Virtual Port Com) +- USER_PB : PC13 + + +For more details please refer to `STM32 Nucleo-64 board User Manual`_. + +Programming and Debugging +************************* + +Nucleo C071RB board includes an ST-LINK/V2-1 embedded debug tool interface. + +Applications for the ``nucleo_c071rb`` board can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. + +Flashing an application to Nucleo C071RB +---------------------------------------- + +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: nucleo_c071rb + :goals: build flash + +You will see the LED blinking every second. + +References +********** + +.. target-notes:: + +.. _Nucleo C071RB website: + https://www.st.com/en/evaluation-tools/nucleo-c071rb.html + +.. _STM32C0x1 reference manual: + https://www.st.com/resource/en/reference_manual/rm0490-stm32c0x1-advanced-armbased-64bit-mcus-stmicroelectronics.pdf + +.. _STM32 Nucleo-64 board User Manual: + https://www.st.com/resource/en/user_manual/um2953-stm32c0-nucleo64-board-mb1717-stmicroelectronics.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/st/nucleo_c071rb/nucleo_c071rb.dts b/boards/st/nucleo_c071rb/nucleo_c071rb.dts new file mode 100644 index 00000000000..14ae1e59f5e --- /dev/null +++ b/boards/st/nucleo_c071rb/nucleo_c071rb.dts @@ -0,0 +1,154 @@ +/* + * Copyright (c) 2024 STMicroelectronics + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include "arduino_r3_connector.dtsi" +#include + +/ { + model = "STMicroelectronics STM32C071RB-NUCLEO board"; + compatible = "st,stm32c071rb-nucleo"; + + chosen { + zephyr,console = &usart2; + zephyr,shell-uart = &usart2; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + }; + + leds: leds { + compatible = "gpio-leds"; + green_led_1: led_1 { + gpios = <&gpioa 5 GPIO_ACTIVE_HIGH>; + label = "User LD1"; + }; + + blue_led: led_2 { + gpios = <&gpioc 9 GPIO_ACTIVE_HIGH>; + label = "User LD2"; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + + green_pwm_led: green_pwm_led { + pwms = <&pwm1 1 PWM_MSEC(20) PWM_POLARITY_NORMAL>; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + user_button: button { + label = "user button"; + gpios = <&gpioc 13 GPIO_ACTIVE_LOW>; + status = "okay"; + zephyr,code = ; + }; + }; + + aliases { + led0 = &green_led_1; + led1 = &blue_led; + pwm-led0 = &green_pwm_led; + sw0 = &user_button; + watchdog0 = &iwdg; + die-temp0 = &die_temp; + volt-sensor0 = &vref; + }; +}; + +&clk_lse { + status = "okay"; +}; + +&clk_hse { + clock-frequency = ; + status = "okay"; +}; + +&rcc { + clocks = <&clk_hse>; + clock-frequency = ; + ahb-prescaler = <1>; + apb1-prescaler = <1>; +}; + +&usart1 { + pinctrl-0 = <&usart1_tx_pb6 &usart1_rx_pb7>; + pinctrl-names = "default"; + current-speed = <115200>; + status = "okay"; +}; + +&usart2 { + pinctrl-0 = <&usart2_tx_pa2 &usart2_rx_pa3>; + pinctrl-names = "default"; + current-speed = <115200>; + status = "okay"; +}; + +&rtc { + clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000400>, + <&rcc STM32_SRC_LSE RTC_SEL(1)>; + status = "okay"; +}; + +&iwdg { + status = "okay"; +}; + +&timers1 { + st,prescaler = <10000>; + status = "okay"; + + pwm1: pwm { + pinctrl-0 = <&tim1_ch1_pa5>; + pinctrl-names = "default"; + status = "okay"; + }; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_scl_pb8 &i2c1_sda_pb9>; + pinctrl-names = "default"; + status = "okay"; + clock-frequency = ; +}; + +&spi1 { + pinctrl-0 = <&spi1_nss_pa4 &spi1_sck_pa5 + &spi1_miso_pa11 &spi1_mosi_pa12>; + pinctrl-names = "default"; + status = "okay"; +}; + +&adc1 { + pinctrl-0 = <&adc1_in0_pa0 &adc1_in1_pa1 &adc1_in4_pa4>; + pinctrl-names = "default"; + st,adc-clock-source = "SYNC"; + st,adc-prescaler = <4>; + status = "okay"; + vref-mv = <3300>; +}; + +&die_temp { + status = "okay"; +}; + +&vref { + status = "okay"; +}; + +&dma1 { + status = "okay"; +}; + +&dmamux1 { + status = "okay"; +}; diff --git a/boards/st/nucleo_c071rb/nucleo_c071rb.yaml b/boards/st/nucleo_c071rb/nucleo_c071rb.yaml new file mode 100644 index 00000000000..6332fc1bd1c --- /dev/null +++ b/boards/st/nucleo_c071rb/nucleo_c071rb.yaml @@ -0,0 +1,21 @@ +identifier: nucleo_c071rb +name: ST Nucleo C071RB +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - arduino_gpio + - counter + - dma + - gpio + - i2c + - pwm + - rtc + - spi + - watchdog +ram: 24 +flash: 128 +vendor: st diff --git a/boards/st/nucleo_c071rb/nucleo_c071rb_defconfig b/boards/st/nucleo_c071rb/nucleo_c071rb_defconfig new file mode 100644 index 00000000000..c60dfffbc3b --- /dev/null +++ b/boards/st/nucleo_c071rb/nucleo_c071rb_defconfig @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Serial Drivers +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# GPIO Controller +CONFIG_GPIO=y diff --git a/boards/st/nucleo_f030r8/doc/index.rst b/boards/st/nucleo_f030r8/doc/index.rst index 376faaa2d57..34abf6f6cb0 100644 --- a/boards/st/nucleo_f030r8/doc/index.rst +++ b/boards/st/nucleo_f030r8/doc/index.rst @@ -1,7 +1,4 @@ -.. _nucleo_f030r8_board: - -ST Nucleo F030R8 -################ +.. zephyr:board:: nucleo_f030r8 Overview ******** @@ -20,10 +17,6 @@ The STM32 Nucleo board integrates the ST-LINK/V2-1 debugger and programmer. The STM32 Nucleo board comes with the STM32 comprehensive software HAL library together with various packaged software examples. -.. image:: img/nucleo_f030r8.jpg - :align: center - :alt: Nucleo F030R8 - More information about the board can be found at the `Nucleo F030R8 website`_. Hardware diff --git a/boards/st/nucleo_f030r8/nucleo_f030r8.dts b/boards/st/nucleo_f030r8/nucleo_f030r8.dts index 3e346fc20c7..398c3ded4ba 100644 --- a/boards/st/nucleo_f030r8/nucleo_f030r8.dts +++ b/boards/st/nucleo_f030r8/nucleo_f030r8.dts @@ -118,7 +118,7 @@ &adc1 { pinctrl-0 = <&adc_in0_pa0>; pinctrl-names = "default"; - st,adc-clock-source = ; + st,adc-clock-source = "SYNC"; st,adc-prescaler = <4>; status = "okay"; }; diff --git a/boards/st/nucleo_f031k6/doc/index.rst b/boards/st/nucleo_f031k6/doc/index.rst index ba1a44d8bc4..2da4927aead 100644 --- a/boards/st/nucleo_f031k6/doc/index.rst +++ b/boards/st/nucleo_f031k6/doc/index.rst @@ -1,7 +1,4 @@ -.. _nucleo_f031k6_board: - -ST Nucleo F031K6 -################ +.. zephyr:board:: nucleo_f031k6 Overview ******** @@ -16,10 +13,6 @@ The STM32 Nucleo board integrates the ST-LINK/V2-1 debugger and programmer. The STM32 Nucleo board comes with the STM32 comprehensive software HAL library together with various packaged software examples. -.. image:: img/nucleo_f031k6.jpg - :align: center - :alt: Nucleo F031k6 - More information about the board can be found at the `Nucleo F031K6 website`_. Hardware diff --git a/boards/st/nucleo_f031k6/nucleo_f031k6.dts b/boards/st/nucleo_f031k6/nucleo_f031k6.dts index 0b5f9a04161..49669945087 100644 --- a/boards/st/nucleo_f031k6/nucleo_f031k6.dts +++ b/boards/st/nucleo_f031k6/nucleo_f031k6.dts @@ -103,7 +103,7 @@ &adc1 { pinctrl-0 = <&adc_in0_pa0>; pinctrl-names = "default"; - st,adc-clock-source = ; + st,adc-clock-source = "SYNC"; st,adc-prescaler = <4>; status = "okay"; }; diff --git a/boards/st/nucleo_f042k6/doc/index.rst b/boards/st/nucleo_f042k6/doc/index.rst index 7d0ec6e2a2b..51145f105e2 100644 --- a/boards/st/nucleo_f042k6/doc/index.rst +++ b/boards/st/nucleo_f042k6/doc/index.rst @@ -1,7 +1,4 @@ -.. _nucleo_f042k6_board: - -ST Nucleo F042K6 -################ +.. zephyr:board:: nucleo_f042k6 Overview ******** @@ -16,10 +13,6 @@ The STM32 Nucleo board integrates the ST-LINK/V2-1 debugger and programmer. The STM32 Nucleo board comes with the STM32 comprehensive software HAL library together with various packaged software examples. -.. image:: img/nucleo_f042k6.jpg - :align: center - :alt: Nucleo F042k6 - More information about the board can be found at the `Nucleo F042K6 website`_. Hardware diff --git a/boards/st/nucleo_f042k6/nucleo_f042k6.dts b/boards/st/nucleo_f042k6/nucleo_f042k6.dts index 74d700c9c1d..0f8a31e35b4 100644 --- a/boards/st/nucleo_f042k6/nucleo_f042k6.dts +++ b/boards/st/nucleo_f042k6/nucleo_f042k6.dts @@ -99,7 +99,7 @@ &adc1 { pinctrl-0 = <&adc_in0_pa0>; pinctrl-names = "default"; - st,adc-clock-source = ; + st,adc-clock-source = "SYNC"; st,adc-prescaler = <4>; status = "okay"; }; diff --git a/boards/st/nucleo_f070rb/doc/index.rst b/boards/st/nucleo_f070rb/doc/index.rst index acecfb20979..c198fe28f6e 100644 --- a/boards/st/nucleo_f070rb/doc/index.rst +++ b/boards/st/nucleo_f070rb/doc/index.rst @@ -1,7 +1,4 @@ -.. _nucleo_f070rb_board: - -ST Nucleo F070RB -################ +.. zephyr:board:: nucleo_f070rb Overview ******** @@ -20,10 +17,6 @@ The STM32 Nucleo board integrates the ST-LINK/V2-1 debugger and programmer. The STM32 Nucleo board comes with the STM32 comprehensive software HAL library together with various packaged software examples. -.. image:: img/nucleo_f070rb.jpg - :align: center - :alt: Nucleo F070RB - More information about the board can be found at the `Nucleo F070RB website`_. Hardware diff --git a/boards/st/nucleo_f070rb/nucleo_f070rb.dts b/boards/st/nucleo_f070rb/nucleo_f070rb.dts index c504dad4de5..8c0b43d71c8 100644 --- a/boards/st/nucleo_f070rb/nucleo_f070rb.dts +++ b/boards/st/nucleo_f070rb/nucleo_f070rb.dts @@ -121,7 +121,7 @@ &adc1 { pinctrl-0 = <&adc_in0_pa0>; pinctrl-names = "default"; - st,adc-clock-source = ; + st,adc-clock-source = "SYNC"; st,adc-prescaler = <4>; status = "okay"; }; diff --git a/boards/st/nucleo_f091rc/doc/index.rst b/boards/st/nucleo_f091rc/doc/index.rst index 2cce144c1fb..60181533aff 100644 --- a/boards/st/nucleo_f091rc/doc/index.rst +++ b/boards/st/nucleo_f091rc/doc/index.rst @@ -1,7 +1,4 @@ -.. _nucleo_f091rc_board: - -ST Nucleo F091RC -################ +.. zephyr:board:: nucleo_f091rc Overview ******** @@ -20,10 +17,6 @@ The STM32 Nucleo board integrates the ST-LINK/V2-1 debugger and programmer. The STM32 Nucleo board comes with the STM32 comprehensive software HAL library together with various packaged software examples. -.. image:: img/nucleo_f091rc.jpg - :align: center - :alt: Nucleo F091RC - More information about the board can be found at the `Nucleo F091RC website`_. Hardware diff --git a/boards/st/nucleo_f091rc/nucleo_f091rc.dts b/boards/st/nucleo_f091rc/nucleo_f091rc.dts index b2443590918..cb9348240ca 100644 --- a/boards/st/nucleo_f091rc/nucleo_f091rc.dts +++ b/boards/st/nucleo_f091rc/nucleo_f091rc.dts @@ -159,7 +159,7 @@ &adc1 { pinctrl-0 = <&adc_in0_pa0>; pinctrl-names = "default"; - st,adc-clock-source = ; + st,adc-clock-source = "SYNC"; st,adc-prescaler = <4>; status = "okay"; }; diff --git a/boards/st/nucleo_f103rb/doc/index.rst b/boards/st/nucleo_f103rb/doc/index.rst index 8a9baaea537..662fd3ac3cc 100644 --- a/boards/st/nucleo_f103rb/doc/index.rst +++ b/boards/st/nucleo_f103rb/doc/index.rst @@ -1,7 +1,4 @@ -.. _nucleo_f103rb_board: - -ST Nucleo F103RB -################ +.. zephyr:board:: nucleo_f103rb Overview ******** @@ -20,10 +17,6 @@ The STM32 Nucleo board integrates the ST-LINK/V2-1 debugger and programmer. The STM32 Nucleo board comes with the STM32 comprehensive software HAL library together with various packaged software examples. -.. image:: img/nucleo_f103rb.jpg - :align: center - :alt: Nucleo F103RB - More information about the board can be found at the `Nucleo F103RB website`_. Hardware diff --git a/boards/st/nucleo_f207zg/doc/index.rst b/boards/st/nucleo_f207zg/doc/index.rst index 17d51354dde..51082a2cfc6 100644 --- a/boards/st/nucleo_f207zg/doc/index.rst +++ b/boards/st/nucleo_f207zg/doc/index.rst @@ -1,7 +1,4 @@ -.. _nucleo_f207zg_board: - -ST Nucleo F207ZG -################ +.. zephyr:board:: nucleo_f207zg Overview ******** @@ -29,10 +26,6 @@ some highlights of the Nucleo F207ZG board: - Three user LEDs - Two push-buttons: USER and RESET -.. image:: img/nucleo_f207zg.jpg - :align: center - :alt: Nucleo F207ZG - More information about the board can be found at the `Nucleo F207ZG website`_. Hardware diff --git a/boards/st/nucleo_f207zg/nucleo_f207zg.dts b/boards/st/nucleo_f207zg/nucleo_f207zg.dts index 0c8d36af39b..724bf9456cc 100644 --- a/boards/st/nucleo_f207zg/nucleo_f207zg.dts +++ b/boards/st/nucleo_f207zg/nucleo_f207zg.dts @@ -164,7 +164,7 @@ zephyr_udc0: &usbotg_fs { &adc1 { pinctrl-0 = <&adc1_in0_pa0>; pinctrl-names = "default"; - st,adc-clock-source = ; + st,adc-clock-source = "SYNC"; st,adc-prescaler = <2>; status = "okay"; }; @@ -197,12 +197,32 @@ zephyr_udc0: &usbotg_fs { #address-cells = <1>; #size-cells = <1>; - /* Last sector of size 128KB at the end of 1MB flash is set - * for storage. + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x0 DT_SIZE_K(32)>; + read-only; + }; + + /* + * nvs subsystem requires 2 sectors with a max total of 32K + * On F2 series, the only option is to use the following + * partition, which is compatible with mcuboot usage. + * Keep it commented in order it is not used by CI. + * + * storage_partition: partition@8000 { + * label = "storage"; + * reg = <0x8000 DT_SIZE_K(32)>; + * }; */ - storage_partition: partition@e0000 { - label = "storage"; - reg = <0x000e0000 DT_SIZE_K(128)>; + + slot0_partition: partition@20000 { + label = "image-0"; + reg = <0x20000 DT_SIZE_K(448)>; + }; + + slot1_partition: partition@90000 { + label = "image-1"; + reg = <0x90000 DT_SIZE_K(448)>; }; }; }; diff --git a/boards/st/nucleo_f302r8/doc/index.rst b/boards/st/nucleo_f302r8/doc/index.rst index 8cb3f9e8a13..9609270cd69 100644 --- a/boards/st/nucleo_f302r8/doc/index.rst +++ b/boards/st/nucleo_f302r8/doc/index.rst @@ -1,7 +1,4 @@ -.. _nucleo_f302r8_board: - -ST Nucleo F302R8 -################ +.. zephyr:board:: nucleo_f302r8 Overview ******** @@ -27,10 +24,6 @@ Here are some highlights of the Nucleo F302R8 board: - One user LED - Two push-buttons: USER and RESET -.. image:: img/nucleo_f302r8.jpg - :align: center - :alt: Nucleo F302R8 - More information about the board can be found at the `Nucleo F302R8 website`_, and in the `STM32 Nucleo-64 board User Manual`_. diff --git a/boards/st/nucleo_f302r8/nucleo_f302r8.dts b/boards/st/nucleo_f302r8/nucleo_f302r8.dts index cb46e89563a..ea85df6c96d 100644 --- a/boards/st/nucleo_f302r8/nucleo_f302r8.dts +++ b/boards/st/nucleo_f302r8/nucleo_f302r8.dts @@ -124,7 +124,7 @@ &adc1 { pinctrl-0 = <&adc1_in1_pa0>; pinctrl-names = "default"; - st,adc-clock-source = ; + st,adc-clock-source = "SYNC"; st,adc-prescaler = <2>; status = "okay"; }; diff --git a/boards/st/nucleo_f303k8/doc/index.rst b/boards/st/nucleo_f303k8/doc/index.rst index e659d453a80..a21cc477b41 100644 --- a/boards/st/nucleo_f303k8/doc/index.rst +++ b/boards/st/nucleo_f303k8/doc/index.rst @@ -1,7 +1,4 @@ -.. _nucleo_f303k8_board: - -ST Nucleo F303K8 -################ +.. zephyr:board:: nucleo_f303k8 Overview ******** @@ -24,10 +21,6 @@ Here are some highlights of the Nucleo F303K8 board: - One user LED - One push-buttons: RESET -.. image:: img/nucleo_f303k8.jpg - :align: center - :alt: Nucleo F303K8 - More information about the board can be found at the `Nucleo F303K8 website`_, and in the `STM32 Nucleo-32 board User Manual`_. diff --git a/boards/st/nucleo_f303k8/nucleo_f303k8.dts b/boards/st/nucleo_f303k8/nucleo_f303k8.dts index efdf58a848f..c4f39c84113 100644 --- a/boards/st/nucleo_f303k8/nucleo_f303k8.dts +++ b/boards/st/nucleo_f303k8/nucleo_f303k8.dts @@ -100,7 +100,7 @@ &adc1 { pinctrl-0 = <&adc1_in1_pa0>; pinctrl-names = "default"; - st,adc-clock-source = ; + st,adc-clock-source = "SYNC"; st,adc-prescaler = <2>; status = "okay"; }; diff --git a/boards/st/nucleo_f303re/doc/index.rst b/boards/st/nucleo_f303re/doc/index.rst index dc7d7e2d0a6..1c8b6363a39 100644 --- a/boards/st/nucleo_f303re/doc/index.rst +++ b/boards/st/nucleo_f303re/doc/index.rst @@ -1,7 +1,4 @@ -.. _nucleo_f303re_board: - -ST Nucleo F303RE -################ +.. zephyr:board:: nucleo_f303re Overview ******** @@ -27,10 +24,6 @@ Here are some highlights of the Nucleo F303RE board: - One user LED - Two push-buttons: USER and RESET -.. image:: img/nucleo_f303re.jpg - :align: center - :alt: Nucleo F303RE - More information about the board can be found at the `Nucleo F303RE website`_, and in the `STM32 Nucleo-64 board User Manual`_. diff --git a/boards/st/nucleo_f334r8/doc/index.rst b/boards/st/nucleo_f334r8/doc/index.rst index 0115b2bda9c..385f4e05094 100644 --- a/boards/st/nucleo_f334r8/doc/index.rst +++ b/boards/st/nucleo_f334r8/doc/index.rst @@ -1,7 +1,4 @@ -.. _nucleo_f334r8_board: - -ST Nucleo F334R8 -################ +.. zephyr:board:: nucleo_f334r8 Overview ******** @@ -21,10 +18,6 @@ debugger and programmer. The STM32 Nucleo board comes with the STM32 comprehensive software HAL library together with various packaged software examples. -.. image:: img/nucleo_f334r8.jpg - :align: center - :alt: Nucleo F334R8 - More information about the board can be found at the `Nucleo F334R8 website`_. Hardware diff --git a/boards/st/nucleo_f401re/doc/index.rst b/boards/st/nucleo_f401re/doc/index.rst index 123992ac18b..fc64a2e5bfd 100644 --- a/boards/st/nucleo_f401re/doc/index.rst +++ b/boards/st/nucleo_f401re/doc/index.rst @@ -1,7 +1,4 @@ -.. _nucleo_f401re_board: - -ST Nucleo F401RE -################ +.. zephyr:board:: nucleo_f401re Overview ******** @@ -25,10 +22,6 @@ some highlights of the Nucleo F401RE board: - Three LEDs: USB communication (LD1), user LED (LD2), power LED (LD3) - Two push-buttons: USER and RESET -.. image:: img/nucleo_f401re.jpg - :align: center - :alt: Nucleo F401RE - More information about the board can be found at the `Nucleo F401RE website`_. Hardware diff --git a/boards/st/nucleo_f401re/nucleo_f401re.dts b/boards/st/nucleo_f401re/nucleo_f401re.dts index fbfdc59bea0..b73ea3f69ef 100644 --- a/boards/st/nucleo_f401re/nucleo_f401re.dts +++ b/boards/st/nucleo_f401re/nucleo_f401re.dts @@ -180,7 +180,7 @@ &adc1 { pinctrl-0 = <&adc1_in0_pa0>; pinctrl-names = "default"; - st,adc-clock-source = ; + st,adc-clock-source = "SYNC"; st,adc-prescaler = <2>; status = "okay"; }; diff --git a/boards/st/nucleo_f410rb/doc/index.rst b/boards/st/nucleo_f410rb/doc/index.rst index af87b501923..4b48811fdf9 100644 --- a/boards/st/nucleo_f410rb/doc/index.rst +++ b/boards/st/nucleo_f410rb/doc/index.rst @@ -1,7 +1,4 @@ -.. _nucleo_f410rb_board: - -ST Nucleo F410RB -################ +.. zephyr:board:: nucleo_f410rb Overview ******** @@ -25,10 +22,6 @@ some highlights of the Nucleo F410RB board: - Three LEDs: USB communication (LD1), user LED (LD2), power LED (LD3) - Two push-buttons: USER and RESET -.. image:: img/nucleo_f410rb.jpg - :align: center - :alt: Nucleo F410RB - More information about the board can be found at the `Nucleo F410RB website`_. Hardware diff --git a/boards/st/nucleo_f411re/doc/index.rst b/boards/st/nucleo_f411re/doc/index.rst index e4c10085d9b..cdfcd326787 100644 --- a/boards/st/nucleo_f411re/doc/index.rst +++ b/boards/st/nucleo_f411re/doc/index.rst @@ -1,7 +1,4 @@ -.. _nucleo_f411re_board: - -ST Nucleo F411RE -################ +.. zephyr:board:: nucleo_f411re Overview ******** @@ -25,10 +22,6 @@ some highlights of the Nucleo F411RE board: - Three LEDs: USB communication (LD1), user LED (LD2), power LED (LD3) - Two push-buttons: USER and RESET -.. image:: img/nucleo_f411re.jpg - :align: center - :alt: Nucleo F411RE - More information about the board can be found at the `Nucleo F411RE website`_. Hardware diff --git a/boards/st/nucleo_f412zg/Kconfig.defconfig b/boards/st/nucleo_f412zg/Kconfig.defconfig deleted file mode 100644 index a2c9ec55881..00000000000 --- a/boards/st/nucleo_f412zg/Kconfig.defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# NUCLEO-144 F412ZG board configuration - -# Copyright (c) 2017 Florian Vaussard, HEIG-VD -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_F412ZG - -if NETWORKING - -config USB_DEVICE_STACK - default y - -config USB_DEVICE_NETWORK_ECM - default y - -endif # NETWORKING - -endif # BOARD_NUCLEO_F412ZG diff --git a/boards/st/nucleo_f412zg/doc/index.rst b/boards/st/nucleo_f412zg/doc/index.rst index f3f1cf0db75..60f5f06531a 100644 --- a/boards/st/nucleo_f412zg/doc/index.rst +++ b/boards/st/nucleo_f412zg/doc/index.rst @@ -1,7 +1,4 @@ -.. _nucleo_f412zg_board: - -ST Nucleo F412ZG -################ +.. zephyr:board:: nucleo_f412zg Overview ******** @@ -28,10 +25,6 @@ some highlights of the Nucleo F412ZG board: - Three user LEDs - Two push-buttons: USER and RESET -.. image:: img/nucleo_f412zg.jpg - :align: center - :alt: Nucleo F412ZG - More information about the board can be found at the `Nucleo F412ZG website`_. Hardware diff --git a/boards/st/nucleo_f413zh/Kconfig.defconfig b/boards/st/nucleo_f413zh/Kconfig.defconfig deleted file mode 100644 index 34fb8d56961..00000000000 --- a/boards/st/nucleo_f413zh/Kconfig.defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# NUCLEO-144 F413ZH board configuration - -# Copyright (c) 2017 Florian Vaussard, HEIG-VD -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_F413ZH - -if NETWORKING - -config USB_DEVICE_STACK - default y - -config USB_DEVICE_NETWORK_ECM - default y - -endif # NETWORKING - -endif # BOARD_NUCLEO_F413ZH diff --git a/boards/st/nucleo_f413zh/doc/index.rst b/boards/st/nucleo_f413zh/doc/index.rst index 1240923df82..0c9bad9f77d 100644 --- a/boards/st/nucleo_f413zh/doc/index.rst +++ b/boards/st/nucleo_f413zh/doc/index.rst @@ -1,7 +1,4 @@ -.. _nucleo_f413zh_board: - -ST Nucleo F413ZH -################ +.. zephyr:board:: nucleo_f413zh Overview ******** @@ -28,10 +25,6 @@ some highlights of the Nucleo F413ZH board: - Three user LEDs - Two push-buttons: USER and RESET -.. image:: img/nucleo_f413zh.jpg - :align: center - :alt: Nucleo F413ZH - More information about the board can be found at the `Nucleo F413ZH website`_. Hardware diff --git a/boards/st/nucleo_f429zi/doc/index.rst b/boards/st/nucleo_f429zi/doc/index.rst index 924c30de42b..1fe03b83ced 100644 --- a/boards/st/nucleo_f429zi/doc/index.rst +++ b/boards/st/nucleo_f429zi/doc/index.rst @@ -1,7 +1,4 @@ -.. _nucleo_f429zi_board: - -ST Nucleo F429ZI -################ +.. zephyr:board:: nucleo_f429zi Overview ******** @@ -31,10 +28,6 @@ some highlights of the Nucleo F429ZI board: - Three user LEDs - Two push-buttons: USER and RESET -.. image:: img/nucleo_f429zi.jpg - :align: center - :alt: Nucleo F429ZI - More information about the board can be found at the `Nucleo F429ZI website`_. Hardware diff --git a/boards/st/nucleo_f429zi/nucleo_f429zi.dts b/boards/st/nucleo_f429zi/nucleo_f429zi.dts index 2e37e448655..d05081ed839 100644 --- a/boards/st/nucleo_f429zi/nucleo_f429zi.dts +++ b/boards/st/nucleo_f429zi/nucleo_f429zi.dts @@ -90,7 +90,7 @@ &adc1 { pinctrl-0 = <&adc1_in0_pa0>; pinctrl-names = "default"; - st,adc-clock-source = ; + st,adc-clock-source = "SYNC"; st,adc-prescaler = <2>; status = "okay"; }; @@ -194,18 +194,24 @@ zephyr_udc0: &usbotg_fs { #address-cells = <1>; #size-cells = <1>; - /* 64KB for bootloader */ + /* 32KB for bootloader */ boot_partition: partition@0 { label = "mcuboot"; - reg = <0x00000000 DT_SIZE_K(64)>; + reg = <0x00000000 DT_SIZE_K(32)>; read-only; }; - /* storage: 64KB for settings */ - storage_partition: partition@10000 { - label = "storage"; - reg = <0x00010000 DT_SIZE_K(64)>; - }; + /* + * nvs subsystem requires 2 sectors with a max total of 32K + * On F4 series, the only option is to use the following + * partition, which is compatible with mcuboot usage. + * Keep it commented in order it is not used by CI. + * + * storage_partition: partition@8000 { + * label = "storage"; + * reg = <0x0008000 DT_SIZE_K(32)>; + * }; + */ /* application image slot: 256KB */ slot0_partition: partition@20000 { diff --git a/boards/st/nucleo_f429zi/nucleo_f429zi.yaml b/boards/st/nucleo_f429zi/nucleo_f429zi.yaml index 8674acc45c8..bec17951950 100644 --- a/boards/st/nucleo_f429zi/nucleo_f429zi.yaml +++ b/boards/st/nucleo_f429zi/nucleo_f429zi.yaml @@ -23,7 +23,6 @@ supported: - adc - dac - dma - - nvs - rtc - usbd vendor: st diff --git a/boards/st/nucleo_f446re/doc/index.rst b/boards/st/nucleo_f446re/doc/index.rst index e111880ef32..0688c3c6f02 100644 --- a/boards/st/nucleo_f446re/doc/index.rst +++ b/boards/st/nucleo_f446re/doc/index.rst @@ -1,7 +1,4 @@ -.. _nucleo_f446re_board: - -ST Nucleo F446RE -################ +.. zephyr:board:: nucleo_f446re Overview ******** @@ -25,10 +22,6 @@ some highlights of the Nucleo F446RE board: - Three LEDs: USB communication (LD1), user LED (LD2), power LED (LD3) - Two push-buttons: USER and RESET -.. image:: img/nucleo_f446re.jpg - :align: center - :alt: Nucleo F446RE - More information about the board can be found at the `Nucleo F446RE website`_. Hardware diff --git a/boards/st/nucleo_f446ze/doc/index.rst b/boards/st/nucleo_f446ze/doc/index.rst index 0029f016ccf..852ce5bd99b 100644 --- a/boards/st/nucleo_f446ze/doc/index.rst +++ b/boards/st/nucleo_f446ze/doc/index.rst @@ -1,7 +1,4 @@ -.. _nucleo_f446ze_board: - -ST Nucleo F446ZE -################ +.. zephyr:board:: nucleo_f446ze Overview @@ -30,10 +27,6 @@ some highlights of the Nucleo F446ZE board: - Three LEDs: USB communication (LD1), user LED (LD2), power LED (LD3) - Two push-buttons: USER and RESET -.. image:: img/nucleo_f446ze.jpg - :align: center - :alt: Nucleo F446ZE - More information about the board can be found at the `Nucleo F446ZE website`_. Hardware diff --git a/boards/st/nucleo_f446ze/nucleo_f446ze.dts b/boards/st/nucleo_f446ze/nucleo_f446ze.dts index 5eaad0ca83d..df262a6f73e 100644 --- a/boards/st/nucleo_f446ze/nucleo_f446ze.dts +++ b/boards/st/nucleo_f446ze/nucleo_f446ze.dts @@ -87,7 +87,7 @@ &adc1 { pinctrl-0 = <&adc1_in0_pa0>; pinctrl-names = "default"; - st,adc-clock-source = ; + st,adc-clock-source = "SYNC"; st,adc-prescaler = <2>; status = "okay"; }; diff --git a/boards/st/nucleo_f446ze/nucleo_f446ze.yaml b/boards/st/nucleo_f446ze/nucleo_f446ze.yaml index f363608c3be..cf62cdd7712 100644 --- a/boards/st/nucleo_f446ze/nucleo_f446ze.yaml +++ b/boards/st/nucleo_f446ze/nucleo_f446ze.yaml @@ -17,7 +17,6 @@ supported: - i2c - can - backup_sram - - usb - quadspi ram: 128 flash: 512 diff --git a/boards/st/nucleo_f722ze/doc/index.rst b/boards/st/nucleo_f722ze/doc/index.rst index fde339622a8..b381f20de4c 100644 --- a/boards/st/nucleo_f722ze/doc/index.rst +++ b/boards/st/nucleo_f722ze/doc/index.rst @@ -1,7 +1,4 @@ -.. _nucleo_f722ze_board: - -ST Nucleo F722ZE -################ +.. zephyr:board:: nucleo_f722ze Overview ******** @@ -23,11 +20,6 @@ Key Features: - On-board ST-LINK debugger/programmer - Flexible power supply options, including ST-LINK VBUS and external sources. -.. image:: img/nucleo_f722ze.jpg - :width: 800px - :align: center - :alt: Nucleo F722ZE - Hardware ******** diff --git a/boards/st/nucleo_f722ze/nucleo_f722ze.dts b/boards/st/nucleo_f722ze/nucleo_f722ze.dts index 988a1204a9f..00faeae1dbc 100644 --- a/boards/st/nucleo_f722ze/nucleo_f722ze.dts +++ b/boards/st/nucleo_f722ze/nucleo_f722ze.dts @@ -102,7 +102,7 @@ &adc1 { pinctrl-0 = <&adc1_in3_pa3 &adc1_in10_pc0>; pinctrl-names = "default"; - st,adc-clock-source = ; + st,adc-clock-source = "SYNC"; st,adc-prescaler = <2>; status = "okay"; }; diff --git a/boards/st/nucleo_f746zg/doc/index.rst b/boards/st/nucleo_f746zg/doc/index.rst index 59566cf34c7..05b436d99e9 100644 --- a/boards/st/nucleo_f746zg/doc/index.rst +++ b/boards/st/nucleo_f746zg/doc/index.rst @@ -1,7 +1,4 @@ -.. _nucleo_f746zg_board: - -ST Nucleo F746ZG -################ +.. zephyr:board:: nucleo_f746zg Overview ******** @@ -44,10 +41,6 @@ Key Features STM32Cube MCU package. - Arm* Mbed Enabled* compliant (only for some Nucleo part numbers) -.. image:: img/nucleo_f746zg.jpg - :align: center - :alt: Nucleo F746ZG - More information about the board can be found at the `Nucleo F746ZG website`_. Hardware diff --git a/boards/st/nucleo_f746zg/nucleo_f746zg.dts b/boards/st/nucleo_f746zg/nucleo_f746zg.dts index 90c4b4409a0..65416d66d52 100644 --- a/boards/st/nucleo_f746zg/nucleo_f746zg.dts +++ b/boards/st/nucleo_f746zg/nucleo_f746zg.dts @@ -176,7 +176,7 @@ zephyr_udc0: &usbotg_fs { &adc1 { pinctrl-0 = <&adc1_in0_pa0>; pinctrl-names = "default"; - st,adc-clock-source = ; + st,adc-clock-source = "SYNC"; st,adc-prescaler = <2>; status = "okay"; }; diff --git a/boards/st/nucleo_f756zg/doc/index.rst b/boards/st/nucleo_f756zg/doc/index.rst index 6d512dcca37..3b90c688ff8 100644 --- a/boards/st/nucleo_f756zg/doc/index.rst +++ b/boards/st/nucleo_f756zg/doc/index.rst @@ -1,7 +1,4 @@ -.. _nucleo_f756zg_board: - -ST Nucleo F756ZG -################ +.. zephyr:board:: nucleo_f756zg Overview ******** @@ -44,10 +41,6 @@ Key Features - STM32Cube MCU package. - Arm* Mbed Enabled* compliant (only for some Nucleo part numbers) -.. image:: img/nucleo_f756zg.jpg - :align: center - :alt: Nucleo F756ZG - More information about the board can be found at the `Nucleo F756ZG website`_. Hardware diff --git a/boards/st/nucleo_f767zi/doc/index.rst b/boards/st/nucleo_f767zi/doc/index.rst index e0b50050151..d68ae61592f 100644 --- a/boards/st/nucleo_f767zi/doc/index.rst +++ b/boards/st/nucleo_f767zi/doc/index.rst @@ -1,7 +1,4 @@ -.. _nucleo_f767zi_board: - -ST Nucleo F767ZI -################ +.. zephyr:board:: nucleo_f767zi Overview ******** @@ -44,10 +41,6 @@ Key Features STM32Cube MCU package. - Arm* Mbed Enabled* compliant (only for some Nucleo part numbers) -.. image:: img/nucleo_f767zi.jpg - :align: center - :alt: Nucleo F767ZI - More information about the board can be found at the `Nucleo F767ZI website`_. Hardware diff --git a/boards/st/nucleo_f767zi/nucleo_f767zi.dts b/boards/st/nucleo_f767zi/nucleo_f767zi.dts index 4125f4e6bde..c7a113fdfcf 100644 --- a/boards/st/nucleo_f767zi/nucleo_f767zi.dts +++ b/boards/st/nucleo_f767zi/nucleo_f767zi.dts @@ -171,7 +171,7 @@ zephyr_udc0: &usbotg_fs { &adc1 { pinctrl-0 = <&adc1_in0_pa0>; pinctrl-names = "default"; - st,adc-clock-source = ; + st,adc-clock-source = "SYNC"; st,adc-prescaler = <2>; status = "okay"; }; diff --git a/boards/st/nucleo_g031k8/doc/index.rst b/boards/st/nucleo_g031k8/doc/index.rst index c3776071ee2..bf985149d83 100644 --- a/boards/st/nucleo_g031k8/doc/index.rst +++ b/boards/st/nucleo_g031k8/doc/index.rst @@ -1,7 +1,4 @@ -.. _nucleo_g031k8_board: - -ST Nucleo G031K8 -################ +.. zephyr:board:: nucleo_g031k8 Overview ******** @@ -21,10 +18,6 @@ The STM32 Nucleo-32 board comes with the STM32 comprehensive free software libraries and examples available with the STM32Cube MCU Package. -.. image:: img/nucleo_g031k8.jpg - :align: center - :alt: Nucleo G031K8 - More information about the board can be found at the `Nucleo G031K8 website`_. Hardware diff --git a/boards/st/nucleo_g070rb/doc/index.rst b/boards/st/nucleo_g070rb/doc/index.rst index 87b8cef25af..f15d559403c 100644 --- a/boards/st/nucleo_g070rb/doc/index.rst +++ b/boards/st/nucleo_g070rb/doc/index.rst @@ -1,7 +1,4 @@ -.. _nucleo_g070rb_board: - -ST Nucleo G070RB -################ +.. zephyr:board:: nucleo_g070rb Overview ******** @@ -24,10 +21,6 @@ some highlights of the Nucleo G070RB board: - Three LEDs: USB communication (LD1), user LED (LD4), power LED (LD3) - Two push-buttons: USER and RESET -.. image:: img/nucleo_g070rb.jpg - :align: center - :alt: Nucleo G070RB - More information about the board can be found at the `Nucleo G070RB website`_. Hardware diff --git a/boards/st/nucleo_g070rb/nucleo_g070rb.dts b/boards/st/nucleo_g070rb/nucleo_g070rb.dts index 7e976c93059..bfbcfbc27f2 100644 --- a/boards/st/nucleo_g070rb/nucleo_g070rb.dts +++ b/boards/st/nucleo_g070rb/nucleo_g070rb.dts @@ -139,7 +139,7 @@ &adc1 { pinctrl-0 = <&adc1_in0_pa0 &adc1_in1_pa1>; pinctrl-names = "default"; - st,adc-clock-source = ; + st,adc-clock-source = "SYNC"; st,adc-prescaler = <4>; status = "okay"; vref-mv = <3300>; @@ -155,10 +155,10 @@ #address-cells = <1>; #size-cells = <1>; - /* Set 2KB of storage at the end of 128KB flash */ - storage_partition: partition@1f800 { + /* Set 4KB of storage at the end of 128KB flash */ + storage_partition: partition@1f000 { label = "storage"; - reg = <0x0001f800 DT_SIZE_K(2)>; + reg = <0x0001f000 DT_SIZE_K(4)>; }; }; }; diff --git a/boards/st/nucleo_g071rb/doc/index.rst b/boards/st/nucleo_g071rb/doc/index.rst index 2202157b6cd..0ab38d78118 100644 --- a/boards/st/nucleo_g071rb/doc/index.rst +++ b/boards/st/nucleo_g071rb/doc/index.rst @@ -1,7 +1,4 @@ -.. _nucleo_g071rb_board: - -ST Nucleo G071RB -################ +.. zephyr:board:: nucleo_g071rb Overview ******** @@ -24,10 +21,6 @@ some highlights of the Nucleo G071RB board: - Three LEDs: USB communication (LD1), user LED (LD4), power LED (LD3) - Two push-buttons: USER and RESET -.. image:: img/nucleo_g071rb.jpg - :align: center - :alt: Nucleo G071RB - More information about the board can be found at the `Nucleo G071RB website`_. Hardware diff --git a/boards/st/nucleo_g071rb/nucleo_g071rb.dts b/boards/st/nucleo_g071rb/nucleo_g071rb.dts index 9237cd779b0..902c30dc43a 100644 --- a/boards/st/nucleo_g071rb/nucleo_g071rb.dts +++ b/boards/st/nucleo_g071rb/nucleo_g071rb.dts @@ -143,9 +143,11 @@ }; &adc1 { + clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00100000>, + <&rcc STM32_SRC_SYSCLK ADC_SEL(0)>; pinctrl-0 = <&adc1_in0_pa0 &adc1_in1_pa1>; pinctrl-names = "default"; - st,adc-clock-source = ; + st,adc-clock-source = "ASYNC"; st,adc-prescaler = <4>; status = "okay"; vref-mv = <3300>; @@ -167,10 +169,10 @@ #address-cells = <1>; #size-cells = <1>; - /* Set 2KB of storage at the end of 128KB flash */ - storage_partition: partition@1f800 { + /* Set 4KB of storage at the end of 128KB flash */ + storage_partition: partition@1f000 { label = "storage"; - reg = <0x0001f800 DT_SIZE_K(2)>; + reg = <0x0001f000 DT_SIZE_K(4)>; }; }; }; diff --git a/boards/st/nucleo_g0b1re/doc/index.rst b/boards/st/nucleo_g0b1re/doc/index.rst index 3a32623a82e..aa68effb93c 100644 --- a/boards/st/nucleo_g0b1re/doc/index.rst +++ b/boards/st/nucleo_g0b1re/doc/index.rst @@ -1,7 +1,4 @@ -.. _nucleo_g0b1re_board: - -ST Nucleo G0B1RE -################ +.. zephyr:board:: nucleo_g0b1re Overview ******** @@ -28,10 +25,6 @@ some highlights of the Nucleo G0B1RE board: - Two push-buttons: USER and RESET - 32.768 kHz crystal oscillator -.. image:: img/nucleo_g0b1re.jpg - :align: center - :alt: Nucleo G0B1RE - More information about the board can be found at the `Nucleo G0B1RE website`_. Hardware diff --git a/boards/st/nucleo_g0b1re/nucleo_g0b1re.dts b/boards/st/nucleo_g0b1re/nucleo_g0b1re.dts index d86d7c6ae8e..75ee749e603 100644 --- a/boards/st/nucleo_g0b1re/nucleo_g0b1re.dts +++ b/boards/st/nucleo_g0b1re/nucleo_g0b1re.dts @@ -163,7 +163,7 @@ zephyr_udc0: &usb { &adc1 { pinctrl-0 = <&adc1_in0_pa0 &adc1_in1_pa1>; pinctrl-names = "default"; - st,adc-clock-source = ; + st,adc-clock-source = "SYNC"; st,adc-prescaler = <4>; status = "okay"; }; diff --git a/boards/st/nucleo_g431kb/Kconfig.nucleo_g431kb b/boards/st/nucleo_g431kb/Kconfig.nucleo_g431kb new file mode 100644 index 00000000000..79f5335fbbd --- /dev/null +++ b/boards/st/nucleo_g431kb/Kconfig.nucleo_g431kb @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Klaus Nagel +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_G431KB + select SOC_STM32G431XX diff --git a/boards/st/nucleo_g431kb/board.cmake b/boards/st/nucleo_g431kb/board.cmake new file mode 100644 index 00000000000..00ab7c45ccf --- /dev/null +++ b/boards/st/nucleo_g431kb/board.cmake @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 + +# keep first +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") +board_runner_args(pyocd "--target=stm32g431kbtx") + +# keep first +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/st/nucleo_g431kb/board.yml b/boards/st/nucleo_g431kb/board.yml new file mode 100644 index 00000000000..759a5ca95e0 --- /dev/null +++ b/boards/st/nucleo_g431kb/board.yml @@ -0,0 +1,6 @@ +board: + name: nucleo_g431kb + full_name: Nucleo G431KB + vendor: st + socs: + - name: stm32g431xx diff --git a/boards/st/nucleo_g431kb/doc/img/nucleo_g431kb.webp b/boards/st/nucleo_g431kb/doc/img/nucleo_g431kb.webp new file mode 100644 index 00000000000..1d7a7f6b838 Binary files /dev/null and b/boards/st/nucleo_g431kb/doc/img/nucleo_g431kb.webp differ diff --git a/boards/st/nucleo_g431kb/doc/index.rst b/boards/st/nucleo_g431kb/doc/index.rst new file mode 100644 index 00000000000..d9400a7b38b --- /dev/null +++ b/boards/st/nucleo_g431kb/doc/index.rst @@ -0,0 +1,182 @@ +.. zephyr:board:: nucleo_g431kb + +Overview +******** + +The Nucleo G431KB board features an ARM Cortex-M4 based STM32G431KB MCU +with a wide range of connectivity support and configurations. +Here are some highlights of the Nucleo G431KB board: + +- STM32 microcontroller in LQFP32 package +- Arduino Nano V3 connectivity +- On-board ST-LINK/V3E debugger/programmer +- Flexible board power supply: + + - USB VBUS or external source(3.3 V, 5 V, 7 - 12 V) + - Power management access point + +- Three LEDs: USB communication (LD1), power LED (LD3), user LED (LD2) +- One push-button for RESET + +More information about the board can be found at the `Nucleo G431KB website`_. + +- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell. + +More information about STM32G431KB can be found here: + +- `STM32G431KB on www.st.com`_ +- `STM32G4 reference manual`_ + +Supported Features +================== + +The Zephyr ``nucleo_g431kb`` board target supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/st/nucleo_g431kb/nucleo_g431kb_defconfig` + + +Connections and IOs +=================== + +Nucleo G431KB Board has 6 GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +For more details please refer to `STM32G4 Nucleo-32 board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +.. rst-class:: rst-columns + +- LPUART_1_TX : PA2 +- LPUART_1_RX : PA3 +- LD2 : PB8 +- PWM_4_CH_3 : PB8 +- I2C_2_SCL : PA9 +- I2C_2_SDA : PA8 + +System Clock +------------ + +The Nucleo G431KB System Clock could be driven by internal or external oscillator, +as well as main PLL clock. By default the external oscillator is not connected to the board. Therefore only the internal +High Speed oscillator is supported. By default System clock is driven by PLL clock at 170 MHz, +the PLL is driven by the 16 MHz high speed internal oscillator. + +Serial Port +----------- + +Nucleo G431KB board has 1 U(S)ARTs and one LPUART. The Zephyr console output is assigned to LPUART1. +Default settings are 115200 8N1. + +Please note that LPUART1 baudrate is limited to 9600 if the MCU is clocked by LSE (32.768 kHz) in +low power mode. + +Programming and Debugging +************************* + +Nucleo G431KB Board includes an ST-Link/V3 embedded debug tool interface. + +Applications for the ``nucleo_g431kb`` board target can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. + +Alternatively, OpenOCD, or pyOCD can also be used to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner openocd + $ west flash --runner pyocd + +To enable support of the STM32G431KB SoC in pyOCD, its pack has to be installed first: + +.. code-block:: console + + $ pyocd pack --update + $ pyocd pack --install stm32g431kb + +Flashing an application to Nucleo G431KB +---------------------------------------- + +Connect the Nucleo G431KB to your host computer using the USB port, +then run a serial host program to connect with your Nucleo board. + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +Now build and flash an application. Here is an example for +:zephyr:code-sample:`hello_world`. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_g431kb + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + $ Hello World! nucleo_g431kb/stm32g431xx + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_g431kb + :maybe-skip-config: + :goals: debug + +References +********** + +.. target-notes:: + +.. _Nucleo G431KB website: + https://www.st.com/en/evaluation-tools/nucleo-g431kb.html + +.. _STM32G4 Nucleo-32 board User Manual: + https://www.st.com/resource/en/user_manual/um2397-stm32g4-nucleo32-board-mb1430-stmicroelectronics.pdf + +.. _STM32g431kb Nucleo-32 board schematic: + https://www.st.com/resource/en/schematic_pack/mb1430-g431kbt6-a02_schematic_internal.pdf + +.. _STM32G431KB on www.st.com: + https://www.st.com/en/microcontrollers-microprocessors/stm32g431kb.html + +.. _STM32G4 reference manual: + https://www.st.com/resource/en/reference_manual/rm0440-stm32g4-series-advanced-armbased-32bit-mcus-stmicroelectronics.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/st/nucleo_g431kb/nucleo_g431kb.dts b/boards/st/nucleo_g431kb/nucleo_g431kb.dts new file mode 100644 index 00000000000..b3d1adaa077 --- /dev/null +++ b/boards/st/nucleo_g431kb/nucleo_g431kb.dts @@ -0,0 +1,117 @@ +/* + * Copyright (c) 2024 Klaus Nagel, + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include + +/ { + model = "STMicroelectronics STM32G431KB-NUCLEO board"; + compatible = "st,stm32g431kb-nucleo"; + + chosen { + zephyr,console = &lpuart1; + zephyr,shell-uart = &lpuart1; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + }; + + leds: leds { + compatible = "gpio-leds"; + green_led: led_0 { + gpios = <&gpiob 8 GPIO_ACTIVE_HIGH>; + label = "User LD2"; + }; + + }; + + pwmleds { + compatible = "pwm-leds"; + + green_pwm_led: green_pwm_led { + pwms = <&pwm4 3 PWM_MSEC(20) PWM_POLARITY_NORMAL>; + }; + }; + + + aliases { + led0 = &green_led; + pwm-led0 = &green_pwm_led; + watchdog0 = &iwdg; + }; +}; + +&clk_hsi { + status = "okay"; +}; + +&clk_lsi { + status = "okay"; +}; + +stm32_lp_tick_source: &lptim1 { + clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>, + <&rcc STM32_SRC_LSI LPTIM1_SEL(3)>; + status = "okay"; +}; + +/* Adjust the pll for a SYSTEM Clock of 170MHz */ +&pll { + div-m = <4>; + mul-n = <85>; + div-p = <7>; + div-q = <2>; + div-r = <2>; + clocks = <&clk_hsi>; + status = "okay"; +}; + +&rcc { + clocks = <&pll>; + clock-frequency = ; + ahb-prescaler = <1>; + apb1-prescaler = <1>; + apb2-prescaler = <1>; +}; + +&lpuart1 { + pinctrl-0 = <&lpuart1_tx_pa2 &lpuart1_rx_pa3>; + pinctrl-names = "default"; + current-speed = <115200>; + status = "okay"; +}; + +&timers4 { + st,prescaler = <10000>; + status = "okay"; + + pwm4: pwm { + status = "okay"; + pinctrl-0 = <&tim4_ch3_pb8>; + pinctrl-names = "default"; + }; +}; + +&i2c2 { + pinctrl-0 = <&i2c2_scl_pa9 &i2c2_sda_pa8>; + pinctrl-names = "default"; + status = "okay"; +}; + +&flash0 { + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Set 4Kb of storage at the end of the 128Kb of flash */ + storage_partition: partition@1f000 { + label = "storage"; + reg = <0x0001f000 DT_SIZE_K(4)>; + }; + }; +}; diff --git a/boards/st/nucleo_g431kb/nucleo_g431kb.yaml b/boards/st/nucleo_g431kb/nucleo_g431kb.yaml new file mode 100644 index 00000000000..eb396a45f57 --- /dev/null +++ b/boards/st/nucleo_g431kb/nucleo_g431kb.yaml @@ -0,0 +1,16 @@ +identifier: nucleo_g431kb +name: ST Nucleo G431KB +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 32 +flash: 128 +supported: + - gpio + - pwm + - counter + - i2c +vendor: st diff --git a/boards/st/nucleo_g431kb/nucleo_g431kb_defconfig b/boards/st/nucleo_g431kb/nucleo_g431kb_defconfig new file mode 100644 index 00000000000..e12697ed812 --- /dev/null +++ b/boards/st/nucleo_g431kb/nucleo_g431kb_defconfig @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Serial drivers +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +# enable GPIO +CONFIG_GPIO=y + +# Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable HW stack protection +CONFIG_HW_STACK_PROTECTION=y diff --git a/boards/st/nucleo_g431kb/support/openocd.cfg b/boards/st/nucleo_g431kb/support/openocd.cfg new file mode 100644 index 00000000000..d936f7d3534 --- /dev/null +++ b/boards/st/nucleo_g431kb/support/openocd.cfg @@ -0,0 +1,7 @@ +source [find interface/stlink.cfg] + +transport select hla_swd + +source [find target/stm32g4x.cfg] + +reset_config srst_only diff --git a/boards/st/nucleo_g431rb/doc/index.rst b/boards/st/nucleo_g431rb/doc/index.rst index 62805c011cd..cebd20cc491 100644 --- a/boards/st/nucleo_g431rb/doc/index.rst +++ b/boards/st/nucleo_g431rb/doc/index.rst @@ -1,7 +1,4 @@ -.. _nucleo_g431rb_board: - -ST Nucleo G431RB -################ +.. zephyr:board:: nucleo_g431rb Overview ******** @@ -21,10 +18,6 @@ some highlights of the Nucleo G431RB board: - Three LEDs: USB communication (LD1), power LED (LD3), user LED (LD2) - Two push-buttons: RESET and USER -.. image:: img/nucleo_g431rb.jpg - :align: center - :alt: Nucleo G431RB - More information about the board can be found at the `Nucleo G431RB website`_. Hardware diff --git a/boards/st/nucleo_g474re/doc/index.rst b/boards/st/nucleo_g474re/doc/index.rst index 8ef04ed8fa1..2b61e4b2296 100644 --- a/boards/st/nucleo_g474re/doc/index.rst +++ b/boards/st/nucleo_g474re/doc/index.rst @@ -1,7 +1,4 @@ -.. _nucleo_g474re_board: - -ST Nucleo G474RE -################ +.. zephyr:board:: nucleo_g474re Overview ******** @@ -21,10 +18,6 @@ some highlights of the Nucleo G474RE board: - Three LEDs: USB communication (LD1), power LED (LD3), user LED (LD2) - Two push-buttons: RESET and USER -.. image:: img/nucleo_g474re.jpg - :align: center - :alt: Nucleo G474RE - More information about the board can be found at the `Nucleo G474RE website`_. Hardware diff --git a/boards/st/nucleo_g474re/nucleo_g474re.dts b/boards/st/nucleo_g474re/nucleo_g474re.dts index a91ec3ccb60..a3152661131 100644 --- a/boards/st/nucleo_g474re/nucleo_g474re.dts +++ b/boards/st/nucleo_g474re/nucleo_g474re.dts @@ -203,7 +203,7 @@ stm32_lp_tick_source: &lptim1 { &adc1 { pinctrl-0 = <&adc1_in1_pa0>; pinctrl-names = "default"; - st,adc-clock-source = ; + st,adc-clock-source = "SYNC"; st,adc-prescaler = <4>; status = "okay"; }; diff --git a/boards/st/nucleo_h503rb/doc/index.rst b/boards/st/nucleo_h503rb/doc/index.rst index ed7133cb5b1..2be64f7e95a 100644 --- a/boards/st/nucleo_h503rb/doc/index.rst +++ b/boards/st/nucleo_h503rb/doc/index.rst @@ -1,7 +1,4 @@ -.. _nucleo_h503rb_board: - -ST Nucleo H503RB -################ +.. zephyr:board:: nucleo_h503rb Overview ******** diff --git a/boards/st/nucleo_h533re/arduino_r3_connector.dtsi b/boards/st/nucleo_h533re/arduino_r3_connector.dtsi index 15bb1aab0bf..7e2ca9b705c 100644 --- a/boards/st/nucleo_h533re/arduino_r3_connector.dtsi +++ b/boards/st/nucleo_h533re/arduino_r3_connector.dtsi @@ -36,3 +36,4 @@ }; arduino_serial: &usart1 {}; +arduino_spi: &spi1 {}; diff --git a/boards/st/nucleo_h533re/doc/index.rst b/boards/st/nucleo_h533re/doc/index.rst index 428f79b83c2..986cda88c35 100644 --- a/boards/st/nucleo_h533re/doc/index.rst +++ b/boards/st/nucleo_h533re/doc/index.rst @@ -1,7 +1,4 @@ -.. _nucleo_h533re_board: - -ST Nucleo H533RE -################ +.. zephyr:board:: nucleo_h533re Overview ******** @@ -41,10 +38,6 @@ Here are some highlights of the Nucleo H533RE board: More information about the board can be found at the `NUCLEO_H533RE website`_. -.. image:: img/nucleo_h533re.jpg - :align: center - :alt: NUCLEO H533RE - Hardware ******** @@ -176,6 +169,8 @@ The Zephyr nucleo_h533re board configuration supports the following hardware fea +-----------+------------+-------------------------------------+ | USB | on-chip | USB full-speed host/device bus | +-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ Other hardware features are not yet supported on this Zephyr port. @@ -213,7 +208,7 @@ Default Zephyr Peripheral Mapping: - ADC1 channel 0 input: PA0 - USART1 TX/RX : PB14/PB15 (Arduino USART1) -- SPI1 SCK/MISO/MOSI/NSS: PA5/PA6/PA7/PA4 +- SPI1 SCK/MISO/MOSI/NSS: PA5/PA6/PA7/PC9 - UART2 TX/RX : PA2/PA3 (VCP) - USER_PB : PC13 diff --git a/boards/st/nucleo_h533re/nucleo_h533re.dts b/boards/st/nucleo_h533re/nucleo_h533re.dts index fdb245e4320..7ca0c23ddea 100644 --- a/boards/st/nucleo_h533re/nucleo_h533re.dts +++ b/boards/st/nucleo_h533re/nucleo_h533re.dts @@ -105,6 +105,13 @@ status = "okay"; }; +&spi1 { + pinctrl-0 = <&spi1_sck_pa5 &spi1_miso_pa6 &spi1_mosi_pa7>; + pinctrl-names = "default"; + cs-gpios = <&gpioc 9 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + &iwdg { status = "okay"; }; @@ -121,9 +128,11 @@ }; &adc1 { + clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000400>, + <&rcc STM32_SRC_HCLK ADCDAC_SEL(0)>; pinctrl-0 = <&adc1_inp0_pa0>; /* Arduino A0 */ pinctrl-names = "default"; - st,adc-clock-source = ; + st,adc-clock-source = "ASYNC"; st,adc-prescaler = <8>; status = "okay"; }; diff --git a/boards/st/nucleo_h533re/nucleo_h533re.yaml b/boards/st/nucleo_h533re/nucleo_h533re.yaml index 6f675df5922..cf36efb57fb 100644 --- a/boards/st/nucleo_h533re/nucleo_h533re.yaml +++ b/boards/st/nucleo_h533re/nucleo_h533re.yaml @@ -10,12 +10,15 @@ toolchain: ram: 272 flash: 512 supported: + - arduino_gpio + - arduino_serial + - arduino_spi - gpio + - spi - watchdog - pwm - rtc - adc - usb_device - - usb - backup_sram vendor: st diff --git a/boards/st/nucleo_h563zi/doc/index.rst b/boards/st/nucleo_h563zi/doc/index.rst index 8bbb099147e..da88685959c 100644 --- a/boards/st/nucleo_h563zi/doc/index.rst +++ b/boards/st/nucleo_h563zi/doc/index.rst @@ -1,7 +1,4 @@ -.. _nucleo_h563zi_board: - -ST Nucleo H563ZI -################ +.. zephyr:board:: nucleo_h563zi Overview ******** @@ -41,10 +38,6 @@ Here are some highlights of the Nucleo H563ZI board: More information about the board can be found at the `NUCLEO_H563ZI website`_. -.. image:: img/nucleo_h563zi.jpg - :align: center - :alt: NUCLEO H563ZI - Hardware ******** @@ -174,6 +167,8 @@ The Zephyr nucleo_h563zi board configuration supports the following hardware fea +-----------+------------+-------------------------------------+ | I2C | on-chip | i2c bus | +-----------+------------+-------------------------------------+ +| I3C | on-chip | i3c bus | ++-----------+------------+-------------------------------------+ | UART | on-chip | serial port-polling; | | | | serial port-interrupt | +-----------+------------+-------------------------------------+ @@ -181,7 +176,8 @@ The Zephyr nucleo_h563zi board configuration supports the following hardware fea +-----------+------------+-------------------------------------+ | USB | on-chip | USB full-speed host/device bus | +-----------+------------+-------------------------------------+ - +| ETHERNET | on-chip | ethernet | ++-----------+------------+-------------------------------------+ Other hardware features are not yet supported on this Zephyr port. @@ -228,6 +224,7 @@ Default Zephyr Peripheral Mapping: - SPI1 SCK/MISO/MOSI/CS: PA5/PG9/PB5/PD14 - UART3 TX/RX : PD8/PD9 (VCP) - USER_PB : PC13 +- I3C1: PD12(SCL) & PD13(SDA) System Clock ------------ diff --git a/boards/st/nucleo_h563zi/nucleo_h563zi-common.dtsi b/boards/st/nucleo_h563zi/nucleo_h563zi-common.dtsi index 030bab86a0c..5c5cecdf407 100644 --- a/boards/st/nucleo_h563zi/nucleo_h563zi-common.dtsi +++ b/boards/st/nucleo_h563zi/nucleo_h563zi-common.dtsi @@ -78,6 +78,13 @@ status = "okay"; }; +&i3c1 { + pinctrl-0 = <&i3c1_scl_pd12 &i3c1_sda_pd13>; + pinctrl-names = "default"; + i3c-scl-hz = <12500000>; + status = "okay"; +}; + &rcc { clocks = <&pll>; clock-frequency = ; @@ -145,9 +152,11 @@ }; &adc1 { + clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000400>, + <&rcc STM32_SRC_HCLK ADCDAC_SEL(0)>; pinctrl-0 = <&adc1_inp3_pa6 &adc1_inp15_pa3>; /* Zio A0, Zio D35 */ pinctrl-names = "default"; - st,adc-clock-source = ; + st,adc-clock-source = "ASYNC"; st,adc-prescaler = <6>; status = "okay"; }; diff --git a/boards/st/nucleo_h563zi/nucleo_h563zi.yaml b/boards/st/nucleo_h563zi/nucleo_h563zi.yaml index a02dc2591a8..d8db97fe4a3 100644 --- a/boards/st/nucleo_h563zi/nucleo_h563zi.yaml +++ b/boards/st/nucleo_h563zi/nucleo_h563zi.yaml @@ -23,7 +23,7 @@ supported: - counter - spi - usb_device - - usb - rtc - i2c + - i3c vendor: st diff --git a/boards/st/nucleo_h723zg/Kconfig.defconfig b/boards/st/nucleo_h723zg/Kconfig.defconfig index 2e205cf96c4..b65c015d777 100644 --- a/boards/st/nucleo_h723zg/Kconfig.defconfig +++ b/boards/st/nucleo_h723zg/Kconfig.defconfig @@ -1,6 +1,6 @@ # STM32H723ZG Nucleo board configuration -# Copyright (c) 2020 Alexander Kozhinov +# Copyright (c) 2020 Alexander Kozhinov # SPDX-License-Identifier: Apache-2.0 if BOARD_NUCLEO_H723ZG @@ -12,8 +12,4 @@ config NET_L2_ETHERNET endif # NETWORKING -config USB_DC_HAS_HS_SUPPORT - default y - depends on USB_DC_STM32 - endif # BOARD_NUCLEO_H723ZG diff --git a/boards/st/nucleo_h723zg/Kconfig.nucleo_h723zg b/boards/st/nucleo_h723zg/Kconfig.nucleo_h723zg index a8ff99320e6..905778feb5a 100644 --- a/boards/st/nucleo_h723zg/Kconfig.nucleo_h723zg +++ b/boards/st/nucleo_h723zg/Kconfig.nucleo_h723zg @@ -1,4 +1,4 @@ -# Copyright (c) 2020 Alexander Kozhinov +# Copyright (c) 2020 Alexander Kozhinov # SPDX-License-Identifier: Apache-2.0 config BOARD_NUCLEO_H723ZG diff --git a/boards/st/nucleo_h723zg/arduino_r3_connector.dtsi b/boards/st/nucleo_h723zg/arduino_r3_connector.dtsi index 6d5288633d2..37f7a293f47 100644 --- a/boards/st/nucleo_h723zg/arduino_r3_connector.dtsi +++ b/boards/st/nucleo_h723zg/arduino_r3_connector.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020 Alexander Kozhinov + * Copyright (c) 2020 Alexander Kozhinov * SPDX-License-Identifier: Apache-2.0 */ diff --git a/boards/st/nucleo_h723zg/doc/index.rst b/boards/st/nucleo_h723zg/doc/index.rst index 5e97327386d..6cd0dc6c568 100644 --- a/boards/st/nucleo_h723zg/doc/index.rst +++ b/boards/st/nucleo_h723zg/doc/index.rst @@ -1,7 +1,4 @@ -.. _nucleo_h723zg_board: - -ST Nucleo H723ZG -################ +.. zephyr:board:: nucleo_h723zg Overview ******** @@ -42,10 +39,6 @@ Key Features - capability: mass storage, virtual COM port and debug port - USB OTG full speed or device only -.. image:: img/nucleo_h723zg.jpg - :align: center - :alt: Nucleo H723ZG - More information about the board can be found at the `Nucleo H723ZG website`_. Hardware @@ -136,10 +129,10 @@ and a ST morpho connector. Board is configured as follows: - UART_3 TX/RX : PD8/PD9 (ST-Link Virtual Port Com) - USER_PB : PC13 - LD1 : PB0 -- LD2 : PB7 +- LD2 : PE1 - LD3 : PB14 - I2C : PB8, PB9 -- SPI1 NSS/SCK/MISO/MOSI : PD14PA5/PA6/PB5 (Arduino SPI) +- SPI1 NSS/SCK/MISO/MOSI : PD14/PA5/PA6/PB5 (Arduino SPI) - FDCAN1 RX/TX : PD0, PD1 System Clock diff --git a/boards/st/nucleo_h723zg/nucleo_h723zg.dts b/boards/st/nucleo_h723zg/nucleo_h723zg.dts index 0626679941c..72fc5b7f092 100644 --- a/boards/st/nucleo_h723zg/nucleo_h723zg.dts +++ b/boards/st/nucleo_h723zg/nucleo_h723zg.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020 Alexander Kozhinov + * Copyright (c) 2020 Alexander Kozhinov * SPDX-License-Identifier: Apache-2.0 */ diff --git a/boards/st/nucleo_h723zg/support/openocd.cfg b/boards/st/nucleo_h723zg/support/openocd.cfg index 0764910b73f..5c0ed13a040 100644 --- a/boards/st/nucleo_h723zg/support/openocd.cfg +++ b/boards/st/nucleo_h723zg/support/openocd.cfg @@ -1,6 +1,6 @@ # STM32H745ZI Nucleo board OpenOCD ST-LINK V3 configuration # -# Copyright (c) 2020 Alexander Kozhinov +# Copyright (c) 2020 Alexander Kozhinov # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/st/nucleo_h743zi/doc/index.rst b/boards/st/nucleo_h743zi/doc/index.rst index 2a790927bfc..cb6e58b3b29 100644 --- a/boards/st/nucleo_h743zi/doc/index.rst +++ b/boards/st/nucleo_h743zi/doc/index.rst @@ -1,7 +1,4 @@ -.. _nucleo_h743zi_board: - -ST Nucleo H743ZI -################ +.. zephyr:board:: nucleo_h743zi Overview ******** @@ -44,10 +41,6 @@ Key Features STM32Cube MCU package. - Arm* Mbed Enabled* compliant (only for some Nucleo part numbers) -.. image:: img/nucleo_h743zi.jpg - :align: center - :alt: Nucleo H743ZI - More information about the board can be found at the `Nucleo H743ZI website`_. Hardware @@ -148,7 +141,7 @@ and a ST morpho connector. Board is configured as follows: - UART_3 TX/RX : PD8/PD9 (ST-Link Virtual Port Com) - USER_PB : PC13 - LD1 : PB0 -- LD2 : PB7 +- LD2 : PE1 - LD3 : PB14 - I2C : PB8, PB9 - ADC1_INP15 : PA3 diff --git a/boards/st/nucleo_h743zi/nucleo_h743zi.dts b/boards/st/nucleo_h743zi/nucleo_h743zi.dts index cc7122b5935..cd47bf9794c 100644 --- a/boards/st/nucleo_h743zi/nucleo_h743zi.dts +++ b/boards/st/nucleo_h743zi/nucleo_h743zi.dts @@ -150,7 +150,7 @@ zephyr_udc0: &usbotg_fs { &adc1 { pinctrl-0 = <&adc1_inp15_pa3>; pinctrl-names = "default"; - st,adc-clock-source = ; + st,adc-clock-source = "SYNC"; st,adc-prescaler = <4>; status = "okay"; }; @@ -162,7 +162,7 @@ zephyr_udc0: &usbotg_fs { &adc3 { pinctrl-0 = <&adc3_inp5_pf3>; pinctrl-names = "default"; - st,adc-clock-source = ; + st,adc-clock-source = "SYNC"; st,adc-prescaler = <4>; status = "okay"; }; diff --git a/boards/st/nucleo_h745zi_q/Kconfig.defconfig b/boards/st/nucleo_h745zi_q/Kconfig.defconfig index 9ad83aa96d1..cf1ac05e519 100644 --- a/boards/st/nucleo_h745zi_q/Kconfig.defconfig +++ b/boards/st/nucleo_h745zi_q/Kconfig.defconfig @@ -1,6 +1,6 @@ # STM32H745ZI Nucleo board configuration -# Copyright (c) 2020 Alexander Kozhinov +# Copyright (c) 2020 Alexander Kozhinov # SPDX-License-Identifier: Apache-2.0 if BOARD_NUCLEO_H745ZI_Q diff --git a/boards/st/nucleo_h745zi_q/Kconfig.nucleo_h745zi_q b/boards/st/nucleo_h745zi_q/Kconfig.nucleo_h745zi_q index 6d19d1592ae..5ec26624339 100644 --- a/boards/st/nucleo_h745zi_q/Kconfig.nucleo_h745zi_q +++ b/boards/st/nucleo_h745zi_q/Kconfig.nucleo_h745zi_q @@ -1,6 +1,6 @@ # STM32H745ZI Nucleo board configuration -# Copyright (c) 2020 Alexander Kozhinov +# Copyright (c) 2020 Alexander Kozhinov # SPDX-License-Identifier: Apache-2.0 config BOARD_NUCLEO_H745ZI_Q diff --git a/boards/st/nucleo_h745zi_q/arduino_r3_connector.dtsi b/boards/st/nucleo_h745zi_q/arduino_r3_connector.dtsi index d7b3dc5dc94..5cd745344e1 100644 --- a/boards/st/nucleo_h745zi_q/arduino_r3_connector.dtsi +++ b/boards/st/nucleo_h745zi_q/arduino_r3_connector.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020 Alexander Kozhinov + * Copyright (c) 2020 Alexander Kozhinov * * SPDX-License-Identifier: Apache-2.0 */ diff --git a/boards/st/nucleo_h745zi_q/board.cmake b/boards/st/nucleo_h745zi_q/board.cmake index 716e0812e71..00797ab426f 100644 --- a/boards/st/nucleo_h745zi_q/board.cmake +++ b/boards/st/nucleo_h745zi_q/board.cmake @@ -1,5 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -# Copyright (c) 2020 Alexander Kozhinov +# Copyright (c) 2020 Alexander Kozhinov # keep first board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") diff --git a/boards/st/nucleo_h745zi_q/doc/index.rst b/boards/st/nucleo_h745zi_q/doc/index.rst index c0e5d3db722..39a74a81ab7 100644 --- a/boards/st/nucleo_h745zi_q/doc/index.rst +++ b/boards/st/nucleo_h745zi_q/doc/index.rst @@ -1,7 +1,4 @@ -.. _nucleo_h745zi_q_board: - -ST Nucleo H745ZI-Q -################### +.. zephyr:board:: nucleo_h745zi_q Overview ******** @@ -45,10 +42,6 @@ Key Features STM32Cube MCU package. - Arm* Mbed Enabled* compliant (only for some Nucleo part numbers) -.. image:: img/nucleo_h745zi_q.jpg - :align: center - :alt: Nucleo H745ZI-Q - More information about the board can be found at the `Nucleo H745ZI-Q website`_. Hardware @@ -119,6 +112,8 @@ features: +-------------+------------+-------------------------------------+ | SPI | on-chip | spi | +-------------+------------+-------------------------------------+ +| FDCAN | on-chip | CAN-FD Control Area Network | ++-------------+------------+-------------------------------------+ Other hardware features are not yet supported on this Zephyr port. @@ -137,7 +132,7 @@ and a ST morpho connector. Board is configured as follows: - UART_3 TX/RX : PD8/PD9 (ST-Link Virtual Port Com) - USER_PB : PC13 - LD1 : PB0 -- LD2 : PB7 +- LD2 : PE1 - LD3 : PB14 - I2C : PB8, PB9 - SPI : PA5, PA6, PB5, PD14 diff --git a/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m4.dts b/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m4.dts index de94f2d0513..3ff190489f5 100644 --- a/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m4.dts +++ b/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m4.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020 Alexander Kozhinov + * Copyright (c) 2020 Alexander Kozhinov * * SPDX-License-Identifier: Apache-2.0 */ diff --git a/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m4_defconfig b/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m4_defconfig index 7d56efa651b..d0dcb5e539f 100644 --- a/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m4_defconfig +++ b/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m4_defconfig @@ -1,5 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -# Copyright (c) 2020 Alexander Kozhinov +# Copyright (c) 2020 Alexander Kozhinov # Enable GPIO CONFIG_GPIO=y diff --git a/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7.dts b/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7.dts index a09d693b029..c79712968e1 100644 --- a/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7.dts +++ b/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020 Alexander Kozhinov + * Copyright (c) 2020 Alexander Kozhinov * * SPDX-License-Identifier: Apache-2.0 */ @@ -26,6 +26,7 @@ zephyr,dtcm = &dtcm; zephyr,sram = &sram0; zephyr,flash = &flash0; + zephyr,canbus = &fdcan1; }; pwmleds { @@ -144,3 +145,14 @@ zephyr_udc0: &usbotg_fs { pinctrl-names = "default"; status = "okay"; }; + +&fdcan1 { + pinctrl-0 = <&fdcan1_rx_pd0 &fdcan1_tx_pd1>; + /* HSE will be used by default. Uncomment below to enable APB1.2 120MHz clock */ + /* + * clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000100>, + * <&rcc STM32_SRC_PLL1_Q FDCAN_SEL(1)>; + */ + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7.yaml b/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7.yaml index ff551e71837..259cd29438b 100644 --- a/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7.yaml +++ b/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7.yaml @@ -16,6 +16,7 @@ supported: - counter - i2c - pwm + - can - netif:eth - spi - usb_device diff --git a/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7_defconfig b/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7_defconfig index 753f46510e3..7575c09f0e2 100644 --- a/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7_defconfig +++ b/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7_defconfig @@ -1,5 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -# Copyright (c) 2020 Alexander Kozhinov +# Copyright (c) 2020 Alexander Kozhinov # Enable the internal SMPS regulator CONFIG_POWER_SUPPLY_DIRECT_SMPS=y diff --git a/boards/st/nucleo_h745zi_q/support/openocd.cfg b/boards/st/nucleo_h745zi_q/support/openocd.cfg index ce4836e9c82..21f5f6452b6 100644 --- a/boards/st/nucleo_h745zi_q/support/openocd.cfg +++ b/boards/st/nucleo_h745zi_q/support/openocd.cfg @@ -1,6 +1,6 @@ # STM32H745ZI Nucleo board OpenOCD ST-LINK V3 configuration # -# Copyright (c) 2020 Alexander Kozhinov +# Copyright (c) 2020 Alexander Kozhinov # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/st/nucleo_h753zi/doc/index.rst b/boards/st/nucleo_h753zi/doc/index.rst index e9af66a3232..a6b8dcf0bf6 100644 --- a/boards/st/nucleo_h753zi/doc/index.rst +++ b/boards/st/nucleo_h753zi/doc/index.rst @@ -1,7 +1,4 @@ -.. _nucleo_h753zi_board: - -ST Nucleo H753ZI -################ +.. zephyr:board:: nucleo_h753zi Overview ******** @@ -44,10 +41,6 @@ Key Features STM32Cube MCU package. - Arm* Mbed Enabled* compliant (only for some Nucleo part numbers) -.. image:: img/nucleo_h753zi.jpg - :align: center - :alt: Nucleo H753ZI - More information about the board can be found at the `Nucleo H753ZI website`_. Hardware @@ -140,12 +133,12 @@ and a ST morpho connector. Board is configured as follows: - UART_3 TX/RX : PD8/PD9 (ST-Link Virtual Port Com) - USER_PB : PC13 - LD1 : PB0 -- LD2 : PB7 +- LD2 : PE1 - LD3 : PB14 - I2C : PB8, PB9 - ADC1_INP15 : PA3 - ETH : PA1, PA2, PA7, PB13, PC1, PC4, PC5, PG11, PG13 -- SPI1 NSS/SCK/MISO/MOSI : PD14PA5/PA6/PB5 (Arduino SPI) +- SPI1 NSS/SCK/MISO/MOSI : PD14/PA5/PA6/PB5 (Arduino SPI) - CAN/CANFD : PD0, PD1 System Clock diff --git a/boards/st/nucleo_h753zi/nucleo_h753zi.dts b/boards/st/nucleo_h753zi/nucleo_h753zi.dts index d4217cfae58..83ee70c171d 100644 --- a/boards/st/nucleo_h753zi/nucleo_h753zi.dts +++ b/boards/st/nucleo_h753zi/nucleo_h753zi.dts @@ -147,7 +147,7 @@ zephyr_udc0: &usbotg_fs { &adc1 { pinctrl-0 = <&adc1_inp15_pa3>; pinctrl-names = "default"; - st,adc-clock-source = ; + st,adc-clock-source = "SYNC"; st,adc-prescaler = <4>; status = "okay"; }; diff --git a/boards/st/nucleo_h755zi_q/doc/index.rst b/boards/st/nucleo_h755zi_q/doc/index.rst index 3d509cc90ba..cc29afb0009 100644 --- a/boards/st/nucleo_h755zi_q/doc/index.rst +++ b/boards/st/nucleo_h755zi_q/doc/index.rst @@ -1,7 +1,4 @@ -.. _nucleo_h755zi_q_board: - -ST Nucleo H755ZI-Q -################### +.. zephyr:board:: nucleo_h755zi_q Overview ******** @@ -37,10 +34,6 @@ Key Features - capability: mass storage, virtual COM port and debug port - USB OTG full speed or device only -.. image:: img/nucleo_h755zi_q.webp - :align: center - :alt: Nucleo H755ZI-Q - More information about the board can be found at the `Nucleo H755ZI-Q website`_. Hardware diff --git a/boards/st/nucleo_h7a3zi_q/doc/index.rst b/boards/st/nucleo_h7a3zi_q/doc/index.rst index 0de0ef109eb..e823191e625 100644 --- a/boards/st/nucleo_h7a3zi_q/doc/index.rst +++ b/boards/st/nucleo_h7a3zi_q/doc/index.rst @@ -1,7 +1,4 @@ -.. _nucleo_h7a3zi_q_board: - -ST Nucleo H7A3ZI-Q -################## +.. zephyr:board:: nucleo_h7a3zi_q Overview ******** @@ -42,10 +39,6 @@ Key Features STM32Cube MCU package. - Arm* Mbed Enabled* compliant (only for some Nucleo part numbers) -.. image:: img/nucleo_h7a3zi_q.jpg - :align: center - :alt: Nucleo H7A3ZI-Q - More information about the board can be found at the `Nucleo H7A3ZI-Q website`_. Hardware diff --git a/boards/st/nucleo_h7a3zi_q/nucleo_h7a3zi_q.dts b/boards/st/nucleo_h7a3zi_q/nucleo_h7a3zi_q.dts index 410bd0b6904..71ee9ccf017 100644 --- a/boards/st/nucleo_h7a3zi_q/nucleo_h7a3zi_q.dts +++ b/boards/st/nucleo_h7a3zi_q/nucleo_h7a3zi_q.dts @@ -116,7 +116,7 @@ &adc1 { pinctrl-0 = <&adc1_inp15_pa3>; pinctrl-names = "default"; - st,adc-clock-source = ; + st,adc-clock-source = "SYNC"; st,adc-prescaler = <4>; status = "okay"; }; diff --git a/boards/st/nucleo_h7s3l8/Kconfig.defconfig b/boards/st/nucleo_h7s3l8/Kconfig.defconfig new file mode 100644 index 00000000000..fdb5f99d840 --- /dev/null +++ b/boards/st/nucleo_h7s3l8/Kconfig.defconfig @@ -0,0 +1,16 @@ +# STM32H7S3L8 NUCLEO board configuration +# +# Copyright (c) 2024 STMicroelectronics +# +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NUCLEO_H7S3L8 + +if NETWORKING + +config NET_L2_ETHERNET + default y + +endif # NETWORKING + +endif # BOARD_NUCLEO_H7S3L8 diff --git a/boards/st/nucleo_h7s3l8/Kconfig.nucleo_h7s3l8 b/boards/st/nucleo_h7s3l8/Kconfig.nucleo_h7s3l8 new file mode 100644 index 00000000000..ef9af59919b --- /dev/null +++ b/boards/st/nucleo_h7s3l8/Kconfig.nucleo_h7s3l8 @@ -0,0 +1,5 @@ +# Copyright (c) 2024 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_H7S3L8 + select SOC_STM32H7S3XX diff --git a/boards/st/nucleo_h7s3l8/arduino_r3_connector.dtsi b/boards/st/nucleo_h7s3l8/arduino_r3_connector.dtsi new file mode 100644 index 00000000000..13e390200fd --- /dev/null +++ b/boards/st/nucleo_h7s3l8/arduino_r3_connector.dtsi @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2024 STMicroelectronics + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + arduino_header: connector { + compatible = "arduino-header-r3"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpioa 3 0>, /* A0 */ + <1 0 &gpioc 0 0>, /* A1 */ + <2 0 &gpioc 3 0>, /* A2 */ + <3 0 &gpioc 4 0>, /* A3 */ + <4 0 &gpioc 5 0>, /* A4 */ + <5 0 &gpiof 11 0>, /* A5 */ + <6 0 &gpioa 10 0>, /* D0 */ + <7 0 &gpiob 14 0>, /* D1 */ + <8 0 &gpiof 15 0>, /* D2 */ + <9 0 &gpioe 13 0>, /* D3 */ + <10 0 &gpiof 3 0>, /* D4 */ + <11 0 &gpioe 11 0>, /* D5 */ + <12 0 &gpioe 9 0>, /* D6 */ + <13 0 &gpiof 4 0>, /* D7 */ + <14 0 &gpiof 5 0>, /* D8 */ + <15 0 &gpiod 15 0>, /* D9 */ + <16 0 &gpiod 14 0>, /* D10 */ + <17 0 &gpiob 5 0>, /* D11 */ + <18 0 &gpioa 6 0>, /* D12 */ + <19 0 &gpioa 5 0>, /* D13 */ + <20 0 &gpiob 9 0>, /* D14 */ + <21 0 &gpiob 8 0>; /* D15 */ + }; +}; + +arduino_i2c: &i2c1 {}; +arduino_spi: &spi1 {}; +arduino_serial: &usart1 {}; diff --git a/boards/st/nucleo_h7s3l8/board.cmake b/boards/st/nucleo_h7s3l8/board.cmake new file mode 100644 index 00000000000..6c18b45b35e --- /dev/null +++ b/boards/st/nucleo_h7s3l8/board.cmake @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 + +# keep first +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") + +board_runner_args(openocd --target-handle=_CHIPNAME.cpu0) + +# keep first +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/st/nucleo_h7s3l8/board.yml b/boards/st/nucleo_h7s3l8/board.yml new file mode 100644 index 00000000000..6d71cded43f --- /dev/null +++ b/boards/st/nucleo_h7s3l8/board.yml @@ -0,0 +1,6 @@ +board: + name: nucleo_h7s3l8 + full_name: Nucleo H7S3L8 + vendor: st + socs: + - name: stm32h7s3xx diff --git a/boards/st/nucleo_h7s3l8/doc/img/nucleo_h7s3l8.webp b/boards/st/nucleo_h7s3l8/doc/img/nucleo_h7s3l8.webp new file mode 100644 index 00000000000..af2535e26b2 Binary files /dev/null and b/boards/st/nucleo_h7s3l8/doc/img/nucleo_h7s3l8.webp differ diff --git a/boards/st/nucleo_h7s3l8/doc/index.rst b/boards/st/nucleo_h7s3l8/doc/index.rst new file mode 100644 index 00000000000..e869bcbe9ca --- /dev/null +++ b/boards/st/nucleo_h7s3l8/doc/index.rst @@ -0,0 +1,324 @@ +.. _nucleo_h7s3l8_board: + +ST Nucleo H7S3L8 +################ + +Overview +******** + +The STM32 Nucleo-144 board provides an affordable and flexible way for users +to try out new concepts and build prototypes by choosing from the various combinations +of performance and power consumption features, provided by the STM32 microcontroller. + +The ST Zio connector, which extends the ARDUINO® Uno V3 connectivity, and +the ST morpho headers provide an easy means of expanding the functionality of the Nucleo +open development platform with a wide choice of specialized shields. +The STM32 Nucleo-144 board does not require any separate probe as it integrates +the ST-LINK V3 debugger/programmer. + +The STM32 Nucleo-144 board comes with the STM32 comprehensive free software +libraries and examples available with the STM32Cube MCU Package. + +Key Features + +- STM32 microcontroller with 64Kbytes of flash and 620Kbytes of RAM in TFBGA225 package +- Ethernet compliant with IEEE-802.3-2002 +- USB USB Device only, USB OTG full speed, or SNK/UFP (full-speed or high-speed mode) +- 3 user LEDs +- 2 user and reset push-buttons +- 32.768 kHz crystal oscillator +- Board connectors: + + - USB with Micro-AB or USB Type-C® + - Ethernet RJ45 + - MIPI20 compatible connector with trace signals + +- Flexible power-supply options: ST-LINK USB VBUS or external sources +- External or internal SMPS to generate Vcore logic supply +- On-board ST-LINK/V3 debugger/programmer with USB re-enumeration +- capability: mass storage, virtual COM port and debug port + + +.. image:: img/nucleo_h7s3l8.webp + :align: center + :alt: Nucleo H7S3L8 + +More information about the board can be found at the `Nucleo H7S3L8 website`_. + +Hardware +******** + +Nucleo H7S3L8 provides the following hardware components: + +The STM32H7S7xx devices are a high-performance microcontrollers family (STM32H7 +Series) based on the high-performance Arm |reg| Cortex |reg|-M7 32-bit RISC core. +They operate at a frequency of up to 500 MHz. + +- Core: ARM |reg| 32-bit Cortex |reg| -M7 CPU with TrustZone |reg| and FPU. +- Performance benchmark: + + - 1284 DMPIS/MHz (Dhrystone 2.1) + +- Security + + - Arm |reg| TrustZone |reg| with ARMv8-M mainline security extension + - Up to 8 configurable SAU regions + - TrustZone |reg| aware and securable peripherals + - Flexible lifecycle scheme with secure debug authentication + - Preconfigured immutable root of trust (ST-iROT) + - SFI (secure firmware installation) + - Secure data storage with hardware unique key (HUK) + - Secure firmware upgrade support with TF-M + - 2x AES coprocessors including one with DPA resistance + - Public key accelerator, DPA resistant + - On-the-fly decryption of Octo-SPI external memories + - HASH hardware accelerator + - True random number generator, NIST SP800-90B compliant + - 96-bit unique ID + - Active tampers + - True Random Number Generator (RNG) NIST SP800-90B compliant + +- Clock management: + + - 24 MHz crystal oscillator (HSE) + - 32768 Hz crystal oscillator for RTC (LSE) + - Internal 64 MHz (HSI) trimmable by software + - Internal low-power 32 kHz RC (LSI)( |plusminus| 5%) + - Internal 4 MHz oscillator (CSI), trimmable by software + - Internal 48 MHz (HSI48) with recovery system + - 3 PLLs for system clock, USB, audio, ADC + +- Power management + + - Embedded regulator (LDO) with three configurable range output to supply the digital circuitry + + +- RTC with HW calendar, alarms and calibration +- Up to 152 fast I/Os, most 5 V-tolerant, up to 10 I/Os with independent supply down to 1.08 V +- Up to 16 timers and 2 watchdogs + + - 16x 16-bit + - 4x 32-bit timers with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input + - 5x 16-bit low-power 16-bit timers (available in Stop mode) + - 2x watchdogs + - 1x SysTick timer + +- Memories + + - Up to 64KB Flash, 2 banks read-while-write + - 1 Kbyte OTP (one-time programmable) + - 640 KB of SRAM including 64 KB with hardware parity check and 320 Kbytes with flexible ECC + - 4 Kbytes of backup SRAM available in the lowest power modes + - Flexible external memory controller with up to 16-bit data bus: SRAM, PSRAM, FRAM, SDRAM/LPSDR SDRAM, NOR/NAND memories + - 2x OCTOSPI memory interface with on-the-fly decryption and support for serial PSRAM/NAND/NOR, Hyper RAM/Flash frame formats + - 1x HEXASPI memory interface with on-the-fly decryption and support for serial PSRAM/NAND/NOR, Hyper RAM/Flash frame formats + - 2x SD/SDIO/MMC interfaces + +- Rich analog peripherals (independent supply) + + - 2x 12-bit ADC with up to 5 MSPS in 12-bit + - 1x Digital temperature sensor + +- 35x communication interfaces + + - 1x USB Type-C / USB power-delivery controller + - 1x USB OTG full-speed with PHY + - 1x USB OTG high-speed with PHY + - 3x I2C FM+ interfaces (SMBus/PMBus) + - 1x I3C interface + - 7x U(S)ARTS (ISO7816 interface, LIN, IrDA, modem control) + - 2x LP UART + - 6x SPIs including 3 muxed with full-duplex I2S + - 2x SAI + - 2x FDCAN + - 2x SD/SDIO/MMC interface + - 2x 16 channel DMA controllers + - 1x 8- to 16- bit camera interface + - 1x HDMI-CEC + - 1x Ethernel MAC interface with DMA controller + - 1x 16-bit parallel slave synchronous-interface + - 1x SPDIF-IN interface + - 1x MDIO slave interface + +- CORDIC for trigonometric functions acceleration +- FMAC (filter mathematical accelerator) +- CRC calculation unit +- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade| + + + +More information about STM32H7S3 can be found here: + +- `STM32H7S3L8 on www.st.com`_ +- `STM32H7Sx reference manual`_ + + +Supported Features +================== + +The Zephyr ``nucleo_h7s3l8`` board target supports the following hardware +features: + ++-------------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++=============+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-------------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++-------------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-------------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-------------+------------+-------------------------------------+ +| RTC | on-chip | counter | ++-------------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-------------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-------------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-------------+------------+-------------------------------------+ +| RNG | on-chip | True Random number generator | ++-------------+------------+-------------------------------------+ +| Backup SRAM | on-chip | Backup SRAM | ++-------------+------------+-------------------------------------+ +| RTC | on-chip | rtc | ++-------------+------------+-------------------------------------+ + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in the defconfig files: +:zephyr_file:`boards/st/nucleo_h7s3l8/nucleo_h7s3l8_defconfig` + +For more details please refer to `STM32H7R/S Nucleo-144 board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +The Nucleo H7S3L8 board features a ST Zio connector (extended Arduino Uno V3) +and a ST morpho connector. Board is configured as follows: + +- UART_3 TX/RX : PD8/PD9 (ST-Link Virtual Port Com) +- USER_PB : PC13 +- LD1 : PD10 +- LD2 : PD13 +- LD3 : PB7 +- I2C : PB8, PB9 +- SPI1 NSS/SCK/MISO/MOSI : PD14PA5/PA6/PB5 (Arduino SPI) + +System Clock +------------ + +Nucleo H7S3L8 System Clock could be driven by an internal or external +oscillator, as well as the main PLL clock. By default, the System clock is +driven by the PLL clock at 600MHz, driven by an 24MHz high-speed external clock. + +Serial Port +----------- + +Nucleo H7S3L8 board has 4 UARTs and 3 USARTs plus one LowPower UART. The Zephyr console +output is assigned to UART3. Default settings are 115200 8N1. + +Backup SRAM +----------- + +In order to test backup SRAM you may want to disconnect VBAT from VDD. You can +do it by removing ``SB13`` jumper on the back side of the board. + +Programming and Debugging +************************* + +Nucleo H7S3L8 board includes an ST-LINK/V3 embedded debug tool interface. + +.. note:: + + Check if your ST-LINK V3 has newest FW version. It can be done with `STM32CubeProgrammer`_ + +Flashing +======== + +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. + +Alternatively, OpenOCD or JLink can also be used to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner openocd + +Flashing an application to Nucleo H7S3L8 +---------------------------------------- + +First, connect the NUCLEO-H7S3L8 to your host computer using +the USB port to prepare it for flashing. Then build and flash your application. + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +Run a serial host program to connect with your NUCLEO-H7S3L8 board. + +.. code-block:: console + + $ minicom -b 115200 -D /dev/ttyACM0 + +or use screen: + +.. code-block:: console + + $ screen /dev/ttyACM0 115200 + +Build and flash the application: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_h7s3l8 + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + $ Hello World! nucleo_h7s3l8 + +Blinky example can also be used: + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: nucleo_h7s3l8 + :goals: build flash + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_h7s3l8 + :maybe-skip-config: + :goals: debug + +.. _Nucleo H7S3L8 website: + https://www.st.com/en/evaluation-tools/nucleo-h7s3l8.html + +.. _STM32H7R/S Nucleo-144 board User Manual: + https://www.st.com/resource/en/user_manual/um3276-stm32h7rx7sx-nucleo144-board-mb1737-stmicroelectronics.pdf + +.. _STM32H7S3L8 on www.st.com: + https://www.st.com/en/microcontrollers-microprocessors/stm32h7s3l8.html + +.. _STM32H7Sx reference manual: + https://www.st.com/resource/en/reference_manual/rm0477-stm32h7rx7sx-armbased-32bit-mcus-stmicroelectronics.pdf + +.. _OpenOCD installing Debug Version: + https://github.com/zephyrproject-rtos/openocd + +.. _OpenOCD installing with ST-LINK V3 support: + https://mbd.kleier.net/integrating-st-link-v3.html + +.. _STM32CubeIDE: + https://www.st.com/en/development-tools/stm32cubeide.html + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/st/nucleo_h7s3l8/nucleo_h7s3l8.dts b/boards/st/nucleo_h7s3l8/nucleo_h7s3l8.dts new file mode 100644 index 00000000000..e5d817bea57 --- /dev/null +++ b/boards/st/nucleo_h7s3l8/nucleo_h7s3l8.dts @@ -0,0 +1,141 @@ +/* + * Copyright (c) 2024 STMicroelectronics + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include "arduino_r3_connector.dtsi" +#include + +/ { + model = "STMicroelectronics STM32H7S3L8-NUCLEO board"; + compatible = "st,stm32h7s3l8-nucleo"; + + chosen { + zephyr,console = &usart3; + zephyr,shell-uart = &usart3; + zephyr,dtcm = &dtcm; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + }; + + leds: leds { + compatible = "gpio-leds"; + green_led: led_1 { + gpios = <&gpiod 10 GPIO_ACTIVE_HIGH>; + label = "User LD1"; + }; + yellow_led: led_2 { + gpios = <&gpiod 13 GPIO_ACTIVE_HIGH>; + label = "User LD2"; + }; + red_led: led_3 { + gpios = <&gpiob 7 GPIO_ACTIVE_HIGH>; + label = "User LD3"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + user_button: button_0 { + label = "User"; + gpios = <&gpioc 13 GPIO_ACTIVE_HIGH>; + zephyr,code = ; + }; + }; + + aliases { + led0 = &green_led; + led1 = &yellow_led; + led2 = &red_led; + sw0 = &user_button; + watchdog0 = &iwdg; + }; +}; + +&clk_lsi { + status = "disabled"; +}; + +&clk_hsi48 { + status = "disabled"; +}; + +&clk_hse { + clock-frequency = ; + status = "okay"; +}; + +&clk_lse { + status = "okay"; +}; + +&pll { + div-m = <12>; + mul-n = <200>; + div-p = <2>; + div-q = <2>; + div-r = <2>; + div-s = <2>; + div-t = <2>; + clocks = <&clk_hse>; + status = "okay"; +}; + +&rcc { + clocks = <&pll>; + clock-frequency = ; + dcpre = <1>; + hpre = <1>; + ppre1 = <2>; + ppre2 = <2>; + ppre4 = <2>; + ppre5 = <2>; +}; + +&usart1 { + pinctrl-0 = <&usart1_tx_pb14 &usart1_rx_pa10>; + pinctrl-names = "default"; + current-speed = <115200>; + status = "okay"; +}; + +&usart3 { + pinctrl-0 = <&usart3_tx_pd8 &usart3_rx_pd9>; + pinctrl-names = "default"; + current-speed = <115200>; + status = "okay"; +}; + +&iwdg { + status = "okay"; +}; + +&wwdg { + status = "okay"; +}; + +&adc1 { + pinctrl-0 = <&adc1_inp15_pa3>; /* Arduino A0 */ + pinctrl-names = "default"; + st,adc-clock-source = "SYNC"; + st,adc-prescaler = <4>; + status = "okay"; +}; + +&spi1 { + status = "okay"; + pinctrl-0 = <&spi1_sck_pa5 &spi1_miso_pa6 &spi1_mosi_pb5>; + pinctrl-names = "default"; + cs-gpios = <&gpiod 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_scl_pb8 &i2c1_sda_pb9>; + pinctrl-names = "default"; + status = "okay"; + clock-frequency = ; +}; diff --git a/boards/st/nucleo_h7s3l8/nucleo_h7s3l8.yaml b/boards/st/nucleo_h7s3l8/nucleo_h7s3l8.yaml new file mode 100644 index 00000000000..f7b72a70d92 --- /dev/null +++ b/boards/st/nucleo_h7s3l8/nucleo_h7s3l8.yaml @@ -0,0 +1,15 @@ +identifier: nucleo_h7s3l8 +name: ST Nucleo H7S3L8 nucleo +type: mcu +arch: arm +toolchain: + - zephyr +ram: 640 +flash: 64 +supported: + - gpio + - uart + - watchdog + - entropy + - adc +vendor: st diff --git a/boards/st/nucleo_h7s3l8/nucleo_h7s3l8_defconfig b/boards/st/nucleo_h7s3l8/nucleo_h7s3l8_defconfig new file mode 100644 index 00000000000..3ed77fa885c --- /dev/null +++ b/boards/st/nucleo_h7s3l8/nucleo_h7s3l8_defconfig @@ -0,0 +1,21 @@ +# Copyright (c) 2024 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +# Disable SMPS +CONFIG_POWER_SUPPLY_DIRECT_SMPS=n + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable HW stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable GPIO +CONFIG_GPIO=y diff --git a/boards/st/nucleo_h7s3l8/support/openocd.cfg b/boards/st/nucleo_h7s3l8/support/openocd.cfg new file mode 100644 index 00000000000..af84952d31d --- /dev/null +++ b/boards/st/nucleo_h7s3l8/support/openocd.cfg @@ -0,0 +1,42 @@ + +source [find interface/stlink-dap.cfg] +transport select "dapdirect_swd" + +set WORKAREASIZE 0x8000 +set CHIPNAME STM32H7S3XX +set BOARDNAME NUCLEO-H7S3L8 + +# Enable debug when in low power modes +set ENABLE_LOW_POWER 1 + +# Stop Watchdog counters when halt +set STOP_WATCHDOG 1 + +# Reset configuration +# use hardware reset, connect under reset +# connect_assert_srst needed if low power mode application running (WFI...) +# reset_config srst_only srst_nogate connect_assert_srst + +#set CONNECT_UNDER_RESET 1 +#set CORE_RESET 0 + +source [find target/stm32h7rx.cfg] + + +$_CHIPNAME.cpu0 configure -event gdb-attach { + echo "Debugger attaching: halting execution" + gdb_breakpoint_override hard +} + +$_CHIPNAME.cpu0 configure -event gdb-detach { + echo "Debugger detaching: resuming execution" + resume +} + +# Due to the use of connect_assert_srst, running gdb requires +# to reset halt just after openocd init. +rename init old_init +proc init {} { + old_init + reset halt +} diff --git a/boards/st/nucleo_l011k4/doc/index.rst b/boards/st/nucleo_l011k4/doc/index.rst index b1d9396f7ed..cb8ad43e2ab 100644 --- a/boards/st/nucleo_l011k4/doc/index.rst +++ b/boards/st/nucleo_l011k4/doc/index.rst @@ -1,7 +1,4 @@ -.. _nucleo_l011k4_board: - -ST Nucleo L011K4 -################ +.. zephyr:board:: nucleo_l011k4 Overview ******** @@ -20,10 +17,6 @@ The STM32 Nucleo board integrates the ST-LINK/V2-1 debugger and programmer. The STM32 Nucleo board comes with the STM32 comprehensive software HAL library together with various packaged software examples. -.. image:: img/nucleo_l011k4.jpg - :align: center - :alt: Nucleo L011K4 - More information about the board can be found at the `Nucleo L011K4 website`_. Hardware diff --git a/boards/st/nucleo_l031k6/doc/index.rst b/boards/st/nucleo_l031k6/doc/index.rst index 0845a046fc0..b5a7727a238 100644 --- a/boards/st/nucleo_l031k6/doc/index.rst +++ b/boards/st/nucleo_l031k6/doc/index.rst @@ -1,7 +1,4 @@ -.. _nucleo_l031k6_board: - -ST Nucleo L031K6 -################ +.. zephyr:board:: nucleo_l031k6 Overview ******** @@ -20,10 +17,6 @@ The STM32 Nucleo board integrates the ST-LINK/V2-1 debugger and programmer. The STM32 Nucleo board comes with the STM32 comprehensive software HAL library together with various packaged software examples. -.. image:: img/nucleo_l031k6.jpg - :align: center - :alt: Nucleo L031K6 - More information about the board can be found at the `Nucleo L031K6 website`_. Hardware diff --git a/boards/st/nucleo_l053r8/doc/index.rst b/boards/st/nucleo_l053r8/doc/index.rst index 4fd63f57f43..755520a2bfb 100644 --- a/boards/st/nucleo_l053r8/doc/index.rst +++ b/boards/st/nucleo_l053r8/doc/index.rst @@ -1,7 +1,4 @@ -.. _nucleo_l053r8_board: - -ST Nucleo L053R8 -################ +.. zephyr:board:: nucleo_l053r8 Overview ******** @@ -20,10 +17,6 @@ The STM32 Nucleo board integrates the ST-LINK/V2-1 debugger and programmer. The STM32 Nucleo board comes with the STM32 comprehensive software HAL library together with various packaged software examples. -.. image:: img/nucleo_l053r8.jpg - :align: center - :alt: Nucleo L053R8 - More information about the board can be found at the `Nucleo L053R8 website`_. Hardware diff --git a/boards/st/nucleo_l073rz/doc/index.rst b/boards/st/nucleo_l073rz/doc/index.rst index 6ea4076a98a..401290d90de 100644 --- a/boards/st/nucleo_l073rz/doc/index.rst +++ b/boards/st/nucleo_l073rz/doc/index.rst @@ -1,7 +1,4 @@ -.. _nucleo_l073rz_board: - -ST Nucleo L073RZ -################ +.. zephyr:board:: nucleo_l073rz Overview ******** @@ -20,10 +17,6 @@ The STM32 Nucleo board integrates the ST-LINK/V2-1 debugger and programmer. The STM32 Nucleo board comes with the STM32 comprehensive software HAL library together with various packaged software examples. -.. image:: img/nucleo_l073rz.jpg - :align: center - :alt: Nucleo L073RZ - More information about the board can be found at the `Nucleo L073RZ website`_. Hardware diff --git a/boards/st/nucleo_l073rz/nucleo_l073rz.dts b/boards/st/nucleo_l073rz/nucleo_l073rz.dts index eefd8d428e7..11db6940d18 100644 --- a/boards/st/nucleo_l073rz/nucleo_l073rz.dts +++ b/boards/st/nucleo_l073rz/nucleo_l073rz.dts @@ -140,7 +140,7 @@ stm32_lp_tick_source: &lptim1 { &adc1 { pinctrl-0 = <&adc_in0_pa0>; pinctrl-names = "default"; - st,adc-clock-source = ; + st,adc-clock-source = "SYNC"; st,adc-prescaler = <4>; status = "okay"; }; diff --git a/boards/st/nucleo_l152re/doc/index.rst b/boards/st/nucleo_l152re/doc/index.rst index c4d18190a23..1973ffa8e5a 100644 --- a/boards/st/nucleo_l152re/doc/index.rst +++ b/boards/st/nucleo_l152re/doc/index.rst @@ -1,7 +1,4 @@ -.. _nucleo_l152re_board: - -ST Nucleo L152RE -################ +.. zephyr:board:: nucleo_l152re Overview ******** @@ -20,10 +17,6 @@ The STM32 Nucleo board integrates the ST-LINK/V2-1 debugger and programmer. The STM32 Nucleo board comes with the STM32 comprehensive software HAL library together with various packaged software examples. -.. image:: img/nucleo_l152re.jpg - :align: center - :alt: NUCLEO-L152RE - More information about the board can be found at the `Nucleo L152RE website`_. Hardware diff --git a/boards/st/nucleo_l152re/nucleo_l152re.dts b/boards/st/nucleo_l152re/nucleo_l152re.dts index fc308f5988f..d1278873fd8 100644 --- a/boards/st/nucleo_l152re/nucleo_l152re.dts +++ b/boards/st/nucleo_l152re/nucleo_l152re.dts @@ -124,7 +124,7 @@ &adc1 { pinctrl-0 = <&adc_in0_pa0>; pinctrl-names = "default"; - st,adc-clock-source = ; + st,adc-clock-source = "ASYNC"; st,adc-prescaler = <4>; status = "okay"; }; @@ -145,10 +145,10 @@ #address-cells = <1>; #size-cells = <1>; - /* Set 2KB of storage at the end of 512KB flash */ - storage_partition: partition@7f800 { + /* Set 8KB of storage at the end of 512KB flash */ + storage_partition: partition@7e000 { label = "storage"; - reg = <0x0007f800 DT_SIZE_K(2)>; + reg = <0x0007e000 DT_SIZE_K(8)>; }; }; }; diff --git a/boards/st/nucleo_l412rb_p/doc/index.rst b/boards/st/nucleo_l412rb_p/doc/index.rst index 11a12390782..75caa4e9f1b 100644 --- a/boards/st/nucleo_l412rb_p/doc/index.rst +++ b/boards/st/nucleo_l412rb_p/doc/index.rst @@ -1,7 +1,4 @@ -.. _nucleo_l412rb_p_board: - -ST Nucleo L412RB-P -################## +.. zephyr:board:: nucleo_l412rb_p Overview ******** @@ -37,10 +34,6 @@ some highlights of the Nucleo L412RB board: - Arm® Mbed Enabled |trade| compliant -.. image:: img/nucleo_l412rb_p.jpg - :align: center - :alt: Nucleo L412RB - More information about the board can be found at the `Nucleo L412RB-P website`_. Hardware diff --git a/boards/st/nucleo_l412rb_p/nucleo_l412rb_p.dts b/boards/st/nucleo_l412rb_p/nucleo_l412rb_p.dts index 070260451f3..0ffe4545645 100644 --- a/boards/st/nucleo_l412rb_p/nucleo_l412rb_p.dts +++ b/boards/st/nucleo_l412rb_p/nucleo_l412rb_p.dts @@ -117,7 +117,7 @@ &adc1 { pinctrl-0 = <&adc1_in5_pa0>; pinctrl-names = "default"; - st,adc-clock-source = ; + st,adc-clock-source = "SYNC"; st,adc-prescaler = <4>; status = "okay"; }; diff --git a/boards/st/nucleo_l432kc/doc/index.rst b/boards/st/nucleo_l432kc/doc/index.rst index f312380a07c..ad17c525de5 100644 --- a/boards/st/nucleo_l432kc/doc/index.rst +++ b/boards/st/nucleo_l432kc/doc/index.rst @@ -1,7 +1,4 @@ -.. _nucleo_l432kc_board: - -ST Nucleo L432KC -################ +.. zephyr:board:: nucleo_l432kc Overview ******** @@ -21,10 +18,6 @@ some highlights of the Nucleo L432KC board: - Three LEDs: USB communication (LD1), power LED (LD2), user LED (LD3) - One push-button: RESET -.. image:: img/nucleo_l432kc.jpg - :align: center - :alt: Nucleo L432KC - More information about the board can be found at the `Nucleo L432KC website`_. Hardware diff --git a/boards/st/nucleo_l433rc_p/doc/index.rst b/boards/st/nucleo_l433rc_p/doc/index.rst index 75b3a8fe20e..5b61f6e7718 100644 --- a/boards/st/nucleo_l433rc_p/doc/index.rst +++ b/boards/st/nucleo_l433rc_p/doc/index.rst @@ -1,7 +1,4 @@ -.. _nucleo_l433rc_board: - -ST Nucleo L433RC -################ +.. zephyr:board:: nucleo_l433rc_p Overview ******** @@ -21,10 +18,6 @@ some highlights of the Nucleo L433RC board: - Three LEDs: USB communication (LD1), power LED (LD3), user LED (LD4) - One push-button: RESET -.. image:: img/nucleo_l433rc_p.jpg - :align: center - :alt: Nucleo L433RC - More information about the board can be found at the `Nucleo L433RC-P website`_. Hardware diff --git a/boards/st/nucleo_l452re/doc/index.rst b/boards/st/nucleo_l452re/doc/index.rst index 9587b9e6c02..2995387e8ae 100644 --- a/boards/st/nucleo_l452re/doc/index.rst +++ b/boards/st/nucleo_l452re/doc/index.rst @@ -1,7 +1,4 @@ -.. _nucleo_l452re_board: - -ST Nucleo L452RE -################ +.. zephyr:board:: nucleo_l452re Overview ******** @@ -25,10 +22,6 @@ Here some highlights of these boards: - Three LEDs: USB communication (LD1), user LED (LD2), power LED (LD3) - One push-button: RESET -.. image:: img/nucleo_l452re_p.jpg - :align: center - :alt: Nucleo L452RE-P - The main difference between the ST Nucleo L452RE and the L452RE-P (note the missing "-P" at the end) lays in the External Switched Mode Power Supply (SMPS) included in the P series. diff --git a/boards/st/nucleo_l452re/nucleo_l452re_common.dtsi b/boards/st/nucleo_l452re/nucleo_l452re_common.dtsi index 8f0d76d9a86..8db389d9074 100644 --- a/boards/st/nucleo_l452re/nucleo_l452re_common.dtsi +++ b/boards/st/nucleo_l452re/nucleo_l452re_common.dtsi @@ -121,7 +121,7 @@ */ storage_partition: partition@7c000 { label = "storage"; - reg = <0x0007c000 0x00008000>; + reg = <0x0007c000 0x00004000>; }; }; }; diff --git a/boards/st/nucleo_l476rg/doc/index.rst b/boards/st/nucleo_l476rg/doc/index.rst index ac566003430..7c0ddb76958 100644 --- a/boards/st/nucleo_l476rg/doc/index.rst +++ b/boards/st/nucleo_l476rg/doc/index.rst @@ -1,7 +1,4 @@ -.. _nucleo_l476rg_board: - -ST Nucleo L476RG -################ +.. zephyr:board:: nucleo_l476rg Overview ******** @@ -26,10 +23,6 @@ some highlights of the Nucleo L476RG board: - Three LEDs: USB communication (LD1), user LED (LD2), power LED (LD3) - Two push-buttons: USER and RESET -.. image:: img/nucleo_l476rg.jpg - :align: center - :alt: Nucleo L476RG - More information about the board can be found at the `Nucleo L476RG website`_. Hardware diff --git a/boards/st/nucleo_l476rg/nucleo_l476rg.dts b/boards/st/nucleo_l476rg/nucleo_l476rg.dts index 573c121dfd1..ecc5ea5cf7a 100644 --- a/boards/st/nucleo_l476rg/nucleo_l476rg.dts +++ b/boards/st/nucleo_l476rg/nucleo_l476rg.dts @@ -167,7 +167,7 @@ stm32_lp_tick_source: &lptim1 { &adc1 { pinctrl-0 = <&adc1_in1_pc0>; pinctrl-names = "default"; - st,adc-clock-source = ; + st,adc-clock-source = "SYNC"; st,adc-prescaler = <4>; status = "okay"; }; diff --git a/boards/st/nucleo_l496zg/doc/index.rst b/boards/st/nucleo_l496zg/doc/index.rst index 4abdc105c6a..838bec9905e 100644 --- a/boards/st/nucleo_l496zg/doc/index.rst +++ b/boards/st/nucleo_l496zg/doc/index.rst @@ -1,7 +1,4 @@ -.. _nucleo_l496zg_board: - -ST Nucleo L496ZG -################ +.. zephyr:board:: nucleo_l496zg Overview ******** @@ -28,10 +25,6 @@ some highlights of the Nucleo L476ZG board: power fault(LD5), power LED (LD6), USB FS OTG (LD7, LD8) - 2 push buttons: USER and RESET -.. image:: img/nucleo_l496zg.jpg - :align: center - :alt: Nucleo L496ZG - More information about the board can be found at the `Nucleo L496ZG website`_. Hardware diff --git a/boards/st/nucleo_l496zg/nucleo_l496zg.yaml b/boards/st/nucleo_l496zg/nucleo_l496zg.yaml index d1b92282d38..b9fba4e7853 100644 --- a/boards/st/nucleo_l496zg/nucleo_l496zg.yaml +++ b/boards/st/nucleo_l496zg/nucleo_l496zg.yaml @@ -5,7 +5,7 @@ arch: arm toolchain: - zephyr - gnuarmemb -ram: 320 +ram: 256 flash: 1024 supported: - arduino_i2c @@ -16,7 +16,6 @@ supported: - spi - pwm - counter - - usb - usb_device - usbd - watchdog diff --git a/boards/st/nucleo_l4a6zg/doc/index.rst b/boards/st/nucleo_l4a6zg/doc/index.rst index 267d5f619b8..aced6276860 100644 --- a/boards/st/nucleo_l4a6zg/doc/index.rst +++ b/boards/st/nucleo_l4a6zg/doc/index.rst @@ -1,7 +1,4 @@ -.. _nucleo_l4a6zg_board: - -ST Nucleo L4A6ZG -################ +.. zephyr:board:: nucleo_l4a6zg Overview ******** @@ -28,10 +25,6 @@ some highlights of the Nucleo L4A6ZG board: power fault(LD5), power LED (LD6), USB FS OTG (LD7, LD8) - 2 push buttons: USER and RESET -.. image:: ../../nucleo_l496zg/doc/img/nucleo_l496zg.jpg - :align: center - :alt: Nucleo L4A6ZG - More information about the board can be found at the `Nucleo L4A6ZG website`_. Hardware diff --git a/boards/st/nucleo_l4a6zg/nucleo_l4a6zg.dts b/boards/st/nucleo_l4a6zg/nucleo_l4a6zg.dts index 5e160d68556..3e5a14298d9 100644 --- a/boards/st/nucleo_l4a6zg/nucleo_l4a6zg.dts +++ b/boards/st/nucleo_l4a6zg/nucleo_l4a6zg.dts @@ -141,3 +141,7 @@ &wwdg { status = "okay"; }; + +&aes { + status = "okay"; +}; diff --git a/boards/st/nucleo_l4a6zg/nucleo_l4a6zg.yaml b/boards/st/nucleo_l4a6zg/nucleo_l4a6zg.yaml index bdc87910a4f..09493d2b217 100644 --- a/boards/st/nucleo_l4a6zg/nucleo_l4a6zg.yaml +++ b/boards/st/nucleo_l4a6zg/nucleo_l4a6zg.yaml @@ -5,7 +5,7 @@ arch: arm toolchain: - zephyr - gnuarmemb -ram: 320 +ram: 256 flash: 1024 supported: - arduino_i2c diff --git a/boards/st/nucleo_l4r5zi/Kconfig.defconfig b/boards/st/nucleo_l4r5zi/Kconfig.defconfig index 31b375e87d2..57e21974c16 100644 --- a/boards/st/nucleo_l4r5zi/Kconfig.defconfig +++ b/boards/st/nucleo_l4r5zi/Kconfig.defconfig @@ -9,14 +9,4 @@ config SPI_STM32_INTERRUPT default y depends on SPI -if NETWORKING - -config USB_DEVICE_STACK - default y - -config USB_DEVICE_NETWORK_EEM - default y - -endif # NETWORKING - endif # BOARD_NUCLEO_L4R5ZI diff --git a/boards/st/nucleo_l4r5zi/doc/index.rst b/boards/st/nucleo_l4r5zi/doc/index.rst index 1a1302aa3e2..7ea8f859806 100644 --- a/boards/st/nucleo_l4r5zi/doc/index.rst +++ b/boards/st/nucleo_l4r5zi/doc/index.rst @@ -1,7 +1,4 @@ -.. _nucleo_l4r5zi_board: - -ST Nucleo L4R5ZI -################ +.. zephyr:board:: nucleo_l4r5zi Overview ******** @@ -26,10 +23,6 @@ some highlights of the Nucleo L4R5ZI board: - Three User LEDs: LD1 (Green), LD2 (Blue), LD3 (Red) - Two push-buttons: USER and RESET -.. image:: img/nucleo_l4r5zi.jpg - :align: center - :alt: Nucleo L4R5ZI - More information about the board can be found at the `Nucleo L4R5ZI website`_. Hardware diff --git a/boards/st/nucleo_l4r5zi/nucleo_l4r5zi.dts b/boards/st/nucleo_l4r5zi/nucleo_l4r5zi.dts index 690e4bea360..ad1586e4382 100644 --- a/boards/st/nucleo_l4r5zi/nucleo_l4r5zi.dts +++ b/boards/st/nucleo_l4r5zi/nucleo_l4r5zi.dts @@ -65,6 +65,7 @@ led2 = &red_led_0; sw0 = &user_button; pwm-led0 = &red_pwm_led; + die-temp0 = &die_temp; volt-sensor0 = &vref; volt-sensor1 = &vbat; }; @@ -206,11 +207,15 @@ zephyr_udc0: &usbotg_fs { &adc1 { pinctrl-0 = <&adc1_in1_pc0>; pinctrl-names = "default"; - st,adc-clock-source = ; + st,adc-clock-source = "SYNC"; st,adc-prescaler = <4>; status = "okay"; }; +&die_temp { + status = "okay"; +}; + &vref { status = "okay"; }; diff --git a/boards/st/nucleo_l4r5zi/nucleo_l4r5zi.yaml b/boards/st/nucleo_l4r5zi/nucleo_l4r5zi.yaml index 5be0e1f69be..5bfd9f26be6 100644 --- a/boards/st/nucleo_l4r5zi/nucleo_l4r5zi.yaml +++ b/boards/st/nucleo_l4r5zi/nucleo_l4r5zi.yaml @@ -19,6 +19,6 @@ supported: - counter - adc - rtc -ram: 640 +ram: 192 flash: 2048 vendor: st diff --git a/boards/st/nucleo_l552ze_q/Kconfig.defconfig b/boards/st/nucleo_l552ze_q/Kconfig.defconfig new file mode 100644 index 00000000000..901b4cf1ad6 --- /dev/null +++ b/boards/st/nucleo_l552ze_q/Kconfig.defconfig @@ -0,0 +1,20 @@ +# STM32L552ZE-Q Nucleo board configuration + +# Copyright (c) 2024 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NUCLEO_L552ZE_Q + +if BUILD_WITH_TFM + +# Not defining LIBC malloc arena has the effect of declaring all available RAM +# as available for malloc. +# This currently conflicts with TF-M MPU setting, resulting in a hard fault. +# Define a specific size to avoid this situation. + +config COMMON_LIBC_MALLOC_ARENA_SIZE + default 2048 + +endif # BUILD_WITH_TFM + +endif # BOARD_NUCLEO_L552ZE_Q diff --git a/boards/st/nucleo_l552ze_q/doc/nucleol552ze_q.rst b/boards/st/nucleo_l552ze_q/doc/nucleol552ze_q.rst index 0d5aa6e0fd8..9dab9c36a9a 100644 --- a/boards/st/nucleo_l552ze_q/doc/nucleol552ze_q.rst +++ b/boards/st/nucleo_l552ze_q/doc/nucleol552ze_q.rst @@ -1,7 +1,4 @@ -.. _nucleo_l552ze_q_board: - -ST Nucleo L552ZE Q -################## +.. zephyr:board:: nucleo_l552ze_q Overview ******** @@ -30,10 +27,6 @@ board: - External or internal SMPS to generate Vcore logic supply - USB OTG full speed or device only -.. image:: img/nucleo_l552ze_q.jpg - :align: center - :alt: Nucleo L552ZE Q - More information about the board can be found at the `Nucleo L552ZE Q website`_. Hardware diff --git a/boards/st/nucleo_l552ze_q/nucleo_l552ze_q-common.dtsi b/boards/st/nucleo_l552ze_q/nucleo_l552ze_q-common.dtsi index 1e862347188..e0faedcc8e7 100644 --- a/boards/st/nucleo_l552ze_q/nucleo_l552ze_q-common.dtsi +++ b/boards/st/nucleo_l552ze_q/nucleo_l552ze_q-common.dtsi @@ -82,7 +82,7 @@ &adc1 { pinctrl-0 = <&adc1_in1_pc0>; pinctrl-names = "default"; - st,adc-clock-source = ; + st,adc-clock-source = "SYNC"; st,adc-prescaler = <4>; status = "okay"; }; diff --git a/boards/st/nucleo_u031r8/board.cmake b/boards/st/nucleo_u031r8/board.cmake index 7028d124f20..fbd5f1ed8e7 100644 --- a/boards/st/nucleo_u031r8/board.cmake +++ b/boards/st/nucleo_u031r8/board.cmake @@ -1,9 +1,11 @@ +# keep first board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") board_runner_args(pyocd "--target=stm32u031r8tx") board_runner_args(jlink "--device=STM32U031R8" "--reset-after-load") +# keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_u031r8/doc/index.rst b/boards/st/nucleo_u031r8/doc/index.rst index 490012ddc81..6126586000f 100644 --- a/boards/st/nucleo_u031r8/doc/index.rst +++ b/boards/st/nucleo_u031r8/doc/index.rst @@ -1,7 +1,4 @@ -.. _nucleo_u031r8_board: - -ST Nucleo U031R8 -################ +.. zephyr:board:: nucleo_u031r8 Overview ******** @@ -29,6 +26,8 @@ board: - Two push-buttons: USER and RESET - USB Type-C |reg| connector for the ST-LINK +More information about the board can be found at the `NUCLEO_U031R8 website`_. + Hardware ******** @@ -140,10 +139,15 @@ The Zephyr _nucleo_u031r8_ board configuration supports the following hardware f +-----------+------------+-------------------------------------+ | NVIC | on-chip | nested vector interrupt controller | +-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ | DAC | on-chip | DAC Controller | +-----------+------------+-------------------------------------+ | I2C | on-chip | i2c | +-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ + Other hardware features are not yet supported on this Zephyr port. @@ -193,15 +197,19 @@ This probe allows to flash the board using various tools. Flashing ======== -Board is configured to be flashed using west STM32CubeProgrammer runner. -Installation of `STM32CubeProgrammer`_ is then required to flash the board. +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. + +Alternatively, JLink or pyOCD can also be used to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console -Alternatively, pyocd or jlink via an external probe can also be used to flash -and debug the board if west is told to use it as runner, which can be done by -passing either or ``-r pyocd``, or ``-r jlink``. + $ west flash --runner pyocd + $ west flash --runner jlink -For pyocd additional target information needs to be installed. -This can be done by executing the following commands. +For pyOCD, additional target information needs to be installed +by executing the following pyOCD commands: .. code-block:: console diff --git a/boards/st/nucleo_u031r8/nucleo_u031r8.dts b/boards/st/nucleo_u031r8/nucleo_u031r8.dts index e6875786e03..d82570718dd 100644 --- a/boards/st/nucleo_u031r8/nucleo_u031r8.dts +++ b/boards/st/nucleo_u031r8/nucleo_u031r8.dts @@ -101,3 +101,34 @@ status = "okay"; clock-frequency = ; }; + +&adc1 { + pinctrl-0 = <&adc1_in0_pc0 &adc1_in1_pc1>; + pinctrl-names = "default"; + st,adc-clock-source = "SYNC"; + st,adc-prescaler = <4>; + status = "okay"; + vref-mv = <3300>; +}; + +&timers1 { + st,prescaler = <10000>; + status = "okay"; + + pwm1: pwm { + status = "okay"; + pinctrl-0 = <&tim1_ch1_pa8>; + pinctrl-names = "default"; + }; +}; + +&timers2 { + st,prescaler = <10000>; + status = "okay"; + + pwm2: pwm { + pinctrl-0 = <&tim2_ch1_pa5>; + pinctrl-names = "default"; + status = "okay"; + }; +}; diff --git a/boards/st/nucleo_u031r8/nucleo_u031r8.yaml b/boards/st/nucleo_u031r8/nucleo_u031r8.yaml index 7995c39a1c6..54870420bb3 100644 --- a/boards/st/nucleo_u031r8/nucleo_u031r8.yaml +++ b/boards/st/nucleo_u031r8/nucleo_u031r8.yaml @@ -6,9 +6,11 @@ toolchain: - zephyr supported: - arduino_gpio + - adc - dac - gpio - i2c + - pwm - usart ram: 12 flash: 64 diff --git a/boards/st/nucleo_u083rc/board.cmake b/boards/st/nucleo_u083rc/board.cmake index d969b9dff1a..2195ba62540 100644 --- a/boards/st/nucleo_u083rc/board.cmake +++ b/boards/st/nucleo_u083rc/board.cmake @@ -1,9 +1,11 @@ +# keep first board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") board_runner_args(pyocd "--target=stm32u083rctx") board_runner_args(jlink "--device=STM32U083RC" "--reset-after-load") +# keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_u083rc/doc/index.rst b/boards/st/nucleo_u083rc/doc/index.rst index e8e7f43e092..7cd2f5db578 100644 --- a/boards/st/nucleo_u083rc/doc/index.rst +++ b/boards/st/nucleo_u083rc/doc/index.rst @@ -1,7 +1,4 @@ -.. _nucleo_u083rc_board: - -ST Nucleo U083RC -################ +.. zephyr:board:: nucleo_u083rc Overview ******** @@ -29,6 +26,8 @@ board: - Two push-buttons: USER and RESET - USB Type-C |reg| connector for the ST-LINK +More information about the board can be found at the `NUCLEO_U083RC website`_. + Hardware ******** @@ -50,6 +49,8 @@ They operate at a frequency of up to 56 MHz. - 4 µA wake-up from Stop mode - 52 µA/MHz Run mode - Brownout reset + - SPI (3) + - DMA Controller (2) - Core: @@ -99,6 +100,7 @@ They operate at a frequency of up to 56 MHz. - Candidate for Arm |reg| PSA level 1 and SESIP level 3 certifications - 5 passive anti-tamper pins - 96-bit unique ID + - True Random Number Generator (RNG) NIST SP800-90B compliant - Up to 10 timers, 2 watchdogs and RTC: @@ -107,6 +109,8 @@ They operate at a frequency of up to 56 MHz. 2x watchdogs, SysTick timer - RTC with hardware calendar, alarms and calibration +- 3 low-power 16-bit timers (available in Stop mode). + - Up to 20 communication peripherals: - 1 USB 2.0 full-speed crystal-less solution with LPM and BCD @@ -146,10 +150,30 @@ The Zephyr nucleo_u083rc board configuration supports the following hardware fea | UART | on-chip | serial port-polling; | | | | serial port-interrupt | +-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ | DAC | on-chip | DAC Controller | +-----------+------------+-------------------------------------+ | I2C | on-chip | i2c | +-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| RTC | on-chip | Real Time Clock | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| USB | on-chip | USB full-speed host/device bus | ++-----------+------------+-------------------------------------+ +| DMA | on-chip | Direct Memory Access Controller | ++-----------+------------+-------------------------------------+ +| RNG | on-chip | True Random number generator | ++-----------+------------+-------------------------------------+ +| AES | on-chip | crypto | ++-----------+------------+-------------------------------------+ +| LPTIM | on-chip | Low Power Timer | ++-----------+------------+-------------------------------------+ Other hardware features are not yet supported on this Zephyr port. diff --git a/boards/st/nucleo_u083rc/nucleo_u083rc.dts b/boards/st/nucleo_u083rc/nucleo_u083rc.dts index 5d3bfe02f85..cfe5e149562 100644 --- a/boards/st/nucleo_u083rc/nucleo_u083rc.dts +++ b/boards/st/nucleo_u083rc/nucleo_u083rc.dts @@ -44,6 +44,7 @@ aliases { led0 = &green_led_1; sw0 = &user_button; + watchdog0 = &iwdg; }; }; @@ -61,10 +62,26 @@ status = "okay"; }; +&iwdg { + status = "okay"; +}; + &clk_hsi { status = "okay"; }; +&clk_hsi48 { + status = "okay"; +}; + +&clk_lse { + status = "okay"; +}; + +&clk_lsi { + status = "okay"; +}; + &pll { div-m = <1>; mul-n = <6>; @@ -95,9 +112,80 @@ clock-frequency = ; }; -&i2c2 { - pinctrl-0 = <&i2c2_scl_pa7 &i2c2_sda_pa6>; +&adc1 { + pinctrl-0 = <&adc1_in0_pc0 &adc1_in1_pc1>; pinctrl-names = "default"; + st,adc-clock-source = "ASYNC"; + clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00100000>, + <&rcc STM32_SRC_HSI ADC_SEL(2)>; + st,adc-prescaler = <4>; + status = "okay"; + vref-mv = <3300>; +}; + +&timers1 { + st,prescaler = <10000>; + status = "okay"; + + pwm1: pwm { + status = "okay"; + pinctrl-0 = <&tim1_ch1_pa8>; + pinctrl-names = "default"; + }; +}; + +&timers2 { + st,prescaler = <10000>; + status = "okay"; + + pwm2: pwm { + pinctrl-0 = <&tim2_ch1_pa5>; + pinctrl-names = "default"; + status = "okay"; + }; +}; + +stm32_lp_tick_source: &lptim1 { + clocks = <&rcc STM32_CLOCK(APB1, 31U)>, + <&rcc STM32_SRC_LSI LPTIM1_SEL(1)>; + status = "okay"; +}; + +&spi1{ + pinctrl-0 = <&spi1_sck_pa5 &spi1_miso_pa6 &spi1_mosi_pa7>; + cs-gpios = <&gpioa 4 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + pinctrl-names = "default"; + status = "okay"; +}; + +&dma1 { + status = "okay"; +}; + +&dmamux1 { + status = "okay"; +}; + +&rng { + clocks = <&rcc STM32_CLOCK(AHB1, 18U)>, + <&rcc STM32_SRC_HSI48 CLK48_SEL(1)>; + status = "okay"; +}; + +&aes { + status = "okay"; +}; + +zephyr_udc0: &usb { + clocks = <&rcc STM32_CLOCK(APB1, 13U)>, + <&rcc STM32_SRC_HSI48 CLK48_SEL(1)>; + pinctrl-0 = <&usb_dm_pa11 &usb_dp_pa12>; + pinctrl-names = "default"; + status = "okay"; +}; + +&rtc { + clocks = <&rcc STM32_CLOCK(APB1, 10U)>, + <&rcc STM32_SRC_LSE RTC_SEL(1)>; status = "okay"; - clock-frequency = ; }; diff --git a/boards/st/nucleo_u083rc/nucleo_u083rc.yaml b/boards/st/nucleo_u083rc/nucleo_u083rc.yaml index 1dc624d55c1..833c40f2e86 100644 --- a/boards/st/nucleo_u083rc/nucleo_u083rc.yaml +++ b/boards/st/nucleo_u083rc/nucleo_u083rc.yaml @@ -7,10 +7,19 @@ toolchain: - gnuarmemb - xtools supported: + - adc + - aes - arduino_gpio - dac + - dma - gpio - i2c + - lptim + - pwm + - rng + - rtc + - spi - usart + - usb ram: 40 flash: 256 diff --git a/boards/st/nucleo_u575zi_q/doc/index.rst b/boards/st/nucleo_u575zi_q/doc/index.rst index 080bd074c4f..29dc145ce29 100644 --- a/boards/st/nucleo_u575zi_q/doc/index.rst +++ b/boards/st/nucleo_u575zi_q/doc/index.rst @@ -1,7 +1,4 @@ -.. _nucleo_u575zi_q_board: - -ST Nucleo U575ZI Q -################## +.. zephyr:board:: nucleo_u575zi_q Overview ******** diff --git a/boards/st/nucleo_u575zi_q/nucleo_u575zi_q-common.dtsi b/boards/st/nucleo_u575zi_q/nucleo_u575zi_q-common.dtsi index 0d66260badd..171aa412658 100644 --- a/boards/st/nucleo_u575zi_q/nucleo_u575zi_q-common.dtsi +++ b/boards/st/nucleo_u575zi_q/nucleo_u575zi_q-common.dtsi @@ -129,7 +129,7 @@ &adc1 { pinctrl-0 = <&adc1_in1_pc0>; pinctrl-names = "default"; - st,adc-clock-source = ; + st,adc-clock-source = "ASYNC"; st,adc-prescaler = <4>; status = "okay"; }; @@ -137,7 +137,7 @@ &adc4 { pinctrl-0 = <&adc4_in18_pb0>; pinctrl-names = "default"; - st,adc-clock-source = ; + st,adc-clock-source = "ASYNC"; st,adc-prescaler = <4>; status = "okay"; }; diff --git a/boards/st/nucleo_u5a5zj_q/doc/index.rst b/boards/st/nucleo_u5a5zj_q/doc/index.rst index d3f90a178d4..794a2351d82 100644 --- a/boards/st/nucleo_u5a5zj_q/doc/index.rst +++ b/boards/st/nucleo_u5a5zj_q/doc/index.rst @@ -1,7 +1,4 @@ -.. _nucleo_u5a5zj_q_board: - -ST Nucleo U5A5ZJ Q -################## +.. zephyr:board:: nucleo_u5a5zj_q Overview ******** @@ -207,6 +204,8 @@ The Zephyr nucleo_u5a5zj_q board configuration supports the following hardware f +-----------+------------+-------------------------------------+ | RTC | on-chip | rtc | +-----------+------------+-------------------------------------+ +| USB | on-chip | USB 2.0 HS | ++-----------+------------+-------------------------------------+ Other hardware features are not yet supported on this Zephyr port. @@ -239,7 +238,7 @@ Default Zephyr Peripheral Mapping: - LD3 : PG2 - LPUART_1_TX : PG7 - LPUART_1_RX : PG8 -- SPI_1_NSS : PA4 +- SPI_1 nCS (GPIO) : PD14 - SPI_1_SCK : PA5 - SPI_1_MISO : PA6 - SPI_1_MOSI : PA7 @@ -248,13 +247,15 @@ Default Zephyr Peripheral Mapping: - UART_2_TX : PD5 - UART_2_RX : PD6 - USER_PB : PC13 +- USB_DM : PA11 +- USB_DP : PA12 System Clock ------------ Nucleo U5A5ZJ Q System Clock could be driven by internal or external oscillator, as well as main PLL clock. By default System clock is driven by PLL clock at -160MHz, driven by 4MHz medium speed internal oscillator. +160MHz, driven by the 16MHz high speed oscillator. Serial Port ----------- @@ -262,13 +263,18 @@ Serial Port Nucleo U5A5ZJ Q board has 6 U(S)ARTs. The Zephyr console output is assigned to USART1. Default settings are 115200 8N1. - Backup SRAM ----------- In order to test backup SRAM you may want to disconnect VBAT from VDD. You can do it by removing ``SB50`` jumper on the back side of the board. +Using USB +--------- + +USB 2.0 high speed (HS) operation requires the HSE clock source to be populated +and enabled. The Nucleo U5A5ZJ-Q includes the 16MHz oscillator and required +jumper settings. Programming and Debugging ************************* diff --git a/boards/st/nucleo_u5a5zj_q/nucleo_u5a5zj_q-common.dtsi b/boards/st/nucleo_u5a5zj_q/nucleo_u5a5zj_q-common.dtsi index a08d7b47ce2..45d7c817ec6 100644 --- a/boards/st/nucleo_u5a5zj_q/nucleo_u5a5zj_q-common.dtsi +++ b/boards/st/nucleo_u5a5zj_q/nucleo_u5a5zj_q-common.dtsi @@ -55,22 +55,23 @@ status = "okay"; }; -&clk_lse { +/* This board has a 16MHz crystal attached */ +&clk_hse { + clock-frequency = ; status = "okay"; }; -&clk_msis { +&clk_lse { status = "okay"; - msi-range = <4>; - msi-pll-mode; }; &pll1 { - div-m = <1>; - mul-n = <80>; - div-q = <2>; - div-r = <2>; - clocks = <&clk_msis>; + /* HSE 16MHz source, outputting 160MHz to sysclk and apbclk */ + div-m = <4>; /* input divisor */ + mul-n = <80>; /* VCO multiplication factor */ + div-q = <2>; /* system clock divisor */ + div-r = <2>; /* peripheral clock divisor */ + clocks = <&clk_hse>; status = "okay"; }; @@ -112,9 +113,9 @@ }; &spi1 { - pinctrl-0 = <&spi1_nss_pe12 &spi1_sck_pa5 - &spi1_miso_pa6 &spi1_mosi_pa7>; + pinctrl-0 = <&spi1_sck_pa5 &spi1_miso_pa6 &spi1_mosi_pa7>; pinctrl-names = "default"; + cs-gpios = <&gpiod 14 GPIO_ACTIVE_LOW>; status = "okay"; }; @@ -127,7 +128,7 @@ &adc1 { pinctrl-0 = <&adc1_in1_pc0>; pinctrl-names = "default"; - st,adc-clock-source = ; + st,adc-clock-source = "ASYNC"; st,adc-prescaler = <4>; status = "okay"; }; @@ -135,7 +136,7 @@ &adc4 { pinctrl-0 = <&adc4_in18_pb0>; pinctrl-names = "default"; - st,adc-clock-source = ; + st,adc-clock-source = "ASYNC"; st,adc-prescaler = <4>; status = "okay"; }; diff --git a/boards/st/nucleo_u5a5zj_q/nucleo_u5a5zj_q.dts b/boards/st/nucleo_u5a5zj_q/nucleo_u5a5zj_q.dts index a9907afe614..e34b10024ab 100644 --- a/boards/st/nucleo_u5a5zj_q/nucleo_u5a5zj_q.dts +++ b/boards/st/nucleo_u5a5zj_q/nucleo_u5a5zj_q.dts @@ -74,3 +74,9 @@ &gpdma1 { status = "okay"; }; + +zephyr_udc0: &usbotg_hs { + pinctrl-0 = <&usb_otg_hs_dm_pa11 &usb_otg_hs_dp_pa12>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/boards/st/nucleo_u5a5zj_q/nucleo_u5a5zj_q.yaml b/boards/st/nucleo_u5a5zj_q/nucleo_u5a5zj_q.yaml index cd937080414..57c0712ffed 100644 --- a/boards/st/nucleo_u5a5zj_q/nucleo_u5a5zj_q.yaml +++ b/boards/st/nucleo_u5a5zj_q/nucleo_u5a5zj_q.yaml @@ -21,5 +21,6 @@ supported: - backup_sram - dma - rtc + - usb_device ram: 2450 flash: 4096 diff --git a/boards/st/nucleo_wb05kz/arduino_r3_connector.dtsi b/boards/st/nucleo_wb05kz/arduino_r3_connector.dtsi index 75fb046f29f..7b61215ab79 100644 --- a/boards/st/nucleo_wb05kz/arduino_r3_connector.dtsi +++ b/boards/st/nucleo_wb05kz/arduino_r3_connector.dtsi @@ -25,4 +25,6 @@ }; }; +arduino_i2c: &i2c1 {}; arduino_serial: &usart1 {}; +arduino_spi: &spi3 {}; diff --git a/boards/st/nucleo_wb05kz/board.cmake b/boards/st/nucleo_wb05kz/board.cmake index 15bdb8e444d..a6b62f37ce2 100644 --- a/boards/st/nucleo_wb05kz/board.cmake +++ b/boards/st/nucleo_wb05kz/board.cmake @@ -1,5 +1,7 @@ # SPDX-License-Identifier: Apache-2.0 +# keep first board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=sw") +# keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/st/nucleo_wb05kz/doc/index.rst b/boards/st/nucleo_wb05kz/doc/index.rst index 7d242549ffe..0c004e59952 100644 --- a/boards/st/nucleo_wb05kz/doc/index.rst +++ b/boards/st/nucleo_wb05kz/doc/index.rst @@ -1,7 +1,4 @@ -.. _nucleo_wb05kz_board: - -ST Nucleo WB05KZ -################ +.. zephyr:board:: nucleo_wb05kz Overview ******** @@ -11,10 +8,6 @@ board featuring an ARM Cortex |reg|-M0+ based STM32WB05KZV MCU, embedding a powerful and ultra-low-power radio compliant with the Bluetooth® Low Energy SIG specification v5.4. -.. image:: img/nucleo_wb05kz.webp - :align: center - :alt: Nucleo WB05KZ - More information about the board can be found on the `Nucleo WB05KZ webpage`_. Hardware @@ -53,6 +46,14 @@ The Zephyr ``nucleo_wb05kz`` board target supports the following hardware featur +-----------+------------+-------------------------------------+ | FLASH | on-chip | internal flash memory | +-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| RADIO | on-chip | Bluetooth Low Energy | ++-----------+------------+-------------------------------------+ Other hardware features are not yet supported on this Zephyr port. @@ -60,6 +61,17 @@ Other hardware features are not yet supported on this Zephyr port. The default configuration can be found in the defconfig file: :zephyr_file:`boards/st/nucleo_wb09ke/nucleo_wb09ke_defconfig` +Bluetooh support +---------------- + +BLE support is enabled; however, to build a Zephyr sample using this board, +you first need to fetch the Bluetooth controller library into Zephyr as a binary BLOB. + +To fetch binary BLOBs: + +.. code-block:: console + + west blobs fetch hal_stm32 Connections and IOs =================== diff --git a/boards/st/nucleo_wb05kz/nucleo_wb05kz.dts b/boards/st/nucleo_wb05kz/nucleo_wb05kz.dts index f61f32e06d0..88f37c00186 100644 --- a/boards/st/nucleo_wb05kz/nucleo_wb05kz.dts +++ b/boards/st/nucleo_wb05kz/nucleo_wb05kz.dts @@ -23,6 +23,7 @@ zephyr,shell-uart = &usart1; zephyr,sram = &sram0; zephyr,flash = &flash0; + zephyr,bt-c2h-uart = &usart1; }; leds: leds { @@ -95,9 +96,41 @@ slow-clock = <&clk_lse>; }; +&bt_hci_wb0 { + status = "okay"; +}; + &usart1 { pinctrl-0 = <&usart1_tx_pa1 &usart1_rx_pb0>; pinctrl-names = "default"; current-speed = <115200>; status = "okay"; }; + +&i2c1 { + pinctrl-0 = <&i2c1_scl_pb6 &i2c1_sda_pb7>; + pinctrl-names = "default"; + status = "okay"; +}; + +&spi3 { + pinctrl-0 = <&spi3_nss_pa9 &spi3_sck_pb3 &spi3_miso_pa8 &spi3_mosi_pa11>; + pinctrl-names = "default"; + status = "okay"; + /* Select 64MHz clock for SPI3 */ + clocks = <&rcc STM32_CLOCK_BUS_APB1 (1 << 14)>, + <&rcc STM32_SRC_SYSCLK SPI3_I2S3_SEL(3)>; +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + /* Set 8KB of storage at the end of 192KB flash */ + storage_partition: partition@2e000 { + label = "storage"; + reg = <0x0002e000 DT_SIZE_K(8)>; + }; + }; +}; diff --git a/boards/st/nucleo_wb05kz/nucleo_wb05kz.yaml b/boards/st/nucleo_wb05kz/nucleo_wb05kz.yaml index ce75ada4a46..cf931e9bd37 100644 --- a/boards/st/nucleo_wb05kz/nucleo_wb05kz.yaml +++ b/boards/st/nucleo_wb05kz/nucleo_wb05kz.yaml @@ -9,6 +9,12 @@ toolchain: ram: 24 flash: 192 supported: + - adc + - arduino_i2c + - arduino_spi + - dma - gpio - - arduino_gpio + - i2c + - spi + - bluetooth vendor: st diff --git a/boards/st/nucleo_wb09ke/arduino_r3_connector.dtsi b/boards/st/nucleo_wb09ke/arduino_r3_connector.dtsi index 75fb046f29f..7b61215ab79 100644 --- a/boards/st/nucleo_wb09ke/arduino_r3_connector.dtsi +++ b/boards/st/nucleo_wb09ke/arduino_r3_connector.dtsi @@ -25,4 +25,6 @@ }; }; +arduino_i2c: &i2c1 {}; arduino_serial: &usart1 {}; +arduino_spi: &spi3 {}; diff --git a/boards/st/nucleo_wb09ke/board.cmake b/boards/st/nucleo_wb09ke/board.cmake index 15bdb8e444d..a6b62f37ce2 100644 --- a/boards/st/nucleo_wb09ke/board.cmake +++ b/boards/st/nucleo_wb09ke/board.cmake @@ -1,5 +1,7 @@ # SPDX-License-Identifier: Apache-2.0 +# keep first board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=sw") +# keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/st/nucleo_wb09ke/doc/index.rst b/boards/st/nucleo_wb09ke/doc/index.rst index 9e4ce9eb728..bab52ff1ba7 100644 --- a/boards/st/nucleo_wb09ke/doc/index.rst +++ b/boards/st/nucleo_wb09ke/doc/index.rst @@ -1,7 +1,4 @@ -.. _nucleo_wb09ke_board: - -ST Nucleo WB09KE -################ +.. zephyr:board:: nucleo_wb09ke Overview ******** @@ -11,10 +8,6 @@ board featuring an ARM Cortex |reg|-M0+ based STM32WB09KEV MCU, embedding a powerful and ultra-low-power radio compliant with the Bluetooth® Low Energy SIG specification v5.4. -.. image:: img/nucleo_wb09ke.webp - :align: center - :alt: Nucleo WB09KE - More information about the board can be found on the `Nucleo WB09KE webpage`_. Hardware @@ -53,6 +46,14 @@ The Zephyr ``nucleo_wb09ke`` board target supports the following hardware featur +-----------+------------+-------------------------------------+ | FLASH | on-chip | internal flash memory | +-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| RADIO | on-chip | Bluetooth Low Energy | ++-----------+------------+-------------------------------------+ Other hardware features are not yet supported on this Zephyr port. @@ -60,6 +61,17 @@ Other hardware features are not yet supported on this Zephyr port. The default configuration can be found in the defconfig file: :zephyr_file:`boards/st/nucleo_wb09ke/nucleo_wb09ke_defconfig` +Bluetooh support +---------------- + +BLE support is enabled; however, to build a Zephyr sample using this board, +you first need to fetch the Bluetooth controller library into Zephyr as a binary BLOB. + +To fetch binary BLOBs: + +.. code-block:: console + + west blobs fetch hal_stm32 Connections and IOs =================== diff --git a/boards/st/nucleo_wb09ke/nucleo_wb09ke.dts b/boards/st/nucleo_wb09ke/nucleo_wb09ke.dts index 733e6c0f717..1b8826ed884 100644 --- a/boards/st/nucleo_wb09ke/nucleo_wb09ke.dts +++ b/boards/st/nucleo_wb09ke/nucleo_wb09ke.dts @@ -23,6 +23,7 @@ zephyr,shell-uart = &usart1; zephyr,sram = &sram0; zephyr,flash = &flash0; + zephyr,bt-c2h-uart = &usart1; }; leds: leds { @@ -95,9 +96,41 @@ slow-clock = <&clk_lse>; }; +&bt_hci_wb0 { + status = "okay"; +}; + &usart1 { pinctrl-0 = <&usart1_tx_pa1 &usart1_rx_pb0>; pinctrl-names = "default"; current-speed = <115200>; status = "okay"; }; + +&i2c1 { + pinctrl-0 = <&i2c1_scl_pb6 &i2c1_sda_pb7>; + pinctrl-names = "default"; + status = "okay"; +}; + +&spi3 { + pinctrl-0 = <&spi3_nss_pa9 &spi3_sck_pb3 &spi3_miso_pa8 &spi3_mosi_pa11>; + pinctrl-names = "default"; + status = "okay"; + /* Select 64MHz clock for SPI3 */ + clocks = <&rcc STM32_CLOCK_BUS_APB1 (1 << 14)>, + <&rcc STM32_SRC_SYSCLK SPI3_I2S3_SEL(3)>; +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + /* Set 32KB of storage at the end of 512KB flash */ + storage_partition: partition@78000 { + label = "storage"; + reg = <0x00078000 DT_SIZE_K(32)>; + }; + }; +}; diff --git a/boards/st/nucleo_wb09ke/nucleo_wb09ke.yaml b/boards/st/nucleo_wb09ke/nucleo_wb09ke.yaml index 908b24ea6da..20c4a33cfec 100644 --- a/boards/st/nucleo_wb09ke/nucleo_wb09ke.yaml +++ b/boards/st/nucleo_wb09ke/nucleo_wb09ke.yaml @@ -9,6 +9,12 @@ toolchain: ram: 64 flash: 512 supported: + - adc + - arduino_i2c + - arduino_spi + - dma - gpio - - arduino_gpio + - i2c + - spi + - bluetooth vendor: st diff --git a/boards/st/nucleo_wb55rg/doc/nucleo_wb55rg.rst b/boards/st/nucleo_wb55rg/doc/nucleo_wb55rg.rst index fb1b76e76ca..0aa7928ca2a 100644 --- a/boards/st/nucleo_wb55rg/doc/nucleo_wb55rg.rst +++ b/boards/st/nucleo_wb55rg/doc/nucleo_wb55rg.rst @@ -1,7 +1,4 @@ -.. _nucleo_wb55rg_board: - -ST Nucleo WB55RG -################ +.. zephyr:board:: nucleo_wb55rg Overview ******** @@ -29,10 +26,6 @@ Low Energy (BLE) SIG specification v5.0 and with IEEE 802.15.4-2011. - On-board ST-LINK/V2-1 debugger/programmer with USB re- enumeration capability: mass storage, virtual COM port and debug port -.. image:: img/nucleowb55rg.jpg - :align: center - :alt: Nucleo WB55RG - More information about the board can be found at the `Nucleo WB55RG website`_. Hardware diff --git a/boards/st/nucleo_wb55rg/nucleo_wb55rg.dts b/boards/st/nucleo_wb55rg/nucleo_wb55rg.dts index f1a0d055aa8..d58d2ebde26 100644 --- a/boards/st/nucleo_wb55rg/nucleo_wb55rg.dts +++ b/boards/st/nucleo_wb55rg/nucleo_wb55rg.dts @@ -181,7 +181,7 @@ &adc1 { pinctrl-0 = <&adc1_in3_pc2 &adc1_in5_pa0>; pinctrl-names = "default"; - st,adc-clock-source = ; + st,adc-clock-source = "SYNC"; st,adc-prescaler = <4>; status = "okay"; }; diff --git a/boards/st/nucleo_wba52cg/doc/nucleo_wba52cg.rst b/boards/st/nucleo_wba52cg/doc/nucleo_wba52cg.rst index 7c3257aa6fa..c27dc4a56a5 100644 --- a/boards/st/nucleo_wba52cg/doc/nucleo_wba52cg.rst +++ b/boards/st/nucleo_wba52cg/doc/nucleo_wba52cg.rst @@ -1,7 +1,4 @@ -.. _nucleo_wba52cg_board: - -ST Nucleo WBA52CG -################# +.. zephyr:board:: nucleo_wba52cg Overview ******** @@ -37,10 +34,6 @@ platform with a wide choice of specialized shields. - On-board STLINK-V3MODS debugger/programmer with USB re-enumeration capability: mass storage, Virtual COM port, and debug port -.. image:: img/nucleowba52cg.jpg - :align: center - :alt: Nucleo WBA52CG - More information about the board can be found at the `Nucleo WBA52CG website`_. Hardware diff --git a/boards/st/nucleo_wba52cg/nucleo_wba52cg.dts b/boards/st/nucleo_wba52cg/nucleo_wba52cg.dts index 0c08acc0bfe..08b81dba0dc 100644 --- a/boards/st/nucleo_wba52cg/nucleo_wba52cg.dts +++ b/boards/st/nucleo_wba52cg/nucleo_wba52cg.dts @@ -125,7 +125,7 @@ &adc4 { pinctrl-0 = <&adc4_in8_pa1>; pinctrl-names = "default"; - st,adc-clock-source = ; + st,adc-clock-source = "ASYNC"; st,adc-prescaler = <4>; status = "okay"; }; diff --git a/boards/st/nucleo_wba55cg/doc/nucleo_wba55cg.rst b/boards/st/nucleo_wba55cg/doc/nucleo_wba55cg.rst index c1ec0751854..affcf8c4c49 100644 --- a/boards/st/nucleo_wba55cg/doc/nucleo_wba55cg.rst +++ b/boards/st/nucleo_wba55cg/doc/nucleo_wba55cg.rst @@ -1,7 +1,4 @@ -.. _nucleo_wba55cg_board: - -ST Nucleo WBA55CG -################# +.. zephyr:board:: nucleo_wba55cg Overview ******** @@ -37,10 +34,6 @@ platform with a wide choice of specialized shields. - On-board STLINK-V3MODS debugger/programmer with USB re-enumeration capability: mass storage, Virtual COM port, and debug port -.. image:: img/nucleowba55cg.jpg - :align: center - :alt: Nucleo WBA55CG - Hardware ******** diff --git a/boards/st/nucleo_wba55cg/nucleo_wba55cg.dts b/boards/st/nucleo_wba55cg/nucleo_wba55cg.dts index d6e1c1f7a5d..2070611b326 100644 --- a/boards/st/nucleo_wba55cg/nucleo_wba55cg.dts +++ b/boards/st/nucleo_wba55cg/nucleo_wba55cg.dts @@ -6,8 +6,7 @@ /dts-v1/; #include -/* Todo: Once available, use wba55 dedicated pinctrl.dtsi */ -#include +#include #include "arduino_r3_connector.dtsi" #include @@ -20,6 +19,7 @@ chosen { zephyr,bt-c2h-uart = &usart1; + zephyr,uart-pipe = &usart1; zephyr,console = &usart1; zephyr,shell-uart = &usart1; zephyr,sram = &sram0; @@ -147,7 +147,7 @@ &adc4 { pinctrl-0 = <&adc4_in8_pa1 &adc4_in9_pa0>; pinctrl-names = "default"; - st,adc-clock-source = ; + st,adc-clock-source = "ASYNC"; st,adc-prescaler = <4>; status = "okay"; }; diff --git a/boards/st/nucleo_wba55cg/support/openocd.cfg b/boards/st/nucleo_wba55cg/support/openocd.cfg index 247de974f39..1715e7d026e 100644 --- a/boards/st/nucleo_wba55cg/support/openocd.cfg +++ b/boards/st/nucleo_wba55cg/support/openocd.cfg @@ -22,5 +22,3 @@ set CLOCK_FREQ 8000 reset_config srst_only srst_nogate source [find target/stm32wbax.cfg] - -gdb_memory_map disable diff --git a/boards/st/nucleo_wl55jc/doc/nucleo_wl55jc.rst b/boards/st/nucleo_wl55jc/doc/nucleo_wl55jc.rst index 98ce41d5877..72f7147c5b6 100644 --- a/boards/st/nucleo_wl55jc/doc/nucleo_wl55jc.rst +++ b/boards/st/nucleo_wl55jc/doc/nucleo_wl55jc.rst @@ -1,7 +1,4 @@ -.. _nucleo_wl55jc_board: - -ST Nucleo WL55JC -################ +.. zephyr:board:: nucleo_wl55jc Overview ******** @@ -43,10 +40,6 @@ power consumption, and features. - Fully open hardware platform -.. image:: img/nucleo_wl55jc.jpg - :align: center - :alt: Nucleo WL55JC - More information about the board can be found at the `Nucleo WL55JC website`_. Hardware diff --git a/boards/st/nucleo_wl55jc/nucleo_wl55jc.dts b/boards/st/nucleo_wl55jc/nucleo_wl55jc.dts index 98fcc7057ae..1fa0c4d9fdb 100644 --- a/boards/st/nucleo_wl55jc/nucleo_wl55jc.dts +++ b/boards/st/nucleo_wl55jc/nucleo_wl55jc.dts @@ -149,7 +149,7 @@ stm32_lp_tick_source: &lptim1 { &adc1 { pinctrl-0 = <&adc_in5_pb1 &adc_in0_pb13>; pinctrl-names = "default"; - st,adc-clock-source = ; + st,adc-clock-source = "SYNC"; st,adc-prescaler = <4>; status = "okay"; }; diff --git a/boards/st/sensortile_box/Kconfig.defconfig b/boards/st/sensortile_box/Kconfig.defconfig index faa5dc0864c..24d16b199dd 100644 --- a/boards/st/sensortile_box/Kconfig.defconfig +++ b/boards/st/sensortile_box/Kconfig.defconfig @@ -7,12 +7,6 @@ if BOARD_SENSORTILE_BOX if BT -config SPI - default y - -config BT_SPI - default y - config BT_BLUENRG_ACI default y # Disable Flow control diff --git a/boards/st/sensortile_box/doc/index.rst b/boards/st/sensortile_box/doc/index.rst index d582d3f2ee1..861b2e559b9 100644 --- a/boards/st/sensortile_box/doc/index.rst +++ b/boards/st/sensortile_box/doc/index.rst @@ -1,7 +1,4 @@ -.. _sensortile_box: - -ST SensorTile.box -################# +.. zephyr:board:: sensortile_box Overview ******** @@ -13,10 +10,6 @@ The SensorTile.box board fits into a small plastic box with a long-life recharge battery, and communicates with a standard smartphone through its Bluetooth interface, providing data coming from the sensors. -.. image:: img/sensortile_box.jpg - :align: center - :alt: SensorTile.box - More information about the board can be found at the `SensorTile.box website`_. Hardware diff --git a/boards/st/sensortile_box_pro/Kconfig b/boards/st/sensortile_box_pro/Kconfig deleted file mode 100644 index d8dc05c44f6..00000000000 --- a/boards/st/sensortile_box_pro/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -# SENSORTILE_BOX_PRO board configuration - -# Copyright (c) 2024 STMicroelectronics -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_SENSORTILE_BOX_PRO - -config BOARD_SERIAL_BACKEND_CDC_ACM - bool "Use USB CDC as serial console backend" - default y - -endif # BOARD_SENSORTILE_BOX_PRO diff --git a/boards/st/sensortile_box_pro/Kconfig.defconfig b/boards/st/sensortile_box_pro/Kconfig.defconfig index fb701bd4265..a357839f6c4 100644 --- a/boards/st/sensortile_box_pro/Kconfig.defconfig +++ b/boards/st/sensortile_box_pro/Kconfig.defconfig @@ -7,12 +7,6 @@ if BOARD_SENSORTILE_BOX_PRO if BT -config SPI - default y - -config BT_SPI - default y - config BT_BLUENRG_ACI default y @@ -26,50 +20,6 @@ config SPI_STM32_INTERRUPT default y depends on SPI -if BOARD_SERIAL_BACKEND_CDC_ACM - -config USB_DEVICE_STACK - default y - -config USB_CDC_ACM - default SERIAL - -config USB_DEVICE_INITIALIZE_AT_BOOT - default y if CONSOLE - -config SHELL_BACKEND_SERIAL_CHECK_DTR - default SHELL - depends on UART_LINE_CTRL - -config UART_LINE_CTRL - default SHELL - -config USB_DEVICE_REMOTE_WAKEUP - default n - -config USB_DEVICE_VID - default 0x0483 - -config USB_DEVICE_PID - default 0x5740 - -config USB_DEVICE_PRODUCT - default "Zephyr CDC SensorTile.box PRO" - -if LOG - -# Logger cannot use itself to log -choice USB_CDC_ACM_LOG_LEVEL_CHOICE - default USB_CDC_ACM_LOG_LEVEL_OFF -endchoice - -endif # LOG - -endif # BOARD_SERIAL_BACKEND_CDC_ACM - -DT_CHOSEN_ZEPHYR_CONSOLE := zephyr,console - -config UART_CONSOLE - default y if $(dt_chosen_enabled,$(DT_CHOSEN_ZEPHYR_CONSOLE)) && CONSOLE +source "boards/common/usb/Kconfig.cdc_acm_serial.defconfig" endif # BOARD_SENSORTILE_BOX_PRO diff --git a/boards/st/sensortile_box_pro/doc/index.rst b/boards/st/sensortile_box_pro/doc/index.rst index eaad9150d70..528e6762a87 100644 --- a/boards/st/sensortile_box_pro/doc/index.rst +++ b/boards/st/sensortile_box_pro/doc/index.rst @@ -1,7 +1,4 @@ -.. _sensortile_box_pro_board: - -ST SensorTile.box PRO -##################### +.. zephyr:board:: sensortile_box_pro Overview ******** @@ -14,10 +11,6 @@ The SensorTile.box PRO board fits into a small plastic box with a long-life rech battery, and communicates with a standard smartphone through its Bluetooth interface, providing data coming from the sensors. -.. image:: img/sensortile_box_pro.jpg - :align: center - :alt: SensorTile.box PRO - More information about the board can be found at the `SensorTile.box PRO website`_. Supported Features @@ -41,6 +34,9 @@ sensors on board) Hardware ******** +The following is a summary of the main board features. More info can be find on `UM3133`_ +and the `schematic`_. + The STM32U585xx devices are an ultra-low-power microcontrollers family (STM32U5 Series) based on the high-performance Arm|reg| Cortex|reg|-M33 32-bit RISC core. They operate at a frequency of up to 160 MHz. @@ -212,29 +208,20 @@ The final application may use it to declare SensorTile.box PRO device as belongi certain standard or vendor class, e.g. a CDC, a mass storage or a composite device with both functions. +BlueNRG-LP chip +=============== + +The board is equipped with an STMicroelectronics `BlueNRG-LP`_ chip. Before running Zephyr Bluetooth samples +on SensorTile.box PRO, it is required to upgrade the BlueNRG chip with a Zephyr BLE stack compatible firmware. +The upgrade may be easily performed using the application provided in `SensorTile.box PRO BLE firmware upgrade package`_. +For more information about BLE binaries for SensorTile.box family, see `stsw-mkbox-bleco`_. + Console ======= There are two possible options for Zephyr console output: -- through USB as USB CDC/ACM class. This is the default case present in the board dts file - and is enabled by :kconfig:option:`CONFIG_BOARD_SERIAL_BACKEND_CDC_ACM`. - -.. code-block:: dts - :caption: boards/st/sensortile_box_pro/sensortile_box_pro.dts - - / { - chosen { - zephyr,console = &cdc_acm_uart0; - }; - }; - - &zephyr_udc0 { - cdc_acm_uart0: cdc_acm_uart0 { - compatible = "zephyr,cdc-acm-uart"; - }; - }; - +- through common CDC ACM UART backend configuration for all boards - through UART4 which is available on SWD connector (JP2). In this case a JTAG adapter can be used to connect SensorTile.box PRO and have both SWD and console lines available. @@ -333,6 +320,12 @@ References .. _SensorTile.box PRO website: https://www.st.com/en/evaluation-tools/steval-mkboxpro.html +.. _UM3133: + https://www.st.com/resource/en/user_manual/um3133-getting-started-with-sensortilebox-pro-multisensors-and-wireless-connectivity-development-kit-for-any-intelligent-iot-node-stmicroelectronics.pdf + +.. _schematic: + https://www.st.com/resource/en/schematic_pack/steval-mkboxpro-schematic.pdf + .. _STM32U585 on www.st.com: https://www.st.com/en/microcontrollers-microprocessors/stm32u575-585.html @@ -357,6 +350,15 @@ References .. _mp23db01hp datasheet: https://www.st.com/en/mems-and-sensors/mp23db01hp.html +.. _BlueNRG-LP: + https://www.st.com/en/wireless-connectivity/bluenrg-lp.html + +.. _SensorTile.box PRO BLE firmware upgrade package: + https://github.com/STMicroelectronics/stsw-mkbox-bleco/blob/master/ble_fw_upg_app/README.rst + +.. _stsw-mkbox-bleco: + https://www.st.com/en/embedded-software/stsw-mkbox-bleco.html + .. _AN2606: http://www.st.com/content/ccc/resource/technical/document/application_note/b9/9b/16/3a/12/1e/40/0c/CD00167594.pdf/files/CD00167594.pdf/jcr:content/translations/en.CD00167594.pdf diff --git a/boards/st/sensortile_box_pro/sensortile_box_pro.dts b/boards/st/sensortile_box_pro/sensortile_box_pro.dts index 7014fd86a7e..85f01ab2a08 100644 --- a/boards/st/sensortile_box_pro/sensortile_box_pro.dts +++ b/boards/st/sensortile_box_pro/sensortile_box_pro.dts @@ -14,9 +14,6 @@ compatible = "st,sensortile-box-pro"; chosen { - zephyr,console = &cdc_acm_uart0; - zephyr,shell-uart = &cdc_acm_uart0; - zephyr,bt-c2h-uart = &cdc_acm_uart0; zephyr,sram = &sram0; zephyr,flash = &flash0; zephyr,code-partition = &slot0_partition; @@ -269,16 +266,14 @@ zephyr_udc0: &usbotg_fs { pinctrl-0 = <&usb_otg_fs_dm_pa11 &usb_otg_fs_dp_pa12>; pinctrl-names = "default"; status = "okay"; - - cdc_acm_uart0: cdc_acm_uart0 { - compatible = "zephyr,cdc-acm-uart"; - }; }; +#include <../boards/common/usb/cdc_acm_serial.dtsi> + &adc1 { pinctrl-0 = <&adc1_in15_pb0>; pinctrl-names = "default"; - st,adc-clock-source = ; + st,adc-clock-source = "ASYNC"; st,adc-prescaler = <4>; status = "okay"; }; @@ -286,7 +281,7 @@ zephyr_udc0: &usbotg_fs { &adc4 { pinctrl-0 = <&adc4_in19_pb1>; pinctrl-names = "default"; - st,adc-clock-source = ; + st,adc-clock-source = "ASYNC"; st,adc-prescaler = <4>; status = "okay"; }; diff --git a/boards/st/st25dv_mb1283_disco/docs/img/st25dv_mb1283_disco.jpg b/boards/st/st25dv_mb1283_disco/doc/img/st25dv_mb1283_disco.jpg similarity index 100% rename from boards/st/st25dv_mb1283_disco/docs/img/st25dv_mb1283_disco.jpg rename to boards/st/st25dv_mb1283_disco/doc/img/st25dv_mb1283_disco.jpg diff --git a/boards/st/st25dv_mb1283_disco/doc/index.rst b/boards/st/st25dv_mb1283_disco/doc/index.rst new file mode 100644 index 00000000000..b1fe8fa35da --- /dev/null +++ b/boards/st/st25dv_mb1283_disco/doc/index.rst @@ -0,0 +1,135 @@ +.. zephyr:board:: st25dv_mb1283_disco + +Overview +******** + +The ST25DV04K device is a dynamic NFC/RFID tag IC with a dual interface. It embeds a +4 Kbits EEPROM memory. It can be operated from an I2C interface, or by a 13.56 MHz +RFID reader, or by a NFC phone. The ST25DV04K Class 5 antenna daughter card, included +in the kit, can be replaced by Class 1 or Class 6 antennas. + +The ST25DV-DISCOVERY is a demonstration kit to evaluate the features and capabilities +of the ST25DV series. +It is based on the NFC ST25DV04K device embedded on a daughter card using a Class 5 antenna +and a STM32 processor driving a mother board. + +.. note:: + The ST25DV itself is not implemented yet. + +Hardware +******** + +The ST25DV Discovery kit provides the following hardware components: + +- Main board: ST25DV_Discovery_Mboard: + + - STM32F405VGT6 LQFP100 32-bit microcontroller, with 1 Mbyte Flash memory, 192 + 4 Kbytes SRAM. + - LCD color screen (320 x 200 pixels) + - Touch screen driver + - Different color LEDs (power, user, ST link) + - User push button + - Joystick for menu selection + - Reset button + - On board ST link for microcontroller firmware upgrade and debug + - ST link mini USB + - User micro USB + - USB micro or mini connector for board powering + - Demonstration edition (optional add-on module) with Bluetooth Low Energy module, + Wi-Fi ® module and JTAG 20 pin connector + +It exists in two variants, MB1283 and MB1285. + +- Antenna daughter board: ST25DV_Discovery_ANT_C5: + + - 40 mm x 24 mm, 13.56 MHz inductive antenna etched on the PCB + - ST25DV04K Dynamic NFC / RFID tag + - I 2 C interface connector + - Energy harvesting output (VOUT) with a 10nF capacitance filtering circuit + - GPO configurable as RF WIP/BUSY output, to indicate that an RF operation is ongoing + +The antenna board can be removed, and its 14-pin 0.254mm header connector used as an eval kit header. + +Connections and IOs +=================== + +Default Zephyr Peripheral Mapping +--------------------------------- + +- UART_6 TX/RX : PC6/PC7 (ST-Link Virtual Port Com) +- UART_2 TX/RX : PA2/PA3 (Available on J6 connector) +- I2C1 SCL/SDA : PB6/PB7 (Touchscreen STMPE811, interrupt pin PB5) +- SPI2 SCK/MOSI/CS : PB13/PC3/PB12 (LCD display FRD24048TP, reset pin PC1, DC pin PC0) +- SPI1 SCK/MISO/MOSI/CS : PA5/PA6/PA7/PA4 (External ST25DV connector J6) +- GPIO : PE8/PE9/PE10/PE11/PE12 (Joystick) +- LD1 : PC13 (Orange led) +- LD2 : PC4 (Yellow led) +- GPIO : PE15/PE7 (Available on external ST25DV connector J6) +- GPIO : PE14 (Available on J5 connector) + +Serial Port +=========== + +The Zephyr console output and shell are assigned to UART6, which is connected to the +onboard ST-LINK/V2 Virtual COM port interface. +Default communication settings are 115200 8N1. + +Programming and Debugging +************************* + +Applications for the ``st25dv_mb1283_disco`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +If programming fails, press the reset button (black) and release it while "west flash" is running. + +Flashing +======== + +ST25DV Discovery kit includes an ST-LINK/V2 embedded debug tool interface. +This interface is supported by the openocd version included in the Zephyr SDK. + +Flashing an application to ST25DV Discovery +-------------------------------------------- + +First, connect the ST25DV Discovery kit to your host computer using +the USB port to prepare it for flashing. Then build and flash your application. + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: st25dv_mb1283_disco + :goals: build flash + +Run a serial host program to connect with your board: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +You should see the following message on the console: + +.. code-block:: console + + Hello World! st25dv_mb1283_disco + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: st25dv_mb1283_disco + :goals: debug + + +.. _ST25DV-DISCO website: + https://www.st.com/en/nfc/st25dv-i2c-series-dynamic-nfc-tags.html + +.. _ST25DV datasheet: + https://www.st.com/resource/en/datasheet/st25dv04k.pdf + +.. _STM32F40xxx reference manual: + https://www.st.com/resource/en/reference_manual/rm0090-stm32f405415-stm32f407417-stm32f427437-and-stm32f429439-advanced-armbased-32bit-mcus-stmicroelectronics.pdf diff --git a/boards/st/st25dv_mb1283_disco/docs/index.rst b/boards/st/st25dv_mb1283_disco/docs/index.rst deleted file mode 100644 index 1fef60ebf63..00000000000 --- a/boards/st/st25dv_mb1283_disco/docs/index.rst +++ /dev/null @@ -1,142 +0,0 @@ -.. _st25dv_mb1283_disco_board: - -ST ST25DV Discovery, MB1283 version -################################### - -Overview -******** - -The ST25DV04K device is a dynamic NFC/RFID tag IC with a dual interface. It embeds a -4 Kbits EEPROM memory. It can be operated from an I2C interface, or by a 13.56 MHz -RFID reader, or by a NFC phone. The ST25DV04K Class 5 antenna daughter card, included -in the kit, can be replaced by Class 1 or Class 6 antennas. - -The ST25DV-DISCOVERY is a demonstration kit to evaluate the features and capabilities -of the ST25DV series. -It is based on the NFC ST25DV04K device embedded on a daughter card using a Class 5 antenna -and a STM32 processor driving a mother board. - -.. image:: img/st25dv_mb1283_disco.jpg - :align: center - :alt: ST25DV_MB1283_DISCO - -.. note:: - The ST25DV itself is not implemented yet. - -Hardware -******** - -The ST25DV Discovery kit provides the following hardware components: - -- Main board: ST25DV_Discovery_Mboard: - - - STM32F405VGT6 LQFP100 32-bit microcontroller, with 1 Mbyte Flash memory, 192 + 4 Kbytes SRAM. - - LCD color screen (320 x 200 pixels) - - Touch screen driver - - Different color LEDs (power, user, ST link) - - User push button - - Joystick for menu selection - - Reset button - - On board ST link for microcontroller firmware upgrade and debug - - ST link mini USB - - User micro USB - - USB micro or mini connector for board powering - - Demonstration edition (optional add-on module) with Bluetooth Low Energy module, - Wi-Fi ® module and JTAG 20 pin connector - -It exists in two variants, MB1283 and MB1285. - -- Antenna daughter board: ST25DV_Discovery_ANT_C5: - - - 40 mm x 24 mm, 13.56 MHz inductive antenna etched on the PCB - - ST25DV04K Dynamic NFC / RFID tag - - I 2 C interface connector - - Energy harvesting output (VOUT) with a 10nF capacitance filtering circuit - - GPO configurable as RF WIP/BUSY output, to indicate that an RF operation is ongoing - -The antenna board can be removed, and its 14-pin 0.254mm header connector used as an eval kit header. - -Connections and IOs -=================== - -Default Zephyr Peripheral Mapping ---------------------------------- - -- UART_6 TX/RX : PC6/PC7 (ST-Link Virtual Port Com) -- UART_2 TX/RX : PA2/PA3 (Available on J6 connector) -- I2C1 SCL/SDA : PB6/PB7 (Touchscreen STMPE811, interrupt pin PB5) -- SPI2 SCK/MOSI/CS : PB13/PC3/PB12 (LCD display FRD24048TP, reset pin PC1, DC pin PC0) -- SPI1 SCK/MISO/MOSI/CS : PA5/PA6/PA7/PA4 (External ST25DV connector J6) -- GPIO : PE8/PE9/PE10/PE11/PE12 (Joystick) -- LD1 : PC13 (Orange led) -- LD2 : PC4 (Yellow led) -- GPIO : PE15/PE7 (Available on external ST25DV connector J6) -- GPIO : PE14 (Available on J5 connector) - -Serial Port -=========== - -The Zephyr console output and shell are assigned to UART6, which is connected to the -onboard ST-LINK/V2 Virtual COM port interface. -Default communication settings are 115200 8N1. - -Programming and Debugging -************************* - -Applications for the ``st25dv_mb1283_disco`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -If programming fails, press the reset button (black) and release it while "west flash" is running. - -Flashing -======== - -ST25DV Discovery kit includes an ST-LINK/V2 embedded debug tool interface. -This interface is supported by the openocd version included in the Zephyr SDK. - -Flashing an application to ST25DV Discovery --------------------------------------------- - -First, connect the ST25DV Discovery kit to your host computer using -the USB port to prepare it for flashing. Then build and flash your application. - -Here is an example for the :zephyr:code-sample:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: st25dv_mb1283_disco - :goals: build flash - -Run a serial host program to connect with your board: - -.. code-block:: console - - $ minicom -D /dev/ttyACM0 - -You should see the following message on the console: - -.. code-block:: console - - Hello World! st25dv_mb1283_disco - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:zephyr:code-sample:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: st25dv_mb1283_disco - :goals: debug - - -.. _ST25DV-DISCO website: - https://www.st.com/en/nfc/st25dv-i2c-series-dynamic-nfc-tags.html - -.. _ST25DV datasheet: - https://www.st.com/resource/en/datasheet/st25dv04k.pdf - -.. _STM32F40xxx reference manual: - https://www.st.com/resource/en/reference_manual/rm0090-stm32f405415-stm32f407417-stm32f427437-and-stm32f429439-advanced-armbased-32bit-mcus-stmicroelectronics.pdf diff --git a/boards/st/steval_fcu001v1/doc/index.rst b/boards/st/steval_fcu001v1/doc/index.rst index f10c0300957..aea2ce5ac79 100644 --- a/boards/st/steval_fcu001v1/doc/index.rst +++ b/boards/st/steval_fcu001v1/doc/index.rst @@ -1,17 +1,10 @@ -.. _steval_fcu001v1: - -ST STM32 Flight Controller Unit -############################### +.. zephyr:board:: steval_fcu001v1 Overview ******** The STEVAL-FCU001V1 is a Cortex M4 MCU-based flight controller unit for toy quad-copter drones. -.. figure:: img/steval_fcu001v1.jpg - :align: center - :alt: STM32 Flight Controller Unit - Hardware ******** diff --git a/boards/st/steval_stwinbx1/Kconfig b/boards/st/steval_stwinbx1/Kconfig deleted file mode 100644 index 520aea81d16..00000000000 --- a/boards/st/steval_stwinbx1/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -# STEVAL_STWINBX1 Development kit board configuration - -# Copyright (c) 2024 STMicroelectronics -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_STEVAL_STWINBX1 - -config BOARD_SERIAL_BACKEND_CDC_ACM - bool "Use USB CDC as serial console backend" - default y - -endif # BOARD_STEVAL_STWINBX1 diff --git a/boards/st/steval_stwinbx1/Kconfig.defconfig b/boards/st/steval_stwinbx1/Kconfig.defconfig index 657170dd303..3d72efbe742 100644 --- a/boards/st/steval_stwinbx1/Kconfig.defconfig +++ b/boards/st/steval_stwinbx1/Kconfig.defconfig @@ -7,12 +7,6 @@ if BOARD_STEVAL_STWINBX1 if BT -config SPI - default y - -config BT_SPI - default y - config BT_BLUENRG_ACI default y @@ -26,50 +20,6 @@ config SPI_STM32_INTERRUPT default y depends on SPI -if BOARD_SERIAL_BACKEND_CDC_ACM - -config USB_DEVICE_STACK - default y - -config USB_CDC_ACM - default SERIAL - -config USB_DEVICE_INITIALIZE_AT_BOOT - default y if CONSOLE - -config SHELL_BACKEND_SERIAL_CHECK_DTR - default SHELL - depends on UART_LINE_CTRL - -config UART_LINE_CTRL - default SHELL - -config USB_DEVICE_REMOTE_WAKEUP - default n - -config USB_DEVICE_VID - default 0x0483 - -config USB_DEVICE_PID - default 0x5740 - -config USB_DEVICE_PRODUCT - default "Zephyr CDC STEval-STWinbx1" - -if LOG - -# Logger cannot use itself to log -choice USB_CDC_ACM_LOG_LEVEL_CHOICE - default USB_CDC_ACM_LOG_LEVEL_OFF -endchoice - -endif # LOG - -endif # BOARD_SERIAL_BACKEND_CDC_ACM - -DT_CHOSEN_ZEPHYR_CONSOLE := zephyr,console - -config UART_CONSOLE - default y if $(dt_chosen_enabled,$(DT_CHOSEN_ZEPHYR_CONSOLE)) && CONSOLE +source "boards/common/usb/Kconfig.cdc_acm_serial.defconfig" endif # BOARD_STEVAL_STWINBX1 diff --git a/boards/st/steval_stwinbx1/doc/index.rst b/boards/st/steval_stwinbx1/doc/index.rst index cd0e2469484..8ef4c10dcca 100644 --- a/boards/st/steval_stwinbx1/doc/index.rst +++ b/boards/st/steval_stwinbx1/doc/index.rst @@ -1,7 +1,4 @@ -.. _steval_stwinbx1_board: - -STEVAL STWINBX1 Development kit -############################### +.. zephyr:board:: steval_stwinbx1 Overview ******** @@ -13,10 +10,6 @@ IoT contexts such as condition monitoring and predictive maintenance. The STEVAL-STWINBX1 kit consists of an STWIN.box core system, a 480mAh LiPo battery, an adapter for the ST-LINK debugger, a plastic case, an adapter board for DIL 24 sensors and a flexible cable. -.. image:: img/steval_stwinbx1.jpg - :align: center - :alt: STEVAL-STWINBX1 Development kit - More information about the board can be found at the `STEVAL-STWINBX1 Development kit website`_. @@ -237,23 +230,7 @@ Console There are two possible options for Zephyr console output: -- through USB as USB CDC/ACM class. This is the default case present in the board dts file - and is enabled by :kconfig:option:`CONFIG_BOARD_SERIAL_BACKEND_CDC_ACM`. - -.. code-block:: dts - :caption: boards/st/steval_stwinbx1/steval_stwinbx1.dts - - / { - chosen { - zephyr,console = &cdc_acm_uart0; - }; - }; - - &zephyr_udc0 { - cdc_acm_uart0: cdc_acm_uart0 { - compatible = "zephyr,cdc-acm-uart"; - }; - }; +- through common CDC ACM UART backend configuration for all boards - through USART2 which is available on SWD connector (CN4). In this case a JTAG adapter can be used to connect STEVAL-STWINBX1 and have both SWD and console lines available. diff --git a/boards/st/steval_stwinbx1/steval_stwinbx1.dts b/boards/st/steval_stwinbx1/steval_stwinbx1.dts index 040452e91b0..c9ef1b4299b 100644 --- a/boards/st/steval_stwinbx1/steval_stwinbx1.dts +++ b/boards/st/steval_stwinbx1/steval_stwinbx1.dts @@ -14,9 +14,6 @@ compatible = "st,steval_stwinbx1"; chosen { - zephyr,console = &cdc_acm_uart0; - zephyr,shell-uart = &cdc_acm_uart0; - zephyr,sram = &sram0; zephyr,flash = &flash0; zephyr,code-partition = &slot0_partition; @@ -218,6 +215,12 @@ stm32_lp_tick_source: &lptim1 { drdy-gpios = <&gpiof 9 GPIO_ACTIVE_HIGH>; status = "okay"; }; + + ilps22qs@5c { + compatible = "st,ilps22qs"; + reg = <0x5c>; + status = "okay"; + }; }; &timers5 { @@ -244,16 +247,14 @@ zephyr_udc0: &usbotg_fs { pinctrl-0 = <&usb_otg_fs_dm_pa11 &usb_otg_fs_dp_pa12>; pinctrl-names = "default"; status = "okay"; - - cdc_acm_uart0: cdc_acm_uart0 { - compatible = "zephyr,cdc-acm-uart"; - }; }; +#include <../boards/common/usb/cdc_acm_serial.dtsi> + &adc1 { pinctrl-0 = <&adc1_in1_pc0>; pinctrl-names = "default"; - st,adc-clock-source = ; + st,adc-clock-source = "ASYNC"; st,adc-prescaler = <4>; vref-mv = <2750>; status = "okay"; @@ -262,7 +263,7 @@ zephyr_udc0: &usbotg_fs { &adc4 { pinctrl-0 = <&adc4_in3_pc2>; pinctrl-names = "default"; - st,adc-clock-source = ; + st,adc-clock-source = "ASYNC"; st,adc-prescaler = <4>; vref-mv = <2750>; status = "okay"; diff --git a/boards/st/stm3210c_eval/doc/index.rst b/boards/st/stm3210c_eval/doc/index.rst index 117e378b659..43a5bdd4b68 100644 --- a/boards/st/stm3210c_eval/doc/index.rst +++ b/boards/st/stm3210c_eval/doc/index.rst @@ -1,7 +1,4 @@ -.. _stm3210c_eval_board: - -ST STM3210C Evaluation -###################### +.. zephyr:board:: stm3210c_eval Overview ******** @@ -15,10 +12,6 @@ audio DAC, MEMS, EEPROM and more) and develop your own applications. Extension headers make it easy to connect a daughterboard or wrapping board for your specific application. -.. image:: img/stm3210c_eval.jpg - :align: center - :alt: STM3210C-EVAL - More information about the board can be found at the `STM3210C-EVAL website`_. Hardware diff --git a/boards/st/stm32373c_eval/doc/index.rst b/boards/st/stm32373c_eval/doc/index.rst index b6895a4bca2..10f722c650d 100644 --- a/boards/st/stm32373c_eval/doc/index.rst +++ b/boards/st/stm32373c_eval/doc/index.rst @@ -1,7 +1,4 @@ -.. _stm32373c_eval_board: - -ST STM32373C Evaluation -####################### +.. zephyr:board:: stm32373c_eval Overview ******** @@ -11,10 +8,6 @@ The full range of hardware features on the board can help the user evaluate all Extension headers make it possible to easily connect a daughter board or wrapping board for a specific application. -.. image:: img/stm32373c_eval.jpg - :align: center - :alt: STM32373C-EVAL - More information about the board can be found at the `STM32373C-EVAL website`_. Hardware diff --git a/boards/st/stm32c0116_dk/doc/index.rst b/boards/st/stm32c0116_dk/doc/index.rst index 52e3c24ef20..b955518a776 100644 --- a/boards/st/stm32c0116_dk/doc/index.rst +++ b/boards/st/stm32c0116_dk/doc/index.rst @@ -1,7 +1,4 @@ -.. _stm32c0116_dk_board: - -ST STM32C0116-DK Discovery Kit -############################## +.. zephyr:board:: stm32c0116_dk Overview ******** @@ -12,10 +9,6 @@ to DIL20 module designed with the STM32C011F6 microcontroller and allows the use and share applications. It includes an on-board ST-LINK/V2-1 to debug and program the embedded STM32 microcontroller. Important board features include: -.. image:: img/stm32c0116_dk.jpg - :align: center - :alt: STM32C0116-DK - More information about the board can be found at the `STM32C0116-DK website`_. Hardware diff --git a/boards/st/stm32c0116_dk/stm32c0116_dk.dts b/boards/st/stm32c0116_dk/stm32c0116_dk.dts index 79b4db1fa25..1e388a0a281 100644 --- a/boards/st/stm32c0116_dk/stm32c0116_dk.dts +++ b/boards/st/stm32c0116_dk/stm32c0116_dk.dts @@ -141,7 +141,7 @@ &adc1 { pinctrl-0 = <&adc1_in8_pa8>; pinctrl-names = "default"; - st,adc-clock-source = ; + st,adc-clock-source = "SYNC"; st,adc-prescaler = <2>; status = "okay"; diff --git a/boards/st/stm32f072_eval/doc/index.rst b/boards/st/stm32f072_eval/doc/index.rst index b1bb7b0b5ac..43c1eb1e0be 100644 --- a/boards/st/stm32f072_eval/doc/index.rst +++ b/boards/st/stm32f072_eval/doc/index.rst @@ -1,7 +1,4 @@ -.. _stm32f072_eval_board: - -ST STM32F072 Evaluation -####################### +.. zephyr:board:: stm32f072_eval Overview ******** @@ -35,11 +32,6 @@ Here are some highlights of the STM32F072-EVAL board: - Smart Card slot - Motor control connector - -.. image:: img/stm32f072_eval.jpg - :align: center - :alt: STM32F072-EVAL - Hardware ******** diff --git a/boards/st/stm32f072b_disco/doc/index.rst b/boards/st/stm32f072b_disco/doc/index.rst index 6f97341d2b3..9790d3f4d0e 100644 --- a/boards/st/stm32f072b_disco/doc/index.rst +++ b/boards/st/stm32f072b_disco/doc/index.rst @@ -1,7 +1,4 @@ -.. _stm32f072b_disco_board: - -ST STM32F072B Discovery -####################### +.. zephyr:board:: stm32f072b_disco Overview ******** @@ -29,10 +26,6 @@ started quickly. Here are some highlights of the STM32F072B-DISCO board: - One linear touch sensor or four touch keys - RF EEprom daughter board connector -.. image:: img/stm32f072b_disco.jpg - :align: center - :alt: STM32F072B-DISCO - More information about the board can be found at the `STM32F072B-DISCO website`_. diff --git a/boards/st/stm32f0_disco/doc/index.rst b/boards/st/stm32f0_disco/doc/index.rst index 64e4605566b..dccce953fac 100644 --- a/boards/st/stm32f0_disco/doc/index.rst +++ b/boards/st/stm32f0_disco/doc/index.rst @@ -1,7 +1,4 @@ -.. _stm32f0_disco_board: - -ST STM32F0 Discovery -#################### +.. zephyr:board:: stm32f0_disco Overview ******** @@ -11,10 +8,6 @@ integrates the ST-LINK/V2-1 debugger and programmer. It also comes with a comprehensive STM32 software HAL library and various packaged software examples. -.. image:: img/stm32f0_disco.jpg - :align: center - :alt: STM32F0DISCOVERY - More information about the board can be found at the `STM32F0DISCOVERY website`_. Hardware diff --git a/boards/st/stm32f3_disco/doc/index.rst b/boards/st/stm32f3_disco/doc/index.rst index e557eb013c7..107f3a60964 100644 --- a/boards/st/stm32f3_disco/doc/index.rst +++ b/boards/st/stm32f3_disco/doc/index.rst @@ -1,7 +1,4 @@ -.. _stm32f3_disco_board: - -ST STM32F3 Discovery -#################### +.. zephyr:board:: stm32f3_disco Overview ******** @@ -35,10 +32,6 @@ started quickly. Here are some highlights of the STM32F3DISCOVERY board: .. HINT:: Recent PCB revisions (E and newer) are shipped with I3G4250D and LSM303AGR. -.. image:: img/stm32f3_disco.jpg - :align: center - :alt: STM32F3DISCOVERY - More information about the board can be found at the `STM32F3DISCOVERY website`_. diff --git a/boards/st/stm32f3_disco/stm32f3_disco.dts b/boards/st/stm32f3_disco/stm32f3_disco.dts index 44a66f038be..01fbad2721f 100644 --- a/boards/st/stm32f3_disco/stm32f3_disco.dts +++ b/boards/st/stm32f3_disco/stm32f3_disco.dts @@ -219,7 +219,7 @@ zephyr_udc0: &usb { &adc1 { pinctrl-0 = <&adc1_in1_pa0>; pinctrl-names = "default"; - st,adc-clock-source = ; + st,adc-clock-source = "SYNC"; st,adc-prescaler = <2>; status = "okay"; }; diff --git a/boards/st/stm32f411e_disco/doc/index.rst b/boards/st/stm32f411e_disco/doc/index.rst index acac229c810..3b97cf29012 100644 --- a/boards/st/stm32f411e_disco/doc/index.rst +++ b/boards/st/stm32f411e_disco/doc/index.rst @@ -1,7 +1,4 @@ -.. _stm32f411e_disco_board: - -ST STM32F411E Discovery -####################### +.. zephyr:board:: stm32f411e_disco Overview ******** @@ -29,10 +26,6 @@ Here are some highlights of the STM32F411E-DISCO board: - USB OTG with micro-AB connector - Extension header for LQFP100 I/Os for a quick connection to the prototyping board and an easy probing -.. image:: img/stm32f411e_disco.jpg - :align: center - :alt: STM32F411E-DISCO - More information about the board can be found at the `32F411EDISCOVERY website`_. Hardware diff --git a/boards/st/stm32f411e_disco/stm32f411e_disco.dts b/boards/st/stm32f411e_disco/stm32f411e_disco.dts index 197df98212d..1f501e05ae0 100644 --- a/boards/st/stm32f411e_disco/stm32f411e_disco.dts +++ b/boards/st/stm32f411e_disco/stm32f411e_disco.dts @@ -81,6 +81,9 @@ accel0 = &lsm303agr_accel; mcuboot-button0 = &user_button; mcuboot-led0 = &orange_led_3; + die-temp0 = &die_temp; + volt-sensor0 = &vref; + volt-sensor1 = &vbat; }; }; @@ -193,3 +196,20 @@ zephyr_udc0: &usbotg_fs { }; }; }; + +&adc1 { + st,adc-prescaler = <2>; + status = "okay"; +}; + +&die_temp { + status = "okay"; +}; + +&vref { + status = "okay"; +}; + +&vbat { + status = "okay"; +}; diff --git a/boards/st/stm32f412g_disco/doc/index.rst b/boards/st/stm32f412g_disco/doc/index.rst index ae84de7cea7..db8674826c2 100644 --- a/boards/st/stm32f412g_disco/doc/index.rst +++ b/boards/st/stm32f412g_disco/doc/index.rst @@ -1,7 +1,4 @@ -.. _stm32f412g_disco_board: - -ST STM32F412G Discovery -####################### +.. zephyr:board:: stm32f412g_disco Overview ******** @@ -39,16 +36,12 @@ some highlights of the STM32F412G-DISCO board: - Extension connector for direct access to various features of STM32F412ZGT6 MCU - Comprehensive free software including a variety of examples, part of STM32Cube package -.. image:: img/stm32f412g_disco.jpg - :align: center - :alt: STM32F412G-DISCO - More information about the board can be found at the `32F412GDISCOVERY website`_. Hardware ******** -STM32F469I-DISCO Discovery kit provides the following hardware components: +STM32F412G-DISCO Discovery kit provides the following hardware components: - STM32F412ZGT6 in LQFP144 package - ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU diff --git a/boards/st/stm32f413h_disco/Kconfig.stm32f413h_disco b/boards/st/stm32f413h_disco/Kconfig.stm32f413h_disco new file mode 100644 index 00000000000..0dc50d88be0 --- /dev/null +++ b/boards/st/stm32f413h_disco/Kconfig.stm32f413h_disco @@ -0,0 +1,5 @@ +# Copyright (c) 2024 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_STM32F413H_DISCO + select SOC_STM32F413XX diff --git a/boards/st/stm32f413h_disco/arduino_r3_connector.dtsi b/boards/st/stm32f413h_disco/arduino_r3_connector.dtsi new file mode 100644 index 00000000000..1a5a2bc468c --- /dev/null +++ b/boards/st/stm32f413h_disco/arduino_r3_connector.dtsi @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2024 STMicroelectronics + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + arduino_header: connector { + compatible = "arduino-header-r3"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpioc 0 0>, /* A0 */ + <1 0 &gpioa 1 0>, /* A1 */ + <2 0 &gpioa 2 0>, /* A2 */ + <3 0 &gpioa 5 0>, /* A3 */ + <4 0 &gpiob 1 0>, /* A4 */ + <5 0 &gpioc 4 0>, /* A5 */ + <6 0 &gpiof 6 0>, /* D0 */ + <7 0 &gpiof 7 0>, /* D1 */ + <8 0 &gpiog 13 0>, /* D2 */ + <9 0 &gpiof 10 0>, /* D3 */ + <10 0 &gpiob 6 0>, /* D4 */ + <11 0 &gpioe 6 0>, /* D5 */ + <12 0 &gpiob 0 0>, /* D6 */ + <13 0 &gpioc 13 0>, /* D7 */ + <14 0 &gpioa 4 0>, /* D8 */ + <15 0 &gpiob 8 0>, /* D9 */ + <16 0 &gpioa 15 0>, /* D10 */ + <17 0 &gpiob 5 0>, /* D11 */ + <18 0 &gpiob 4 0>, /* D12 */ + <19 0 &gpiob 12 0>, /* D13 */ + <20 0 &gpiob 11 0>, /* D14 */ + <21 0 &gpiob 10 0>; /* D15 */ + }; +}; + +arduino_i2c: &i2c2 {}; +arduino_spi: &spi3 {}; +arduino_serial: &uart7 {}; diff --git a/boards/st/stm32f413h_disco/board.cmake b/boards/st/stm32f413h_disco/board.cmake new file mode 100644 index 00000000000..800b779a42d --- /dev/null +++ b/boards/st/stm32f413h_disco/board.cmake @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 + +# keep first +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") +board_runner_args(jlink "--device=STM32F413ZH" "--speed=4000") + +# keep first +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/stm32f413h_disco/board.yml b/boards/st/stm32f413h_disco/board.yml new file mode 100644 index 00000000000..e29d47b57be --- /dev/null +++ b/boards/st/stm32f413h_disco/board.yml @@ -0,0 +1,6 @@ +board: + name: stm32f413h_disco + full_name: STM32F413H Discovery + vendor: st + socs: + - name: stm32f413xx diff --git a/boards/st/stm32f413h_disco/doc/img/stm32F413H_DiscoveryKit.webp b/boards/st/stm32f413h_disco/doc/img/stm32F413H_DiscoveryKit.webp new file mode 100644 index 00000000000..93785299b0b Binary files /dev/null and b/boards/st/stm32f413h_disco/doc/img/stm32F413H_DiscoveryKit.webp differ diff --git a/boards/st/stm32f413h_disco/doc/index.rst b/boards/st/stm32f413h_disco/doc/index.rst new file mode 100644 index 00000000000..49ce176da65 --- /dev/null +++ b/boards/st/stm32f413h_disco/doc/index.rst @@ -0,0 +1,206 @@ +.. zephyr:board:: stm32f413h_disco + +Overview +******** + +The STM32F413H-DISCO Discovery kit features an ARM Cortex-M4 based STM32F413ZH MCU +with a wide range of connectivity support and configurations. Here are +some highlights of the STM32F413H-DISCO board: + + +- STM32F413ZHT6 microcontroller featuring 1.5 Mbyte of Flash memory and 320 Kbytes of RAM in an LQFP144 package +- On-board ST-LINK/V2-1 SWD debugger supporting USB re-enumeration capability: + + - USB virtual COM port + - mass storage + - debug port + +- 1.54 inch 240x240 pixel TFT color LCD with parallel interface and capacitive touchscreen +- I2S Audio CODEC, with a stereo headset jack, including analog microphone input and a loudspeaker output +- Stereo digital MEMS microphones +- MicroSD card connector extension +- I2C extension connector +- 128 Mbit Quad-SPI Nor Flash +- 8 Mbit 16-bit wide PSRAM +- Reset and User buttons +- Two color user LEDs. +- USB OTG FS with Micro-AB connector +- Four power supply options: + + - ST-LINK/V2-1 USB connector + - User USB FS connector + - VIN from Arduino* connectors + - + 5 V from Arduino* connectors + +- Two power supplies for MCU: 2.0 V and 3.3 V +- Compatible with Arduino(tm) Uno revision 3 connectors +- Extension connector for direct access to various features of STM32F413ZHT6 MCU +- Comprehensive free software including a variety of examples, part of STM32Cube package + +More information about the board can be found at the `32F413HDISCOVERY website`_. + +Hardware +******** + +STM32F413H-DISCO Discovery kit provides the following hardware components: + +- STM32F413ZHT6 in LQFP144 package +- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU +- 100 MHz max CPU frequency +- VDD from 1.7 V to 3.6 V +- 1.5 MB Flash +- 320 KB SRAM +- GPIO with external interrupt capability +- LCD parallel interface, 8080/6800 modes +- 1x12-bit ADC with 16 channels +- RTC +- Advanced-control Timer +- General Purpose Timers (12) +- Watchdog Timers (2) +- USART/UART (10) +- I2C (4) +- SPI (5) +- SDIO +- SAI +- 3xCAN +- USB OTG 2.0 Full-speed +- CRC calculation unit +- True random number generator +- DMA Controller + +More information about STM32F413ZH can be found here: + - `STM32F413ZH on www.st.com`_ + - `STM32F413 reference manual`_ + +Supported Features +================== + +The Zephyr STM32F413H-DISCO board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported by Zephyr. + +The default configuration can be found in +:zephyr_file:`boards/st/stm32f413h_disco/stm32f413h_disco_defconfig` + + +Pin Mapping +=========== + +STM32F413H-DISCO Discovery kit has 8 GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +For more details please refer to `32F413HDISCOVERY board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- +- UART_6_TX : PG14 +- UART_6_RX : PG9 +- LD1 : PE3 +- LD2 : PC5 + +System Clock +============ + +STM32F413H-DISCO System Clock could be driven by internal or external oscillator, +as well as main PLL clock. By default System clock is driven by PLL clock at 100MHz, +that is driven by the internal oscillator. + +Serial Port +=========== + +The STM32F413H-DISCO Discovery kit has up to 10 UARTs. The Zephyr console output is assigned to UART6. +Default settings are 115200 8N1. + + +Programming and Debugging +************************* + +STM32F413H-DISCO Discovery kit includes an ST-LINK/V2 embedded debug tool interface. + +Applications for the STM32F413H-DISCO board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. + +Alternatively, OpenOCD or JLink can also be used to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner openocd + $ west flash --runner jlink + +Flashing an application to STM32F413H-DISCO +------------------------------------------- + +Connect the STM32F413H-DISCO Discovery kit to your host computer using +the USB port, then run a serial host program to connect with your +board: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +Then build and flash an application. Here is an example for the +:zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32f413h_disco + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + Hello World! stm32f413h_disco/stm32f413xx + + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32f413h_disco + :maybe-skip-config: + :goals: debug + +.. _32F413HDISCOVERY website: + https://www.st.com/en/evaluation-tools/32f413hdiscovery.html + +.. _32F413HDISCOVERY board User Manual: + https://www.st.com/resource/en/user_manual/um2135-discovery-kit-with-stm32f413zh-mcu-stmicroelectronics.pdf + +.. _STM32F413ZH on www.st.com: + https://www.st.com/en/microcontrollers/stm32f413zh.html + +.. _STM32F413 reference manual: + https://www.st.com/resource/en/reference_manual/rm0430-stm32f413423-advanced-armbased-32bit-mcus-stmicroelectronics.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/st/stm32f413h_disco/stm32f413h_disco.dts b/boards/st/stm32f413h_disco/stm32f413h_disco.dts new file mode 100644 index 00000000000..72315d784e2 --- /dev/null +++ b/boards/st/stm32f413h_disco/stm32f413h_disco.dts @@ -0,0 +1,102 @@ +/* + * Copyright (c) 2024 STMicroelectronics + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include "arduino_r3_connector.dtsi" +#include + +/ { + model = "STMicroelectronics STM32F413H-DISCO board"; + compatible = "st,stm32f413h-disco"; + + chosen { + zephyr,console = &usart6; + zephyr,shell-uart = &usart6; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + }; + + leds { + compatible = "gpio-leds"; + green_led_1: led_1 { + gpios = <&gpioc 5 GPIO_ACTIVE_HIGH>; + label = "User LD1"; + }; + red_led_2: led_2 { + gpios = <&gpioe 3 GPIO_ACTIVE_HIGH>; + label = "User LD4"; + }; + }; + + aliases { + led0 = &green_led_1; + led1 = &red_led_2; + + }; +}; + +&clk_lsi { + status = "okay"; +}; + +&clk_hse { + hse-bypass; + clock-frequency = ; /* STLink 8MHz clock */ + status = "okay"; +}; + +&pll { + div-m = <4>; + mul-n = <100>; + div-p = <2>; + div-q = <8>; + clocks = <&clk_hse>; + status = "okay"; +}; + +&rcc { + clocks = <&pll>; + clock-frequency = ; + ahb-prescaler = <1>; + apb1-prescaler = <2>; + apb2-prescaler = <1>; +}; + +&usart6 { + pinctrl-0 = <&usart6_tx_pg14 &usart6_rx_pg9>; + pinctrl-names = "default"; + current-speed = <115200>; + status = "okay"; +}; + +&uart7 { + pinctrl-0 = <&uart7_tx_pf7 &uart7_rx_pf6>; + pinctrl-names = "default"; + current-speed = <115200>; + status = "okay"; +}; + +&i2c2 { + pinctrl-0 = <&i2c2_scl_pb10 &i2c2_sda_pb11>; + pinctrl-names = "default"; + clock-frequency = ; + status = "okay"; +}; + +&spi3 { + pinctrl-0 = <&spi3_nss_pa15 &spi3_sck_pb12 + &spi3_miso_pb4 &spi3_mosi_pb5>; + pinctrl-names = "default"; + status = "okay"; +}; + +&rtc { + clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>, + <&rcc STM32_SRC_LSI RTC_SEL(2)>; + status = "okay"; +}; diff --git a/boards/st/stm32f413h_disco/stm32f413h_disco.yaml b/boards/st/stm32f413h_disco/stm32f413h_disco.yaml new file mode 100644 index 00000000000..27f178934f8 --- /dev/null +++ b/boards/st/stm32f413h_disco/stm32f413h_disco.yaml @@ -0,0 +1,14 @@ +identifier: stm32f413h_disco +name: ST STM32F413H Discovery +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - arduino_gpio + - arduino_serial + - arduino_i2c + - arduino_spi +vendor: st diff --git a/boards/st/stm32f413h_disco/stm32f413h_disco_defconfig b/boards/st/stm32f413h_disco/stm32f413h_disco_defconfig new file mode 100644 index 00000000000..2ae252482c9 --- /dev/null +++ b/boards/st/stm32f413h_disco/stm32f413h_disco_defconfig @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable HW stack protection +CONFIG_HW_STACK_PROTECTION=y + +CONFIG_SERIAL=y + +# Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable GPIO ports A, B, C, D, E, F, G, H +CONFIG_GPIO=y diff --git a/boards/st/stm32f413h_disco/support/openocd.cfg b/boards/st/stm32f413h_disco/support/openocd.cfg new file mode 100644 index 00000000000..837f0cd2958 --- /dev/null +++ b/boards/st/stm32f413h_disco/support/openocd.cfg @@ -0,0 +1,12 @@ +source [find board/stm32f4discovery.cfg] + +$_TARGETNAME configure -event gdb-attach { + echo "Debugger attaching: halting execution" + reset halt + gdb_breakpoint_override hard +} + +$_TARGETNAME configure -event gdb-detach { + echo "Debugger detaching: resuming execution" + resume +} diff --git a/boards/st/stm32f429i_disc1/doc/index.rst b/boards/st/stm32f429i_disc1/doc/index.rst index 28a79e9ac2a..24780fb6cc0 100644 --- a/boards/st/stm32f429i_disc1/doc/index.rst +++ b/boards/st/stm32f429i_disc1/doc/index.rst @@ -1,7 +1,4 @@ -.. _stm32f429i_disc1_board: - -ST STM32F429I Discovery -####################### +.. zephyr:board:: stm32f429i_disc1 Overview ******** @@ -31,10 +28,6 @@ some highlights of the STM32F429I-DISC1 board: - Two user LEDs: LD3 (green), LD4 (red) - Two USB OTG LEDs: LD5 (green) VBUS and LD6 (red) OC (over-current) -.. image:: img/stm32f429i_disc1.jpg - :align: center - :alt: STM32F429I-DISC1 - More information about the board can be found at the `STM32F429I-DISC1 website`_. Hardware @@ -99,6 +92,8 @@ The Zephyr stm32f429i_disc1 board configuration supports the following hardware +-----------+------------+-------------------------------------+ | OTG_HS | on-chip | usbotg_hs | +-----------+------------+-------------------------------------+ +| LTDC | on-chip | display | ++-----------+------------+-------------------------------------+ Other hardware features are not yet supported on Zephyr porting. @@ -158,6 +153,7 @@ and host OTG operation, but only device mode has been tested with Zephyr at this Programming and Debugging ************************* +The STM32F429I-DISC1 Discovery kit includes a ST-LINK/V2-B embedded debug tool interface. Applications for the ``stm32f429i_disc1`` board configuration can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details). @@ -165,19 +161,17 @@ and flashed in the usual way (see :ref:`build_an_application` and Flashing ======== -The STM32F429I-DISC1 Discovery kit includes a ST-LINK/V2-B embedded debug tool interface. -This interface is supported by the openocd version included in Zephyr SDK. - -Flashing an application to STM32F429I-DISC1 -------------------------------------------- +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. -The board is configured to be flashed using west OpenOCD runner. -Alternatively, you can use `STM32CubeProgrammer`_ (after installing it) using the ``--runner`` -(or ``-r``) option: +Alternatively, OpenOCD, JLink, or pyOCD can also be used to flash the board using +the ``--runner`` (or ``-r``) option: .. code-block:: console - $ west flash --runner stm32cubeprogrammer + $ west flash --runner openocd + $ west flash --runner jlink + $ west flash --runner pyocd First, connect the STM32F429I-DISC1 Discovery kit to your host computer using the USB port to prepare it for flashing. Then build and flash your application. diff --git a/boards/st/stm32f429i_disc1/stm32f429i_disc1.dts b/boards/st/stm32f429i_disc1/stm32f429i_disc1.dts index cbcc551a716..26d1833c249 100644 --- a/boards/st/stm32f429i_disc1/stm32f429i_disc1.dts +++ b/boards/st/stm32f429i_disc1/stm32f429i_disc1.dts @@ -22,6 +22,7 @@ zephyr,flash = &flash0; zephyr,ccm = &ccm0; zephyr,display = <dc; + zephyr,touch = &stmpe811; }; sdram2: sdram@d0000000 { @@ -60,8 +61,6 @@ lvgl_pointer { compatible = "zephyr,lvgl-pointer-input"; input = <&stmpe811>; - invert-x; - invert-y; }; mipi_dbi { @@ -176,6 +175,8 @@ touch-detect-delay-us = <5000>; touch-average-control = <8>; tracking-index = <127>; + inverted-x; + inverted-y; }; }; diff --git a/boards/st/stm32f469i_disco/doc/index.rst b/boards/st/stm32f469i_disco/doc/index.rst index 549ffd4c67e..7570831c568 100644 --- a/boards/st/stm32f469i_disco/doc/index.rst +++ b/boards/st/stm32f469i_disco/doc/index.rst @@ -1,7 +1,4 @@ -.. _stm32f469i_disco_board: - -ST STM32F469I Discovery -####################### +.. zephyr:board:: stm32f469i_disco Overview ******** @@ -31,10 +28,6 @@ some highlights of the STM32F469I-DISCO board: - 128-Mbit Quad-SPI NOR Flash - Expansion connectors and Arduino UNO V3 connectors -.. image:: img/stm32f469i_disco.jpg - :align: center - :alt: STM32F469I-DISCO - More information about the board can be found at the `32F469IDISCOVERY website`_. Hardware diff --git a/boards/st/stm32f4_disco/doc/index.rst b/boards/st/stm32f4_disco/doc/index.rst index e590250741a..f21b1cdc014 100644 --- a/boards/st/stm32f4_disco/doc/index.rst +++ b/boards/st/stm32f4_disco/doc/index.rst @@ -1,7 +1,4 @@ -.. _stm32f4_disco_board: - -ST STM32F4 Discovery -#################### +.. zephyr:board:: stm32f4_disco Overview ******** @@ -32,10 +29,6 @@ some highlights of the STM32F4DISCOVERY board: - MP45DT02 ST-MEMS audio sensor omni-directional digital microphone - CS43L22 audio DAC with integrated class D speaker driver -.. image:: img/stm32f4_disco.jpg - :align: center - :alt: STM32F4DISCOVERY - More information about the board can be found at the `STM32F4DISCOVERY website`_. Hardware diff --git a/boards/st/stm32f4_disco/stm32f4_disco.dts b/boards/st/stm32f4_disco/stm32f4_disco.dts index 163612aaf07..4e5d9ff87f8 100644 --- a/boards/st/stm32f4_disco/stm32f4_disco.dts +++ b/boards/st/stm32f4_disco/stm32f4_disco.dts @@ -51,12 +51,35 @@ }; }; + pwmleds: pwmleds { + compatible = "pwm-leds"; + + orange_pwm_led: orange_pwm_led { + pwms = <&pwm4 2 PWM_USEC(100) PWM_POLARITY_NORMAL>; + }; + + green_pwm_led: green_pwm_led { + pwms = <&pwm4 1 PWM_USEC(100) PWM_POLARITY_NORMAL>; + }; + + red_pwm_led: red_pwm_led { + pwms = <&pwm4 3 PWM_USEC(100) PWM_POLARITY_NORMAL>; + }; + + blue_pwm_led: blue_pwm_led { + pwms = <&pwm4 4 PWM_USEC(100) PWM_POLARITY_NORMAL>; + }; + }; + aliases { led0 = &green_led_4; led1 = &orange_led_3; led2 = &red_led_5; led3 = &blue_led_6; sw0 = &user_button; + die-temp0 = &die_temp; + volt-sensor0 = &vref; + volt-sensor1 = &vbat; }; }; @@ -110,6 +133,16 @@ }; }; +&timers4 { + status = "okay"; + + pwm4: pwm { + status = "okay"; + pinctrl-0 = <&tim4_ch1_pd12 &tim4_ch2_pd13 &tim4_ch3_pd14 &tim4_ch4_pd15>; + pinctrl-names = "default"; + }; +}; + &rtc { clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>, <&rcc STM32_SRC_LSI RTC_SEL(2)>; @@ -137,3 +170,20 @@ zephyr_udc0: &usbotg_fs { pinctrl-names = "default"; status = "okay"; }; + +&adc1 { + st,adc-prescaler = <2>; + status = "okay"; +}; + +&die_temp { + status = "okay"; +}; + +&vref { + status = "okay"; +}; + +&vbat { + status = "okay"; +}; diff --git a/boards/st/stm32f4_disco/stm32f4_disco.yaml b/boards/st/stm32f4_disco/stm32f4_disco.yaml index 5bdfaca3b7b..b3cca00ab7b 100644 --- a/boards/st/stm32f4_disco/stm32f4_disco.yaml +++ b/boards/st/stm32f4_disco/stm32f4_disco.yaml @@ -12,5 +12,4 @@ supported: - can - pwm - counter - - usb vendor: st diff --git a/boards/st/stm32f723e_disco/doc/index.rst b/boards/st/stm32f723e_disco/doc/index.rst index 755e87d4a12..412e5998dd0 100644 --- a/boards/st/stm32f723e_disco/doc/index.rst +++ b/boards/st/stm32f723e_disco/doc/index.rst @@ -1,7 +1,4 @@ -.. _stm32f723e_disco_board: - -ST STM32F723E Discovery -####################### +.. zephyr:board:: stm32f723e_disco Overview ******** @@ -23,10 +20,6 @@ and high-speed connectivity features. Important board features include: - USB OTG HS with Micro-AB connectors - USB OTG FS with Micro-AB connectors -.. image:: img/stm32f723e_disco.jpg - :align: center - :alt: STM32F723E-DISCO - More information about the board can be found at the `32F723E-DISCO website`_. Hardware diff --git a/boards/st/stm32f746g_disco/doc/index.rst b/boards/st/stm32f746g_disco/doc/index.rst index 7bd37aa2652..bdd9ee665b6 100644 --- a/boards/st/stm32f746g_disco/doc/index.rst +++ b/boards/st/stm32f746g_disco/doc/index.rst @@ -1,7 +1,4 @@ -.. _stm32f746g_disco_board: - -ST STM32F746G Discovery -####################### +.. zephyr:board:: stm32f746g_disco Overview ******** @@ -35,10 +32,6 @@ and high-speed connectivity features. Important board features include: - USB OTG FS with Micro-AB connectors - Ethernet connector compliant with IEEE-802.3-2002 -.. image:: img/stm32f746g_disco.jpg - :align: center - :alt: STM32F746G-DISCO - More information about the board can be found at the `32F746G-DISCO website`_. Hardware diff --git a/boards/st/stm32f746g_disco/stm32f746g_disco.dts b/boards/st/stm32f746g_disco/stm32f746g_disco.dts index 2c31fef1c92..e224d24beaa 100644 --- a/boards/st/stm32f746g_disco/stm32f746g_disco.dts +++ b/boards/st/stm32f746g_disco/stm32f746g_disco.dts @@ -24,6 +24,7 @@ zephyr,dtcm = &dtcm; zephyr,flash-controller = &n25q128a1; zephyr,display = <dc; + zephyr,touch = &ft5336; }; leds { diff --git a/boards/st/stm32f746g_disco/stm32f746g_disco.yaml b/boards/st/stm32f746g_disco/stm32f746g_disco.yaml index 5442db5bb67..7d58f2b1f2b 100644 --- a/boards/st/stm32f746g_disco/stm32f746g_disco.yaml +++ b/boards/st/stm32f746g_disco/stm32f746g_disco.yaml @@ -19,4 +19,5 @@ supported: - usb_device - display - memc + - dma vendor: st diff --git a/boards/st/stm32f7508_dk/doc/index.rst b/boards/st/stm32f7508_dk/doc/index.rst index 7a3c1c96c22..fae2512a2f0 100644 --- a/boards/st/stm32f7508_dk/doc/index.rst +++ b/boards/st/stm32f7508_dk/doc/index.rst @@ -1,7 +1,4 @@ -.. _stm32f7508_dk_board: - -ST STM32F7508-DK Discovery Kit -############################## +.. zephyr:board:: stm32f7508_dk Overview ******** @@ -34,10 +31,6 @@ and high-speed connectivity features. Important board features include: - USB OTG FS with Micro-AB connectors - Ethernet connector compliant with IEEE-802.3-2002 -.. image:: img/stm32f7508_dk.jpg - :align: center - :alt: STM32F7508-DK - More information about the board can be found at the `32F7508-DK website`_. Hardware diff --git a/boards/st/stm32f7508_dk/stm32f7508_dk.dts b/boards/st/stm32f7508_dk/stm32f7508_dk.dts index 100fd6e661d..cf05ebfd479 100644 --- a/boards/st/stm32f7508_dk/stm32f7508_dk.dts +++ b/boards/st/stm32f7508_dk/stm32f7508_dk.dts @@ -24,6 +24,7 @@ zephyr,dtcm = &dtcm; zephyr,flash-controller = &n25q128a1; zephyr,display = <dc; + zephyr,touch = &ft5336; }; leds { diff --git a/boards/st/stm32f769i_disco/doc/index.rst b/boards/st/stm32f769i_disco/doc/index.rst index 210eb840ff0..5324f080bed 100644 --- a/boards/st/stm32f769i_disco/doc/index.rst +++ b/boards/st/stm32f769i_disco/doc/index.rst @@ -1,7 +1,4 @@ -.. _stm32f769i_disco_board: - -ST STM32F769I Discovery -####################### +.. zephyr:board:: stm32f769i_disco Overview ******** @@ -40,10 +37,6 @@ and high-speed connectivity features. Important board features include: - Comprehensive free software including a variety of examples, part of the STM32Cube package - Supported by a wide choice of integrated development environments -.. image:: img/stm32f769i_disco.jpg - :align: center - :alt: STM32F769I-DISCO - More information about the board can be found at the `32F769I-DISCO website`_. Hardware diff --git a/boards/st/stm32f769i_disco/stm32f769i_disco.dts b/boards/st/stm32f769i_disco/stm32f769i_disco.dts index 9ad4f4ef3bc..94dd6f6bb22 100644 --- a/boards/st/stm32f769i_disco/stm32f769i_disco.dts +++ b/boards/st/stm32f769i_disco/stm32f769i_disco.dts @@ -22,6 +22,7 @@ zephyr,flash = &flash0; zephyr,dtcm = &dtcm; zephyr,flash-controller = &mx25l51245g; + zephyr,touch = &ft6202; }; sdram1: sdram@c0000000 { diff --git a/boards/st/stm32g0316_disco/doc/index.rst b/boards/st/stm32g0316_disco/doc/index.rst index de6c2d91e55..45741fad177 100644 --- a/boards/st/stm32g0316_disco/doc/index.rst +++ b/boards/st/stm32g0316_disco/doc/index.rst @@ -1,7 +1,4 @@ -.. _stm32g0316_disco_board: - -ST STM32G0316 Discovery -####################### +.. zephyr:board:: stm32g0316_disco Overview ******** @@ -11,10 +8,6 @@ This discovery kit offers an SO8 to DIL8 module designed with the STM32G031J6 mi and allows the user to develop applications. It includes an on-board ST-LINK/V2-1 to debug and program the embedded STM32 microcontroller. -.. image:: img/stm32g0316_disco.jpg - :align: center - :alt: STM32G0316-DISCO - Hardware ******** diff --git a/boards/st/stm32g071b_disco/doc/index.rst b/boards/st/stm32g071b_disco/doc/index.rst index e64a06d1213..6937ea9452e 100644 --- a/boards/st/stm32g071b_disco/doc/index.rst +++ b/boards/st/stm32g071b_disco/doc/index.rst @@ -1,7 +1,4 @@ -.. _stm32g071b_disco_board: - -ST STM32G071B Discovery -####################### +.. zephyr:board:: stm32g071b_disco Overview ******** @@ -43,10 +40,6 @@ as a USB Type-C™ and Power Delivery analyzer. - On-board ST-LINK/V2-1 debugger/programmer with USB enumeration capability: mass storage, Virtual COM port and debug port -.. image:: img/stm32g071b_disco.jpg - :align: center - :alt: STM32G071B-DISCO - More information about the board can be found at the `STM32G071B-DISCO website`_. diff --git a/boards/st/stm32g081b_eval/doc/index.rst b/boards/st/stm32g081b_eval/doc/index.rst index 1f737c8daa1..27d932b096b 100644 --- a/boards/st/stm32g081b_eval/doc/index.rst +++ b/boards/st/stm32g081b_eval/doc/index.rst @@ -1,7 +1,4 @@ -.. _stm32g081b_eval_board: - -ST STM32G081B Evaluation -######################## +.. zephyr:board:: stm32g081b_eval Overview ******** @@ -84,10 +81,6 @@ through various use cases. - USB2.0 Type-A receptacle - 19 V power jack for USB PD -.. image:: img/stm32g081b_eval.jpg - :align: center - :alt: STM32G081B-EVAL - More information about the board can be found at the `STM32G081B-EVAL website`_. diff --git a/boards/st/stm32g081b_eval/stm32g081b_eval.dts b/boards/st/stm32g081b_eval/stm32g081b_eval.dts index fa29e8147d0..103e745cfe0 100644 --- a/boards/st/stm32g081b_eval/stm32g081b_eval.dts +++ b/boards/st/stm32g081b_eval/stm32g081b_eval.dts @@ -131,7 +131,7 @@ &adc1 { pinctrl-0 = <&adc1_in3_pa3 &adc1_in9_pb1>; pinctrl-names = "default"; - st,adc-clock-source = ; + st,adc-clock-source = "SYNC"; st,adc-prescaler = <4>; status = "okay"; diff --git a/boards/st/stm32h573i_dk/doc/index.rst b/boards/st/stm32h573i_dk/doc/index.rst index 86190a77ded..c5ae45a9a20 100644 --- a/boards/st/stm32h573i_dk/doc/index.rst +++ b/boards/st/stm32h573i_dk/doc/index.rst @@ -1,7 +1,4 @@ -.. _stm32h573i_dk_board: - -ST STM32H573I-DK Discovery -########################## +.. zephyr:board:: stm32h573i_dk Overview ******** @@ -43,10 +40,6 @@ the STM32H573I-DK Discovery board: - 4 user LEDs - User and reset push-buttons -.. image:: img/stm32h573i_dk.jpg - :align: center - :alt: STM32H573I-DK Discovery - More information about the board can be found at the `STM32H573I-DK Discovery website`_. Hardware @@ -199,7 +192,8 @@ hardware features: +-----------+------------+-------------------------------------+ | RTC | on-chip | rtc | +-----------+------------+-------------------------------------+ - +| ETHERNET | on-chip | ethernet | ++-----------+------------+-------------------------------------+ Other hardware features are not yet supported on this Zephyr port. diff --git a/boards/st/stm32h573i_dk/stm32h573i_dk.dts b/boards/st/stm32h573i_dk/stm32h573i_dk.dts index c64ff945106..97664d80eba 100644 --- a/boards/st/stm32h573i_dk/stm32h573i_dk.dts +++ b/boards/st/stm32h573i_dk/stm32h573i_dk.dts @@ -237,9 +237,11 @@ }; &adc1 { + clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000400>, + <&rcc STM32_SRC_HCLK ADCDAC_SEL(0)>; pinctrl-0 = <&adc1_inp6_pf12>; /* Arduino A5 */ pinctrl-names = "default"; - st,adc-clock-source = ; + st,adc-clock-source = "ASYNC"; st,adc-prescaler = <6>; status = "okay"; }; diff --git a/boards/st/stm32h573i_dk/stm32h573i_dk.yaml b/boards/st/stm32h573i_dk/stm32h573i_dk.yaml index 35802081879..39425b9e0f4 100644 --- a/boards/st/stm32h573i_dk/stm32h573i_dk.yaml +++ b/boards/st/stm32h573i_dk/stm32h573i_dk.yaml @@ -22,7 +22,6 @@ supported: - octospi - can - usb_device - - usb - i2c - rtc - usbd diff --git a/boards/st/stm32h735g_disco/doc/index.rst b/boards/st/stm32h735g_disco/doc/index.rst index 3ec250bb4e8..919451922dc 100644 --- a/boards/st/stm32h735g_disco/doc/index.rst +++ b/boards/st/stm32h735g_disco/doc/index.rst @@ -1,7 +1,4 @@ -.. _stm32h735g_disco_board: - -ST STM32H735G Discovery -####################### +.. zephyr:board:: stm32h735g_disco Overview ******** @@ -27,10 +24,6 @@ programmer for the STM32 MCU and USB Virtual COM port bridge. STM32H735G-DK boar comes with the STM32CubeH7 MCU Package, which provides an STM32 comprehensive software HAL library as well as various software examples. -.. image:: img/stm32h735g_disco.jpg - :align: center - :alt: STM32H735G-DISCO - More information about the board can be found at the `STM32H735G-DISCO website`_. More information about STM32H735 can be found here: diff --git a/boards/st/stm32h735g_disco/stm32h735g_disco.dts b/boards/st/stm32h735g_disco/stm32h735g_disco.dts index af351902869..0dc2d17f93d 100644 --- a/boards/st/stm32h735g_disco/stm32h735g_disco.dts +++ b/boards/st/stm32h735g_disco/stm32h735g_disco.dts @@ -124,7 +124,7 @@ &adc1 { pinctrl-0 = <&adc1_inp0_pa0_c>; pinctrl-names = "default"; - st,adc-clock-source = ; + st,adc-clock-source = "SYNC"; st,adc-prescaler = <4>; status = "okay"; }; diff --git a/boards/st/stm32h745i_disco/Kconfig.defconfig b/boards/st/stm32h745i_disco/Kconfig.defconfig index b6242139bfd..1788447e060 100644 --- a/boards/st/stm32h745i_disco/Kconfig.defconfig +++ b/boards/st/stm32h745i_disco/Kconfig.defconfig @@ -1,6 +1,6 @@ # STM32H745XI DISCOVERY board configuration -# Copyright (c) 2020 Alexander Kozhinov +# Copyright (c) 2020 Alexander Kozhinov # Copyright (c) 2024 Tomas Jurena # SPDX-License-Identifier: Apache-2.0 @@ -14,6 +14,10 @@ config NET_L2_ETHERNET config ETH_STM32_HAL_MII default y +# STM32H745I-DISCO have PHY connected to address 1 +config ETH_STM32_HAL_PHY_ADDRESS + default 1 + endif # NETWORKING config MEMC diff --git a/boards/st/stm32h745i_disco/Kconfig.stm32h745i_disco b/boards/st/stm32h745i_disco/Kconfig.stm32h745i_disco index 7dacd75eb4b..d8fdf600ee2 100644 --- a/boards/st/stm32h745i_disco/Kconfig.stm32h745i_disco +++ b/boards/st/stm32h745i_disco/Kconfig.stm32h745i_disco @@ -1,6 +1,6 @@ # STM32H745XI DISCOVERY board configuration -# Copyright (c) 2020 Alexander Kozhinov +# Copyright (c) 2020 Alexander Kozhinov # Copyright (c) 2024 Tomas Jurena # SPDX-License-Identifier: Apache-2.0 diff --git a/boards/st/stm32h745i_disco/arduino_r3_connector.dtsi b/boards/st/stm32h745i_disco/arduino_r3_connector.dtsi index 1d24b1ecb74..4a30db3ffe3 100644 --- a/boards/st/stm32h745i_disco/arduino_r3_connector.dtsi +++ b/boards/st/stm32h745i_disco/arduino_r3_connector.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020 Alexander Kozhinov + * Copyright (c) 2020 Alexander Kozhinov * Copyright (c) 2024 Tomas Jurena * * SPDX-License-Identifier: Apache-2.0 diff --git a/boards/st/stm32h745i_disco/board.cmake b/boards/st/stm32h745i_disco/board.cmake index ae99e34ce51..d9453fbb534 100644 --- a/boards/st/stm32h745i_disco/board.cmake +++ b/boards/st/stm32h745i_disco/board.cmake @@ -1,5 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -# Copyright (c) 2020 Alexander Kozhinov +# Copyright (c) 2020 Alexander Kozhinov # Copyright (c) 2024 Tomas Jurena # keep first diff --git a/boards/st/stm32h745i_disco/doc/index.rst b/boards/st/stm32h745i_disco/doc/index.rst index c5b0ef79276..24dab98ae4c 100644 --- a/boards/st/stm32h745i_disco/doc/index.rst +++ b/boards/st/stm32h745i_disco/doc/index.rst @@ -1,7 +1,4 @@ -.. _stm32h745i_disco_board: - -ST STM32H745I Discovery -####################### +.. zephyr:board:: stm32h745i_disco Overview ******** @@ -53,10 +50,6 @@ Key Features - USB charger - USB power -.. image:: img/stm32h745i-disco.jpg - :align: center - :alt: STM32H745I-DISCO - More information about the board can be found at the `STM32H745I-DISCO website`_. More information about STM32H747XIH6 can be found here: diff --git a/boards/st/stm32h745i_disco/stm32h745i_disco.dtsi b/boards/st/stm32h745i_disco/stm32h745i_disco.dtsi index c196018316c..86be45c4f33 100644 --- a/boards/st/stm32h745i_disco/stm32h745i_disco.dtsi +++ b/boards/st/stm32h745i_disco/stm32h745i_disco.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020 Alexander Kozhinov + * Copyright (c) 2020 Alexander Kozhinov * Copyright (c) 2024 Tomas Jurena * * SPDX-License-Identifier: Apache-2.0 diff --git a/boards/st/stm32h745i_disco/stm32h745i_disco_stm32h745xx_m4.dts b/boards/st/stm32h745i_disco/stm32h745i_disco_stm32h745xx_m4.dts index fe16637e5ef..7f46637f575 100644 --- a/boards/st/stm32h745i_disco/stm32h745i_disco_stm32h745xx_m4.dts +++ b/boards/st/stm32h745i_disco/stm32h745i_disco_stm32h745xx_m4.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020 Alexander Kozhinov + * Copyright (c) 2020 Alexander Kozhinov * Copyright (c) 2024 Tomas Jurena * * SPDX-License-Identifier: Apache-2.0 diff --git a/boards/st/stm32h745i_disco/stm32h745i_disco_stm32h745xx_m4_defconfig b/boards/st/stm32h745i_disco/stm32h745i_disco_stm32h745xx_m4_defconfig index e2c6b592151..ad60e4956a1 100644 --- a/boards/st/stm32h745i_disco/stm32h745i_disco_stm32h745xx_m4_defconfig +++ b/boards/st/stm32h745i_disco/stm32h745i_disco_stm32h745xx_m4_defconfig @@ -1,5 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -# Copyright (c) 2020 Alexander Kozhinov +# Copyright (c) 2020 Alexander Kozhinov # Copyright (c) 2024 Tomas Jurena # Enable GPIO diff --git a/boards/st/stm32h745i_disco/stm32h745i_disco_stm32h745xx_m7.dts b/boards/st/stm32h745i_disco/stm32h745i_disco_stm32h745xx_m7.dts index ba2f771cfbf..f1e7204a864 100644 --- a/boards/st/stm32h745i_disco/stm32h745i_disco_stm32h745xx_m7.dts +++ b/boards/st/stm32h745i_disco/stm32h745i_disco_stm32h745xx_m7.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020 Alexander Kozhinov + * Copyright (c) 2020 Alexander Kozhinov * Copyright (c) 2024 Tomas Jurena * * SPDX-License-Identifier: Apache-2.0 @@ -151,9 +151,9 @@ pinctrl-0 = <ð_mdio_pa2 ð_mdc_pc1>; pinctrl-names = "default"; - ethernet-phy@0 { + ethernet-phy@1 { compatible = "ethernet-phy"; - reg = <0x00>; + reg = <0x01>; status = "okay"; }; }; @@ -224,8 +224,6 @@ pinctrl-names = "default"; clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000100>, <&rcc STM32_SRC_PLL2_Q FDCAN_SEL(2)>; - sample-point = <875>; - sample-point-data = <875>; can-transceiver { max-bitrate = <5000000>; @@ -238,8 +236,6 @@ pinctrl-names = "default"; clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000100>, <&rcc STM32_SRC_PLL2_Q FDCAN_SEL(2)>; - sample-point = <875>; - sample-point-data = <875>; can-transceiver { max-bitrate = <5000000>; diff --git a/boards/st/stm32h745i_disco/stm32h745i_disco_stm32h745xx_m7_defconfig b/boards/st/stm32h745i_disco/stm32h745i_disco_stm32h745xx_m7_defconfig index 1ad6ad9133d..bc7dfd35826 100644 --- a/boards/st/stm32h745i_disco/stm32h745i_disco_stm32h745xx_m7_defconfig +++ b/boards/st/stm32h745i_disco/stm32h745i_disco_stm32h745xx_m7_defconfig @@ -1,5 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -# Copyright (c) 2020 Alexander Kozhinov +# Copyright (c) 2020 Alexander Kozhinov # Copyright (c) 2024 Tomas Jurena # Enable the internal SMPS regulator diff --git a/boards/st/stm32h745i_disco/support/openocd.cfg b/boards/st/stm32h745i_disco/support/openocd.cfg index cd2f2e5753b..562cdf84339 100644 --- a/boards/st/stm32h745i_disco/support/openocd.cfg +++ b/boards/st/stm32h745i_disco/support/openocd.cfg @@ -1,6 +1,6 @@ # STM32H745XI DISCOVERY board OpenOCD ST-LINK V3 configuration # -# Copyright (c) 2020 Alexander Kozhinov +# Copyright (c) 2020 Alexander Kozhinov # Copyright (c) 2024 Tomas Jurena # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/st/stm32h747i_disco/CMakeLists.txt b/boards/st/stm32h747i_disco/CMakeLists.txt index 2f480bd7966..76017297389 100644 --- a/boards/st/stm32h747i_disco/CMakeLists.txt +++ b/boards/st/stm32h747i_disco/CMakeLists.txt @@ -5,5 +5,5 @@ # # Add custom linker section to relocate framebuffers to PSRAM -zephyr_linker_sources_ifdef(CONFIG_LV_Z_VBD_CUSTOM_SECTION +zephyr_linker_sources_ifdef(CONFIG_LV_Z_VDB_CUSTOM_SECTION SECTIONS dc_ram.ld) diff --git a/boards/st/stm32h747i_disco/doc/index.rst b/boards/st/stm32h747i_disco/doc/index.rst index 4f7a345ccc4..8d61400060a 100644 --- a/boards/st/stm32h747i_disco/doc/index.rst +++ b/boards/st/stm32h747i_disco/doc/index.rst @@ -1,7 +1,4 @@ -.. _stm32h747i_disco_board: - -ST STM32H747I Discovery -####################### +.. zephyr:board:: stm32h747i_disco Overview ******** @@ -34,10 +31,6 @@ Additionally, the board features: - 4-direction joystick with selection button - Arduino Uno V3 connectors -.. image:: img/stm32h747i_disco.jpg - :align: center - :alt: STM32H747I-DISCO - More information about the board can be found at the `STM32H747I-DISCO website`_. More information about STM32H747XIH6 can be found here: diff --git a/boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m7.dts b/boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m7.dts index 9feb49e0987..b5b0ee1cd88 100644 --- a/boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m7.dts +++ b/boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m7.dts @@ -278,3 +278,17 @@ zephyr_udc0: &usbotg_hs { }; arduino_spi: &spi5 {}; + +/* alias used by display shields with touch control */ +qsh_030_i2c: &i2c4 { + pinctrl-0 = <&i2c4_scl_pd12 &i2c4_sda_pd13>; + pinctrl-names = "default"; + clock-frequency = ; + status = "okay"; +}; + +/* alias used by display shields */ +zephyr_mipi_dsi: &mipi_dsi {}; + +/* alias used by LCD display shields */ +zephyr_lcd_controller: <dc {}; diff --git a/boards/st/stm32h750b_dk/arduino_r3_connector.dtsi b/boards/st/stm32h750b_dk/arduino_r3_connector.dtsi index d5b1e520459..40ed77d4adf 100644 --- a/boards/st/stm32h750b_dk/arduino_r3_connector.dtsi +++ b/boards/st/stm32h750b_dk/arduino_r3_connector.dtsi @@ -34,3 +34,5 @@ <21 0 &gpiod 12 0>; /* D15 */ }; }; + +arduino_serial: &usart1 {}; diff --git a/boards/st/stm32h750b_dk/doc/index.rst b/boards/st/stm32h750b_dk/doc/index.rst index 3e2cd3d009e..8dacd802075 100644 --- a/boards/st/stm32h750b_dk/doc/index.rst +++ b/boards/st/stm32h750b_dk/doc/index.rst @@ -1,7 +1,4 @@ -.. _stm32h750b_dk_board: - -ST STM32H750B Discovery Kit -########################### +.. zephyr:board:: stm32h750b_dk Overview ******** @@ -27,10 +24,6 @@ programmer for the STM32 MCU and USB Virtual COM port bridge. STM32H750B-DK boar comes with the STM32CubeH7 MCU Package, which provides an STM32 comprehensive software HAL library as well as various software examples. -.. image:: img/stm32h750b_dk.png - :align: center - :alt: STM32H750B-DK - More information about the board can be found at the `STM32H750B-DK website`_. More information about STM32H750 can be found here: @@ -59,7 +52,14 @@ The current Zephyr stm32h750b_dk board configuration supports the following hard +-----------+------------+-------------------------------------+ | RTC | on-chip | rtc | +-----------+------------+-------------------------------------+ - +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| LTDC | on-chip | display | ++-----------+------------+-------------------------------------+ +| QSPI NOR | on-chip | off-chip flash | ++-----------+------------+-------------------------------------+ +| FMC | on-chip | memc (SDRAM) | ++-----------+------------+-------------------------------------+ Other hardware features are not yet supported on Zephyr porting. @@ -77,6 +77,7 @@ Default Zephyr Peripheral Mapping: - UART_3 TX/RX : PB10/PB11 (ST-Link Virtual Port Com) - LD1 : PJ2 - LD2 : PI13 +- USART1 TX/RX : PB6/PB7 (Arduino D1/D0) System Clock ============ @@ -96,12 +97,29 @@ COM port interface. Default communication settings are 115200 8N1. Programming and Debugging ************************* +STM32H750B Discovery kit includes an ST-LINK-V3E embedded debug tool interface. +This probe allows flashing and debugging the board using various tools. + See :ref:`build_an_application` for more information about application builds. Flashing ======== +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. + +Alternatively, OpenOCD or JLink can also be used to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner openocd + $ west flash --runner jlink + +Flashing an application to STM32H750B_DK +---------------------------------------- + Connect the STM32H750B-DK to your host computer using the ST-LINK USB port, then run a serial host program to connect with the board. For example: @@ -147,3 +165,6 @@ You can debug an application in the usual way. Here is an example for the .. _STM32H750xx datasheet: https://www.st.com/resource/en/datasheet/stm32h750ib.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/st/stm32h750b_dk/stm32h750b_dk.dts b/boards/st/stm32h750b_dk/stm32h750b_dk.dts index 14a6fe1fef1..b5c9189288b 100644 --- a/boards/st/stm32h750b_dk/stm32h750b_dk.dts +++ b/boards/st/stm32h750b_dk/stm32h750b_dk.dts @@ -239,7 +239,17 @@ }; &adc3 { - st,adc-clock-source = ; + st,adc-clock-source = "SYNC"; st,adc-prescaler = <4>; status = "okay"; }; + +/* Arduino Header pins: Tx:D1, Rx:D0 */ +/* LPUART1 can also be used with this pins */ +&usart1 { + dma-names = "tx", "rx"; + pinctrl-0 = <&usart1_tx_pb6 &usart1_rx_pb7>; + pinctrl-names = "default"; + current-speed = <115200>; + status = "okay"; +}; diff --git a/boards/st/stm32h750b_dk/stm32h750b_dk.yaml b/boards/st/stm32h750b_dk/stm32h750b_dk.yaml index 2ef5ca14dcd..da7d087b060 100644 --- a/boards/st/stm32h750b_dk/stm32h750b_dk.yaml +++ b/boards/st/stm32h750b_dk/stm32h750b_dk.yaml @@ -15,4 +15,6 @@ supported: - flash - rtc - memc + - display + - spi vendor: st diff --git a/boards/st/stm32h7b3i_dk/CMakeLists.txt b/boards/st/stm32h7b3i_dk/CMakeLists.txt index 6edbccee55c..67def763643 100644 --- a/boards/st/stm32h7b3i_dk/CMakeLists.txt +++ b/boards/st/stm32h7b3i_dk/CMakeLists.txt @@ -5,5 +5,5 @@ # # Add custom linker section to relocate framebuffers to PSRAM -zephyr_linker_sources_ifdef(CONFIG_LV_Z_VBD_CUSTOM_SECTION +zephyr_linker_sources_ifdef(CONFIG_LV_Z_VDB_CUSTOM_SECTION SECTIONS dc_ram.ld) diff --git a/boards/st/stm32h7b3i_dk/Kconfig.defconfig b/boards/st/stm32h7b3i_dk/Kconfig.defconfig index 863570e555a..37932189b7c 100644 --- a/boards/st/stm32h7b3i_dk/Kconfig.defconfig +++ b/boards/st/stm32h7b3i_dk/Kconfig.defconfig @@ -22,10 +22,10 @@ if LVGL config CACHE_MANAGEMENT default y -config LV_USE_GPU_STM32_DMA2D +config LV_USE_DRAW_DMA2D default y -config LV_GPU_DMA2D_CMSIS_INCLUDE +config LV_DRAW_DMA2D_HAL_INCLUDE default "stm32h7xx.h" config STM32_LTDC_FB_NUM @@ -40,7 +40,7 @@ config LV_Z_DOUBLE_VDB config LV_Z_FULL_REFRESH default y -config LV_Z_VBD_CUSTOM_SECTION +config LV_Z_VDB_CUSTOM_SECTION default y config LV_Z_FLUSH_THREAD diff --git a/boards/st/stm32h7b3i_dk/doc/index.rst b/boards/st/stm32h7b3i_dk/doc/index.rst index 954f4342d56..e5ad38f4c2b 100644 --- a/boards/st/stm32h7b3i_dk/doc/index.rst +++ b/boards/st/stm32h7b3i_dk/doc/index.rst @@ -1,7 +1,4 @@ -.. _stm32h7b3i_dk_board: - -ST STM32H7B3I Discovery kit -########################### +.. zephyr:board:: stm32h7b3i_dk Overview ******** @@ -50,10 +47,6 @@ Important board features include: - ST-LINK USB VBUS, USB OTG HS connector, or external sources - On-board STLINK-V3E debugger/programmer with USB re-enumeration capability -.. image:: img/stm32h7b3i_dk.jpg - :align: center - :alt: STM32H7B3I-DK - More information about the board can be found at the `STM32H7B3I-DK website`_. Hardware diff --git a/boards/st/stm32h7b3i_dk/stm32h7b3i_dk.dts b/boards/st/stm32h7b3i_dk/stm32h7b3i_dk.dts index 95325e254b5..7e4fe7f9c2d 100644 --- a/boards/st/stm32h7b3i_dk/stm32h7b3i_dk.dts +++ b/boards/st/stm32h7b3i_dk/stm32h7b3i_dk.dts @@ -22,6 +22,7 @@ zephyr,flash = &flash0; zephyr,display = <dc; zephyr,canbus = &fdcan1; + zephyr,touch = &ft5336; }; leds { diff --git a/boards/st/stm32h7s78_dk/doc/index.rst b/boards/st/stm32h7s78_dk/doc/index.rst index 2352fde0fc9..430b3d9dd0e 100644 --- a/boards/st/stm32h7s78_dk/doc/index.rst +++ b/boards/st/stm32h7s78_dk/doc/index.rst @@ -1,7 +1,4 @@ -.. _stm32h7s78_dk_board: - -ST STM32H7S78-DK Discovery -########################## +.. zephyr:board:: stm32h7s78_dk Overview ******** @@ -41,10 +38,6 @@ the STM32H7S78-DK Discovery board: - 4 user LEDs - User and reset push-buttons -.. image:: img/stm32h7s78_dk.jpg - :align: center - :alt: STM32H7S78-DK Discovery - More information about the board can be found at the `STM32H7S78-DK Discovery website`_. Hardware diff --git a/boards/st/stm32h7s78_dk/stm32h7s78_dk.dts b/boards/st/stm32h7s78_dk/stm32h7s78_dk.dts index 6cd70cbe60d..e4192d41641 100644 --- a/boards/st/stm32h7s78_dk/stm32h7s78_dk.dts +++ b/boards/st/stm32h7s78_dk/stm32h7s78_dk.dts @@ -148,7 +148,7 @@ &adc1 { pinctrl-0 = <&adc1_inp6_pf12>; /* Arduino A3 */ pinctrl-names = "default"; - st,adc-clock-source = ; + st,adc-clock-source = "SYNC"; st,adc-prescaler = <4>; status = "okay"; }; @@ -156,7 +156,7 @@ &adc2 { pinctrl-0 = <&adc2_inp2_pf13>; /* Arduino A4 */ pinctrl-names = "default"; - st,adc-clock-source = ; + st,adc-clock-source = "SYNC"; st,adc-prescaler = <4>; status = "okay"; }; diff --git a/boards/st/stm32l1_disco/doc/index.rst b/boards/st/stm32l1_disco/doc/index.rst index 20d6067b966..6954625564b 100644 --- a/boards/st/stm32l1_disco/doc/index.rst +++ b/boards/st/stm32l1_disco/doc/index.rst @@ -1,7 +1,4 @@ -.. _stm32l1_disco_board: - -ST STM32L1 Discovery -#################### +.. zephyr:board:: stm32l1_disco Overview ******** @@ -24,10 +21,6 @@ stm32l1_disco configuration enables support for STM32LDISCOVERY board and stm32l152c_disco configuration enables support for STM32L152CDISCOVERY board. -.. image:: img/stm32l1_disco.jpg - :align: center - :alt: STM32LDISCOVERY - More information about the board can be found at the `STM32LDISCOVERY website`_. Hardware diff --git a/boards/st/stm32l476g_disco/doc/index.rst b/boards/st/stm32l476g_disco/doc/index.rst index 94a6e9ce24f..00c7fdc45d4 100644 --- a/boards/st/stm32l476g_disco/doc/index.rst +++ b/boards/st/stm32l476g_disco/doc/index.rst @@ -1,7 +1,4 @@ -.. _stm32l476g_disco_board: - -ST STM32L476G Discovery -####################### +.. zephyr:board:: stm32l476g_disco Overview ******** @@ -42,10 +39,6 @@ some highlights of the STM32L476G Discovery board: - External 5 V - CR2032 battery (not provided) -.. image:: img/stm32l476g_disco.jpg - :align: center - :alt: STM32L476G Discovery - More information about the board can be found at the `STM32L476G Discovery website`_. Hardware diff --git a/boards/st/stm32l496g_disco/doc/index.rst b/boards/st/stm32l496g_disco/doc/index.rst index 15461fb1a71..ce91d694043 100644 --- a/boards/st/stm32l496g_disco/doc/index.rst +++ b/boards/st/stm32l496g_disco/doc/index.rst @@ -1,7 +1,4 @@ -.. _stm32l496g_disco_board: - -ST STM32L496G Discovery -####################### +.. zephyr:board:: stm32l496g_disco Overview ******** @@ -41,10 +38,6 @@ some highlights of the STM32L496G Discovery board: - Reset push button - 4 direction-joystick with selection -.. image:: img/stm32l496g_disco.jpg - :align: center - :alt: STM32L496G Discovery - More information about the board can be found at the `STM32L496G Discovery website`_. Hardware diff --git a/boards/st/stm32l496g_disco/stm32l496g_disco.dts b/boards/st/stm32l496g_disco/stm32l496g_disco.dts index a6d1e876f4e..9027656636a 100644 --- a/boards/st/stm32l496g_disco/stm32l496g_disco.dts +++ b/boards/st/stm32l496g_disco/stm32l496g_disco.dts @@ -164,7 +164,7 @@ &adc1 { pinctrl-0 = < &adc1_in2_pc1>; pinctrl-names = "default"; - st,adc-clock-source = ; + st,adc-clock-source = "SYNC"; st,adc-prescaler = <4>; status = "okay"; }; diff --git a/boards/st/stm32l496g_disco/stm32l496g_disco.yaml b/boards/st/stm32l496g_disco/stm32l496g_disco.yaml index 15301e002c7..e6b153cb0e4 100644 --- a/boards/st/stm32l496g_disco/stm32l496g_disco.yaml +++ b/boards/st/stm32l496g_disco/stm32l496g_disco.yaml @@ -6,7 +6,7 @@ toolchain: - zephyr - gnuarmemb - xtools -ram: 320 +ram: 256 flash: 1024 supported: - arduino_i2c diff --git a/boards/st/stm32l4r9i_disco/doc/index.rst b/boards/st/stm32l4r9i_disco/doc/index.rst index 6fadc331d45..0b5b992c059 100644 --- a/boards/st/stm32l4r9i_disco/doc/index.rst +++ b/boards/st/stm32l4r9i_disco/doc/index.rst @@ -1,7 +1,4 @@ -.. _stm32l4r9i_disco_board: - -ST STM32L4R9I Discovery -####################### +.. zephyr:board:: stm32l4r9i_disco Overview ******** @@ -18,10 +15,6 @@ support for AMOLED DSI round LCD display. For even more user-friendliness, the on-board ST-LINK/V2-1 debugger provides out-of-the-box programming and debugging capabilities. -.. image:: img/stm32l4r9i_disco.jpg - :align: center - :alt: STM32L4R9I-DISCO - More information about the board can be found at the `STM32L4R9I-DISCOVERY website`_. More information about STM32L4R9 can be found here: diff --git a/boards/st/stm32l4r9i_disco/stm32l4r9i_disco.dts b/boards/st/stm32l4r9i_disco/stm32l4r9i_disco.dts index 49737c68c8f..27cfdb2f0a7 100644 --- a/boards/st/stm32l4r9i_disco/stm32l4r9i_disco.dts +++ b/boards/st/stm32l4r9i_disco/stm32l4r9i_disco.dts @@ -190,7 +190,7 @@ pinctrl-0 = <&adc1_in5_pa0 &adc1_in12_pa7 &adc1_in15_pb0 &adc1_in4_pc3 &adc1_in13_pc4>; pinctrl-names = "default"; - st,adc-clock-source = ; + st,adc-clock-source = "SYNC"; st,adc-prescaler = <1>; }; diff --git a/boards/st/stm32l4r9i_disco/stm32l4r9i_disco.yaml b/boards/st/stm32l4r9i_disco/stm32l4r9i_disco.yaml index 81d844caf75..3b4ef674d84 100644 --- a/boards/st/stm32l4r9i_disco/stm32l4r9i_disco.yaml +++ b/boards/st/stm32l4r9i_disco/stm32l4r9i_disco.yaml @@ -6,7 +6,7 @@ toolchain: - zephyr - gnuarmemb - xtools -ram: 640 +ram: 192 flash: 2048 vendor: st supported: @@ -20,5 +20,4 @@ supported: - rtc - spi - uart - - usb - usb_device diff --git a/boards/st/stm32l562e_dk/Kconfig.defconfig b/boards/st/stm32l562e_dk/Kconfig.defconfig index b0dc8f3bab8..154a875da56 100644 --- a/boards/st/stm32l562e_dk/Kconfig.defconfig +++ b/boards/st/stm32l562e_dk/Kconfig.defconfig @@ -7,12 +7,6 @@ if BOARD_STM32L562E_DK if BT -config SPI - default y - -config BT_SPI - default y - config BT_BLUENRG_ACI default y @@ -36,4 +30,26 @@ endchoice endif # DISPLAY +if BUILD_WITH_TFM + +# Not defining LIBC malloc arena has the effect of declaring all available RAM +# as available for malloc. +# This currently conflicts with TF-M MPU setting, resulting in a hard fault. +# Define a specific size to avoid this situation. + +config COMMON_LIBC_MALLOC_ARENA_SIZE + default 2048 + +endif # BUILD_WITH_TFM + +config INPUT + default y if LVGL + +if INPUT + +config INPUT_FT5336_INTERRUPT + default y + +endif # INPUT + endif # BOARD_STM32L562E_DK diff --git a/boards/st/stm32l562e_dk/doc/index.rst b/boards/st/stm32l562e_dk/doc/index.rst index 55fd91a34fa..4e159971936 100644 --- a/boards/st/stm32l562e_dk/doc/index.rst +++ b/boards/st/stm32l562e_dk/doc/index.rst @@ -1,7 +1,4 @@ -.. _stm32l562e_dk_board: - -ST STM32L562E-DK Discovery -########################## +.. zephyr:board:: stm32l562e_dk Overview ******** @@ -43,10 +40,6 @@ the STM32L562E-DK Discovery board: - 2 user LEDs - User and reset push-buttons -.. image:: img/stm32l562e_dk.jpg - :align: center - :alt: STM32L562E-DK Discovery - More information about the board can be found at the `STM32L562E-DK Discovery website`_. Hardware @@ -160,6 +153,9 @@ hardware features: +-----------+------------+-------------------------------------+ | DAC | on-chip | DAC Controller | +-----------+------------+-------------------------------------+ +| DISPLAY | on-chip | TFT LCD screen with st7789v driver | +| | | and touch panel with ft5336 driver | ++-----------+------------+-------------------------------------+ | DMA | on-chip | Direct Memory Access | +-----------+------------+-------------------------------------+ | GPIO | on-chip | gpio | @@ -280,6 +276,16 @@ Serial Port STM32L562E-DK Discovery board has 6 U(S)ARTs. The Zephyr console output is assigned to USART1. Default settings are 115200 8N1. +TFT LCD screen and touch panel +------------------------------ + +The TFT LCD screen and touch panel are supported for the STM32L562E-DK Discovery board. +They can be tested using :zephyr:code-sample:`lvgl` sample: + +.. zephyr-app-commands:: + :zephyr-app: samples/subsys/display/lvgl + :board: stm32l562e_dk + :goals: build Programming and Debugging ************************* diff --git a/boards/st/stm32l562e_dk/stm32l562e_dk.yaml b/boards/st/stm32l562e_dk/stm32l562e_dk.yaml index cad386fb4f3..1703d4c9933 100644 --- a/boards/st/stm32l562e_dk/stm32l562e_dk.yaml +++ b/boards/st/stm32l562e_dk/stm32l562e_dk.yaml @@ -19,7 +19,6 @@ supported: - dma - usart - arduino_spi - - usb - usb_device - nvs - usbd diff --git a/boards/st/stm32l562e_dk/stm32l562e_dk_common.dtsi b/boards/st/stm32l562e_dk/stm32l562e_dk_common.dtsi index f80159110e3..47c678db786 100644 --- a/boards/st/stm32l562e_dk/stm32l562e_dk_common.dtsi +++ b/boards/st/stm32l562e_dk/stm32l562e_dk_common.dtsi @@ -42,6 +42,12 @@ chosen { zephyr,bt-hci = &hci_spi; }; + + lvgl_pointer { + compatible = "zephyr,lvgl-pointer-input"; + input = <&ft5336>; + invert-y; + }; }; &fmc { @@ -87,7 +93,7 @@ st7789v: lcd-panel@0 { compatible = "sitronix,st7789v"; reg = <0>; - mipi-mode = ; + mipi-mode = "MIPI_DBI_MODE_8080_BUS_16_BIT"; /* A write cycle should be 68ns */ mipi-max-frequency = <14705882>; width = <240>; @@ -177,6 +183,13 @@ stm32_lp_tick_source: &lptim1 { reg = <0x6a>; irq-gpios = <&gpiof 3 GPIO_ACTIVE_HIGH>; }; + + ft5336: ft5336@38 { + compatible = "focaltech,ft5336"; + reg = <0x38>; + int-gpios = <&gpiof 1 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpiof 15 GPIO_ACTIVE_LOW>; + }; }; &rng { @@ -277,7 +290,7 @@ stm32_lp_tick_source: &lptim1 { &adc1 { pinctrl-0 = <&adc1_in13_pc4>; pinctrl-names = "default"; - st,adc-clock-source = ; + st,adc-clock-source = "SYNC"; st,adc-prescaler = <4>; status = "okay"; }; diff --git a/boards/st/stm32l562e_dk/stm32l562e_dk_stm32l562xx_ns.yaml b/boards/st/stm32l562e_dk/stm32l562e_dk_stm32l562xx_ns.yaml index 50d239c805b..e6596ddacbe 100644 --- a/boards/st/stm32l562e_dk/stm32l562e_dk_stm32l562xx_ns.yaml +++ b/boards/st/stm32l562e_dk/stm32l562e_dk_stm32l562xx_ns.yaml @@ -13,7 +13,6 @@ supported: - dac - spi - arduino_spi - - usb - usb_device ram: 192 flash: 512 diff --git a/boards/st/stm32mp157c_dk2/doc/stm32mp157_dk2.rst b/boards/st/stm32mp157c_dk2/doc/stm32mp157_dk2.rst index f8f9a4869e2..bd649f2e251 100644 --- a/boards/st/stm32mp157c_dk2/doc/stm32mp157_dk2.rst +++ b/boards/st/stm32mp157c_dk2/doc/stm32mp157_dk2.rst @@ -1,7 +1,4 @@ -.. _stm32mp157c_dk2_board: - -ST STM32MP157C-DK2 Discovery -############################ +.. zephyr:board:: stm32mp157c_dk2 Overview ******** @@ -46,10 +43,6 @@ Zephyr OS is ported to run on the Cortex®-M4 core. - Wi-Fi® 802.11b/g/n - Bluetooth® Low Energy 4.1 -.. image:: img/en.stm32mp157c-dk2.jpg - :align: center - :alt: STM32MP157C-DK2 Discovery - More information about the board can be found at the `STM32P157C Discovery website`_. diff --git a/boards/st/stm32mp157c_dk2/stm32mp157c_dk2.yaml b/boards/st/stm32mp157c_dk2/stm32mp157c_dk2.yaml index d552a6d6aa0..91a4aa38fe0 100644 --- a/boards/st/stm32mp157c_dk2/stm32mp157c_dk2.yaml +++ b/boards/st/stm32mp157c_dk2/stm32mp157c_dk2.yaml @@ -18,7 +18,6 @@ testing: - cmsis_rtos_v2 - net - mpu - - tinycrypt - crypto - aes - cmm diff --git a/boards/st/stm32u083c_dk/arduino_r3_connector.dtsi b/boards/st/stm32u083c_dk/arduino_r3_connector.dtsi index 297fd9b7f18..f2b85867b89 100644 --- a/boards/st/stm32u083c_dk/arduino_r3_connector.dtsi +++ b/boards/st/stm32u083c_dk/arduino_r3_connector.dtsi @@ -36,3 +36,4 @@ }; arduino_serial: &usart2 {}; +arduino_i2c: &i2c1 {}; diff --git a/boards/st/stm32u083c_dk/board.cmake b/boards/st/stm32u083c_dk/board.cmake index a274ab952ee..10df49ddf0e 100644 --- a/boards/st/stm32u083c_dk/board.cmake +++ b/boards/st/stm32u083c_dk/board.cmake @@ -1,9 +1,11 @@ +# keep first board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") board_runner_args(pyocd "--target=stm32u083mctx") board_runner_args(jlink "--device=STM32U083C-DK" "--reset-after-load") +# keep first include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/stm32u083c_dk/doc/index.rst b/boards/st/stm32u083c_dk/doc/index.rst index 52f419f804a..81ddcf92a1f 100644 --- a/boards/st/stm32u083c_dk/doc/index.rst +++ b/boards/st/stm32u083c_dk/doc/index.rst @@ -1,7 +1,4 @@ -.. _stm32u083c_dk_board: - -ST STM32U083C_DK -################ +.. zephyr:board:: stm32u083c_dk Overview ******** @@ -36,6 +33,8 @@ board: - Touchkey - Temperature sensor +More information about the board can be found at the `STM32U083_DK website`_. + Hardware ******** @@ -159,10 +158,14 @@ The Zephyr stm32u083c_dk board configuration supports the following hardware fea | UART | on-chip | serial port-polling; | | | | serial port-interrupt | +-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ | DAC | on-chip | DAC Controller | +-----------+------------+-------------------------------------+ | I2C | on-chip | i2c | +-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ Other hardware features are not yet supported on this Zephyr port. @@ -238,7 +241,7 @@ This can be done by executing the following commands. Flashing an application to STM32U083C_DK ------------------------------------------- +---------------------------------------- Connect the STM32U083C_DK to your host computer using the USB port. Then build and flash an application. Here is an example for the diff --git a/boards/st/stm32u083c_dk/stm32u083c_dk.dts b/boards/st/stm32u083c_dk/stm32u083c_dk.dts index 05a1485163f..4f340422d51 100644 --- a/boards/st/stm32u083c_dk/stm32u083c_dk.dts +++ b/boards/st/stm32u083c_dk/stm32u083c_dk.dts @@ -72,6 +72,17 @@ apb1-prescaler = <1>; }; +&adc1 { + pinctrl-0 = <&adc1_in0_pc0 &adc1_in1_pc1>; + pinctrl-names = "default"; + st,adc-clock-source = "ASYNC"; + clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00100000>, + <&rcc STM32_SRC_HSI ADC_SEL(2)>; + st,adc-prescaler = <4>; + status = "okay"; + vref-mv = <3300>; +}; + &dac1 { status = "okay"; pinctrl-0 = <&dac1_out1_pa4>; @@ -91,3 +102,25 @@ status = "okay"; clock-frequency = ; }; + +&timers1 { + st,prescaler = <10000>; + status = "okay"; + + pwm1: pwm { + status = "okay"; + pinctrl-0 = <&tim1_ch1_pa8>; + pinctrl-names = "default"; + }; +}; + +&timers2 { + st,prescaler = <10000>; + status = "okay"; + + pwm2: pwm { + pinctrl-0 = <&tim2_ch1_pa5>; + pinctrl-names = "default"; + status = "okay"; + }; +}; diff --git a/boards/st/stm32u083c_dk/stm32u083c_dk.yaml b/boards/st/stm32u083c_dk/stm32u083c_dk.yaml index 615f17f1c8e..3db304b10ef 100644 --- a/boards/st/stm32u083c_dk/stm32u083c_dk.yaml +++ b/boards/st/stm32u083c_dk/stm32u083c_dk.yaml @@ -7,10 +7,14 @@ toolchain: - gnuarmemb - xtools supported: + - adc - arduino_gpio + - arduino_serial + - arduino_i2c - dac - gpio - i2c + - pwm - usart ram: 40 flash: 256 diff --git a/boards/st/stm32u5a9j_dk/doc/index.rst b/boards/st/stm32u5a9j_dk/doc/index.rst index 571ee80f334..0851459c268 100644 --- a/boards/st/stm32u5a9j_dk/doc/index.rst +++ b/boards/st/stm32u5a9j_dk/doc/index.rst @@ -1,7 +1,4 @@ -.. _stm32u5a9j_dk_board: - -ST STM32U5A9J Discovery Kit -########################### +.. zephyr:board:: stm32u5a9j_dk Overview ******** @@ -142,8 +139,18 @@ This probe allows to flash and debug the board using various tools. Flashing ======== -Board is configured to be flashed using west STM32CubeProgrammer runner. -Installation of `STM32CubeProgrammer`_ is then required to flash the board., +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its :ref:`installation ` is required. + +Alternatively, OpenOCD can also be used to flash the board using +the ``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner openocd + +Flashing an application to STM32U5A9J_DK +---------------------------------------- Connect the STM32U5A9J Discovery board to your host computer using the USB port, then run a serial host program to connect with your Discovery diff --git a/boards/st/stm32u5a9j_dk/stm32u5a9j_dk.dts b/boards/st/stm32u5a9j_dk/stm32u5a9j_dk.dts index f8dbb7f8d18..5696253f93c 100644 --- a/boards/st/stm32u5a9j_dk/stm32u5a9j_dk.dts +++ b/boards/st/stm32u5a9j_dk/stm32u5a9j_dk.dts @@ -204,7 +204,7 @@ uart0: &usart3 { &adc1 { pinctrl-0 = <&adc1_in5_pa0 &adc1_in14_pc5>; pinctrl-names = "default"; - st,adc-clock-source = ; + st,adc-clock-source = "ASYNC"; st,adc-prescaler = <1>; status = "okay"; @@ -231,7 +231,7 @@ uart0: &usart3 { &adc4 { pinctrl-0 = <&adc4_in5_pf14>; pinctrl-names = "default"; - st,adc-clock-source = ; + st,adc-clock-source = "ASYNC"; st,adc-prescaler = <1>; status = "okay"; diff --git a/boards/st/stm32vl_disco/doc/index.rst b/boards/st/stm32vl_disco/doc/index.rst index e676e4ab426..a2bb8c8baec 100644 --- a/boards/st/stm32vl_disco/doc/index.rst +++ b/boards/st/stm32vl_disco/doc/index.rst @@ -1,7 +1,4 @@ -.. _stm32vl_disco_board: - -ST STM32VL Discovery -#################### +.. zephyr:board:: stm32vl_disco Overview ******** @@ -11,10 +8,6 @@ Line" STM32F100x SoC series is showcased. Like other Discovery board, an integrated ST-LINK debugger and programmer is included (V1), but the only included I/O devices are two user LEDs and one user button. -.. image:: img/stm32vl_disco.jpg - :align: center - :alt: STM32VLDISCOVERY - More information about the board can be found at the `STM32VLDISCOVERY website`_. Hardware diff --git a/boards/st/stm32wb5mm_dk/doc/stm32wb5mm_dk.rst b/boards/st/stm32wb5mm_dk/doc/stm32wb5mm_dk.rst index 9ee025f45e9..3a7bae73f13 100644 --- a/boards/st/stm32wb5mm_dk/doc/stm32wb5mm_dk.rst +++ b/boards/st/stm32wb5mm_dk/doc/stm32wb5mm_dk.rst @@ -1,7 +1,4 @@ -.. _stm32wb5mm_dk_discovery_kit: - -ST STM32WB5MM-DK -################ +.. zephyr:board:: stm32wb5mm_dk Overview ******** @@ -47,10 +44,6 @@ STM32WB5MM-DK supports the following features: - Virtual COM port and debug port -.. image:: img/STM32WB5MM_DK.jpg - :align: center - :alt: STM32WB5MM-DK - More information about the board can be found in `STM32WB5MM-DK on www.st.com`_. Hardware diff --git a/boards/st/stm32wb5mm_dk/stm32wb5mm_dk.dts b/boards/st/stm32wb5mm_dk/stm32wb5mm_dk.dts index e11ec3f0f20..7395329ca23 100644 --- a/boards/st/stm32wb5mm_dk/stm32wb5mm_dk.dts +++ b/boards/st/stm32wb5mm_dk/stm32wb5mm_dk.dts @@ -111,7 +111,7 @@ &adc1 { pinctrl-0 = <&adc1_in3_pc2>; pinctrl-names = "default"; - st,adc-clock-source = ; + st,adc-clock-source = "SYNC"; st,adc-prescaler = <4>; status = "okay"; }; diff --git a/boards/st/stm32wb5mmg/doc/stm32wb5mmg.rst b/boards/st/stm32wb5mmg/doc/stm32wb5mmg.rst index 7b8ee9f0062..f4f2a34cdd1 100644 --- a/boards/st/stm32wb5mmg/doc/stm32wb5mmg.rst +++ b/boards/st/stm32wb5mmg/doc/stm32wb5mmg.rst @@ -1,7 +1,4 @@ -.. _stm32wb5mmg_bluetooth_module: - -ST STM32WB5MMG -################ +.. zephyr:board:: stm32wb5mmg Overview ******** @@ -33,10 +30,6 @@ STM32WB5MMG supports the following features: - 68 GPIOs - SWD, JTAG -.. image:: img/STM32WB5MMG.jpg - :align: center - :alt: STM32WB5MMG - More information about the board can be found at the `` `STM32WB5MMG on www.st.com`_. Hardware diff --git a/boards/st/stm32wb5mmg/stm32wb5mmg.dts b/boards/st/stm32wb5mmg/stm32wb5mmg.dts index d494b7024dc..29f7de31302 100644 --- a/boards/st/stm32wb5mmg/stm32wb5mmg.dts +++ b/boards/st/stm32wb5mmg/stm32wb5mmg.dts @@ -69,7 +69,7 @@ &adc1 { pinctrl-0 = <&adc1_in3_pc2>; pinctrl-names = "default"; - st,adc-clock-source = ; + st,adc-clock-source = "SYNC"; st,adc-prescaler = <4>; status = "okay"; }; diff --git a/boards/starfive/visionfive2/doc/index.rst b/boards/starfive/visionfive2/doc/index.rst index 98f966f0513..24cebc6021c 100644 --- a/boards/starfive/visionfive2/doc/index.rst +++ b/boards/starfive/visionfive2/doc/index.rst @@ -1,7 +1,4 @@ -.. _visionfive2: - -Starfive VisionFive 2 JH7110 -############################ +.. zephyr:board:: visionfive2 Overview ******** @@ -9,10 +6,6 @@ Overview The StarFive VisionFive 2 is a development board with a StarFive JH7110 multi-core 64bit RISC-V SoC. -.. image:: img/visionfive2.webp - :align: center - :alt: StarFive VisionFive 2 Board - Programming and debugging ************************* diff --git a/boards/tdk/robokit1/Kconfig.defconfig b/boards/tdk/robokit1/Kconfig.defconfig new file mode 100644 index 00000000000..7dccfa805bf --- /dev/null +++ b/boards/tdk/robokit1/Kconfig.defconfig @@ -0,0 +1,18 @@ +# Copyright (c) 2024 Henrik Brix Andersen +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_ROBOKIT1 + +config ADC_ADS7052_INIT_PRIORITY + default 60 + depends on ADC_ADS7052 + +config SENSOR_INIT_PRIORITY + default 60 + depends on SENSOR + +config EEPROM_INIT_PRIORITY + default 60 + depends on EEPROM + +endif # BOARD_ROBOKIT1 diff --git a/boards/tdk/robokit1/doc/index.rst b/boards/tdk/robokit1/doc/index.rst index abc90a0a611..4f674a18861 100644 --- a/boards/tdk/robokit1/doc/index.rst +++ b/boards/tdk/robokit1/doc/index.rst @@ -1,7 +1,4 @@ -.. _robokit1: - -TDK RoboKit 1 -############# +.. zephyr:board:: robokit1 Overview ******** @@ -12,10 +9,6 @@ number of small ground robotics useful sensors including chirp sensors for time It pairs a 300MHz Cortex-M7 ATSAME70Q21 with an array of TDK sensors and pin headers useful for robotics. -.. image:: img/tdk_robokit1.jpg - :align: center - :alt: TDK RoboKit1 - Hardware ******** diff --git a/boards/tdk/robokit1/robokit1.dts b/boards/tdk/robokit1/robokit1.dts index 46d160b2074..7564ccfb5f6 100644 --- a/boards/tdk/robokit1/robokit1.dts +++ b/boards/tdk/robokit1/robokit1.dts @@ -7,7 +7,7 @@ /dts-v1/; -#include +#include #include "robokit1-common.dtsi" diff --git a/boards/technexion/pico_pi/doc/index.rst b/boards/technexion/pico_pi/doc/index.rst index 3b651729227..530bc3a86af 100644 --- a/boards/technexion/pico_pi/doc/index.rst +++ b/boards/technexion/pico_pi/doc/index.rst @@ -1,7 +1,4 @@ -.. _pico_pi: - -Pico-Pi i.MX7D - Android Things IoT Development Platform -############################################################# +.. zephyr:board:: pico_pi Overview ******** @@ -11,11 +8,6 @@ core and Single Cortex M4 core. Zephyr was ported to run on the M4 core. In a later release, it will also communicate with the A7 core (running Linux) via RPmsg. - -.. image:: pico_pi.jpg - :align: center - :alt: Pico-Pi i.MX7D - Hardware ******** diff --git a/boards/technexion/pico_pi/pico_pi_mcimx7d_m4_defconfig b/boards/technexion/pico_pi/pico_pi_mcimx7d_m4_defconfig index a9f1db5c8a7..78568d4528e 100644 --- a/boards/technexion/pico_pi/pico_pi_mcimx7d_m4_defconfig +++ b/boards/technexion/pico_pi/pico_pi_mcimx7d_m4_defconfig @@ -10,4 +10,3 @@ CONFIG_UART_INTERRUPT_DRIVEN=y CONFIG_CONSOLE=y CONFIG_XIP=y CONFIG_GPIO=n -CONFIG_PINCTRL=y diff --git a/boards/telink/tlsr9518adk80d/doc/index.rst b/boards/telink/tlsr9518adk80d/doc/index.rst index 97413403889..27a65a04299 100644 --- a/boards/telink/tlsr9518adk80d/doc/index.rst +++ b/boards/telink/tlsr9518adk80d/doc/index.rst @@ -1,7 +1,4 @@ -.. _tlsr9518adk80d: - -Telink TLSR9518ADK80D -##################### +.. zephyr:board:: tlsr9518adk80d Overview ******** @@ -12,10 +9,6 @@ for several 2.4 GHz air interface standards including Bluetooth 5.2 (Basic data rate, Enhanced data rate, LE, Indoor positioning and BLE Mesh), Zigbee 3.0, Homekit, 6LoWPAN, Thread and 2.4 Ghz proprietary. -.. figure:: img/tlsr9518adk80d.jpg - :align: center - :alt: TLSR9518ADK80D - More information about the board can be found at the `Telink B91 Generic Starter Kit Hardware Guide`_ website. Hardware diff --git a/boards/ti/cc1352p1_launchxl/cc1352p1_launchxl_defconfig b/boards/ti/cc1352p1_launchxl/cc1352p1_launchxl_defconfig index 42ca455ed33..4e65416ca53 100644 --- a/boards/ti/cc1352p1_launchxl/cc1352p1_launchxl_defconfig +++ b/boards/ti/cc1352p1_launchxl/cc1352p1_launchxl_defconfig @@ -16,7 +16,6 @@ CONFIG_CC13X2_CC26X2_BOOTLOADER_BACKDOOR_PIN=15 CONFIG_ARM_MPU=y CONFIG_HW_STACK_PROTECTION=y -CONFIG_PINCTRL=y CONFIG_GPIO=y CONFIG_SERIAL=y diff --git a/boards/ti/cc1352p1_launchxl/doc/index.rst b/boards/ti/cc1352p1_launchxl/doc/index.rst index b751b357307..dc807f55942 100644 --- a/boards/ti/cc1352p1_launchxl/doc/index.rst +++ b/boards/ti/cc1352p1_launchxl/doc/index.rst @@ -1,7 +1,4 @@ -.. _cc1352p1_launchxl: - -CC1352P1 LaunchXL -################# +.. zephyr:board:: cc1352p1_launchxl Overview ******** @@ -11,13 +8,6 @@ development kit for the SimpleLink |trade| multi-Standard CC1352P wireless MCU. See the `TI CC1352P LaunchPad Product Page`_ for details. -.. figure:: img/cc1352p1_launchxl.jpg - :width: 400px - :align: center - :alt: TI CC1352P1 LaunchPad - - Texas Instruments CC1352P1 LaunchPad |trade| - Hardware ******** diff --git a/boards/ti/cc1352p7_launchpad/cc1352p7_lp_defconfig b/boards/ti/cc1352p7_launchpad/cc1352p7_lp_defconfig index 42ca455ed33..4e65416ca53 100644 --- a/boards/ti/cc1352p7_launchpad/cc1352p7_lp_defconfig +++ b/boards/ti/cc1352p7_launchpad/cc1352p7_lp_defconfig @@ -16,7 +16,6 @@ CONFIG_CC13X2_CC26X2_BOOTLOADER_BACKDOOR_PIN=15 CONFIG_ARM_MPU=y CONFIG_HW_STACK_PROTECTION=y -CONFIG_PINCTRL=y CONFIG_GPIO=y CONFIG_SERIAL=y diff --git a/boards/ti/cc1352p7_launchpad/doc/index.rst b/boards/ti/cc1352p7_launchpad/doc/index.rst index 2b7fbc12a2c..6ad90f18e86 100644 --- a/boards/ti/cc1352p7_launchpad/doc/index.rst +++ b/boards/ti/cc1352p7_launchpad/doc/index.rst @@ -1,7 +1,4 @@ -.. _cc1352p7_lp: - -CC1352P7 LaunchPad -################## +.. zephyr:board:: cc1352p7_lp Overview ******** @@ -11,12 +8,6 @@ development kit for the SimpleLink |trade| multi-Standard CC1352P7 wireless MCU. See the `TI CC1352P7 LaunchPad Product Page`_ for details. -.. figure:: img/lp-cc1352p7-top.jpg - :width: 400px - :align: center - :alt: TI CC1352P7 LaunchPad - - Texas Instruments CC1352P7 LaunchPad |trade| Hardware ******** @@ -151,15 +142,20 @@ Prerequisites: #. Install OpenOCD - You can obtain OpenOCD by following these - :ref:`installing the latest Zephyr SDK instructions `. + Currently, OpenOCD doesn't support the CC1352P7. + Until its support get merged, we have to builld a downstream version that could found `here `_. + Please refer to OpenOCD documentation to build and install OpenOCD. - After the installation, add the directory containing the OpenOCD executable - to your environment's PATH variable. For example, use this command in Linux: + For your convenience, we provide a `prebuilt binary `_. + +.. code-block:: console - .. code-block:: console + $ unzip openocd-810cb5b21-x86_64-linux-gnu.zip + $ chmod +x openocd-x86_64-linux-gnu/bin/openocd + $ export OPENOCD_DIST=$PWD/openocd-x86_64-linux-gnu - export PATH=$ZEPHYR_SDK_INSTALL_DIR/sysroots/x86_64-pokysdk-linux/usr/bin/openocd:$PATH +By default, zephyr will try to use the OpenOCD binary from SDK. +You will have to define :code:`OPENOCD` and :code:`OPENOCD_DEFAULT_PATH` to use the custom OpenOCD binary. Flashing ======== @@ -185,6 +181,7 @@ Then build and flash the application in the usual way. :zephyr-app: samples/hello_world :board: cc1352p7_lp :goals: build flash + :gen-args: -DOPENOCD=$OPENOCD_DIST/bin/openocd -DOPENOCD_DEFAULT_PATH=$OPENOCD_DIST/share/openocd Debugging ========= @@ -197,6 +194,7 @@ You can debug an application in the usual way. Here is an example for the :board: cc1352p7_lp :maybe-skip-config: :goals: debug + :gen-args: -DOPENOCD=$OPENOCD_DIST/bin/openocd -DOPENOCD_DEFAULT_PATH=$OPENOCD_DIST/share/openocd Bootloader ========== diff --git a/boards/ti/cc1352p7_launchpad/support/openocd.cfg b/boards/ti/cc1352p7_launchpad/support/openocd.cfg index 8be969b1819..e66d8841104 100644 --- a/boards/ti/cc1352p7_launchpad/support/openocd.cfg +++ b/boards/ti/cc1352p7_launchpad/support/openocd.cfg @@ -1 +1,7 @@ +# Serial could be found using the following command: +# lsusb -d 0451:bef3 -v | grep -i iserial +if { [info exists _ZEPHYR_BOARD_SERIAL] } { + adapter serial $_ZEPHYR_BOARD_SERIAL +} + source [find board/ti_cc26x2x7_launchpad.cfg] diff --git a/boards/ti/cc1352r1_launchxl/cc1352r1_launchxl_defconfig b/boards/ti/cc1352r1_launchxl/cc1352r1_launchxl_defconfig index 872843de16d..3977a366b52 100644 --- a/boards/ti/cc1352r1_launchxl/cc1352r1_launchxl_defconfig +++ b/boards/ti/cc1352r1_launchxl/cc1352r1_launchxl_defconfig @@ -14,7 +14,6 @@ CONFIG_CC13X2_CC26X2_BOOTLOADER_BACKDOOR_PIN=15 CONFIG_ARM_MPU=y CONFIG_HW_STACK_PROTECTION=y -CONFIG_PINCTRL=y CONFIG_GPIO=y CONFIG_SERIAL=y diff --git a/boards/ti/cc1352r1_launchxl/doc/index.rst b/boards/ti/cc1352r1_launchxl/doc/index.rst index 2e7ed0ae2ff..a908e1ceccc 100644 --- a/boards/ti/cc1352r1_launchxl/doc/index.rst +++ b/boards/ti/cc1352r1_launchxl/doc/index.rst @@ -1,7 +1,4 @@ -.. _cc1352r1_launchxl: - -CC1352R1 LaunchXL -################# +.. zephyr:board:: cc1352r1_launchxl Overview ******** @@ -11,12 +8,6 @@ development kit for the SimpleLink |trade| multi-Standard CC1352R wireless MCU. See the `TI CC1352R LaunchPad Product Page`_ for details. -.. figure:: img/cc1352r1_launchxl.jpg - :align: center - :alt: TI CC1352R LaunchPad - - Texas Instruments CC1352R LaunchPad |trade| - Hardware ******** diff --git a/boards/ti/cc1352r_sensortag/cc1352r_sensortag_defconfig b/boards/ti/cc1352r_sensortag/cc1352r_sensortag_defconfig index 2cddbd5af73..84b07413d0c 100644 --- a/boards/ti/cc1352r_sensortag/cc1352r_sensortag_defconfig +++ b/boards/ti/cc1352r_sensortag/cc1352r_sensortag_defconfig @@ -13,7 +13,6 @@ CONFIG_CC13X2_CC26X2_BOOTLOADER_BACKDOOR_PIN=15 CONFIG_ARM_MPU=y CONFIG_HW_STACK_PROTECTION=y -CONFIG_PINCTRL=y CONFIG_GPIO=y CONFIG_SERIAL=y diff --git a/boards/ti/cc1352r_sensortag/doc/index.rst b/boards/ti/cc1352r_sensortag/doc/index.rst index 4120f4934df..f31c744b7b7 100644 --- a/boards/ti/cc1352r_sensortag/doc/index.rst +++ b/boards/ti/cc1352r_sensortag/doc/index.rst @@ -1,7 +1,4 @@ -.. _cc1352r_sensortag: - -CC1352R SensorTag -################# +.. zephyr:board:: cc1352r_sensortag Overview ******** @@ -11,12 +8,6 @@ development kit for the SimpleLink |trade| multi-Standard CC1352R wireless MCU. See the `TI CC1352R SensorTag Product Page`_ for details. -.. figure:: img/cc1352r_sensortag.jpg - :align: center - :alt: TI CC1352R SensorTag - - Texas Instruments CC1352R SensorTag |trade| - Hardware ******** diff --git a/boards/ti/cc26x2r1_launchxl/cc26x2r1_launchxl_defconfig b/boards/ti/cc26x2r1_launchxl/cc26x2r1_launchxl_defconfig index d10e7a152e5..f4aa8c3c541 100644 --- a/boards/ti/cc26x2r1_launchxl/cc26x2r1_launchxl_defconfig +++ b/boards/ti/cc26x2r1_launchxl/cc26x2r1_launchxl_defconfig @@ -14,7 +14,6 @@ CONFIG_CC13X2_CC26X2_BOOTLOADER_BACKDOOR_PIN=13 CONFIG_ARM_MPU=y CONFIG_HW_STACK_PROTECTION=y -CONFIG_PINCTRL=y CONFIG_GPIO=y CONFIG_SERIAL=y diff --git a/boards/ti/cc26x2r1_launchxl/doc/index.rst b/boards/ti/cc26x2r1_launchxl/doc/index.rst index 1f6a02d92dd..c08b2b9a933 100644 --- a/boards/ti/cc26x2r1_launchxl/doc/index.rst +++ b/boards/ti/cc26x2r1_launchxl/doc/index.rst @@ -1,7 +1,4 @@ -.. _cc26x2r1_launchxl: - -CC26x2R1 LaunchXL -################# +.. zephyr:board:: cc26x2r1_launchxl Overview ******** @@ -11,12 +8,6 @@ development kit for the SimpleLink |trade| multi-Standard CC2652R wireless MCU. See the `TI CC26x2R LaunchPad Product Page`_ for details. -.. figure:: img/cc26x2r1_launchxl.jpg - :align: center - :alt: TI CC26x2R LaunchPad - - Texas Instruments CC26x2R LaunchPad |trade| - Hardware ******** diff --git a/boards/ti/cc3220sf_launchxl/doc/index.rst b/boards/ti/cc3220sf_launchxl/doc/index.rst index cc14840d999..6ff33afb88b 100644 --- a/boards/ti/cc3220sf_launchxl/doc/index.rst +++ b/boards/ti/cc3220sf_launchxl/doc/index.rst @@ -1,7 +1,4 @@ -.. _cc3220sf_launchxl: - -CC3220SF LaunchXL -################# +.. zephyr:board:: cc3220sf_launchxl Overview ******** @@ -218,7 +215,7 @@ Usage: Set :kconfig:option:`CONFIG_WIFI_SIMPLELINK` and :kconfig:option:`CONFIG_WIFI` to ``y`` to enable Wi-Fi. -See :zephyr_file:`samples/net/wifi/boards/cc3220sf_launchxl.conf`. +See :zephyr_file:`samples/net/wifi/shell/boards/cc3220sf_launchxl.conf`. Provisioning: ============= diff --git a/boards/ti/cc3235sf_launchxl/doc/index.rst b/boards/ti/cc3235sf_launchxl/doc/index.rst index 69c5bae82f6..7602a3b2712 100644 --- a/boards/ti/cc3235sf_launchxl/doc/index.rst +++ b/boards/ti/cc3235sf_launchxl/doc/index.rst @@ -1,7 +1,4 @@ -.. _cc3235sf_launchxl: - -CC3235SF LaunchXL -################# +.. zephyr:board:: cc3235sf_launchxl Overview ******** @@ -218,7 +215,7 @@ Usage: Set :kconfig:option:`CONFIG_WIFI_SIMPLELINK` and :kconfig:option:`CONFIG_WIFI` to ``y`` to enable Wi-Fi. -See :zephyr_file:`samples/net/wifi/boards/cc3235sf_launchxl.conf`. +See :zephyr_file:`samples/net/wifi/shell/boards/cc3235sf_launchxl.conf`. Provisioning: ============= @@ -266,6 +263,8 @@ using the TI UniFlash tool for certificate programming. References ********** +.. target-notes:: + TI SimpleLink MCUs: http://www.ti.com/microcontrollers/simplelink-mcus/overview.html diff --git a/boards/ti/msp_exp432p401r_launchxl/doc/index.rst b/boards/ti/msp_exp432p401r_launchxl/doc/index.rst index e59942416f9..7b0662d6622 100644 --- a/boards/ti/msp_exp432p401r_launchxl/doc/index.rst +++ b/boards/ti/msp_exp432p401r_launchxl/doc/index.rst @@ -1,7 +1,4 @@ -.. _msp_exp432p401r_launchxl: - -MSP-EXP432P401R LaunchXL -######################## +.. zephyr:board:: msp_exp432p401r_launchxl Overview ******** @@ -11,10 +8,6 @@ module for the SimpleLink MSP432P401R microcontroller. It contains everything ne developing on the SimpleLink MSP432 low-power + performance ARM |reg| 32-bit Cortex |reg|-M4F microcontroller (MCU). -.. figure:: img/msp_exp432p401r_launchxl.jpg - :align: center - :alt: MSP-EXP432P401R LaunchXL development board - Features: ========= @@ -133,6 +126,8 @@ build target: References ********** +.. target-notes:: + TI MSP432 Wiki: https://en.wikipedia.org/wiki/TI_MSP432 diff --git a/boards/ti/sk_am62/doc/index.rst b/boards/ti/sk_am62/doc/index.rst index 60252c236eb..5e6cab8439f 100644 --- a/boards/ti/sk_am62/doc/index.rst +++ b/boards/ti/sk_am62/doc/index.rst @@ -1,7 +1,4 @@ -.. _sk_am62: - -SK-AM62 M4F Core -################ +.. zephyr:board:: sk_am62 Overview ******** @@ -17,12 +14,6 @@ The board configuration also enables support for the semihosting debugging conso See the `TI AM62X Product Page`_ for details. -.. figure:: img/sk_am62_angled.webp - :align: center - :alt: TI SK-AM62 EVM - - Texas Instruments SK-AM62 EVM - Hardware ******** The SK-AM62 EVM features the AM62x SoC, which is composed of a quad Cortex-A53 diff --git a/boards/ti/sk_am62/sk_am62_am6234_m4_defconfig b/boards/ti/sk_am62/sk_am62_am6234_m4_defconfig index 8ed54c6554e..329040d31bd 100644 --- a/boards/ti/sk_am62/sk_am62_am6234_m4_defconfig +++ b/boards/ti/sk_am62/sk_am62_am6234_m4_defconfig @@ -11,9 +11,6 @@ CONFIG_CORTEX_M_SYSTICK=y # Zephyr Kernel Configuration CONFIG_XIP=n -# Enable Pinctrl -CONFIG_PINCTRL=y - # Serial Driver CONFIG_SERIAL=y diff --git a/boards/toradex/colibri_imx7d/colibri_imx7d_mcimx7d_m4_defconfig b/boards/toradex/colibri_imx7d/colibri_imx7d_mcimx7d_m4_defconfig index a55e01a9fa7..64735316867 100644 --- a/boards/toradex/colibri_imx7d/colibri_imx7d_mcimx7d_m4_defconfig +++ b/boards/toradex/colibri_imx7d/colibri_imx7d_mcimx7d_m4_defconfig @@ -9,4 +9,3 @@ CONFIG_SERIAL=y CONFIG_UART_INTERRUPT_DRIVEN=y CONFIG_CONSOLE=y CONFIG_XIP=y -CONFIG_PINCTRL=y diff --git a/boards/toradex/colibri_imx7d/doc/index.rst b/boards/toradex/colibri_imx7d/doc/index.rst index dd13a140b3c..ea36ff6b50b 100644 --- a/boards/toradex/colibri_imx7d/doc/index.rst +++ b/boards/toradex/colibri_imx7d/doc/index.rst @@ -1,7 +1,4 @@ -.. _colibri_imx7d: - -NXP i.MX 7 Computer on Module - Colibri iMX7 -############################################ +.. zephyr:board:: colibri_imx7d Overview ******** @@ -11,11 +8,6 @@ core and Single Cortex M4 core. Zephyr was ported to run on the M4 core. In a later release, it will also communicate with the A7 core (running Linux) via RPmsg. - -.. image:: colibri_imx7d.jpg - :align: center - :alt: Colibri-iMX7 - Hardware ******** diff --git a/boards/toradex/verdin_imx8mm/Kconfig.defconfig b/boards/toradex/verdin_imx8mm/Kconfig.defconfig new file mode 100644 index 00000000000..331e26b4b0b --- /dev/null +++ b/boards/toradex/verdin_imx8mm/Kconfig.defconfig @@ -0,0 +1,15 @@ +# VERDIN_IMX8MM board defconfig +# +# Copyright (c) 2024, Toradex +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_VERDIN_IMX8MM + +if !XIP +config FLASH_SIZE + default 0 +config FLASH_BASE_ADDRESS + default 0 +endif + +endif # BOARD_VERDIN_IMX8MM diff --git a/boards/toradex/verdin_imx8mm/Kconfig.verdin_imx8mm b/boards/toradex/verdin_imx8mm/Kconfig.verdin_imx8mm new file mode 100644 index 00000000000..52de27de01d --- /dev/null +++ b/boards/toradex/verdin_imx8mm/Kconfig.verdin_imx8mm @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Toradex +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_VERDIN_IMX8MM + select SOC_PART_NUMBER_MIMX8MM6DVTLZ + select SOC_MIMX8MM6_M4 if BOARD_VERDIN_IMX8MM_MIMX8MM6_M4 diff --git a/boards/toradex/verdin_imx8mm/board.cmake b/boards/toradex/verdin_imx8mm/board.cmake new file mode 100644 index 00000000000..ae521ff4962 --- /dev/null +++ b/boards/toradex/verdin_imx8mm/board.cmake @@ -0,0 +1,11 @@ +# +# Copyright (c) 2024, Toradex +# +# SPDX-License-Identifier: Apache-2.0 +# + +board_set_debugger_ifnset(jlink) +board_set_flasher_ifnset(jlink) + +board_runner_args(jlink "--device=MIMX8MD6_M4") +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/toradex/verdin_imx8mm/board.yml b/boards/toradex/verdin_imx8mm/board.yml new file mode 100644 index 00000000000..0426a516da0 --- /dev/null +++ b/boards/toradex/verdin_imx8mm/board.yml @@ -0,0 +1,6 @@ +board: + name: verdin_imx8mm + full_name: Verdin iMX8M Mini + vendor: toradex + socs: + - name: mimx8mm6 diff --git a/boards/toradex/verdin_imx8mm/doc/img/verdin_imx8mm_m4.webp b/boards/toradex/verdin_imx8mm/doc/img/verdin_imx8mm_m4.webp new file mode 100644 index 00000000000..87a26a21b11 Binary files /dev/null and b/boards/toradex/verdin_imx8mm/doc/img/verdin_imx8mm_m4.webp differ diff --git a/boards/toradex/verdin_imx8mm/doc/index.rst b/boards/toradex/verdin_imx8mm/doc/index.rst new file mode 100644 index 00000000000..112596322bc --- /dev/null +++ b/boards/toradex/verdin_imx8mm/doc/index.rst @@ -0,0 +1,261 @@ +.. zephyr:board:: verdin_imx8mm + +Overview +******** + +The Verdin iMX8M Mini is a System on Module based on the NXP® i.MX 8M Mini family of +embedded System on Chips (SoCs). The i.MX 8M Mini family consists of the i.MX 8M Mini Quad, +i.MX 8M Mini QuadLite, i.MX 8M Mini Dual, i.MX 8M Mini DualLite, i.MX 8M Mini Solo, and i.MX +8M Mini SoloLite. The top-tier i.MX 8M Mini Quad features four Cortex-A53 cores as the main +processor cluster. The cores provide complete 64-bit Armv8-A support while maintaining seamless +backwards compatibility with 32-bit Armv7-A software. The main cores run at up to 1.8 GHz for +commercial graded products and 1.6 GHz for industrial temperature range products. + +In addition to the main CPU complex, the i.MX 8M Mini features a Cortex-M4F processor which +peaks up to 400 MHz. This processor is independent of the main complex and features its own +dedicated interfaces while still being able to access the regular interfaces. This heterogeneous +multicore system allows for the running of additional real-time operating systems on the M4 cores +for time- and security-critical tasks. + +- Board features: + + - RAM: 1GB - 2GB (LPDDR4) + - Storage: + + - 4GB - 17GB eMMC + - 2KB I²C EEPROM + - Wireless: + + - WiFi Dual-band 802.11 ac/a/b/g/n 2.4/5 GHz + - Bluetooth 5/BLE + - USB: + + - 1x USB2.0 Host + - 1x USB2.0 OTG + - Ethernet Gigabit + - Interfaces: + + - MIPI DSI 1x4 Data Lanes + - PCIe Gen 2 + - MIPI CSI-2 + - SPI + - QSPI + - UART + - I²C + - I²S + - SD/SDIO/MMC + - GPIOs + - CAN + - ADC + - S/PDIF + - Debug + + - JTAG 10-pin connector + +More information about the board can be found at the +`Toradex website`_. + +Supported Features +================== + +The Zephyr ``verdin_imx8mm/mimx8mm6/m4`` board target supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | GPIO output | +| | | GPIO input | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/toradex/verdin_imx8mm/verdin_imx8mm_mimx8mm6_m4_defconfig`. + +It is recommended to disable peripherals used by the M4 core on the Linux host. + +Other hardware features are not currently supported by the port. + +Connections and IOs +=================== + +UART: + +Zephyr is configured to use the UART4 by default, which is connected to the FTDI +USB converter on most Toradex carrier boards. + +This is also the UART connected to WiFi/BT chip in modules that have the WiFi/BT +chip. Therefore, if UART4 is used, WiFI/BT will not work properly. + +If the WiFi/BT is needed, then another UART should be used for Zephyr (UART2 for +example). You can change the UART by changing the ``zephyr,console`` and +``zephyr,shell-uart`` in the :zephyr_file:`boards/toradex/verdin_imx8mm/verdin_imx8mm_mimx8mm6_m4.dts` file. + ++---------------+-----------------+---------------------------+ +| Board Name | SoC Name | Usage | ++===============+=================+===========================+ +| UART_1 | UART2 | General purpose UART | ++---------------+-----------------+---------------------------+ +| UART_2 | UART3 | General purpose UART | ++---------------+-----------------+---------------------------+ +| UART_3 | UART1 | Cortex-A53 debug UART | ++---------------+-----------------+---------------------------+ +| UART_4 | UART4 | Cortex-M4 debug UART | ++---------------+-----------------+---------------------------+ + +GPIO: + +All the GPIO banks are enabled in the :zephyr_file:`dts/arm/nxp/nxp_imx8m_m4.dtsi`. + +LED: + +There is no LED in the module itself, this is dependent on the carrier board that +is being used with the module. The device tree is configured to use the GPIO3_IO1, +which can be connected to the LED of the Verdin Development Board or changed in the +:zephyr_file:`boards/toradex/verdin_imx8mm/verdin_imx8mm_mimx8mm6_m4.dts` if needed. + +System Clock +============ + +The M4 Core is configured to run at a 400 MHz clock speed. + +Programming and Debugging +************************* + +The i.MX8MM doesn't have QSPI flash for the M4 and it needs +to be started by the A53 core. The A53 core is responsible to load the M4 binary +application into the RAM, putting the M4 in reset, setting the M4 Program Counter and +Stack Pointer, and get the M4 out of reset. The A53 can perform these steps at the +bootloader level or after the Linux system has booted via RemoteProc. + +The M4 can use up to 3 different RAMs. These are the memory mapping for A53 and M4: + ++------------+-------------------------+------------------------+-----------------------+----------------------+ +| Region | Cortex-A53 | Cortex-M4 (System Bus) | Cortex-M4 (Code Bus) | Size | ++============+=========================+========================+=======================+======================+ +| OCRAM | 0x00900000-0x0093FFFF | 0x20200000-0x2023FFFF | 0x00900000-0x0093FFFF | 256KB | ++------------+-------------------------+------------------------+-----------------------+----------------------+ +| TCMU | 0x00800000-0x0081FFFF | 0x20000000-0x2001FFFF | | 128KB | ++------------+-------------------------+------------------------+-----------------------+----------------------+ +| TCML | 0x007E0000-0x007FFFFF | | 0x1FFE0000-0x1FFFFFFF | 128KB | ++------------+-------------------------+------------------------+-----------------------+----------------------+ +| OCRAM_S | 0x00180000-0x00187FFF | 0x20180000-0x20187FFF | 0x00180000-0x00187FFF | 32KB | ++------------+-------------------------+------------------------+-----------------------+----------------------+ + +For more information about memory mapping see the +`i.MX 8M Applications Processor Reference Manual`_ (section 2.1.2 and 2.1.3) + +At compilation time you have to choose which RAM will be used. This +configuration is done in the file :zephyr_file:`boards/toradex/verdin_imx8mm/verdin_imx8mm_mimx8mm6_m4.dts` +with "zephyr,flash" (when CONFIG_XIP=y) and "zephyr,sram" properties. +The available configurations are: + +.. code-block:: none + + "zephyr,flash" + - &tcml_code + - &ocram_code + - &ocram_s_code + + "zephyr,sram" + - &tcmu_sys + - &ocram_sys + - &ocram_s_sys + +Starting the Cortex-M4 via U-Boot +================================= + +Load and run Zephyr on M4 from A53 using u-boot by copying the compiled +``zephyr.bin`` to the eMMC (can be the FAT or EXT4 partition). You can do it +by using a USB stick or through the ethernet with the scp command, for example. +Power it up and stop at the u-boot prompt. + +Load the M4 binary onto the desired memory and start its execution using: + +.. code-block:: console + + fatload mmc 0:1 ${loadaddr} zephyr.bin + cp.b ${loadaddr} 0x7e0000 + bootaux 0x7e0000 + +Or if the binary is on the ext4 partition: + +.. code-block:: console + + ext4load mmc 0:2 ${loadaddr} /path/to/zephyr.bin + cp.b ${loadaddr} 0x7e0000 + bootaux 0x7e0000 + +If you are using `TorizonCore`_ OS, then you should use partition 1: + +.. code-block:: console + + ext4load mmc 0:1 ${loadaddr} /path/to/zephyr.bin + cp.b ${loadaddr} 0x7e0000 + bootaux 0x7e0000 + +Starting the Cortex-M4 via RemoteProc +===================================== + +Copy the ``zepyhr.elf`` to ``/lib/firmware`` on the target. + +.. note:: + In order to use remoteproc you have to add ``imx8mm-verdin_hmp_overlay.dtbo`` at + the end of the line in the ``/boot/overlays.txt``, then reboot the target. If + you are using `TorizonCore`_, then this file is located at + ``/boot/ostree/torizon-/dtb/overlays.txt``. + +To load and start a firmware use these commands: + +.. code-block:: console + + verdin-imx8mm:~# echo zepyhr.elf > /sys/class/remoteproc/remoteproc0/firmware + verdin-imx8mm:~# echo start > /sys/class/remoteproc/remoteproc0/state + [ 94.714498] remoteproc remoteproc0: powering up imx-rproc + [ 94.720481] remoteproc remoteproc0: Booting fw image zephyr.elf, size 473172 + [ 94.727713] remoteproc remoteproc0: No resource table in elf + [ 94.733615] remoteproc remoteproc0: remote processor imx-rproc is now up + +The M4-Core is now started up and running. You can see the output from Zephyr +on UART4. + +Debugging +========= + +MIMX8MM EVK board can be debugged by connecting an external JLink +JTAG debugger to the J902 debug connector and to the PC. Then +the application can be debugged using the usual way. + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: verdin_imx8mm/mimx8mm6/m4 + :goals: debug + +Open a serial terminal, step through the application in your debugger, and you +should see the following message in the terminal: + +.. code-block:: console + + *** Booting Zephyr OS build zephyr-v3.4.0-1251-g43c549305bdb *** + Hello World! verdin_imx8mm_m4 + +.. _Toradex website: + https://developer.toradex.com/hardware/verdin-som-family/modules/verdin-imx8m-mini/ + +.. _i.MX 8M Applications Processor Reference Manual: + https://www.nxp.com/webapp/Download?colCode=IMX8MMRM + +.. _TorizonCore: + https://developer.toradex.com/torizon/ diff --git a/boards/toradex/verdin_imx8mm/verdin_imx8mm-pinctrl.dtsi b/boards/toradex/verdin_imx8mm/verdin_imx8mm-pinctrl.dtsi new file mode 100644 index 00000000000..ed92bc9f038 --- /dev/null +++ b/boards/toradex/verdin_imx8mm/verdin_imx8mm-pinctrl.dtsi @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2023 Toradex + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + uart4_default: uart4_default { + group0 { + pinmux = <&iomuxc_uart4_rxd_uart_rx_uart4_rx>, + <&iomuxc_uart4_txd_uart_tx_uart4_tx>; + slew-rate = "fast"; + drive-strength = "x6"; + }; + }; + + uart3_default: uart3_default { + group0 { + pinmux = <&iomuxc_uart3_rxd_uart_rx_uart3_rx>, + <&iomuxc_uart3_txd_uart_tx_uart3_tx>; + slew-rate = "fast"; + drive-strength = "x6"; + }; + }; + + uart2_default: uart2_default { + group0 { + pinmux = <&iomuxc_sai3_rxd_uart_cts_b_uart2_rts_b>, + <&iomuxc_sai3_rxd_uart_rts_b_uart2_rts_b>, + <&iomuxc_sai3_txfs_uart_tx_uart2_rx>, + <&iomuxc_sai3_txc_uart_rx_uart2_tx>; + slew-rate = "fast"; + drive-strength = "x6"; + }; + }; + + uart1_default: uart1_default { + group0 { + pinmux = <&iomuxc_sai2_rxfs_uart_rx_uart1_tx>, + <&iomuxc_sai2_rxc_uart_rx_uart1_rx>, + <&iomuxc_sai2_rxd0_uart_rts_b_uart1_rts_b>, + <&iomuxc_sai2_txfs_uart_cts_b_uart1_cts_b>; + slew-rate = "fast"; + drive-strength = "x6"; + }; + }; +}; diff --git a/boards/toradex/verdin_imx8mm/verdin_imx8mm_mimx8mm6_m4.dts b/boards/toradex/verdin_imx8mm/verdin_imx8mm_mimx8mm6_m4.dts new file mode 100644 index 00000000000..e1b0f61a1cc --- /dev/null +++ b/boards/toradex/verdin_imx8mm/verdin_imx8mm_mimx8mm6_m4.dts @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2024, Toradex + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "verdin_imx8mm-pinctrl.dtsi" + +/ { + model = "Toradex Verdin iMX8M Mini"; + compatible = "nxp,verdin_imx8mm"; + + aliases { + uart-1 = &uart1; + uart-2 = &uart2; + uart-3 = &uart3; + uart-4 = &uart4; + led0 = &led_0; + }; + + chosen { + zephyr,flash = &tcml_code; + zephyr,sram = &tcmu_sys; + zephyr,console = &uart4; + zephyr,shell-uart = &uart4; + }; + + leds { + compatible = "gpio-leds"; + + led_0: led_0 { + gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&gpio3 { + status = "okay"; +}; + +&mailbox0 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_default>; + current-speed = <115200>; + status = "disabled"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_default>; + current-speed = <115200>; + status = "disabled"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_default>; + current-speed = <115200>; + status = "disabled"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_default>; + current-speed = <115200>; + status = "okay"; +}; diff --git a/boards/toradex/verdin_imx8mm/verdin_imx8mm_mimx8mm6_m4.yaml b/boards/toradex/verdin_imx8mm/verdin_imx8mm_mimx8mm6_m4.yaml new file mode 100644 index 00000000000..dc6f24f56d0 --- /dev/null +++ b/boards/toradex/verdin_imx8mm/verdin_imx8mm_mimx8mm6_m4.yaml @@ -0,0 +1,21 @@ +# +# Copyright (c) 2024 Toradex +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: verdin_imx8mm/mimx8mm6/m4 +name: Toradex Verdin iMX8M Mini +type: mcu +arch: arm +ram: 128 +flash: 128 +toolchain: + - zephyr + - gnuarmemb + - xtools +testing: + ignore_tags: + - net + - bluetooth +vendor: toradex diff --git a/boards/toradex/verdin_imx8mm/verdin_imx8mm_mimx8mm6_m4_defconfig b/boards/toradex/verdin_imx8mm/verdin_imx8mm_mimx8mm6_m4_defconfig new file mode 100644 index 00000000000..0978045d488 --- /dev/null +++ b/boards/toradex/verdin_imx8mm/verdin_imx8mm_mimx8mm6_m4_defconfig @@ -0,0 +1,12 @@ +# +# Copyright (c) 2024 Toradex +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_CLOCK_CONTROL=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_CONSOLE=y +CONFIG_XIP=y +CONFIG_GPIO=y diff --git a/boards/toradex/verdin_imx8mp/doc/index.rst b/boards/toradex/verdin_imx8mp/doc/index.rst index e59101fa212..af78ea49808 100644 --- a/boards/toradex/verdin_imx8mp/doc/index.rst +++ b/boards/toradex/verdin_imx8mp/doc/index.rst @@ -1,7 +1,4 @@ -.. _verdin_imx8mp: - -Toradex Verdin iMX8M Plus SoM -############################# +.. zephyr:board:: verdin_imx8mp Overview ******** @@ -34,12 +31,6 @@ Quoting NXP: The Verdin iMX8M Plus integrates a total of 4 Arm Cortex™-A53 CPUs, operating at 1.6 GHz, alongside a single Arm Cortex™-M7F microcontroller operating at 800 MHz. -.. figure:: verdin_imx8mp_front.jpg - :align: center - :alt: Toradex Verdin iMX8M Plus - - Toradex Verdin iMX8M Plus (Credit: Toradex) - Regarding the Cortex-A53 cluster, it employs the ARMv8-A architecture as a mid-range and energy-efficient processor. With four cores in this cluster, each core is equipped with its own L1 memory system. Moreover, the cluster incorporates a unified L2 cache that offers supplementary diff --git a/boards/toradex/verdin_imx8mp/verdin_imx8mp_mimx8ml8_m7_ddr_defconfig b/boards/toradex/verdin_imx8mp/verdin_imx8mp_mimx8ml8_m7_ddr_defconfig index 0f2a48bcc79..850c9bdc905 100644 --- a/boards/toradex/verdin_imx8mp/verdin_imx8mp_mimx8ml8_m7_ddr_defconfig +++ b/boards/toradex/verdin_imx8mp/verdin_imx8mp_mimx8ml8_m7_ddr_defconfig @@ -11,4 +11,3 @@ CONFIG_SERIAL=y CONFIG_CONSOLE=y CONFIG_XIP=y CONFIG_CODE_DDR=y -CONFIG_PINCTRL=y diff --git a/boards/toradex/verdin_imx8mp/verdin_imx8mp_mimx8ml8_m7_defconfig b/boards/toradex/verdin_imx8mp/verdin_imx8mp_mimx8ml8_m7_defconfig index c7f1110e266..2df7198927d 100644 --- a/boards/toradex/verdin_imx8mp/verdin_imx8mp_mimx8ml8_m7_defconfig +++ b/boards/toradex/verdin_imx8mp/verdin_imx8mp_mimx8ml8_m7_defconfig @@ -11,4 +11,3 @@ CONFIG_SERIAL=y CONFIG_CONSOLE=y CONFIG_XIP=y CONFIG_CODE_ITCM=y -CONFIG_PINCTRL=y diff --git a/boards/u-blox/ubx_bmd300eval/Kconfig.defconfig b/boards/u-blox/ubx_bmd300eval/Kconfig.defconfig index 8ba8ca2d640..f5d3c0f7f67 100644 --- a/boards/u-blox/ubx_bmd300eval/Kconfig.defconfig +++ b/boards/u-blox/ubx_bmd300eval/Kconfig.defconfig @@ -5,7 +5,4 @@ if BOARD_UBX_BMD300EVAL -config BT_CTLR - default BT - endif # BOARD_UBX_BMD300EVAL diff --git a/boards/u-blox/ubx_bmd330eval/Kconfig b/boards/u-blox/ubx_bmd330eval/Kconfig index fbc749c300a..a1d19f19bc8 100644 --- a/boards/u-blox/ubx_bmd330eval/Kconfig +++ b/boards/u-blox/ubx_bmd330eval/Kconfig @@ -2,8 +2,3 @@ # Copyright (c) 2021 u-blox AG # SPDX-License-Identifier: Apache-2.0 - -# BT_CTLR depends on BT. When BT is enabled we should default to also -# enabling the controller. -config BT_CTLR - default y if BT diff --git a/boards/u-blox/ubx_bmd340eval/Kconfig.defconfig b/boards/u-blox/ubx_bmd340eval/Kconfig.defconfig index 37b10951309..9db86863bba 100644 --- a/boards/u-blox/ubx_bmd340eval/Kconfig.defconfig +++ b/boards/u-blox/ubx_bmd340eval/Kconfig.defconfig @@ -5,7 +5,4 @@ if BOARD_UBX_BMD340EVAL -config BT_CTLR - default BT - endif # BOARD_UBX_BMD340EVAL diff --git a/boards/u-blox/ubx_bmd345eval/Kconfig.defconfig b/boards/u-blox/ubx_bmd345eval/Kconfig.defconfig index 21e8ac9b5ca..c972f6639f2 100644 --- a/boards/u-blox/ubx_bmd345eval/Kconfig.defconfig +++ b/boards/u-blox/ubx_bmd345eval/Kconfig.defconfig @@ -6,7 +6,4 @@ if BOARD_UBX_BMD345EVAL_NRF52840 -config BT_CTLR - default BT - endif # BOARD_UBX_BMD345EVAL_NRF52840 diff --git a/boards/u-blox/ubx_bmd360eval/Kconfig b/boards/u-blox/ubx_bmd360eval/Kconfig index 60b85dcb6dd..c0148fc1c4d 100644 --- a/boards/u-blox/ubx_bmd360eval/Kconfig +++ b/boards/u-blox/ubx_bmd360eval/Kconfig @@ -2,8 +2,3 @@ # Copyright (c) 2021 u-blox AG # SPDX-License-Identifier: Apache-2.0 - -# BT_CTLR depends on BT. When BT is enabled we should default to also -# enabling the controller. -config BT_CTLR - default y if BT diff --git a/boards/u-blox/ubx_bmd380eval/Kconfig.defconfig b/boards/u-blox/ubx_bmd380eval/Kconfig.defconfig index 58afb83796f..47907f3d4c9 100644 --- a/boards/u-blox/ubx_bmd380eval/Kconfig.defconfig +++ b/boards/u-blox/ubx_bmd380eval/Kconfig.defconfig @@ -5,7 +5,4 @@ if BOARD_UBX_BMD380EVAL -config BT_CTLR - default BT - endif # BOARD_UBX_BMD380EVAL diff --git a/boards/u-blox/ubx_evkannab1/Kconfig.defconfig b/boards/u-blox/ubx_evkannab1/Kconfig.defconfig index e12e7d4ebac..93aec0902b7 100644 --- a/boards/u-blox/ubx_evkannab1/Kconfig.defconfig +++ b/boards/u-blox/ubx_evkannab1/Kconfig.defconfig @@ -5,7 +5,4 @@ if BOARD_UBX_EVKANNAB1 -config BT_CTLR - default BT - endif # BOARD_UBX_EVKANNAB1 diff --git a/boards/u-blox/ubx_evkninab1/Kconfig.defconfig b/boards/u-blox/ubx_evkninab1/Kconfig.defconfig index 5f897eb6bb1..b657e5f34fb 100644 --- a/boards/u-blox/ubx_evkninab1/Kconfig.defconfig +++ b/boards/u-blox/ubx_evkninab1/Kconfig.defconfig @@ -5,7 +5,4 @@ if BOARD_UBX_EVKNINAB1 -config BT_CTLR - default BT - endif # BOARD_UBX_EVKNINAB1 diff --git a/boards/u-blox/ubx_evkninab3/Kconfig.defconfig b/boards/u-blox/ubx_evkninab3/Kconfig.defconfig index 2579b835428..f976dd594a8 100644 --- a/boards/u-blox/ubx_evkninab3/Kconfig.defconfig +++ b/boards/u-blox/ubx_evkninab3/Kconfig.defconfig @@ -5,7 +5,4 @@ if BOARD_UBX_EVKNINAB3 -config BT_CTLR - default BT - endif # BOARD_UBX_EVKNINAB3 diff --git a/boards/u-blox/ubx_evkninab4/Kconfig.defconfig b/boards/u-blox/ubx_evkninab4/Kconfig.defconfig index c9e958708bf..d710b03f842 100644 --- a/boards/u-blox/ubx_evkninab4/Kconfig.defconfig +++ b/boards/u-blox/ubx_evkninab4/Kconfig.defconfig @@ -5,7 +5,4 @@ if BOARD_UBX_EVKNINAB4 -config BT_CTLR - default BT - endif # BOARD_UBX_EVKNINAB4 diff --git a/boards/udoo/udoo_neo_full/doc/index.rst b/boards/udoo/udoo_neo_full/doc/index.rst index 945c1dcee4a..3c9dd90e214 100644 --- a/boards/udoo/udoo_neo_full/doc/index.rst +++ b/boards/udoo/udoo_neo_full/doc/index.rst @@ -1,7 +1,4 @@ -.. _udoo_neo_full: - -UDOO Neo Full -############# +.. zephyr:board:: udoo_neo_full Overview ******** @@ -13,12 +10,6 @@ core running up to 227 MHz for high CPU performance and real-time response. Zephyr was ported to run on the Cortex-M4 core only. In a future release, it will also communicate with the Cortex-A9 core (running Linux) via OpenAMP. -.. figure:: udoo_neo_full_mcimx6x_m4.jpg - :align: center - :alt: UDOO-Neo-Full - - UDOO Neo Full (Credit: udoo.org) - Hardware ******** diff --git a/boards/udoo/udoo_neo_full/udoo_neo_full_mcimx6x_m4_defconfig b/boards/udoo/udoo_neo_full/udoo_neo_full_mcimx6x_m4_defconfig index 140679e50c3..3cbbb4d6f67 100644 --- a/boards/udoo/udoo_neo_full/udoo_neo_full_mcimx6x_m4_defconfig +++ b/boards/udoo/udoo_neo_full/udoo_neo_full_mcimx6x_m4_defconfig @@ -10,4 +10,3 @@ CONFIG_SERIAL=y CONFIG_UART_INTERRUPT_DRIVEN=y CONFIG_GPIO=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=227000000 -CONFIG_PINCTRL=y diff --git a/boards/up-bridge-the-gap/up_squared/up_squared.dts b/boards/up-bridge-the-gap/up_squared/up_squared.dts index 2e8e763115f..24818e98930 100644 --- a/boards/up-bridge-the-gap/up_squared/up_squared.dts +++ b/boards/up-bridge-the-gap/up_squared/up_squared.dts @@ -36,14 +36,14 @@ cpu@0 { device_type = "cpu"; - compatible = "intel,apollo-lake"; + compatible = "intel,apollo-lake", "intel,x86_64"; d-cache-line-size = <64>; reg = <0>; }; cpu@1 { device_type = "cpu"; - compatible = "intel,apollo-lake"; + compatible = "intel,apollo-lake", "intel,x86_64"; d-cache-line-size = <64>; reg = <1>; }; diff --git a/boards/up-bridge-the-gap/up_squared/up_squared.yaml b/boards/up-bridge-the-gap/up_squared/up_squared.yaml index 79e4d5e7e92..959feb7dfce 100644 --- a/boards/up-bridge-the-gap/up_squared/up_squared.yaml +++ b/boards/up-bridge-the-gap/up_squared/up_squared.yaml @@ -9,6 +9,7 @@ supported: - acpi - smp testing: + timeout_multiplier: 2 ignore_tags: - net - bluetooth diff --git a/boards/up-bridge-the-gap/up_squared/up_squared_defconfig b/boards/up-bridge-the-gap/up_squared/up_squared_defconfig index 608e32cdef0..cbc59ed83a7 100644 --- a/boards/up-bridge-the-gap/up_squared/up_squared_defconfig +++ b/boards/up-bridge-the-gap/up_squared/up_squared_defconfig @@ -9,7 +9,6 @@ CONFIG_SERIAL=y CONFIG_X2APIC=y CONFIG_SMP=y CONFIG_BUILD_OUTPUT_EFI=y -CONFIG_BUILD_NO_GAP_FILL=y CONFIG_APIC_TSC_DEADLINE_TIMER=n CONFIG_HPET_TIMER=y diff --git a/boards/up-bridge-the-gap/up_squared_pro_7000/up_squared_pro_7000_defconfig b/boards/up-bridge-the-gap/up_squared_pro_7000/up_squared_pro_7000_defconfig index fb9be2a4994..7fad00df636 100644 --- a/boards/up-bridge-the-gap/up_squared_pro_7000/up_squared_pro_7000_defconfig +++ b/boards/up-bridge-the-gap/up_squared_pro_7000/up_squared_pro_7000_defconfig @@ -9,4 +9,3 @@ CONFIG_UART_CONSOLE=y CONFIG_X2APIC=y CONFIG_SMP=y CONFIG_BUILD_OUTPUT_EFI=y -CONFIG_BUILD_NO_GAP_FILL=y diff --git a/boards/vcc-gnd/yd_esp32/Kconfig b/boards/vcc-gnd/yd_esp32/Kconfig new file mode 100644 index 00000000000..9c2cc2e18dc --- /dev/null +++ b/boards/vcc-gnd/yd_esp32/Kconfig @@ -0,0 +1,7 @@ +# Copyright (c) 2023 Julio Cesar +# SPDX-License-Identifier: Apache-2.0 + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 4096 if BOARD_YD_ESP32_ESP32_PROCPU + default 256 if BOARD_YD_ESP32_ESP32_APPCPU diff --git a/boards/vcc-gnd/yd_esp32/Kconfig.defconfig b/boards/vcc-gnd/yd_esp32/Kconfig.defconfig deleted file mode 100644 index 2ca1ba19036..00000000000 --- a/boards/vcc-gnd/yd_esp32/Kconfig.defconfig +++ /dev/null @@ -1,22 +0,0 @@ -# YD-ESP32 board configuration - -# Copyright (c) 2023 Julio Cesar -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_YD_ESP32_ESP32_PROCPU - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 65535 if WIFI && BT - default 51200 if WIFI - default 40960 if BT - default 4096 - -endif # BOARD_YD_ESP32_ESP32_PROCPU - -if BOARD_YD_ESP32_ESP32_APPCPU - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - default 256 - -endif # BOARD_YD_ESP32_ESP32_PROCPU diff --git a/boards/vcc-gnd/yd_esp32/doc/index.rst b/boards/vcc-gnd/yd_esp32/doc/index.rst index 20201b3a347..425c11c69f0 100644 --- a/boards/vcc-gnd/yd_esp32/doc/index.rst +++ b/boards/vcc-gnd/yd_esp32/doc/index.rst @@ -1,7 +1,4 @@ -.. _yd_esp32: - -YD-ESP32 -######## +.. zephyr:board:: yd_esp32 Overview ******** @@ -9,12 +6,6 @@ Overview The YD-ESP32 development board is one of VCC-GND® Studio's official boards. This board is based on the ESP32-WROOM-32E module, with the ESP32 as the core. -.. figure:: img/yd_esp32.png - :align: center - :alt: YD-ESP32 - - YD-ESP32 DevKit with ESP32-WROOM-32E Module - ESP32 ===== @@ -306,6 +297,8 @@ GDB stub is enabled on ESP32. References ********** +.. target-notes:: + .. _`ESP32-DevKitC-WROVER`: https://docs.espressif.com/projects/esp-idf/en/stable/esp32/hw-reference/esp32/get-started-devkitc.html# .. _`ESP32 Datasheet`: https://www.espressif.com/sites/default/files/documentation/esp32_datasheet_en.pdf .. _`ESP32 Technical Reference Manual`: https://espressif.com/sites/default/files/documentation/esp32_technical_reference_manual_en.pdf diff --git a/boards/vcc-gnd/yd_esp32/yd_esp32_appcpu.dts b/boards/vcc-gnd/yd_esp32/yd_esp32_appcpu.dts index 8501714220d..3514cbabbd3 100644 --- a/boards/vcc-gnd/yd_esp32/yd_esp32_appcpu.dts +++ b/boards/vcc-gnd/yd_esp32/yd_esp32_appcpu.dts @@ -6,15 +6,18 @@ /dts-v1/; #include +#include / { model = "VCC-GND Studio YD-ESP32 APPCPU"; compatible = "espressif,esp32"; chosen { - zephyr,sram = &sram0; + zephyr,sram = &sram1; zephyr,ipc_shm = &shm0; zephyr,ipc = &ipm0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_appcpu_partition; }; }; @@ -25,42 +28,3 @@ &trng0 { status = "okay"; }; - -&flash0 { - status = "okay"; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Reserve 60kB for the bootloader */ - boot_partition: partition@1000 { - label = "mcuboot"; - reg = <0x00001000 0x0000F000>; - read-only; - }; - - /* Reserve 1024kB for the application in slot 0 */ - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 0x00100000>; - }; - - /* Reserve 1024kB for the application in slot 1 */ - slot1_partition: partition@110000 { - label = "image-1"; - reg = <0x00110000 0x00100000>; - }; - - /* Reserve 256kB for the scratch partition */ - scratch_partition: partition@210000 { - label = "image-scratch"; - reg = <0x00210000 0x00040000>; - }; - - storage_partition: partition@250000 { - label = "storage"; - reg = <0x00250000 0x00006000>; - }; - }; -}; diff --git a/boards/vcc-gnd/yd_esp32/yd_esp32_procpu.dts b/boards/vcc-gnd/yd_esp32/yd_esp32_procpu.dts index a409ed6e909..119e18f222f 100644 --- a/boards/vcc-gnd/yd_esp32/yd_esp32_procpu.dts +++ b/boards/vcc-gnd/yd_esp32/yd_esp32_procpu.dts @@ -7,6 +7,7 @@ #include #include "yd_esp32-pinctrl.dtsi" #include +#include / { model = "VCC-GND Studio YD-ESP32 PROCPU"; @@ -30,7 +31,7 @@ }; chosen { - zephyr,sram = &sram0; + zephyr,sram = &sram1; zephyr,console = &uart0; zephyr,shell-uart = &uart0; zephyr,flash = &flash0; @@ -136,45 +137,6 @@ status = "okay"; }; -&flash0 { - status = "okay"; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Reserve 60kB for the bootloader */ - boot_partition: partition@1000 { - label = "mcuboot"; - reg = <0x00001000 0x0000F000>; - read-only; - }; - - /* Reserve 1024kB for the application in slot 0 */ - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 0x00100000>; - }; - - /* Reserve 1024kB for the application in slot 1 */ - slot1_partition: partition@110000 { - label = "image-1"; - reg = <0x00110000 0x00100000>; - }; - - /* Reserve 256kB for the scratch partition */ - scratch_partition: partition@210000 { - label = "image-scratch"; - reg = <0x00210000 0x00040000>; - }; - - storage_partition: partition@250000 { - label = "storage"; - reg = <0x00250000 0x00006000>; - }; - }; -}; - &esp32_bt_hci { status = "okay"; }; diff --git a/boards/vcc-gnd/yd_esp32/yd_esp32_procpu.yaml b/boards/vcc-gnd/yd_esp32/yd_esp32_procpu.yaml index 7e8e17cf71f..99ac5390768 100644 --- a/boards/vcc-gnd/yd_esp32/yd_esp32_procpu.yaml +++ b/boards/vcc-gnd/yd_esp32/yd_esp32_procpu.yaml @@ -17,8 +17,4 @@ supported: - spi - counter - entropy -testing: - ignore_tags: - - net - - bluetooth vendor: vcc-gnd diff --git a/boards/vcc-gnd/yd_stm32h750vb/doc/index.rst b/boards/vcc-gnd/yd_stm32h750vb/doc/index.rst index 2b5e1794bd2..d11a7e24730 100644 --- a/boards/vcc-gnd/yd_stm32h750vb/doc/index.rst +++ b/boards/vcc-gnd/yd_stm32h750vb/doc/index.rst @@ -1,7 +1,4 @@ -.. _yd_stm32h750vb: - -YD-STM32H750VB -############## +.. zephyr:board:: yd_stm32h750vb Overview ******** @@ -10,10 +7,6 @@ The YD-STM32H750VB development board is a complete demonstration and development platform for Arm |reg| Cortex |reg|-M7 core-based STM32H750VBT6 microcontroller, with 128Kbytes of Flash memory and 1 Mbytes of SRAM. -.. image:: img/yd_stm32h750vb.png - :align: center - :alt: YD-STM32H750VB - More information about STM32H750 can be found here: - `STM32H750 on www.st.com`_ diff --git a/boards/vcc-gnd/yd_stm32h750vb/yd_stm32h750vb_defconfig b/boards/vcc-gnd/yd_stm32h750vb/yd_stm32h750vb_defconfig index 40e6adc0583..62aac97cc60 100644 --- a/boards/vcc-gnd/yd_stm32h750vb/yd_stm32h750vb_defconfig +++ b/boards/vcc-gnd/yd_stm32h750vb/yd_stm32h750vb_defconfig @@ -21,6 +21,3 @@ CONFIG_GPIO=y # Enable Clocks CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/vngiotlab/nrf51_vbluno51/Kconfig.defconfig b/boards/vngiotlab/nrf51_vbluno51/Kconfig.defconfig index 4957faeb05c..ac83af0b12a 100644 --- a/boards/vngiotlab/nrf51_vbluno51/Kconfig.defconfig +++ b/boards/vngiotlab/nrf51_vbluno51/Kconfig.defconfig @@ -5,7 +5,4 @@ if BOARD_NRF51_VBLUNO51 -config BT_CTLR - default BT - endif # BOARD_NRF51_VBLUNO51 diff --git a/boards/vngiotlab/nrf51_vbluno51/doc/index.rst b/boards/vngiotlab/nrf51_vbluno51/doc/index.rst index b56bcdd093d..ad9db23a69e 100644 --- a/boards/vngiotlab/nrf51_vbluno51/doc/index.rst +++ b/boards/vngiotlab/nrf51_vbluno51/doc/index.rst @@ -1,7 +1,4 @@ -.. _nrf51_vbluno51: - -nRF51-VBLUno51 -############## +.. zephyr:board:: nrf51_vbluno51 Overview ******** @@ -9,12 +6,6 @@ Overview Zephyr uses the nrf51_vbluno51 board configuration to run on the VBLUno51 board, a VNG Bluetooth Low Energy UNO using an nRF51822 ARM processor. -.. figure:: img/nrf51_vbluno51.jpg - :align: center - :alt: nRF51_VBLUno51 - - nrf51_vbluno51 Top - .. figure:: img/nrf51_vbluno51_bot.jpg :align: center :alt: nRF51_VBLUno51 Bottom diff --git a/boards/vngiotlab/nrf52_vbluno52/Kconfig.defconfig b/boards/vngiotlab/nrf52_vbluno52/Kconfig.defconfig index 700df41dfc6..026b4b301a7 100644 --- a/boards/vngiotlab/nrf52_vbluno52/Kconfig.defconfig +++ b/boards/vngiotlab/nrf52_vbluno52/Kconfig.defconfig @@ -5,7 +5,4 @@ if BOARD_NRF52_VBLUNO52 -config BT_CTLR - default BT - endif # BOARD_NRF52_VBLUNO52 diff --git a/boards/vngiotlab/nrf52_vbluno52/doc/index.rst b/boards/vngiotlab/nrf52_vbluno52/doc/index.rst index 68a7c1b97c6..2c710421a64 100644 --- a/boards/vngiotlab/nrf52_vbluno52/doc/index.rst +++ b/boards/vngiotlab/nrf52_vbluno52/doc/index.rst @@ -1,7 +1,4 @@ -.. _nrf52_vbluno52: - -nRF52-VBLUno52 -############## +.. zephyr:board:: nrf52_vbluno52 Overview ******** @@ -18,12 +15,6 @@ the following devices: * FLASH * RADIO (Bluetooth Low Energy 5.0) -.. figure:: img/nrf52_vbluno52.jpg - :align: center - :alt: nRF52 VBLUno52 - - nRF52_VBLUno52 board - Hardware ******** diff --git a/boards/waveshare/esp32s3_touch_lcd_1_28/Kconfig b/boards/waveshare/esp32s3_touch_lcd_1_28/Kconfig index e6b26bf1d67..23a5df29f92 100644 --- a/boards/waveshare/esp32s3_touch_lcd_1_28/Kconfig +++ b/boards/waveshare/esp32s3_touch_lcd_1_28/Kconfig @@ -1,6 +1,7 @@ # Copyright (c) 2024 Joel Guittet # SPDX-License-Identifier: Apache-2.0 -config BOARD_ESP32S3_TOUCH_LCD_1_28 - select SOC_ESP32S3_PROCPU if BOARD_ESP32S3_TOUCH_LCD_1_28_ESP32S3_PROCPU - select SOC_ESP32S3_APPCPU if BOARD_ESP32S3_TOUCH_LCD_1_28_ESP32S3_APPCPU +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 4096 if BOARD_ESP32S3_TOUCH_LCD_1_28_ESP32S3_PROCPU + default 256 if BOARD_ESP32S3_TOUCH_LCD_1_28_ESP32S3_APPCPU diff --git a/boards/waveshare/esp32s3_touch_lcd_1_28/Kconfig.defconfig b/boards/waveshare/esp32s3_touch_lcd_1_28/Kconfig.defconfig index 06c61c850aa..f7e7a746798 100644 --- a/boards/waveshare/esp32s3_touch_lcd_1_28/Kconfig.defconfig +++ b/boards/waveshare/esp32s3_touch_lcd_1_28/Kconfig.defconfig @@ -3,30 +3,13 @@ if BOARD_ESP32S3_TOUCH_LCD_1_28_ESP32S3_PROCPU -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 65535 if WIFI && BT - default 51200 if WIFI - default 40960 if BT - default 4096 - -endif # BOARD_ESP32S3_TOUCH_LCD_1_28_ESP32S3_PROCPU - -if BOARD_ESP32S3_TOUCH_LCD_1_28_ESP32S3_APPCPU - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - default 256 - -endif # BOARD_ESP32S3_TOUCH_LCD_1_28_ESP32S3_APPCPU - -config ENTROPY_GENERATOR - default y - config KERNEL_MEM_POOL default y config PWM default y if DISPLAY -config LV_COLOR_16_SWAP +configdefault LV_COLOR_16_SWAP default y if LVGL + +endif # BOARD_ESP32S3_TOUCH_LCD_1_28_ESP32S3_PROCPU diff --git a/boards/waveshare/esp32s3_touch_lcd_1_28/Kconfig.esp32s3_touch_lcd_1_28 b/boards/waveshare/esp32s3_touch_lcd_1_28/Kconfig.esp32s3_touch_lcd_1_28 index b62dd557d26..5ba9a20d753 100644 --- a/boards/waveshare/esp32s3_touch_lcd_1_28/Kconfig.esp32s3_touch_lcd_1_28 +++ b/boards/waveshare/esp32s3_touch_lcd_1_28/Kconfig.esp32s3_touch_lcd_1_28 @@ -3,3 +3,5 @@ config BOARD_ESP32S3_TOUCH_LCD_1_28 select SOC_ESP32S3_R2 + select SOC_ESP32S3_PROCPU if BOARD_ESP32S3_TOUCH_LCD_1_28_ESP32S3_PROCPU + select SOC_ESP32S3_APPCPU if BOARD_ESP32S3_TOUCH_LCD_1_28_ESP32S3_APPCPU diff --git a/boards/waveshare/esp32s3_touch_lcd_1_28/doc/img/esp32s3_touch_lcd_1_28.webp b/boards/waveshare/esp32s3_touch_lcd_1_28/doc/img/esp32s3_touch_lcd_1_28.webp new file mode 100644 index 00000000000..99586a6c5b0 Binary files /dev/null and b/boards/waveshare/esp32s3_touch_lcd_1_28/doc/img/esp32s3_touch_lcd_1_28.webp differ diff --git a/boards/waveshare/esp32s3_touch_lcd_1_28/doc/index.rst b/boards/waveshare/esp32s3_touch_lcd_1_28/doc/index.rst index b80884a2e96..540ac8a68e6 100644 --- a/boards/waveshare/esp32s3_touch_lcd_1_28/doc/index.rst +++ b/boards/waveshare/esp32s3_touch_lcd_1_28/doc/index.rst @@ -1,7 +1,4 @@ -.. _esp32s3_touch_lcd_1_28: - -Waveshare ESP32-S3-Touch-LCD-1.28 -################################# +.. zephyr:board:: esp32s3_touch_lcd_1_28 Overview ******** @@ -122,6 +119,8 @@ It is the default option when building the application without additional config References ********** +.. target-notes:: + .. _ESP32-S3-Touch-LCD-1.28 Waveshare Wiki: https://www.waveshare.com/wiki/ESP32-S3-Touch-LCD-1.28 .. _ESP32-S3 Datasheet: https://www.espressif.com/sites/default/files/documentation/esp32-s3-mini-1_mini-1u_datasheet_en.pdf .. _ESP32-S3 Technical Reference Manual: https://www.espressif.com/sites/default/files/documentation/esp32-s3_technical_reference_manual_en.pdf diff --git a/boards/waveshare/esp32s3_touch_lcd_1_28/esp32s3_touch_lcd_1_28_esp32s3_appcpu.dts b/boards/waveshare/esp32s3_touch_lcd_1_28/esp32s3_touch_lcd_1_28_esp32s3_appcpu.dts index 9b345338aa4..53d70cdc115 100644 --- a/boards/waveshare/esp32s3_touch_lcd_1_28/esp32s3_touch_lcd_1_28_esp32s3_appcpu.dts +++ b/boards/waveshare/esp32s3_touch_lcd_1_28/esp32s3_touch_lcd_1_28_esp32s3_appcpu.dts @@ -4,52 +4,24 @@ */ /dts-v1/; -#include +#include +#include / { model = "ESP32-S3-Touch-LCD-1.28 APPCPU"; compatible = "waveshare,esp32-s3-touch-lcd-1.28"; chosen { - zephyr,sram = &sram0; + zephyr,sram = &sram1; + zephyr,ipc_shm = &shm0; + zephyr,ipc = &ipm0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_appcpu_partition; }; }; &flash0 { - status = "okay"; reg = <0x0 DT_SIZE_M(16)>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x0000F000>; - read-only; - }; - - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 0x00100000>; - }; - - slot1_partition: partition@110000 { - label = "image-1"; - reg = <0x00110000 0x00100000>; - }; - - scratch_partition: partition@210000 { - label = "image-scratch"; - reg = <0x00210000 0x00040000>; - }; - - storage_partition: partition@250000 { - label = "storage"; - reg = <0x00250000 0x00006000>; - }; - }; }; &trng0 { diff --git a/boards/waveshare/esp32s3_touch_lcd_1_28/esp32s3_touch_lcd_1_28_esp32s3_appcpu_defconfig b/boards/waveshare/esp32s3_touch_lcd_1_28/esp32s3_touch_lcd_1_28_esp32s3_appcpu_defconfig index a2196414381..15e93d6bf4a 100644 --- a/boards/waveshare/esp32s3_touch_lcd_1_28/esp32s3_touch_lcd_1_28_esp32s3_appcpu_defconfig +++ b/boards/waveshare/esp32s3_touch_lcd_1_28/esp32s3_touch_lcd_1_28_esp32s3_appcpu_defconfig @@ -3,4 +3,3 @@ CONFIG_MAIN_STACK_SIZE=2048 CONFIG_CLOCK_CONTROL=y -CONFIG_MINIMAL_LIBC=y diff --git a/boards/waveshare/esp32s3_touch_lcd_1_28/esp32s3_touch_lcd_1_28_esp32s3_procpu.dts b/boards/waveshare/esp32s3_touch_lcd_1_28/esp32s3_touch_lcd_1_28_esp32s3_procpu.dts index cb4bd891f61..55bd4f1e929 100644 --- a/boards/waveshare/esp32s3_touch_lcd_1_28/esp32s3_touch_lcd_1_28_esp32s3_procpu.dts +++ b/boards/waveshare/esp32s3_touch_lcd_1_28/esp32s3_touch_lcd_1_28_esp32s3_procpu.dts @@ -9,6 +9,7 @@ #include #include #include +#include / { model = "ESP32-S3-Touch-LCD-1.28 PROCPU"; @@ -24,13 +25,14 @@ }; chosen { - zephyr,sram = &sram0; + zephyr,sram = &sram1; zephyr,console = &uart0; zephyr,shell-uart = &uart0; zephyr,flash = &flash0; zephyr,code-partition = &slot0_partition; zephyr,display = &gc9a01; zephyr,bt-hci = &esp32_bt_hci; + zephyr,touch = &cst816s; }; /* Buttons */ @@ -81,40 +83,7 @@ }; &flash0 { - status = "okay"; reg = <0x0 DT_SIZE_M(16)>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x0000F000>; - read-only; - }; - - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 0x00100000>; - }; - - slot1_partition: partition@110000 { - label = "image-1"; - reg = <0x00110000 0x00100000>; - }; - - scratch_partition: partition@210000 { - label = "image-scratch"; - reg = <0x00210000 0x00040000>; - }; - - storage_partition: partition@250000 { - label = "storage"; - reg = <0x00250000 0x00006000>; - }; - }; }; &gpio0 { diff --git a/boards/waveshare/esp32s3_touch_lcd_1_28/esp32s3_touch_lcd_1_28_esp32s3_procpu.yaml b/boards/waveshare/esp32s3_touch_lcd_1_28/esp32s3_touch_lcd_1_28_esp32s3_procpu.yaml index 5c81ff792a3..a2ae32d60f6 100644 --- a/boards/waveshare/esp32s3_touch_lcd_1_28/esp32s3_touch_lcd_1_28_esp32s3_procpu.yaml +++ b/boards/waveshare/esp32s3_touch_lcd_1_28/esp32s3_touch_lcd_1_28_esp32s3_procpu.yaml @@ -15,8 +15,4 @@ supported: - pinmux - nvs - display -testing: - ignore_tags: - - net - - bluetooth vendor: waveshare diff --git a/boards/waveshare/nrf51_ble400/Kconfig.defconfig b/boards/waveshare/nrf51_ble400/Kconfig.defconfig index 65d41b852d3..727fc35fece 100644 --- a/boards/waveshare/nrf51_ble400/Kconfig.defconfig +++ b/boards/waveshare/nrf51_ble400/Kconfig.defconfig @@ -5,7 +5,4 @@ if BOARD_NRF51_BLE400 -config BT_CTLR - default BT - endif # BOARD_NRF51_BLE400 diff --git a/boards/waveshare/nrf51_ble400/doc/index.rst b/boards/waveshare/nrf51_ble400/doc/index.rst index 3d34f2f27f0..5dd3034f9ca 100644 --- a/boards/waveshare/nrf51_ble400/doc/index.rst +++ b/boards/waveshare/nrf51_ble400/doc/index.rst @@ -1,7 +1,4 @@ -.. _nrf51_ble400: - -Waveshare BLE400 -################# +.. zephyr:board:: nrf51_ble400 Overview ******** diff --git a/boards/waveshare/open103z/doc/index.rst b/boards/waveshare/open103z/doc/index.rst index 773b60f202f..0ba052cc623 100644 --- a/boards/waveshare/open103z/doc/index.rst +++ b/boards/waveshare/open103z/doc/index.rst @@ -1,15 +1,10 @@ -.. _waveshare_open103z_board: - -Waveshare Open103Z -################## +.. zephyr:board:: waveshare_open103z Overview ******** The Waveshare Open103Z-64 is a development board equipped with STM32F103ZE MCU. -.. image:: img/waveshare_open103z.jpg - Hardware ******** diff --git a/boards/waveshare/rp2040_zero/Kconfig b/boards/waveshare/rp2040_zero/Kconfig new file mode 100644 index 00000000000..1ccd1ffd571 --- /dev/null +++ b/boards/waveshare/rp2040_zero/Kconfig @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Iacopo Moles +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_RP2040_ZERO + select RP2_FLASH_W25Q080 diff --git a/boards/waveshare/rp2040_zero/Kconfig.defconfig b/boards/waveshare/rp2040_zero/Kconfig.defconfig new file mode 100644 index 00000000000..b03a6c6d9d5 --- /dev/null +++ b/boards/waveshare/rp2040_zero/Kconfig.defconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2024 Iacopo Moles +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_RP2040_ZERO + +if I2C_DW + +config I2C_DW_CLOCK_SPEED + default 125 + +endif # I2C_DW + +endif # BOARD_RP2040_ZERO diff --git a/boards/waveshare/rp2040_zero/Kconfig.rp2040_zero b/boards/waveshare/rp2040_zero/Kconfig.rp2040_zero new file mode 100644 index 00000000000..47a5fbbb7eb --- /dev/null +++ b/boards/waveshare/rp2040_zero/Kconfig.rp2040_zero @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Iacopo Moles +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_RP2040_ZERO + select SOC_RP2040 diff --git a/boards/waveshare/rp2040_zero/board.cmake b/boards/waveshare/rp2040_zero/board.cmake new file mode 100644 index 00000000000..4103e36e635 --- /dev/null +++ b/boards/waveshare/rp2040_zero/board.cmake @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(uf2 "--board-id=RPI-RP2") + +include(${ZEPHYR_BASE}/boards/common/uf2.board.cmake) diff --git a/boards/waveshare/rp2040_zero/board.yml b/boards/waveshare/rp2040_zero/board.yml new file mode 100644 index 00000000000..4af02703a2e --- /dev/null +++ b/boards/waveshare/rp2040_zero/board.yml @@ -0,0 +1,6 @@ +board: + name: rp2040_zero + full_name: RP2040-Zero + vendor: waveshare + socs: + - name: rp2040 diff --git a/boards/waveshare/rp2040_zero/doc/img/rp2040_zero.png b/boards/waveshare/rp2040_zero/doc/img/rp2040_zero.png new file mode 100644 index 00000000000..d192b1a7d20 Binary files /dev/null and b/boards/waveshare/rp2040_zero/doc/img/rp2040_zero.png differ diff --git a/boards/waveshare/rp2040_zero/doc/index.rst b/boards/waveshare/rp2040_zero/doc/index.rst new file mode 100644 index 00000000000..27e527e32c3 --- /dev/null +++ b/boards/waveshare/rp2040_zero/doc/index.rst @@ -0,0 +1,132 @@ +.. zephyr:board:: rp2040_zero + +Overview +******** + +RP2040-Zero, A Low-Cost, High-Performance Pico-Like MCU Board Based On Raspberry Pi Microcontroller RP2040. + +Hardware +******** +- RP2040 microcontroller chip designed by Raspberry Pi in the United Kingdom. +- Dual-core Arm Cortex M0+ processor, flexible clock running up to 133 MHz. +- 264KB of SRAM, and 2MB of on-board Flash memory. +- USB-C connector, keeps it up to date, easier to use. +- The castellated module allows soldering direct to carrier boards. +- USB 1.1 with device and host support. +- Low-power sleep and dormant modes. +- Drag-and-drop programming using mass storage over USB. +- 29 × multi-function GPIO pins (20× via edge pinout, others via solder points). +- 2 × SPI, 2 × I2C, 2 × UART, 4 × 12-bit ADC, 16 × controllable PWM channels. +- Accurate clock and timer on-chip. +- Temperature sensor. +- Accelerated floating-point libraries on-chip. +- 8 × Programmable I/O (PIO) state machines for custom peripheral support. + +Supported Features +================== + +The ``rp2040_zero`` board target supports the following hardware features: + +.. list-table:: + :header-rows: 1 + + * - Peripheral + - Kconfig option + - Devicetree compatible + * - NVIC + - N/A + - :dtcompatible:`arm,v6m-nvic` + * - UART + - :kconfig:option:`CONFIG_SERIAL` + - :dtcompatible:`raspberrypi,pico-uart` + * - GPIO + - :kconfig:option:`CONFIG_GPIO` + - :dtcompatible:`raspberrypi,pico-gpio` + * - ADC + - :kconfig:option:`CONFIG_ADC` + - :dtcompatible:`raspberrypi,pico-adc` + * - I2C + - :kconfig:option:`CONFIG_I2C` + - :dtcompatible:`snps,designware-i2c` + * - SPI + - :kconfig:option:`CONFIG_SPI` + - :dtcompatible:`raspberrypi,pico-spi` + * - USB Device + - :kconfig:option:`CONFIG_USB_DEVICE_STACK` + - :dtcompatible:`raspberrypi,pico-usbd` + * - HWINFO + - :kconfig:option:`CONFIG_HWINFO` + - N/A + * - Watchdog Timer (WDT) + - :kconfig:option:`CONFIG_WATCHDOG` + - :dtcompatible:`raspberrypi,pico-watchdog` + * - PWM + - :kconfig:option:`CONFIG_PWM` + - :dtcompatible:`raspberrypi,pico-pwm` + * - Flash + - :kconfig:option:`CONFIG_FLASH` + - :dtcompatible:`raspberrypi,pico-flash` + * - Clock controller + - :kconfig:option:`CONFIG_CLOCK_CONTROL` + - :dtcompatible:`raspberrypi,pico-clock-controller` + * - UART (PIO) + - :kconfig:option:`CONFIG_SERIAL` + - :dtcompatible:`raspberrypi,pico-uart-pio` + * - SPI (PIO) + - :kconfig:option:`CONFIG_SPI` + - :dtcompatible:`raspberrypi,pico-spi-pio` + +Pin Mapping +=========== + +The peripherals of the RP2040 SoC can be routed to various pins on the board. The configuration of these routes can be modified through DTS. Please refer to the datasheet to see the possible routings for each peripheral. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +.. rst-class:: rst-columns + +- UART0_TX : P0 +- UART0_RX : P1 +- I2C0_SDA : P4 +- I2C0_SCL : P5 +- I2C1_SDA : P6 +- I2C1_SCL : P7 +- ADC_CH0 : P26 +- ADC_CH1 : P27 +- ADC_CH2 : P28 +- ADC_CH3 : P29 + +Programming and Debugging +************************* + +Flashing +======== + +Using UF2 +--------- + +Here is an example of building the sample for driving the built-in RGB led. + +.. zephyr-app-commands:: + :zephyr-app: samples/drivers/led/led_strip + :board: rp2040_zero + :goals: build + :compact: + +You must flash the RP2040-Zero with an UF2 file. One option is to use West (Zephyr’s meta-tool). To enter the UF2 flashing mode just keep the ``BOOT`` button pressed while you connect the USB port, it will appear on the host as a mass storage device. In alternative with the board already connected via USB you can keep the ``RESET`` button pressed, press and release ``BOOT``, release ``RESET``. At this point you can flash the image file by running: + +.. code-block:: bash + + west flash + +In alternative you can locate the generated file at ``build/zephyr/zephyr.uf2 file`` and simply drag-and-drop to the device after entreing the UF2 flashing mode. + +References +********** + +- `Official Documentation`_ +- `WS2812 datasheet`_ + +.. _Official Documentation: https://www.waveshare.com/wiki/RP2040-Zero +.. _WS2812 datasheet: https://cdn-shop.adafruit.com/datasheets/WS2812.pdf diff --git a/boards/waveshare/rp2040_zero/rp2040_zero-pinctrl.dtsi b/boards/waveshare/rp2040_zero/rp2040_zero-pinctrl.dtsi new file mode 100644 index 00000000000..80b18d45014 --- /dev/null +++ b/boards/waveshare/rp2040_zero/rp2040_zero-pinctrl.dtsi @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2024 Iacopo Moles + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +&pinctrl { + uart0_default: uart0_default { + status = "okay"; + group1 { + pinmux = ; + }; + group2 { + pinmux = ; + input-enable; + }; + }; + + i2c0_default: i2c0_default { + group1 { + pinmux = ; + input-enable; + }; + group2 { + pinmux = ; + input-enable; + }; + }; + + i2c1_default: i2c1_default { + group1 { + pinmux = ; + input-enable; + }; + group2 { + pinmux = ; + input-enable; + }; + }; + + spi0_default: spi0_default { + group1 { + pinmux = ; + }; + group2 { + pinmux = ; + input-enable; + }; + group3 { + pinmux = ; + }; + }; + + adc_default: adc_default { + group1 { + pinmux = , , , ; + input-enable; + }; + }; + + ws2812_pio0_default: ws2812_pio0_default { + ws2812 { + pinmux = ; + }; + }; +}; diff --git a/boards/waveshare/rp2040_zero/rp2040_zero.dts b/boards/waveshare/rp2040_zero/rp2040_zero.dts new file mode 100644 index 00000000000..88c41f55d2e --- /dev/null +++ b/boards/waveshare/rp2040_zero/rp2040_zero.dts @@ -0,0 +1,147 @@ +/* + * Copyright (c) 2024 Iacopo Moles + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "rp2040_zero-pinctrl.dtsi" +#include +#include +/ { + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,flash-controller = &ssi; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,code-partition = &code_partition; + }; + + aliases { + rtc = &rtc; + watchdog0 = &wdt0; + led-strip = &ws2812; + }; +}; + +&flash0 { + reg = <0x10000000 DT_SIZE_M(16)>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserved memory for the second stage bootloader */ + second_stage_bootloader: partition@0 { + label = "second_stage_bootloader"; + reg = <0x00000000 0x100>; + read-only; + }; + + /* + * Usable flash. Starts at 0x100, after the bootloader. The partition + * size is 16MB minus the 0x100 bytes taken by the bootloader. + */ + code_partition: partition@100 { + label = "code-partition"; + reg = <0x100 (DT_SIZE_M(16) - 0x100)>; + read-only; + }; + }; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; +}; + +&i2c0 { + status = "okay"; + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; + clock-frequency = ; +}; + +&i2c1 { + status = "okay"; + pinctrl-0 = <&i2c1_default>; + pinctrl-names = "default"; + clock-frequency = ; +}; + +&spi0 { + clock-frequency = ; + status = "okay"; + pinctrl-0 = <&spi0_default>; + pinctrl-names = "default"; +}; + +&timer { + status = "okay"; +}; + +&wdt0 { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&rtc { + clocks = <&clocks RPI_PICO_CLKID_CLK_RTC>; + status = "okay"; +}; + +&adc { + status = "okay"; + pinctrl-0 = <&adc_default>; + pinctrl-names = "default"; +}; + +&pio0 { + status = "okay"; + + pio-ws2812 { + compatible = "worldsemi,ws2812-rpi_pico-pio"; + status = "okay"; + pinctrl-0 = <&ws2812_pio0_default>; + pinctrl-names = "default"; + bit-waveform = <3>, <3>, <4>; + + ws2812: ws2812 { + status = "okay"; + gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; + chain-length = <1>; + color-mapping = ; + reset-delay = <280>; + frequency = <800000>; + }; + }; +}; + +&pio1 { + status = "okay"; +}; + +zephyr_udc0: &usbd { + status = "okay"; +}; + +&vreg { + regulator-always-on; + regulator-allowed-modes = ; +}; + +pico_spi: &spi0 {}; +pico_i2c0: &i2c0 {}; +pico_i2c1: &i2c1 {}; +pico_serial: &uart0 {}; diff --git a/boards/waveshare/rp2040_zero/rp2040_zero.yaml b/boards/waveshare/rp2040_zero/rp2040_zero.yaml new file mode 100644 index 00000000000..b93e332f7d8 --- /dev/null +++ b/boards/waveshare/rp2040_zero/rp2040_zero.yaml @@ -0,0 +1,24 @@ +identifier: rp2040_zero +name: Waveshare RP2040-Zero +type: mcu +arch: arm +flash: 16384 +ram: 264 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - uart + - gpio + - adc + - i2c + - spi + - hwinfo + - watchdog + - pwm + - flash + - dma + - counter + - clock + - usbd diff --git a/boards/waveshare/rp2040_zero/rp2040_zero_defconfig b/boards/waveshare/rp2040_zero/rp2040_zero_defconfig new file mode 100644 index 00000000000..3be05ed9862 --- /dev/null +++ b/boards/waveshare/rp2040_zero/rp2040_zero_defconfig @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=125000000 +CONFIG_SERIAL=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_GPIO=y +CONFIG_USE_DT_CODE_PARTITION=y +CONFIG_BUILD_OUTPUT_UF2=y +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_RESET=y +CONFIG_CLOCK_CONTROL=y diff --git a/boards/wch/ch32v003evt/Kconfig.ch32v003evt b/boards/wch/ch32v003evt/Kconfig.ch32v003evt new file mode 100644 index 00000000000..37a9c244442 --- /dev/null +++ b/boards/wch/ch32v003evt/Kconfig.ch32v003evt @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Michael Hope +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_CH32V003EVT + select SOC_CH32V003 diff --git a/boards/wch/ch32v003evt/board.cmake b/boards/wch/ch32v003evt/board.cmake new file mode 100644 index 00000000000..41ee69473bf --- /dev/null +++ b/boards/wch/ch32v003evt/board.cmake @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Michael Hope +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(minichlink) +include(${ZEPHYR_BASE}/boards/common/minichlink.board.cmake) + +board_runner_args(openocd "--use-elf" "--cmd-reset-halt" "halt") +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/wch/ch32v003evt/board.yml b/boards/wch/ch32v003evt/board.yml new file mode 100644 index 00000000000..291955892da --- /dev/null +++ b/boards/wch/ch32v003evt/board.yml @@ -0,0 +1,6 @@ +board: + name: ch32v003evt + full_name: WCH CH32V003EVT + vendor: wch + socs: + - name: ch32v003 diff --git a/boards/wch/ch32v003evt/ch32v003evt-pinctrl.dtsi b/boards/wch/ch32v003evt/ch32v003evt-pinctrl.dtsi new file mode 100644 index 00000000000..7f33d888e75 --- /dev/null +++ b/boards/wch/ch32v003evt/ch32v003evt-pinctrl.dtsi @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2024 Michael Hope + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + usart1_default: usart1_default { + group1 { + pinmux = ; + output-high; + drive-push-pull; + slew-rate = "max-speed-10mhz"; + }; + group2 { + pinmux = ; + bias-pull-up; + }; + }; +}; diff --git a/boards/wch/ch32v003evt/ch32v003evt.dts b/boards/wch/ch32v003evt/ch32v003evt.dts new file mode 100644 index 00000000000..d702b6d43d0 --- /dev/null +++ b/boards/wch/ch32v003evt/ch32v003evt.dts @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2024 Michael Hope + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "ch32v003evt-pinctrl.dtsi" + +/ { + model = "ch32v003evt"; + compatible = "wch,ch32v003"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,console = &usart1; + zephyr,shell-uart = &usart1; + }; + + leds { + compatible = "gpio-leds"; + + /* + * Please connect the unconnected LED on the WCH CH32V003EVT + * board to a suitable GPIO pin (like PD4) and then change + * this status to "okay". + */ + status = "disabled"; + + red_led: led0 { + gpios = <&gpiod 4 GPIO_ACTIVE_HIGH>; + }; + }; + + aliases { + led0 = &red_led; + }; +}; + +&clk_hse { + clock-frequency = ; + status = "okay"; +}; + +&pll { + clocks = <&clk_hse>; + status = "okay"; +}; + +&rcc { + clocks = <&pll>; +}; + +&gpiod { + status = "okay"; +}; + +&usart1 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&usart1_default>; + pinctrl-names = "default"; +}; diff --git a/boards/wch/ch32v003evt/ch32v003evt.yaml b/boards/wch/ch32v003evt/ch32v003evt.yaml new file mode 100644 index 00000000000..0968fd0b4e7 --- /dev/null +++ b/boards/wch/ch32v003evt/ch32v003evt.yaml @@ -0,0 +1,11 @@ +identifier: ch32v003evt +name: WCH CH32V003 Evaluation Board +type: mcu +arch: riscv +toolchain: + - cross-compile + - zephyr +ram: 2 +flash: 16 +supported: + - gpio diff --git a/boards/wch/ch32v003evt/ch32v003evt_defconfig b/boards/wch/ch32v003evt/ch32v003evt_defconfig new file mode 100644 index 00000000000..ea223eef702 --- /dev/null +++ b/boards/wch/ch32v003evt/ch32v003evt_defconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Michael Hope +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_GPIO=y + +CONFIG_SERIAL=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/wch/ch32v003evt/doc/img/ch32v003evt.webp b/boards/wch/ch32v003evt/doc/img/ch32v003evt.webp new file mode 100644 index 00000000000..9c1e800c7ad Binary files /dev/null and b/boards/wch/ch32v003evt/doc/img/ch32v003evt.webp differ diff --git a/boards/wch/ch32v003evt/doc/index.rst b/boards/wch/ch32v003evt/doc/index.rst new file mode 100644 index 00000000000..0c59c492de2 --- /dev/null +++ b/boards/wch/ch32v003evt/doc/index.rst @@ -0,0 +1,107 @@ +.. zephyr:board:: ch32v003evt + +Overview +******** + +The `WCH`_ CH32V003EVT hardware provides support for QingKe 32-bit RISC-V2A +processor and the following devices: + +* CLOCK +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` + +The board is equipped with two LEDs. The `WCH webpage on CH32V003`_ contains +the processor's information and the datasheet. + +Hardware +******** + +The QingKe 32-bit RISC-V2A processor of the WCH CH32V003EVT is clocked by an +external crystal and runs at 48 MHz. + +Supported Features +================== + +The ``ch32v003evt`` board target supports the following hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| PINCTRL | on-chip | pinctrl | ++-----------+------------+----------------------+ +| TIMER | on-chip | timer | ++-----------+------------+----------------------+ +| UART | on-chip | uart | ++-----------+------------+----------------------+ + +Other hardware features have not been enabled yet for this board. + +Connections and IOs +=================== + +LED +--- + +* LED1 = Unconnected. Connect to an I/O pin (PD4). + +Programming and Debugging +************************* + +Applications for the ``ch32v003evt`` board target can be built and flashed +in the usual way (see :ref:`build_an_application` and :ref:`application_run` +for more details); however, an external programmer is required since the board +does not have any built-in debug support. + +The following pins of the external programmer must be connected to the +following pins on the PCB (see image): + +* VCC = VCC (do not power the board from the USB port at the same time) +* GND = GND +* SWIO = PD1 + +Flashing +======== + +You can use ``minichlink`` to flash the board. Once ``minichlink`` has been set +up, build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: ch32v003evt + :goals: build flash + +Debugging +========= + +This board can be debugged via OpenOCD or ``minichlink``. + +Testing the LED on the WCH CH32V003EVT +************************************** + +There is 1 sample program that allow you to test that the LED on the board is +working properly with Zephyr: + +.. code-block:: console + + samples/basic/blinky + +You can build and flash the examples to make sure Zephyr is running +correctly on your board. The button and LED definitions can be found +in :zephyr_file:`boards/wch/ch32v003evt/ch32v003evt.dts`. + +References +********** + +.. target-notes:: + +.. _WCH: http://www.wch-ic.com +.. _WCH webpage on CH32V003: https://www.wch-ic.com/products/CH32V003.html diff --git a/boards/wch/ch32v003evt/support/openocd.cfg b/boards/wch/ch32v003evt/support/openocd.cfg new file mode 100644 index 00000000000..0d24d16ca20 --- /dev/null +++ b/boards/wch/ch32v003evt/support/openocd.cfg @@ -0,0 +1,15 @@ +#interface wlink +adapter driver wlink +wlink_set +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x00001 + +set _TARGETNAME $_CHIPNAME.cpu + +target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME +$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1 +set _FLASHNAME $_CHIPNAME.flash + +flash bank $_FLASHNAME wch_riscv 0x00000000 0 0 0 $_TARGETNAME.0 + +echo "Ready for Remote Connections" diff --git a/boards/wch/index.rst b/boards/wch/index.rst new file mode 100644 index 00000000000..21745ccfccd --- /dev/null +++ b/boards/wch/index.rst @@ -0,0 +1,10 @@ +.. _boards-wch: + +WCH - Nanjing Qinheng Microelectronics Co. +########################################## + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/we/ophelia1ev/Kconfig.defconfig b/boards/we/ophelia1ev/Kconfig.defconfig index c148d677183..e380a1452e5 100644 --- a/boards/we/ophelia1ev/Kconfig.defconfig +++ b/boards/we/ophelia1ev/Kconfig.defconfig @@ -3,7 +3,4 @@ if BOARD_WE_OPHELIA1EV -config BT_CTLR - default BT - endif diff --git a/boards/we/ophelia1ev/doc/index.rst b/boards/we/ophelia1ev/doc/index.rst index 908b0ce6889..189e0bdcfc7 100644 --- a/boards/we/ophelia1ev/doc/index.rst +++ b/boards/we/ophelia1ev/doc/index.rst @@ -1,7 +1,4 @@ -.. _we_ophelia1ev_nrf52805: - -Ophelia-I EV NRF52805 -##################### +.. zephyr:board:: we_ophelia1ev Overview ******** @@ -22,12 +19,6 @@ the following devices: * :abbr:`UART (Universal asynchronous receiver-transmitter)` * :abbr:`WDT (Watchdog Timer)` -.. figure:: img/we_ophelia1ev_nrf52805.jpg - :align: center - :alt: Ophelia-I EV - - Ophelia-I EV (Credit: Würth Elektronik) - Hardware ******** diff --git a/boards/we/orthosie1ev/Kconfig b/boards/we/orthosie1ev/Kconfig new file mode 100644 index 00000000000..acfac103f8c --- /dev/null +++ b/boards/we/orthosie1ev/Kconfig @@ -0,0 +1,6 @@ +# Copyright (c) Würth Elektronik GmbH & Co. KG +# SPDX-License-Identifier: Apache-2.0 + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 4096 diff --git a/boards/we/orthosie1ev/Kconfig.sysbuild b/boards/we/orthosie1ev/Kconfig.sysbuild new file mode 100644 index 00000000000..7f06e9b17fe --- /dev/null +++ b/boards/we/orthosie1ev/Kconfig.sysbuild @@ -0,0 +1,10 @@ +# Copyright (c) 2024 Würth Elektronik GmbH & Co. KG +# SPDX-License-Identifier: Apache-2.0 + +choice BOOTLOADER + default BOOTLOADER_MCUBOOT +endchoice + +choice BOOT_SIGNATURE_TYPE + default BOOT_SIGNATURE_TYPE_NONE +endchoice diff --git a/boards/we/orthosie1ev/Kconfig.we_orthosie1ev b/boards/we/orthosie1ev/Kconfig.we_orthosie1ev new file mode 100644 index 00000000000..ec731e24f3f --- /dev/null +++ b/boards/we/orthosie1ev/Kconfig.we_orthosie1ev @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Würth Elektronik GmbH & Co. KG +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_WE_ORTHOSIE1EV + select SOC_ESP32C3 diff --git a/boards/we/orthosie1ev/board.cmake b/boards/we/orthosie1ev/board.cmake new file mode 100644 index 00000000000..2f04d1fe886 --- /dev/null +++ b/boards/we/orthosie1ev/board.cmake @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +if(NOT "${OPENOCD}" MATCHES "^${ESPRESSIF_TOOLCHAIN_PATH}/.*") + set(OPENOCD OPENOCD-NOTFOUND) +endif() +find_program(OPENOCD openocd PATHS ${ESPRESSIF_TOOLCHAIN_PATH}/openocd-esp32/bin NO_DEFAULT_PATH) + +include(${ZEPHYR_BASE}/boards/common/esp32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/we/orthosie1ev/board.yml b/boards/we/orthosie1ev/board.yml new file mode 100644 index 00000000000..28762af893d --- /dev/null +++ b/boards/we/orthosie1ev/board.yml @@ -0,0 +1,6 @@ +board: + name: we_orthosie1ev + full_name: Orthosie-I-EV + vendor: we + socs: + - name: esp32c3 diff --git a/boards/we/orthosie1ev/doc/img/we_orthosie1ev.webp b/boards/we/orthosie1ev/doc/img/we_orthosie1ev.webp new file mode 100644 index 00000000000..aff718ad805 Binary files /dev/null and b/boards/we/orthosie1ev/doc/img/we_orthosie1ev.webp differ diff --git a/boards/we/orthosie1ev/doc/index.rst b/boards/we/orthosie1ev/doc/index.rst new file mode 100644 index 00000000000..f6fdb4d5546 --- /dev/null +++ b/boards/we/orthosie1ev/doc/index.rst @@ -0,0 +1,251 @@ +.. zephyr:board:: we_orthosie1ev + +Overview +******** + +Orthosie-I-EV is an entry-level development board based on Orthosie-I, +a module named for its small size. This board integrates complete Wi-Fi and Bluetooth® Low Energy functions. +For more information, check `Orthosie-I Website`_. + +Hardware +******** + +ESP32-C3 is a single-core Wi-Fi and Bluetooth 5 (LE) microcontroller SoC, +based on the open-source RISC-V architecture. It strikes the right balance of power, +I/O capabilities and security, thus offering the optimal cost-effective +solution for connected devices. +The availability of Wi-Fi and Bluetooth 5 (LE) connectivity not only makes the device configuration easy, +but it also facilitates a variety of use-cases based on dual connectivity. + +The features include the following: + +- 32-bit core RISC-V microcontroller with a maximum clock speed of 160 MHz +- 400 KB of internal RAM +- 802.11b/g/n/e/i +- A Bluetooth LE subsystem that supports features of Bluetooth 5 and Bluetooth Mesh +- Various peripherals: + + - 12-bit ADC with up to 6 channels + - TWAI compatible with CAN bus 2.0 + - Temperature sensor + - 3x SPI + - 1x I2S + - 1x I2C + - 2x UART + - LED PWM with up to 6 channels + +- Cryptographic hardware acceleration (RNG, ECC, RSA, SHA-2, AES) + +For more information, check the datasheet at `ESP32-C3 Datasheet`_ or the technical reference +manual at `ESP32-C3 Technical Reference Manual`_. + +Supported Features +================== + +Currently Zephyr's ``we_orthosie1ev`` board target supports the following features: + ++------------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++============+============+=====================================+ +| UART | on-chip | serial port | ++------------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++------------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++------------+------------+-------------------------------------+ +| USB-JTAG | on-chip | hardware interface | ++------------+------------+-------------------------------------+ +| SPI Master | on-chip | spi | ++------------+------------+-------------------------------------+ +| Timers | on-chip | counter | ++------------+------------+-------------------------------------+ +| Watchdog | on-chip | watchdog | ++------------+------------+-------------------------------------+ +| TRNG | on-chip | entropy | ++------------+------------+-------------------------------------+ +| LEDC | on-chip | pwm | ++------------+------------+-------------------------------------+ +| SPI DMA | on-chip | spi | ++------------+------------+-------------------------------------+ +| TWAI | on-chip | can | ++------------+------------+-------------------------------------+ +| USB-CDC | on-chip | serial | ++------------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++------------+------------+-------------------------------------+ +| Wi-Fi | on-chip | | ++------------+------------+-------------------------------------+ +| Bluetooth | on-chip | | ++------------+------------+-------------------------------------+ + +System requirements +******************* + +Prerequisites +============= + +Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command +below to retrieve those files. + +.. code-block:: console + + west blobs fetch hal_espressif + +.. note:: + + It is recommended running the command above after :file:`west update`. + +Building & Flashing +******************* + +Simple boot +=========== + +The board could be loaded using the single binary image, without 2nd stage bootloader. +It is the default option when building the application without additional configuration. + +.. note:: + + Simple boot does not provide any security features nor OTA updates. + +MCUboot bootloader +================== + +User may choose to use MCUboot bootloader instead. In that case the bootloader +must be built (and flashed) at least once. + +There are two options to be used when building an application: + +1. Sysbuild +2. Manual build + +.. note:: + + User can select the MCUboot bootloader by adding the following line + to the board default configuration file. + + .. code:: cfg + + CONFIG_BOOTLOADER_MCUBOOT=y + +Sysbuild +======== + +The sysbuild makes possible to build and flash all necessary images needed to +bootstrap the board with the ESP32 SoC. + +To build the sample application using sysbuild use the command: + +.. zephyr-app-commands:: + :tool: west + :zephyr-app: samples/hello_world + :board: orthosie1ev + :goals: build + :west-args: --sysbuild + :compact: + +By default, the ESP32 sysbuild creates bootloader (MCUboot) and application +images. But it can be configured to create other kind of images. + +Build directory structure created by sysbuild is different from traditional +Zephyr build. Output is structured by the domain subdirectories: + +.. code-block:: + + build/ + ├── hello_world + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + ├── mcuboot + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + └── domains.yaml + +.. note:: + + With ``--sysbuild`` option the bootloader will be re-build and re-flash + every time the pristine build is used. + +For more information about the system build please read the :ref:`sysbuild` documentation. + +Manual build +============ + +During the development cycle, it is intended to build & flash as quickly possible. +For that reason, images can be built one at a time using traditional build. + +The instructions following are relevant for both manual build and sysbuild. +The only difference is the structure of the build directory. + +.. note:: + + Remember that bootloader (MCUboot) needs to be flash at least once. + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: orthosie1ev + :goals: build + +The usual ``flash`` target will work with the ``orthosie1ev`` board +configuration. Here is an example for the :zephyr:code-sample:`hello_world` +application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: orthosie1ev + :goals: flash + +Open the serial monitor using the following command: + +.. code-block:: shell + + west espressif monitor + +After the board has automatically reset and booted, you should see the following +message in the monitor: + +.. code-block:: console + + ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** + Hello World! orthosie1ev + +Debugging +********* + +As with much custom hardware, the ESP32-C3 modules require patches to +OpenOCD that are not upstreamed yet. Espressif maintains their own fork of +the project. The custom OpenOCD can be obtained at `OpenOCD ESP32`_. + +The Zephyr SDK uses a bundled version of OpenOCD by default. You can overwrite that behavior by adding the +``-DOPENOCD= -DOPENOCD_DEFAULT_PATH=`` +parameter when building. + +Here is an example for building the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: orthosie1ev + :goals: build flash + :gen-args: -DOPENOCD= -DOPENOCD_DEFAULT_PATH= + +You can debug an application in the usual way. Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: orthosie1ev + :goals: debug + +References +********** + +.. target-notes:: + +.. _`Orthosie-I Website`: https://www.we-online.com/en/components/products/ORTHOSIE-I +.. _`ESP32-C3 Datasheet`: https://www.espressif.com/sites/default/files/documentation/esp32-c3_datasheet_en.pdf +.. _`ESP32-C3 Technical Reference Manual`: https://espressif.com/sites/default/files/documentation/esp32-c3_technical_reference_manual_en.pdf +.. _`OpenOCD ESP32`: https://github.com/espressif/openocd-esp32/releases diff --git a/boards/we/orthosie1ev/support/openocd.cfg b/boards/we/orthosie1ev/support/openocd.cfg new file mode 100644 index 00000000000..92a792fecb8 --- /dev/null +++ b/boards/we/orthosie1ev/support/openocd.cfg @@ -0,0 +1,11 @@ +set ESP_RTOS none + +# ESP32C3 has built-in JTAG interface over USB port in pins GPIO18/GPIO19 (D-/D+). +# Uncomment the line below to enable USB debugging. +# source [find interface/esp_usb_jtag.cfg] + +# Otherwise, use external JTAG programmer as ESP-Prog +source [find interface/ftdi/esp32_devkitj_v1.cfg] + +source [find target/esp32c3.cfg] +adapter speed 5000 diff --git a/boards/we/orthosie1ev/we_orthosie1ev-pinctrl.dtsi b/boards/we/orthosie1ev/we_orthosie1ev-pinctrl.dtsi new file mode 100644 index 00000000000..881f1b3808d --- /dev/null +++ b/boards/we/orthosie1ev/we_orthosie1ev-pinctrl.dtsi @@ -0,0 +1,66 @@ +/* + * Copyright (c) Würth Elektronik GmbH & Co. KG + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +&pinctrl { + + uart0_default: uart0_default { + group1 { + pinmux = ; + output-high; + }; + group2 { + pinmux = ; + bias-pull-up; + }; + }; + + spim2_default: spim2_default { + group1 { + pinmux = , + , + ; + }; + group2 { + pinmux = ; + output-low; + }; + }; + + i2c0_default: i2c0_default { + group1 { + pinmux = , + ; + bias-pull-up; + drive-open-drain; + output-high; + }; + }; + + i2s_default: i2s_default { + group1 { + pinmux = , + , + , + ; + output-enable; + }; + group2 { + pinmux = ; + input-enable; + }; + }; + + twai_default: twai_default { + group1 { + pinmux = , + ; + }; + }; +}; diff --git a/boards/we/orthosie1ev/we_orthosie1ev.dts b/boards/we/orthosie1ev/we_orthosie1ev.dts new file mode 100644 index 00000000000..a0c27fc81bb --- /dev/null +++ b/boards/we/orthosie1ev/we_orthosie1ev.dts @@ -0,0 +1,109 @@ +/* + * Copyright (c) 2024 Würth Elektronik GmbH & Co. KG + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "we_orthosie1ev-pinctrl.dtsi" +#include +#include + +/ { + model = "we_orthosie1ev"; + compatible = "we,we-orthosie1ev"; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + zephyr,bt-hci = &esp32_bt_hci; + }; + + aliases { + sw0 = &user_button1; + i2c-0 = &i2c0; + watchdog0 = &wdt0; + }; + + gpio_keys { + compatible = "gpio-keys"; + user_button1: button_1 { + label = "User SW1"; + gpios = <&gpio0 3 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + zephyr,code = ; + }; + }; +}; + +&flash0 { + reg = <0x0 DT_SIZE_M(4)>; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; +}; + +&usb_serial { + /* requires resoldering of resistors on the board */ + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = ; + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; +}; + +&i2s { + pinctrl-0 = <&i2s_default>; + pinctrl-names = "default"; + status = "disabled"; +}; + +&trng0 { + status = "okay"; +}; + +&spi2 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim2_default>; + pinctrl-names = "default"; +}; + +&gpio0 { + status = "okay"; +}; + +&wdt0 { + status = "okay"; +}; + +&timer0 { + status = "disabled"; +}; + +&timer1 { + status = "disabled"; +}; + +&twai { + /* requires external CAN transceiver or jumper on RX and TX pins for loopback testing */ + status = "disabled"; + pinctrl-0 = <&twai_default>; + pinctrl-names = "default"; +}; + +&esp32_bt_hci { + status = "okay"; +}; diff --git a/boards/we/orthosie1ev/we_orthosie1ev.yaml b/boards/we/orthosie1ev/we_orthosie1ev.yaml new file mode 100644 index 00000000000..0033d158343 --- /dev/null +++ b/boards/we/orthosie1ev/we_orthosie1ev.yaml @@ -0,0 +1,19 @@ +identifier: we_orthosie1ev +name: we_orthosie1ev +type: mcu +arch: riscv +toolchain: + - zephyr +supported: + - adc + - gpio + - i2c + - i2s + - watchdog + - uart + - dma + - pwm + - spi + - counter + - entropy +vendor: we diff --git a/boards/we/orthosie1ev/we_orthosie1ev_defconfig b/boards/we/orthosie1ev/we_orthosie1ev_defconfig new file mode 100644 index 00000000000..ef633ce56a1 --- /dev/null +++ b/boards/we/orthosie1ev/we_orthosie1ev_defconfig @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_GPIO=y diff --git a/boards/we/proteus2ev/Kconfig.defconfig b/boards/we/proteus2ev/Kconfig.defconfig index dcdfd0a06e0..1733a45b3ab 100644 --- a/boards/we/proteus2ev/Kconfig.defconfig +++ b/boards/we/proteus2ev/Kconfig.defconfig @@ -3,7 +3,4 @@ if BOARD_WE_PROTEUS2EV_NRF52832 -config BT_CTLR - default BT - endif diff --git a/boards/we/proteus2ev/doc/index.rst b/boards/we/proteus2ev/doc/index.rst index 19a7df8fbac..938258249a1 100644 --- a/boards/we/proteus2ev/doc/index.rst +++ b/boards/we/proteus2ev/doc/index.rst @@ -1,7 +1,4 @@ -.. _we_proteus2ev_nrf52832: - -Würth Elektronik Proteus-II-EV -############################## +.. zephyr:board:: we_proteus2ev Overview ******** @@ -25,12 +22,6 @@ the following devices: * :abbr:`UART (Universal asynchronous receiver-transmitter)` * :abbr:`WDT (Watchdog Timer)` -.. figure:: img/we_proteus2ev_nrf52832.jpg - :align: center - :alt: Proteus-II EV - - Proteus-II-EV (Credit: Würth Elektronik) - More information about the radio module can be found the Würth Elektronik web page https://www.we-online.com/katalog/de/PROTEUS-II . diff --git a/boards/we/proteus3ev/Kconfig.defconfig b/boards/we/proteus3ev/Kconfig.defconfig index ef564abbcbc..a75ef22e02f 100644 --- a/boards/we/proteus3ev/Kconfig.defconfig +++ b/boards/we/proteus3ev/Kconfig.defconfig @@ -3,7 +3,4 @@ if BOARD_WE_PROTEUS3EV -config BT_CTLR - default BT - endif # BOARD_WE_PROTEUS3EV diff --git a/boards/we/proteus3ev/doc/index.rst b/boards/we/proteus3ev/doc/index.rst index 87180a801b4..8c8b855cc5d 100644 --- a/boards/we/proteus3ev/doc/index.rst +++ b/boards/we/proteus3ev/doc/index.rst @@ -1,7 +1,4 @@ -.. _we_proteus3ev_nrf52840: - -Würth Elektronik Proteus-III-EV -############################### +.. zephyr:board:: we_proteus3ev Overview ******** @@ -25,12 +22,6 @@ nRF52840 ARM Cortex-M4F CPU and the following devices: * :abbr:`UART (Universal asynchronous receiver-transmitter)` * :abbr:`WDT (Watchdog Timer)` -.. figure:: img/we_proteus3ev_nrf52840.jpg - :align: center - :alt: Proteus-III EV - - Proteus-III EV (Credit: Würth Elektronik) - More information about the radio module can be found the Würth Elektronik web page https://www.we-online.com/katalog/de/PROTEUS-III . diff --git a/boards/weact/blackpill_f401cc/blackpill_f401cc.dts b/boards/weact/blackpill_f401cc/blackpill_f401cc.dts index 1fdecac9704..07d48c5497c 100644 --- a/boards/weact/blackpill_f401cc/blackpill_f401cc.dts +++ b/boards/weact/blackpill_f401cc/blackpill_f401cc.dts @@ -125,7 +125,7 @@ zephyr_udc0: &usbotg_fs { &adc1 { pinctrl-0 = <&adc1_in1_pa1>; pinctrl-names = "default"; - st,adc-clock-source = ; + st,adc-clock-source = "SYNC"; st,adc-prescaler = <2>; status = "okay"; }; diff --git a/boards/weact/blackpill_f401cc/blackpill_f401cc.yaml b/boards/weact/blackpill_f401cc/blackpill_f401cc.yaml index 2601e64546b..b8f88615acd 100644 --- a/boards/weact/blackpill_f401cc/blackpill_f401cc.yaml +++ b/boards/weact/blackpill_f401cc/blackpill_f401cc.yaml @@ -9,7 +9,6 @@ toolchain: supported: - counter - spi - - usb - i2c - uart - pwm diff --git a/boards/weact/blackpill_f401cc/doc/index.rst b/boards/weact/blackpill_f401cc/doc/index.rst index 79e30862e87..e5ea1e7f699 100644 --- a/boards/weact/blackpill_f401cc/doc/index.rst +++ b/boards/weact/blackpill_f401cc/doc/index.rst @@ -1,7 +1,4 @@ -.. _blackpill_f401cc: - -WeAct Studio Black Pill V1.2 -############################ +.. zephyr:board:: blackpill_f401cc Overview ******** @@ -12,10 +9,6 @@ This is the 48-pin variant of the STM32F401x series, see `STM32F401x reference manual`_. More info about the board available `here `_ and on `WeAct Github`_. -.. image:: img/blackpill-v3.jpg - :align: center - :alt: Black Pill V3.0+ - Hardware ******** @@ -44,7 +37,7 @@ hardware components: Supported Features ================== -The Zephyr blackpill_f401ce board configuration supports the following +The Zephyr blackpill_f401cc board configuration supports the following hardware features: +------------+------------+-------------------------------------+ @@ -72,7 +65,7 @@ hardware features: +------------+------------+-------------------------------------+ The default configuration can be found in -:zephyr_file:`boards/weact/blackpill_f401ce/blackpill_f401ce_defconfig` +:zephyr_file:`boards/weact/blackpill_f401cc/blackpill_f401cc_defconfig` Pin Mapping =========== diff --git a/boards/weact/blackpill_f401ce/blackpill_f401ce.dts b/boards/weact/blackpill_f401ce/blackpill_f401ce.dts index d670a327019..04d490d0f79 100644 --- a/boards/weact/blackpill_f401ce/blackpill_f401ce.dts +++ b/boards/weact/blackpill_f401ce/blackpill_f401ce.dts @@ -125,7 +125,7 @@ zephyr_udc0: &usbotg_fs { &adc1 { pinctrl-0 = <&adc1_in1_pa1>; pinctrl-names = "default"; - st,adc-clock-source = ; + st,adc-clock-source = "SYNC"; st,adc-prescaler = <2>; status = "okay"; }; diff --git a/boards/weact/blackpill_f401ce/blackpill_f401ce.yaml b/boards/weact/blackpill_f401ce/blackpill_f401ce.yaml index 813781644f2..5f44db28d39 100644 --- a/boards/weact/blackpill_f401ce/blackpill_f401ce.yaml +++ b/boards/weact/blackpill_f401ce/blackpill_f401ce.yaml @@ -9,7 +9,6 @@ toolchain: supported: - counter - spi - - usb - i2c - uart - pwm diff --git a/boards/weact/blackpill_f401ce/doc/index.rst b/boards/weact/blackpill_f401ce/doc/index.rst index eb4983577ae..aa81976e7d9 100644 --- a/boards/weact/blackpill_f401ce/doc/index.rst +++ b/boards/weact/blackpill_f401ce/doc/index.rst @@ -1,7 +1,4 @@ -.. _blackpill_f401ce: - -WeAct Studio Black Pill V3.0 -############################ +.. zephyr:board:: blackpill_f401ce Overview ******** @@ -12,10 +9,6 @@ This is the 48-pin variant of the STM32F401x series, see `STM32F401x reference manual`_. More info about the board available `here `_ and on `WeAct Github`_. -.. image:: img/blackpill-v3.jpg - :align: center - :alt: Black Pill V3.0+ - Hardware ******** diff --git a/boards/weact/blackpill_f411ce/blackpill_f411ce.dts b/boards/weact/blackpill_f411ce/blackpill_f411ce.dts index d53bfa5f021..5acd309cbc9 100644 --- a/boards/weact/blackpill_f411ce/blackpill_f411ce.dts +++ b/boards/weact/blackpill_f411ce/blackpill_f411ce.dts @@ -126,7 +126,7 @@ zephyr_udc0: &usbotg_fs { &adc1 { pinctrl-0 = <&adc1_in1_pa1>; pinctrl-names = "default"; - st,adc-clock-source = ; + st,adc-clock-source = "SYNC"; st,adc-prescaler = <2>; status = "okay"; }; diff --git a/boards/weact/blackpill_f411ce/blackpill_f411ce.yaml b/boards/weact/blackpill_f411ce/blackpill_f411ce.yaml index d0b145fc1e4..f93ce7397cd 100644 --- a/boards/weact/blackpill_f411ce/blackpill_f411ce.yaml +++ b/boards/weact/blackpill_f411ce/blackpill_f411ce.yaml @@ -9,7 +9,6 @@ toolchain: supported: - counter - spi - - usb - i2c - uart - pwm diff --git a/boards/weact/blackpill_f411ce/doc/index.rst b/boards/weact/blackpill_f411ce/doc/index.rst index f190d7ea64a..f045f331b86 100644 --- a/boards/weact/blackpill_f411ce/doc/index.rst +++ b/boards/weact/blackpill_f411ce/doc/index.rst @@ -1,7 +1,4 @@ -.. _blackpill_f411ce: - -WeAct Studio Black Pill V2.0 -############################ +.. zephyr:board:: blackpill_f411ce Overview ******** @@ -12,10 +9,6 @@ This is the 48-pin variant of the STM32F411x series, see `STM32F411x reference manual`_. More info about the board available `here `_ and on `WeAct Github`_. -.. image:: img/blackpill-v2.jpg - :align: center - :alt: Black Pill V2.0+ - Hardware ******** diff --git a/boards/weact/mini_stm32h743/Kconfig.defconfig b/boards/weact/mini_stm32h743/Kconfig.defconfig index 6817cc3f5f7..3ebe575aff6 100644 --- a/boards/weact/mini_stm32h743/Kconfig.defconfig +++ b/boards/weact/mini_stm32h743/Kconfig.defconfig @@ -12,7 +12,7 @@ config INPUT if LVGL -config LV_COLOR_16_SWAP +configdefault LV_COLOR_16_SWAP default y config LV_Z_BITS_PER_PIXEL @@ -22,14 +22,6 @@ endif # LVGL endif # DISPLAY -if USB_DEVICE_STACK - -config UART_CONSOLE - default CONSOLE - -config USB_DEVICE_INITIALIZE_AT_BOOT - default y - -endif # USB_DEVICE_STACK +source "boards/common/usb/Kconfig.cdc_acm_serial.defconfig" endif # BOARD_MINI_STM32H743 diff --git a/boards/weact/mini_stm32h743/doc/img/stm32h7xx.webp b/boards/weact/mini_stm32h743/doc/img/mini_stm32h743.webp similarity index 100% rename from boards/weact/mini_stm32h743/doc/img/stm32h7xx.webp rename to boards/weact/mini_stm32h743/doc/img/mini_stm32h743.webp diff --git a/boards/weact/mini_stm32h743/doc/index.rst b/boards/weact/mini_stm32h743/doc/index.rst index 9b63292ad57..9dc96700d5b 100644 --- a/boards/weact/mini_stm32h743/doc/index.rst +++ b/boards/weact/mini_stm32h743/doc/index.rst @@ -1,7 +1,4 @@ -.. mini_stm32h743: - -WeAct Studio MiniSTM32H743 Core Board -##################################### +.. zephyr:board:: mini_stm32h743 Overview ******** @@ -27,12 +24,6 @@ Key Features - SWD header for external debugger - 2x 40-pin GPIO connector -.. figure:: img/stm32h7xx.webp - :align: center - :alt: MiniSTM32H743 Core Board - - MiniSTM32H743 Core Board (Credit: WeAct Studio) - More information about the board can be found on the `Mini_STM32H743 website`_. Hardware diff --git a/boards/weact/mini_stm32h743/mini_stm32h743.dts b/boards/weact/mini_stm32h743/mini_stm32h743.dts index 9968b82d7d7..abec39683d4 100644 --- a/boards/weact/mini_stm32h743/mini_stm32h743.dts +++ b/boards/weact/mini_stm32h743/mini_stm32h743.dts @@ -15,8 +15,6 @@ compatible = "weact,mini-stm32h743"; chosen { - zephyr,console = &usb_cdc_acm_uart; - zephyr,shell-uart = &usb_cdc_acm_uart; zephyr,sram = &sram0; zephyr,flash = &flash0; zephyr,display = &st7735r_160x80; @@ -49,7 +47,7 @@ st7735r_160x80: st7735r@0 { compatible = "sitronix,st7735r"; mipi-max-frequency = <20000000>; - mipi-mode = ; + mipi-mode = "MIPI_DBI_MODE_SPI_4WIRE"; reg = <0>; width = <160>; height = <80>; @@ -83,6 +81,29 @@ watchdog0 = &iwdg; sdhc0 = &sdmmc1; }; + + dcmi_camera_connector: connector_dcmi_camera { + compatible = "weact,dcmi-camera-connector"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + + gpio-map = <3 0 &gpiob 9 0>, /* DVP_SDA (I2C1_SDA) */ + <5 0 &gpiob 8 0>, /* DVP_SCL (I2C1_SCL) */ + <7 0 &gpiob 7 0>, /* DVP_VSYNC */ + <8 0 &gpioa 7 0>, /* DVP_PWDN */ + <9 0 &gpioa 4 0>, /* DVP_HSYNC */ + <12 0 &gpioe 6 0>, /* DVP_D7 */ + <13 0 &gpioa 8 0>, /* DVP_XCLK (RCC_MCO1) */ + <14 0 &gpioe 5 0>, /* DVP_D6 */ + <16 0 &gpiod 3 0>, /* DVP_D5 */ + <17 0 &gpioa 6 0>, /* DVP_PCLK */ + <18 0 &gpioe 4 0>, /* DVP_D4 */ + <19 0 &gpioc 6 0>, /* DVP_D0 */ + <20 0 &gpioe 1 0>, /* DVP_D3 */ + <21 0 &gpioc 7 0>, /* DVP_D1 */ + <22 0 &gpioe 0 0>; /* DVP_D2 */ + }; }; &clk_lsi { @@ -132,12 +153,10 @@ zephyr_udc0: &usbotg_fs { pinctrl-0 = <&usb_otg_fs_dm_pa11 &usb_otg_fs_dp_pa12>; pinctrl-names = "default"; status = "okay"; - - usb_cdc_acm_uart: cdc_acm_uart { - compatible = "zephyr,cdc-acm-uart"; - }; }; +#include <../boards/common/usb/cdc_acm_serial.dtsi> + &quadspi { pinctrl-names = "default"; pinctrl-0 = <&quadspi_clk_pb2 &quadspi_bk1_ncs_pb6 @@ -148,7 +167,7 @@ zephyr_udc0: &usbotg_fs { w25q64_qspi: qspi-nor-flash@90000000 { compatible = "st,stm32-qspi-nor"; - reg = <0x90000000 DT_SIZE_M(64)>; /* 64 Mbits */ + reg = <0x90000000 DT_SIZE_M(8)>; /* 64 Mbits */ qspi-max-frequency = <40000000>; status = "okay"; spi-bus-width = <4>; @@ -159,7 +178,7 @@ zephyr_udc0: &usbotg_fs { #address-cells = <1>; #size-cells = <1>; slot0_partition: partition@0 { - reg = <0x00000000 DT_SIZE_M(64)>; + reg = <0x00000000 DT_SIZE_M(8)>; }; }; }; @@ -186,7 +205,7 @@ zephyr_udc0: &usbotg_fs { #size-cells = <1>; storage_partition: partition@0 { label = "storage"; - reg = <0x00000000 DT_SIZE_M(64)>; + reg = <0x00000000 DT_SIZE_M(8)>; }; }; }; @@ -220,3 +239,15 @@ zephyr_udc0: &usbotg_fs { &iwdg1 { status = "okay"; }; + +zephyr_camera_i2c: &i2c1 { + pinctrl-0 = <&i2c1_scl_pb8 &i2c1_sda_pb9>; + pinctrl-names = "default"; +}; + +zephyr_camera_dvp: &dcmi { + pinctrl-0 = <&dcmi_hsync_pa4 &dcmi_pixclk_pa6 &dcmi_vsync_pb7 + &dcmi_d0_pc6 &dcmi_d1_pc7 &dcmi_d2_pe0 &dcmi_d3_pe1 + &dcmi_d4_pe4 &dcmi_d5_pd3 &dcmi_d6_pe5 &dcmi_d7_pe6>; + pinctrl-names = "default"; +}; diff --git a/boards/weact/mini_stm32h743/mini_stm32h743.yaml b/boards/weact/mini_stm32h743/mini_stm32h743.yaml index b92c045ee23..10edcbb5ed2 100644 --- a/boards/weact/mini_stm32h743/mini_stm32h743.yaml +++ b/boards/weact/mini_stm32h743/mini_stm32h743.yaml @@ -14,6 +14,6 @@ supported: - spi - backup_sram - watchdog - - usb - qspi + - video vendor: weact diff --git a/boards/weact/mini_stm32h743/mini_stm32h743_defconfig b/boards/weact/mini_stm32h743/mini_stm32h743_defconfig index 809e85276c9..7feee60d01c 100644 --- a/boards/weact/mini_stm32h743/mini_stm32h743_defconfig +++ b/boards/weact/mini_stm32h743/mini_stm32h743_defconfig @@ -15,9 +15,3 @@ CONFIG_CONSOLE=y # Enable GPIO CONFIG_GPIO=y - -# Logger cannot use itself to log -CONFIG_USB_CDC_ACM_LOG_LEVEL_OFF=y - -# Enable USB -CONFIG_USB_DEVICE_STACK=y diff --git a/boards/weact/mini_stm32h7b0/Kconfig.defconfig b/boards/weact/mini_stm32h7b0/Kconfig.defconfig new file mode 100644 index 00000000000..4286c38d989 --- /dev/null +++ b/boards/weact/mini_stm32h7b0/Kconfig.defconfig @@ -0,0 +1,35 @@ +# Copyright (c) 2024 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +# WeAct Studio MiniSTM32H7B0 board configuration + +if BOARD_MINI_STM32H7B0 + +if DISPLAY + +config INPUT + default y + +if LVGL + +configdefault LV_COLOR_16_SWAP + default y + +config LV_Z_BITS_PER_PIXEL + default 16 + +endif # LVGL + +endif # DISPLAY + +if USB_DEVICE_STACK + +config UART_CONSOLE + default CONSOLE + +config USB_DEVICE_INITIALIZE_AT_BOOT + default y + +endif # USB_DEVICE_STACK + +endif # BOARD_MINI_STM32H7B0 diff --git a/boards/weact/mini_stm32h7b0/Kconfig.mini_stm32h7b0 b/boards/weact/mini_stm32h7b0/Kconfig.mini_stm32h7b0 new file mode 100644 index 00000000000..cf900ccd670 --- /dev/null +++ b/boards/weact/mini_stm32h7b0/Kconfig.mini_stm32h7b0 @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MINI_STM32H7B0 + select SOC_STM32H7B0XX diff --git a/boards/weact/mini_stm32h7b0/board.cmake b/boards/weact/mini_stm32h7b0/board.cmake new file mode 100644 index 00000000000..cf935a32ffa --- /dev/null +++ b/boards/weact/mini_stm32h7b0/board.cmake @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(dfu-util "--pid=0483:df11" "--alt=0" "--dfuse") +board_runner_args(jlink "--device=STM32H7B0VB" "--speed=4000") + +include(${ZEPHYR_BASE}/boards/common/dfu-util.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/weact/mini_stm32h7b0/board.yml b/boards/weact/mini_stm32h7b0/board.yml new file mode 100644 index 00000000000..9baae2f9f96 --- /dev/null +++ b/boards/weact/mini_stm32h7b0/board.yml @@ -0,0 +1,6 @@ +board: + name: mini_stm32h7b0 + full_name: MiniSTM32H7B0 Core Board + vendor: weact + socs: + - name: stm32h7b0xx diff --git a/boards/weact/mini_stm32h7b0/doc/img/mini_stm32h7b0.webp b/boards/weact/mini_stm32h7b0/doc/img/mini_stm32h7b0.webp new file mode 100644 index 00000000000..7f92df0963b Binary files /dev/null and b/boards/weact/mini_stm32h7b0/doc/img/mini_stm32h7b0.webp differ diff --git a/boards/weact/mini_stm32h7b0/doc/index.rst b/boards/weact/mini_stm32h7b0/doc/index.rst new file mode 100644 index 00000000000..8cf425d5570 --- /dev/null +++ b/boards/weact/mini_stm32h7b0/doc/index.rst @@ -0,0 +1,234 @@ +.. zephyr:board:: mini_stm32h7b0 + +Overview +******** + +The MiniSTM32H7B0 Core board is a compact development board equipped with +an STM32H7B0VBT6 microcontroller. It features a variety of peripherals, +including a user LED and button, a display, and external SPI and QuadSPI +NOR flash memory. + +Key Features + +- STM32 microcontroller in LQFP100 package +- USB OTG or full-speed device +- 1 user LED +- User, boot, and reset push-buttons +- 32.768 kHz and 25MHz HSE crystal oscillators +- External NOR Flash memories: 64-Mbit Quad-SPI and 64-Mbit SPI +- Board connectors: + + - Camera (8 bit) connector + - ST7735 TFT-LCD 160 x 80 pixels (RGB565 3-SPI) + - microSD |trade| card + - USB Type-C Connector + - SWD header for external debugger + - 2x 40-pin GPIO connector + + +More information about the board can be found on the `Mini_STM32H7B0 website`_. + +Hardware +******** + +The MiniSTM32H7B0 Core board provides the following hardware components: + +- STM32H7B0VBT6 in LQFP100 package +- ARM 32-bit Cortex-M7 CPU with FPU +- Chrom-ART Accelerator +- Hardware JPEG Codec +- 280 MHz max CPU frequency +- VDD from 1.62 V to 3.6 V +- 128 KB Flash +- 1.4 MB SRAM +- High-resolution timer (2.1 ns) +- 32-bit timers(2) +- 16-bit timers(10) +- SPI(5) +- I2C(4) +- I2S (4) +- USART(5) +- UART(5) +- USB OTG Full Speed and High Speed(1) +- CAN FD(2) +- SAI(4) +- SPDIF_Rx(4) +- HDMI_CEC(1) +- Dual Mode Quad SPI(1) +- Camera Interface +- GPIO (up to 80) with external interrupt capability +- 16-bit ADC(2) with 16 channels +- 12-bit DAC with 2 channels(2) +- True Random Number Generator (RNG) +- 16-channel DMA +- LCD-TFT Controller with XGA resolution + +More information about STM32H7BO can be found here: + +- `STM32H7B0VB on www.st.com`_ +- `STM32H7B0VB reference manual`_ +- `STM32H7B0VB datasheet`_ + +Supported Features +================== + +The ``mini_stm32h7b0`` board target supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| QSPI NOR | on-chip | off-chip flash | ++-----------+------------+-------------------------------------+ +| SDMMC | on-chip | disk access | ++-----------+------------+-------------------------------------+ +| DISPLAY | on-chip | display | ++-----------+------------+-------------------------------------+ + +Other hardware features have not been enabled yet for this board. + +The default configuration per core can be found in the defconfig file: +:zephyr_file:`boards/weact/mini_stm32h7b0/mini_stm32h7b0_defconfig` + +Pin Mapping +=========== + +MiniSTM32H7B0 Core board has 5 GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +For more details please refer to `Mini_STM32H7B0 website`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +The MiniSTM32H7B0 Core board is configured as follows + +- USER_LED : PE3 +- USER_PB : PC13 +- SPI1 SCK/MISO/MOSI/NSS : PB3/PB4/PD7/PD6 (NOR Flash memory) +- SPI4 SCK/MOSI/NSS : PE12/PE14/PE11 (LCD) +- QuadSPI CLK/NCS/IO0/IO1/IO2/IO3 : PB2/PB6/PD11/PD12/PE2/PD13 (NOR Flash memory) +- SDMMC1 CLK/DCMD/CD/D0/D1/D2/D3 : PC12/PD2/PD4/PC8/PC9/PC10/PC11 (microSD card) +- USB DM/DP : PA11/PA12 (USB CDC ACM) + +System Clock +============ + +The STM32H7B0VB System Clock can be driven by an internal or external oscillator, +as well as by the main PLL clock. By default, the System clock is driven +by the PLL clock at 280MHz. PLL clock is fed by a 25MHz high speed external clock. + +Serial Port (USB CDC ACM) +========================= + +The Zephyr console output is assigned to the USB CDC ACM virtual serial port. +Virtual COM port interface. Default communication settings are 115200 8N1. + +Programming and Debugging +************************* + +The MiniSTM32H7B0 Core board facilitates firmware flashing via the USB DFU +bootloader. This method simplifies the process of updating images, although +it doesn't provide debugging capabilities. However, the board provides header +pins for the Serial Wire Debug (SWD) interface, which can be used to connect +an external debugger, such as ST-Link. + +Flashing +======== + +To activate the bootloader, follow these steps: + +1. Press and hold the BOOT0 key. +2. While still holding the BOOT0 key, press and release the RESET key. +3. Wait for 0.5 seconds, then release the BOOT0 key. + +Upon successful execution of these steps, the device will transition into +bootloader mode and present itself as a USB DFU Mode device. You can program +the device using the west tool or the STM32CubeProgrammer. + +Flashing an application to MiniSTM32H7B0 +---------------------------------------- + +Here is an example for the :zephyr:code-sample:`hello_world` application. + +First, put the board in bootloader mode as described above. Then build and flash +the application in the usual way. Just add ``CONFIG_BOOT_DELAY=5000`` to the +configuration, so that USB CDC ACM is initialized before any text is printed, +as below: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: mini_stm32h7b0 + :goals: build flash + :gen-args: -DCONFIG_BOOT_DELAY=5000 + +Run a serial host program to connect with your board: + +.. code-block:: console + + $ minicom -D -b 115200 + +Then, press the RESET button, you should see the following message after few seconds: + +.. code-block:: console + + Hello World! mini_stm32h7b0 + +Replace :code:`` with the port where the board XIAO BLE +can be found. For example, under Linux, :code:`/dev/ttyACM0`. + +Debugging +--------- + +This current Zephyr port does not support debugging. + +Testing the LEDs in the MiniSTM32H7B0 +************************************* + +There is a sample that allows to test that LED on the board are working +properly with Zephyr: + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: mini_stm32h7b0 + :goals: build flash + :gen-args: -DCONFIG_BOOT_DELAY=5000 + +You can build and flash the examples to make sure Zephyr is running correctly on +your board. The LED definitions can be found in +:zephyr_file:`boards/weact/mini_stm32h7b0/mini_stm32h7b0.dts`. + +Testing shell over USB in the MiniSTM32H7B0 +******************************************* + +There is a sample that allows to test shell interface over USB CDC ACM interface +with Zephyr: + +.. zephyr-app-commands:: + :zephyr-app: samples/subsys/shell/shell_module + :board: mini_stm32h7b0 + :goals: build flash + :gen-args: -DCONFIG_BOOT_DELAY=5000 + +.. _Mini_STM32H7B0 website: + https://github.com/WeActStudio/WeActStudio.MiniSTM32H7B0 + +.. _STM32H7B0VB on www.st.com: + https://www.st.com/en/microcontrollers-microprocessors/stm32h7b0vb.html + +.. _STM32H7B0VB reference manual: + https://www.st.com/resource/en/reference_manual/rm0455-stm32h7a37b3-and-stm32h7b0-value-line-advanced-armbased-32bit-mcus-stmicroelectronics.pdf + +.. _STM32H7B0VB datasheet: + https://www.st.com/resource/en/datasheet/stm32h7b0vb.pdf diff --git a/boards/weact/mini_stm32h7b0/mini_stm32h7b0.dts b/boards/weact/mini_stm32h7b0/mini_stm32h7b0.dts new file mode 100644 index 00000000000..cc09b5dda68 --- /dev/null +++ b/boards/weact/mini_stm32h7b0/mini_stm32h7b0.dts @@ -0,0 +1,223 @@ +/* + * Copyright (c) 2024 Linaro Limited + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include +#include + +/ { + model = "WeAct Studio MiniSTM32H7B0 Core Board"; + compatible = "weact,mini-stm32h7b0"; + + chosen { + zephyr,console = &usb_cdc_acm_uart; + zephyr,shell-uart = &usb_cdc_acm_uart; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,display = &st7735r_160x80; + }; + + leds { + compatible = "gpio-leds"; + user_led: led { + gpios = <&gpioe 3 GPIO_ACTIVE_HIGH>; + label = "User LED"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + user_button: button { + label = "User PB"; + gpios = <&gpioc 13 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; + zephyr,code = ; + }; + }; + + mipi_dbi_st7735r_160x80 { + compatible = "zephyr,mipi-dbi-spi"; + spi-dev = <&spi4>; + dc-gpios = <&gpioe 13 GPIO_ACTIVE_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + + st7735r_160x80: st7735r@0 { + compatible = "sitronix,st7735r"; + mipi-max-frequency = <20000000>; + mipi-mode = "MIPI_DBI_MODE_SPI_4WIRE"; + reg = <0>; + width = <160>; + height = <80>; + inversion-on; + rgb-is-inverted; + x-offset = <1>; + y-offset = <26>; + pwctr1 = [A2 02 84]; + pwctr2 = [C5]; + pwctr3 = [0A 00]; + pwctr4 = [8A 2A]; + pwctr5 = [8A EE]; + invctr = <7>; + frmctr1 = [01 2C 2D]; + frmctr2 = [01 2C 2D]; + frmctr3 = [01 2C 2D 01 2C 2D]; + vmctr1 = <14>; + gamctrp1 = [02 1C 07 12 37 32 29 2D 29 25 2B 39 00 01 03 10]; + gamctrn1 = [03 1D 07 06 2E 2C 29 2D 2E 2E 37 3F 00 00 02 10]; + colmod = <5>; + /* Set D3 (RGB) bit to 1. LV_COLOR_16_SWAP is enabled by default */ + madctl = <120>; /* Set to <184> to rotate the image 180 degrees. */ + caset = [00 01 00 a0]; + raset = [00 1a 00 69]; + }; + }; + + aliases { + led0 = &user_led; + sw0 = &user_button; + watchdog0 = &iwdg; + sdhc0 = &sdmmc1; + }; +}; + +&clk_lsi { + status = "okay"; +}; + +&clk_hsi48 { + status = "okay"; +}; + +&clk_hse { + clock-frequency = ; + status = "okay"; +}; + +&pll { + div-m = <5>; + mul-n = <112>; + div-p = <2>; + div-q = <2>; + div-r = <2>; + clocks = <&clk_hse>; + status = "okay"; +}; + +&rcc { + clocks = <&pll>; + clock-frequency = ; + d1cpre = <1>; + hpre = <2>; + d1ppre = <1>; + d2ppre1 = <1>; + d2ppre2 = <1>; + d3ppre = <1>; +}; + +&sdmmc1 { + pinctrl-0 = <&sdmmc1_d0_pc8 &sdmmc1_d1_pc9 + &sdmmc1_d2_pc10 &sdmmc1_d3_pc11 + &sdmmc1_ck_pc12 &sdmmc1_cmd_pd2>; + pinctrl-names = "default"; + cd-gpios = <&gpiod 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; + status = "okay"; +}; + +zephyr_udc0: &usbotg_hs { + pinctrl-0 = <&usb_otg_hs_dm_pa11 &usb_otg_hs_dp_pa12>; + pinctrl-names = "default"; + status = "okay"; + + usb_cdc_acm_uart: cdc_acm_uart { + compatible = "zephyr,cdc-acm-uart"; + }; +}; + + +&octospi1 { + pinctrl-names = "default"; + pinctrl-0 = <&octospim_p1_clk_pb2 &octospim_p1_ncs_pb6 + &octospim_p1_io0_pd11 &octospim_p1_io1_pd12 + &octospim_p1_io2_pe2 &octospim_p1_io3_pd13>; + status = "okay"; + + w25q64_qspi: ospi-nor-flash@90000000 { + compatible = "st,stm32-ospi-nor"; + reg = <0x90000000 DT_SIZE_M(64)>; /* 64 Mbits */ + ospi-max-frequency = <40000000>; + status = "okay"; + spi-bus-width = <4>; + data-rate = ; + writeoc = "PP_1_1_4"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + slot0_partition: partition@0 { + reg = <0x00000000 DT_SIZE_M(64)>; + }; + }; + }; +}; + +&spi1 { + pinctrl-0 = <&spi1_sck_pb3 &spi1_miso_pb4 &spi1_mosi_pd7>; + cs-gpios = <&gpiod 6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + status = "okay"; + w25q64_spi: spi-nor-flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <40000000>; + size = ; /* 64 Mbits */ + status = "okay"; + jedec-id = [ef 40 17]; + has-dpd; + t-enter-dpd = <3500>; + t-exit-dpd = <3500>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + storage_partition: partition@0 { + label = "storage"; + reg = <0x00000000 DT_SIZE_M(64)>; + }; + }; + }; +}; + +&gpioe { + status = "okay"; + + lcd_led { + gpio-hog; + gpios = <10 GPIO_ACTIVE_LOW>; + output-high; + }; +}; + +&spi4 { + pinctrl-0 = <&spi4_sck_pe12 &spi4_mosi_pe14>; + cs-gpios = <&gpioe 11 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + status = "okay"; +}; + +&rng { + status = "okay"; +}; + +&backup_sram { + status = "okay"; +}; + +&iwdg1 { + status = "okay"; +}; diff --git a/boards/weact/mini_stm32h7b0/mini_stm32h7b0.yaml b/boards/weact/mini_stm32h7b0/mini_stm32h7b0.yaml new file mode 100644 index 00000000000..d9904423aa6 --- /dev/null +++ b/boards/weact/mini_stm32h7b0/mini_stm32h7b0.yaml @@ -0,0 +1,19 @@ +identifier: mini_stm32h7b0 +name: WeAct Studio MiniSTM32H7B0 Core Board +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 512 +flash: 2048 +supported: + - gpio + - counter + - spi + - backup_sram + - watchdog + - qspi + - video +vendor: weact diff --git a/boards/weact/mini_stm32h7b0/mini_stm32h7b0_defconfig b/boards/weact/mini_stm32h7b0/mini_stm32h7b0_defconfig new file mode 100644 index 00000000000..77c7a720619 --- /dev/null +++ b/boards/weact/mini_stm32h7b0/mini_stm32h7b0_defconfig @@ -0,0 +1,23 @@ +# Copyright (c) 2024 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable HW stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y + +# Enable GPIO +CONFIG_GPIO=y + +# Logger cannot use itself to log +CONFIG_USB_CDC_ACM_LOG_LEVEL_OFF=y + +# Enable USB +CONFIG_USB_DEVICE_STACK=y diff --git a/boards/weact/stm32f405_core/doc/index.rst b/boards/weact/stm32f405_core/doc/index.rst index e08ec5cb787..3afc69b79d0 100644 --- a/boards/weact/stm32f405_core/doc/index.rst +++ b/boards/weact/stm32f405_core/doc/index.rst @@ -1,7 +1,4 @@ -.. _weact_stm32f405_core: - -WeAct Studio STM32F405 Core Board V1.0 -###################################### +.. zephyr:board:: weact_stm32f405_core Overview ******** @@ -12,10 +9,6 @@ This is the 64-pin variant of the STM32F405x series, see `STM32F405x reference manual`_. More info about the board available on `WeAct Github`_. -.. image:: img/stm32f405_core.jpg - :align: center - :alt: STM32F405 Core Board v1.0 - Hardware ******** diff --git a/boards/weact/stm32f405_core/weact_stm32f405_core.yaml b/boards/weact/stm32f405_core/weact_stm32f405_core.yaml index 880770c6913..e1f98a41ce4 100644 --- a/boards/weact/stm32f405_core/weact_stm32f405_core.yaml +++ b/boards/weact/stm32f405_core/weact_stm32f405_core.yaml @@ -13,7 +13,6 @@ supported: - spi - i2c - uart - - usb - can - gpio - watchdog diff --git a/boards/weact/stm32g431_core/doc/index.rst b/boards/weact/stm32g431_core/doc/index.rst index bf6f80009d5..862398794f6 100644 --- a/boards/weact/stm32g431_core/doc/index.rst +++ b/boards/weact/stm32g431_core/doc/index.rst @@ -1,7 +1,4 @@ -.. _weact_stm32g431_core: - -WeAct Studio STM32G431 Core Board -################################# +.. zephyr:board:: weact_stm32g431_core The WeAct STM32G431 Core Board is a low-cost bare-bones STM32G431-based development board. See the `STM32G431CB website`_ for more information about the MCU. More information diff --git a/boards/weact/stm32g431_core/weact_stm32g431_core.dts b/boards/weact/stm32g431_core/weact_stm32g431_core.dts index ca6dfcf6569..1038536369f 100644 --- a/boards/weact/stm32g431_core/weact_stm32g431_core.dts +++ b/boards/weact/stm32g431_core/weact_stm32g431_core.dts @@ -154,7 +154,7 @@ stm32_lp_tick_source: &lptim1 { &adc2 { pinctrl-0 = <&adc2_in12_pb2>; pinctrl-names = "default"; - st,adc-clock-source = ; + st,adc-clock-source = "SYNC"; st,adc-prescaler = <4>; #address-cells = <1>; diff --git a/boards/weact/usb2canfdv1/Kconfig.usb2canfdv1 b/boards/weact/usb2canfdv1/Kconfig.usb2canfdv1 new file mode 100644 index 00000000000..76072f6297a --- /dev/null +++ b/boards/weact/usb2canfdv1/Kconfig.usb2canfdv1 @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Henrik Brix Andersen +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_USB2CANFDV1 + select SOC_STM32G0B1XX diff --git a/boards/weact/usb2canfdv1/board.cmake b/boards/weact/usb2canfdv1/board.cmake new file mode 100644 index 00000000000..07c49fc8644 --- /dev/null +++ b/boards/weact/usb2canfdv1/board.cmake @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Henrik Brix Andersen +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=STM32G0B1CB") + +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/weact/usb2canfdv1/board.yml b/boards/weact/usb2canfdv1/board.yml new file mode 100644 index 00000000000..4608eaaa2df --- /dev/null +++ b/boards/weact/usb2canfdv1/board.yml @@ -0,0 +1,6 @@ +board: + name: usb2canfdv1 + full_name: USB2CANFDV1 + vendor: weact + socs: + - name: stm32g0b1xx diff --git a/boards/weact/usb2canfdv1/doc/index.rst b/boards/weact/usb2canfdv1/doc/index.rst new file mode 100644 index 00000000000..1ea39dcd4be --- /dev/null +++ b/boards/weact/usb2canfdv1/doc/index.rst @@ -0,0 +1,62 @@ +.. zephyr:board:: usb2canfdv1 + +Overview +******** + +The WeAct Studio USB2CANFDV1 is a dedicated USB to CAN FD adapter board. More information can be +found on the `USB2CANFDV1 website`_. + +Hardware +******** + +The USB2CANFDV1 is equipped with a STM32G0B1CBT6 microcontroller and features a USB-C connector, a +terminal block for connecting to the CAN bus, and three LEDs. + +Supported Features +================== + +The ``usb2canfdv1`` board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| USB | on-chip | USB | ++-----------+------------+-------------------------------------+ +| FDCAN1 | on-chip | CAN controller | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/weact/usb2canfdv1/usb2canfdv1_defconfig`. + +Other hardware features are not currently supported by the port. + +System Clock +============ + +The STM32G0B1CBT6 PLL is driven by an external crystal oscillator (HSE) running at 16 MHz and +configured to provide a system clock of 60 MHz. This allows generating a FDCAN1 core clock of 80 +MHz. + +Programming and Debugging +************************* + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: usb2canfdv1 + :goals: flash + +.. _USB2CANFDV1 website: + https://github.com/WeActStudio/WeActStudio.USB2CANFDV1 diff --git a/boards/weact/usb2canfdv1/doc/usb2canfdv1.webp b/boards/weact/usb2canfdv1/doc/usb2canfdv1.webp new file mode 100644 index 00000000000..a1c4e3e24af Binary files /dev/null and b/boards/weact/usb2canfdv1/doc/usb2canfdv1.webp differ diff --git a/boards/weact/usb2canfdv1/usb2canfdv1.dts b/boards/weact/usb2canfdv1/usb2canfdv1.dts new file mode 100644 index 00000000000..b67f2692e3d --- /dev/null +++ b/boards/weact/usb2canfdv1/usb2canfdv1.dts @@ -0,0 +1,108 @@ +/* + * Copyright (c) 2024 Henrik Brix Andersen + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include + +/ { + model = "WeAct USB2CANFDV1 board"; + compatible = "weact,usb2canfdv1"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + zephyr,canbus = &fdcan1; + }; + + aliases { + led0 = &led_ready; + led1 = &led_rxd; + led2 = &led_txd; + mcuboot-led0 = &led_ready; + }; + + leds { + compatible = "gpio-leds"; + led_ready: led_ready { + gpios = <&gpioa 2 GPIO_ACTIVE_LOW>; + label = "LED READY"; + }; + led_rxd: led_rxd { + gpios = <&gpioa 0 GPIO_ACTIVE_LOW>; + label = "LED RXD"; + }; + led_txd: led_txd { + gpios = <&gpioa 1 GPIO_ACTIVE_LOW>; + label = "LED TXD"; + }; + }; +}; + +&clk_hse { + status = "okay"; + clock-frequency = ; +}; + +&clk_hsi48 { + status = "okay"; + crs-usb-sof; +}; + +&pll { + div-m = <1>; + mul-n = <15>; + div-p = <2>; + div-q = <3>; + div-r = <4>; + clocks = <&clk_hse>; + status = "okay"; +}; + +&rcc { + clocks = <&pll>; + clock-frequency = ; + ahb-prescaler = <1>; + apb1-prescaler = <1>; +}; + +zephyr_udc0: &usb { + pinctrl-0 = <&usb_dm_pa11 &usb_dp_pa12>; + pinctrl-names = "default"; + status = "okay"; +}; + +&fdcan1 { + clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00001000>, + <&rcc STM32_SRC_PLL_Q FDCAN_SEL(1)>; + pinctrl-0 = <&fdcan1_rx_pb8 &fdcan1_tx_pb9>; + pinctrl-names = "default"; + status = "okay"; + + can-transceiver { + max-bitrate = <5000000>; + }; +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 DT_SIZE_K(48)>; + read-only; + }; + slot0_partition: partition@c000 { + label = "image-0"; + reg = <0x0000c000 DT_SIZE_K(80)>; + }; + }; +}; diff --git a/boards/weact/usb2canfdv1/usb2canfdv1.yaml b/boards/weact/usb2canfdv1/usb2canfdv1.yaml new file mode 100644 index 00000000000..8fb61f88e14 --- /dev/null +++ b/boards/weact/usb2canfdv1/usb2canfdv1.yaml @@ -0,0 +1,16 @@ +identifier: usb2canfdv1 +name: WeAct USB2CANFDV1 +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 144 +flash: 128 +supported: + - can + - gpio + - usb_device + - usbd +vendor: weact diff --git a/boards/weact/usb2canfdv1/usb2canfdv1_defconfig b/boards/weact/usb2canfdv1/usb2canfdv1_defconfig new file mode 100644 index 00000000000..90c77db2fff --- /dev/null +++ b/boards/weact/usb2canfdv1/usb2canfdv1_defconfig @@ -0,0 +1,2 @@ +CONFIG_ARM_MPU=y +CONFIG_GPIO=y diff --git a/boards/wemos/esp32s2_lolin_mini/Kconfig b/boards/wemos/esp32s2_lolin_mini/Kconfig new file mode 100644 index 00000000000..03ec3c08d38 --- /dev/null +++ b/boards/wemos/esp32s2_lolin_mini/Kconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2023 Google, LLC +# SPDX-License-Identifier: Apache-2.0 + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 4096 diff --git a/boards/wemos/esp32s2_lolin_mini/Kconfig.defconfig b/boards/wemos/esp32s2_lolin_mini/Kconfig.defconfig deleted file mode 100644 index 85fdb266956..00000000000 --- a/boards/wemos/esp32s2_lolin_mini/Kconfig.defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# ESP32S2 LOLIN S2 MINI board configuration - -# Copyright (c) 2023 Google, LLC -# SPDX-License-Identifier: Apache-2.0 - -config ENTROPY_GENERATOR - default y - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 32768 if WIFI - default 4096 diff --git a/boards/wemos/esp32s2_lolin_mini/doc/index.rst b/boards/wemos/esp32s2_lolin_mini/doc/index.rst index d09dec2b5f9..c9ce4b23068 100644 --- a/boards/wemos/esp32s2_lolin_mini/doc/index.rst +++ b/boards/wemos/esp32s2_lolin_mini/doc/index.rst @@ -1,7 +1,4 @@ -.. _esp32s2_lolin_mini: - -ESP32-S2 Lolin Mini -################### +.. zephyr:board:: esp32s2_lolin_mini Overview ******** @@ -30,10 +27,6 @@ The features include the following: - DAC - LED PWM with up to 8 channels -.. figure:: img/esp32_s2_lolin_mini.jpg - :align: center - :alt: ESP32-S2 LOLIN MINI - System requirements ******************* @@ -91,6 +84,8 @@ message in the monitor: References ********** +.. target-notes:: + .. [1] https://www.espressif.com/en/products/socs/esp32-s2 .. _`ESP32S2 Technical Reference Manual`: https://espressif.com/sites/default/files/documentation/esp32-s2_technical_reference_manual_en.pdf .. _`ESP32S2 Datasheet`: https://www.espressif.com/sites/default/files/documentation/esp32-s2_datasheet_en.pdf diff --git a/boards/wemos/esp32s2_lolin_mini/esp32s2_lolin_mini.dts b/boards/wemos/esp32s2_lolin_mini/esp32s2_lolin_mini.dts index 14d6fd4b1d8..66761886e55 100644 --- a/boards/wemos/esp32s2_lolin_mini/esp32s2_lolin_mini.dts +++ b/boards/wemos/esp32s2_lolin_mini/esp32s2_lolin_mini.dts @@ -9,6 +9,7 @@ #include #include #include "esp32s2_lolin_mini-pinctrl.dtsi" +#include / { model = "Wemos ESP32S2-Lolin Mini"; @@ -46,6 +47,10 @@ }; }; +&flash0 { + reg = <0x0 DT_SIZE_M(4)>; +}; + &uart0 { status = "okay"; current-speed = <115200>; @@ -81,47 +86,6 @@ status = "okay"; }; -&flash0 { - reg = <0x0 DT_SIZE_M(4)>; - - status = "okay"; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Reserve 60kB for the bootloader */ - boot_partition: partition@1000 { - label = "mcuboot"; - reg = <0x00001000 0x0000F000>; - read-only; - }; - - /* Reserve 1024kB for the application in slot 0 */ - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 0x00100000>; - }; - - /* Reserve 1024kB for the application in slot 1 */ - slot1_partition: partition@110000 { - label = "image-1"; - reg = <0x00110000 0x00100000>; - }; - - /* Reserve 256kB for the scratch partition */ - scratch_partition: partition@210000 { - label = "image-scratch"; - reg = <0x00210000 0x00040000>; - }; - - storage_partition: partition@250000 { - label = "storage"; - reg = <0x00250000 0x00006000>; - }; - }; -}; - &wdt0 { status = "okay"; }; diff --git a/boards/wemos/esp32s2_lolin_mini/esp32s2_lolin_mini.yaml b/boards/wemos/esp32s2_lolin_mini/esp32s2_lolin_mini.yaml index 763b8c838f4..fcc4d03a44f 100644 --- a/boards/wemos/esp32s2_lolin_mini/esp32s2_lolin_mini.yaml +++ b/boards/wemos/esp32s2_lolin_mini/esp32s2_lolin_mini.yaml @@ -10,6 +10,5 @@ supported: - uart testing: ignore_tags: - - net - bluetooth vendor: wemos diff --git a/boards/witte/linum/doc/index.rst b/boards/witte/linum/doc/index.rst index 537807a7979..43466abdfc8 100644 --- a/boards/witte/linum/doc/index.rst +++ b/boards/witte/linum/doc/index.rst @@ -1,7 +1,4 @@ -.. _linum: - -Witte Technology Linum Board -############################ +.. zephyr:board:: linum Overview ******** @@ -11,10 +8,6 @@ touchscreen and another for access to other peripherals of microcontroller. Also of communications interfaces like UART with RS232 and RS485 capabillities, CAN bus compatible to FD standard, and networking over Ethernet. -.. image:: img/linum-stm32h753bi-top.jpg - :align: center - :alt: Linum development board - Hardware ******** diff --git a/boards/witte/linum/linum.dts b/boards/witte/linum/linum.dts index d4846f3e1c7..fe2280ec117 100644 --- a/boards/witte/linum/linum.dts +++ b/boards/witte/linum/linum.dts @@ -203,7 +203,7 @@ zephyr_udc0: &usbotg_fs { &adc1 { pinctrl-0 = <&adc1_inp15_pa3>; pinctrl-names = "default"; - st,adc-clock-source = ; + st,adc-clock-source = "SYNC"; st,adc-prescaler = <4>; status = "okay"; }; diff --git a/boards/wiznet/w5500_evb_pico/Kconfig b/boards/wiznet/w5500_evb_pico/Kconfig new file mode 100644 index 00000000000..0c91d9e23ae --- /dev/null +++ b/boards/wiznet/w5500_evb_pico/Kconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2021 Yonatan Schachter +# Copyright (c) 2023 Ian Wakely +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_W5500_EVB_PICO + select RP2_FLASH_W25Q080 diff --git a/boards/wiznet/w5500_evb_pico/Kconfig.defconfig b/boards/wiznet/w5500_evb_pico/Kconfig.defconfig index a159b56f52a..016942be74f 100644 --- a/boards/wiznet/w5500_evb_pico/Kconfig.defconfig +++ b/boards/wiznet/w5500_evb_pico/Kconfig.defconfig @@ -4,9 +4,6 @@ if BOARD_W5500_EVB_PICO -config RP2_FLASH_W25Q080 - default y - if NETWORKING config NET_L2_ETHERNET diff --git a/boards/wiznet/w5500_evb_pico/board.cmake b/boards/wiznet/w5500_evb_pico/board.cmake index e95d4d3767f..a52ac5d15e0 100644 --- a/boards/wiznet/w5500_evb_pico/board.cmake +++ b/boards/wiznet/w5500_evb_pico/board.cmake @@ -13,7 +13,7 @@ # The value must be the 'stem' part of the name of one of the files # in the openocd interface configuration file. # The setting is store to CMakeCache.txt. -if ("${RPI_PICO_DEBUG_ADAPTER}" STREQUAL "") +if("${RPI_PICO_DEBUG_ADAPTER}" STREQUAL "") set(RPI_PICO_DEBUG_ADAPTER "cmsis-dap") endif() diff --git a/boards/wiznet/w5500_evb_pico/w5500_evb_pico-pinctrl.dtsi b/boards/wiznet/w5500_evb_pico/w5500_evb_pico-pinctrl.dtsi index 761354420c6..747b0d04e40 100644 --- a/boards/wiznet/w5500_evb_pico/w5500_evb_pico-pinctrl.dtsi +++ b/boards/wiznet/w5500_evb_pico/w5500_evb_pico-pinctrl.dtsi @@ -54,7 +54,4 @@ input-enable; }; }; - - clocks_default: clocks_default { - }; }; diff --git a/boards/wiznet/w5500_evb_pico/w5500_evb_pico.dts b/boards/wiznet/w5500_evb_pico/w5500_evb_pico.dts index c14cb0b7d64..3f853ce0605 100644 --- a/boards/wiznet/w5500_evb_pico/w5500_evb_pico.dts +++ b/boards/wiznet/w5500_evb_pico/w5500_evb_pico.dts @@ -9,7 +9,7 @@ #include -#include +#include #include "w5500_evb_pico-pinctrl.dtsi" #include @@ -112,11 +112,6 @@ }; }; -&clocks { - pinctrl-0 = <&clocks_default>; - pinctrl-names = "default"; -}; - &uart0 { current-speed = <115200>; status = "okay"; diff --git a/boards/xen/xenvm/Kconfig.defconfig b/boards/xen/xenvm/Kconfig.defconfig index 965dc9cda33..66ef1066e4c 100644 --- a/boards/xen/xenvm/Kconfig.defconfig +++ b/boards/xen/xenvm/Kconfig.defconfig @@ -7,6 +7,6 @@ config BUILD_OUTPUT_BIN default y config HEAP_MEM_POOL_SIZE - default 16384 if BOARD_XENVM_XENVM + default 16384 endif # BOARD_XENVM diff --git a/boards/xen/xenvm/xenvm_xenvm_gicv3_defconfig b/boards/xen/xenvm/xenvm_xenvm_gicv3_defconfig new file mode 100644 index 00000000000..2115f9175bd --- /dev/null +++ b/boards/xen/xenvm/xenvm_xenvm_gicv3_defconfig @@ -0,0 +1,13 @@ +# Enable UART driver +CONFIG_SERIAL=y + +CONFIG_MAX_XLAT_TABLES=24 + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable logging subsys +CONFIG_LOG=y +CONFIG_LOG_MODE_MINIMAL=n +CONFIG_TIMER_READS_ITS_FREQUENCY_AT_RUNTIME=y diff --git a/cmake/compiler/arcmwdt/compiler_flags.cmake b/cmake/compiler/arcmwdt/compiler_flags.cmake index 6b334c1fe84..7234afc0c80 100644 --- a/cmake/compiler/arcmwdt/compiler_flags.cmake +++ b/cmake/compiler/arcmwdt/compiler_flags.cmake @@ -167,7 +167,9 @@ set_compiler_property(PROPERTY imacros -imacros) # Security canaries. #no support of -mstack-protector-guard=global" -set_compiler_property(PROPERTY security_canaries -fstack-protector-all) +set_compiler_property(PROPERTY security_canaries -fstack-protector) +set_compiler_property(PROPERTY security_canaries_strong -fstack-protector-strong) +set_compiler_property(PROPERTY security_canaries_all -fstack-protector-all) #no support of _FORTIFY_SOURCE" set_compiler_property(PROPERTY security_fortify_compile_time) diff --git a/cmake/compiler/compiler_flags_template.cmake b/cmake/compiler/compiler_flags_template.cmake index 5a4386f49be..447db04a2d3 100644 --- a/cmake/compiler/compiler_flags_template.cmake +++ b/cmake/compiler/compiler_flags_template.cmake @@ -92,6 +92,9 @@ set_compiler_property(PROPERTY coverage) # Security canaries flags. set_compiler_property(PROPERTY security_canaries) +set_compiler_property(PROPERTY security_canaries_strong) +set_compiler_property(PROPERTY security_canaries_all) +set_compiler_property(PROPERTY security_canaries_explicit) set_compiler_property(PROPERTY security_fortify_compile_time) set_compiler_property(PROPERTY security_fortify_run_time) @@ -143,3 +146,6 @@ set_compiler_property(PROPERTY no_builtin_malloc) # Compiler flag for defining specs. Used only by gcc, other compilers may keep # this undefined. set_compiler_property(PROPERTY specs) + +# Compiler flag for defining preinclude files. +set_compiler_property(PROPERTY include_file) diff --git a/cmake/compiler/gcc/compiler_flags.cmake b/cmake/compiler/gcc/compiler_flags.cmake index c346a750af4..204df61d01a 100644 --- a/cmake/compiler/gcc/compiler_flags.cmake +++ b/cmake/compiler/gcc/compiler_flags.cmake @@ -23,7 +23,7 @@ set_compiler_property(PROPERTY optimization_size -Os) set_compiler_property(PROPERTY optimization_size_aggressive -Oz) if(CMAKE_C_COMPILER_VERSION GREATER_EQUAL "4.5.0") - set_compiler_property(PROPERTY optimization_lto -flto) + set_compiler_property(PROPERTY optimization_lto -flto=auto) set_compiler_property(PROPERTY prohibit_lto -fno-lto) endif() @@ -59,7 +59,7 @@ set_compiler_property(PROPERTY warning_dw_1 ) check_set_compiler_property(APPEND PROPERTY warning_dw_1 -Wlogical-op - -Wmissing-field-initializers + -Wno-missing-field-initializers ) set_compiler_property(PROPERTY warning_dw_2 @@ -71,6 +71,7 @@ set_compiler_property(PROPERTY warning_dw_2 -Wpointer-arith -Wredundant-decls -Wswitch-default + -Wmissing-field-initializers ) check_set_compiler_property(APPEND PROPERTY warning_dw_2 -Wpacked-bitfield-compat @@ -166,13 +167,22 @@ set_property(TARGET compiler-cpp PROPERTY no_rtti "-fno-rtti") set_compiler_property(PROPERTY coverage -fprofile-arcs -ftest-coverage -fno-inline) # Security canaries. -set_compiler_property(PROPERTY security_canaries -fstack-protector-all) +set_compiler_property(PROPERTY security_canaries -fstack-protector) +set_compiler_property(PROPERTY security_canaries_strong -fstack-protector-strong) +set_compiler_property(PROPERTY security_canaries_all -fstack-protector-all) +set_compiler_property(PROPERTY security_canaries_explicit -fstack-protector-explicit) # Only a valid option with GCC 7.x and above, so let's do check and set. if(CONFIG_STACK_CANARIES_TLS) check_set_compiler_property(APPEND PROPERTY security_canaries -mstack-protector-guard=tls) + check_set_compiler_property(APPEND PROPERTY security_canaries_strong -mstack-protector-guard=tls) + check_set_compiler_property(APPEND PROPERTY security_canaries_all -mstack-protector-guard=tls) + check_set_compiler_property(APPEND PROPERTY security_canaries_explicit -mstack-protector-guard=tls) else() check_set_compiler_property(APPEND PROPERTY security_canaries -mstack-protector-guard=global) + check_set_compiler_property(APPEND PROPERTY security_canaries_global -mstack-protector-guard=global) + check_set_compiler_property(APPEND PROPERTY security_canaries_all -mstack-protector-guard=global) + check_set_compiler_property(APPEND PROPERTY security_canaries_explicit -mstack-protector-guard=global) endif() @@ -243,3 +253,5 @@ set_compiler_property(PROPERTY no_builtin -fno-builtin) set_compiler_property(PROPERTY no_builtin_malloc -fno-builtin-malloc) set_compiler_property(PROPERTY specs -specs=) + +set_compiler_property(PROPERTY include_file -include) diff --git a/cmake/compiler/gcc/target_arc.cmake b/cmake/compiler/gcc/target_arc.cmake index e18fa468f16..d306fe1550f 100644 --- a/cmake/compiler/gcc/target_arc.cmake +++ b/cmake/compiler/gcc/target_arc.cmake @@ -8,5 +8,16 @@ if(NOT DEFINED GCC_ARC_TUNED_CPU) set(GCC_ARC_TUNED_CPU ${GCC_M_CPU}) endif() +# Flags not supported by llext linker +# (regexps are supported and match whole word) +set(LLEXT_REMOVE_FLAGS + -fno-pic + -fno-pie + -ffunction-sections + -fdata-sections + -g.* + -Os +) + list(APPEND TOOLCHAIN_C_FLAGS -mcpu=${GCC_ARC_TUNED_CPU}) list(APPEND TOOLCHAIN_LD_FLAGS -mcpu=${GCC_ARC_TUNED_CPU}) diff --git a/cmake/compiler/gcc/target_riscv.cmake b/cmake/compiler/gcc/target_riscv.cmake index b4875720c9b..a297a772886 100644 --- a/cmake/compiler/gcc/target_riscv.cmake +++ b/cmake/compiler/gcc/target_riscv.cmake @@ -71,3 +71,23 @@ endif() list(APPEND TOOLCHAIN_C_FLAGS -mabi=${riscv_mabi} -march=${riscv_march}) list(APPEND TOOLCHAIN_LD_FLAGS NO_SPLIT -mabi=${riscv_mabi} -march=${riscv_march}) + +# Flags not supported by llext linker +# (regexps are supported and match whole word) +set(LLEXT_REMOVE_FLAGS + -fno-pic + -fno-pie + -ffunction-sections + -fdata-sections + -g.* + -Os +) + +# Flags to be added to llext code compilation +# mno-relax is needed to stop gcc from generating R_RISCV_ALIGN relocations, +# which are currently not supported +set(LLEXT_APPEND_FLAGS + -mabi=${riscv_mabi} + -march=${riscv_march} + -mno-relax +) \ No newline at end of file diff --git a/cmake/compiler/gcc/target_xtensa.cmake b/cmake/compiler/gcc/target_xtensa.cmake index 5321204c2df..0b398023f67 100644 --- a/cmake/compiler/gcc/target_xtensa.cmake +++ b/cmake/compiler/gcc/target_xtensa.cmake @@ -3,8 +3,6 @@ # Flags not supported by llext linker # (regexps are supported and match whole word) set(LLEXT_REMOVE_FLAGS - -fno-pic - -fno-pie -ffunction-sections -fdata-sections -g.* @@ -14,7 +12,20 @@ set(LLEXT_REMOVE_FLAGS # Flags to be added to llext code compilation set(LLEXT_APPEND_FLAGS - -fPIC -nostdlib -nodefaultlibs ) + +if(CONFIG_LLEXT_BUILD_PIC) +set(LLEXT_REMOVE_FLAGS ${LLEXT_REMOVE_FLAGS} + -fno-pic + -fno-pie +) +set(LLEXT_APPEND_FLAGS ${LLEXT_APPEND_FLAGS} + -fPIC +) +else() +set(LLEXT_APPEND_FLAGS ${LLEXT_APPEND_FLAGS} + -ffreestanding +) +endif() diff --git a/cmake/compiler/xcc/compiler_flags.cmake b/cmake/compiler/xcc/compiler_flags.cmake index 28f76d5d809..4528b6a7421 100644 --- a/cmake/compiler/xcc/compiler_flags.cmake +++ b/cmake/compiler/xcc/compiler_flags.cmake @@ -15,3 +15,6 @@ set_compiler_property(PROPERTY no_position_independent "") # Remove after testing that -Wshadow works set_compiler_property(PROPERTY warning_shadow_variables) + +# xcc does not recognize -fno-printf-return-value +set_compiler_property(PROPERTY no_printf_return_value) diff --git a/cmake/compiler/xcc/generic.cmake b/cmake/compiler/xcc/generic.cmake index b6be58ceb9f..d9020bf59bf 100644 --- a/cmake/compiler/xcc/generic.cmake +++ b/cmake/compiler/xcc/generic.cmake @@ -17,13 +17,13 @@ TOOLCHAIN_VER: ${TOOLCHAIN_VER} endif() execute_process( - COMMAND ${CMAKE_C_COMPILER} --version + COMMAND ${CMAKE_C_COMPILER} --version ${XTENSA_CORE_LOCAL_C_FLAG} RESULT_VARIABLE ret OUTPUT_VARIABLE stdoutput ) if(ret) message(FATAL_ERROR "Executing the below command failed. Are permissions set correctly? - ${CMAKE_C_COMPILER} --version + ${CMAKE_C_COMPILER} --version ${XTENSA_CORE_LOCAL_C_FLAG} ${stdoutput} " ) diff --git a/cmake/compiler/xcc/target.cmake b/cmake/compiler/xcc/target.cmake index a23c9d5bde6..f9e9c721a15 100644 --- a/cmake/compiler/xcc/target.cmake +++ b/cmake/compiler/xcc/target.cmake @@ -40,11 +40,16 @@ foreach(file_name include/stddef.h include-fixed/limits.h) list(APPEND NOSTDINC ${_OUTPUT}) endforeach() -list(APPEND TOOLCHAIN_LIBS - gcc - hal +# This libgcc code is partially duplicated in compiler/*/target.cmake +execute_process( + COMMAND ${CMAKE_C_COMPILER} ${TOOLCHAIN_C_FLAGS} --print-libgcc-file-name + OUTPUT_VARIABLE LIBGCC_FILE_NAME + OUTPUT_STRIP_TRAILING_WHITESPACE ) +get_filename_component(LIBGCC_DIR ${LIBGCC_FILE_NAME} DIRECTORY) + +list(APPEND LIB_INCLUDE_DIR "-L\"${LIBGCC_DIR}\"") # For CMake to be able to test if a compiler flag is supported by the # toolchain we need to give CMake the necessary flags to compile and diff --git a/cmake/compiler/xt-clang/target.cmake b/cmake/compiler/xt-clang/target.cmake index 41a72aa782e..978bc7c7860 100644 --- a/cmake/compiler/xt-clang/target.cmake +++ b/cmake/compiler/xt-clang/target.cmake @@ -5,8 +5,6 @@ include(${ZEPHYR_BASE}/cmake/compiler/xcc/target.cmake) # Flags not supported by llext linker # (regexps are supported and match whole word) set(LLEXT_REMOVE_FLAGS - -fno-pic - -fno-pie -ffunction-sections -fdata-sections -g.* @@ -16,7 +14,21 @@ set(LLEXT_REMOVE_FLAGS # Flags to be added to llext code compilation set(LLEXT_APPEND_FLAGS - -fPIC -nostdlib -nodefaultlibs ) + +if(CONFIG_LLEXT_BUILD_PIC) +set(LLEXT_REMOVE_FLAGS ${LLEXT_REMOVE_FLAGS} + -fno-pic + -fno-pie +) +set(LLEXT_APPEND_FLAGS ${LLEXT_APPEND_FLAGS} + -fPIC +) +else() +set(LLEXT_APPEND_FLAGS ${LLEXT_APPEND_FLAGS} + -ffreestanding + -mno-generate-flix +) +endif() diff --git a/cmake/emu/qemu.cmake b/cmake/emu/qemu.cmake index cc47f48d1ff..11dead318fb 100644 --- a/cmake/emu/qemu.cmake +++ b/cmake/emu/qemu.cmake @@ -257,26 +257,27 @@ elseif(QEMU_NET_STACK) set_ifndef(NET_TOOLS ${ZEPHYR_BASE}/../tools/net-tools) # Default if not set list(APPEND PRE_QEMU_COMMANDS_FOR_server - COMMAND #Disable Ctrl-C to ensure that users won't accidentally exit #w/o killing the monitor. - stty intr ^d - COMMAND + COMMAND stty intr ^d + #This command is run in the background using '&'. This prevents #chaining other commands with '&&'. The command is enclosed in '{}' #to fix this. - { - ${NET_TOOLS}/monitor_15_4 - ${PCAP} - /tmp/ip-stack-server - /tmp/ip-stack-client - > /dev/null & + COMMAND { + ${NET_TOOLS}/monitor_15_4 + ${PCAP} + /tmp/ip-stack-server + /tmp/ip-stack-client + > /dev/null & } ) set(POST_QEMU_COMMANDS_FOR_server - COMMAND + # Re-enable Ctrl-C. + COMMAND stty intr ^c + # Kill the monitor_15_4 sub-process - pkill -P $$$$ + COMMAND pkill -P $$$$ ) endif() endif(QEMU_PIPE_STACK) diff --git a/cmake/emu/simics.cmake b/cmake/emu/simics.cmake index dee1305a1f1..f20c09f052a 100644 --- a/cmake/emu/simics.cmake +++ b/cmake/emu/simics.cmake @@ -1,30 +1,42 @@ -# Copyright (c) 2023 Intel Corporation +# Copyright (c) 2023-2024 Intel Corporation # # SPDX-License-Identifier: Apache-2.0 find_program( SIMICS NAMES simics + NO_DEFAULT_PATH + PATHS ENV SIMICS_PROJECT + # Search exactly for the project's autogenerated 'trampoline' script. ) -zephyr_get(SIMICS_SCRIPT_PATH SYSBUILD GLOBAL) -if(SIMICS_SCRIPT_PATH) - set(SIMICS_SCRIPT ${SIMICS_SCRIPT_PATH}) +if(SIMICS STREQUAL SIMICS-NOTFOUND) + message(WARNING "Simics simulator environment is not found at SIMICS_PROJECT:'${SIMICS_PROJECT}'") else() - set(SIMICS_SCRIPT ${BOARD_DIR}/support/${BOARD}.simics) -endif() + message(STATUS "Found Simics: ${SIMICS}") -get_property(SIMICS_ARGS GLOBAL PROPERTY "BOARD_EMU_ARGS_simics") + zephyr_get(SIMICS_SCRIPT_PATH SYSBUILD GLOBAL) + if(SIMICS_SCRIPT_PATH) + set(SIMICS_SCRIPT ${SIMICS_SCRIPT_PATH}) + else() + set(SIMICS_SCRIPT ${BOARD_DIR}/support/${BOARD}.simics) + endif() -add_custom_target(run_simics - COMMAND - ${SIMICS} - -no-gui - -no-win - ${SIMICS_SCRIPT} - ${SIMICS_ARGS} - -e run - WORKING_DIRECTORY ${APPLICATION_BINARY_DIR} - DEPENDS ${logical_target_for_zephyr_elf} - USES_TERMINAL - ) + get_property(SIMICS_ARGS GLOBAL PROPERTY "BOARD_EMU_ARGS_simics") + + add_custom_target(run_simics + COMMAND + ${SIMICS} + -no-gui + --no-win + --batch-mode + ${SIMICS_SCRIPT} + ${SIMICS_ARGS} + $ENV{SIMICS_EXTRA_ARGS} + -e run + WORKING_DIRECTORY ${APPLICATION_BINARY_DIR} + DEPENDS ${logical_target_for_zephyr_elf} + USES_TERMINAL + ) + +endif() diff --git a/cmake/flash/CMakeLists.txt b/cmake/flash/CMakeLists.txt index f948b059751..d1f0d17da6e 100644 --- a/cmake/flash/CMakeLists.txt +++ b/cmake/flash/CMakeLists.txt @@ -61,6 +61,8 @@ function(runners_yaml_append_config) runners_yaml_append(" uf2_file: ${uf2}") endif() + zephyr_get(OPENOCD) + zephyr_get(OPENOCD_DEFAULT_PATH) if(CMAKE_GDB OR OPENOCD OR OPENOCD_DEFAULT_PATH) runners_yaml_append(" # Host tools:") endif() @@ -152,7 +154,7 @@ endif() # Generate the flash, debug, debugserver, attach targets within the build # system itself. -foreach(target flash debug debugserver attach) +foreach(target flash debug debugserver attach rtt) if(target STREQUAL flash) set(comment "Flashing ${BOARD}") elseif(target STREQUAL debug) @@ -166,6 +168,8 @@ foreach(target flash debug debugserver attach) endif() elseif(target STREQUAL attach) set(comment "Debugging ${BOARD}") + elseif(target STREQUAL rtt) + set(comment "RTT ${BOARD}") endif() string(TOUPPER ${target} TARGET_UPPER) diff --git a/cmake/hex.cmake b/cmake/hex.cmake deleted file mode 100644 index f5eb586f7bd..00000000000 --- a/cmake/hex.cmake +++ /dev/null @@ -1,64 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -# This code was deprecated after Zephyr v3.5.0 -message(DEPRECATION "The to_hex() and from_hex() functions are deprecated. Please " - "use CMake's math(... OUTPUT_FORMAT ) instead.") - -# from https://gist.github.com/korzo89/71a6de0f388f7cf8b349101b0134060c -function(from_hex HEX DEC) - string(SUBSTRING "${HEX}" 2 -1 HEX) - string(TOUPPER "${HEX}" HEX) - set(_res 0) - string(LENGTH "${HEX}" _strlen) - - while(_strlen GREATER 0) - math(EXPR _res "${_res} * 16") - string(SUBSTRING "${HEX}" 0 1 NIBBLE) - string(SUBSTRING "${HEX}" 1 -1 HEX) - if(NIBBLE STREQUAL "A") - math(EXPR _res "${_res} + 10") - elseif(NIBBLE STREQUAL "B") - math(EXPR _res "${_res} + 11") - elseif(NIBBLE STREQUAL "C") - math(EXPR _res "${_res} + 12") - elseif(NIBBLE STREQUAL "D") - math(EXPR _res "${_res} + 13") - elseif(NIBBLE STREQUAL "E") - math(EXPR _res "${_res} + 14") - elseif(NIBBLE STREQUAL "F") - math(EXPR _res "${_res} + 15") - else() - math(EXPR _res "${_res} + ${NIBBLE}") - endif() - - string(LENGTH "${HEX}" _strlen) - endwhile() - - set(${DEC} ${_res} PARENT_SCOPE) -endfunction() - -function(to_hex DEC HEX) - if(DEC EQUAL 0) - set(${HEX} "0x0" PARENT_SCOPE) - return() - endif() - while(DEC GREATER 0) - math(EXPR _val "${DEC} % 16") - math(EXPR DEC "${DEC} / 16") - if(_val EQUAL 10) - set(_val "A") - elseif(_val EQUAL 11) - set(_val "B") - elseif(_val EQUAL 12) - set(_val "C") - elseif(_val EQUAL 13) - set(_val "D") - elseif(_val EQUAL 14) - set(_val "E") - elseif(_val EQUAL 15) - set(_val "F") - endif() - set(_res "${_val}${_res}") - endwhile() - set(${HEX} "0x${_res}" PARENT_SCOPE) -endfunction() diff --git a/cmake/linker/arcmwdt/target.cmake b/cmake/linker/arcmwdt/target.cmake index 4eaf824b7c0..389bbeb5845 100644 --- a/cmake/linker/arcmwdt/target.cmake +++ b/cmake/linker/arcmwdt/target.cmake @@ -155,7 +155,7 @@ macro(toolchain_ld_relocation) ${ZEPHYR_BASE}/scripts/build/gen_relocate_app.py $<$:--verbose> -d ${APPLICATION_BINARY_DIR} - -i \"$\" + -i \"$\" -o ${MEM_RELOCATION_LD} -s ${MEM_RELOCATION_SRAM_DATA_LD} -b ${MEM_RELOCATION_SRAM_BSS_LD} diff --git a/cmake/linker/armlink/target.cmake b/cmake/linker/armlink/target.cmake index b2e1e867f90..be2bb8e8977 100644 --- a/cmake/linker/armlink/target.cmake +++ b/cmake/linker/armlink/target.cmake @@ -18,6 +18,9 @@ macro(configure_linker_script linker_script_gen linker_pass_define) set(STEERING_FILE_ARG) set(STEERING_C_ARG) set(linker_pass_define_list ${linker_pass_define}) + set(cmake_linker_script_settings + ${PROJECT_BINARY_DIR}/include/generated/ld_script_settings_${linker_pass_define}.cmake + ) if("LINKER_ZEPHYR_FINAL" IN_LIST linker_pass_define_list) set(STEERING_FILE ${CMAKE_CURRENT_BINARY_DIR}/armlink_symbol_steering.steer) @@ -26,21 +29,29 @@ macro(configure_linker_script linker_script_gen linker_pass_define) set(STEERING_C_ARG "-DSTEERING_C=${STEERING_C}") endif() + file(GENERATE OUTPUT ${cmake_linker_script_settings} CONTENT + "set(FORMAT \"$\" CACHE INTERNAL \"\")\n + set(ENTRY \"$\" CACHE INTERNAL \"\")\n + set(MEMORY_REGIONS \"$\" CACHE INTERNAL \"\")\n + set(GROUPS \"$\" CACHE INTERNAL \"\")\n + set(SECTIONS \"$\" CACHE INTERNAL \"\")\n + set(SECTION_SETTINGS \"$\" CACHE INTERNAL \"\")\n + set(SYMBOLS \"$\" CACHE INTERNAL \"\")\n + " + ) add_custom_command( OUTPUT ${linker_script_gen} ${STEERING_FILE} ${STEERING_C} COMMAND ${CMAKE_COMMAND} + -C ${DEVICE_API_LINKER_SECTIONS_CMAKE} + -C ${cmake_linker_script_settings} -DPASS="${linker_pass_define}" - -DMEMORY_REGIONS="$" - -DGROUPS="$" - -DSECTIONS="$" - -DSECTION_SETTINGS="$" - -DSYMBOLS="$" ${STEERING_FILE_ARG} ${STEERING_C_ARG} -DOUT_FILE=${CMAKE_CURRENT_BINARY_DIR}/${linker_script_gen} -P ${ZEPHYR_BASE}/cmake/linker/armlink/scatter_script.cmake + DEPENDS ${DEVICE_API_LD_TARGET} ) if("LINKER_ZEPHYR_FINAL" IN_LIST linker_pass_define_list) diff --git a/cmake/linker/ld/linker_flags.cmake b/cmake/linker/ld/linker_flags.cmake index 5063ddb46fb..0e0e8b6b0a1 100644 --- a/cmake/linker/ld/linker_flags.cmake +++ b/cmake/linker/ld/linker_flags.cmake @@ -36,7 +36,7 @@ endif() set_property(TARGET linker PROPERTY partial_linking "-r") -set_property(TARGET linker PROPERTY lto_arguments -flto -fno-ipa-sra -ffunction-sections -fdata-sections) +set_property(TARGET linker PROPERTY lto_arguments -flto=auto -fno-ipa-sra -ffunction-sections -fdata-sections) check_set_linker_property(TARGET linker PROPERTY no_relax ${LINKERFLAGPREFIX},--no-relax) diff --git a/cmake/linker/ld/linker_libraries.cmake b/cmake/linker/ld/linker_libraries.cmake index 1305d682ab5..999420164aa 100644 --- a/cmake/linker/ld/linker_libraries.cmake +++ b/cmake/linker/ld/linker_libraries.cmake @@ -2,22 +2,17 @@ # # SPDX-License-Identifier: Apache-2.0 -# Do not specify default link libraries when targeting host (native build). -if(NOT CONFIG_NATIVE_BUILD) - set_linker_property(NO_CREATE PROPERTY c_library "-lc") - set_linker_property(NO_CREATE PROPERTY rt_library "-lgcc") - set_linker_property(NO_CREATE PROPERTY c++_library "-lstdc++") - set_linker_property(NO_CREATE PROPERTY math_library "-lm") - # Keeping default include dir empty. The linker will then select libraries - # from its default search path. The toolchain may adjust the value to a - # specific location, for example gcc infrastructure will set the value based - # on output from --print-libgcc-file-name. - set_linker_property(NO_CREATE PROPERTY lib_include_dir "") -endif() +set_linker_property(NO_CREATE PROPERTY c_library "-lc") +set_linker_property(NO_CREATE PROPERTY rt_library "-lgcc") +set_linker_property(NO_CREATE PROPERTY c++_library "-lstdc++") +set_linker_property(NO_CREATE PROPERTY math_library "-lm") +# Keeping default include dir empty. The linker will then select libraries +# from its default search path. The toolchain may adjust the value to a +# specific location, for example gcc infrastructure will set the value based +# on output from --print-libgcc-file-name. +set_linker_property(NO_CREATE PROPERTY lib_include_dir "") if(CONFIG_CPP - AND NOT CONFIG_MINIMAL_LIBCPP - AND NOT CONFIG_NATIVE_LIBRARY # When new link principle is fully introduced, then the below condition can # be removed, and instead the external module c++ should use: # set_property(TARGET linker PROPERTY c++_library "") diff --git a/cmake/linker/ld/target.cmake b/cmake/linker/ld/target.cmake index d7ac5e41d89..6bbc11af14a 100644 --- a/cmake/linker/ld/target.cmake +++ b/cmake/linker/ld/target.cmake @@ -18,22 +18,31 @@ endif() # NOTE: ${linker_script_gen} will be produced at build-time; not at configure-time macro(configure_linker_script linker_script_gen linker_pass_define) set(extra_dependencies ${ARGN}) + set(cmake_linker_script_settings + ${PROJECT_BINARY_DIR}/include/generated/ld_script_settings_${linker_pass_define}.cmake + ) if(CONFIG_CMAKE_LINKER_GENERATOR) + file(GENERATE OUTPUT ${cmake_linker_script_settings} CONTENT + "set(FORMAT \"$\" CACHE INTERNAL \"\")\n + set(ENTRY \"$\" CACHE INTERNAL \"\")\n + set(MEMORY_REGIONS \"$\" CACHE INTERNAL \"\")\n + set(GROUPS \"$\" CACHE INTERNAL \"\")\n + set(SECTIONS \"$\" CACHE INTERNAL \"\")\n + set(SECTION_SETTINGS \"$\" CACHE INTERNAL \"\")\n + set(SYMBOLS \"$\" CACHE INTERNAL \"\")\n + " + ) add_custom_command( OUTPUT ${linker_script_gen} COMMAND ${CMAKE_COMMAND} + -C ${DEVICE_API_LINKER_SECTIONS_CMAKE} + -C ${cmake_linker_script_settings} -DPASS="${linker_pass_define}" - -DFORMAT="$" - -DENTRY="$" - -DMEMORY_REGIONS="$" - -DGROUPS="$" - -DSECTIONS="$" - -DSECTION_SETTINGS="$" - -DSYMBOLS="$" -DOUT_FILE=${CMAKE_CURRENT_BINARY_DIR}/${linker_script_gen} -P ${ZEPHYR_BASE}/cmake/linker/ld/ld_script.cmake - ) + DEPENDS ${DEVICE_API_LD_TARGET} + ) else() set(template_script_defines ${linker_pass_define}) list(TRANSFORM template_script_defines PREPEND "-D") @@ -148,7 +157,7 @@ macro(toolchain_linker_finalize) endforeach() string(REPLACE ";" " " zephyr_std_libs "${zephyr_std_libs}") - set(link_libraries " -o ${zephyr_std_libs}") + set(link_libraries " -o ${zephyr_std_libs}") set(common_link " ${link_libraries}") set(CMAKE_ASM_LINK_EXECUTABLE " ${common_link}") diff --git a/cmake/linker/ld/target_relocation.cmake b/cmake/linker/ld/target_relocation.cmake index a90941d04af..2bc2aa24c11 100644 --- a/cmake/linker/ld/target_relocation.cmake +++ b/cmake/linker/ld/target_relocation.cmake @@ -16,7 +16,7 @@ macro(toolchain_ld_relocation) OUTPUT ${DICT_FILE} CONTENT - $ + $ ) add_custom_command( diff --git a/cmake/linker/linker_libraries_native.cmake b/cmake/linker/linker_libraries_native.cmake new file mode 100644 index 00000000000..f3e852bc629 --- /dev/null +++ b/cmake/linker/linker_libraries_native.cmake @@ -0,0 +1,21 @@ +# Copyright (c) 2024 Nordic Semiconductor +# +# SPDX-License-Identifier: Apache-2.0 + +# When doing native builds, then we default to host libraries. +# No reason for loading linker libraries properties in this case, however we do +# define link order because that allows the build system to hook in alternative +# C library implementations, such as minimal libc or picolibc. + +# Empty on purpose as we default to host libraries selected by the linker. +set_linker_property(PROPERTY c_library "") +set_linker_property(PROPERTY rt_library "") +set_linker_property(PROPERTY c++_library "") + +# Although library properties are empty per default, then we still define link +# order as this allows to update libraries in use elsewhere. +if(CONFIG_CPP) + set_property(TARGET linker PROPERTY link_order_library "c++") +endif() + +set_property(TARGET linker APPEND PROPERTY link_order_library "c;rt") diff --git a/cmake/linker/linker_script_common.cmake b/cmake/linker/linker_script_common.cmake index ef5ded66fdd..017de14cf6b 100644 --- a/cmake/linker/linker_script_common.cmake +++ b/cmake/linker/linker_script_common.cmake @@ -132,7 +132,7 @@ function(create_section) set(INDEX 100) set(settings_single "ALIGN;ANY;FIRST;KEEP;OFFSET;PRIO;SECTION;SORT") set(settings_multi "FLAGS;INPUT;PASS;SYMBOLS") - foreach(settings ${SECTION_SETTINGS}) + foreach(settings ${SECTION_SETTINGS} ${DEVICE_API_SECTION_SETTINGS}) if("${settings}" MATCHES "^{(.*)}$") cmake_parse_arguments(SETTINGS "" "${settings_single}" "${settings_multi}" ${CMAKE_MATCH_1}) @@ -652,7 +652,7 @@ foreach(group ${GROUPS}) endif() endforeach() -foreach(section ${SECTIONS}) +foreach(section ${SECTIONS} ${DEVICE_API_SECTIONS}) if("${section}" MATCHES "^{(.*)}$") create_section(${CMAKE_MATCH_1} SYSTEM ${new_system}) endif() diff --git a/cmake/linker/lld/linker_flags.cmake b/cmake/linker/lld/linker_flags.cmake index f11139aa1e2..6997f865d28 100644 --- a/cmake/linker/lld/linker_flags.cmake +++ b/cmake/linker/lld/linker_flags.cmake @@ -7,15 +7,10 @@ # and adjust for lld specifics afterwards. include(${ZEPHYR_BASE}/cmake/linker/ld/linker_flags.cmake OPTIONAL) -if(NOT CONFIG_MINIMAL_LIBCPP AND NOT CONFIG_NATIVE_LIBRARY AND NOT CONFIG_EXTERNAL_MODULE_LIBCPP) +if(NOT CONFIG_NATIVE_LIBRARY AND NOT CONFIG_EXTERNAL_MODULE_LIBCPP) set_property(TARGET linker PROPERTY cpp_base ${LINKERFLAGPREFIX},-z,norelro) endif() -# Force LLVM to use built-in lld linker -if(NOT CONFIG_LLVM_USE_LD) - check_set_linker_property(TARGET linker APPEND PROPERTY baremetal -fuse-ld=lld) -endif() - set_property(TARGET linker PROPERTY no_position_independent "${LINKERFLAGPREFIX},--no-pie") set_property(TARGET linker PROPERTY lto_arguments) diff --git a/cmake/linker/lld/linker_libraries.cmake b/cmake/linker/lld/linker_libraries.cmake index 2347898ad64..8275d779337 100644 --- a/cmake/linker/lld/linker_libraries.cmake +++ b/cmake/linker/lld/linker_libraries.cmake @@ -8,8 +8,6 @@ set_linker_property(NO_CREATE TARGET linker PROPERTY rt_library "") set_linker_property(TARGET linker PROPERTY c++_library "-lc++;-lc++abi") if(CONFIG_CPP - AND NOT CONFIG_MINIMAL_LIBCPP - AND NOT CONFIG_NATIVE_LIBRARY # When new link principle is fully introduced, then the below condition can # be removed, and instead the external module c++ should use: # set_property(TARGET linker PROPERTY c++_library "") diff --git a/cmake/linker/xt-ld/linker_flags.cmake b/cmake/linker/xt-ld/linker_flags.cmake index af464509b87..ab66461e452 100644 --- a/cmake/linker/xt-ld/linker_flags.cmake +++ b/cmake/linker/xt-ld/linker_flags.cmake @@ -7,7 +7,7 @@ check_set_linker_property(TARGET linker PROPERTY base ${LINKERFLAGPREFIX},--build-id=none ) -if(NOT CONFIG_MINIMAL_LIBCPP AND NOT CONFIG_NATIVE_LIBRARY AND NOT CONFIG_EXTERNAL_MODULE_LIBCPP) +if(NOT CONFIG_NATIVE_LIBRARY AND NOT CONFIG_EXTERNAL_MODULE_LIBCPP) set_property(TARGET linker PROPERTY cpp_base -lstdc++) endif() diff --git a/cmake/linker/xt-ld/linker_libraries.cmake b/cmake/linker/xt-ld/linker_libraries.cmake new file mode 100644 index 00000000000..f4fedfc4f0d --- /dev/null +++ b/cmake/linker/xt-ld/linker_libraries.cmake @@ -0,0 +1,9 @@ +# Copyright (c) 2024 Nordic Semiconductor +# +# SPDX-License-Identifier: Apache-2.0 + +set_linker_property(NO_CREATE PROPERTY c_library "-lc") +set_linker_property(NO_CREATE PROPERTY rt_library "-lgcc") +set_linker_property(NO_CREATE PROPERTY c++_library "-lstdc++") +set_linker_property(NO_CREATE PROPERTY hal_library "-lhal") +set_linker_property(PROPERTY link_order_library "c;rt;hal") diff --git a/cmake/linker/xt-ld/target.cmake b/cmake/linker/xt-ld/target.cmake index 3546881cc71..9a6b76cda62 100644 --- a/cmake/linker/xt-ld/target.cmake +++ b/cmake/linker/xt-ld/target.cmake @@ -130,7 +130,6 @@ function(toolchain_ld_link_elf) ${NO_WHOLE_ARCHIVE_LIBS} $ -L${PROJECT_BINARY_DIR} - ${TOOLCHAIN_LIBS} ${TOOLCHAIN_LD_LINK_ELF_DEPENDENCIES} ) diff --git a/cmake/linker_script/arm/linker.cmake b/cmake/linker_script/arm/linker.cmake index 332d44b2435..ad639f373cc 100644 --- a/cmake/linker_script/arm/linker.cmake +++ b/cmake/linker_script/arm/linker.cmake @@ -41,10 +41,9 @@ zephyr_linker_memory(NAME FLASH FLAGS rx START ${FLASH_ADDR} SIZE ${FLASH_SIZ zephyr_linker_memory(NAME RAM FLAGS wx START ${RAM_ADDR} SIZE ${RAM_SIZE}) zephyr_linker_memory(NAME IDT_LIST FLAGS wx START ${IDT_ADDR} SIZE 2K) -# Only use 'rw' as FLAGS. It's not used anyway. dt_comp_path(paths COMPATIBLE "zephyr,memory-region") foreach(path IN LISTS paths) - zephyr_linker_dts_memory(PATH ${path} FLAGS rw) + zephyr_linker_dts_memory(PATH ${path}) endforeach() if(CONFIG_XIP) @@ -144,6 +143,7 @@ endif() include(${COMMON_ZEPHYR_LINKER_DIR}/ram-end.cmake) +zephyr_linker_symbol(SYMBOL __ramfunc_region_start EXPR "ADDR(.ramfunc)") zephyr_linker_symbol(SYMBOL __kernel_ram_start EXPR "(@__bss_start@)") zephyr_linker_symbol(SYMBOL __kernel_ram_end EXPR "(${RAM_ADDR} + ${RAM_SIZE})") zephyr_linker_symbol(SYMBOL __kernel_ram_size EXPR "(@__kernel_ram_end@ - @__bss_start@)") diff --git a/cmake/linker_script/common/common-ram.cmake b/cmake/linker_script/common/common-ram.cmake index 48e0c6010aa..5d2f9d18430 100644 --- a/cmake/linker_script/common/common-ram.cmake +++ b/cmake/linker_script/common/common-ram.cmake @@ -41,10 +41,12 @@ zephyr_iterable_section(NAME k_msgq GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SU zephyr_iterable_section(NAME k_mbox GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) zephyr_iterable_section(NAME k_pipe GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) zephyr_iterable_section(NAME k_sem GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) -zephyr_iterable_section(NAME k_queue GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) -zephyr_iterable_section(NAME k_condvar GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) zephyr_iterable_section(NAME k_event GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) +zephyr_iterable_section(NAME k_queue GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) zephyr_iterable_section(NAME k_fifo GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) +zephyr_iterable_section(NAME k_lifo GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) +zephyr_iterable_section(NAME k_condvar GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) +zephyr_iterable_section(NAME sys_mem_blocks_ptr GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) zephyr_iterable_section(NAME net_buf_pool GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) @@ -69,10 +71,7 @@ if(CONFIG_USB_DEVICE_STACK) KEEP SORT NAME INPUT ".usb.descriptor*" ) - zephyr_linker_section(NAME usb_data GROUP DATA_REGION NOINPUT ${XIP_ALIGN_WITH_INPUT} SUBALIGN 1) - zephyr_linker_section_configure(SECTION usb_data - KEEP SORT NAME INPUT ".usb.data*" - ) + zephyr_iterable_section(NAME usb_cfg_data GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) endif() if(CONFIG_USB_DEVICE_BOS) @@ -85,6 +84,12 @@ endif() if(CONFIG_RTIO) zephyr_iterable_section(NAME rtio GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) zephyr_iterable_section(NAME rtio_iodev GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) + zephyr_iterable_section(NAME rtio_sqe_pool GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) + zephyr_iterable_section(NAME rtio_cqe_pool GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) +endif() + +if(CONFIG_SENSING) + zephyr_iterable_section(NAME sensing_sensor GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) endif() #if(CONFIG_USERSPACE) @@ -119,7 +124,6 @@ if(CONFIG_PCIE) endif() if(CONFIG_USB_DEVICE_STACK OR CONFIG_USB_DEVICE_STACK_NEXT) - zephyr_iterable_section(NAME usb_cfg_data GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) zephyr_iterable_section(NAME usbd_context GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) zephyr_iterable_section(NAME usbd_class_fs GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) zephyr_iterable_section(NAME usbd_class_hs GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) diff --git a/cmake/mcuboot.cmake b/cmake/mcuboot.cmake index 6dd0717f515..b6ab9dd5034 100644 --- a/cmake/mcuboot.cmake +++ b/cmake/mcuboot.cmake @@ -73,12 +73,30 @@ function(zephyr_mcuboot_tasks) return() endif() - # Basic 'west sign' command and output format independent arguments. - separate_arguments(west_sign_extra UNIX_COMMAND ${CONFIG_MCUBOOT_CMAKE_WEST_SIGN_PARAMS}) - set(west_sign ${WEST} sign ${west_sign_extra} - --tool imgtool - --tool-path "${imgtool_path}" - --build-dir "${APPLICATION_BINARY_DIR}") + # Fetch devicetree details for flash and slot information + dt_chosen(flash_node PROPERTY "zephyr,flash") + dt_nodelabel(slot0_flash NODELABEL "slot0_partition" REQUIRED) + dt_prop(slot_size PATH "${slot0_flash}" PROPERTY "reg" INDEX 1 REQUIRED) + dt_prop(write_block_size PATH "${flash_node}" PROPERTY "write-block-size") + + if(NOT write_block_size) + set(write_block_size 4) + message(WARNING "slot0_partition write block size devicetree parameter is missing, assuming write block size is 4") + endif() + + # If single slot mode, or if in firmware updater mode and this is the firmware updater image, + # use slot 0 information + if(NOT CONFIG_MCUBOOT_BOOTLOADER_MODE_SINGLE_APP AND (NOT CONFIG_MCUBOOT_BOOTLOADER_MODE_FIRMWARE_UPDATER OR CONFIG_MCUBOOT_APPLICATION_FIRMWARE_UPDATER)) + # Slot 1 size is used instead of slot 0 size + set(slot_size) + dt_nodelabel(slot1_flash NODELABEL "slot1_partition" REQUIRED) + dt_prop(slot_size PATH "${slot1_flash}" PROPERTY "reg" INDEX 1 REQUIRED) + endif() + + # Basic 'imgtool sign' command with known image information. + set(imgtool_sign ${PYTHON_EXECUTABLE} ${imgtool_path} sign + --version ${CONFIG_MCUBOOT_IMGTOOL_SIGN_VERSION} --header-size ${CONFIG_ROM_START_OFFSET} + --slot-size ${slot_size}) # Arguments to imgtool. if(NOT CONFIG_MCUBOOT_EXTRA_IMGTOOL_ARGS STREQUAL "") @@ -87,101 +105,142 @@ function(zephyr_mcuboot_tasks) # # Use UNIX_COMMAND syntax for uniform results across host # platforms. - separate_arguments(imgtool_extra UNIX_COMMAND ${CONFIG_MCUBOOT_EXTRA_IMGTOOL_ARGS}) + separate_arguments(imgtool_args UNIX_COMMAND ${CONFIG_MCUBOOT_EXTRA_IMGTOOL_ARGS}) else() - set(imgtool_extra) + set(imgtool_args) endif() if(NOT "${keyfile}" STREQUAL "") - set(imgtool_extra --key "${keyfile}" ${imgtool_extra}) + set(imgtool_args --key "${keyfile}" ${imgtool_args}) endif() - # Use overwrite-only instead of swap upgrades. if(CONFIG_MCUBOOT_IMGTOOL_OVERWRITE_ONLY) - set(imgtool_extra --overwrite-only --align 1 ${imgtool_extra}) + # Use overwrite-only instead of swap upgrades. + set(imgtool_args --overwrite-only --align 1 ${imgtool_args}) + elseif(CONFIG_MCUBOOT_BOOTLOADER_MODE_RAM_LOAD) + # RAM load requires setting the location of where to load the image to + dt_chosen(chosen_ram PROPERTY "zephyr,sram") + dt_reg_addr(chosen_ram_address PATH ${chosen_ram}) + dt_nodelabel(slot0_partition NODELABEL "slot0_partition" REQUIRED) + dt_reg_addr(slot0_partition_address PATH ${slot0_partition}) + dt_nodelabel(slot1_partition NODELABEL "slot1_partition" REQUIRED) + dt_reg_addr(slot1_partition_address PATH ${slot1_partition}) + + set(imgtool_args --align 1 --load-addr ${chosen_ram_address} ${imgtool_args}) + set(imgtool_args_alt_slot ${imgtool_args} --hex-addr ${slot1_partition_address}) + set(imgtool_args ${imgtool_args} --hex-addr ${slot0_partition_address}) + else() + set(imgtool_args --align ${write_block_size} ${imgtool_args}) endif() - set(imgtool_args -- ${imgtool_extra}) - # Extensionless prefix of any output file. set(output ${ZEPHYR_BINARY_DIR}/${KERNEL_NAME}) # List of additional build byproducts. set(byproducts) - # 'west sign' arguments for confirmed, unconfirmed and encrypted images. - set(unconfirmed_args) - set(confirmed_args) - set(encrypted_args) - # Set up .bin outputs. if(CONFIG_BUILD_OUTPUT_BIN) - list(APPEND unconfirmed_args --bin --sbin ${output}.signed.bin) list(APPEND byproducts ${output}.signed.bin) zephyr_runner_file(bin ${output}.signed.bin) set(BYPRODUCT_KERNEL_SIGNED_BIN_NAME "${output}.signed.bin" CACHE FILEPATH "Signed kernel bin file" FORCE ) + set_property(GLOBAL APPEND PROPERTY extra_post_build_commands COMMAND + ${imgtool_sign} ${imgtool_args} ${output}.bin ${output}.signed.bin) if(CONFIG_MCUBOOT_GENERATE_CONFIRMED_IMAGE) - list(APPEND confirmed_args --bin --sbin ${output}.signed.confirmed.bin) list(APPEND byproducts ${output}.signed.confirmed.bin) set(BYPRODUCT_KERNEL_SIGNED_CONFIRMED_BIN_NAME "${output}.signed.confirmed.bin" CACHE FILEPATH "Signed and confirmed kernel bin file" FORCE ) + set_property(GLOBAL APPEND PROPERTY extra_post_build_commands COMMAND + ${imgtool_sign} ${imgtool_args} --pad --confirm ${output}.bin + ${output}.signed.confirmed.bin) endif() if(NOT "${keyfile_enc}" STREQUAL "") - list(APPEND encrypted_args --bin --sbin ${output}.signed.encrypted.bin) list(APPEND byproducts ${output}.signed.encrypted.bin) set(BYPRODUCT_KERNEL_SIGNED_ENCRYPTED_BIN_NAME "${output}.signed.encrypted.bin" CACHE FILEPATH "Signed and encrypted kernel bin file" FORCE ) + set_property(GLOBAL APPEND PROPERTY extra_post_build_commands COMMAND + ${imgtool_sign} ${imgtool_args} --encrypt "${keyfile_enc}" ${output}.bin + ${output}.signed.encrypted.bin) + endif() + + if(CONFIG_MCUBOOT_BOOTLOADER_MODE_RAM_LOAD) + list(APPEND byproducts ${output}.slot1.signed.encrypted.bin) + set_property(GLOBAL APPEND PROPERTY extra_post_build_commands COMMAND + ${imgtool_sign} ${imgtool_args_alt_slot} ${output}.bin + ${output}.slot1.signed.bin) + + if(CONFIG_MCUBOOT_GENERATE_CONFIRMED_IMAGE) + list(APPEND byproducts ${output}.slot1.signed.confirmed.bin) + set_property(GLOBAL APPEND PROPERTY extra_post_build_commands COMMAND + ${imgtool_sign} ${imgtool_args_alt_slot} --pad --confirm ${output}.bin + ${output}.slot1.signed.confirmed.bin) + endif() + + if(NOT "${keyfile_enc}" STREQUAL "") + list(APPEND byproducts ${output}.slot1.signed.encrypted.bin) + set_property(GLOBAL APPEND PROPERTY extra_post_build_commands COMMAND + ${imgtool_sign} ${imgtool_args_alt_slot} --encrypt "${keyfile_enc}" + ${output}.bin ${output}.slot1.signed.encrypted.bin) + endif() endif() endif() # Set up .hex outputs. if(CONFIG_BUILD_OUTPUT_HEX) - list(APPEND unconfirmed_args --hex --shex ${output}.signed.hex) list(APPEND byproducts ${output}.signed.hex) zephyr_runner_file(hex ${output}.signed.hex) set(BYPRODUCT_KERNEL_SIGNED_HEX_NAME "${output}.signed.hex" CACHE FILEPATH "Signed kernel hex file" FORCE ) + set_property(GLOBAL APPEND PROPERTY extra_post_build_commands COMMAND + ${imgtool_sign} ${imgtool_args} ${output}.hex ${output}.signed.hex) if(CONFIG_MCUBOOT_GENERATE_CONFIRMED_IMAGE) - list(APPEND confirmed_args --hex --shex ${output}.signed.confirmed.hex) list(APPEND byproducts ${output}.signed.confirmed.hex) set(BYPRODUCT_KERNEL_SIGNED_CONFIRMED_HEX_NAME "${output}.signed.confirmed.hex" CACHE FILEPATH "Signed and confirmed kernel hex file" FORCE ) + set_property(GLOBAL APPEND PROPERTY extra_post_build_commands COMMAND + ${imgtool_sign} ${imgtool_args} --pad --confirm ${output}.hex + ${output}.signed.confirmed.hex) endif() if(NOT "${keyfile_enc}" STREQUAL "") - list(APPEND encrypted_args --hex --shex ${output}.signed.encrypted.hex) list(APPEND byproducts ${output}.signed.encrypted.hex) set(BYPRODUCT_KERNEL_SIGNED_ENCRYPTED_HEX_NAME "${output}.signed.encrypted.hex" CACHE FILEPATH "Signed and encrypted kernel hex file" FORCE ) + set_property(GLOBAL APPEND PROPERTY extra_post_build_commands COMMAND + ${imgtool_sign} ${imgtool_args} --encrypt "${keyfile_enc}" ${output}.hex + ${output}.signed.encrypted.hex) endif() - endif() - # Add the west sign calls and their byproducts to the post-processing - # steps for zephyr.elf. - # - # CMake guarantees that multiple COMMANDs given to - # add_custom_command() are run in order, so adding the 'west sign' - # calls to the "extra_post_build_commands" property ensures they run - # after the commands which generate the unsigned versions. - set_property(GLOBAL APPEND PROPERTY extra_post_build_commands COMMAND - ${west_sign} ${unconfirmed_args} ${imgtool_args}) - if(confirmed_args) - set_property(GLOBAL APPEND PROPERTY extra_post_build_commands COMMAND - ${west_sign} ${confirmed_args} ${imgtool_args} --pad --confirm) - endif() - if(encrypted_args) - set_property(GLOBAL APPEND PROPERTY extra_post_build_commands COMMAND - ${west_sign} ${encrypted_args} ${imgtool_args} --encrypt "${keyfile_enc}") + if(CONFIG_MCUBOOT_BOOTLOADER_MODE_RAM_LOAD) + list(APPEND byproducts ${output}.slot1.signed.hex) + set_property(GLOBAL APPEND PROPERTY extra_post_build_commands COMMAND + ${imgtool_sign} ${imgtool_args_alt_slot} ${output}.hex + ${output}.slot1.signed.hex) + + if(CONFIG_MCUBOOT_GENERATE_CONFIRMED_IMAGE) + list(APPEND byproducts ${output}.slot1.signed.confirmed.hex) + set_property(GLOBAL APPEND PROPERTY extra_post_build_commands COMMAND + ${imgtool_sign} ${imgtool_args_alt_slot} --pad --confirm ${output}.hex + ${output}.slot1.signed.confirmed.hex) + endif() + + if(NOT "${keyfile_enc}" STREQUAL "") + list(APPEND byproducts ${output}.slot1.signed.encrypted.hex) + set_property(GLOBAL APPEND PROPERTY extra_post_build_commands COMMAND + ${imgtool_sign} ${imgtool_args_alt_slot} --encrypt "${keyfile_enc}" + ${output}.hex ${output}.slot1.signed.encrypted.hex) + endif() + endif() endif() set_property(GLOBAL APPEND PROPERTY extra_post_build_byproducts ${byproducts}) endfunction() diff --git a/cmake/modules/FindHostTools.cmake b/cmake/modules/FindHostTools.cmake index 1dfce4d3d4a..a1ea6631bf5 100644 --- a/cmake/modules/FindHostTools.cmake +++ b/cmake/modules/FindHostTools.cmake @@ -65,6 +65,12 @@ find_program(BOSSAC bossac) # in the mcuboot repository if that's present in some cases) find_program(IMGTOOL imgtool) +# winpty is an optional dependency +find_program(PTY_INTERFACE winpty) +if("${PTY_INTERFACE}" STREQUAL "PTY_INTERFACE-NOTFOUND") + set(PTY_INTERFACE "") +endif() + # Default to the host system's toolchain if we are targeting a host based target if((${BOARD_DIR} MATCHES "boards\/native") OR ("${ARCH}" STREQUAL "posix") OR ("${BOARD}" STREQUAL "unit_testing")) diff --git a/cmake/modules/FindZephyr-sdk.cmake b/cmake/modules/FindZephyr-sdk.cmake index 1b56379ec66..90bbed017ce 100644 --- a/cmake/modules/FindZephyr-sdk.cmake +++ b/cmake/modules/FindZephyr-sdk.cmake @@ -77,7 +77,7 @@ if(("zephyr" STREQUAL ${ZEPHYR_TOOLCHAIN_VARIANT}) OR # To support Zephyr SDK tools (DTC, and other tools) with 3rd party toolchains # then we keep track of current toolchain variant. set(ZEPHYR_CURRENT_TOOLCHAIN_VARIANT ${ZEPHYR_TOOLCHAIN_VARIANT}) - find_package(Zephyr-sdk ${Zephyr-sdk_FIND_VERSION} + find_package(Zephyr-sdk ${Zephyr-sdk_FIND_VERSION_COMPLETE} REQUIRED QUIET CONFIG HINTS ${ZEPHYR_SDK_INSTALL_DIR} ) if(DEFINED ZEPHYR_CURRENT_TOOLCHAIN_VARIANT) @@ -123,16 +123,27 @@ if(("zephyr" STREQUAL ${ZEPHYR_TOOLCHAIN_VARIANT}) OR endif() endforeach() else() + if("${Zephyr-sdk_FIND_VERSION_RANGE_MAX}" STREQUAL "INCLUDE") + set(upper_bound _EQUAL) + endif() + + if(NOT DEFINED Zephyr-sdk_FIND_VERSION_RANGE) + # Range not given, max out to ensure max version is not in effect. + set(Zephyr-sdk_FIND_VERSION_MAX 99999999) + endif() + # Loop over each found Zepher SDK version until one is found that is compatible. foreach(zephyr_sdk_candidate ${Zephyr-sdk_CONSIDERED_VERSIONS}) - if("${zephyr_sdk_candidate}" VERSION_GREATER_EQUAL "${Zephyr-sdk_FIND_VERSION}") + if("${zephyr_sdk_candidate}" VERSION_GREATER_EQUAL "${Zephyr-sdk_FIND_VERSION}" + AND "${zephyr_sdk_candidate}" VERSION_LESS${upper_bound} "${Zephyr-sdk_FIND_VERSION_MAX}" + ) # Find the path for the current version being checked and get the directory # of the Zephyr SDK so it can be checked. cmake_path(GET Zephyr-sdk-${zephyr_sdk_candidate}_DIR PARENT_PATH zephyr_sdk_current_check_path) cmake_path(GET zephyr_sdk_current_check_path PARENT_PATH zephyr_sdk_current_check_path) # Then see if this version is compatible. - find_package(Zephyr-sdk ${Zephyr-sdk_FIND_VERSION} QUIET CONFIG PATHS ${zephyr_sdk_current_check_path} NO_DEFAULT_PATH) + find_package(Zephyr-sdk ${Zephyr-sdk_FIND_VERSION_COMPLETE} QUIET CONFIG PATHS ${zephyr_sdk_current_check_path} NO_DEFAULT_PATH) if (${Zephyr-sdk_FOUND}) # A compatible version of the Zephyr SDK has been found which is the highest @@ -145,7 +156,7 @@ if(("zephyr" STREQUAL ${ZEPHYR_TOOLCHAIN_VARIANT}) OR if (NOT ${Zephyr-sdk_FOUND}) # This means no compatible Zephyr SDK versions were found, set the version # back to the minimum version so that it is displayed in the error text. - find_package(Zephyr-sdk ${Zephyr-sdk_FIND_VERSION} REQUIRED CONFIG PATHS ${zephyr_sdk_search_paths}) + find_package(Zephyr-sdk ${Zephyr-sdk_FIND_VERSION_COMPLETE} REQUIRED CONFIG PATHS ${zephyr_sdk_search_paths}) endif() endif() endif() diff --git a/cmake/modules/dts.cmake b/cmake/modules/dts.cmake index eb7869548fe..4ab76989f74 100644 --- a/cmake/modules/dts.cmake +++ b/cmake/modules/dts.cmake @@ -66,6 +66,12 @@ find_package(Dtc 1.4.6) # # Required variables: # - BINARY_DIR_INCLUDE_GENERATED: where to put generated include files +# - DTS_ROOT: a deduplicated list of places where devicetree +# implementation files (like bindings, vendor prefixes, etc.) are +# found +# - DTS_ROOT_SYSTEM_INCLUDE_DIRS: set to "PATH1 PATH2 ...", +# with one path per potential location where C preprocessor #includes +# may be found for devicetree files # - KCONFIG_BINARY_DIR: where to put generated Kconfig files # # Optional variables: @@ -73,6 +79,8 @@ find_package(Dtc 1.4.6) # - BOARD_DIRECTORIES: list of board directories to use when looking for DTS_SOURCE # - BOARD_REVISION_STRING: used when looking for a board revision's # devicetree overlay file in one of the BOARD_DIRECTORIES +# - CMAKE_DTS_PREPROCESSOR: the path to the preprocessor to use +# for devicetree files # - DTC_OVERLAY_FILE: list of devicetree overlay files which will be # used to modify or extend the base devicetree. # - EXTRA_DTC_OVERLAY_FILE: list of extra devicetree overlay files. @@ -94,6 +102,8 @@ find_package(Dtc 1.4.6) # The directory containing devicetree related scripts. set(DT_SCRIPTS ${ZEPHYR_BASE}/scripts/dts) +# This parses and collects the DT information +set(GEN_EDT_SCRIPT ${DT_SCRIPTS}/gen_edt.py) # This generates DT information needed by the C macro APIs, # along with a few other things. set(GEN_DEFINES_SCRIPT ${DT_SCRIPTS}/gen_defines.py) @@ -222,7 +232,7 @@ foreach(dts_root ${DTS_ROOT}) set(vendor_prefixes ${dts_root}/${VENDOR_PREFIXES}) if(EXISTS ${vendor_prefixes}) - list(APPEND EXTRA_GEN_DEFINES_ARGS --vendor-prefixes ${vendor_prefixes}) + list(APPEND EXTRA_GEN_EDT_ARGS --vendor-prefixes ${vendor_prefixes}) endif() endforeach() @@ -272,23 +282,44 @@ toolchain_parse_make_rule(${DTS_DEPS} set_property(DIRECTORY APPEND PROPERTY CMAKE_CONFIGURE_DEPENDS ${DTS_INCLUDE_FILES} + ${GEN_EDT_SCRIPT} ${GEN_DEFINES_SCRIPT} ${GEN_DRIVER_KCONFIG_SCRIPT} ${GEN_DTS_CMAKE_SCRIPT} ) # -# Run GEN_DEFINES_SCRIPT. +# Run GEN_EDT_SCRIPT. # string(REPLACE ";" " " EXTRA_DTC_FLAGS_RAW "${EXTRA_DTC_FLAGS}") -set(CMD_GEN_DEFINES ${PYTHON_EXECUTABLE} ${GEN_DEFINES_SCRIPT} +set(CMD_GEN_EDT ${PYTHON_EXECUTABLE} ${GEN_EDT_SCRIPT} --dts ${DTS_POST_CPP} --dtc-flags '${EXTRA_DTC_FLAGS_RAW}' --bindings-dirs ${DTS_ROOT_BINDINGS} ---header-out ${DEVICETREE_GENERATED_H}.new --dts-out ${ZEPHYR_DTS}.new # for debugging and dtc ---edt-pickle-out ${EDT_PICKLE} +--edt-pickle-out ${EDT_PICKLE}.new +${EXTRA_GEN_EDT_ARGS} +) + +execute_process( + COMMAND ${CMD_GEN_EDT} + WORKING_DIRECTORY ${PROJECT_BINARY_DIR} + COMMAND_ERROR_IS_FATAL ANY + ) +zephyr_file_copy(${ZEPHYR_DTS}.new ${ZEPHYR_DTS} ONLY_IF_DIFFERENT) +zephyr_file_copy(${EDT_PICKLE}.new ${EDT_PICKLE} ONLY_IF_DIFFERENT) +file(REMOVE ${ZEPHYR_DTS}.new ${EDT_PICKLE}.new) +message(STATUS "Generated zephyr.dts: ${ZEPHYR_DTS}") +message(STATUS "Generated pickled edt: ${EDT_PICKLE}") + +# +# Run GEN_DEFINES_SCRIPT. +# + +set(CMD_GEN_DEFINES ${PYTHON_EXECUTABLE} ${GEN_DEFINES_SCRIPT} +--header-out ${DEVICETREE_GENERATED_H}.new +--edt-pickle ${EDT_PICKLE} ${EXTRA_GEN_DEFINES_ARGS} ) @@ -297,7 +328,6 @@ execute_process( WORKING_DIRECTORY ${PROJECT_BINARY_DIR} COMMAND_ERROR_IS_FATAL ANY ) -zephyr_file_copy(${ZEPHYR_DTS}.new ${ZEPHYR_DTS} ONLY_IF_DIFFERENT) zephyr_file_copy(${DEVICETREE_GENERATED_H}.new ${DEVICETREE_GENERATED_H} ONLY_IF_DIFFERENT) file(REMOVE ${ZEPHYR_DTS}.new ${DEVICETREE_GENERATED_H}.new) message(STATUS "Generated zephyr.dts: ${ZEPHYR_DTS}") diff --git a/cmake/modules/extensions.cmake b/cmake/modules/extensions.cmake index 921a457067d..91bfa14aeff 100644 --- a/cmake/modules/extensions.cmake +++ b/cmake/modules/extensions.cmake @@ -1526,9 +1526,9 @@ function(zephyr_code_relocate) # each directive can embed multiple CMake lists, representing flags and files, # the latter of which can come from generator expressions. get_property(code_rel_str TARGET code_data_relocation_target - PROPERTY COMPILE_DEFINITIONS) + PROPERTY INTERFACE_SOURCES) set_property(TARGET code_data_relocation_target - PROPERTY COMPILE_DEFINITIONS + PROPERTY INTERFACE_SOURCES "${code_rel_str}|${CODE_REL_LOCATION}:${flag_list}:${file_list}") endfunction() @@ -3251,8 +3251,9 @@ function(zephyr_get variable) set(sysbuild_global_${var}) endif() - if(TARGET snippets_scope) - get_property(snippets_${var} TARGET snippets_scope PROPERTY ${var}) + zephyr_scope_exists(scope_defined snippets) + if(scope_defined) + zephyr_get_scoped(snippets_${var} snippets ${var}) endif() endforeach() @@ -3317,11 +3318,54 @@ endfunction(zephyr_get variable) # : Name of new scope. # function(zephyr_create_scope scope) - if(TARGET ${scope}_scope) + zephyr_scope_exists(scope_defined ${scope}) + if(scope_defined) message(FATAL_ERROR "zephyr_create_scope(${scope}) already exists.") endif() - add_custom_target(${scope}_scope) + set_property(GLOBAL PROPERTY scope:${scope} TRUE) +endfunction() + +# Usage: +# zephyr_scope_exists( ) +# +# Check if exists. +# +# : Variable to set with result. +# TRUE if scope exists, FALSE otherwise. +# : Name of scope. +# +function(zephyr_scope_exists result scope) + get_property(scope_defined GLOBAL PROPERTY scope:${scope}) + if(scope_defined) + set(${result} TRUE PARENT_SCOPE) + else() + set(${result} FALSE PARENT_SCOPE) + endif() +endfunction() + +# Usage: +# zephyr_get_scoped( ) +# +# Get the current value of in a specific , as defined by a +# previous zephyr_set() call. The value will be stored in the var. +# +# : Variable to store the value in +# : Scope for the variable look up +# : Name to look up in the specific scope +# +function(zephyr_get_scoped output scope var) + zephyr_scope_exists(scope_defined ${scope}) + if(NOT scope_defined) + message(FATAL_ERROR "zephyr_get_scoped(): scope ${scope} doesn't exists.") + endif() + + get_property(value GLOBAL PROPERTY ${scope}_scope:${var}) + if(DEFINED value) + set(${output} "${value}" PARENT_SCOPE) + else() + unset(${output} PARENT_SCOPE) + endif() endfunction() # Usage: @@ -3342,7 +3386,8 @@ function(zephyr_set variable) zephyr_check_arguments_required_all(zephyr_set SET_VAR SCOPE) - if(NOT TARGET ${SET_VAR_SCOPE}_scope) + zephyr_scope_exists(scope_defined ${SET_VAR_SCOPE}) + if(NOT scope_defined) message(FATAL_ERROR "zephyr_set(... SCOPE ${SET_VAR_SCOPE}) doesn't exists.") endif() @@ -3350,8 +3395,8 @@ function(zephyr_set variable) set(property_args APPEND) endif() - set_property(TARGET ${SET_VAR_SCOPE}_scope ${property_args} - PROPERTY ${variable} ${SET_VAR_UNPARSED_ARGUMENTS} + set_property(GLOBAL ${property_args} PROPERTY + ${SET_VAR_SCOPE}_scope:${variable} ${SET_VAR_UNPARSED_ARGUMENTS} ) endfunction() @@ -4680,7 +4725,7 @@ function(zephyr_linker) endfunction() # Usage: -# zephyr_linker_memory(NAME START
SIZE FLAGS ) +# zephyr_linker_memory(NAME START
SIZE [FLAGS ]) # # Zephyr linker memory. # This function specifies a memory region for the platform in use. @@ -4697,14 +4742,18 @@ endfunction() # All the following are valid values: # 1048576, 0x10000, 1024k, 1024K, 1m, and 1M. # FLAGS : Flags describing properties of the memory region. -# Currently supported: # r: Read-only region # w: Read-write region # x: Executable region -# The flags r and x, or w and x may be combined like: rx, wx. +# a: Allocatable region +# i: Initialized region +# l: Same as ‘i’ +# !: Invert the sense of any of the attributes that follow +# The flags may be combined like: rx, rx!w. function(zephyr_linker_memory) - set(single_args "FLAGS;NAME;SIZE;START") - cmake_parse_arguments(MEMORY "" "${single_args}" "" ${ARGN}) + set(req_single_args "NAME;SIZE;START") + set(single_args "FLAGS") + cmake_parse_arguments(MEMORY "" "${req_single_args};${single_args}" "" ${ARGN}) if(MEMORY_UNPARSED_ARGUMENTS) message(FATAL_ERROR "zephyr_linker_memory(${ARGV0} ...) given unknown " @@ -4712,7 +4761,7 @@ function(zephyr_linker_memory) ) endif() - foreach(arg ${single_args}) + foreach(arg ${req_single_args}) if(NOT DEFINED MEMORY_${arg}) message(FATAL_ERROR "zephyr_linker_memory(${ARGV0} ...) missing required " "argument: ${arg}" @@ -4721,6 +4770,7 @@ function(zephyr_linker_memory) endforeach() set(MEMORY) + zephyr_linker_arg_val_list(MEMORY "${req_single_args}") zephyr_linker_arg_val_list(MEMORY "${single_args}") string(REPLACE ";" "\;" MEMORY "${MEMORY}") @@ -4730,7 +4780,7 @@ function(zephyr_linker_memory) endfunction() # Usage: -# zephyr_linker_memory_ifdef( NAME START
SIZE FLAGS ) +# zephyr_linker_memory_ifdef( NAME START
SIZE [FLAGS ]) # # Will create memory region if is enabled. # @@ -4793,9 +4843,9 @@ function(zephyr_linker_dts_section) endfunction() # Usage: -# zephyr_linker_dts_memory(PATH FLAGS ) -# zephyr_linker_dts_memory(NODELABEL FLAGS ) -# zephyr_linker_dts_memory(CHOSEN FLAGS ) +# zephyr_linker_dts_memory(PATH ) +# zephyr_linker_dts_memory(NODELABEL ) +# zephyr_linker_dts_memory(CHOSEN ) # # Zephyr linker devicetree memory. # This function specifies a memory region for the platform in use based on its @@ -4810,15 +4860,9 @@ endfunction() # NODELABEL