From 9b007aac249f8cffb20c4dde99ba63d22e9a2f09 Mon Sep 17 00:00:00 2001 From: olikraus Date: Tue, 5 Apr 2016 20:07:05 +0200 Subject: [PATCH] merge --- src/clib/u8g_com_atxmega_hw_spi.c | 174 +++++++++++++++++++ src/clib/u8g_com_atxmega_st7920_hw_spi.c | 202 +++++++++++++++++++++++ src/clib/u8g_com_linux_ssd_i2c.c | 168 +++++++++++++++++++ src/clib/u8g_com_psoc5_ssd_hw_parallel.c | 107 ++++++++++++ 4 files changed, 651 insertions(+) create mode 100644 src/clib/u8g_com_atxmega_hw_spi.c create mode 100644 src/clib/u8g_com_atxmega_st7920_hw_spi.c create mode 100644 src/clib/u8g_com_linux_ssd_i2c.c create mode 100644 src/clib/u8g_com_psoc5_ssd_hw_parallel.c diff --git a/src/clib/u8g_com_atxmega_hw_spi.c b/src/clib/u8g_com_atxmega_hw_spi.c new file mode 100644 index 0000000..4c2dfa2 --- /dev/null +++ b/src/clib/u8g_com_atxmega_hw_spi.c @@ -0,0 +1,174 @@ +/* + + u8g_com_atxmega_hw_spi.c + + Universal 8bit Graphics Library + + Copyright (c) 2011, olikraus@gmail.com + Copyright (c) 2015, florianmenne@t-online.de + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, + are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, this list + of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or other + materials provided with the distribution. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + A special SPI interface for ST7920 controller with HW SPI Support + + Assumes, that + MOSI is at PORTB, Pin 3 + and + SCK is at PORTB, Pin 5 + + Update for ATOMIC operation done (01 Jun 2013) + U8G_ATOMIC_OR(ptr, val) + U8G_ATOMIC_AND(ptr, val) + U8G_ATOMIC_START() + U8G_ATOMIC_END() + + +*/ + +#include "u8g.h" + +#if defined(__AVR_XMEGA__) +#define U8G_ATXMEGA_HW_SPI +#endif + + +#if defined(U8G_ATXMEGA_HW_SPI) + +#include +#include + + +static uint8_t u8g_atxmega_spi_out(uint8_t data) +{ + /* send data */ + SPIC.DATA = data; + + /* wait for transmission */ + while(!(SPIC.STATUS & SPI_IF_bm)); + + /* clear the SPIF flag by reading SPDR */ + return SPIC.DATA; +} + + +uint8_t u8g_com_atxmega_hw_spi_fn(u8g_t *u8g, uint8_t msg, uint8_t arg_val, void *arg_ptr) +{ + switch(msg) + { + case U8G_COM_MSG_STOP: + break; + + case U8G_COM_MSG_INIT: + + u8g_SetPIOutput(u8g, U8G_PI_CS); + u8g_SetPIOutput(u8g, U8G_PI_A0); + u8g_SetPIOutput(u8g, U8G_PI_RESET); + + //U8G_ATOMIC_START(); + + PORTC.DIR |= PIN4_bm | PIN5_bm | PIN7_bm; + PORTC.DIR &= ~PIN6_bm; + + //U8G_ATOMIC_END(); + + u8g_SetPILevel(u8g, U8G_PI_CS, 1); + + SPIC.CTRL = 0; + SPIC.CTRL = SPI_PRESCALER_DIV4_gc | // SPI prescaler. + //SPI_CLK2X_bm | //SPI Clock double. + SPI_ENABLE_bm | //Enable SPI module. + //SPI_DORD_bm | //Data order. + SPI_MASTER_bm | //SPI master. + SPI_MODE_0_gc; // SPI mode. + +#ifdef U8G_HW_SPI_2X + SPIC.CTRL |= SPI_CLK2X_bm; /* double speed, issue 89 */ +#endif + + break; + + case U8G_COM_MSG_ADDRESS: /* define cmd (arg_val = 0) or data mode (arg_val = 1) */ + u8g_SetPILevel(u8g, U8G_PI_A0, arg_val); + break; + + case U8G_COM_MSG_CHIP_SELECT: + + if ( arg_val == 0 ) + { + /* disable */ + u8g_SetPILevel(u8g, U8G_PI_CS, 1); + } + else + { + //PORTB &= ~_BV(5); /* SCK = 0 */ + PORTC.OUT &= ~PIN7_bm; + /* enable */ + u8g_SetPILevel(u8g, U8G_PI_CS, 0); /* CS = 0 (low active) */ + } + + break; + + case U8G_COM_MSG_RESET: + u8g_SetPILevel(u8g, U8G_PI_RESET, arg_val); + break; + + case U8G_COM_MSG_WRITE_BYTE: + u8g_atxmega_spi_out(arg_val); + break; + + case U8G_COM_MSG_WRITE_SEQ: + { + register uint8_t *ptr = arg_ptr; + while( arg_val > 0 ) + { + u8g_atxmega_spi_out(*ptr++); + arg_val--; + } + } + break; + case U8G_COM_MSG_WRITE_SEQ_P: + { + register uint8_t *ptr = arg_ptr; + while( arg_val > 0 ) + { + u8g_atxmega_spi_out(u8g_pgm_read(ptr)); + ptr++; + arg_val--; + } + } + break; + } + return 1; +} + +#else + +uint8_t u8g_com_atxmega_hw_spi_fn(u8g_t *u8g, uint8_t msg, uint8_t arg_val, void *arg_ptr) +{ + return 1; +} + +#endif \ No newline at end of file diff --git a/src/clib/u8g_com_atxmega_st7920_hw_spi.c b/src/clib/u8g_com_atxmega_st7920_hw_spi.c new file mode 100644 index 0000000..4b82385 --- /dev/null +++ b/src/clib/u8g_com_atxmega_st7920_hw_spi.c @@ -0,0 +1,202 @@ +/* + + u8g_com_atxmega_st7920_hw_spi.c + + Universal 8bit Graphics Library + + Copyright (c) 2011, olikraus@gmail.com + Copyright (c) 2015, florianmenne@t-online.de + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, + are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, this list + of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or other + materials provided with the distribution. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + A special SPI interface for ST7920 controller with HW SPI Support + + Assumes, that + MOSI is at PORTB, Pin 3 + and + SCK is at PORTB, Pin 5 + + Update for ATOMIC operation done (01 Jun 2013) + U8G_ATOMIC_OR(ptr, val) + U8G_ATOMIC_AND(ptr, val) + U8G_ATOMIC_START() + U8G_ATOMIC_END() + + +*/ + +#include "u8g.h" + +#if defined(__AVR_XMEGA__) +#define U8G_ATXMEGA_HW_SPI +#endif + +#if defined(U8G_ATXMEGA_HW_SPI) + +#include +#include + +static uint8_t u8g_atxmega_st7920_hw_spi_shift_out(u8g_t *u8g, uint8_t val) U8G_NOINLINE; +static uint8_t u8g_atxmega_st7920_hw_spi_shift_out(u8g_t *u8g, uint8_t val) +{ + /* send data */ + SPIC.DATA = val; + + /* wait for transmission */ + while(!(SPIC.STATUS & SPI_IF_bm)); + + /* clear the SPIF flag by reading SPDR */ + return SPIC.DATA; +} + + +static void u8g_com_atxmega_st7920_write_byte_hw_spi(u8g_t *u8g, uint8_t rs, uint8_t val) U8G_NOINLINE; +static void u8g_com_atxmega_st7920_write_byte_hw_spi(u8g_t *u8g, uint8_t rs, uint8_t val) +{ + uint8_t i; + + if ( rs == 0 ) + { + /* command */ + u8g_atxmega_st7920_hw_spi_shift_out(u8g, 0x0f8); + } + else if ( rs == 1 ) + { + /* data */ + u8g_atxmega_st7920_hw_spi_shift_out(u8g, 0x0fa); + } + + u8g_atxmega_st7920_hw_spi_shift_out(u8g, val & 0x0f0); + u8g_atxmega_st7920_hw_spi_shift_out(u8g, val << 4); + + for( i = 0; i < 4; i++ ) + u8g_10MicroDelay(); +} + + +uint8_t u8g_com_atxmega_st7920_hw_spi_fn(u8g_t *u8g, uint8_t msg, uint8_t arg_val, void *arg_ptr) +{ + switch(msg) + { + case U8G_COM_MSG_INIT: + u8g_SetPIOutput(u8g, U8G_PI_CS); + //u8g_SetPIOutput(u8g, U8G_PI_A0); + + //U8G_ATOMIC_START(); + + PORTC.DIR |= PIN4_bm | PIN5_bm | PIN7_bm; + PORTC.DIR &= ~PIN6_bm; + + //U8G_ATOMIC_END(); + + u8g_SetPILevel(u8g, U8G_PI_CS, 1); + + SPIC.CTRL = 0; + SPIC.CTRL = SPI_PRESCALER_DIV4_gc | // SPI prescaler. + //SPI_CLK2X_bm | //SPI Clock double. + SPI_ENABLE_bm | //Enable SPI module. + //SPI_DORD_bm | //Data order. + SPI_MASTER_bm | //SPI master. + SPI_MODE_0_gc; // SPI mode. + +#ifdef U8G_HW_SPI_2X + SPIC.CTRL |= SPI_CLK2X_bm; /* double speed, issue 89 */ +#endif + + u8g->pin_list[U8G_PI_A0_STATE] = 0; /* inital RS state: command mode */ + break; + + case U8G_COM_MSG_STOP: + break; + + case U8G_COM_MSG_RESET: + u8g_SetPILevel(u8g, U8G_PI_RESET, arg_val); + break; + + case U8G_COM_MSG_ADDRESS: /* define cmd (arg_val = 0) or data mode (arg_val = 1) */ + u8g->pin_list[U8G_PI_A0_STATE] = arg_val; + break; + + case U8G_COM_MSG_CHIP_SELECT: + if ( arg_val == 0 ) + { + /* disable, note: the st7920 has an active high chip select */ + u8g_SetPILevel(u8g, U8G_PI_CS, 0); + } + else + { + /* u8g_SetPILevel(u8g, U8G_PI_SCK, 0 ); */ + /* enable */ + u8g_SetPILevel(u8g, U8G_PI_CS, 1); /* CS = 1 (high active) */ + } + break; + + + case U8G_COM_MSG_WRITE_BYTE: + u8g_com_atxmega_st7920_write_byte_hw_spi(u8g, u8g->pin_list[U8G_PI_A0_STATE], arg_val); + //u8g->pin_list[U8G_PI_A0_STATE] = 2; + break; + + case U8G_COM_MSG_WRITE_SEQ: + { + register uint8_t *ptr = arg_ptr; + while( arg_val > 0 ) + { + u8g_com_atxmega_st7920_write_byte_hw_spi(u8g, u8g->pin_list[U8G_PI_A0_STATE], *ptr++); + //u8g->pin_list[U8G_PI_A0_STATE] = 2; + arg_val--; + } + } + break; + + case U8G_COM_MSG_WRITE_SEQ_P: + { + register uint8_t *ptr = arg_ptr; + while( arg_val > 0 ) + { + u8g_com_atxmega_st7920_write_byte_hw_spi(u8g, u8g->pin_list[U8G_PI_A0_STATE], u8g_pgm_read(ptr)); + //u8g->pin_list[U8G_PI_A0_STATE] = 2; + ptr++; + arg_val--; + } + } + break; + } + return 1; +} + +#else + + +uint8_t u8g_com_atxmega_st7920_hw_spi_fn(u8g_t *u8g, uint8_t msg, uint8_t arg_val, void *arg_ptr) +{ + return 1; +} + + +#endif + + \ No newline at end of file diff --git a/src/clib/u8g_com_linux_ssd_i2c.c b/src/clib/u8g_com_linux_ssd_i2c.c new file mode 100644 index 0000000..bd5b735 --- /dev/null +++ b/src/clib/u8g_com_linux_ssd_i2c.c @@ -0,0 +1,168 @@ +/* + + u8g_com_linux_ssd_i2c.c + + com interface for linux i2c-dev and the SSDxxxx chip (SOLOMON) variant + I2C protocol + + + Universal 8bit Graphics Library + + Copyright (c) 2012, olikraus@gmail.com + Copyright (c) 2015, daniel@redfelineninja.org.uk + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, + are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, this list + of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or other + materials provided with the distribution. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*/ + +#include "u8g.h" + +#if defined(U8G_LINUX) + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include + + +#define I2C_SLA 0x3c +#define I2C_CMD_MODE 0x80 +#define I2C_DATA_MODE 0x40 +#define MAX_PACKET 64 + +#ifndef U8G_WITH_PINLIST +#error U8G_WITH_PINLIST is mandatory for this driver +#endif + +static void set_cmd_mode(u8g_t *u8g, bool cmd_mode) +{ + u8g->pin_list[U8G_PI_A0_STATE] = cmd_mode; +} + +static bool get_cmd_mode(u8g_t *u8g) +{ + return u8g->pin_list[U8G_PI_A0_STATE]; +} + +static uint8_t send_data_burst(u8g_t *u8g, int fd, uint8_t *buf, size_t buflen) +{ + uint8_t i2cbuf[2*MAX_PACKET]; + uint8_t i2clen; + int res; + + /* ignore bursts when there is no file open */ + if (fd < 0) + return 0; + + if (get_cmd_mode(u8g)) { + i2clen = 0; + while (buflen > 0) { + i2cbuf[i2clen++] = I2C_CMD_MODE; + i2cbuf[i2clen++] = *buf++; + buflen--; + } + } else { + i2cbuf[0] = I2C_DATA_MODE; + memcpy(i2cbuf+1, buf, buflen); + i2clen = buflen + 1; + } + + res = write(fd, i2cbuf, i2clen); + if (res < 0) + fprintf(stderr, "I2C write failed (%s)\n", strerror(errno)); + else if (res != i2clen) + fprintf(stderr, "Incomplete I2C write (%d of %d packet)\n", res, i2clen); + + return res == i2clen; +} + +uint8_t u8g_com_linux_ssd_i2c_fn(u8g_t *u8g, uint8_t msg, uint8_t arg_val, void *arg_ptr) +{ + static int fd = -1; + char dev[24]; + + switch(msg) + { + case U8G_COM_MSG_INIT: + sprintf(dev, "/dev/i2c-%d", u8g->pin_list[U8G_PI_I2C_OPTION]); + fd = open(dev, O_RDWR); + if (fd < 0) { + fprintf(stderr, "cannot open %s (%s)\n", dev, strerror(errno)); + return 0; + } + + if (ioctl(fd, I2C_SLAVE, I2C_SLA) < 0) { + fprintf(stderr, "cannot set slave address (%s)\n", strerror(errno)); + return 0; + } + + break; + + case U8G_COM_MSG_STOP: + /* ignored - i2c-dev will automatically stop between writes */ + break; + + case U8G_COM_MSG_RESET: + /* ignored - no obvious means to reset an SSD via I2C */ + break; + + case U8G_COM_MSG_CHIP_SELECT: + set_cmd_mode(u8g, true); + break; + + case U8G_COM_MSG_WRITE_BYTE: + send_data_burst(u8g, fd, &arg_val, 1); + break; + + case U8G_COM_MSG_WRITE_SEQ: + case U8G_COM_MSG_WRITE_SEQ_P: /* no progmem in Linux */ + while (arg_val > MAX_PACKET) { + send_data_burst(u8g, fd, arg_ptr, MAX_PACKET); + arg_ptr += MAX_PACKET; + arg_val -= MAX_PACKET; + } + send_data_burst(u8g, fd, arg_ptr, arg_val); + break; + + case U8G_COM_MSG_ADDRESS: + /* choose cmd (arg_val = 0) or data mode (arg_val = 1) */ + set_cmd_mode(u8g, !arg_val); + break; + } + + return 1; +} + +#endif /* U8G_LINUX */ diff --git a/src/clib/u8g_com_psoc5_ssd_hw_parallel.c b/src/clib/u8g_com_psoc5_ssd_hw_parallel.c new file mode 100644 index 0000000..668c61b --- /dev/null +++ b/src/clib/u8g_com_psoc5_ssd_hw_parallel.c @@ -0,0 +1,107 @@ +/* + + u8g_com_psoc5_ssd_hw_parallel.c + + com interface for Cypress PSoC5 and the SSDxxxx chip variant + I2C protocol + + Universal 8bit Graphics Library + + Copyright (c) 2015, olikraus@gmail.com, schmidt.ronny@gmail.com + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, + are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, this list + of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or other + materials provided with the distribution. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + +*/ + +#include "u8g.h" + +#if defined(U8G_CYPRESS_PSOC5) + +#include + +static uint8 dc = 0; // need to store whether next write is data or command + +uint8_t u8g_com_psoc5_ssd_hw_parallel_fn(u8g_t *u8g, uint8_t msg, uint8_t arg_val, void *arg_ptr) +{ + switch(msg) + { + case U8G_COM_MSG_STOP: + // stop the device + GraphicLCDIntf_Stop(); + break; + + case U8G_COM_MSG_INIT: + // init hardware interfaces, timers, gpios, ... + GraphicLCDIntf_Init(); + break; + + case U8G_COM_MSG_ADDRESS: + // switch from cmd (arg_val = 0) to data mode (arg_val = 1) or vice versa + dc = arg_val; + break; + + case U8G_COM_MSG_CHIP_SELECT: + /* done by the hardware */ + break; + + case U8G_COM_MSG_RESET: + // toggle the reset pin of the display by value in arg_val + nRES_Write(0); + u8g_10MicroDelay(); + nRES_Write(1); + break; + + case U8G_COM_MSG_WRITE_BYTE: + // write byte to the device + GraphicLCDIntf_Write8(dc, arg_val); + break; + + case U8G_COM_MSG_WRITE_SEQ: + case U8G_COM_MSG_WRITE_SEQ_P: + { + // write a sequence of bytes to the device + register uint8_t *ptr = arg_ptr; + while (arg_val-- > 0) + { + GraphicLCDIntf_Write8(dc, *ptr++); + } + } + break; + + + } + return 1; +} + +#else + +uint8_t u8g_com_psoc5_ssd_hw_spi_fn(u8g_t *u8g, uint8_t msg, uint8_t arg_val, void *arg_ptr) +{ + return 1; +} + +#endif