You signed in with another tab or window. Reload to refresh your session.You signed out in another tab or window. Reload to refresh your session.You switched accounts on another tab or window. Reload to refresh your session.Dismiss alert
Remove mentions to FPGAs in simple-add and vector-add (#2578)
There will be no support for FPGAs in the 2025.1 release of the Intel OneAPI compiler.
This PR therefore removes mentions to FPGAs in the simple-add and vector-add samples.
Copy file name to clipboardExpand all lines: DirectProgramming/C++SYCL/DenseLinearAlgebra/simple-add/README.md
+5-153Lines changed: 5 additions & 153 deletions
Original file line number
Diff line number
Diff line change
@@ -15,27 +15,16 @@ The `Simple Add` sample is a simple program that adds two large vectors of integ
15
15
The basic SYCL implementations explained in the sample includes device selector,
16
16
USM, buffer, accessor, kernel, and command groups.
17
17
18
-
>**Note**: See the `Base: Vector Add` sample to examine another getting started sample you can use to learn more about using the Intel® oneAPI Toolkits to develop SYCL-compliant applications for CPU, GPU, and FPGA devices.
18
+
>**Note**: See the `Base: Vector Add` sample to examine another getting started sample you can use to learn more about using the Intel® oneAPI Toolkits to develop SYCL-compliant applications for CPUand GPU devices.
19
19
20
20
## Prerequisites
21
21
22
22
| Optimized for | Description
23
23
|:--- |:---
24
24
| OS | Ubuntu* 18.04 <br> Windows* 10, 11
25
-
| Hardware | GEN9 or newer <br> Intel® Agilex® 7, Arria® 10, and Stratix® 10 FPGAs
25
+
| Hardware | GEN9 or newer
26
26
| Software | Intel® oneAPI DPC++/C++ Compiler
27
27
28
-
29
-
> **Note**: Even though the Intel DPC++/C++ OneAPI compiler is enough to compile for CPU, GPU, FPGA emulation, generating FPGA reports and generating RTL for FPGAs, there are extra software requirements for the FPGA simulation flow and FPGA compiles.
30
-
>
31
-
> For using the simulator flow, Intel® Quartus® Prime Pro Edition and one of the following simulators must be installed and accessible through your PATH:
32
-
> - Questa*-Intel® FPGA Edition
33
-
> - Questa*-Intel® FPGA Starter Edition
34
-
> - ModelSim® SE
35
-
>
36
-
> When using the hardware compile flow, Intel® Quartus® Prime Pro Edition must be installed and accessible through your PATH.
37
-
> **Warning** Make sure you add the device files associated with the FPGA that you are targeting to your Intel® Quartus® Prime installation.
38
-
39
28
## Key Implementation Details
40
29
41
30
This sample provides examples of both buffers and USM implementations for simple side-by-side comparison.
@@ -105,20 +94,7 @@ To learn more about the extensions and how to configure the oneAPI environment,
105
94
cmake .. -DUSM=1
106
95
```
107
96
108
-
> **Note**: When building for FPGAs, the default FPGA family will be used (Intel® Agilex® 7).
109
-
> You can change the default target by using the command:
110
-
> ```
111
-
> cmake .. -DFPGA_DEVICE=<FPGA device family or FPGA part number>
112
-
> ```
113
-
>
114
-
> Alternatively, you can target an explicit FPGA board variant and BSP by using the following command:
4. Run on FPGA hardware (only if you ran `cmake` with `-DFPGA_DEVICE=<board-support-package>:<board-variant>`).
270
-
```
271
-
./simple-add-buffers.fpga
272
-
./simple-add-usm.fpga
273
-
```
274
160
275
161
### On Windows
276
162
277
-
#### Run for CPU and GPU
278
-
279
163
1. Change to the output directory.
280
164
281
165
2. Run the program for Unified Shared Memory (USM) and buffers.
@@ -284,31 +168,9 @@ If you receive an error message, troubleshoot the problem using the **Diagnostic
284
168
simple-add-buffers.exe
285
169
```
286
170
287
-
#### Run for FPGA
288
-
289
-
1. Change to the output directory.
290
-
291
-
2. Run for FPGA emulation.
292
-
```
293
-
simple-add-buffers.fpga_emu.exe
294
-
simple-add-usm.fpga_emu.exe
295
-
```
296
-
3. Run on FPGA simulator.
297
-
```
298
-
set CL_CONTEXT_MPSIM_DEVICE_INTELFPGA=1
299
-
simple-add-buffers.fpga_sim.exe
300
-
simple-add-usm.fpga_sim.exe
301
-
set CL_CONTEXT_MPSIM_DEVICE_INTELFPGA=
302
-
```
303
-
4. Run on FPGA hardware (only if you ran `cmake` with `-DFPGA_DEVICE=<board-support-package>:<board-variant>`).
304
-
```
305
-
simple-add-buffers.fpga.exe
306
-
simple-add-usm.fpga.exe
307
-
```
308
-
309
171
### Build and Run the `Simple Add` Sample in Intel® DevCloud (Optional)
310
172
311
-
When running a sample in the Intel® DevCloud, you must specify the compute node (CPU, GPU, FPGA) and whether to run in batch or interactive mode.
173
+
When running a sample in the Intel® DevCloud, you must specify the compute node (CPU, GPU) and whether to run in batch or interactive mode.
312
174
313
175
>**Note**: Since Intel® DevCloud for oneAPI includes the appropriate development environment already configured, you do not need to set environment variables.
>**Note**: For more information on how to specify compute nodes, read *[Launch and manage jobs](https://devcloud.intel.com/oneapi/documentation/job-submission/)* in the Intel® DevCloud for oneAPI Documentation.
336
195
337
-
Only `fpga_compile` nodes support compiling to FPGA. When compiling for FPGA hardware, increase the job timeout to **24 hours**.
338
-
339
-
Executing programs on FPGA hardware is only supported on `fpga_runtime` nodes of the appropriate type, such as `fpga_runtime:arria10`.
340
-
341
-
Neither compiling nor executing programs on FPGA hardware are supported on the login nodes. For more information, see the Intel® DevCloud for oneAPI [*Intel® oneAPI Base Toolkit Get Started*](https://devcloud.intel.com/oneapi/get_started/) page.
0 commit comments