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Is the configuration for the OutputClock incomplete? In the register definitions, there is a CLOCK_GATE which enables/disables the output gate, but there is also a GATE_RUN register which "sets the gate using run status. Bit 0 = 0: Clock runs whenever CLOCK_GATE(0) is 1. Bit 0 = 1: Clock runs only when acquisition is in RUNNING state."
Currently, only CLOCK_GATE is written to. If the GATE_RUN register is always set to 0, this would be correct, but from the datasheet it appears that the POR value for GATE_RUN is 1, indicating that CLOCK_GATE might not have any effect right now.
The text was updated successfully, but these errors were encountered:
CLOCK_GATE is a global enable for this device. If it's 0 there will not be an output, no matter what. If it's 1 there might be an output GATE_RUN means that, when '0' the clock is free-running (always tied to CLOCK_GATE master enable, of course) and when '1' the clock will only run when acquisition is active.
Since in a Bonsai onix1 workflow there is no situation in which the workflow is running but acquisition is not, the GATE_RUN option is meaningless here, since acquisition is always running. Externalizing it will do nothing.
However, we should configure it to '1', even if it's the default value, in case it were modified externally somehow. A good practice for this lib should be to always initialize all registers.
Is the configuration for the
OutputClock
incomplete? In the register definitions, there is aCLOCK_GATE
which enables/disables the output gate, but there is also aGATE_RUN
register which "sets the gate using run status. Bit 0 = 0: Clock runs whenever CLOCK_GATE(0) is 1. Bit 0 = 1: Clock runs only when acquisition is in RUNNING state."Currently, only
CLOCK_GATE
is written to. If theGATE_RUN
register is always set to 0, this would be correct, but from the datasheet it appears that the POR value forGATE_RUN
is 1, indicating thatCLOCK_GATE
might not have any effect right now.The text was updated successfully, but these errors were encountered: