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AyoubJalaliASintzoff
andauthoredJan 31, 2025··
Makefile : Add target to generate functional coverage using verdi tool (#2755)
Co-authored-by: André Sintzoff <61976467+ASintzoff@users.noreply.github.com>
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‎verif/sim/Makefile

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@@ -382,6 +382,9 @@ questa-uvm:
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generate_cov_dash:
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urg -warn none -hvp_proj cva6_embedded -format both -group instcov_for_score -hvp_attributes weight+description+Comment -dir vcs_results/default/vcs.d/simv.vdb -plan cva6.hvp -tgl portsonly
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generate_verdi_cov:
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-verdi -cov -format both -group instcov_for_score -covdir vcs_results/default/vcs.d/simv.vdb -plan cva6.hvp -tgl portsonly
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vcs_clean_all:
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@echo "[VCS] Cleanup (entire vcs_work dir)"
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rm -rf $(CVA6_REPO_DIR)/verif/sim/vcs_results/ verdiLog/ simv* *.daidir *.vpd *.fsdb *.db csrc ucli.key vc_hdrs.h novas* inter.fsdb uart

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