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RISC-V: C2: Support Zvbb Vector And-Not instruction
modify Test and match rule name
1 parent e9e33fc commit 29c1c9b

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4 files changed

+14
-161
lines changed

4 files changed

+14
-161
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‎src/hotspot/cpu/riscv/riscv_v.ad

+8-8
Original file line numberDiff line numberDiff line change
@@ -1116,7 +1116,7 @@ instruct vxor_regL_masked(vReg dst_src, iRegL src, vRegMask_V0 v0) %{
11161116

11171117
// vector and not
11181118

1119-
instruct vandnI(vReg dst, vReg src2, vReg src1, immI_M1 m1) %{
1119+
instruct vand_notI(vReg dst, vReg src2, vReg src1, immI_M1 m1) %{
11201120
predicate(UseZvbb);
11211121
predicate(Matcher::vector_element_basic_type(n) == T_INT ||
11221122
Matcher::vector_element_basic_type(n) == T_BYTE ||
@@ -1133,7 +1133,7 @@ instruct vandnI(vReg dst, vReg src2, vReg src1, immI_M1 m1) %{
11331133
ins_pipe(pipe_slow);
11341134
%}
11351135

1136-
instruct vandnL(vReg dst, vReg src2, vReg src1, immL_M1 m1) %{
1136+
instruct vand_notL(vReg dst, vReg src2, vReg src1, immL_M1 m1) %{
11371137
predicate(UseZvbb);
11381138
predicate(Matcher::vector_element_basic_type(n) == T_LONG);
11391139
match(Set dst (AndV src2 (XorV src1 (Replicate m1))));
@@ -1147,7 +1147,7 @@ instruct vandnL(vReg dst, vReg src2, vReg src1, immL_M1 m1) %{
11471147
ins_pipe(pipe_slow);
11481148
%}
11491149

1150-
instruct vandnI_masked(vReg dst, vReg src2, vReg src1, immI_M1 m1, vRegMask_V0 v0) %{
1150+
instruct vand_notI_masked(vReg dst, vReg src2, vReg src1, immI_M1 m1, vRegMask_V0 v0) %{
11511151
predicate(UseZvbb);
11521152
predicate(Matcher::vector_element_basic_type(n) == T_INT ||
11531153
Matcher::vector_element_basic_type(n) == T_BYTE ||
@@ -1165,7 +1165,7 @@ instruct vandnI_masked(vReg dst, vReg src2, vReg src1, immI_M1 m1, vRegMask_V0 v
11651165
ins_pipe(pipe_slow);
11661166
%}
11671167

1168-
instruct vandnL_masked(vReg dst, vReg src2, vReg src1, immL_M1 m1, vRegMask_V0 v0) %{
1168+
instruct vand_notL_masked(vReg dst, vReg src2, vReg src1, immL_M1 m1, vRegMask_V0 v0) %{
11691169
predicate(UseZvbb);
11701170
predicate(Matcher::vector_element_basic_type(n) == T_LONG);
11711171
match(Set dst (AndV (Binary src2 (XorV (Binary src1 (Replicate m1)) v0)) v0));
@@ -1180,7 +1180,7 @@ instruct vandnL_masked(vReg dst, vReg src2, vReg src1, immL_M1 m1, vRegMask_V0 v
11801180
ins_pipe(pipe_slow);
11811181
%}
11821182

1183-
instruct vandnI_regI(vReg dst, vReg src2, iRegIorL2I src1, immI_M1 m1) %{
1183+
instruct vand_not_regI(vReg dst, vReg src2, iRegIorL2I src1, immI_M1 m1) %{
11841184
predicate(UseZvbb);
11851185
predicate(Matcher::vector_element_basic_type(n) == T_INT ||
11861186
Matcher::vector_element_basic_type(n) == T_BYTE ||
@@ -1197,7 +1197,7 @@ instruct vandnI_regI(vReg dst, vReg src2, iRegIorL2I src1, immI_M1 m1) %{
11971197
ins_pipe(pipe_slow);
11981198
%}
11991199

1200-
instruct vandnL_regL(vReg dst, vReg src2, iRegL src1, immL_M1 m1) %{
1200+
instruct vand_not_regL(vReg dst, vReg src2, iRegL src1, immL_M1 m1) %{
12011201
predicate(UseZvbb);
12021202
predicate(Matcher::vector_element_basic_type(n) == T_LONG);
12031203
match(Set dst (AndV src2 (Replicate (XorL src1 m1))));
@@ -1211,7 +1211,7 @@ instruct vandnL_regL(vReg dst, vReg src2, iRegL src1, immL_M1 m1) %{
12111211
ins_pipe(pipe_slow);
12121212
%}
12131213

1214-
instruct vandnI_regI_masked(vReg dst, vReg src2, iRegIorL2I src1, immI_M1 m1, vRegMask_V0 v0) %{
1214+
instruct vand_not_regI_masked(vReg dst, vReg src2, iRegIorL2I src1, immI_M1 m1, vRegMask_V0 v0) %{
12151215
predicate(UseZvbb);
12161216
predicate(Matcher::vector_element_basic_type(n) == T_INT ||
12171217
Matcher::vector_element_basic_type(n) == T_BYTE ||
@@ -1229,7 +1229,7 @@ instruct vandnI_regI_masked(vReg dst, vReg src2, iRegIorL2I src1, immI_M1 m1, vR
12291229
ins_pipe(pipe_slow);
12301230
%}
12311231

1232-
instruct vandnL_regL_masked(vReg dst, vReg src2, iRegL src1, immL_M1 m1, vRegMask_V0 v0) %{
1232+
instruct vand_not_regL_masked(vReg dst, vReg src2, iRegL src1, immL_M1 m1, vRegMask_V0 v0) %{
12331233
predicate(UseZvbb);
12341234
predicate(Matcher::vector_element_basic_type(n) == T_LONG);
12351235
match(Set dst (AndV (Binary src2 (Replicate (XorL src1 m1))) v0));

‎test/hotspot/jtreg/compiler/lib/ir_framework/IRNode.java

-15
Original file line numberDiff line numberDiff line change
@@ -1992,21 +1992,6 @@ public class IRNode {
19921992
machOnlyNameRegex(VAND_NOT_L, "vand_notL");
19931993
}
19941994

1995-
public static final String RISCV_VAND_NOT_I = PREFIX + "RISCV_VAND_NOT_I" + POSTFIX;
1996-
static {
1997-
machOnlyNameRegex(RISCV_VAND_NOT_I, "vandnI");
1998-
}
1999-
2000-
public static final String RISCV_VAND_NOT_L = PREFIX + "RISCV_VAND_NOT_L" + POSTFIX;
2001-
static {
2002-
machOnlyNameRegex(RISCV_VAND_NOT_L, "vandnL");
2003-
}
2004-
2005-
public static final String RISCV_VAND_NOT_I_MASKED = PREFIX + "RISCV_VAND_NOT_I_MASKED" + POSTFIX;
2006-
static {
2007-
machOnlyNameRegex(RISCV_VAND_NOT_I_MASKED, "vandnI_masked");
2008-
}
2009-
20101995
public static final String VECTOR_BLEND_B = VECTOR_PREFIX + "VECTOR_BLEND_B" + POSTFIX;
20111996
static {
20121997
vectorNode(VECTOR_BLEND_B, "VectorBlend", TYPE_BYTE);

‎test/hotspot/jtreg/compiler/vectorapi/AllBitsSetVectorMatchRuleTest.java

+6-4
Original file line numberDiff line numberDiff line change
@@ -42,8 +42,8 @@
4242
* @key randomness
4343
* @library /test/lib /
4444
* @requires vm.compiler2.enabled
45-
* @requires vm.cpu.features ~= ".*asimd.*"
46-
* @summary AArch64: [vector] Make all bits set vector sharable for match rules
45+
* @requires (vm.cpu.features ~= ".*asimd.*") | (os.arch == "riscv64")
46+
* @summary [vector] Make all bits set vector sharable for match rules
4747
* @modules jdk.incubator.vector
4848
*
4949
* @run driver compiler.vectorapi.AllBitsSetVectorMatchRuleTest
@@ -84,7 +84,8 @@ public class AllBitsSetVectorMatchRuleTest {
8484

8585
@Test
8686
@Warmup(10000)
87-
@IR(counts = { IRNode.VAND_NOT_I, " >= 1" })
87+
@IR(counts = { IRNode.VAND_NOT_I, " >= 1" }, applyIf = {"UseZvbb", "> 0"})
88+
@IR(counts = { IRNode.VAND_NOT_I, " >= 1" }, applyIfCPUFeatureOr = {"asimd", "true"})
8889
public static void testAllBitsSetVector() {
8990
IntVector av = IntVector.fromArray(I_SPECIES, ia, 0);
9091
IntVector bv = IntVector.fromArray(I_SPECIES, ib, 0);
@@ -98,7 +99,8 @@ public static void testAllBitsSetVector() {
9899

99100
@Test
100101
@Warmup(10000)
101-
@IR(counts = { IRNode.VAND_NOT_L, " >= 1" }, applyIf = {"UseSVE", "0"})
102+
@IR(counts = { IRNode.VAND_NOT_L, " >= 1" }, applyIf = {"UseZvbb", "> 0"})
103+
@IR(counts = { IRNode.VAND_NOT_L, " >= 1" }, applyIf = {"UseSVE", "0"}, applyIfCPUFeatureOr = {"asimd", "true"})
102104
@IR(counts = { IRNode.VMASK_AND_NOT_L, " >= 1" }, applyIf = {"UseSVE", "> 0"})
103105
public static void testAllBitsSetMask() {
104106
VectorMask<Long> avm = VectorMask.fromArray(L_SPECIES, ma, 0);

‎test/hotspot/jtreg/compiler/vectorapi/VectorAndNotMatchRuleTest.java

-134
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