RISC-V: C2: Support Zvbb Vector And-Not instruction

modify some test

Author: Anjian-Wen

src/hotspot/cpu/riscv/assembler_riscv.hpp

@@ -2270,7 +2270,6 @@ enum Nf {
   }
 
   // Vector Bit-manipulation used in Cryptography (Zvbb) Extension
-  INSN(vandn_vx,   0b1010111, 0b100, 0b000001);
   INSN(vrol_vx,    0b1010111, 0b100, 0b010101);
   INSN(vror_vx,    0b1010111, 0b100, 0b010100);
 

src/hotspot/cpu/riscv/riscv_v.ad

@@ -1180,70 +1180,6 @@ instruct vand_notL_masked(vReg dst, vReg src2, vReg src1, immL_M1 m1, vRegMask_V
   ins_pipe(pipe_slow);
 %}
 
-instruct vand_not_regI(vReg dst, vReg src2, iRegIorL2I src1, immI_M1 m1) %{
-  predicate(UseZvbb);
-  predicate(Matcher::vector_element_basic_type(n) == T_INT ||
-            Matcher::vector_element_basic_type(n) == T_BYTE ||
-            Matcher::vector_element_basic_type(n) == T_SHORT);
-  match(Set dst (AndV src2 (Replicate (XorI src1 m1))));
-  format %{ "vandn.vx $dst, $src2, $src1" %}
-  ins_encode %{
-    BasicType bt = Matcher::vector_element_basic_type(this);
-    __ vsetvli_helper(bt, Matcher::vector_length(this));
-    __ vandn_vx(as_VectorRegister($dst$$reg),
-                as_VectorRegister($src2$$reg),
-                as_Register($src1$$reg));
-  %}
-  ins_pipe(pipe_slow);
-%}
-
-instruct vand_not_regL(vReg dst, vReg src2, iRegL src1, immL_M1 m1) %{
-  predicate(UseZvbb);
-  predicate(Matcher::vector_element_basic_type(n) == T_LONG);
-  match(Set dst (AndV src2 (Replicate (XorL src1 m1))));
-  format %{ "vandn.vx $dst, $src2, $src1" %}
-  ins_encode %{
-    __ vsetvli_helper(T_LONG, Matcher::vector_length(this));
-    __ vandn_vx(as_VectorRegister($dst$$reg),
-                as_VectorRegister($src2$$reg),
-                as_Register($src1$$reg));
-  %}
-  ins_pipe(pipe_slow);
-%}
-
-instruct vand_not_regI_masked(vReg dst, vReg src2, iRegIorL2I src1, immI_M1 m1, vRegMask_V0 v0) %{
-  predicate(UseZvbb);
-  predicate(Matcher::vector_element_basic_type(n) == T_INT ||
-            Matcher::vector_element_basic_type(n) == T_BYTE ||
-            Matcher::vector_element_basic_type(n) == T_SHORT);
-  match(Set dst (AndV (Binary src2 (Replicate (XorI src1 m1))) v0));
-  format %{ "vandn.vx $dst, $src2, $src1, $v0" %}
-  ins_encode %{
-    BasicType bt = Matcher::vector_element_basic_type(this);
-    __ vsetvli_helper(bt, Matcher::vector_length(this));
-    __ vandn_vx(as_VectorRegister($dst$$reg),
-                as_VectorRegister($src2$$reg),
-                as_Register($src1$$reg),
-                Assembler::v0_t);
-  %}
-  ins_pipe(pipe_slow);
-%}
-
-instruct vand_not_regL_masked(vReg dst, vReg src2, iRegL src1, immL_M1 m1, vRegMask_V0 v0) %{
-  predicate(UseZvbb);
-  predicate(Matcher::vector_element_basic_type(n) == T_LONG);
-  match(Set dst (AndV (Binary src2 (Replicate (XorL src1 m1))) v0));
-  format %{ "vandn.vx $dst, $src2, $src1, $v0" %}
-  ins_encode %{
-    __ vsetvli_helper(T_LONG, Matcher::vector_length(this));
-    __ vandn_vx(as_VectorRegister($dst$$reg),
-                as_VectorRegister($src2$$reg),
-                as_Register($src1$$reg),
-                Assembler::v0_t);
-  %}
-  ins_pipe(pipe_slow);
-%}
-
 // ------------------------------ Vector not -----------------------------------
 
 // vector not

test/hotspot/jtreg/compiler/lib/ir_framework/IRNode.java

@@ -1992,11 +1992,6 @@ public class IRNode {
         machOnlyNameRegex(VAND_NOT_L, "vand_notL");
     }
 
-    public static final String VAND_NOT_REGI = PREFIX + "VAND_NOT_REGI" + POSTFIX;
-    static {
-        machOnlyNameRegex(VAND_NOT_REGI, "vand_not_regI");
-    }
-
     public static final String VECTOR_BLEND_B = VECTOR_PREFIX + "VECTOR_BLEND_B" + POSTFIX;
     static {
         vectorNode(VECTOR_BLEND_B, "VectorBlend", TYPE_BYTE);

test/hotspot/jtreg/compiler/vectorapi/AllBitsSetVectorMatchRuleTest.java

@@ -98,8 +98,9 @@ public static void testAllBitsSetVector() {
 
     @Test
     @Warmup(10000)
-    @IR(counts = { IRNode.VAND_NOT_L, " >= 1" }, applyIf = {"UseSVE", "0"})
-    @IR(counts = { IRNode.VMASK_AND_NOT_L, " >= 1" }, applyIf = {"UseSVE", "> 0"})
+    @IR(counts = { IRNode.VAND_NOT_L, " >= 1" }, applyIfPlatform = {"aarch64", "true"}, applyIf = {"UseSVE", "0"})
+    @IR(counts = { IRNode.VMASK_AND_NOT_L, " >= 1" }, applyIfPlatform = {"aarch64", "true"}, applyIf = {"UseSVE", "> 0"})
+    @IR(counts = { IRNode.VAND_NOT_L, " >= 1" }, applyIfPlatform = {"riscv64", "true"}, applyIfCPUFeatureOr = {"zvbb", "true"})
     public static void testAllBitsSetMask() {
         VectorMask<Long> avm = VectorMask.fromArray(L_SPECIES, ma, 0);
         VectorMask<Long> bvm = VectorMask.fromArray(L_SPECIES, mb, 0);
@@ -112,20 +113,6 @@ public static void testAllBitsSetMask() {
         }
     }
 
-    @Test
-    @Warmup(10000)
-    @IR(counts = { IRNode.VAND_NOT_REGI, " >= 1" }, applyIfCPUFeatureOr = {"zvbb", "true"})
-    public static void testAllBitsSetVectorRegI() {
-        IntVector av = IntVector.fromArray(I_SPECIES, ia, 0);
-        int bs = ib[0];
-        av.not().lanewise(VectorOperators.AND_NOT, bs).intoArray(ir, 0);
-
-        // Verify results
-        for (int i = 0; i < I_SPECIES.length(); i++) {
-            Asserts.assertEquals((~ia[i]) & (~bs), ir[i]);
-        }
-    }
-
     public static void main(String[] args) {
         TestFramework.runWithFlags("--add-modules=jdk.incubator.vector");
     }