RISC-V: C2: Support Zvbb Vector And-Not instruction

correct XorL to XorI and add Tests

Author: Anjian-Wen

src/hotspot/cpu/riscv/riscv_v.ad

@@ -1185,7 +1185,7 @@ instruct vandnI_regI(vReg dst, vReg src2, iRegIorL2I src1, immI_M1 m1) %{
   predicate(Matcher::vector_element_basic_type(n) == T_INT ||
             Matcher::vector_element_basic_type(n) == T_BYTE ||
             Matcher::vector_element_basic_type(n) == T_SHORT);
-  match(Set dst (AndV src2 (Replicate (XorL src1 m1))));
+  match(Set dst (AndV src2 (Replicate (XorI src1 m1))));
   format %{ "vandn.vx $dst, $src2, $src1" %}
   ins_encode %{
     BasicType bt = Matcher::vector_element_basic_type(this);

test/hotspot/jtreg/compiler/lib/ir_framework/IRNode.java

@@ -1985,16 +1985,18 @@ public class IRNode {
     public static final String VAND_NOT_I = PREFIX + "VAND_NOT_I" + POSTFIX;
     static {
         machOnlyNameRegex(VAND_NOT_I, "vand_notI");
+        machOnlyNameRegex(VAND_NOT_I, "vandnI");
     }
 
-    public static final String VAND_NOT_I_RISCV = PREFIX + "VAND_NOT_I" + POSTFIX;
+    public static final String VAND_NOT_L = PREFIX + "VAND_NOT_L" + POSTFIX;
     static {
-        machOnlyNameRegex(VAND_NOT_I_RISCV, "vandnI");
+        machOnlyNameRegex(VAND_NOT_L, "vand_notL");
+        machOnlyNameRegex(VAND_NOT_L, "vandnL");
     }
 
-    public static final String VAND_NOT_L = PREFIX + "VAND_NOT_L" + POSTFIX;
+    public static final String VAND_NOT_I_MASKED = PREFIX + "VAND_NOT_I_MASKED" + POSTFIX;
     static {
-        machOnlyNameRegex(VAND_NOT_L, "vand_notL");
+        machOnlyNameRegex(VAND_NOT_I_MASKED, "vandnI_masked");
     }
 
     public static final String VECTOR_BLEND_B = VECTOR_PREFIX + "VECTOR_BLEND_B" + POSTFIX;

test/hotspot/jtreg/compiler/vectorapi/AllBitsSetVectorMatchRuleTest.java

@@ -42,7 +42,7 @@
  * @key randomness
  * @library /test/lib /
  * @requires vm.compiler2.enabled
- * @requires (vm.cpu.features ~= ".*asimd.*") | (os.simpleArch == "riscv64" & vm.cpu.features ~= ".*zvbb.*")
+ * @requires vm.cpu.features ~= ".*asimd.*"
  * @summary AArch64: [vector] Make all bits set vector sharable for match rules
  * @modules jdk.incubator.vector
  *
@@ -84,8 +84,7 @@ public class AllBitsSetVectorMatchRuleTest {
 
     @Test
     @Warmup(10000)
-    @IR(counts = { IRNode.VAND_NOT_I, " >= 1" }, applyIf = {"UseZvbb", "0"})
-    @IR(counts = { IRNode.VAND_NOT_I_RISCV, " >= 1" }, applyIf = {"UseZvbb", "> 0"})
+    @IR(counts = { IRNode.VAND_NOT_I, " >= 1" })
     public static void testAllBitsSetVector() {
         IntVector av = IntVector.fromArray(I_SPECIES, ia, 0);
         IntVector bv = IntVector.fromArray(I_SPECIES, ib, 0);

test/hotspot/jtreg/compiler/vectorapi/VectorAndNotMatchRuleTest.java

@@ -0,0 +1,134 @@
+/*
+ * Copyright (c) 2022, Arm Limited. All rights reserved.
+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
+ * This code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 only, as
+ * published by the Free Software Foundation.
+ *
+ * This code is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * version 2 for more details (a copy is included in the LICENSE file that
+ * accompanied this code).
+ *
+ * You should have received a copy of the GNU General Public License version
+ * 2 along with this work; if not, write to the Free Software Foundation,
+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
+ * or visit www.oracle.com if you need additional information or have any
+ * questions.
+ */
+
+package compiler.vectorapi;
+
+import compiler.lib.ir_framework.*;
+
+import java.util.Random;
+
+import jdk.incubator.vector.IntVector;
+import jdk.incubator.vector.LongVector;
+import jdk.incubator.vector.VectorMask;
+import jdk.incubator.vector.VectorOperators;
+import jdk.incubator.vector.VectorSpecies;
+
+import jdk.test.lib.Asserts;
+import jdk.test.lib.Utils;
+
+/**
+ * @test
+ * @bug 8329887
+ * @key randomness
+ * @library /test/lib /
+ * @requires vm.compiler2.enabled
+ * @requires os.arch == "riscv64" & vm.cpu.features ~= ".*zvbb.*"
+ * @summary RISCV: [vector] zvbb extension And-Not support Test for match rules
+ * @modules jdk.incubator.vector
+ *
+ * @run driver compiler.vectorapi.VectorAndNotMatchRuleTest
+ */
+
+public class VectorAndNotMatchRuleTest {
+    private static final VectorSpecies<Integer> I_SPECIES = IntVector.SPECIES_MAX;
+    private static final VectorSpecies<Long> L_SPECIES = LongVector.SPECIES_MAX;
+
+    private static int LENGTH = 128;
+    private static final Random RD = Utils.getRandomInstance();
+
+    private static int[] ia;
+    private static int[] ib;
+    private static int[] ir;
+    private static boolean[] ma;
+    private static boolean[] mb;
+    private static boolean[] mc;
+    private static boolean[] mr;
+
+    static {
+        ia = new int[LENGTH];
+        ib = new int[LENGTH];
+        ir = new int[LENGTH];
+        ma = new boolean[LENGTH];
+        mb = new boolean[LENGTH];
+        mc = new boolean[LENGTH];
+        mr = new boolean[LENGTH];
+
+        for (int i = 0; i < LENGTH; i++) {
+            ia[i] = RD.nextInt(25);
+            ib[i] = RD.nextInt(25);
+            ma[i] = RD.nextBoolean();
+            mb[i] = RD.nextBoolean();
+            mc[i] = RD.nextBoolean();
+        }
+    }
+
+    @Test
+    @Warmup(10000)
+    @IR(counts = { IRNode.VAND_NOT_I, " >= 1" }, applyIf = {"UseZvbb", "> 0"})
+    public static void testVectorVAndNotI() {
+        IntVector av = IntVector.fromArray(I_SPECIES, ia, 0);
+        IntVector bv = IntVector.fromArray(I_SPECIES, ib, 0);
+        av.not().lanewise(VectorOperators.AND_NOT, bv).intoArray(ir, 0);
+
+        // Verify results
+        for (int i = 0; i < I_SPECIES.length(); i++) {
+            Asserts.assertEquals((~ia[i]) & (~ib[i]), ir[i]);
+        }
+    }
+
+    @Test
+    @Warmup(10000)
+    @IR(counts = { IRNode.VAND_NOT_L, " >= 1" }, applyIf = {"UseZvbb", "> 0"})
+    public static void testVectorVAndNotL() {
+        VectorMask<Long> avm = VectorMask.fromArray(L_SPECIES, ma, 0);
+        VectorMask<Long> bvm = VectorMask.fromArray(L_SPECIES, mb, 0);
+        VectorMask<Long> cvm = VectorMask.fromArray(L_SPECIES, mc, 0);
+        avm.andNot(bvm).andNot(cvm).intoArray(mr, 0);
+
+        // Verify results
+        for (int i = 0; i < L_SPECIES.length(); i++) {
+            Asserts.assertEquals((ma[i] & (!mb[i])) & (!mc[i]), mr[i]);
+        }
+    }
+
+    @Test
+    @Warmup(10000)
+    @IR(counts = { IRNode.VAND_NOT_I_MASKED, " >= 1" }, applyIf = {"UseZvbb", "> 0"} )
+    public static void testVectorVAndNotIMasked() {
+        VectorMask<Integer> avm = VectorMask.fromArray(I_SPECIES, ma, 0);
+        IntVector av = IntVector.fromArray(I_SPECIES, ia, 0);
+        IntVector bv = IntVector.fromArray(I_SPECIES, ib, 0);
+        av.not().lanewise(VectorOperators.AND_NOT, bv, avm).intoArray(ir, 0);
+
+        // Verify results
+        for (int i = 0; i < I_SPECIES.length(); i++) {
+            if (ma[i] == true) {
+                Asserts.assertEquals((~ia[i]) & (~ib[i]), ir[i]);
+            }
+        }
+    }
+
+    public static void main(String[] args) {
+        TestFramework.runWithFlags("--add-modules=jdk.incubator.vector");
+    }
+}