From 7fc67099ad4b7c928c7c7c8bcbb702c69bc4a822 Mon Sep 17 00:00:00 2001 From: Anjian-Wen Date: Mon, 31 Mar 2025 14:00:36 +0800 Subject: [PATCH 1/8] RISC-V: C2: Support Zvbb Vector And-Not instruction add Vector And-Not match rule and tests --- src/hotspot/cpu/riscv/riscv_v.ad | 68 +++++++++++++++++++ .../AllBitsSetVectorMatchRuleTest.java | 9 +-- 2 files changed, 73 insertions(+), 4 deletions(-) diff --git a/src/hotspot/cpu/riscv/riscv_v.ad b/src/hotspot/cpu/riscv/riscv_v.ad index 9892d2b9c0392..5cf7fff6a4e19 100644 --- a/src/hotspot/cpu/riscv/riscv_v.ad +++ b/src/hotspot/cpu/riscv/riscv_v.ad @@ -1112,6 +1112,74 @@ instruct vxor_regL_masked(vReg dst_src, iRegL src, vRegMask_V0 v0) %{ ins_pipe(pipe_slow); %} +// ------------------------------ Vector and not ----------------------------------- + +// vector and not + +instruct vand_notI(vReg dst, vReg src2, vReg src1, immI_M1 m1) %{ + predicate(UseZvbb); + predicate(Matcher::vector_element_basic_type(n) == T_INT || + Matcher::vector_element_basic_type(n) == T_BYTE || + Matcher::vector_element_basic_type(n) == T_SHORT); + match(Set dst (AndV src2 (XorV src1 (Replicate m1)))); + format %{ "vandn.vv $dst, $src2, $src1" %} + ins_encode %{ + BasicType bt = Matcher::vector_element_basic_type(this); + __ vsetvli_helper(bt, Matcher::vector_length(this)); + __ vandn_vv(as_VectorRegister($dst$$reg), + as_VectorRegister($src2$$reg), + as_VectorRegister($src1$$reg)); + %} + ins_pipe(pipe_slow); +%} + +instruct vand_notL(vReg dst, vReg src2, vReg src1, immL_M1 m1) %{ + predicate(UseZvbb); + predicate(Matcher::vector_element_basic_type(n) == T_LONG); + match(Set dst (AndV src2 (XorV src1 (Replicate m1)))); + format %{ "vandn.vv $dst, $src2, $src1" %} + ins_encode %{ + __ vsetvli_helper(T_LONG, Matcher::vector_length(this)); + __ vandn_vv(as_VectorRegister($dst$$reg), + as_VectorRegister($src2$$reg), + as_VectorRegister($src1$$reg)); + %} + ins_pipe(pipe_slow); +%} + +instruct vand_notI_masked(vReg dst, vReg src2, vReg src1, immI_M1 m1, vRegMask_V0 v0) %{ + predicate(UseZvbb); + predicate(Matcher::vector_element_basic_type(n) == T_INT || + Matcher::vector_element_basic_type(n) == T_BYTE || + Matcher::vector_element_basic_type(n) == T_SHORT); + match(Set dst (AndV (Binary src2 (XorV (Binary src1 (Replicate m1)) v0)) v0)); + format %{ "vandn.vv $dst, $src2, $src1, $v0" %} + ins_encode %{ + BasicType bt = Matcher::vector_element_basic_type(this); + __ vsetvli_helper(bt, Matcher::vector_length(this)); + __ vandn_vv(as_VectorRegister($dst$$reg), + as_VectorRegister($src2$$reg), + as_VectorRegister($src1$$reg), + Assembler::v0_t); + %} + ins_pipe(pipe_slow); +%} + +instruct vand_notL_masked(vReg dst, vReg src2, vReg src1, immL_M1 m1, vRegMask_V0 v0) %{ + predicate(UseZvbb); + predicate(Matcher::vector_element_basic_type(n) == T_LONG); + match(Set dst (AndV (Binary src2 (XorV (Binary src1 (Replicate m1)) v0)) v0)); + format %{ "vandn.vv $dst, $src2, $src1, $v0" %} + ins_encode %{ + __ vsetvli_helper(T_LONG, Matcher::vector_length(this)); + __ vandn_vv(as_VectorRegister($dst$$reg), + as_VectorRegister($src2$$reg), + as_VectorRegister($src1$$reg), + Assembler::v0_t); + %} + ins_pipe(pipe_slow); +%} + // ------------------------------ Vector not ----------------------------------- // vector not diff --git a/test/hotspot/jtreg/compiler/vectorapi/AllBitsSetVectorMatchRuleTest.java b/test/hotspot/jtreg/compiler/vectorapi/AllBitsSetVectorMatchRuleTest.java index e490174e380de..52e5423c9e68a 100644 --- a/test/hotspot/jtreg/compiler/vectorapi/AllBitsSetVectorMatchRuleTest.java +++ b/test/hotspot/jtreg/compiler/vectorapi/AllBitsSetVectorMatchRuleTest.java @@ -42,8 +42,8 @@ * @key randomness * @library /test/lib / * @requires vm.compiler2.enabled - * @requires vm.cpu.features ~= ".*asimd.*" - * @summary AArch64: [vector] Make all bits set vector sharable for match rules + * @requires (os.simpleArch == "aarch64" & vm.cpu.features ~= ".*asimd.*") | (os.simpleArch == "riscv64" & vm.cpu.features ~= ".*zvbb.*") + * @summary [vector] Make all bits set vector sharable for match rules * @modules jdk.incubator.vector * * @run driver compiler.vectorapi.AllBitsSetVectorMatchRuleTest @@ -98,8 +98,9 @@ public static void testAllBitsSetVector() { @Test @Warmup(10000) - @IR(counts = { IRNode.VAND_NOT_L, " >= 1" }, applyIf = {"UseSVE", "0"}) - @IR(counts = { IRNode.VMASK_AND_NOT_L, " >= 1" }, applyIf = {"UseSVE", "> 0"}) + @IR(counts = { IRNode.VAND_NOT_L, " >= 1" }, applyIfPlatform = {"aarch64", "true"}, applyIf = {"UseSVE", "0"}) + @IR(counts = { IRNode.VMASK_AND_NOT_L, " >= 1" }, applyIfPlatform = {"aarch64", "true"}, applyIf = {"UseSVE", "> 0"}) + @IR(counts = { IRNode.VAND_NOT_L, " >= 1" }, applyIfPlatform = {"riscv64", "true"}) public static void testAllBitsSetMask() { VectorMask avm = VectorMask.fromArray(L_SPECIES, ma, 0); VectorMask bvm = VectorMask.fromArray(L_SPECIES, mb, 0); From a15d58dc68b9f4686567df5fefc9f38ef4d116cd Mon Sep 17 00:00:00 2001 From: Anjian-Wen Date: Tue, 1 Apr 2025 12:28:54 +0800 Subject: [PATCH 2/8] RISC-V: C2: Support Zvbb Vector And-Not instruction fix match rule for format --- src/hotspot/cpu/riscv/riscv_v.ad | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/hotspot/cpu/riscv/riscv_v.ad b/src/hotspot/cpu/riscv/riscv_v.ad index 5cf7fff6a4e19..38474785cf7bd 100644 --- a/src/hotspot/cpu/riscv/riscv_v.ad +++ b/src/hotspot/cpu/riscv/riscv_v.ad @@ -1122,7 +1122,7 @@ instruct vand_notI(vReg dst, vReg src2, vReg src1, immI_M1 m1) %{ Matcher::vector_element_basic_type(n) == T_BYTE || Matcher::vector_element_basic_type(n) == T_SHORT); match(Set dst (AndV src2 (XorV src1 (Replicate m1)))); - format %{ "vandn.vv $dst, $src2, $src1" %} + format %{ "vand_notI $dst, $src2, $src1" %} ins_encode %{ BasicType bt = Matcher::vector_element_basic_type(this); __ vsetvli_helper(bt, Matcher::vector_length(this)); @@ -1137,7 +1137,7 @@ instruct vand_notL(vReg dst, vReg src2, vReg src1, immL_M1 m1) %{ predicate(UseZvbb); predicate(Matcher::vector_element_basic_type(n) == T_LONG); match(Set dst (AndV src2 (XorV src1 (Replicate m1)))); - format %{ "vandn.vv $dst, $src2, $src1" %} + format %{ "vand_notL $dst, $src2, $src1" %} ins_encode %{ __ vsetvli_helper(T_LONG, Matcher::vector_length(this)); __ vandn_vv(as_VectorRegister($dst$$reg), @@ -1153,7 +1153,7 @@ instruct vand_notI_masked(vReg dst, vReg src2, vReg src1, immI_M1 m1, vRegMask_V Matcher::vector_element_basic_type(n) == T_BYTE || Matcher::vector_element_basic_type(n) == T_SHORT); match(Set dst (AndV (Binary src2 (XorV (Binary src1 (Replicate m1)) v0)) v0)); - format %{ "vandn.vv $dst, $src2, $src1, $v0" %} + format %{ "vand_notI_masked $dst, $src2, $src1, $v0" %} ins_encode %{ BasicType bt = Matcher::vector_element_basic_type(this); __ vsetvli_helper(bt, Matcher::vector_length(this)); @@ -1169,7 +1169,7 @@ instruct vand_notL_masked(vReg dst, vReg src2, vReg src1, immL_M1 m1, vRegMask_V predicate(UseZvbb); predicate(Matcher::vector_element_basic_type(n) == T_LONG); match(Set dst (AndV (Binary src2 (XorV (Binary src1 (Replicate m1)) v0)) v0)); - format %{ "vandn.vv $dst, $src2, $src1, $v0" %} + format %{ "vand_notL_masked $dst, $src2, $src1, $v0" %} ins_encode %{ __ vsetvli_helper(T_LONG, Matcher::vector_length(this)); __ vandn_vv(as_VectorRegister($dst$$reg), From 840618dd7addccfcf9afd532ad124db8f5e1011b Mon Sep 17 00:00:00 2001 From: Anjian-Wen Date: Tue, 8 Apr 2025 12:06:02 +0800 Subject: [PATCH 3/8] add vand_not_L test --- .../AllBitsSetVectorMatchRuleTest.java | 23 ++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/test/hotspot/jtreg/compiler/vectorapi/AllBitsSetVectorMatchRuleTest.java b/test/hotspot/jtreg/compiler/vectorapi/AllBitsSetVectorMatchRuleTest.java index 52e5423c9e68a..eb5987afc4b4a 100644 --- a/test/hotspot/jtreg/compiler/vectorapi/AllBitsSetVectorMatchRuleTest.java +++ b/test/hotspot/jtreg/compiler/vectorapi/AllBitsSetVectorMatchRuleTest.java @@ -63,6 +63,9 @@ public class AllBitsSetVectorMatchRuleTest { private static boolean[] mb; private static boolean[] mc; private static boolean[] mr; + private static long[] la; + private static long[] lb; + private static long[] lr; static { ia = new int[LENGTH]; @@ -72,6 +75,9 @@ public class AllBitsSetVectorMatchRuleTest { mb = new boolean[LENGTH]; mc = new boolean[LENGTH]; mr = new boolean[LENGTH]; + la = new long[LENGTH]; + lb = new long[LENGTH]; + lr = new long[LENGTH]; for (int i = 0; i < LENGTH; i++) { ia[i] = RD.nextInt(25); @@ -79,6 +85,8 @@ public class AllBitsSetVectorMatchRuleTest { ma[i] = RD.nextBoolean(); mb[i] = RD.nextBoolean(); mc[i] = RD.nextBoolean(); + la[i] = RD.nextLong(25); + lb[i] = RD.nextLong(25); } } @@ -100,7 +108,6 @@ public static void testAllBitsSetVector() { @Warmup(10000) @IR(counts = { IRNode.VAND_NOT_L, " >= 1" }, applyIfPlatform = {"aarch64", "true"}, applyIf = {"UseSVE", "0"}) @IR(counts = { IRNode.VMASK_AND_NOT_L, " >= 1" }, applyIfPlatform = {"aarch64", "true"}, applyIf = {"UseSVE", "> 0"}) - @IR(counts = { IRNode.VAND_NOT_L, " >= 1" }, applyIfPlatform = {"riscv64", "true"}) public static void testAllBitsSetMask() { VectorMask avm = VectorMask.fromArray(L_SPECIES, ma, 0); VectorMask bvm = VectorMask.fromArray(L_SPECIES, mb, 0); @@ -113,6 +120,20 @@ public static void testAllBitsSetMask() { } } + @Test + @Warmup(10000) + @IR(counts = { IRNode.VAND_NOT_L, " >= 1" }) + public static void testVectorVAndNotL() { + LongVector av = LongVector.fromArray(L_SPECIES, la, 0); + LongVector bv = LongVector.fromArray(L_SPECIES, lb, 0); + av.not().lanewise(VectorOperators.AND_NOT, bv).intoArray(lr, 0); + + // Verify results + for (int i = 0; i < L_SPECIES.length(); i++) { + Asserts.assertEquals((~la[i]) & (~lb[i]), lr[i]); + } + } + public static void main(String[] args) { TestFramework.runWithFlags("--add-modules=jdk.incubator.vector"); } From 225985a8dd3952ae82fb822511d3296bcb601683 Mon Sep 17 00:00:00 2001 From: Anjian-Wen Date: Thu, 10 Apr 2025 16:03:32 +0800 Subject: [PATCH 4/8] add vand_not_masked test --- .../compiler/lib/ir_framework/IRNode.java | 10 ++++++ .../AllBitsSetVectorMatchRuleTest.java | 34 +++++++++++++++++++ 2 files changed, 44 insertions(+) diff --git a/test/hotspot/jtreg/compiler/lib/ir_framework/IRNode.java b/test/hotspot/jtreg/compiler/lib/ir_framework/IRNode.java index 46bd48eefb2c9..b67a7945a8e9d 100644 --- a/test/hotspot/jtreg/compiler/lib/ir_framework/IRNode.java +++ b/test/hotspot/jtreg/compiler/lib/ir_framework/IRNode.java @@ -2076,6 +2076,16 @@ public class IRNode { machOnlyNameRegex(VAND_NOT_L, "vand_notL"); } + public static final String VAND_NOT_I_MASKED = PREFIX + "VAND_NOT_I_MASKED" + POSTFIX; + static { + machOnlyNameRegex(VAND_NOT_I_MASKED, "vand_notI_masked"); + } + + public static final String VAND_NOT_L_MASKED = PREFIX + "VAND_NOT_L_MASKED" + POSTFIX; + static { + machOnlyNameRegex(VAND_NOT_L_MASKED, "vand_notL_masked"); + } + public static final String VECTOR_BLEND_B = VECTOR_PREFIX + "VECTOR_BLEND_B" + POSTFIX; static { vectorNode(VECTOR_BLEND_B, "VectorBlend", TYPE_BYTE); diff --git a/test/hotspot/jtreg/compiler/vectorapi/AllBitsSetVectorMatchRuleTest.java b/test/hotspot/jtreg/compiler/vectorapi/AllBitsSetVectorMatchRuleTest.java index eb5987afc4b4a..8f35b0033eb1d 100644 --- a/test/hotspot/jtreg/compiler/vectorapi/AllBitsSetVectorMatchRuleTest.java +++ b/test/hotspot/jtreg/compiler/vectorapi/AllBitsSetVectorMatchRuleTest.java @@ -134,6 +134,40 @@ public static void testVectorVAndNotL() { } } + @Test + @Warmup(10000) + @IR(counts = { IRNode.VAND_NOT_I_MASKED, " >= 1" }) + public static void testVectorVAndNotIMasked() { + VectorMask avm = VectorMask.fromArray(I_SPECIES, ma, 0); + IntVector av = IntVector.fromArray(I_SPECIES, ia, 0); + IntVector bv = IntVector.fromArray(I_SPECIES, ib, 0); + av.not().lanewise(VectorOperators.AND_NOT, bv, avm).intoArray(ir, 0); + + // Verify results + for (int i = 0; i < I_SPECIES.length(); i++) { + if (ma[i] == true) { + Asserts.assertEquals((~ia[i]) & (~ib[i]), ir[i]); + } + } + } + + @Test + @Warmup(10000) + @IR(counts = { IRNode.VAND_NOT_L_MASKED, " >= 1" }) + public static void testVectorVAndNotLMasked() { + VectorMask avm = VectorMask.fromArray(L_SPECIES, ma, 0); + LongVector av = LongVector.fromArray(L_SPECIES, la, 0); + LongVector bv = LongVector.fromArray(L_SPECIES, lb, 0); + av.not().lanewise(VectorOperators.AND_NOT, bv, avm).intoArray(lr, 0); + + // Verify results + for (int i = 0; i < L_SPECIES.length(); i++) { + if (ma[i] == true) { + Asserts.assertEquals((~la[i]) & (~lb[i]), lr[i]); + } + } + } + public static void main(String[] args) { TestFramework.runWithFlags("--add-modules=jdk.incubator.vector"); } From edb166838bf07801e0acd7b9bc207962a50c044e Mon Sep 17 00:00:00 2001 From: Anjian-Wen Date: Fri, 11 Apr 2025 14:25:17 +0800 Subject: [PATCH 5/8] fix zvbb mask match rule --- src/hotspot/cpu/riscv/riscv_v.ad | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/src/hotspot/cpu/riscv/riscv_v.ad b/src/hotspot/cpu/riscv/riscv_v.ad index 0d097f6378d38..965b29258f038 100644 --- a/src/hotspot/cpu/riscv/riscv_v.ad +++ b/src/hotspot/cpu/riscv/riscv_v.ad @@ -1152,34 +1152,34 @@ instruct vand_notL(vReg dst, vReg src2, vReg src1, immL_M1 m1) %{ ins_pipe(pipe_slow); %} -instruct vand_notI_masked(vReg dst, vReg src2, vReg src1, immI_M1 m1, vRegMask_V0 v0) %{ +instruct vand_notI_masked(vReg dst_src1, vReg src2, immI_M1 m1, vRegMask_V0 v0) %{ predicate(UseZvbb); predicate(Matcher::vector_element_basic_type(n) == T_INT || Matcher::vector_element_basic_type(n) == T_BYTE || Matcher::vector_element_basic_type(n) == T_SHORT); - match(Set dst (AndV (Binary src2 (XorV (Binary src1 (Replicate m1)) v0)) v0)); - format %{ "vand_notI_masked $dst, $src2, $src1, $v0" %} + match(Set dst_src1 (AndV (Binary dst_src1 (XorV src2 (Replicate m1))) v0)); + format %{ "vand_notI_masked $dst_src1, $dst_src1, $src2, $v0" %} ins_encode %{ BasicType bt = Matcher::vector_element_basic_type(this); __ vsetvli_helper(bt, Matcher::vector_length(this)); - __ vandn_vv(as_VectorRegister($dst$$reg), + __ vandn_vv(as_VectorRegister($dst_src1$$reg), + as_VectorRegister($dst_src1$$reg), as_VectorRegister($src2$$reg), - as_VectorRegister($src1$$reg), Assembler::v0_t); %} ins_pipe(pipe_slow); %} -instruct vand_notL_masked(vReg dst, vReg src2, vReg src1, immL_M1 m1, vRegMask_V0 v0) %{ +instruct vand_notL_masked(vReg dst_src1, vReg src2, immL_M1 m1, vRegMask_V0 v0) %{ predicate(UseZvbb); predicate(Matcher::vector_element_basic_type(n) == T_LONG); - match(Set dst (AndV (Binary src2 (XorV (Binary src1 (Replicate m1)) v0)) v0)); - format %{ "vand_notL_masked $dst, $src2, $src1, $v0" %} + match(Set dst_src1 (AndV (Binary dst_src1 (XorV src2 (Replicate m1))) v0)); + format %{ "vand_notL_masked $dst_src1, $dst_src1, $src2, $v0" %} ins_encode %{ __ vsetvli_helper(T_LONG, Matcher::vector_length(this)); - __ vandn_vv(as_VectorRegister($dst$$reg), + __ vandn_vv(as_VectorRegister($dst_src1$$reg), + as_VectorRegister($dst_src1$$reg), as_VectorRegister($src2$$reg), - as_VectorRegister($src1$$reg), Assembler::v0_t); %} ins_pipe(pipe_slow); From fd4e05c25b6c78ab2a2616c17f748c84a857a681 Mon Sep 17 00:00:00 2001 From: Anjian-Wen Date: Sat, 12 Apr 2025 11:37:02 +0800 Subject: [PATCH 6/8] add aarch64 judgement for the test --- .../compiler/vectorapi/AllBitsSetVectorMatchRuleTest.java | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/test/hotspot/jtreg/compiler/vectorapi/AllBitsSetVectorMatchRuleTest.java b/test/hotspot/jtreg/compiler/vectorapi/AllBitsSetVectorMatchRuleTest.java index 8f35b0033eb1d..c8339e1a7376b 100644 --- a/test/hotspot/jtreg/compiler/vectorapi/AllBitsSetVectorMatchRuleTest.java +++ b/test/hotspot/jtreg/compiler/vectorapi/AllBitsSetVectorMatchRuleTest.java @@ -136,7 +136,8 @@ public static void testVectorVAndNotL() { @Test @Warmup(10000) - @IR(counts = { IRNode.VAND_NOT_I_MASKED, " >= 1" }) + @IR(counts = { IRNode.VAND_NOT_I_MASKED, " >= 1" }, applyIfPlatform = {"aarch64", "true"}, applyIf = {"UseSVE", "> 0"}) + @IR(counts = { IRNode.VAND_NOT_I_MASKED, " >= 1" }, applyIfPlatform = {"riscv64", "true"}) public static void testVectorVAndNotIMasked() { VectorMask avm = VectorMask.fromArray(I_SPECIES, ma, 0); IntVector av = IntVector.fromArray(I_SPECIES, ia, 0); @@ -153,7 +154,8 @@ public static void testVectorVAndNotIMasked() { @Test @Warmup(10000) - @IR(counts = { IRNode.VAND_NOT_L_MASKED, " >= 1" }) + @IR(counts = { IRNode.VAND_NOT_I_MASKED, " >= 1" }, applyIfPlatform = {"aarch64", "true"}, applyIf = {"UseSVE", "> 0"}) + @IR(counts = { IRNode.VAND_NOT_I_MASKED, " >= 1" }, applyIfPlatform = {"riscv64", "true"}) public static void testVectorVAndNotLMasked() { VectorMask avm = VectorMask.fromArray(L_SPECIES, ma, 0); LongVector av = LongVector.fromArray(L_SPECIES, la, 0); From dd649507cef3f10c8cc0fbe067d3a74b6847b209 Mon Sep 17 00:00:00 2001 From: Anjian-Wen Date: Sat, 12 Apr 2025 15:55:45 +0800 Subject: [PATCH 7/8] fix test bug --- .../compiler/vectorapi/AllBitsSetVectorMatchRuleTest.java | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/test/hotspot/jtreg/compiler/vectorapi/AllBitsSetVectorMatchRuleTest.java b/test/hotspot/jtreg/compiler/vectorapi/AllBitsSetVectorMatchRuleTest.java index c8339e1a7376b..12a1b46c8a5a5 100644 --- a/test/hotspot/jtreg/compiler/vectorapi/AllBitsSetVectorMatchRuleTest.java +++ b/test/hotspot/jtreg/compiler/vectorapi/AllBitsSetVectorMatchRuleTest.java @@ -154,8 +154,8 @@ public static void testVectorVAndNotIMasked() { @Test @Warmup(10000) - @IR(counts = { IRNode.VAND_NOT_I_MASKED, " >= 1" }, applyIfPlatform = {"aarch64", "true"}, applyIf = {"UseSVE", "> 0"}) - @IR(counts = { IRNode.VAND_NOT_I_MASKED, " >= 1" }, applyIfPlatform = {"riscv64", "true"}) + @IR(counts = { IRNode.VAND_NOT_L_MASKED, " >= 1" }, applyIfPlatform = {"aarch64", "true"}, applyIf = {"UseSVE", "> 0"}) + @IR(counts = { IRNode.VAND_NOT_L_MASKED, " >= 1" }, applyIfPlatform = {"riscv64", "true"}) public static void testVectorVAndNotLMasked() { VectorMask avm = VectorMask.fromArray(L_SPECIES, ma, 0); LongVector av = LongVector.fromArray(L_SPECIES, la, 0); From 717bc300fb31c51070efb48216b198522395ac59 Mon Sep 17 00:00:00 2001 From: Anjian-Wen Date: Mon, 14 Apr 2025 15:47:48 +0800 Subject: [PATCH 8/8] modify code and test format --- src/hotspot/cpu/riscv/riscv_v.ad | 20 ++++---- .../AllBitsSetVectorMatchRuleTest.java | 50 +++++++++---------- 2 files changed, 35 insertions(+), 35 deletions(-) diff --git a/src/hotspot/cpu/riscv/riscv_v.ad b/src/hotspot/cpu/riscv/riscv_v.ad index 965b29258f038..9b135215b3d0f 100644 --- a/src/hotspot/cpu/riscv/riscv_v.ad +++ b/src/hotspot/cpu/riscv/riscv_v.ad @@ -1121,33 +1121,33 @@ instruct vxor_regL_masked(vReg dst_src, iRegL src, vRegMask_V0 v0) %{ // vector and not -instruct vand_notI(vReg dst, vReg src2, vReg src1, immI_M1 m1) %{ +instruct vand_notI(vReg dst, vReg src1, vReg src2, immI_M1 m1) %{ predicate(UseZvbb); predicate(Matcher::vector_element_basic_type(n) == T_INT || Matcher::vector_element_basic_type(n) == T_BYTE || Matcher::vector_element_basic_type(n) == T_SHORT); - match(Set dst (AndV src2 (XorV src1 (Replicate m1)))); - format %{ "vand_notI $dst, $src2, $src1" %} + match(Set dst (AndV src1 (XorV src2 (Replicate m1)))); + format %{ "vand_notI $dst, $src1, $src2" %} ins_encode %{ BasicType bt = Matcher::vector_element_basic_type(this); __ vsetvli_helper(bt, Matcher::vector_length(this)); __ vandn_vv(as_VectorRegister($dst$$reg), - as_VectorRegister($src2$$reg), - as_VectorRegister($src1$$reg)); + as_VectorRegister($src1$$reg), + as_VectorRegister($src2$$reg)); %} ins_pipe(pipe_slow); %} -instruct vand_notL(vReg dst, vReg src2, vReg src1, immL_M1 m1) %{ +instruct vand_notL(vReg dst, vReg src1, vReg src2, immL_M1 m1) %{ predicate(UseZvbb); predicate(Matcher::vector_element_basic_type(n) == T_LONG); - match(Set dst (AndV src2 (XorV src1 (Replicate m1)))); - format %{ "vand_notL $dst, $src2, $src1" %} + match(Set dst (AndV src1 (XorV src2 (Replicate m1)))); + format %{ "vand_notL $dst, $src1, $src2" %} ins_encode %{ __ vsetvli_helper(T_LONG, Matcher::vector_length(this)); __ vandn_vv(as_VectorRegister($dst$$reg), - as_VectorRegister($src2$$reg), - as_VectorRegister($src1$$reg)); + as_VectorRegister($src1$$reg), + as_VectorRegister($src2$$reg)); %} ins_pipe(pipe_slow); %} diff --git a/test/hotspot/jtreg/compiler/vectorapi/AllBitsSetVectorMatchRuleTest.java b/test/hotspot/jtreg/compiler/vectorapi/AllBitsSetVectorMatchRuleTest.java index 12a1b46c8a5a5..f33dd24e726a8 100644 --- a/test/hotspot/jtreg/compiler/vectorapi/AllBitsSetVectorMatchRuleTest.java +++ b/test/hotspot/jtreg/compiler/vectorapi/AllBitsSetVectorMatchRuleTest.java @@ -43,7 +43,7 @@ * @library /test/lib / * @requires vm.compiler2.enabled * @requires (os.simpleArch == "aarch64" & vm.cpu.features ~= ".*asimd.*") | (os.simpleArch == "riscv64" & vm.cpu.features ~= ".*zvbb.*") - * @summary [vector] Make all bits set vector sharable for match rules + * @summary AArch64: [vector] Make all bits set vector sharable for match rules * @modules jdk.incubator.vector * * @run driver compiler.vectorapi.AllBitsSetVectorMatchRuleTest @@ -59,34 +59,34 @@ public class AllBitsSetVectorMatchRuleTest { private static int[] ia; private static int[] ib; private static int[] ir; + private static long[] la; + private static long[] lb; + private static long[] lr; private static boolean[] ma; private static boolean[] mb; private static boolean[] mc; private static boolean[] mr; - private static long[] la; - private static long[] lb; - private static long[] lr; static { ia = new int[LENGTH]; ib = new int[LENGTH]; ir = new int[LENGTH]; + la = new long[LENGTH]; + lb = new long[LENGTH]; + lr = new long[LENGTH]; ma = new boolean[LENGTH]; mb = new boolean[LENGTH]; mc = new boolean[LENGTH]; mr = new boolean[LENGTH]; - la = new long[LENGTH]; - lb = new long[LENGTH]; - lr = new long[LENGTH]; for (int i = 0; i < LENGTH; i++) { ia[i] = RD.nextInt(25); ib[i] = RD.nextInt(25); + la[i] = RD.nextLong(25); + lb[i] = RD.nextLong(25); ma[i] = RD.nextBoolean(); mb[i] = RD.nextBoolean(); mc[i] = RD.nextBoolean(); - la[i] = RD.nextLong(25); - lb[i] = RD.nextLong(25); } } @@ -104,22 +104,6 @@ public static void testAllBitsSetVector() { } } - @Test - @Warmup(10000) - @IR(counts = { IRNode.VAND_NOT_L, " >= 1" }, applyIfPlatform = {"aarch64", "true"}, applyIf = {"UseSVE", "0"}) - @IR(counts = { IRNode.VMASK_AND_NOT_L, " >= 1" }, applyIfPlatform = {"aarch64", "true"}, applyIf = {"UseSVE", "> 0"}) - public static void testAllBitsSetMask() { - VectorMask avm = VectorMask.fromArray(L_SPECIES, ma, 0); - VectorMask bvm = VectorMask.fromArray(L_SPECIES, mb, 0); - VectorMask cvm = VectorMask.fromArray(L_SPECIES, mc, 0); - avm.andNot(bvm).andNot(cvm).intoArray(mr, 0); - - // Verify results - for (int i = 0; i < L_SPECIES.length(); i++) { - Asserts.assertEquals((ma[i] & (!mb[i])) & (!mc[i]), mr[i]); - } - } - @Test @Warmup(10000) @IR(counts = { IRNode.VAND_NOT_L, " >= 1" }) @@ -170,6 +154,22 @@ public static void testVectorVAndNotLMasked() { } } + @Test + @Warmup(10000) + @IR(counts = { IRNode.VAND_NOT_L, " >= 1" }, applyIfPlatform = {"aarch64", "true"}, applyIf = {"UseSVE", "0"}) + @IR(counts = { IRNode.VMASK_AND_NOT_L, " >= 1" }, applyIfPlatform = {"aarch64", "true"}, applyIf = {"UseSVE", "> 0"}) + public static void testAllBitsSetMask() { + VectorMask avm = VectorMask.fromArray(L_SPECIES, ma, 0); + VectorMask bvm = VectorMask.fromArray(L_SPECIES, mb, 0); + VectorMask cvm = VectorMask.fromArray(L_SPECIES, mc, 0); + avm.andNot(bvm).andNot(cvm).intoArray(mr, 0); + + // Verify results + for (int i = 0; i < L_SPECIES.length(); i++) { + Asserts.assertEquals((ma[i] & (!mb[i])) & (!mc[i]), mr[i]); + } + } + public static void main(String[] args) { TestFramework.runWithFlags("--add-modules=jdk.incubator.vector"); }