Merge commit 'a3237779e53281929fc874c114d5b1e4268f1c84'

wallento · wallento · commit 857149c4663d · 2016-02-02T08:29:10.000+01:00
diff --git a/glip/configure.ac b/glip/configure.ac
@@ -108,9 +108,9 @@ AS_IF([test "x$enable_cypressfx2" = "xyes"], [
 
 
 AC_ARG_ENABLE([tcp],
-    AS_HELP_STRING([--enable-tcp], [enable TCP backend @<:@default=disabled@:>@]),
+    AS_HELP_STRING([--enable-tcp], [enable TCP backend @<:@default=enabled@:>@]),
     [],
-    [enable_tcp=no])
+    [enable_tcp=yes])
 AM_CONDITIONAL([BACKEND_TCP], [test "x$enable_tcp" = "xyes"])
 
 GLIP_CONFIG_BACKEND(tcp, TCP)
diff --git a/glip/src/backend_uart/logic/demo/nexys4ddr/nexys4ddr.v b/glip/src/backend_uart/logic/demo/nexys4ddr/nexys4ddr.v
@@ -55,18 +55,20 @@ module nexys4ddr
    output reg   redled
    );
 
+   parameter WIDTH = 8;
+
    localparam FREQ = 100000000;
    localparam BAUD = 3000000;
 
    wire         rst;
    assign rst = ~rstn;
 
-   wire [7:0]   in_data;
-   wire         in_valid;
-   reg          in_ready;
-   reg [7:0]    out_data;
-   reg          out_valid;
-   wire         out_ready;
+   wire [WIDTH-1:0] in_data;
+   wire             in_valid;
+   reg              in_ready;
+   reg [WIDTH-1:0]  out_data;
+   reg              out_valid;
+   wire             out_ready;
 
    always @(*) begin
       casez(switch[1:0])
@@ -108,7 +110,8 @@ module nexys4ddr
 
    glip_uart_toplevel
      #(.FREQ(FREQ),
-       .BAUD(BAUD))
+       .BAUD(BAUD),
+       .WIDTH(WIDTH))
    u_uart(.clk_io         (clk),
           .clk_logic      (clk),
           .rst            (rst),
@@ -128,9 +131,9 @@ module nexys4ddr
 
    wire [8*7-1:0] digits;
    wire           overflow;
-   
+
    glip_measure_sevensegment
-     #(.FREQ(FREQ), .DIGITS(8), .OFFSET(0), .STEP(4'd1))
+     #(.FREQ(FREQ), .DIGITS(8), .OFFSET(0), .STEP(WIDTH/8))
    u_measure(.clk      (clk),
              .rst      (logic_rst),
              .trigger  ((in_valid & in_ready) | (out_valid & out_ready)),
diff --git a/glip/src/backend_uart/logic/demo/nexys4ddr/vivado.tcl b/glip/src/backend_uart/logic/demo/nexys4ddr/vivado.tcl
@@ -103,6 +103,8 @@ set files [list \
  "[file normalize "$origin_dir/../../../../common/logic/sevensegment/sevensegment.v"]"\
  "[file normalize "$origin_dir/../../../../common/logic/measure/glip_measure_sevensegment.v"]"\
  "[file normalize "$origin_dir/../../../../common/logic/measure/glip_measure.v"]"\
+ "[file normalize "$origin_dir/../../../../common/logic/scaler/verilog/glip_downscale.v"]"\
+ "[file normalize "$origin_dir/../../../../common/logic/scaler/verilog/glip_upscale.v"]"\
 ]
 add_files -norecurse -fileset $obj $files
 
@@ -160,6 +162,18 @@ if {[string equal [get_runs -quiet synth_1] ""]} {
 }
 set obj [get_runs synth_1]
 set_property "part" "xc7a100tcsg324-1" $obj
+set_property -name {steps.synth_design.args.more options} -value {-generic WIDTH=8} -objects $obj
+
+# Create 'synth_2' run (if not found)
+if {[string equal [get_runs -quiet synth_2] ""]} {
+  create_run -name synth_2 -part xc7a100tcsg324-1 -flow {Vivado Synthesis 2015} -strategy "Vivado Synthesis Defaults" -constrset constrs_1
+} else {
+  set_property strategy "Vivado Synthesis Defaults" [get_runs synth_2]
+  set_property flow "Vivado Synthesis 2015" [get_runs synth_2]
+}
+set obj [get_runs synth_2]
+set_property "part" "xc7a100tcsg324-1" $obj
+set_property -name {steps.synth_design.args.more options} -value {-generic WIDTH=16} -objects $obj
 
 # set the current synth run
 current_run -synthesis [get_runs synth_1]
@@ -176,6 +190,18 @@ set_property "part" "xc7a100tcsg324-1" $obj
 set_property "steps.write_bitstream.args.readback_file" "0" $obj
 set_property "steps.write_bitstream.args.verbose" "0" $obj
 
+# Create 'impl_2' run (if not found)
+if {[string equal [get_runs -quiet impl_2] ""]} {
+  create_run -name impl_2 -part xc7a100tcsg324-1 -flow {Vivado Implementation 2015} -strategy "Vivado Implementation Defaults" -constrset constrs_1 -parent_run synth_2
+} else {
+  set_property strategy "Vivado Implementation Defaults" [get_runs impl_2]
+  set_property flow "Vivado Implementation 2015" [get_runs impl_2]
+}
+set obj [get_runs impl_2]
+set_property "part" "xc7a100tcsg324-1" $obj
+set_property "steps.write_bitstream.args.readback_file" "0" $obj
+set_property "steps.write_bitstream.args.verbose" "0" $obj
+
 # set the current impl run
 current_run -implementation [get_runs impl_1]
 
diff --git a/glip/src/backend_uart/logic/verilog/glip_uart_toplevel.v b/glip/src/backend_uart/logic/verilog/glip_uart_toplevel.v
@@ -41,35 +41,43 @@
 module glip_uart_toplevel
   #(parameter FREQ = 32'hx,
     parameter BAUD = 115200,
+    parameter WIDTH = 8,
     parameter XILINX_TARGET_DEVICE = "7SERIES")
    (
     // Clock & Reset
-    input        clk_io,
-    input        clk_logic,
-    input        rst,
+    input              clk_io,
+    input              clk_logic,
+    input              rst,
 
     // GLIP FIFO Interface
-    input [7:0]  fifo_out_data,
-    input        fifo_out_valid,
-    output       fifo_out_ready,
-    output [7:0] fifo_in_data,
-    output       fifo_in_valid,
-    input        fifo_in_ready,
+    input [WIDTH-1:0]  fifo_out_data,
+    input              fifo_out_valid,
+    output             fifo_out_ready,
+    output [WIDTH-1:0] fifo_in_data,
+    output             fifo_in_valid,
+    input              fifo_in_ready,
 
     // GLIP Control Interface
-    output       logic_rst,
-    output       com_rst,
+    output             logic_rst,
+    output             com_rst,
     
     // UART Interface
-    input        uart_rx,
-    output       uart_tx,
-    input        uart_cts,
-    output       uart_rts,
+    input              uart_rx,
+    output             uart_tx,
+    input              uart_cts,
+    output             uart_rts,
     
     // Error signal if failure on the line
-    output reg   error
+    output reg         error
     );
 
+   wire [7:0]     fifo_out_data_scale;
+   wire           fifo_out_valid_scale;
+   wire           fifo_out_ready_scale;
+   wire [7:0]     fifo_in_data_scale;
+   wire           fifo_in_valid_scale;
+   wire           fifo_in_ready_scale;
+
    wire [7:0]    ingress_in_data;
    wire          ingress_in_valid;
    wire          ingress_in_ready;
@@ -99,9 +107,9 @@ module glip_uart_toplevel
    assign ingress_out_ready = ~in_buffer_almost_full;
    assign ingress_buffer_valid = ~in_buffer_empty;
    assign ingress_buffer_ready = ~in_fifo_full;
-   assign fifo_in_valid = ~in_fifo_empty;
+   assign fifo_in_valid_scale = ~in_fifo_empty;
    assign egress_in_valid = ~out_fifo_empty;
-   assign fifo_out_ready = ~out_fifo_full;
+   assign fifo_out_ready_scale = ~out_fifo_full;
 
    assign uart_rts = 0;
 
@@ -116,6 +124,40 @@ module glip_uart_toplevel
       end
    end
 
+   generate
+      if (WIDTH == 8) begin
+         assign fifo_out_data_scale = fifo_out_data;
+         assign fifo_out_valid_scale = fifo_out_valid;
+         assign fifo_out_ready = fifo_out_ready_scale;
+         assign fifo_in_data = fifo_in_data_scale;
+         assign fifo_in_valid = fifo_in_valid_scale;
+         assign fifo_in_ready_scale = fifo_in_ready;
+      end else if (WIDTH == 16) begin
+         glip_upscale
+           #(.IN_SIZE(8))
+         u_upscale(.clk       (clk_io),
+                   .rst       (com_rst),
+                   .in_data   (fifo_in_data_scale),
+                   .in_valid  (fifo_in_valid_scale),
+                   .in_ready  (fifo_in_ready_scale),
+                   .out_data  (fifo_in_data),
+                   .out_valid (fifo_in_valid),
+                   .out_ready (fifo_in_ready));
+
+         glip_downscale
+           #(.OUT_SIZE(8))
+         u_downscale(.clk       (clk_io),
+                     .rst       (com_rst),
+                     .in_data   (fifo_out_data),
+                     .in_valid  (fifo_out_valid),
+                     .in_ready  (fifo_out_ready),
+                     .out_data  (fifo_out_data_scale),
+                     .out_valid (fifo_out_valid_scale),
+                     .out_ready (fifo_out_ready_scale));
+
+      end
+   endgenerate
+
    /* glip_uart_control AUTO_TEMPLATE(
     .clk   (clk_io),
     .error (control_error),
@@ -224,7 +266,7 @@ module glip_uart_toplevel
    in_fifo
      (.ALMOSTEMPTY (),
       .ALMOSTFULL  (),
-      .DO          (fifo_in_data[7:0]),
+      .DO          (fifo_in_data_scale[7:0]),
       .EMPTY       (in_fifo_empty),
       .FULL        (in_fifo_full),
       .RDCOUNT     (),
@@ -233,7 +275,7 @@ module glip_uart_toplevel
       .WRERR       (),
       .DI          (ingress_buffer_data[7:0]),
       .RDCLK       (clk_logic),
-      .RDEN        (fifo_in_ready),
+      .RDEN        (fifo_in_ready_scale),
       .RST         (com_rst),
       .WRCLK       (clk_io),
       .WREN        (ingress_buffer_valid)
@@ -258,12 +300,12 @@ module glip_uart_toplevel
       .RDERR       (),
       .WRCOUNT     (),
       .WRERR       (),
-      .DI          (fifo_out_data[7:0]),
+      .DI          (fifo_out_data_scale[7:0]),
       .RDCLK       (clk_io),
       .RDEN        (egress_in_ready),
       .RST         (com_rst),
       .WRCLK       (clk_logic),
-      .WREN        (fifo_out_valid)
+      .WREN        (fifo_out_valid_scale)
       );
    
 endmodule // glip_uart_toplevel
diff --git a/glip/src/backend_uart/sw/backend_uart.c b/glip/src/backend_uart/sw/backend_uart.c
@@ -394,7 +394,7 @@ int gb_uart_open(struct glip_ctx *ctx, unsigned int num_channels)
         do {
             uint8_t buffer[128];
             rv = read(bctx->fd, buffer, 128);
-        } while ((rv > 0) || ((rv == -1) && (errno == EAGAIN)));
+        } while (rv > 0);
 
         /* - De-assert reset */
         rv = reset_com(bctx->fd, 0);
diff --git a/glip/src/common/logic/scaler/verilog/glip_downscale.v b/glip/src/common/logic/scaler/verilog/glip_downscale.v
@@ -0,0 +1,73 @@
+/* Copyright (c) 2015-2016 by the author(s)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * =============================================================================
+ *
+ * Sownscale a FIFO interface
+ *
+ * parameter:
+ *  - OUT_SIZE: Output width in bits. The input will have the double width.
+ * 
+ * Author(s):
+ *   Stefan Wallentowitz <stefan@wallentowitz.de>
+ */
+
+module glip_downscale
+  #(parameter OUT_SIZE=16)
+   (input clk, rst,
+
+    input [OUT_SIZE*2-1:0] in_data,
+    input                  in_valid,
+    output                 in_ready,
+
+    output [OUT_SIZE-1:0]  out_data,
+    output                 out_valid,
+    input                  out_ready);
+
+   /* 0 when passthrough and 1 when emitting upper part */
+   reg                     scale;
+   /* Store upper part for emitting in second transfer */
+   reg [OUT_SIZE-1:0]      upper;
+
+   /* Ready during passthrough */
+   assign in_ready = !scale & out_ready;
+   /* Valid during passthrough or second transfer */
+   assign out_valid = scale ? 1 : in_valid;
+   /* Passthrough in first and stored upper in second transfer */
+   assign out_data = !scale ? in_data[OUT_SIZE-1:0] : upper; 
+   
+   always @(posedge clk) begin
+      if (rst) begin
+         scale <= 0;
+      end else if (scale & out_valid & out_ready) begin
+         scale <= 0;
+      end else if (!scale & in_valid & in_ready) begin
+         scale <= 1;
+      end
+   end
+
+   always @(posedge clk) begin
+      if (in_valid & in_ready) begin
+         upper <= in_data[OUT_SIZE*2-1:OUT_SIZE];
+      end
+   end
+   
+endmodule // glip_downscale
+
diff --git a/glip/src/common/logic/scaler/verilog/glip_upscale.v b/glip/src/common/logic/scaler/verilog/glip_upscale.v
