wip: Add TPIU decoder and bypass for SWO.

Author: zyp

orbtrace/trace/__init__.py

@@ -254,6 +254,7 @@ def __init__(self, platform):
         swo_manchester = Signal()
         swo_nrz = Signal()
         swo_tpiu = Signal()
+        swo_itm = Signal()
 
         self.comb += Case(self.input_format, {
             0x01: [
@@ -271,6 +272,7 @@ def __init__(self, platform):
             0x10: [
                 swo_active.eq(1),
                 swo_manchester.eq(1),
+                swo_itm.eq(1),
             ],
             0x11: [
                 swo_active.eq(1),
@@ -280,6 +282,7 @@ def __init__(self, platform):
             0x12: [
                 swo_active.eq(1),
                 swo_nrz.eq(1),
+                swo_itm.eq(1),
             ],
             0x13: [
                 swo_active.eq(1),
@@ -307,20 +310,11 @@ def __init__(self, platform):
         trace_pipeline = [
             phy := ClockDomainsRenamer('trace')(TracePHY(trace_pads)),
             ClockDomainsRenamer({'write': 'trace', 'read': 'sys'})(AsyncFIFO([('data', 128)], 4)),
-            ByteSwap(16),
-            #injector := Injector(),
-            #pv := PipeValid([('data', 128)]),
-            #Converter(128, 8),
-            tpiu.TPIUDemux(),
-            cobs.ChecksumAppender(),
-            cobs.COBSEncoder(),
-            cobs.DelimiterAppender(),
-            cobs.SuperFramer(7500000, 65536),
         ]
 
         #pv.comb += pv.source.last.eq(1)
 
-        trace_stream = Endpoint([('data', 8)])
+        trace_stream = Endpoint([('data', 128)])
 
         self.submodules += [*trace_pipeline, Pipeline(*trace_pipeline, trace_stream)]
 
@@ -370,7 +364,7 @@ def __init__(self, platform):
         swo_stream_backend_source = Endpoint([('data', 8)])
         swo_pipeline_backend = [
             ClockDomainsRenamer({'write': 'swo', 'read': 'sys'})(AsyncFIFO([('data', 8)], 4)),
-            StreamFlush(7500000),
+            #StreamFlush(7500000),
         ]
         self.submodules += [*swo_pipeline_backend, Pipeline(swo_stream_backend_sink, *swo_pipeline_backend, swo_stream_backend_source)]
 
@@ -393,18 +387,30 @@ def __init__(self, platform):
         self.submodules.swo_overrun_indicator = Indicator(swo_monitor.lost, 7500000)
         self.submodules.swo_data_indicator = Indicator(swo_monitor.total, 7500000)
 
-        # Output mux and FIFO
-        fifo = SyncFIFO([('data', 8)], 8192, buffered = True)
+        # Orbtag pipeline
+        orbtag_pipeline_sink = Endpoint([('data', 128)])
+        orbtag_pipeline = [
+            ByteSwap(16),
+            tpiu_demux := tpiu.TPIUDemux(),
+            cobs.ChecksumAppender(),
+            cobs.COBSEncoder(),
+            cobs.DelimiterAppender(),
+            cobs.SuperFramer(7500000, 65536),
+            SyncFIFO([('data', 8)], 8192, buffered = True),
+        ]
+        self.submodules += [*orbtag_pipeline, Pipeline(orbtag_pipeline_sink, *orbtag_pipeline, source)]
+
+        self.submodules.swo_tpiu_sync = swo_tpiu_sync = tpiu.TPIUSync()
 
+        # Output mux
         self.comb += [
             If(trace_active,
-                trace_stream.connect(fifo.sink),
+                trace_stream.connect(orbtag_pipeline_sink),
                 self.led_overrun.eq(self.overrun_indicator.out),
                 self.led_data.eq(self.data_indicator.out),
                 self.led_clk.eq(self.clk_indicator.out),
             ),
             If(swo_active,
-                swo_stream_backend_source.connect(fifo.sink),
                 self.led_overrun.eq(self.swo_overrun_indicator.out),
                 self.led_data.eq(self.swo_data_indicator.out),
             ),
@@ -416,10 +422,15 @@ def __init__(self, platform):
                 swo_stream_frontend_source.connect(swo_stream_nrz_sink),
                 swo_stream_nrz_source.connect(swo_stream_backend_sink),
             ),
-            fifo.source.connect(source),
+            If(swo_tpiu,
+                swo_stream_backend_source.connect(swo_tpiu_sync.sink),
+                swo_tpiu_sync.source.connect(orbtag_pipeline_sink),
+            ),
+            If(swo_itm,
+                swo_stream_backend_source.connect(tpiu_demux.bypass_sink),
+                tpiu_demux.bypass.eq(1),
+            ),
         ]
 
-        self.submodules += fifo
-
         # Add verilog sources.
         platform.add_source('verilog/traceIF.v') # TODO: make sure the path is correct

orbtrace/trace/tpiu.py

@@ -158,8 +158,11 @@ def __init__(self):
 class TPIUDemux(Module):
     def __init__(self):
         self.sink = sink = Endpoint([('data', 128)])
+        self.bypass_sink = bypass_sink = Endpoint([('data', 8)])
         self.source = source = Endpoint([('data', 8)])
 
+        self.bypass = Signal()
+
         self.submodules.rearrange = Rearrange()
         self.submodules.converter = Converter(135, 9)
         self.submodules.track_stream = TrackStream()
@@ -168,17 +171,59 @@ def __init__(self):
         self.submodules.packetizer = Packetizer()
         self.submodules.last_from_first = LastFromFirst()
 
-        self.submodules.pipeline = Pipeline(
+        self.submodules += Pipeline(
             sink,
             self.rearrange,
             self.converter,
             self.track_stream,
             #self.demux,
             self.strip_channel_zero,
+        )
+
+        self.submodules += Pipeline(
             self.packetizer,
             self.last_from_first,
             source,
         )
 
+        self.comb += If(self.bypass,
+            bypass_sink.ready.eq(self.packetizer.sink.ready),
+            self.packetizer.sink.valid.eq(bypass_sink.valid),
+            self.packetizer.sink.data.eq(bypass_sink.data),
+            self.packetizer.sink.channel.eq(1),
+        ).Else(
+            self.strip_channel_zero.source.connect(self.packetizer.sink),
+        )
+
         #self.comb += self.demux.source_etm.connect(source)
-        #self.comb += self.demux.source_itm.ready.eq(1)
+        #self.comb += self.demux.source_itm.ready.eq(1)
+
+class TPIUSync(Module):
+    def __init__(self):
+        self.sink = sink = Endpoint([('data', 8)])
+        self.source = source = Endpoint([('data', 128)])
+
+        buf = Signal(129, reset = 1)
+
+        self.comb += [
+            source.valid.eq(buf[128]),
+            source.data.eq(buf),
+            sink.ready.eq(~source.valid),
+        ]
+
+        self.sync += If(source.valid & source.ready,
+            buf.eq(1),
+        )
+
+        self.sync += If(sink.valid & sink.ready,
+            If(Cat(sink.data, buf)[:32] == 0xffffff7f,
+                # Full sync, reset buffer.
+                buf.eq(1),
+            ).Elif(Cat(sink.data, buf)[:16] == 0xff7f,
+                # Half sync, drop previous byte from buffer.
+                buf.eq(buf[8:]),
+            ).Else(
+                # Regular byte, add to buffer.
+                buf.eq(Cat(sink.data, buf)),
+            )
+        )