Updated mem_writer scripts and example output

Author: pConst

scripts/mem_writer.sh

@@ -0,0 +1,56 @@
+#!/bin/bash
+
+#  mem_writer.sh
+#  published as part of https://github.com/pConst/basic_verilog
+#  Konstantin Pavlov, [email protected]
+#
+#  generates a bunch of .mem files to test block memory initialization
+#
+#  see also for "./scripts/mem_writer_adv.py" for advanced
+#    functional memory file generator
+
+
+# linear file contents =========================================================
+# looping file len
+for l in 16 32 64 128 256 512 1024 2048 4096 65536
+do
+  # looping element width, in bits
+  for w in 8 16 32
+  do
+    # calculating padded hex string width
+    ws=$((w/8))
+    # skipping erroneous widths
+    if (( l <= 16 ** ${ws} )); then
+      rm -rf ${l}x${w}bit_linear.mem
+      # generating strings to the file
+      for (( s=0; s <= ${l}-1; s++ ))
+      do
+        printf "%0${ws}X\n" ${s} >> ${l}x${w}bit_linear.mem
+      done
+    fi
+  done
+done
+
+
+# ramdom file contents =========================================================
+# looping file len
+for l in 16 32 64 128 256 512 1024 2048 4096 65536
+do
+  # looping element width, in bits
+  for w in 8 16 32
+  do
+    # calculating padded hex string width
+    ws=$((w/8))
+    # skipping erroneous widths
+    if (( l <= 16 ** ${ws} )); then
+      rm -rf ${l}x${w}bit_random.mem
+      # generating strings to the file
+      for (( s=0; s <= ${l}-1; s++ ))
+      do
+        printf "%0${ws}X\n" $(($RANDOM % (2 ** ${w}) )) >> ${l}x${w}bit_random.mem
+      done
+    fi
+  done
+done
+
+printf "DONE\n"

scripts/ascii_hex_writer.py scripts/mem_writer_adv.pyscripts/ascii_hex_writer.py renamed to scripts/mem_writer_adv.py

@@ -1,37 +1,38 @@
-#!/usr/bin/env python
-# coding: utf-8
-
-# author: Konstantin Pavlov
-# email:  [email protected]
-
-# boilerplate script to generate ASCII hex files to initialize RAMs in Verilog
-
-import math
-import os
-
-# settings =====================================================================
-N = 128
-tablename = "sin"
-filename = tablename + ".hex"
-
-# main =========================================================================
-if os.path.exists(filename):
-  os.remove(filename)
-  print("Old file version removed")
-
-f = open(filename, "x")
-f.write("// ascii hex file for " + tablename + " function\n\n")
-
-for i in range(0, N):
-    # computing and scaling
-    rad = math.pi/4/N*i
-    val = math.floor(math.sin(rad) * 256)
-    # formatting to HEX string of specified length
-    val_str = format(val, "#06x")
-    # additional prefix
-    prefix_str = format(i, "#04x")
-    # cutting '0x' prefix away
-    f.write(prefix_str[2:] + "_" + val_str[2:] + "\n")
-
-f.close()
-
+#!/usr/bin/env python
+# coding: utf-8
+
+# author: Konstantin Pavlov
+# published as part of https://github.com/pConst/basic_verilog
+# email:  [email protected]
+
+# boilerplate script to generate ASCII hex files to initialize RAMs in Verilog
+
+import math
+import os
+
+# settings =====================================================================
+N = 1024
+tablename = "1024sin"
+filename = tablename + ".mem"
+
+# main =========================================================================
+if os.path.exists(filename):
+  os.remove(filename)
+  print("Old file version removed")
+
+f = open(filename, "x")
+#f.write("// ascii hex file for " + tablename + " function\n\n")
+
+for i in range(0, N):
+    # computing and scaling
+    rad = math.pi/4/N*i
+    val = round(math.sin(rad) * 65535)
+    # formatting to HEX string of specified length
+    val_str = format(val, "#06x")
+    # additional prefix
+    prefix_str = format(i, "#06x")
+    # cutting '0x' prefix away
+    f.write(prefix_str[2:] + "_" + val_str[2:] + "\n")
+
+f.close()
+